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authorDimitry Andric <dim@FreeBSD.org>2023-07-26 19:03:47 +0000
committerDimitry Andric <dim@FreeBSD.org>2023-07-26 19:04:23 +0000
commit7fa27ce4a07f19b07799a767fc29416f3b625afb (patch)
tree27825c83636c4de341eb09a74f49f5d38a15d165 /llvm/lib/Target/Mips
parente3b557809604d036af6e00c60f012c2025b59a5e (diff)
vendor/llvm-project/llvmorg-17-init-19304-gd0b54bb50e51
Diffstat (limited to 'llvm/lib/Target/Mips')
-rw-r--r--llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp329
-rw-r--r--llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp20
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp2
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h2
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h2
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp2
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp4
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp2
-rw-r--r--llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp4
-rw-r--r--llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td1
-rw-r--r--llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp8
-rw-r--r--llvm/lib/Target/Mips/Mips16InstrInfo.cpp10
-rw-r--r--llvm/lib/Target/Mips/MipsAnalyzeImmediate.cpp2
-rw-r--r--llvm/lib/Target/Mips/MipsAsmPrinter.cpp12
-rw-r--r--llvm/lib/Target/Mips/MipsCallLowering.cpp10
-rw-r--r--llvm/lib/Target/Mips/MipsCombine.td6
-rw-r--r--llvm/lib/Target/Mips/MipsDSPInstrInfo.td2
-rw-r--r--llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp3
-rw-r--r--llvm/lib/Target/Mips/MipsFastISel.cpp6
-rw-r--r--llvm/lib/Target/Mips/MipsISelLowering.cpp112
-rw-r--r--llvm/lib/Target/Mips/MipsISelLowering.h4
-rw-r--r--llvm/lib/Target/Mips/MipsInstructionSelector.cpp2
-rw-r--r--llvm/lib/Target/Mips/MipsLegalizerInfo.cpp2
-rw-r--r--llvm/lib/Target/Mips/MipsOptimizePICCall.cpp2
-rw-r--r--llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp71
-rw-r--r--llvm/lib/Target/Mips/MipsRegisterInfo.cpp5
-rw-r--r--llvm/lib/Target/Mips/MipsRegisterInfo.h4
-rw-r--r--llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp14
-rw-r--r--llvm/lib/Target/Mips/MipsSEISelLowering.cpp17
-rw-r--r--llvm/lib/Target/Mips/MipsSEISelLowering.h2
-rw-r--r--llvm/lib/Target/Mips/MipsSEInstrInfo.cpp34
-rw-r--r--llvm/lib/Target/Mips/MipsSubtarget.cpp3
32 files changed, 342 insertions, 357 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 45cbddd03d92..b4f99788410b 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -18,7 +18,6 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
-#include "llvm/ADT/Triple.h"
#include "llvm/ADT/Twine.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/MC/MCContext.h"
@@ -39,7 +38,6 @@
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/MCSymbolELF.h"
#include "llvm/MC/MCValue.h"
-#include "llvm/MC/SubtargetFeature.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Alignment.h"
#include "llvm/Support/Casting.h"
@@ -51,6 +49,8 @@
#include "llvm/Support/SMLoc.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/TargetParser/SubtargetFeature.h"
+#include "llvm/TargetParser/Triple.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
@@ -195,20 +195,17 @@ class MipsAsmParser : public MCTargetAsmParser {
bool ParseDirective(AsmToken DirectiveID) override;
- OperandMatchResultTy parseMemOperand(OperandVector &Operands);
- OperandMatchResultTy
- matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
- StringRef Identifier, SMLoc S);
- OperandMatchResultTy matchAnyRegisterWithoutDollar(OperandVector &Operands,
- const AsmToken &Token,
- SMLoc S);
- OperandMatchResultTy matchAnyRegisterWithoutDollar(OperandVector &Operands,
- SMLoc S);
- OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
- OperandMatchResultTy parseImm(OperandVector &Operands);
- OperandMatchResultTy parseJumpTarget(OperandVector &Operands);
- OperandMatchResultTy parseInvNum(OperandVector &Operands);
- OperandMatchResultTy parseRegisterList(OperandVector &Operands);
+ ParseStatus parseMemOperand(OperandVector &Operands);
+ ParseStatus matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
+ StringRef Identifier, SMLoc S);
+ ParseStatus matchAnyRegisterWithoutDollar(OperandVector &Operands,
+ const AsmToken &Token, SMLoc S);
+ ParseStatus matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S);
+ ParseStatus parseAnyRegister(OperandVector &Operands);
+ ParseStatus parseImm(OperandVector &Operands);
+ ParseStatus parseJumpTarget(OperandVector &Operands);
+ ParseStatus parseInvNum(OperandVector &Operands);
+ ParseStatus parseRegisterList(OperandVector &Operands);
bool searchSymbolAlias(OperandVector &Operands);
@@ -482,7 +479,7 @@ class MipsAsmParser : public MCTargetAsmParser {
}
void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
- if (!(getSTI().getFeatureBits()[Feature])) {
+ if (!(getSTI().hasFeature(Feature))) {
MCSubtargetInfo &STI = copySTI();
setAvailableFeatures(
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
@@ -491,7 +488,7 @@ class MipsAsmParser : public MCTargetAsmParser {
}
void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
- if (getSTI().getFeatureBits()[Feature]) {
+ if (getSTI().hasFeature(Feature)) {
MCSubtargetInfo &STI = copySTI();
setAvailableFeatures(
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
@@ -576,11 +573,11 @@ public:
bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
bool isGP64bit() const {
- return getSTI().getFeatureBits()[Mips::FeatureGP64Bit];
+ return getSTI().hasFeature(Mips::FeatureGP64Bit);
}
bool isFP64bit() const {
- return getSTI().getFeatureBits()[Mips::FeatureFP64Bit];
+ return getSTI().hasFeature(Mips::FeatureFP64Bit);
}
bool isJalrRelocAvailable(const MCExpr *JalExpr) {
@@ -601,99 +598,99 @@ public:
bool isABI_N64() const { return ABI.IsN64(); }
bool isABI_O32() const { return ABI.IsO32(); }
bool isABI_FPXX() const {
- return getSTI().getFeatureBits()[Mips::FeatureFPXX];
+ return getSTI().hasFeature(Mips::FeatureFPXX);
}
bool useOddSPReg() const {
- return !(getSTI().getFeatureBits()[Mips::FeatureNoOddSPReg]);
+ return !(getSTI().hasFeature(Mips::FeatureNoOddSPReg));
}
bool inMicroMipsMode() const {
- return getSTI().getFeatureBits()[Mips::FeatureMicroMips];
+ return getSTI().hasFeature(Mips::FeatureMicroMips);
}
bool hasMips1() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips1];
+ return getSTI().hasFeature(Mips::FeatureMips1);
}
bool hasMips2() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips2];
+ return getSTI().hasFeature(Mips::FeatureMips2);
}
bool hasMips3() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips3];
+ return getSTI().hasFeature(Mips::FeatureMips3);
}
bool hasMips4() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips4];
+ return getSTI().hasFeature(Mips::FeatureMips4);
}
bool hasMips5() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips5];
+ return getSTI().hasFeature(Mips::FeatureMips5);
}
bool hasMips32() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips32];
+ return getSTI().hasFeature(Mips::FeatureMips32);
}
bool hasMips64() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips64];
+ return getSTI().hasFeature(Mips::FeatureMips64);
}
bool hasMips32r2() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips32r2];
+ return getSTI().hasFeature(Mips::FeatureMips32r2);
}
bool hasMips64r2() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips64r2];
+ return getSTI().hasFeature(Mips::FeatureMips64r2);
}
bool hasMips32r3() const {
- return (getSTI().getFeatureBits()[Mips::FeatureMips32r3]);
+ return (getSTI().hasFeature(Mips::FeatureMips32r3));
}
bool hasMips64r3() const {
- return (getSTI().getFeatureBits()[Mips::FeatureMips64r3]);
+ return (getSTI().hasFeature(Mips::FeatureMips64r3));
}
bool hasMips32r5() const {
- return (getSTI().getFeatureBits()[Mips::FeatureMips32r5]);
+ return (getSTI().hasFeature(Mips::FeatureMips32r5));
}
bool hasMips64r5() const {
- return (getSTI().getFeatureBits()[Mips::FeatureMips64r5]);
+ return (getSTI().hasFeature(Mips::FeatureMips64r5));
}
bool hasMips32r6() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips32r6];
+ return getSTI().hasFeature(Mips::FeatureMips32r6);
}
bool hasMips64r6() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips64r6];
+ return getSTI().hasFeature(Mips::FeatureMips64r6);
}
bool hasDSP() const {
- return getSTI().getFeatureBits()[Mips::FeatureDSP];
+ return getSTI().hasFeature(Mips::FeatureDSP);
}
bool hasDSPR2() const {
- return getSTI().getFeatureBits()[Mips::FeatureDSPR2];
+ return getSTI().hasFeature(Mips::FeatureDSPR2);
}
bool hasDSPR3() const {
- return getSTI().getFeatureBits()[Mips::FeatureDSPR3];
+ return getSTI().hasFeature(Mips::FeatureDSPR3);
}
bool hasMSA() const {
- return getSTI().getFeatureBits()[Mips::FeatureMSA];
+ return getSTI().hasFeature(Mips::FeatureMSA);
}
bool hasCnMips() const {
- return (getSTI().getFeatureBits()[Mips::FeatureCnMips]);
+ return (getSTI().hasFeature(Mips::FeatureCnMips));
}
bool hasCnMipsP() const {
- return (getSTI().getFeatureBits()[Mips::FeatureCnMipsP]);
+ return (getSTI().hasFeature(Mips::FeatureCnMipsP));
}
bool inPicMode() {
@@ -701,30 +698,30 @@ public:
}
bool inMips16Mode() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips16];
+ return getSTI().hasFeature(Mips::FeatureMips16);
}
bool useTraps() const {
- return getSTI().getFeatureBits()[Mips::FeatureUseTCCInDIV];
+ return getSTI().hasFeature(Mips::FeatureUseTCCInDIV);
}
bool useSoftFloat() const {
- return getSTI().getFeatureBits()[Mips::FeatureSoftFloat];
+ return getSTI().hasFeature(Mips::FeatureSoftFloat);
}
bool hasMT() const {
- return getSTI().getFeatureBits()[Mips::FeatureMT];
+ return getSTI().hasFeature(Mips::FeatureMT);
}
bool hasCRC() const {
- return getSTI().getFeatureBits()[Mips::FeatureCRC];
+ return getSTI().hasFeature(Mips::FeatureCRC);
}
bool hasVirt() const {
- return getSTI().getFeatureBits()[Mips::FeatureVirt];
+ return getSTI().hasFeature(Mips::FeatureVirt);
}
bool hasGINV() const {
- return getSTI().getFeatureBits()[Mips::FeatureGINV];
+ return getSTI().hasFeature(Mips::FeatureGINV);
}
/// Warn if RegIndex is the same as the current AT.
@@ -2671,9 +2668,7 @@ bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc,
/// Can the value be represented by a unsigned N-bit value and a shift left?
template <unsigned N> static bool isShiftedUIntAtAnyPosition(uint64_t x) {
- unsigned BitNum = findFirstSet(x);
-
- return (x == x >> BitNum << BitNum) && isUInt<N>(x >> BitNum);
+ return x && isUInt<N>(x >> llvm::countr_zero(x));
}
/// Load (or add) an immediate into a register.
@@ -2798,11 +2793,14 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
return true;
}
+ // We've processed ImmValue satisfying isUInt<16> above, so ImmValue must be
+ // at least 17-bit wide here.
+ unsigned BitWidth = llvm::bit_width((uint64_t)ImmValue);
+ assert(BitWidth >= 17 && "ImmValue must be at least 17-bit wide");
+
// Traditionally, these immediates are shifted as little as possible and as
// such we align the most significant bit to bit 15 of our temporary.
- unsigned FirstSet = findFirstSet((uint64_t)ImmValue);
- unsigned LastSet = findLastSet((uint64_t)ImmValue);
- unsigned ShiftAmount = FirstSet - (15 - (LastSet - FirstSet));
+ unsigned ShiftAmount = BitWidth - 16;
uint16_t Bits = (ImmValue >> ShiftAmount) & 0xffff;
TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI);
TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI);
@@ -2923,7 +2921,7 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
(Res.getSymA()->getSymbol().isELF() &&
cast<MCSymbolELF>(Res.getSymA()->getSymbol()).getBinding() ==
ELF::STB_LOCAL);
- bool UseXGOT = STI->getFeatureBits()[Mips::FeatureXGOT] && !IsLocalSym;
+ bool UseXGOT = STI->hasFeature(Mips::FeatureXGOT) && !IsLocalSym;
// The case where the result register is $25 is somewhat special. If the
// symbol in the final relocation is external and not modified with a
@@ -3086,6 +3084,7 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, SymExpr, getContext());
bool RdRegIsRsReg =
+ UseSrcReg &&
getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg);
if (canUseATReg() && UseSrcReg && RdRegIsRsReg) {
@@ -3341,9 +3340,9 @@ static uint64_t convertIntToDoubleImm(uint64_t ImmOp64) {
static uint32_t covertDoubleImmToSingleImm(uint64_t ImmOp64) {
// Conversion of a double in an uint64_t to a float in a uint32_t,
// retaining the bit pattern of a float.
- double DoubleImm = BitsToDouble(ImmOp64);
+ double DoubleImm = llvm::bit_cast<double>(ImmOp64);
float TmpFloat = static_cast<float>(DoubleImm);
- return FloatToBits(TmpFloat);
+ return llvm::bit_cast<uint32_t>(TmpFloat);
}
bool MipsAsmParser::expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc,
@@ -6331,13 +6330,13 @@ bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
// Check if the current operand has a custom associated parser, if so, try to
// custom parse the operand, or fallback to the general approach.
- OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
- if (ResTy == MatchOperand_Success)
+ ParseStatus Res = MatchOperandParserImpl(Operands, Mnemonic);
+ if (Res.isSuccess())
return false;
// If there wasn't a custom match, try the generic matcher below. Otherwise,
// there was a match, but an error occurred, in which case, just return that
// the operand parsing failed.
- if (ResTy == MatchOperand_ParseFail)
+ if (Res.isFailure())
return true;
LLVM_DEBUG(dbgs() << ".. Generic Parser\n");
@@ -6352,7 +6351,7 @@ bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
// for div, divu, and similar instructions because it is not an operand
// to the instruction definition but an explicit register. Special case
// this situation for now.
- if (parseAnyRegister(Operands) != MatchOperand_NoMatch)
+ if (!parseAnyRegister(Operands).isNoMatch())
return false;
// Maybe it is a symbol reference.
@@ -6363,10 +6362,10 @@ bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
MCSymbol *Sym = getContext().getOrCreateSymbol("$" + Identifier);
// Otherwise create a symbol reference.
- const MCExpr *Res =
+ const MCExpr *SymRef =
MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
- Operands.push_back(MipsOperand::CreateImm(Res, S, E, *this));
+ Operands.push_back(MipsOperand::CreateImm(SymRef, S, E, *this));
return false;
}
default: {
@@ -6395,8 +6394,8 @@ OperandMatchResultTy MipsAsmParser::tryParseRegister(MCRegister &RegNo,
SMLoc &StartLoc,
SMLoc &EndLoc) {
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
- OperandMatchResultTy ResTy = parseAnyRegister(Operands);
- if (ResTy == MatchOperand_Success) {
+ ParseStatus Res = parseAnyRegister(Operands);
+ if (Res.isSuccess()) {
assert(Operands.size() == 1);
MipsOperand &Operand = static_cast<MipsOperand &>(*Operands.front());
StartLoc = Operand.getStartLoc();
@@ -6427,14 +6426,13 @@ bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
return getParser().parseExpression(Res);
}
-OperandMatchResultTy
-MipsAsmParser::parseMemOperand(OperandVector &Operands) {
+ParseStatus MipsAsmParser::parseMemOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
LLVM_DEBUG(dbgs() << "parseMemOperand\n");
const MCExpr *IdVal = nullptr;
SMLoc S;
bool isParenExpr = false;
- OperandMatchResultTy Res = MatchOperand_NoMatch;
+ ParseStatus Res = ParseStatus::NoMatch;
// First operand is the offset.
S = Parser.getTok().getLoc();
@@ -6445,7 +6443,7 @@ MipsAsmParser::parseMemOperand(OperandVector &Operands) {
if (getLexer().getKind() != AsmToken::Dollar) {
if (parseMemOffset(IdVal, isParenExpr))
- return MatchOperand_ParseFail;
+ return ParseStatus::Failure;
const AsmToken &Tok = Parser.getTok(); // Get the next token.
if (Tok.isNot(AsmToken::LParen)) {
@@ -6454,7 +6452,7 @@ MipsAsmParser::parseMemOperand(OperandVector &Operands) {
SMLoc E =
SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
if (Tok.is(AsmToken::EndOfStatement)) {
SMLoc E =
@@ -6466,7 +6464,7 @@ MipsAsmParser::parseMemOperand(OperandVector &Operands) {
0, "0", getContext().getRegisterInfo(), S, E, *this);
Operands.push_back(
MipsOperand::CreateMem(std::move(Base), IdVal, S, E, *this));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
MCBinaryExpr::Opcode Opcode;
// GAS and LLVM treat comparison operators different. GAS will generate -1
@@ -6515,12 +6513,11 @@ MipsAsmParser::parseMemOperand(OperandVector &Operands) {
Parser.Lex();
break;
default:
- Error(Parser.getTok().getLoc(), "'(' or expression expected");
- return MatchOperand_ParseFail;
+ return Error(Parser.getTok().getLoc(), "'(' or expression expected");
}
const MCExpr * NextExpr;
if (getParser().parseExpression(NextExpr))
- return MatchOperand_ParseFail;
+ return ParseStatus::Failure;
IdVal = MCBinaryExpr::create(Opcode, IdVal, NextExpr, getContext());
}
@@ -6528,13 +6525,11 @@ MipsAsmParser::parseMemOperand(OperandVector &Operands) {
}
Res = parseAnyRegister(Operands);
- if (Res != MatchOperand_Success)
+ if (!Res.isSuccess())
return Res;
- if (Parser.getTok().isNot(AsmToken::RParen)) {
- Error(Parser.getTok().getLoc(), "')' expected");
- return MatchOperand_ParseFail;
- }
+ if (Parser.getTok().isNot(AsmToken::RParen))
+ return Error(Parser.getTok().getLoc(), "')' expected");
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
@@ -6560,7 +6555,7 @@ MipsAsmParser::parseMemOperand(OperandVector &Operands) {
}
Operands.push_back(MipsOperand::CreateMem(std::move(op), IdVal, S, E, *this));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) {
@@ -6576,14 +6571,14 @@ bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) {
const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
StringRef DefSymbol = Ref->getSymbol().getName();
if (DefSymbol.startswith("$")) {
- OperandMatchResultTy ResTy =
+ ParseStatus Res =
matchAnyRegisterNameWithoutDollar(Operands, DefSymbol.substr(1), S);
- if (ResTy == MatchOperand_Success) {
+ if (Res.isSuccess()) {
Parser.Lex();
return true;
}
- if (ResTy == MatchOperand_ParseFail)
- llvm_unreachable("Should never ParseFail");
+ if (Res.isFailure())
+ llvm_unreachable("Should never fail");
}
}
} else if (Sym->isUnset()) {
@@ -6592,9 +6587,9 @@ bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) {
// Lookup in the aliases list.
auto Entry = RegisterSets.find(Sym->getName());
if (Entry != RegisterSets.end()) {
- OperandMatchResultTy ResTy =
+ ParseStatus Res =
matchAnyRegisterWithoutDollar(Operands, Entry->getValue(), S);
- if (ResTy == MatchOperand_Success) {
+ if (Res.isSuccess()) {
Parser.Lex();
return true;
}
@@ -6604,16 +6599,14 @@ bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) {
return false;
}
-OperandMatchResultTy
-MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
- StringRef Identifier,
- SMLoc S) {
+ParseStatus MipsAsmParser::matchAnyRegisterNameWithoutDollar(
+ OperandVector &Operands, StringRef Identifier, SMLoc S) {
int Index = matchCPURegisterName(Identifier);
if (Index != -1) {
Operands.push_back(MipsOperand::createGPRReg(
Index, Identifier, getContext().getRegisterInfo(), S,
getLexer().getLoc(), *this));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
Index = matchHWRegsRegisterName(Identifier);
@@ -6621,7 +6614,7 @@ MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
Operands.push_back(MipsOperand::createHWRegsReg(
Index, Identifier, getContext().getRegisterInfo(), S,
getLexer().getLoc(), *this));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
Index = matchFPURegisterName(Identifier);
@@ -6629,7 +6622,7 @@ MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
Operands.push_back(MipsOperand::createFGRReg(
Index, Identifier, getContext().getRegisterInfo(), S,
getLexer().getLoc(), *this));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
Index = matchFCCRegisterName(Identifier);
@@ -6637,7 +6630,7 @@ MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
Operands.push_back(MipsOperand::createFCCReg(
Index, Identifier, getContext().getRegisterInfo(), S,
getLexer().getLoc(), *this));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
Index = matchACRegisterName(Identifier);
@@ -6645,7 +6638,7 @@ MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
Operands.push_back(MipsOperand::createACCReg(
Index, Identifier, getContext().getRegisterInfo(), S,
getLexer().getLoc(), *this));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
Index = matchMSA128RegisterName(Identifier);
@@ -6653,7 +6646,7 @@ MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
Operands.push_back(MipsOperand::createMSA128Reg(
Index, Identifier, getContext().getRegisterInfo(), S,
getLexer().getLoc(), *this));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
Index = matchMSA128CtrlRegisterName(Identifier);
@@ -6661,22 +6654,21 @@ MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
Operands.push_back(MipsOperand::createMSACtrlReg(
Index, Identifier, getContext().getRegisterInfo(), S,
getLexer().getLoc(), *this));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
}
-OperandMatchResultTy
+ParseStatus
MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands,
const AsmToken &Token, SMLoc S) {
if (Token.is(AsmToken::Identifier)) {
LLVM_DEBUG(dbgs() << ".. identifier\n");
StringRef Identifier = Token.getIdentifier();
- OperandMatchResultTy ResTy =
- matchAnyRegisterNameWithoutDollar(Operands, Identifier, S);
- return ResTy;
- } else if (Token.is(AsmToken::Integer)) {
+ return matchAnyRegisterNameWithoutDollar(Operands, Identifier, S);
+ }
+ if (Token.is(AsmToken::Integer)) {
LLVM_DEBUG(dbgs() << ".. integer\n");
int64_t RegNum = Token.getIntVal();
if (RegNum < 0 || RegNum > 31) {
@@ -6688,22 +6680,21 @@ MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands,
Operands.push_back(MipsOperand::createNumericReg(
RegNum, Token.getString(), getContext().getRegisterInfo(), S,
Token.getLoc(), *this));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
LLVM_DEBUG(dbgs() << Token.getKind() << "\n");
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
}
-OperandMatchResultTy
+ParseStatus
MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) {
auto Token = getLexer().peekTok(false);
return matchAnyRegisterWithoutDollar(Operands, Token, S);
}
-OperandMatchResultTy
-MipsAsmParser::parseAnyRegister(OperandVector &Operands) {
+ParseStatus MipsAsmParser::parseAnyRegister(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
LLVM_DEBUG(dbgs() << "parseAnyRegister\n");
@@ -6715,46 +6706,44 @@ MipsAsmParser::parseAnyRegister(OperandVector &Operands) {
LLVM_DEBUG(dbgs() << ".. !$ -> try sym aliasing\n");
if (Token.is(AsmToken::Identifier)) {
if (searchSymbolAlias(Operands))
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
LLVM_DEBUG(dbgs() << ".. !symalias -> NoMatch\n");
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
}
LLVM_DEBUG(dbgs() << ".. $\n");
- OperandMatchResultTy ResTy = matchAnyRegisterWithoutDollar(Operands, S);
- if (ResTy == MatchOperand_Success) {
+ ParseStatus Res = matchAnyRegisterWithoutDollar(Operands, S);
+ if (Res.isSuccess()) {
Parser.Lex(); // $
Parser.Lex(); // identifier
}
- return ResTy;
+ return Res;
}
-OperandMatchResultTy
-MipsAsmParser::parseJumpTarget(OperandVector &Operands) {
+ParseStatus MipsAsmParser::parseJumpTarget(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
LLVM_DEBUG(dbgs() << "parseJumpTarget\n");
SMLoc S = getLexer().getLoc();
// Registers are a valid target and have priority over symbols.
- OperandMatchResultTy ResTy = parseAnyRegister(Operands);
- if (ResTy != MatchOperand_NoMatch)
- return ResTy;
+ ParseStatus Res = parseAnyRegister(Operands);
+ if (!Res.isNoMatch())
+ return Res;
// Integers and expressions are acceptable
const MCExpr *Expr = nullptr;
if (Parser.parseExpression(Expr)) {
// We have no way of knowing if a symbol was consumed so we must ParseFail
- return MatchOperand_ParseFail;
+ return ParseStatus::Failure;
}
Operands.push_back(
MipsOperand::CreateImm(Expr, S, getLexer().getLoc(), *this));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
-OperandMatchResultTy
-MipsAsmParser::parseInvNum(OperandVector &Operands) {
+ParseStatus MipsAsmParser::parseInvNum(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
const MCExpr *IdVal;
// If the first token is '$' we may have register operand. We have to reject
@@ -6764,23 +6753,22 @@ MipsAsmParser::parseInvNum(OperandVector &Operands) {
SMLoc S = Parser.getTok().getLoc();
if (Parser.getTok().is(AsmToken::Dollar)) {
return matchCPURegisterName(Parser.getLexer().peekTok().getString()) == -1
- ? MatchOperand_ParseFail
- : MatchOperand_NoMatch;
+ ? ParseStatus::Failure
+ : ParseStatus::NoMatch;
}
if (getParser().parseExpression(IdVal))
- return MatchOperand_ParseFail;
+ return ParseStatus::Failure;
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
if (!MCE)
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
int64_t Val = MCE->getValue();
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
Operands.push_back(MipsOperand::CreateImm(
MCConstantExpr::create(0 - Val, getContext()), S, E, *this));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
-OperandMatchResultTy
-MipsAsmParser::parseRegisterList(OperandVector &Operands) {
+ParseStatus MipsAsmParser::parseRegisterList(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SmallVector<unsigned, 10> Regs;
unsigned RegNo;
@@ -6789,10 +6777,10 @@ MipsAsmParser::parseRegisterList(OperandVector &Operands) {
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> TmpOperands;
if (Parser.getTok().isNot(AsmToken::Dollar))
- return MatchOperand_ParseFail;
+ return ParseStatus::Failure;
SMLoc S = Parser.getTok().getLoc();
- while (parseAnyRegister(TmpOperands) == MatchOperand_Success) {
+ while (parseAnyRegister(TmpOperands).isSuccess()) {
SMLoc E = getLexer().getLoc();
MipsOperand &Reg = static_cast<MipsOperand &>(*TmpOperands.back());
RegNo = isGP64bit() ? Reg.getGPR64Reg() : Reg.getGPR32Reg();
@@ -6807,10 +6795,8 @@ MipsAsmParser::parseRegisterList(OperandVector &Operands) {
while (TmpReg <= RegNo) {
if ((((TmpReg < Mips::S0) || (TmpReg > Mips::S7)) && !isGP64bit()) ||
(((TmpReg < Mips::S0_64) || (TmpReg > Mips::S7_64)) &&
- isGP64bit())) {
- Error(E, "invalid register operand");
- return MatchOperand_ParseFail;
- }
+ isGP64bit()))
+ return Error(E, "invalid register operand");
PrevReg = TmpReg;
Regs.push_back(TmpReg++);
@@ -6821,24 +6807,19 @@ MipsAsmParser::parseRegisterList(OperandVector &Operands) {
} else {
if ((PrevReg == Mips::NoRegister) &&
((isGP64bit() && (RegNo != Mips::S0_64) && (RegNo != Mips::RA_64)) ||
- (!isGP64bit() && (RegNo != Mips::S0) && (RegNo != Mips::RA)))) {
- Error(E, "$16 or $31 expected");
- return MatchOperand_ParseFail;
- } else if (!(((RegNo == Mips::FP || RegNo == Mips::RA ||
- (RegNo >= Mips::S0 && RegNo <= Mips::S7)) &&
- !isGP64bit()) ||
- ((RegNo == Mips::FP_64 || RegNo == Mips::RA_64 ||
- (RegNo >= Mips::S0_64 && RegNo <= Mips::S7_64)) &&
- isGP64bit()))) {
- Error(E, "invalid register operand");
- return MatchOperand_ParseFail;
- } else if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) &&
- ((RegNo != Mips::FP && RegNo != Mips::RA && !isGP64bit()) ||
- (RegNo != Mips::FP_64 && RegNo != Mips::RA_64 &&
- isGP64bit()))) {
- Error(E, "consecutive register numbers expected");
- return MatchOperand_ParseFail;
- }
+ (!isGP64bit() && (RegNo != Mips::S0) && (RegNo != Mips::RA))))
+ return Error(E, "$16 or $31 expected");
+ if (!(((RegNo == Mips::FP || RegNo == Mips::RA ||
+ (RegNo >= Mips::S0 && RegNo <= Mips::S7)) &&
+ !isGP64bit()) ||
+ ((RegNo == Mips::FP_64 || RegNo == Mips::RA_64 ||
+ (RegNo >= Mips::S0_64 && RegNo <= Mips::S7_64)) &&
+ isGP64bit())))
+ return Error(E, "invalid register operand");
+ if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) &&
+ ((RegNo != Mips::FP && RegNo != Mips::RA && !isGP64bit()) ||
+ (RegNo != Mips::FP_64 && RegNo != Mips::RA_64 && isGP64bit())))
+ return Error(E, "consecutive register numbers expected");
Regs.push_back(RegNo);
}
@@ -6847,10 +6828,8 @@ MipsAsmParser::parseRegisterList(OperandVector &Operands) {
RegRange = true;
if (!Parser.getTok().isNot(AsmToken::Minus) &&
- !Parser.getTok().isNot(AsmToken::Comma)) {
- Error(E, "',' or '-' expected");
- return MatchOperand_ParseFail;
- }
+ !Parser.getTok().isNot(AsmToken::Comma))
+ return Error(E, "',' or '-' expected");
Lex(); // Consume comma or minus
if (Parser.getTok().isNot(AsmToken::Dollar))
@@ -6862,7 +6841,7 @@ MipsAsmParser::parseRegisterList(OperandVector &Operands) {
SMLoc E = Parser.getTok().getLoc();
Operands.push_back(MipsOperand::CreateRegList(Regs, S, E, *this));
parseMemOperand(Operands);
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
/// Sometimes (i.e. load/stores) the operand may be followed immediately by
@@ -7642,8 +7621,8 @@ bool MipsAsmParser::isPicAndNotNxxAbi() {
bool MipsAsmParser::parseDirectiveCpAdd(SMLoc Loc) {
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Reg;
- OperandMatchResultTy ResTy = parseAnyRegister(Reg);
- if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) {
+ ParseStatus Res = parseAnyRegister(Reg);
+ if (Res.isNoMatch() || Res.isFailure()) {
reportParseError("expected register");
return false;
}
@@ -7675,8 +7654,8 @@ bool MipsAsmParser::parseDirectiveCpLoad(SMLoc Loc) {
}
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Reg;
- OperandMatchResultTy ResTy = parseAnyRegister(Reg);
- if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) {
+ ParseStatus Res = parseAnyRegister(Reg);
+ if (Res.isNoMatch() || Res.isFailure()) {
reportParseError("expected register containing function address");
return false;
}
@@ -7704,8 +7683,8 @@ bool MipsAsmParser::parseDirectiveCpLocal(SMLoc Loc) {
}
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Reg;
- OperandMatchResultTy ResTy = parseAnyRegister(Reg);
- if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) {
+ ParseStatus Res = parseAnyRegister(Reg);
+ if (Res.isNoMatch() || Res.isFailure()) {
reportParseError("expected register containing global pointer");
return false;
}
@@ -7783,8 +7762,8 @@ bool MipsAsmParser::parseDirectiveCPSetup() {
bool SaveIsReg = true;
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg;
- OperandMatchResultTy ResTy = parseAnyRegister(TmpReg);
- if (ResTy == MatchOperand_NoMatch) {
+ ParseStatus Res = parseAnyRegister(TmpReg);
+ if (Res.isNoMatch()) {
reportParseError("expected register containing function address");
return false;
}
@@ -7801,8 +7780,8 @@ bool MipsAsmParser::parseDirectiveCPSetup() {
if (!eatComma("unexpected token, expected comma"))
return true;
- ResTy = parseAnyRegister(TmpReg);
- if (ResTy == MatchOperand_NoMatch) {
+ Res = parseAnyRegister(TmpReg);
+ if (Res.isNoMatch()) {
const MCExpr *OffsetExpr;
int64_t OffsetVal;
SMLoc ExprLoc = getLexer().getLoc();
@@ -8675,8 +8654,8 @@ bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
if (IDVal == ".frame") {
// .frame $stack_reg, frame_size_in_bytes, $return_reg
SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg;
- OperandMatchResultTy ResTy = parseAnyRegister(TmpReg);
- if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) {
+ ParseStatus Res = parseAnyRegister(TmpReg);
+ if (Res.isNoMatch() || Res.isFailure()) {
reportParseError("expected stack register");
return false;
}
@@ -8719,8 +8698,8 @@ bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
// Parse the return register.
TmpReg.clear();
- ResTy = parseAnyRegister(TmpReg);
- if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) {
+ Res = parseAnyRegister(TmpReg);
+ if (Res.isNoMatch() || Res.isFailure()) {
reportParseError("expected return register");
return false;
}
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index fb92590350c7..cda288a25aed 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -44,26 +44,26 @@ class MipsDisassembler : public MCDisassembler {
public:
MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
: MCDisassembler(STI, Ctx),
- IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
+ IsMicroMips(STI.hasFeature(Mips::FeatureMicroMips)),
IsBigEndian(IsBigEndian) {}
- bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
- bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
- bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
+ bool hasMips2() const { return STI.hasFeature(Mips::FeatureMips2); }
+ bool hasMips3() const { return STI.hasFeature(Mips::FeatureMips3); }
+ bool hasMips32() const { return STI.hasFeature(Mips::FeatureMips32); }
bool hasMips32r6() const {
- return STI.getFeatureBits()[Mips::FeatureMips32r6];
+ return STI.hasFeature(Mips::FeatureMips32r6);
}
- bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
+ bool isFP64() const { return STI.hasFeature(Mips::FeatureFP64Bit); }
- bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
+ bool isGP64() const { return STI.hasFeature(Mips::FeatureGP64Bit); }
- bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; }
+ bool isPTR64() const { return STI.hasFeature(Mips::FeaturePTR64Bit); }
- bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
+ bool hasCnMips() const { return STI.hasFeature(Mips::FeatureCnMips); }
- bool hasCnMipsP() const { return STI.getFeatureBits()[Mips::FeatureCnMipsP]; }
+ bool hasCnMipsP() const { return STI.hasFeature(Mips::FeatureCnMipsP); }
bool hasCOP3() const {
// Only present in MIPS-I and MIPS-II
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
index 933077beb0c2..3e0d51ef887c 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
@@ -9,10 +9,10 @@
#include "MipsABIInfo.h"
#include "MipsRegisterInfo.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/LowLevelType.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/MC/MCTargetOptions.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/LowLevelTypeImpl.h"
using namespace llvm;
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
index 046cc686b311..41f80771142d 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
@@ -9,9 +9,9 @@
#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIINFO_H
#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIINFO_H
-#include "llvm/ADT/Triple.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/TargetParser/Triple.h"
namespace llvm {
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
index 1172a06a3e08..749223a6d01b 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h
@@ -15,8 +15,8 @@
#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H
#include "MCTargetDesc/MipsFixupKinds.h"
-#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCAsmBackend.h"
+#include "llvm/TargetParser/Triple.h"
namespace llvm {
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
index 9c85a39bc348..f89c78e75d3e 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
@@ -12,7 +12,7 @@
#include "MipsMCAsmInfo.h"
#include "MipsABIInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/TargetParser/Triple.h"
using namespace llvm;
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index 781f1097176d..1c7440dfbe91 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -116,11 +116,11 @@ void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
}
bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
- return STI.getFeatureBits()[Mips::FeatureMicroMips];
+ return STI.hasFeature(Mips::FeatureMicroMips);
}
bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
- return STI.getFeatureBits()[Mips::FeatureMips32r6];
+ return STI.hasFeature(Mips::FeatureMips32r6);
}
void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
index 273dcdb0b429..d38b89f9a1f2 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
@@ -19,7 +19,6 @@
#include "MipsMCNaCl.h"
#include "MipsTargetStreamer.h"
#include "TargetInfo/MipsTargetInfo.h"
-#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCELFStreamer.h"
#include "llvm/MC/MCInstrAnalysis.h"
@@ -32,6 +31,7 @@
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/FormattedStream.h"
+#include "llvm/TargetParser/Triple.h"
using namespace llvm;
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
index 9893c6055f81..d0aa14a1b724 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
@@ -37,11 +37,11 @@ static cl::opt<bool> RoundSectionSizes(
} // end anonymous namespace
static bool isMicroMips(const MCSubtargetInfo *STI) {
- return STI->getFeatureBits()[Mips::FeatureMicroMips];
+ return STI->hasFeature(Mips::FeatureMicroMips);
}
static bool isMips32r6(const MCSubtargetInfo *STI) {
- return STI->getFeatureBits()[Mips::FeatureMips32r6];
+ return STI->hasFeature(Mips::FeatureMips32r6);
}
MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
diff --git a/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
index 8950de230a01..f7d0105f4d7d 100644
--- a/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
@@ -374,7 +374,6 @@ class WRDSP_MM_DESC {
string AsmString = !strconcat("wrdsp", "\t$rt, $mask");
list<dag> Pattern = [(int_mips_wrdsp GPR32Opnd:$rt, timmZExt7:$mask)];
InstrItinClass Itinerary = NoItinerary;
- bit isMoveReg = 1;
}
class BPOSGE32C_MMR3_DESC {
diff --git a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
index ce04124a7b00..c8c9612b75e7 100644
--- a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
@@ -47,16 +47,16 @@ Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, const SDLoc &DL, EVT Ty,
SDNode *Lo = nullptr, *Hi = nullptr;
SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
N->getOperand(1));
- SDValue InFlag = SDValue(Mul, 0);
+ SDValue InGlue = SDValue(Mul, 0);
if (HasLo) {
unsigned Opcode = Mips::Mflo16;
- Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
- InFlag = SDValue(Lo, 1);
+ Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InGlue);
+ InGlue = SDValue(Lo, 1);
}
if (HasHi) {
unsigned Opcode = Mips::Mfhi16;
- Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
+ Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InGlue);
}
return std::make_pair(Lo, Hi);
}
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
index bb527dca6b6d..20185e83286d 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
@@ -340,8 +340,8 @@ unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
int Reg =0;
int SpReg = 0;
- rs.enterBasicBlock(MBB);
- rs.forward(II);
+ rs.enterBasicBlockEnd(MBB);
+ rs.backward(II);
//
// We need to know which registers can be used, in the case where there
// are not enough free registers. We exclude all registers that
@@ -351,8 +351,7 @@ unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
RI.getAllocatableSet
(*II->getParent()->getParent(), &Mips::CPU16RegsRegClass);
// Exclude all the registers being used by the instruction.
- for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = II->getOperand(i);
+ for (MachineOperand &MO : II->operands()) {
if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
!MO.getReg().isVirtual())
Candidates.reset(MO.getReg());
@@ -367,8 +366,7 @@ unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
// whether the register is live before the instruction. if it's not
// then we don't need to save it in case there are no free registers.
int DefReg = 0;
- for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = II->getOperand(i);
+ for (MachineOperand &MO : II->operands()) {
if (MO.isReg() && MO.isDef()) {
DefReg = MO.getReg();
break;
diff --git a/llvm/lib/Target/Mips/MipsAnalyzeImmediate.cpp b/llvm/lib/Target/Mips/MipsAnalyzeImmediate.cpp
index 33da0ff31be8..ea4a25a62a0b 100644
--- a/llvm/lib/Target/Mips/MipsAnalyzeImmediate.cpp
+++ b/llvm/lib/Target/Mips/MipsAnalyzeImmediate.cpp
@@ -43,7 +43,7 @@ void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize,
void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize,
InstSeqLs &SeqLs) {
- unsigned Shamt = countTrailingZeros(Imm);
+ unsigned Shamt = llvm::countr_zero(Imm);
GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs);
AddInstr(SeqLs, Inst(SLL, Shamt));
}
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index dd0b384ff53d..26df40e3b13c 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -26,7 +26,6 @@
#include "TargetInfo/MipsTargetInfo.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringRef.h"
-#include "llvm/ADT/Triple.h"
#include "llvm/ADT/Twine.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
@@ -58,6 +57,7 @@
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
+#include "llvm/TargetParser/Triple.h"
#include <cassert>
#include <cstdint>
#include <map>
@@ -777,14 +777,18 @@ void MipsAsmPrinter::emitStartOfAsmFile(Module &M) {
// around it by re-initializing the PIC state here.
TS.setPic(OutContext.getObjectFileInfo()->isPositionIndependent());
+ // Try to get target-features from the first function.
+ StringRef FS = TM.getTargetFeatureString();
+ Module::iterator F = M.begin();
+ if (FS.empty() && M.size() && F->hasFnAttribute("target-features"))
+ FS = F->getFnAttribute("target-features").getValueAsString();
+
// Compute MIPS architecture attributes based on the default subtarget
- // that we'd have constructed. Module level directives aren't LTO
- // clean anyhow.
+ // that we'd have constructed.
// FIXME: For ifunc related functions we could iterate over and look
// for a feature string that doesn't match the default one.
const Triple &TT = TM.getTargetTriple();
StringRef CPU = MIPS_MC::selectMipsCPU(TT, TM.getTargetCPU());
- StringRef FS = TM.getTargetFeatureString();
const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM, std::nullopt);
diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp
index 044fad6d9e5c..4d6ca5ac2bcc 100644
--- a/llvm/lib/Target/Mips/MipsCallLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp
@@ -412,7 +412,7 @@ bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
int VaArgOffset;
unsigned RegSize = 4;
if (ArgRegs.size() == Idx)
- VaArgOffset = alignTo(CCInfo.getNextStackOffset(), RegSize);
+ VaArgOffset = alignTo(CCInfo.getStackSize(), RegSize);
else {
VaArgOffset =
(int)ABI.GetCalleeAllocdArgSizeInBytes(CCInfo.getCallingConv()) -
@@ -524,14 +524,14 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
if (!handleAssignments(ArgHandler, ArgInfos, CCInfo, ArgLocs, MIRBuilder))
return false;
- unsigned NextStackOffset = CCInfo.getNextStackOffset();
+ unsigned StackSize = CCInfo.getStackSize();
unsigned StackAlignment = F.getParent()->getOverrideStackAlignment();
if (!StackAlignment) {
const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
StackAlignment = TFL->getStackAlignment();
}
- NextStackOffset = alignTo(NextStackOffset, StackAlignment);
- CallSeqStart.addImm(NextStackOffset).addImm(0);
+ StackSize = alignTo(StackSize, StackAlignment);
+ CallSeqStart.addImm(StackSize).addImm(0);
if (IsCalleeGlobalPIC) {
MIRBuilder.buildCopy(
@@ -570,7 +570,7 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
return false;
}
- MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0);
+ MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(StackSize).addImm(0);
return true;
}
diff --git a/llvm/lib/Target/Mips/MipsCombine.td b/llvm/lib/Target/Mips/MipsCombine.td
index 29550a15d38d..cb1594421cc5 100644
--- a/llvm/lib/Target/Mips/MipsCombine.td
+++ b/llvm/lib/Target/Mips/MipsCombine.td
@@ -8,8 +8,6 @@
include "llvm/Target/GlobalISel/Combine.td"
-def MipsPostLegalizerCombinerHelper: GICombinerHelper<
- "MipsGenPostLegalizerCombinerHelper", []> {
- let DisableRuleOption = "mipspostlegalizercombiner-disable-rule";
+def MipsPostLegalizerCombiner: GICombinerHelper<
+ "MipsPostLegalizerCombinerImpl", []> {
}
-
diff --git a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td
index dd0b48573ef6..9498cd015ba3 100644
--- a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td
@@ -452,7 +452,6 @@ class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode timmZExt10:$mask))];
InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
- bit isMoveReg = 1;
}
class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
@@ -463,7 +462,6 @@ class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
list<dag> Pattern = [(OpNode GPR32Opnd:$rs, timmZExt10:$mask)];
InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
- bit isMoveReg = 1;
}
class DPA_W_PH_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
index 94053fa2eb7a..8aa5f769c903 100644
--- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -321,8 +321,7 @@ static void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap) {
/// This function adds registers Filler defines to MBB's live-in register list.
static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) {
- for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) {
- const MachineOperand &MO = Filler->getOperand(I);
+ for (const MachineOperand &MO : Filler->operands()) {
unsigned R;
if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index 7533c1273523..7fcf375aa10b 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -35,6 +35,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/ValueTypes.h"
@@ -63,7 +64,6 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
@@ -1135,7 +1135,7 @@ bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
// Get a count of how many bytes are to be pushed on the stack.
- NumBytes = CCInfo.getNextStackOffset();
+ NumBytes = CCInfo.getStackSize();
// This is the minimum argument area used for A0-A3.
if (NumBytes < 16)
NumBytes = 16;
@@ -1356,7 +1356,7 @@ bool MipsFastISel::fastLowerArguments() {
EVT ArgVT = TLI.getValueType(DL, ArgTy);
LLVM_DEBUG(dbgs() << ".. " << FormalArg.getArgNo() << ": "
- << ArgVT.getEVTString() << "\n");
+ << ArgVT << "\n");
if (!ArgVT.isSimple()) {
LLVM_DEBUG(dbgs() << ".. .. gave up (not a simple type)\n");
return false;
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 5d1fc69b24e8..18d7773067f1 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -40,6 +40,7 @@
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
@@ -63,7 +64,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
@@ -102,29 +102,37 @@ MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
if (!VT.isVector())
return getRegisterType(Context, VT);
- return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32
- : MVT::i64;
+ if (VT.isPow2VectorType() && VT.getVectorElementType().isRound())
+ return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32
+ : MVT::i64;
+ return getRegisterType(Context, VT.getVectorElementType());
}
unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
CallingConv::ID CC,
EVT VT) const {
- if (VT.isVector())
- return divideCeil(VT.getSizeInBits(), Subtarget.isABI_O32() ? 32 : 64);
+ if (VT.isVector()) {
+ if (VT.isPow2VectorType() && VT.getVectorElementType().isRound())
+ return divideCeil(VT.getSizeInBits(), Subtarget.isABI_O32() ? 32 : 64);
+ return VT.getVectorNumElements() *
+ getNumRegisters(Context, VT.getVectorElementType());
+ }
return MipsTargetLowering::getNumRegisters(Context, VT);
}
unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv(
LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
unsigned &NumIntermediates, MVT &RegisterVT) const {
- // Break down vector types to either 2 i64s or 4 i32s.
- RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT);
- IntermediateVT = RegisterVT;
- NumIntermediates =
- VT.getFixedSizeInBits() < RegisterVT.getFixedSizeInBits()
- ? VT.getVectorNumElements()
- : divideCeil(VT.getSizeInBits(), RegisterVT.getSizeInBits());
- return NumIntermediates;
+ if (VT.isPow2VectorType()) {
+ IntermediateVT = getRegisterTypeForCallingConv(Context, CC, VT);
+ RegisterVT = IntermediateVT.getSimpleVT();
+ NumIntermediates = getNumRegistersForCallingConv(Context, CC, VT);
+ return NumIntermediates;
+ }
+ IntermediateVT = VT.getVectorElementType();
+ NumIntermediates = VT.getVectorNumElements();
+ RegisterVT = getRegisterType(Context, IntermediateVT);
+ return NumIntermediates * getNumRegisters(Context, IntermediateVT);
}
SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
@@ -493,6 +501,11 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
setLibcallName(RTLIB::MULO_I128, nullptr);
}
+ if (Subtarget.isGP64bit())
+ setMaxAtomicSizeInBitsSupported(64);
+ else
+ setMaxAtomicSizeInBitsSupported(32);
+
setMinFunctionAlignment(Subtarget.isGP64bit() ? Align(8) : Align(4));
// The arguments on the stack are defined in terms of 4-byte slots on O32
@@ -1015,16 +1028,11 @@ static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG,
// Initialize accumulator.
SDLoc DL(ROOTNode);
- SDValue TopHalf;
- SDValue BottomHalf;
- BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
- CurDAG.getIntPtrConstant(0, DL));
-
- TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
- CurDAG.getIntPtrConstant(1, DL));
- SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
- BottomHalf,
- TopHalf);
+ SDValue BottomHalf, TopHalf;
+ std::tie(BottomHalf, TopHalf) =
+ CurDAG.SplitScalar(AddOperand, DL, MVT::i32, MVT::i32);
+ SDValue ACCIn =
+ CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, BottomHalf, TopHalf);
// Create MipsMAdd(u) / MipsMSub(u) node.
bool IsAdd = ROOTNode->getOpcode() == ISD::ADD;
@@ -3058,13 +3066,13 @@ getOpndList(SmallVectorImpl<SDValue> &Ops,
// Build a sequence of copy-to-reg nodes chained together with token
// chain and flag operands which copy the outgoing args into registers.
- // The InFlag in necessary since all emitted instructions must be
+ // The InGlue in necessary since all emitted instructions must be
// stuck together.
- SDValue InFlag;
+ SDValue InGlue;
for (auto &R : RegsToPass) {
- Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, R.first, R.second, InFlag);
- InFlag = Chain.getValue(1);
+ Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, R.first, R.second, InGlue);
+ InGlue = Chain.getValue(1);
}
// Add argument registers to the end of the list so that they are
@@ -3088,8 +3096,8 @@ getOpndList(SmallVectorImpl<SDValue> &Ops,
}
Ops.push_back(CLI.DAG.getRegisterMask(Mask));
- if (InFlag.getNode())
- Ops.push_back(InFlag);
+ if (InGlue.getNode())
+ Ops.push_back(InGlue);
}
void MipsTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
@@ -3219,7 +3227,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
ES ? ES->getSymbol() : nullptr);
// Get a count of how many bytes are to be pushed on the stack.
- unsigned NextStackOffset = CCInfo.getNextStackOffset();
+ unsigned StackSize = CCInfo.getStackSize();
// Call site info for function parameters tracking.
MachineFunction::CallSiteInfo CSInfo;
@@ -3229,8 +3237,8 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
bool InternalLinkage = false;
if (IsTailCall) {
IsTailCall = isEligibleForTailCallOptimization(
- CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
- if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
+ CCInfo, StackSize, *MF.getInfo<MipsFunctionInfo>());
+ if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
InternalLinkage = G->getGlobal()->hasInternalLinkage();
IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() ||
G->getGlobal()->hasPrivateLinkage() ||
@@ -3249,10 +3257,10 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
// ByValChain is the output chain of the last Memcpy node created for copying
// byval arguments to the stack.
unsigned StackAlignment = TFL->getStackAlignment();
- NextStackOffset = alignTo(NextStackOffset, StackAlignment);
+ StackSize = alignTo(StackSize, StackAlignment);
if (!(IsTailCall || MemcpyInByVal))
- Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
+ Chain = DAG.getCALLSEQ_START(Chain, StackSize, 0, DL);
SDValue StackPtr =
DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
@@ -3473,27 +3481,27 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
}
Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
- SDValue InFlag = Chain.getValue(1);
+ SDValue InGlue = Chain.getValue(1);
DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
// Create the CALLSEQ_END node in the case of where it is not a call to
// memcpy.
if (!(MemcpyInByVal)) {
- Chain = DAG.getCALLSEQ_END(Chain, NextStackOffset, 0, InFlag, DL);
- InFlag = Chain.getValue(1);
+ Chain = DAG.getCALLSEQ_END(Chain, StackSize, 0, InGlue, DL);
+ InGlue = Chain.getValue(1);
}
// Handle result values, copying them out of physregs into vregs that we
// return.
- return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
+ return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins, DL, DAG,
InVals, CLI);
}
/// LowerCallResult - Lower the result values of a call into the
/// appropriate copies out of appropriate physical registers.
SDValue MipsTargetLowering::LowerCallResult(
- SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
+ SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
TargetLowering::CallLoweringInfo &CLI) const {
@@ -3513,9 +3521,9 @@ SDValue MipsTargetLowering::LowerCallResult(
assert(VA.isRegLoc() && "Can only return in registers!");
SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
- RVLocs[i].getLocVT(), InFlag);
+ RVLocs[i].getLocVT(), InGlue);
Chain = Val.getValue(1);
- InFlag = Val.getValue(2);
+ InGlue = Val.getValue(2);
if (VA.isUpperBitsInLoc()) {
unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
@@ -3645,7 +3653,7 @@ SDValue MipsTargetLowering::LowerFormalArguments(
"Functions with the interrupt attribute cannot have arguments!");
CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
- MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
+ MipsFI->setFormalArgInfo(CCInfo.getStackSize(),
CCInfo.getInRegsParamsCount() > 0);
unsigned CurArgIdx = 0;
@@ -3832,7 +3840,7 @@ MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
// Analyze return values.
CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
- SDValue Flag;
+ SDValue Glue;
SmallVector<SDValue, 4> RetOps(1, Chain);
// Copy the result values into the output registers.
@@ -3878,10 +3886,10 @@ MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
}
- Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
+ Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);
// Guarantee that all emitted copies are stuck together with flags.
- Flag = Chain.getValue(1);
+ Glue = Chain.getValue(1);
RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
}
@@ -3899,16 +3907,16 @@ MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
- Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
- Flag = Chain.getValue(1);
+ Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Glue);
+ Glue = Chain.getValue(1);
RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
}
RetOps[0] = Chain; // Update chain.
- // Add the flag if we have it.
- if (Flag.getNode())
- RetOps.push_back(Flag);
+ // Add the glue if we have it.
+ if (Glue.getNode())
+ RetOps.push_back(Glue);
// ISRs must use "eret".
if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt"))
@@ -4038,7 +4046,7 @@ static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
EVT MipsTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
ISD::NodeType) const {
bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32;
- EVT MinVT = getRegisterType(Context, Cond ? MVT::i64 : MVT::i32);
+ EVT MinVT = getRegisterType(Cond ? MVT::i64 : MVT::i32);
return VT.bitsLT(MinVT) ? MinVT : VT;
}
@@ -4507,7 +4515,7 @@ void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
int VaArgOffset;
if (ArgRegs.size() == Idx)
- VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes);
+ VaArgOffset = alignTo(State.getStackSize(), RegSizeInBytes);
else {
VaArgOffset =
(int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h
index 723be3b31dce..8614c4d3abe5 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.h
+++ b/llvm/lib/Target/Mips/MipsISelLowering.h
@@ -21,6 +21,7 @@
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineMemOperand.h"
+#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetLowering.h"
@@ -28,7 +29,6 @@
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Type.h"
-#include "llvm/Support/MachineValueType.h"
#include "llvm/Target/TargetMachine.h"
#include <algorithm>
#include <cassert>
@@ -524,7 +524,7 @@ class TargetRegisterClass;
unsigned Flag) const;
// Lower Operand helpers
- SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
+ SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
const SDLoc &dl, SelectionDAG &DAG,
diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
index 04fe0960998d..4478a574a240 100644
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -15,7 +15,7 @@
#include "MipsMachineFunction.h"
#include "MipsRegisterBankInfo.h"
#include "MipsTargetMachine.h"
-#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/IR/IntrinsicsMips.h"
diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
index 7ed504325dbf..2738a78e4a86 100644
--- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -445,7 +445,7 @@ bool MipsLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
MIRBuilder.buildMergeLikeInstr(s64, {Src, C_HiMask.getReg(0)});
MachineInstrBuilder TwoP52FP = MIRBuilder.buildFConstant(
- s64, BitsToDouble(UINT64_C(0x4330000000000000)));
+ s64, llvm::bit_cast<double>(UINT64_C(0x4330000000000000)));
if (DstTy == s64)
MIRBuilder.buildFSub(Dst, Bitcast, TwoP52FP);
diff --git a/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp b/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
index 96fd9abfa19f..ef847adbebc1 100644
--- a/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
+++ b/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
@@ -26,6 +26,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -33,7 +34,6 @@
#include "llvm/Support/Allocator.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/RecyclingAllocator.h"
#include <cassert>
#include <utility>
diff --git a/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp b/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp
index c16869aeb637..4247bf9a4e3a 100644
--- a/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp
@@ -18,38 +18,84 @@
#include "llvm/CodeGen/GlobalISel/Combiner.h"
#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/Target/TargetMachine.h"
+#define GET_GICOMBINER_DEPS
+#include "MipsGenPostLegalizeGICombiner.inc"
+#undef GET_GICOMBINER_DEPS
+
#define DEBUG_TYPE "mips-postlegalizer-combiner"
using namespace llvm;
using namespace MIPatternMatch;
-#define MIPSPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
+namespace {
+#define GET_GICOMBINER_TYPES
#include "MipsGenPostLegalizeGICombiner.inc"
-#undef MIPSPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
+#undef GET_GICOMBINER_TYPES
-namespace {
-#define MIPSPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
+class MipsPostLegalizerCombinerImpl : public GIMatchTableExecutor {
+protected:
+ CombinerHelper &Helper;
+ const MipsPostLegalizerCombinerImplRuleConfig &RuleConfig;
+
+ const MipsSubtarget &STI;
+ GISelChangeObserver &Observer;
+ MachineIRBuilder &B;
+ MachineFunction &MF;
+
+ MachineRegisterInfo &MRI;
+
+public:
+ MipsPostLegalizerCombinerImpl(
+ const MipsPostLegalizerCombinerImplRuleConfig &RuleConfig,
+ const MipsSubtarget &STI, GISelChangeObserver &Observer,
+ MachineIRBuilder &B, CombinerHelper &Helper);
+
+ static const char *getName() { return "MipsPostLegalizerCombiner"; }
+
+ bool tryCombineAll(MachineInstr &I) const;
+
+private:
+#define GET_GICOMBINER_CLASS_MEMBERS
+#include "MipsGenPostLegalizeGICombiner.inc"
+#undef GET_GICOMBINER_CLASS_MEMBERS
+};
+
+#define GET_GICOMBINER_IMPL
+#include "MipsGenPostLegalizeGICombiner.inc"
+#undef GET_GICOMBINER_IMPL
+
+MipsPostLegalizerCombinerImpl::MipsPostLegalizerCombinerImpl(
+ const MipsPostLegalizerCombinerImplRuleConfig &RuleConfig,
+ const MipsSubtarget &STI, GISelChangeObserver &Observer,
+ MachineIRBuilder &B, CombinerHelper &Helper)
+ : Helper(Helper), RuleConfig(RuleConfig), STI(STI), Observer(Observer),
+ B(B), MF(B.getMF()), MRI(*B.getMRI()),
+#define GET_GICOMBINER_CONSTRUCTOR_INITS
#include "MipsGenPostLegalizeGICombiner.inc"
-#undef MIPSPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
+#undef GET_GICOMBINER_CONSTRUCTOR_INITS
+{
+}
class MipsPostLegalizerCombinerInfo final : public CombinerInfo {
GISelKnownBits *KB;
public:
- MipsGenPostLegalizerCombinerHelperRuleConfig GeneratedRuleCfg;
+ MipsPostLegalizerCombinerImplRuleConfig RuleConfig;
MipsPostLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
GISelKnownBits *KB, const MipsLegalizerInfo *LI)
: CombinerInfo(/*AllowIllegalOps*/ false, /*ShouldLegalizeIllegal*/ true,
/*LegalizerInfo*/ LI, EnableOpt, OptSize, MinSize),
KB(KB) {
- if (!GeneratedRuleCfg.parseCommandLineOption())
+ if (!RuleConfig.parseCommandLineOption())
report_fatal_error("Invalid rule identifier");
}
@@ -60,17 +106,14 @@ public:
bool MipsPostLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
MachineInstr &MI,
MachineIRBuilder &B) const {
-
+ const auto &STI = MI.getMF()->getSubtarget<MipsSubtarget>();
CombinerHelper Helper(Observer, B, /* IsPreLegalize*/ false, KB,
/*DominatorTree*/ nullptr, LInfo);
- MipsGenPostLegalizerCombinerHelper Generated(GeneratedRuleCfg, Helper);
- return Generated.tryCombineAll(Observer, MI, B, Helper);
+ MipsPostLegalizerCombinerImpl Impl(RuleConfig, STI, Observer, B, Helper);
+ Impl.setupMF(*MI.getMF(), KB);
+ return Impl.tryCombineAll(MI);
}
-#define MIPSPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
-#include "MipsGenPostLegalizeGICombiner.inc"
-#undef MIPSPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
-
// Pass boilerplate
// ================
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
index e1fa03379776..3b12cb35b367 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -239,11 +239,6 @@ getReservedRegs(const MachineFunction &MF) const {
return Reserved;
}
-bool
-MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
- return true;
-}
-
// FrameIndex represent objects inside a abstract stack.
// We must replace FrameIndex with an stack/frame pointer
// direct reference.
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.h b/llvm/lib/Target/Mips/MipsRegisterInfo.h
index 7eaab8d1d206..1463304d35ce 100644
--- a/llvm/lib/Target/Mips/MipsRegisterInfo.h
+++ b/llvm/lib/Target/Mips/MipsRegisterInfo.h
@@ -56,8 +56,6 @@ public:
BitVector getReservedRegs(const MachineFunction &MF) const override;
- bool requiresRegisterScavenging(const MachineFunction &MF) const override;
-
/// Stack Frame Processing Methods
bool eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
@@ -72,6 +70,8 @@ public:
/// Return GPR register class.
virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
+ bool supportsBackwardScavenger() const override { return true; }
+
private:
virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
int FrameIndex, uint64_t StackSize,
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
index df357506b34f..138735d44df6 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -204,15 +204,15 @@ void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
}
void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
- SDValue InFlag = Node->getOperand(2);
- unsigned Opc = InFlag.getOpcode();
+ SDValue InGlue = Node->getOperand(2);
+ unsigned Opc = InGlue.getOpcode();
SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
EVT VT = LHS.getValueType();
// In the base case, we can rely on the carry bit from the addsc
// instruction.
if (Opc == ISD::ADDC) {
- SDValue Ops[3] = {LHS, RHS, InFlag};
+ SDValue Ops[3] = {LHS, RHS, InGlue};
CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Ops);
return;
}
@@ -236,7 +236,7 @@ void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32);
SDNode *DSPCtrlField = CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32,
- MVT::Glue, CstOne, InFlag);
+ MVT::Glue, CstOne, InGlue);
SDNode *Carry = CurDAG->getMachineNode(
Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne);
@@ -670,8 +670,7 @@ bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
// as the original value.
if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
- Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
- EltTy);
+ Imm = CurDAG->getTargetConstant(ImmValue.popcount() - 1, SDLoc(N), EltTy);
return true;
}
}
@@ -702,8 +701,7 @@ bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
// Extract the run of set bits starting with bit zero, and test that the
// result is the same as the original value
if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
- Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
- EltTy);
+ Imm = CurDAG->getTargetConstant(ImmValue.popcount() - 1, SDLoc(N), EltTy);
return true;
}
}
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
index 2891ff0ef223..b84f304373f6 100644
--- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -18,7 +18,6 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/Triple.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
@@ -27,6 +26,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
@@ -39,9 +39,9 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/TargetParser/Triple.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
@@ -1230,10 +1230,9 @@ SDValue MipsSETargetLowering::lowerBITCAST(SDValue Op,
// Bitcast i64 to double.
if (Src == MVT::i64 && Dest == MVT::f64) {
- SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
- Op.getOperand(0), DAG.getIntPtrConstant(0, DL));
- SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
- Op.getOperand(0), DAG.getIntPtrConstant(1, DL));
+ SDValue Lo, Hi;
+ std::tie(Lo, Hi) =
+ DAG.SplitScalar(Op.getOperand(0), DL, MVT::i32, MVT::i32);
return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
}
@@ -1277,10 +1276,8 @@ SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
}
static SDValue initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG) {
- SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
- DAG.getConstant(0, DL, MVT::i32));
- SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
- DAG.getConstant(1, DL, MVT::i32));
+ SDValue InLo, InHi;
+ std::tie(InLo, InHi) = DAG.SplitScalar(In, DL, MVT::i32, MVT::i32);
return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
}
diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.h b/llvm/lib/Target/Mips/MipsSEISelLowering.h
index 9714e976a9d3..34f221e2fbf2 100644
--- a/llvm/lib/Target/Mips/MipsSEISelLowering.h
+++ b/llvm/lib/Target/Mips/MipsSEISelLowering.h
@@ -14,8 +14,8 @@
#define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
#include "MipsISelLowering.h"
+#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
-#include "llvm/Support/MachineValueType.h"
namespace llvm {
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
index f752ab2d2549..d76dc0143b23 100644
--- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -200,44 +200,14 @@ static bool isORCopyInst(const MachineInstr &MI) {
return false;
}
-/// If @MI is WRDSP/RRDSP instruction return true with @isWrite set to true
-/// if it is WRDSP instruction.
-static bool isReadOrWriteToDSPReg(const MachineInstr &MI, bool &isWrite) {
- switch (MI.getOpcode()) {
- default:
- return false;
- case Mips::WRDSP:
- case Mips::WRDSP_MM:
- isWrite = true;
- break;
- case Mips::RDDSP:
- case Mips::RDDSP_MM:
- isWrite = false;
- break;
- }
- return true;
-}
-
/// We check for the common case of 'or', as it's MIPS' preferred instruction
/// for GPRs but we have to check the operands to ensure that is the case.
/// Other move instructions for MIPS are directly identifiable.
std::optional<DestSourcePair>
MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
- bool isDSPControlWrite = false;
- // Condition is made to match the creation of WRDSP/RDDSP copy instruction
- // from copyPhysReg function.
- if (isReadOrWriteToDSPReg(MI, isDSPControlWrite)) {
- if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1 << 4))
- return std::nullopt;
- else if (isDSPControlWrite) {
- return DestSourcePair{MI.getOperand(2), MI.getOperand(0)};
-
- } else {
- return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
- }
- } else if (MI.isMoveReg() || isORCopyInst(MI)) {
+ if (MI.isMoveReg() || isORCopyInst(MI))
return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
- }
+
return std::nullopt;
}
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index 10530cdafeed..323e611207a2 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -104,8 +104,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
report_fatal_error("Code generation for MIPS-V is not implemented", false);
// Check if Architecture and ABI are compatible.
- assert(((!isGP64bit() && isABI_O32()) ||
- (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
+ assert(((!isGP64bit() && isABI_O32()) || isGP64bit()) &&
"Invalid Arch & ABI pair.");
if (hasMSA() && !isFP64bit())
generated by cgit v1.3 (git 2.53.0) at 2026-04-18 14:22:05 +0000