diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2024-09-04 14:11:41 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2024-09-04 14:11:41 +0000 |
| commit | 7432c96084d72c631f1e5ddf1cc2e24fd9c92482 (patch) | |
| tree | 20ffb3d1bc199b08a4f6b8b597e70c5e32333e15 /llvm/lib/Target/X86/X86SchedIceLake.td | |
| parent | adf62863f35c84e4c5708f3dc5a1589ce958a238 (diff) | |
Diffstat (limited to 'llvm/lib/Target/X86/X86SchedIceLake.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedIceLake.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86SchedIceLake.td b/llvm/lib/Target/X86/X86SchedIceLake.td index 186d4d84c251..b68be9be6d47 100644 --- a/llvm/lib/Target/X86/X86SchedIceLake.td +++ b/llvm/lib/Target/X86/X86SchedIceLake.td @@ -1510,8 +1510,10 @@ def ICXWriteResGroup113 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort78,ICXPort015 let ReleaseAtCycles = [1,8,8,2]; } def: InstRW<[ICXWriteResGroup113], (instrs VPSCATTERDQZmr, + VPSCATTERQDZmr, VPSCATTERQQZmr, VSCATTERDPDZmr, + VSCATTERQPSZmr, VSCATTERQPDZmr)>; def ICXWriteResGroup114 : SchedWriteRes<[ICXPort0,ICXPort49,ICXPort5,ICXPort78,ICXPort0156]> { |