10 files changed, 1661 insertions, 4 deletions

diff --git a/sys/boot/i386/Makefile b/sys/boot/i386/Makefile
index aac1821a8857..aaf94d26db27 100644
--- a/sys/boot/i386/Makefile
+++ b/sys/boot/i386/Makefile
@@ -1,6 +1,7 @@
 # $FreeBSD$
 
-SUBDIR=		mbr boot0 boot0sio btx boot2 cdboot kgzldr libi386 loader
+SUBDIR=		mbr boot0 boot0sio btx boot2 cdboot kgzldr libi386 libfirewire \
+		loader
 
 # special boot programs, 'self-extracting boot2+loader'
 SUBDIR+=	pxeldr
diff --git a/sys/boot/i386/libfirewire/Makefile b/sys/boot/i386/libfirewire/Makefile
new file mode 100644
index 000000000000..28f76307d8a0
--- /dev/null
+++ b/sys/boot/i386/libfirewire/Makefile
@@ -0,0 +1,30 @@
+# $FreeBSD$
+
+LIB=		firewire
+INTERNALLIB=
+
+.PATH:		${.CURDIR}/../../../dev/dcons ${.CURDIR}/../../../dev/firewire
+SRCS+=		firewire.c fwohci.c dconsole.c
+SRCS+=		dcons.c fwcrom.c
+
+CFLAGS+=	-D_BOOT
+
+CFLAGS+=	-I${.CURDIR}/../../common -I${.CURDIR}/../../.. -I.
+CFLAGS+=	-I${.CURDIR}/../../../../lib/libstand
+CFLAGS+=	-I${.CURDIR}/../btx/lib
+CFLAGS+=	-I${.CURDIR}/../libi386
+
+CFLAGS+=	-Wformat -Wall
+
+.if ${MACHINE_ARCH} == "amd64"
+CLEANFILES+=    machine
+machine:
+	ln -sf ${.CURDIR}/../../../i386/include machine
+.endif
+
+.include <bsd.lib.mk>
+
+.if ${MACHINE_ARCH} == "amd64"
+beforedepend ${OBJS}: machine
+.endif
+
diff --git a/sys/boot/i386/libfirewire/dconsole.c b/sys/boot/i386/libfirewire/dconsole.c
new file mode 100644
index 000000000000..16645e259cb0
--- /dev/null
+++ b/sys/boot/i386/libfirewire/dconsole.c
@@ -0,0 +1,127 @@
+/*-
+ * Copyright (c) 2004 Hidetoshi Shimokawa
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <stand.h>
+#include <bootstrap.h>
+#include <sys/param.h>
+#include <btxv86.h>
+#include <dev/dcons/dcons.h>
+
+void fw_enable(void);
+void fw_poll(void);
+
+static void	dconsole_probe(struct console *cp);
+static int	dconsole_init(int arg);
+static void	dconsole_putchar(int c);
+static int	dconsole_getchar(void);
+static int	dconsole_ischar(void);
+
+static int	dcons_started = 0;
+
+#define DCONS_BUF_SIZE (64*1024)
+static struct dcons_softc sc[DCONS_NPORT];
+uint32_t dcons_paddr;
+
+/* The buffer must be allocated in BSS becase:
+ *    - The dcons driver in the kernel is initialized before VM/pmap is
+ *	initialized, so that the buffer must be allocate in the region
+ *	that is mapped at the very early boot state.
+ *    - We expect identiy map only for regions before KERNLOAD
+ *	(i386:4MB amd64:1MB).
+ *    - It seems that heap in conventional memory(640KB) is not sufficent
+ *	and we move it to high address as LOADER_SUPPORT_BZIP2.
+ *    - BSS is placed in conventional memory.
+ */
+static char dcons_buffer[DCONS_BUF_SIZE + PAGE_SIZE];
+
+struct console dconsole = {
+    "dcons",
+    "dumb console port",
+    0,
+    dconsole_probe,
+    dconsole_init,
+    dconsole_putchar,
+    dconsole_getchar,
+    dconsole_ischar
+};
+
+#define DCONSOLE_AS_MULTI_CONSOLE	1
+
+static void
+dconsole_probe(struct console *cp)
+{
+    /* XXX check the BIOS equipment list? */
+    cp->c_flags |= (C_PRESENTIN | C_PRESENTOUT);
+#if DCONSOLE_AS_MULTI_CONSOLE
+    dconsole_init(0);
+    cp->c_flags |= (C_ACTIVEIN | C_ACTIVEOUT);
+#endif
+}
+
+static int
+dconsole_init(int arg)
+{
+    char buf[16], *dbuf;
+    int size;
+
+    if (dcons_started && arg == 0)
+	return 0;
+    dcons_started = 1;
+
+    size = DCONS_BUF_SIZE;
+    dbuf = (char *)round_page((vm_offset_t)&dcons_buffer[0]);
+    dcons_paddr = VTOP(dbuf);
+    sprintf(buf, "0x%08x", dcons_paddr);
+    setenv("dcons.addr", buf, 1);
+
+    dcons_init((struct dcons_buf *)dbuf, size, sc);
+    sprintf(buf, "%d", size);
+    setenv("dcons.size", buf, 1);
+    fw_enable();
+    return(0);
+}
+
+static void
+dconsole_putchar(int c)
+{
+    dcons_putc(&sc[0], c);
+}
+
+static int
+dconsole_getchar(void)
+{
+    fw_poll();
+    return (dcons_checkc(&sc[0]));
+}
+
+static int
+dconsole_ischar(void)
+{
+    fw_poll();
+    return (dcons_ischar(&sc[0]));
+}
diff --git a/sys/boot/i386/libfirewire/firewire.c b/sys/boot/i386/libfirewire/firewire.c
new file mode 100644
index 000000000000..5d408e0959f2
--- /dev/null
+++ b/sys/boot/i386/libfirewire/firewire.c
@@ -0,0 +1,470 @@
+/*-
+ * Copyright (c) 2004 Hidetoshi Shimokawa <simokawa@FreeBSD.ORG>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * FireWire disk device handling.
+ * 
+ */
+
+#include <stand.h>
+
+#include <machine/bootinfo.h>
+
+#include <stdarg.h>
+
+#include <bootstrap.h>
+#include <btxv86.h>
+#include <libi386.h>
+#include "fwohci.h"
+#include <dev/dcons/dcons.h>
+
+/* XXX */
+#define BIT4x2(x,y)      uint8_t  y:4, x:4
+#define BIT16x2(x,y)    uint32_t y:16, x:16
+#define _KERNEL
+#include <dev/firewire/iec13213.h>
+
+extern uint32_t dcons_paddr;
+extern struct console dconsole;
+
+struct crom_src_buf {
+	struct crom_src src;
+	struct crom_chunk root;
+	struct crom_chunk vendor;
+	struct crom_chunk hw;
+	/* for dcons */
+	struct crom_chunk unit;
+	struct crom_chunk spec;
+	struct crom_chunk ver;
+};
+
+static int	fw_init(void);
+static int	fw_strategy(void *devdata, int flag, daddr_t dblk,
+		    size_t size, char *buf, size_t *rsize);
+static int	fw_open(struct open_file *f, ...);
+static int	fw_close(struct open_file *f);
+static void	fw_print(int verbose);
+static void	fw_cleanup(void);
+
+void		fw_enable(void);
+
+struct devsw fwohci = {
+    "FW1394", 	/* 7 chars at most */
+    DEVT_NET, 
+    fw_init,
+    fw_strategy, 
+    fw_open, 
+    fw_close, 
+    noioctl,
+    fw_print,
+    fw_cleanup
+};
+
+static struct fwohci_softc fwinfo[MAX_OHCI];
+static int fw_initialized = 0;
+
+static void
+fw_probe(int index, struct fwohci_softc *sc)
+{
+	int err;
+
+	sc->state = FWOHCI_STATE_INIT;
+	err = biospci_find_devclass(
+		0x0c0010	/* Serial:FireWire:OHCI */,
+		index		/* index */,
+		&sc->locator);
+
+	if (err != 0) {
+		sc->state = FWOHCI_STATE_DEAD;
+		return;
+	}
+
+	biospci_write_config(sc->locator,
+		0x4	/* command */,
+		0x6	/* enable bus master and memory mapped I/O */,
+		1	/* word */);
+
+	biospci_read_config(sc->locator, 0x00 /*devid*/, 2 /*dword*/,
+		&sc->devid);
+	biospci_read_config(sc->locator, 0x10 /*base_addr*/, 2 /*dword*/,
+		&sc->base_addr);
+
+        sc->handle = (uint32_t)PTOV(sc->base_addr);
+	sc->bus_id = OREAD(sc, OHCI_BUS_ID);
+
+	return;
+}
+
+static int
+fw_init(void) 
+{
+	int i, avail;
+	struct fwohci_softc *sc;
+
+	if (fw_initialized)
+		return (0);
+
+	avail = 0;
+	for (i = 0; i < MAX_OHCI; i ++) {
+		sc = &fwinfo[i];
+		fw_probe(i, sc);
+		if (sc->state == FWOHCI_STATE_DEAD)
+			break;
+		avail ++;
+			break;
+	}
+	fw_initialized = 1;
+
+	return (0);
+}
+
+
+/*
+ * Print information about OHCI chips
+ */
+static void
+fw_print(int verbose)
+{
+	int i;
+	struct fwohci_softc *sc;
+
+	for (i = 0; i < MAX_OHCI; i ++) {
+		sc = &fwinfo[i];
+		if (sc->state == FWOHCI_STATE_DEAD)
+			break;
+		printf("%d: locator=0x%04x devid=0x%08x"
+			" base_addr=0x%08x handle=0x%08x bus_id=0x%08x\n",
+			i, sc->locator, sc->devid,
+			sc->base_addr, sc->handle, sc->bus_id);
+	}
+}
+
+static int 
+fw_open(struct open_file *f, ...)
+{
+#if 0
+    va_list			ap;
+    struct i386_devdesc		*dev;
+    struct open_disk		*od;
+    int				error;
+
+    va_start(ap, f);
+    dev = va_arg(ap, struct i386_devdesc *);
+    va_end(ap);
+#endif
+
+    return (ENXIO);
+}
+
+static int
+fw_close(struct open_file *f)
+{
+    return (0);
+}
+
+static void 
+fw_cleanup()
+{
+    struct dcons_buf *db;
+
+    /* invalidate dcons buffer */
+    if (dcons_paddr) {
+	db = (struct dcons_buf *)PTOV(dcons_paddr);
+	db->magic = 0;
+    }
+}
+
+static int 
+fw_strategy(void *devdata, int rw, daddr_t dblk, size_t size, char *buf, size_t *rsize)
+{
+	return (EIO);
+}
+
+static void
+fw_init_crom(struct fwohci_softc *sc)
+{
+	struct crom_src *src;
+
+	printf("fw_init_crom\n");
+	sc->crom_src_buf = (struct crom_src_buf *)
+		malloc(sizeof(struct crom_src_buf));
+	if (sc->crom_src_buf == NULL)
+		return;
+
+	src = &sc->crom_src_buf->src;
+	bzero(src, sizeof(struct crom_src));
+
+	/* BUS info sample */
+	src->hdr.info_len = 4;
+
+	src->businfo.bus_name = CSR_BUS_NAME_IEEE1394;
+
+	src->businfo.irmc = 1;
+	src->businfo.cmc = 1;
+	src->businfo.isc = 1;
+	src->businfo.bmc = 1;
+	src->businfo.pmc = 0;
+	src->businfo.cyc_clk_acc = 100;
+	src->businfo.max_rec = sc->maxrec;
+	src->businfo.max_rom = MAXROM_4;
+	src->businfo.generation = 1;
+	src->businfo.link_spd = sc->speed;
+
+	src->businfo.eui64.hi = sc->eui.hi;
+	src->businfo.eui64.lo = sc->eui.lo;
+
+	STAILQ_INIT(&src->chunk_list);
+
+	sc->crom_src = src;
+	sc->crom_root = &sc->crom_src_buf->root;
+}
+
+static void
+fw_reset_crom(struct fwohci_softc *sc)
+{
+	struct crom_src_buf *buf;
+	struct crom_src *src;
+	struct crom_chunk *root;
+
+	printf("fw_reset\n");
+	if (sc->crom_src_buf == NULL)
+		fw_init_crom(sc);
+
+	buf = sc->crom_src_buf;
+	src = sc->crom_src;
+	root = sc->crom_root;
+
+	STAILQ_INIT(&src->chunk_list);
+
+	bzero(root, sizeof(struct crom_chunk));
+	crom_add_chunk(src, NULL, root, 0);
+	crom_add_entry(root, CSRKEY_NCAP, 0x0083c0); /* XXX */
+	/* private company_id */
+	crom_add_entry(root, CSRKEY_VENDOR, CSRVAL_VENDOR_PRIVATE);
+#ifdef __DragonFly__
+	crom_add_simple_text(src, root, &buf->vendor, "DragonFly Project");
+#else
+	crom_add_simple_text(src, root, &buf->vendor, "FreeBSD Project");
+#endif
+}
+
+
+#define ADDR_HI(x)	(((x) >> 24) & 0xffffff)
+#define ADDR_LO(x)	((x) & 0xffffff)
+
+static void
+dcons_crom(struct fwohci_softc *sc)
+{
+	struct crom_src_buf *buf;
+	struct crom_src *src;
+	struct crom_chunk *root;
+
+	buf = sc->crom_src_buf;
+	src = sc->crom_src;
+	root = sc->crom_root;
+
+	bzero(&buf->unit, sizeof(struct crom_chunk));
+
+	crom_add_chunk(src, root, &buf->unit, CROM_UDIR);
+	crom_add_entry(&buf->unit, CSRKEY_SPEC, CSRVAL_VENDOR_PRIVATE);
+	crom_add_simple_text(src, &buf->unit, &buf->spec, "FreeBSD");
+	crom_add_entry(&buf->unit, CSRKEY_VER, DCONS_CSR_VAL_VER);
+	crom_add_simple_text(src, &buf->unit, &buf->ver, "dcons");
+	crom_add_entry(&buf->unit, DCONS_CSR_KEY_HI, ADDR_HI(dcons_paddr));
+	crom_add_entry(&buf->unit, DCONS_CSR_KEY_LO, ADDR_LO(dcons_paddr));
+}
+
+void
+fw_crom(struct fwohci_softc *sc)
+{
+	struct crom_src *src;
+	void *newrom;
+
+	fw_reset_crom(sc);
+	dcons_crom(sc);
+
+	newrom = malloc(CROMSIZE);
+	src = &sc->crom_src_buf->src;
+	crom_load(src, (uint32_t *)newrom, CROMSIZE);
+	if (bcmp(newrom, sc->config_rom, CROMSIZE) != 0) {
+		/* bump generation and reload */
+		src->businfo.generation ++;
+		/* generation must be between 0x2 and 0xF */
+		if (src->businfo.generation < 2)
+			src->businfo.generation ++;
+		crom_load(src, (uint32_t *)newrom, CROMSIZE);
+		bcopy(newrom, (void *)sc->config_rom, CROMSIZE);
+	}
+	free(newrom);
+}
+
+static int
+fw_busreset(struct fwohci_softc *sc)
+{
+	int count;
+
+	if (sc->state < FWOHCI_STATE_ENABLED) {
+		printf("fwohci not enabled\n");
+		return(CMD_OK);
+	}
+	fw_crom(sc);
+	fwohci_ibr(sc);
+	count = 0;
+	while (sc->state< FWOHCI_STATE_NORMAL) {
+		fwohci_poll(sc);
+		count ++;
+		if (count > 1000) {
+			printf("give up to wait bus initialize\n");
+			return (-1);
+		}
+	}
+	printf("poll count = %d\n", count);
+	return (0);
+}
+
+void
+fw_enable(void)
+{
+	struct fwohci_softc *sc;
+	int i;
+
+	if (fw_initialized == 0)
+		fw_init();
+
+	for (i = 0; i < MAX_OHCI; i ++) {
+		sc = &fwinfo[i];
+		if (sc->state != FWOHCI_STATE_INIT)
+			break;
+
+		sc->config_rom = (uint32_t *)
+			(((uint32_t)sc->config_rom_buf
+				+ (CROMSIZE - 1)) & ~(CROMSIZE - 1));
+#if 0
+		printf("configrom: %08p %08p\n",
+			sc->config_rom_buf, sc->config_rom);
+#endif
+		if (fwohci_init(sc, 0) == 0) {
+			sc->state = FWOHCI_STATE_ENABLED;
+			fw_busreset(sc);
+		} else
+			sc->state = FWOHCI_STATE_DEAD;
+	}
+}
+
+void
+fw_poll(void)
+{
+	struct fwohci_softc *sc;
+	int i;
+
+	if (fw_initialized == 0)
+		return;
+
+	for (i = 0; i < MAX_OHCI; i ++) {
+		sc = &fwinfo[i];
+		if (sc->state < FWOHCI_STATE_ENABLED)
+			break;
+		fwohci_poll(sc);
+	}
+}
+
+#if 0 /* for debug */
+static int
+fw_busreset_cmd(int argc, char *argv[])
+{
+	struct fwohci_softc *sc;
+	int i;
+
+	for (i = 0; i < MAX_OHCI; i ++) {
+		sc = &fwinfo[i];
+		if (sc->state < FWOHCI_STATE_INIT)
+			break;
+		fw_busreset(sc);
+	}
+	return(CMD_OK);
+}
+
+static int
+fw_poll_cmd(int argc, char *argv[])
+{
+	fw_poll();
+	return(CMD_OK);
+}
+
+static int
+fw_enable_cmd(int argc, char *argv[])
+{
+	fw_print(0);
+	fw_enable();
+	return(CMD_OK);
+}
+
+
+static int
+dcons_enable(int argc, char *argv[])
+{
+	dconsole.c_init(0);
+	fw_enable();
+	dconsole.c_flags |= C_ACTIVEIN | C_ACTIVEOUT;
+	return(CMD_OK);
+}
+
+static int
+dcons_read(int argc, char *argv[])
+{
+	char c;
+	while (dconsole.c_ready()) {
+		c = dconsole.c_in();
+		printf("%c", c);
+	}
+	printf("\r\n");
+	return(CMD_OK);
+}
+
+static int
+dcons_write(int argc, char *argv[])
+{
+	int len, i;
+	if (argc < 2)
+		return(CMD_OK);
+
+	len = strlen(argv[1]);
+	for (i = 0; i < len; i ++)
+		dconsole.c_out(argv[1][i]);
+	dconsole.c_out('\r');
+	dconsole.c_out('\n');
+	return(CMD_OK);
+}
+COMMAND_SET(firewire, "firewire", "enable firewire", fw_enable_cmd);
+COMMAND_SET(fwbusreset, "fwbusreset", "firewire busreset", fw_busreset_cmd);
+COMMAND_SET(fwpoll, "fwpoll", "firewire poll", fw_poll_cmd);
+COMMAND_SET(dcons, "dcons", "enable dcons", dcons_enable);
+COMMAND_SET(dread, "dread", "read from dcons", dcons_read);
+COMMAND_SET(dwrite, "dwrite", "write to dcons", dcons_write);
+#endif
diff --git a/sys/boot/i386/libfirewire/fwohci.c b/sys/boot/i386/libfirewire/fwohci.c
new file mode 100644
index 000000000000..326e44b2ecc6
--- /dev/null
+++ b/sys/boot/i386/libfirewire/fwohci.c
@@ -0,0 +1,479 @@
+/*
+ * Copyright (c) 2003 Hidetoshi Shimokawa
+ * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the acknowledgement as bellow:
+ *
+ *    This product includes software developed by K. Kobayashi and H. Shimokawa
+ *
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * $FreeBSD$
+ *
+ */
+
+#include <stand.h>
+#include <btxv86.h>
+#include <bootstrap.h>
+
+#include "fwohci.h"
+#include "fwohcireg.h"
+#include <dev/firewire/firewire_phy.h>
+
+static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t);
+static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t);
+int firewire_debug=0;
+
+#if 0
+#define device_printf(a, x, ...)	printf("FW1394: " x, ## __VA_ARGS__)
+#else
+#define device_printf(a, x, ...)
+#endif
+
+#define device_t int
+#define	DELAY(x)	delay(x)
+
+#define MAX_SPEED 3
+#define MAXREC(x)  (2 << (x))
+char *linkspeed[] = {
+	"S100", "S200", "S400", "S800",
+	"S1600", "S3200", "undef", "undef"
+};
+
+#define FW_EUI64_BYTE(eui, x) \
+	((((x)<4)?				\
+		((eui)->hi >> (8*(3-(x)))): 	\
+		((eui)->lo >> (8*(7-(x))))	\
+	) & 0xff)
+
+/*
+ * Communication with PHY device
+ */
+static uint32_t
+fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data)
+{
+	uint32_t fun;
+
+	addr &= 0xf;
+	data &= 0xff;
+
+	fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
+	OWRITE(sc, OHCI_PHYACCESS, fun);
+	DELAY(100);
+
+	return(fwphy_rddata( sc, addr));
+}
+
+static uint32_t
+fwphy_rddata(struct fwohci_softc *sc,  u_int addr)
+{
+	uint32_t fun, stat;
+	u_int i, retry = 0;
+
+	addr &= 0xf;
+#define MAX_RETRY 100
+again:
+	OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
+	fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
+	OWRITE(sc, OHCI_PHYACCESS, fun);
+	for ( i = 0 ; i < MAX_RETRY ; i ++ ){
+		fun = OREAD(sc, OHCI_PHYACCESS);
+		if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
+			break;
+		DELAY(100);
+	}
+	if(i >= MAX_RETRY) {
+		if (firewire_debug)
+			device_printf(sc->fc.dev, "phy read failed(1).\n");
+		if (++retry < MAX_RETRY) {
+			DELAY(100);
+			goto again;
+		}
+	}
+	/* Make sure that SCLK is started */
+	stat = OREAD(sc, FWOHCI_INTSTAT);
+	if ((stat & OHCI_INT_REG_FAIL) != 0 ||
+			((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
+		if (firewire_debug)
+			device_printf(sc->fc.dev, "phy read failed(2).\n");
+		if (++retry < MAX_RETRY) {
+			DELAY(100);
+			goto again;
+		}
+	}
+	if (firewire_debug || retry >= MAX_RETRY)
+		device_printf(sc->fc.dev, 
+		    "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry);
+#undef MAX_RETRY
+	return((fun >> PHYDEV_RDDATA )& 0xff);
+}
+
+
+static int
+fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
+{
+	uint32_t reg, reg2;
+	int e1394a = 1;
+	int nport, speed;
+/*
+ * probe PHY parameters
+ * 0. to prove PHY version, whether compliance of 1394a.
+ * 1. to probe maximum speed supported by the PHY and 
+ *    number of port supported by core-logic.
+ *    It is not actually available port on your PC .
+ */
+	OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
+	DELAY(500);
+
+	reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
+
+	if((reg >> 5) != 7 ){
+		nport = reg & FW_PHY_NP;
+		speed = reg & FW_PHY_SPD >> 6;
+		if (speed > MAX_SPEED) {
+			device_printf(dev, "invalid speed %d (fixed to %d).\n",
+				speed, MAX_SPEED);
+			speed = MAX_SPEED;
+		}
+		device_printf(dev,
+			"Phy 1394 only %s, %d ports.\n",
+			linkspeed[speed], nport);
+	}else{
+		reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
+		nport = reg & FW_PHY_NP;
+		speed = (reg2 & FW_PHY_ESPD) >> 5;
+		if (speed > MAX_SPEED) {
+			device_printf(dev, "invalid speed %d (fixed to %d).\n",
+				speed, MAX_SPEED);
+			speed = MAX_SPEED;
+		}
+		device_printf(dev,
+			"Phy 1394a available %s, %d ports.\n",
+			linkspeed[speed], nport);
+
+		/* check programPhyEnable */
+		reg2 = fwphy_rddata(sc, 5);
+#if 0
+		if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
+#else	/* XXX force to enable 1394a */
+		if (e1394a) {
+#endif
+			if (firewire_debug)
+				device_printf(dev,
+					"Enable 1394a Enhancements\n");
+			/* enable EAA EMC */
+			reg2 |= 0x03;
+			/* set aPhyEnhanceEnable */
+			OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
+			OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
+		} else {
+			/* for safe */
+			reg2 &= ~0x83;
+		}
+		reg2 = fwphy_wrdata(sc, 5, reg2);
+	}
+	sc->speed = speed;
+
+	reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
+	if((reg >> 5) == 7 ){
+		reg = fwphy_rddata(sc, 4);
+		reg |= 1 << 6;
+		fwphy_wrdata(sc, 4, reg);
+		reg = fwphy_rddata(sc, 4);
+	}
+	return 0;
+}
+
+
+void
+fwohci_reset(struct fwohci_softc *sc, device_t dev)
+{
+	int i, max_rec, speed;
+	uint32_t reg, reg2;
+
+	/* Disable interrupts */ 
+	OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
+
+	/* FLUSH FIFO and reset Transmitter/Reciever */
+	OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
+	if (firewire_debug)
+		device_printf(dev, "resetting OHCI...");
+	i = 0;
+	while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
+		if (i++ > 100) break;
+		DELAY(1000);
+	}
+	if (firewire_debug)
+		printf("done (loop=%d)\n", i);
+
+	/* Probe phy */
+	fwohci_probe_phy(sc, dev);
+
+	/* Probe link */
+	reg = OREAD(sc,  OHCI_BUS_OPT);
+	reg2 = reg | OHCI_BUSFNC;
+	max_rec = (reg & 0x0000f000) >> 12;
+	speed = (reg & 0x00000007);
+	device_printf(dev, "Link %s, max_rec %d bytes.\n",
+			linkspeed[speed], MAXREC(max_rec));
+	/* XXX fix max_rec */
+	sc->maxrec = sc->speed + 8;
+	if (max_rec != sc->maxrec) {
+		reg2 = (reg2 & 0xffff0fff) | (sc->maxrec << 12);
+		device_printf(dev, "max_rec %d -> %d\n",
+				MAXREC(max_rec), MAXREC(sc->maxrec));
+	}
+	if (firewire_debug)
+		device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
+	OWRITE(sc,  OHCI_BUS_OPT, reg2);
+
+	/* Initialize registers */
+	OWRITE(sc, OHCI_CROMHDR, sc->config_rom[0]);
+	OWRITE(sc, OHCI_CROMPTR, VTOP(sc->config_rom));
+#if 0
+	OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
+#endif
+	OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
+	OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
+#if 0
+	OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
+#endif
+
+	/* Enable link */
+	OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
+}
+
+int
+fwohci_init(struct fwohci_softc *sc, device_t dev)
+{
+	int i, mver;
+	uint32_t reg;
+	uint8_t ui[8];
+
+/* OHCI version */
+	reg = OREAD(sc, OHCI_VERSION);
+	mver = (reg >> 16) & 0xff;
+	device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
+			mver, reg & 0xff, (reg>>24) & 1);
+	if (mver < 1 || mver > 9) {
+		device_printf(dev, "invalid OHCI version\n");
+		return (ENXIO);
+	}
+
+/* Available Isochronous DMA channel probe */
+	OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
+	OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
+	reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
+	OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
+	OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
+	for (i = 0; i < 0x20; i++)
+		if ((reg & (1 << i)) == 0)
+			break;
+	device_printf(dev, "No. of Isochronous channels is %d.\n", i);
+	if (i == 0)
+		return (ENXIO);
+
+#if 0
+/* SID recieve buffer must align 2^11 */
+#define	OHCI_SIDSIZE	(1 << 11)
+	sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
+						&sc->sid_dma, BUS_DMA_WAITOK);
+	if (sc->sid_buf == NULL) {
+		device_printf(dev, "sid_buf alloc failed.");
+		return ENOMEM;
+	}
+#endif
+
+	sc->eui.hi = OREAD(sc, FWOHCIGUID_H);
+	sc->eui.lo = OREAD(sc, FWOHCIGUID_L);
+	for( i = 0 ; i < 8 ; i ++)
+		ui[i] = FW_EUI64_BYTE(&sc->eui,i);
+	device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
+		ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
+	fwohci_reset(sc, dev);
+
+	return 0;
+}
+
+void
+fwohci_ibr(struct fwohci_softc *sc)
+{
+	uint32_t fun;
+
+	device_printf(sc->dev, "Initiate bus reset\n");
+
+	/*
+	 * Make sure our cached values from the config rom are
+	 * initialised.
+	 */
+	OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0]));
+	OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2]));
+
+	/*
+	 * Set root hold-off bit so that non cyclemaster capable node
+	 * shouldn't became the root node.
+	 */
+#if 1
+	fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
+	fun |= FW_PHY_IBR;
+	fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
+#else	/* Short bus reset */
+	fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
+	fun |= FW_PHY_ISBR;
+	fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
+#endif
+}
+
+
+void
+fwohci_sid(struct fwohci_softc *sc)
+{
+		uint32_t node_id;
+		int plen;
+
+		node_id = OREAD(sc, FWOHCI_NODEID);
+		if (!(node_id & OHCI_NODE_VALID)) {
+#if 0
+			printf("Bus reset failure\n");
+#endif
+			return;
+		}
+
+		/* Enable bus reset interrupt */
+		OWRITE(sc, FWOHCI_INTMASK,  OHCI_INT_PHY_BUS_R);
+		/* Allow async. request to us */
+		OWRITE(sc, OHCI_AREQHI, 1 << 31);
+		/* XXX insecure ?? */
+		OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
+		OWRITE(sc, OHCI_PREQLO, 0xffffffff);
+		OWRITE(sc, OHCI_PREQUPPER, 0x10000);
+		/* Set ATRetries register */
+		OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
+/*
+** Checking whether the node is root or not. If root, turn on 
+** cycle master.
+*/
+		plen = OREAD(sc, OHCI_SID_CNT);
+		device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
+			node_id, (plen >> 16) & 0xff);
+		if (node_id & OHCI_NODE_ROOT) {
+			device_printf(sc->dev, "CYCLEMASTER mode\n");
+			OWRITE(sc, OHCI_LNKCTL,
+				OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
+		} else {
+			device_printf(sc->dev, "non CYCLEMASTER mode\n");
+			OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
+			OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
+		}
+		if (plen & OHCI_SID_ERR) {
+			device_printf(fc->dev, "SID Error\n");
+			return;
+		}
+		device_printf(sc->dev, "bus reset phase done\n");
+		sc->state = FWOHCI_STATE_NORMAL;
+}
+
+static void
+fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count)
+{
+#undef OHCI_DEBUG
+#ifdef OHCI_DEBUG
+#if 0
+	if(stat & OREAD(sc, FWOHCI_INTMASK))
+#else
+	if (1)
+#endif
+		device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
+			stat & OHCI_INT_EN ? "DMA_EN ":"",
+			stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
+			stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
+			stat & OHCI_INT_ERR ? "INT_ERR ":"",
+			stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
+			stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
+			stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
+			stat & OHCI_INT_CYC_START ? "CYC_START ":"",
+			stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
+			stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
+			stat & OHCI_INT_PHY_SID ? "SID ":"",
+			stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
+			stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
+			stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
+			stat & OHCI_INT_DMA_IT  ? "DMA_IT " :"",
+			stat & OHCI_INT_DMA_PRRS  ? "DMA_PRRS " :"",
+			stat & OHCI_INT_DMA_PRRQ  ? "DMA_PRRQ " :"",
+			stat & OHCI_INT_DMA_ARRS  ? "DMA_ARRS " :"",
+			stat & OHCI_INT_DMA_ARRQ  ? "DMA_ARRQ " :"",
+			stat & OHCI_INT_DMA_ATRS  ? "DMA_ATRS " :"",
+			stat & OHCI_INT_DMA_ATRQ  ? "DMA_ATRQ " :"",
+			stat, OREAD(sc, FWOHCI_INTMASK) 
+		);
+#endif
+/* Bus reset */
+	if(stat & OHCI_INT_PHY_BUS_R ){
+		device_printf(fc->dev, "BUS reset\n");
+		if (sc->state == FWOHCI_STATE_BUSRESET)
+			goto busresetout;
+		sc->state = FWOHCI_STATE_BUSRESET;
+		/* Disable bus reset interrupt until sid recv. */
+		OWRITE(sc, FWOHCI_INTMASKCLR,  OHCI_INT_PHY_BUS_R);
+	
+		OWRITE(sc, FWOHCI_INTMASKCLR,  OHCI_INT_CYC_LOST);
+		OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
+
+		OWRITE(sc, OHCI_CROMHDR, ntohl(sc->config_rom[0]));
+		OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->config_rom[2]));
+	} else if (sc->state == FWOHCI_STATE_BUSRESET) {
+		fwohci_sid(sc);
+	}
+busresetout:
+	return;
+}
+
+static uint32_t
+fwochi_check_stat(struct fwohci_softc *sc)
+{
+	uint32_t stat;
+
+	stat = OREAD(sc, FWOHCI_INTSTAT);
+	if (stat == 0xffffffff) {
+		device_printf(sc->fc.dev, 
+			"device physically ejected?\n");
+		return(stat);
+	}
+	if (stat)
+		OWRITE(sc, FWOHCI_INTSTATCLR, stat);
+	return(stat);
+}
+
+void
+fwohci_poll(struct fwohci_softc *sc)
+{
+	uint32_t stat;
+
+	stat = fwochi_check_stat(sc);
+	if (stat != 0xffffffff)
+		fwohci_intr_body(sc, stat, 1);
+}
diff --git a/sys/boot/i386/libfirewire/fwohci.h b/sys/boot/i386/libfirewire/fwohci.h
new file mode 100644
index 000000000000..fc20043d9274
--- /dev/null
+++ b/sys/boot/i386/libfirewire/fwohci.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2007 Hidetoshi Shimokawa
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the acknowledgement as bellow:
+ *
+ *    This product includes software developed by K. Kobayashi and H. Shimokawa
+ *
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * $FreeBSD$
+ *
+ */
+
+#define MAX_OHCI 5
+#define CROMSIZE 0x400
+
+struct fw_eui64 {
+        uint32_t hi, lo;
+};
+
+struct fwohci_softc {
+	uint32_t locator;
+	uint32_t devid;
+	uint32_t base_addr;
+	uint32_t bus_id;
+	uint32_t handle;
+	int32_t state;
+	struct crom_src_buf *crom_src_buf;
+	struct crom_src *crom_src;
+	struct crom_chunk *crom_root;
+	struct fw_eui64 eui;
+	int	speed;
+	int	maxrec;
+	uint32_t *config_rom;
+	char config_rom_buf[CROMSIZE*2]; /* double size for alignment */
+};
+
+int fwohci_init(struct fwohci_softc *, int);
+void fwohci_ibr(struct fwohci_softc *);
+void fwohci_poll(struct fwohci_softc *);
+
+#define FWOHCI_STATE_DEAD	(-1)
+#define FWOHCI_STATE_INIT	0
+#define FWOHCI_STATE_ENABLED	1
+#define FWOHCI_STATE_BUSRESET	2
+#define FWOHCI_STATE_NORMAL	3
+
+#define OREAD(f, o) (*(volatile uint32_t *)((f)->handle + (o)))
+#define OWRITE(f, o, v) (*(volatile uint32_t *)((f)->handle + (o)) = (v))
+
+#define	OHCI_VERSION		0x00
+#define	OHCI_ATRETRY		0x08
+#define	OHCI_CROMHDR		0x18
+#define OHCI_BUS_ID		0x1c
+#define	OHCI_BUS_OPT		0x20
+#define	OHCI_BUSIRMC		(1 << 31)
+#define	OHCI_BUSCMC		(1 << 30)
+#define	OHCI_BUSISC		(1 << 29)
+#define	OHCI_BUSBMC		(1 << 28)
+#define	OHCI_BUSPMC		(1 << 27)
+#define OHCI_BUSFNC		OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
+				OHCI_BUSBMC | OHCI_BUSPMC
+
+#define	OHCI_EUID_HI		0x24
+#define	OHCI_EUID_LO		0x28
+
+#define	OHCI_CROMPTR		0x34
+#define	OHCI_HCCCTL		0x50
+#define	OHCI_HCCCTLCLR		0x54
+#define	OHCI_AREQHI		0x100
+#define	OHCI_AREQHICLR		0x104
+#define	OHCI_AREQLO		0x108
+#define	OHCI_AREQLOCLR		0x10c
+#define	OHCI_PREQHI		0x110
+#define	OHCI_PREQHICLR		0x114
+#define	OHCI_PREQLO		0x118
+#define	OHCI_PREQLOCLR		0x11c
+#define	OHCI_PREQUPPER		0x120
+
+#define	OHCI_SID_BUF		0x64
+#define	OHCI_SID_CNT		0x68
+#define OHCI_SID_ERR		(1 << 31)
+#define OHCI_SID_CNT_MASK	0xffc
+
+#define	OHCI_IT_STAT		0x90
+#define	OHCI_IT_STATCLR		0x94
+#define	OHCI_IT_MASK		0x98
+#define	OHCI_IT_MASKCLR		0x9c
+
+#define	OHCI_IR_STAT		0xa0
+#define	OHCI_IR_STATCLR		0xa4
+#define	OHCI_IR_MASK		0xa8
+#define	OHCI_IR_MASKCLR		0xac
+
+#define	OHCI_LNKCTL		0xe0
+#define	OHCI_LNKCTLCLR		0xe4
+
+#define	OHCI_PHYACCESS		0xec
+#define	OHCI_CYCLETIMER		0xf0
+
+#define	OHCI_DMACTL(off)	(off)
+#define	OHCI_DMACTLCLR(off)	(off + 4)
+#define	OHCI_DMACMD(off)	(off + 0xc)
+#define	OHCI_DMAMATCH(off)	(off + 0x10)
+
+#define OHCI_ATQOFF		0x180
+#define OHCI_ATQCTL		OHCI_ATQOFF
+#define OHCI_ATQCTLCLR		(OHCI_ATQOFF + 4)
+#define OHCI_ATQCMD		(OHCI_ATQOFF + 0xc)
+#define OHCI_ATQMATCH		(OHCI_ATQOFF + 0x10)
+
+#define OHCI_ATSOFF		0x1a0
+#define OHCI_ATSCTL		OHCI_ATSOFF
+#define OHCI_ATSCTLCLR		(OHCI_ATSOFF + 4)
+#define OHCI_ATSCMD		(OHCI_ATSOFF + 0xc)
+#define OHCI_ATSMATCH		(OHCI_ATSOFF + 0x10)
+
+#define OHCI_ARQOFF		0x1c0
+#define OHCI_ARQCTL		OHCI_ARQOFF
+#define OHCI_ARQCTLCLR		(OHCI_ARQOFF + 4)
+#define OHCI_ARQCMD		(OHCI_ARQOFF + 0xc)
+#define OHCI_ARQMATCH		(OHCI_ARQOFF + 0x10)
+
+#define OHCI_ARSOFF		0x1e0
+#define OHCI_ARSCTL		OHCI_ARSOFF
+#define OHCI_ARSCTLCLR		(OHCI_ARSOFF + 4)
+#define OHCI_ARSCMD		(OHCI_ARSOFF + 0xc)
+#define OHCI_ARSMATCH		(OHCI_ARSOFF + 0x10)
+
+#define OHCI_ITOFF(CH)		(0x200 + 0x10 * (CH))
+#define OHCI_ITCTL(CH)		(OHCI_ITOFF(CH))
+#define OHCI_ITCTLCLR(CH)	(OHCI_ITOFF(CH) + 4)
+#define OHCI_ITCMD(CH)		(OHCI_ITOFF(CH) + 0xc)
+
+#define OHCI_IROFF(CH)		(0x400 + 0x20 * (CH))
+#define OHCI_IRCTL(CH)		(OHCI_IROFF(CH))
+#define OHCI_IRCTLCLR(CH)	(OHCI_IROFF(CH) + 4)
+#define OHCI_IRCMD(CH)		(OHCI_IROFF(CH) + 0xc)
+#define OHCI_IRMATCH(CH)	(OHCI_IROFF(CH) + 0x10)
diff --git a/sys/boot/i386/libfirewire/fwohcireg.h b/sys/boot/i386/libfirewire/fwohcireg.h
new file mode 100644
index 000000000000..27786e8b9813
--- /dev/null
+++ b/sys/boot/i386/libfirewire/fwohcireg.h
@@ -0,0 +1,369 @@
+/*
+ * Copyright (c) 2003 Hidetoshi Shimokawa
+ * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the acknowledgement as bellow:
+ *
+ *    This product includes software developed by K. Kobayashi and H. Shimokawa
+ *
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * $FreeBSD$
+ *
+ */
+#define		PCI_CBMEM		PCIR_BAR(0)
+
+#define		FW_VENDORID_NATSEMI	0x100B
+#define		FW_VENDORID_NEC		0x1033
+#define		FW_VENDORID_SIS		0x1039
+#define		FW_VENDORID_TI		0x104c
+#define		FW_VENDORID_SONY	0x104d
+#define		FW_VENDORID_VIA		0x1106
+#define		FW_VENDORID_RICOH	0x1180
+#define		FW_VENDORID_APPLE	0x106b
+#define		FW_VENDORID_LUCENT	0x11c1
+#define		FW_VENDORID_INTEL	0x8086
+#define		FW_VENDORID_ADAPTEC	0x9004
+
+#define		FW_DEVICE_CS4210	(0x000f << 16)
+#define		FW_DEVICE_UPD861	(0x0063 << 16)
+#define		FW_DEVICE_UPD871	(0x00ce << 16)
+#define		FW_DEVICE_UPD72870	(0x00cd << 16)
+#define		FW_DEVICE_UPD72873	(0x00e7 << 16)
+#define		FW_DEVICE_UPD72874	(0x00f2 << 16)
+#define		FW_DEVICE_TITSB22	(0x8009 << 16)
+#define		FW_DEVICE_TITSB23	(0x8019 << 16)
+#define		FW_DEVICE_TITSB26	(0x8020 << 16)
+#define		FW_DEVICE_TITSB43	(0x8021 << 16)
+#define		FW_DEVICE_TITSB43A	(0x8023 << 16)
+#define		FW_DEVICE_TITSB43AB23	(0x8024 << 16)
+#define		FW_DEVICE_TITSB82AA2	(0x8025 << 16)
+#define		FW_DEVICE_TITSB43AB21	(0x8026 << 16)
+#define		FW_DEVICE_TIPCI4410A	(0x8017 << 16)
+#define		FW_DEVICE_TIPCI4450	(0x8011 << 16)
+#define		FW_DEVICE_TIPCI4451	(0x8027 << 16)
+#define		FW_DEVICE_CXD1947	(0x8009 << 16)
+#define		FW_DEVICE_CXD3222	(0x8039 << 16)
+#define		FW_DEVICE_VT6306	(0x3044 << 16)
+#define		FW_DEVICE_R5C551	(0x0551 << 16)
+#define		FW_DEVICE_R5C552	(0x0552 << 16)
+#define		FW_DEVICE_PANGEA	(0x0030 << 16)
+#define		FW_DEVICE_UNINORTH	(0x0031 << 16)
+#define		FW_DEVICE_AIC5800	(0x5800 << 16)
+#define		FW_DEVICE_FW322		(0x5811 << 16)
+#define		FW_DEVICE_7007		(0x7007 << 16)
+#define		FW_DEVICE_82372FB	(0x7605 << 16)
+
+#define PCI_INTERFACE_OHCI	0x10
+
+#define FW_OHCI_BASE_REG	0x10
+
+#define		OHCI_DMA_ITCH		0x20
+#define		OHCI_DMA_IRCH		0x20
+
+#define		OHCI_MAX_DMA_CH		(0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH)
+
+
+typedef uint32_t 	fwohcireg_t;
+
+/* for PCI */
+#if BYTE_ORDER == BIG_ENDIAN
+#define FWOHCI_DMA_WRITE(x, y)	((x) = htole32(y))
+#define FWOHCI_DMA_READ(x)	le32toh(x)
+#define FWOHCI_DMA_SET(x, y)	((x) |= htole32(y))
+#define FWOHCI_DMA_CLEAR(x, y)	((x) &= htole32(~(y)))
+#else
+#define FWOHCI_DMA_WRITE(x, y)	((x) = (y))
+#define FWOHCI_DMA_READ(x)	(x)
+#define FWOHCI_DMA_SET(x, y)	((x) |= (y))
+#define FWOHCI_DMA_CLEAR(x, y)	((x) &= ~(y))
+#endif
+
+struct fwohcidb {
+	union {
+		struct {
+			uint32_t cmd;
+			uint32_t addr;
+			uint32_t depend;
+			uint32_t res;
+		} desc;
+		uint32_t immed[4];
+	} db;
+#define OHCI_STATUS_SHIFT	16
+#define OHCI_COUNT_MASK		0xffff
+#define OHCI_OUTPUT_MORE	(0 << 28)
+#define OHCI_OUTPUT_LAST	(1 << 28)
+#define OHCI_INPUT_MORE		(2 << 28)
+#define OHCI_INPUT_LAST		(3 << 28)
+#define OHCI_STORE_QUAD		(4 << 28)
+#define OHCI_LOAD_QUAD		(5 << 28)
+#define OHCI_NOP		(6 << 28)
+#define OHCI_STOP		(7 << 28)
+#define OHCI_STORE		(8 << 28)
+#define OHCI_CMD_MASK		(0xf << 28)
+
+#define	OHCI_UPDATE		(1 << 27)
+
+#define OHCI_KEY_ST0		(0 << 24)
+#define OHCI_KEY_ST1		(1 << 24)
+#define OHCI_KEY_ST2		(2 << 24)
+#define OHCI_KEY_ST3		(3 << 24)
+#define OHCI_KEY_REGS		(5 << 24)
+#define OHCI_KEY_SYS		(6 << 24)
+#define OHCI_KEY_DEVICE		(7 << 24)
+#define OHCI_KEY_MASK		(7 << 24)
+
+#define OHCI_INTERRUPT_NEVER	(0 << 20)
+#define OHCI_INTERRUPT_TRUE	(1 << 20)
+#define OHCI_INTERRUPT_FALSE	(2 << 20)
+#define OHCI_INTERRUPT_ALWAYS	(3 << 20)
+
+#define OHCI_BRANCH_NEVER	(0 << 18)
+#define OHCI_BRANCH_TRUE	(1 << 18)
+#define OHCI_BRANCH_FALSE	(2 << 18)
+#define OHCI_BRANCH_ALWAYS	(3 << 18)
+#define OHCI_BRANCH_MASK	(3 << 18)
+
+#define OHCI_WAIT_NEVER		(0 << 16)
+#define OHCI_WAIT_TRUE		(1 << 16)
+#define OHCI_WAIT_FALSE		(2 << 16)
+#define OHCI_WAIT_ALWAYS	(3 << 16)
+};
+
+#define OHCI_SPD_S100 0x4
+#define OHCI_SPD_S200 0x1
+#define OHCI_SPD_S400 0x2
+
+
+#define FWOHCIEV_NOSTAT 0
+#define FWOHCIEV_LONGP 2
+#define FWOHCIEV_MISSACK 3
+#define FWOHCIEV_UNDRRUN 4
+#define FWOHCIEV_OVRRUN 5
+#define FWOHCIEV_DESCERR 6
+#define FWOHCIEV_DTRDERR 7
+#define FWOHCIEV_DTWRERR 8
+#define FWOHCIEV_BUSRST 9
+#define FWOHCIEV_TIMEOUT 0xa
+#define FWOHCIEV_TCODERR 0xb
+#define FWOHCIEV_UNKNOWN 0xe
+#define FWOHCIEV_FLUSHED 0xf
+#define FWOHCIEV_ACKCOMPL 0x11
+#define FWOHCIEV_ACKPEND 0x12
+#define FWOHCIEV_ACKBSX 0x14
+#define FWOHCIEV_ACKBSA 0x15
+#define FWOHCIEV_ACKBSB 0x16
+#define FWOHCIEV_ACKTARD 0x1b
+#define FWOHCIEV_ACKDERR 0x1d
+#define FWOHCIEV_ACKTERR 0x1e
+
+#define FWOHCIEV_MASK 0x1f
+
+struct ohci_dma{
+	fwohcireg_t	cntl;
+
+#define	OHCI_CNTL_CYCMATCH_S	(0x1 << 31)
+
+#define	OHCI_CNTL_BUFFIL	(0x1 << 31)
+#define	OHCI_CNTL_ISOHDR	(0x1 << 30)
+#define	OHCI_CNTL_CYCMATCH_R	(0x1 << 29)
+#define	OHCI_CNTL_MULTICH	(0x1 << 28)
+
+#define	OHCI_CNTL_DMA_RUN	(0x1 << 15)
+#define	OHCI_CNTL_DMA_WAKE	(0x1 << 12)
+#define	OHCI_CNTL_DMA_DEAD	(0x1 << 11)
+#define	OHCI_CNTL_DMA_ACTIVE	(0x1 << 10)
+#define	OHCI_CNTL_DMA_BT	(0x1 << 8)
+#define	OHCI_CNTL_DMA_BAD	(0x1 << 7)
+#define	OHCI_CNTL_DMA_STAT	(0xff)
+
+	fwohcireg_t	cntl_clr;
+	fwohcireg_t	dummy0;
+	fwohcireg_t	cmd;
+	fwohcireg_t	match;
+	fwohcireg_t	dummy1;
+	fwohcireg_t	dummy2;
+	fwohcireg_t	dummy3;
+};
+
+struct ohci_itdma{
+	fwohcireg_t	cntl;
+	fwohcireg_t	cntl_clr;
+	fwohcireg_t	dummy0;
+	fwohcireg_t	cmd;
+};
+
+struct ohci_registers {
+	fwohcireg_t	ver;		/* Version No. 0x0 */
+	fwohcireg_t	guid;		/* GUID_ROM No. 0x4 */
+	fwohcireg_t	retry;		/* AT retries 0x8 */
+#define FWOHCI_RETRY	0x8
+	fwohcireg_t	csr_data;	/* CSR data   0xc */
+	fwohcireg_t	csr_cmp;	/* CSR compare 0x10 */
+	fwohcireg_t	csr_cntl;	/* CSR compare 0x14 */
+	fwohcireg_t	rom_hdr;	/* config ROM ptr. 0x18 */
+	fwohcireg_t	bus_id;		/* BUS_ID 0x1c */
+	fwohcireg_t	bus_opt;	/* BUS option 0x20 */
+#define	FWOHCIGUID_H	0x24
+#define	FWOHCIGUID_L	0x28
+	fwohcireg_t	guid_hi;	/* GUID hi 0x24 */
+	fwohcireg_t	guid_lo;	/* GUID lo 0x28 */
+	fwohcireg_t	dummy0[2];	/* dummy 0x2c-0x30 */
+	fwohcireg_t	config_rom;	/* config ROM map 0x34 */
+	fwohcireg_t	post_wr_lo;	/* post write addr lo 0x38 */
+	fwohcireg_t	post_wr_hi;	/* post write addr hi 0x3c */
+	fwohcireg_t	vender;		/* vender ID 0x40 */
+	fwohcireg_t	dummy1[3];	/* dummy 0x44-0x4c */
+	fwohcireg_t	hcc_cntl_set;	/* HCC control set 0x50 */
+	fwohcireg_t	hcc_cntl_clr;	/* HCC control clr 0x54 */
+#define	OHCI_HCC_BIBIV	(1 << 31)	/* BIBimage Valid */
+#define	OHCI_HCC_BIGEND	(1 << 30)	/* noByteSwapData */
+#define	OHCI_HCC_PRPHY	(1 << 23)	/* programPhyEnable */
+#define	OHCI_HCC_PHYEN	(1 << 22)	/* aPhyEnhanceEnable */
+#define	OHCI_HCC_LPS	(1 << 19)	/* LPS */
+#define	OHCI_HCC_POSTWR	(1 << 18)	/* postedWriteEnable */
+#define	OHCI_HCC_LINKEN	(1 << 17)	/* linkEnable */
+#define	OHCI_HCC_RESET	(1 << 16)	/* softReset */
+	fwohcireg_t	dummy2[2];	/* dummy 0x58-0x5c */
+	fwohcireg_t	dummy3[1];	/* dummy 0x60 */
+	fwohcireg_t	sid_buf;	/* self id buffer 0x64 */
+	fwohcireg_t	sid_cnt;	/* self id count 0x68 */
+	fwohcireg_t	dummy4[1];	/* dummy 0x6c */
+	fwohcireg_t	ir_mask_hi_set;	/* ir mask hi set 0x70 */
+	fwohcireg_t	ir_mask_hi_clr;	/* ir mask hi set 0x74 */
+	fwohcireg_t	ir_mask_lo_set;	/* ir mask hi set 0x78 */
+	fwohcireg_t	ir_mask_lo_clr;	/* ir mask hi set 0x7c */
+#define	FWOHCI_INTSTAT		0x80
+#define	FWOHCI_INTSTATCLR	0x84
+#define	FWOHCI_INTMASK		0x88
+#define	FWOHCI_INTMASKCLR	0x8c
+	fwohcireg_t	int_stat;   /*       0x80 */
+	fwohcireg_t	int_clear;  /*       0x84 */
+	fwohcireg_t	int_mask;   /*       0x88 */
+	fwohcireg_t	int_mask_clear;   /*       0x8c */
+	fwohcireg_t	it_int_stat;   /*       0x90 */
+	fwohcireg_t	it_int_clear;  /*       0x94 */
+	fwohcireg_t	it_int_mask;   /*       0x98 */
+	fwohcireg_t	it_mask_clear;   /*       0x9c */
+	fwohcireg_t	ir_int_stat;   /*       0xa0 */
+	fwohcireg_t	ir_int_clear;  /*       0xa4 */
+	fwohcireg_t	ir_int_mask;   /*       0xa8 */
+	fwohcireg_t	ir_mask_clear;   /*       0xac */
+	fwohcireg_t	dummy5[11];	/* dummy 0xb0-d8 */
+	fwohcireg_t	fairness;   /* fairness control      0xdc */
+	fwohcireg_t	link_cntl;		/* Chip control 0xe0*/
+	fwohcireg_t	link_cntl_clr;	/* Chip control clear 0xe4*/
+#define FWOHCI_NODEID	0xe8
+	fwohcireg_t	node;		/* Node ID 0xe8 */
+#define	OHCI_NODE_VALID	(1 << 31)
+#define	OHCI_NODE_ROOT	(1 << 30)
+
+#define	OHCI_ASYSRCBUS	1
+
+	fwohcireg_t	phy_access;	/* PHY cntl 0xec */
+#define	PHYDEV_RDDONE		(1<<31)
+#define	PHYDEV_RDCMD		(1<<15)
+#define	PHYDEV_WRCMD		(1<<14)
+#define	PHYDEV_REGADDR		8
+#define	PHYDEV_WRDATA		0
+#define	PHYDEV_RDADDR		24
+#define	PHYDEV_RDDATA		16
+
+	fwohcireg_t	cycle_timer;	/* Cycle Timer 0xf0 */
+	fwohcireg_t	dummy6[3];	/* dummy 0xf4-fc */
+	fwohcireg_t	areq_hi;	/* Async req. filter hi 0x100 */
+	fwohcireg_t	areq_hi_clr;	/* Async req. filter hi 0x104 */
+	fwohcireg_t	areq_lo;	/* Async req. filter lo 0x108 */
+	fwohcireg_t	areq_lo_clr;	/* Async req. filter lo 0x10c */
+	fwohcireg_t	preq_hi;	/* Async req. filter hi 0x110 */
+	fwohcireg_t	preq_hi_clr;	/* Async req. filter hi 0x114 */
+	fwohcireg_t	preq_lo;	/* Async req. filter lo 0x118 */
+	fwohcireg_t	preq_lo_clr;	/* Async req. filter lo 0x11c */
+
+	fwohcireg_t	pys_upper;	/* Physical Upper bound 0x120 */
+
+	fwohcireg_t	dummy7[23];	/* dummy 0x124-0x17c */
+	
+	/*       0x180, 0x184, 0x188, 0x18c */
+	/*       0x190, 0x194, 0x198, 0x19c */
+	/*       0x1a0, 0x1a4, 0x1a8, 0x1ac */
+	/*       0x1b0, 0x1b4, 0x1b8, 0x1bc */
+	/*       0x1c0, 0x1c4, 0x1c8, 0x1cc */
+	/*       0x1d0, 0x1d4, 0x1d8, 0x1dc */
+	/*       0x1e0, 0x1e4, 0x1e8, 0x1ec */
+	/*       0x1f0, 0x1f4, 0x1f8, 0x1fc */
+	struct ohci_dma dma_ch[0x4];
+
+	/*       0x200, 0x204, 0x208, 0x20c */
+	/*       0x210, 0x204, 0x208, 0x20c */
+	struct ohci_itdma dma_itch[0x20];
+
+	/*       0x400, 0x404, 0x408, 0x40c */
+	/*       0x410, 0x404, 0x408, 0x40c */
+	struct ohci_dma dma_irch[0x20];
+};
+
+#define	OHCI_CNTL_CYCSRC	(0x1 << 22)
+#define	OHCI_CNTL_CYCMTR	(0x1 << 21)
+#define	OHCI_CNTL_CYCTIMER	(0x1 << 20)
+#define	OHCI_CNTL_PHYPKT	(0x1 << 10)
+#define	OHCI_CNTL_SID		(0x1 << 9)
+
+#define OHCI_INT_DMA_ATRQ	(0x1 << 0)
+#define OHCI_INT_DMA_ATRS	(0x1 << 1)
+#define OHCI_INT_DMA_ARRQ	(0x1 << 2)
+#define OHCI_INT_DMA_ARRS	(0x1 << 3)
+#define OHCI_INT_DMA_PRRQ	(0x1 << 4)
+#define OHCI_INT_DMA_PRRS	(0x1 << 5)
+#define OHCI_INT_DMA_IT	(0x1 << 6)
+#define OHCI_INT_DMA_IR	(0x1 << 7)
+#define OHCI_INT_PW_ERR	(0x1 << 8)
+#define OHCI_INT_LR_ERR	(0x1 << 9)
+
+#define OHCI_INT_PHY_SID	(0x1 << 16)
+#define OHCI_INT_PHY_BUS_R	(0x1 << 17)
+
+#define OHCI_INT_REG_FAIL	(0x1 << 18)
+
+#define OHCI_INT_PHY_INT	(0x1 << 19)
+#define OHCI_INT_CYC_START	(0x1 << 20)
+#define OHCI_INT_CYC_64SECOND	(0x1 << 21)
+#define OHCI_INT_CYC_LOST	(0x1 << 22)
+#define OHCI_INT_CYC_ERR	(0x1 << 23)
+
+#define OHCI_INT_ERR		(0x1 << 24)
+#define OHCI_INT_CYC_LONG	(0x1 << 25)
+#define OHCI_INT_PHY_REG	(0x1 << 26)
+
+#define OHCI_INT_EN		(0x1 << 31)
+
+#define IP_CHANNELS             0x0234
+#define FWOHCI_MAXREC		2048
+
+#define	OHCI_ISORA		0x02
+#define	OHCI_ISORB		0x04
+
+#define FWOHCITCODE_PHY		0xe
diff --git a/sys/boot/i386/loader/Makefile b/sys/boot/i386/loader/Makefile
index ce9b2c1084af..fb8cc835a315 100644
--- a/sys/boot/i386/loader/Makefile
+++ b/sys/boot/i386/loader/Makefile
@@ -9,6 +9,12 @@ NEWVERSWHAT=	"bootstrap loader" i386
 # architecture-specific loader code
 SRCS=		main.c conf.c vers.c
 
+# Put LOADER_FIREWIRE_SUPPORT=yes in /etc/make.conf for FireWire/dcons support
+.if defined(LOADER_FIREWIRE_SUPPORT)
+CFLAGS+=	-DLOADER_FIREWIRE_SUPPORT
+LIBFIREWIRE=	${.OBJDIR}/../libfirewire/libfirewire.a
+.endif
+
 # Enable PXE TFTP or NFS support, not both.
 .if defined(LOADER_TFTP_SUPPORT)
 CFLAGS+=	-DLOADER_TFTP_SUPPORT
@@ -90,8 +96,8 @@ FILES+=	loader.rc
 # XXX crt0.o needs to be first for pxeboot(8) to work
 OBJS=	${BTXCRT} 
 
-DPADD=	${LIBFICL} ${LIBI386} ${LIBSTAND}
-LDADD=	${LIBFICL} ${LIBI386} -lstand
+DPADD=	${LIBFICL} ${LIBFIREWIRE} ${LIBI386} ${LIBSTAND}
+LDADD=	${LIBFICL} ${LIBFIREWIRE} ${LIBI386} -lstand
 
 .include <bsd.prog.mk>
 
diff --git a/sys/boot/i386/loader/conf.c b/sys/boot/i386/loader/conf.c
index 1d8bd047f9e0..245f960ed210 100644
--- a/sys/boot/i386/loader/conf.c
+++ b/sys/boot/i386/loader/conf.c
@@ -46,6 +46,10 @@ __FBSDID("$FreeBSD$");
 #error "Cannot have both tftp and nfs support yet."
 #endif
 
+#if defined(LOADER_FIREWIRE_SUPPORT)
+extern struct devsw fwohci;
+#endif
+
 /* Exported for libstand */
 struct devsw *devsw[] = {
     &bioscd,
@@ -53,6 +57,9 @@ struct devsw *devsw[] = {
 #if defined(LOADER_NFS_SUPPORT) || defined(LOADER_TFTP_SUPPORT)
     &pxedisk,
 #endif
+#if defined(LOADER_FIREWIRE_SUPPORT)
+    &fwohci,
+#endif
     NULL
 };
 
@@ -103,11 +110,17 @@ struct file_format *file_formats[] = {
  */
 extern struct console vidconsole;
 extern struct console comconsole;
+#if defined(LOADER_FIREWIRE_SUPPORT)
+extern struct console dconsole;
+#endif
 extern struct console nullconsole;
 
 struct console *consoles[] = {
     &vidconsole,
     &comconsole,
+#if defined(LOADER_FIREWIRE_SUPPORT)
+    &dconsole,
+#endif
     &nullconsole,
     NULL
 };
diff --git a/sys/boot/i386/loader/main.c b/sys/boot/i386/loader/main.c
index 3838f10d3b94..0c0046ff4726 100644
--- a/sys/boot/i386/loader/main.c
+++ b/sys/boot/i386/loader/main.c
@@ -91,7 +91,7 @@ main(void)
      */
     bios_getmem();
 
-#ifdef LOADER_BZIP2_SUPPORT
+#if defined(LOADER_BZIP2_SUPPORT) || defined(LOADER_FIREWIRE_SUPPORT)
     heap_top = PTOV(memtop_copyin);
     memtop_copyin -= 0x300000;
     heap_bottom = PTOV(memtop_copyin);