2 files changed, 353 insertions, 17 deletions

diff --git a/sys/dev/ata/ata-chipset.c b/sys/dev/ata/ata-chipset.c
index b9f5379c9408..838d5e1b6321 100644
--- a/sys/dev/ata/ata-chipset.c
+++ b/sys/dev/ata/ata-chipset.c
@@ -159,6 +159,13 @@ static int ata_sii_allocate(device_t dev);
 static int ata_sii_status(device_t dev);
 static void ata_sii_reset(device_t dev);
 static void ata_sii_setmode(device_t dev, int mode);
+static int ata_siiprb_allocate(device_t dev);
+static int ata_siiprb_status(device_t dev);
+static int ata_siiprb_begin_transaction(struct ata_request *request);
+static int ata_siiprb_end_transaction(struct ata_request *request);
+static void ata_siiprb_reset(device_t dev);
+static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
+static void ata_siiprb_dmainit(device_t dev);
 static int ata_sis_chipinit(device_t dev);
 static int ata_sis_allocate(device_t dev);
 static void ata_sis_reset(device_t dev);
@@ -2976,20 +2983,16 @@ ata_nvidia_status(device_t dev)
     int shift = ch->unit << (ctlr->chip->cfg2 & NVQ ? 4 : 2);
     u_int32_t istatus = ATA_INL(ctlr->r_res2, offset);
 
-    /* do we have any device action ? */
-    if (istatus & (0x0f << shift)) {
-
-	/* clear interrupt(s) */
-	ATA_OUTB(ctlr->r_res2, offset,
-		 (0x0f << shift) | (ctlr->chip->cfg2 & NVQ ? 0x00f000f0 : 0));
-
-	/* do we have any PHY events ? */
+    /* do we have any PHY events ? */
+    if (istatus & (0x0c << shift))
 	ata_sata_phy_check_events(dev);
 
-	/* do we have any device action ? */
-	return (istatus & (0x01 << shift));
-    }
-    return 0;
+    /* clear interrupt(s) */
+    ATA_OUTB(ctlr->r_res2, offset,
+	     (0x0f << shift) | (ctlr->chip->cfg2 & NVQ ? 0x00f000f0 : 0));
+
+    /* do we have any device action ? */
+    return (istatus & (0x01 << shift));
 }
 
 static void
@@ -4165,6 +4168,8 @@ ata_sii_ident(device_t dev)
      { ATA_SII3512,   0x00, SIIMEMIO, SIIBUG,    ATA_SA150, "SiI 3512" },
      { ATA_SII3112,   0x00, SIIMEMIO, SIIBUG,    ATA_SA150, "SiI 3112" },
      { ATA_SII3112_1, 0x00, SIIMEMIO, SIIBUG,    ATA_SA150, "SiI 3112" },
+     { ATA_SII3124,   0x00, SIIPRBIO, SII4CH,    ATA_SA300, "SiI 3124" },
+     { ATA_SII3132,   0x00, SIIPRBIO, 0,         ATA_SA300, "SiI 3132" },
      { ATA_SII0680,   0x00, SIIMEMIO, SIISETCLK, ATA_UDMA6, "SiI 0680" },
      { ATA_CMD649,    0x00, 0,        SIIINTR,   ATA_UDMA5, "CMD 649" },
      { ATA_CMD648,    0x00, 0,        SIIINTR,   ATA_UDMA4, "CMD 648" },
@@ -4192,6 +4197,36 @@ ata_sii_chipinit(device_t dev)
 	return ENXIO;
 
     switch (ctlr->chip->cfg1) {
+    case SIIPRBIO:
+	ctlr->r_type1 = SYS_RES_MEMORY;
+	ctlr->r_rid1 = PCIR_BAR(0);
+	if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
+						    &ctlr->r_rid1, RF_ACTIVE)))
+	    return ENXIO;
+
+	ctlr->r_rid2 = PCIR_BAR(2);
+	ctlr->r_type2 = SYS_RES_MEMORY;
+	if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
+						    &ctlr->r_rid2, RF_ACTIVE))){
+	    bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
+	    return ENXIO;
+	}
+	ctlr->allocate = ata_siiprb_allocate;
+	ctlr->reset = ata_siiprb_reset;
+	ctlr->dmainit = ata_siiprb_dmainit;
+	ctlr->setmode = ata_sata_setmode;
+	ctlr->channels = (ctlr->chip->cfg2 == SII4CH) ? 4 : 2;
+
+	/* reset controller */
+	ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
+	DELAY(10000);
+	ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
+
+	/* enable PCI interrupt */
+	pci_write_config(dev, PCIR_COMMAND,
+			 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
+	break;
+
     case SIIMEMIO:
 	ctlr->r_type2 = SYS_RES_MEMORY;
 	ctlr->r_rid2 = PCIR_BAR(5);
@@ -4388,13 +4423,10 @@ ata_sii_status(device_t dev)
     int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
     int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
 
-    /* check for PHY related interrupts on SATA capable HW */
+    /* do we have any PHY events ? */
     if (ctlr->chip->max_dma >= ATA_SA150 &&
-	(ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) {
-	
-	/* do we have any PHY events ? */
+	(ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
 	ata_sata_phy_check_events(dev);
-    }
 
     if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
 	return ata_pci_status(dev);
@@ -4475,6 +4507,307 @@ ata_sii_setmode(device_t dev, int mode)
 }
 
 
+struct ata_siiprb_dma_prdentry {
+    u_int64_t addr;
+    u_int32_t count;
+    u_int32_t control;
+} __packed;
+
+struct ata_siiprb_ata_command {
+    u_int32_t reserved0;
+    struct ata_siiprb_dma_prdentry prd[126];
+} __packed;
+
+struct ata_siiprb_atapi_command {
+    u_int8_t cdb[16];
+    struct ata_siiprb_dma_prdentry prd[125];
+} __packed;
+
+struct ata_siiprb_command {
+    u_int16_t control;
+    u_int16_t protocol_override;
+    u_int32_t transfer_count;
+    u_int8_t fis[20];
+    union {
+	struct ata_siiprb_ata_command ata;
+	struct ata_siiprb_atapi_command atapi;
+    } u;
+} __packed;
+
+static int
+ata_siiprb_allocate(device_t dev)
+{
+    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
+    struct ata_channel *ch = device_get_softc(dev);
+    int offset = ch->unit * 0x2000;
+
+    /* set the SATA resources */
+    ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
+    ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
+    ch->r_io[ATA_SERROR].res = ctlr->r_res2;
+    ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
+    ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
+    ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
+    ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
+    ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
+   
+    ch->hw.begin_transaction = ata_siiprb_begin_transaction;
+    ch->hw.end_transaction = ata_siiprb_end_transaction;
+    ch->hw.status = ata_siiprb_status;
+    ch->hw.command = NULL;	/* not used here */
+    return 0;
+}
+
+static int
+ata_siiprb_status(device_t dev)
+{
+    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
+    struct ata_channel *ch = device_get_softc(dev);
+    int offset = ch->unit * 0x2000;
+
+    if ((ATA_INL(ctlr->r_res1, 0x0044) & (1 << ch->unit))) {
+	u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
+
+	/* do we have any PHY events ? */
+	ata_sata_phy_check_events(dev);
+
+	/* clear interrupt(s) */
+	ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
+
+	/* do we have any device action ? */
+	return (istatus & 0x00000001);
+    }
+    return 0;
+}
+
+static int
+ata_siiprb_begin_transaction(struct ata_request *request)
+{
+    struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
+    struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
+    struct ata_siiprb_command *prb;
+    int offset = ch->unit * 0x2000;
+    u_int64_t prb_bus;
+    int tag = 0, dummy;
+
+    /* check for 48 bit access and convert if needed */
+    ata_modify_if_48bit(request);
+
+    /* get a piece of the workspace for this request */
+    prb = (struct ata_siiprb_command *)
+	(ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
+
+    /* set basic prd options ata/atapi etc etc */
+    bzero(prb, sizeof(struct ata_siiprb_command));
+
+    /* setup the FIS for this request */
+    if (!ata_request2fis_h2d(request, &prb->fis[0])) {
+        device_printf(request->dev, "setting up SATA FIS failed\n");
+        request->result = EIO;
+        return ATA_OP_FINISHED;
+    }
+
+    /* if request moves data setup and load SG list */
+    if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
+	struct ata_siiprb_dma_prdentry *prd;
+
+	if (request->flags & ATA_R_ATAPI)
+	    prd = &prb->u.atapi.prd[0];
+	else
+	    prd = &prb->u.ata.prd[0];
+	if (ch->dma->load(ch->dev, request->data, request->bytecount,
+			  request->flags & ATA_R_READ, prd, &dummy)) {
+	    device_printf(request->dev, "setting up DMA failed\n");
+	    request->result = EIO;
+	    return ATA_OP_FINISHED;
+	}
+    }
+
+    /* activate the prb */
+    prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
+    ATA_OUTL(ctlr->r_res2,
+	     0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
+    ATA_OUTL(ctlr->r_res2,
+	     0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
+
+    /* start the timeout */
+    callout_reset(&request->callout, request->timeout * hz,
+                  (timeout_t*)ata_timeout, request);
+    return ATA_OP_CONTINUES;
+}
+
+static int
+ata_siiprb_end_transaction(struct ata_request *request)
+{
+    struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
+    struct ata_channel *ch = device_get_softc(device_get_parent(request->dev));
+    struct ata_siiprb_command *prb;
+    int offset = ch->unit * 0x2000;
+    int error, tag = 0;
+
+    /* kill the timeout */
+    callout_stop(&request->callout);
+    
+    prb = (struct ata_siiprb_command *)
+	((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
+
+    /* if error status get details */
+    request->status = prb->fis[2];
+    if (request->status & ATA_S_ERROR)  
+	request->error = prb->fis[3];
+
+    /* update progress */
+    if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT))
+	request->donecount = prb->transfer_count;
+
+    /* any controller errors flagged ? */
+    if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
+	printf("ata_siiprb_end_transaction %s error=%08x\n",
+	       ata_cmd2str(request), error);
+    }
+
+    /* release SG list etc */
+    ch->dma->unload(ch->dev);
+
+    return ATA_OP_FINISHED;
+}
+
+static void
+ata_siiprb_reset(device_t dev)
+{
+    struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
+    struct ata_channel *ch = device_get_softc(dev);
+    int offset = ch->unit * 0x2000;
+    struct ata_siiprb_command *prb;
+    u_int64_t prb_bus;
+    u_int32_t status, signature;
+    int timeout, tag = 0;
+
+    /* reset channel HW */
+    ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
+    DELAY(1000);
+    ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
+    DELAY(10000);
+
+    /* poll for channel ready */
+    for (timeout = 0; timeout < 1000; timeout++) {
+        if ((status = ATA_INL(ctlr->r_res2, 0x1000 + offset)) & 0x00040000)
+            break;
+        DELAY(1000);
+    }
+    if (timeout >= 1000) {
+	device_printf(ch->dev, "channel HW reset timeout reset failure\n");
+	ch->devices = 0;
+	goto finish;
+    }
+    if (bootverbose)
+	device_printf(ch->dev, "channel HW reset time=%dms\n", timeout * 1);
+
+    /* reset phy */
+    if (!ata_sata_phy_reset(dev)) {
+	if (bootverbose)
+	    device_printf(ch->dev, "phy reset found no device\n");
+	ch->devices = 0;
+	goto finish;
+    }
+
+    /* get a piece of the workspace for a soft reset request */
+    prb = (struct ata_siiprb_command *)
+	(ch->dma->work + (sizeof(struct ata_siiprb_command) * tag));
+    bzero(prb, sizeof(struct ata_siiprb_command));
+    prb->control = htole16(0x0080);
+
+    /* activate the soft reset prb */
+    prb_bus = ch->dma->work_bus + (sizeof(struct ata_siiprb_command) * tag);
+    ATA_OUTL(ctlr->r_res2,
+	     0x1c00 + offset + (tag * sizeof(u_int64_t)), prb_bus);
+    ATA_OUTL(ctlr->r_res2,
+	     0x1c04 + offset + (tag * sizeof(u_int64_t)), prb_bus>>32);
+
+    /* poll for channel ready */
+    for (timeout = 0; timeout < 1000; timeout++) {
+        DELAY(1000);
+        if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
+            break;
+    }
+    if (timeout >= 1000) {
+	device_printf(ch->dev, "reset timeout - no device found\n");
+	ch->devices = 0;
+	goto finish;
+    }
+    if (bootverbose)
+	device_printf(ch->dev, "soft reset exec time=%dms status=%08x\n",
+			timeout, status);
+
+    /* find out whats there */
+    prb = (struct ata_siiprb_command *)
+	((u_int8_t *)rman_get_virtual(ctlr->r_res2) + (tag << 7) + offset);
+    signature =
+	prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
+    if (bootverbose)
+	device_printf(ch->dev, "signature=%08x\n", signature);
+    switch (signature) {
+    case 0xeb140101:
+	ch->devices = ATA_ATAPI_MASTER;
+	device_printf(ch->dev, "SATA ATAPI devices not supported yet\n");
+	ch->devices = 0;
+	break;
+    case 0x96690101:
+	ch->devices = ATA_PORTMULTIPLIER;
+	device_printf(ch->dev, "Portmultipliers not supported yet\n");
+	ch->devices = 0;
+	break;
+    case 0x00000101:
+	ch->devices = ATA_ATA_MASTER;
+	break;
+    default:
+	ch->devices = 0;
+    }
+
+finish:
+    /* clear interrupt(s) */
+    ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
+
+    /* require explicit interrupt ack */
+    ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
+
+    /* 64bit mode */
+    ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
+
+    /* enable interrupts wanted */
+    ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
+}
+
+static void
+ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
+{
+    struct ata_dmasetprd_args *args = xsc;
+    struct ata_siiprb_dma_prdentry *prd = args->dmatab;
+    int i;
+
+    if ((args->error = error))
+	return;
+
+    for (i = 0; i < nsegs; i++) {
+	prd[i].addr = htole64(segs[i].ds_addr);
+	prd[i].count = htole32(segs[i].ds_len);
+    }
+    prd[i - 1].control = htole32(ATA_DMA_EOT);
+}
+
+static void
+ata_siiprb_dmainit(device_t dev)
+{
+    struct ata_channel *ch = device_get_softc(dev);
+
+    ata_dmainit(dev);
+    if (ch->dma) {
+	/* note start and stop are not used here */
+	ch->dma->setprd = ata_siiprb_dmasetprd;
+    }
+}
+
+
 /*
  * Silicon Integrated Systems Corp. (SiS) chipset support functions
  */
diff --git a/sys/dev/ata/ata-pci.h b/sys/dev/ata/ata-pci.h
index 9f9e29b2736f..4784d9c4eb8c 100644
--- a/sys/dev/ata/ata-pci.h
+++ b/sys/dev/ata/ata-pci.h
@@ -281,6 +281,8 @@ struct ata_connect_task {
 #define ATA_SII3512             0x35121095
 #define ATA_SII3112             0x31121095
 #define ATA_SII3112_1           0x02401095
+#define ATA_SII3124		0x31241095
+#define ATA_SII3132		0x31321095
 #define ATA_SII0680             0x06801095
 #define ATA_CMD646              0x06461095
 #define ATA_CMD648              0x06481095
@@ -393,6 +395,7 @@ struct ata_connect_task {
 #define SWKSMIO         3
 
 #define SIIMEMIO        1
+#define SIIPRBIO        2
 #define SIIINTR         0x01
 #define SIISETCLK       0x02
 #define SIIBUG          0x04