diff options
| author | Mateusz Guzik <mjg@FreeBSD.org> | 2020-09-01 21:41:07 +0000 |
|---|---|---|
| committer | Mateusz Guzik <mjg@FreeBSD.org> | 2020-09-01 21:41:07 +0000 |
| commit | 9966c0f962e22d47291b867d16f7845c05d1e9da (patch) | |
| tree | f9371377d08ac684394f07a1d3b8777b9dbd454b /sys/dev/ath/ath_hal | |
| parent | 1529c5096670b9c0d687a30a57f58c08a614ba01 (diff) | |
Notes
Diffstat (limited to 'sys/dev/ath/ath_hal')
67 files changed, 63 insertions, 131 deletions
diff --git a/sys/dev/ath/ath_hal/ah.c b/sys/dev/ath/ath_hal/ah.c index 9d80c4f1e109..e2305d10b452 100644 --- a/sys/dev/ath/ath_hal/ah.c +++ b/sys/dev/ath/ath_hal/ah.c @@ -556,7 +556,6 @@ ath_hal_get_curmode(struct ath_hal *ah, const struct ieee80211_channel *chan) return HAL_MODE_11NG_HT20; } - typedef enum { WIRELESS_MODE_11a = 0, WIRELESS_MODE_TURBO = 1, @@ -971,7 +970,7 @@ ath_hal_getregdump(struct ath_hal *ah, const HAL_REGRANGE *regs, } return (char *) dp - (char *) dstbuf; } - + static void ath_hal_setregs(struct ath_hal *ah, const HAL_REGWRITE *regs, int space) { diff --git a/sys/dev/ath/ath_hal/ah.h b/sys/dev/ath/ath_hal/ah.h index 412754bc7c2e..e39ff2b7d03d 100644 --- a/sys/dev/ath/ath_hal/ah.h +++ b/sys/dev/ath/ath_hal/ah.h @@ -739,7 +739,6 @@ typedef enum { HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ } HAL_HT_EXTPROTSPACING; - typedef enum { HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ @@ -1053,7 +1052,6 @@ typedef enum { HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ } HAL_DFS_DOMAIN; - /* * MFP decryption options for initializing the MAC. */ diff --git a/sys/dev/ath/ath_hal/ah_eeprom_9287.c b/sys/dev/ath/ath_hal/ah_eeprom_9287.c index 974580d26394..42b3ff8b3252 100644 --- a/sys/dev/ath/ath_hal/ah_eeprom_9287.c +++ b/sys/dev/ath/ath_hal/ah_eeprom_9287.c @@ -207,11 +207,11 @@ static uint16_t v9287EepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz) { HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom; - + HALASSERT(is2GHz == AH_TRUE); if (is2GHz != AH_TRUE) return 0; /* XXX ? */ - + HALASSERT(0 <= ix && ix < AR5416_EEPROM_MODAL_SPURS); return ee->ee_base.modalHeader.spurChans[ix].spurChan; } @@ -234,7 +234,6 @@ fbin2freq(uint8_t fbin, HAL_BOOL is2GHz) return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); } - /* * Copy EEPROM Conformance Testing Limits contents * into the allocated space @@ -247,7 +246,7 @@ v9287EepromReadCTLInfo(struct ath_hal *ah, HAL_EEPROM_9287 *ee) { RD_EDGES_POWER *rep = ee->ee_rdEdgesPower; int i, j; - + HALASSERT(AR9287_NUM_CTLS <= sizeof(ee->ee_rdEdgesPower)/NUM_EDGES); for (i = 0; ee->ee_base.ctlIndex[i] != 0 && i < AR9287_NUM_CTLS; i++) { @@ -359,7 +358,7 @@ ath_hal_9287EepromAttach(struct ath_hal *ah) len = ee->ee_base.baseEepHeader.length; } len = AH_MIN(len, sizeof(HAL_EEPROM_9287)) / sizeof(uint16_t); - + /* Apply the checksum, done in native eeprom format */ /* XXX - Need to check to make sure checksum calculation is done * in the correct endian format. Right now, it seems it would diff --git a/sys/dev/ath/ath_hal/ah_eeprom_9287.h b/sys/dev/ath/ath_hal/ah_eeprom_9287.h index 891b4841b153..6d15a6df0204 100644 --- a/sys/dev/ath/ath_hal/ah_eeprom_9287.h +++ b/sys/dev/ath/ath_hal/ah_eeprom_9287.h @@ -166,5 +166,4 @@ typedef struct { typedef struct modal_eep_ar9287_header MODAL_EEP_9287_HEADER; typedef struct base_eep_ar9287_header BASE_EEP_9287_HEADER; - #endif /* __AH_EEPROM_9287_H__ */ diff --git a/sys/dev/ath/ath_hal/ah_eeprom_v14.c b/sys/dev/ath/ath_hal/ah_eeprom_v14.c index 3ae81217327d..d8bb96d56b28 100644 --- a/sys/dev/ath/ath_hal/ah_eeprom_v14.c +++ b/sys/dev/ath/ath_hal/ah_eeprom_v14.c @@ -249,7 +249,7 @@ static uint16_t v14EepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz) { HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; - + HALASSERT(0 <= ix && ix < AR5416_EEPROM_MODAL_SPURS); return ee->ee_base.modalHeader[is2GHz].spurChans[ix].spurChan; } @@ -284,7 +284,7 @@ v14EepromReadCTLInfo(struct ath_hal *ah, HAL_EEPROM_v14 *ee) { RD_EDGES_POWER *rep = ee->ee_rdEdgesPower; int i, j; - + HALASSERT(AR5416_NUM_CTLS <= sizeof(ee->ee_rdEdgesPower)/NUM_EDGES); for (i = 0; ee->ee_base.ctlIndex[i] != 0 && i < AR5416_NUM_CTLS; i++) { @@ -342,7 +342,7 @@ ath_hal_v14EepromAttach(struct ath_hal *ah) uint32_t sum; HALASSERT(ee == AH_NULL); - + /* * Don't check magic if we're supplied with an EEPROM block, * typically this is from Howl but it may also be from later @@ -398,7 +398,7 @@ ath_hal_v14EepromAttach(struct ath_hal *ah) len = ee->ee_base.baseEepHeader.length; } len = AH_MIN(len, sizeof(struct ar5416eeprom)) / sizeof(uint16_t); - + /* Apply the checksum, done in native eeprom format */ /* XXX - Need to check to make sure checksum calculation is done * in the correct endian format. Right now, it seems it would diff --git a/sys/dev/ath/ath_hal/ah_eeprom_v3.c b/sys/dev/ath/ath_hal/ah_eeprom_v3.c index 9d7d011fcd65..2f1b2940de47 100644 --- a/sys/dev/ath/ath_hal/ah_eeprom_v3.c +++ b/sys/dev/ath/ath_hal/ah_eeprom_v3.c @@ -739,14 +739,14 @@ readEepromRawPowerCalInfo2413(struct ath_hal *ah, HAL_EEPROM *ee) int numEEPROMWordsPerChannel; uint32_t off; HAL_BOOL ret = AH_FALSE; - + HALASSERT(ee->ee_version >= AR_EEPROM_VER5_0); HALASSERT(ee->ee_eepMap == 2); - + pCal = ath_hal_malloc(sizeof(EEPROM_DATA_STRUCT_2413)); if (pCal == AH_NULL) goto exit; - + off = ee->ee_eepMap2PowerCalStart; if (ee->ee_Amode) { OS_MEMZERO(pCal, sizeof(EEPROM_DATA_STRUCT_2413)); diff --git a/sys/dev/ath/ath_hal/ah_eeprom_v3.h b/sys/dev/ath/ath_hal/ah_eeprom_v3.h index 2ec54713b261..be71a2486fde 100644 --- a/sys/dev/ath/ath_hal/ah_eeprom_v3.h +++ b/sys/dev/ath/ath_hal/ah_eeprom_v3.h @@ -231,7 +231,6 @@ typedef struct cornerCalInfo { #define NUM_TARGET_POWER_LOCATIONS_11B 4 #define NUM_TARGET_POWER_LOCATIONS_11G 6 - typedef struct { uint16_t xpd_gain; uint16_t numPcdacs; diff --git a/sys/dev/ath/ath_hal/ah_eeprom_v4k.c b/sys/dev/ath/ath_hal/ah_eeprom_v4k.c index 69142ded5447..a9d16100d917 100644 --- a/sys/dev/ath/ath_hal/ah_eeprom_v4k.c +++ b/sys/dev/ath/ath_hal/ah_eeprom_v4k.c @@ -200,7 +200,7 @@ static uint16_t v4kEepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz) { HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; - + HALASSERT(0 <= ix && ix < AR5416_EEPROM_MODAL_SPURS); HALASSERT(is2GHz); return ee->ee_base.modalHeader.spurChans[ix].spurChan; @@ -236,7 +236,7 @@ v4kEepromReadCTLInfo(struct ath_hal *ah, HAL_EEPROM_v4k *ee) { RD_EDGES_POWER *rep = ee->ee_rdEdgesPower; int i, j; - + HALASSERT(AR5416_4K_NUM_CTLS <= sizeof(ee->ee_rdEdgesPower)/NUM_EDGES); for (i = 0; ee->ee_base.ctlIndex[i] != 0 && i < AR5416_4K_NUM_CTLS; i++) { @@ -347,7 +347,7 @@ ath_hal_v4kEepromAttach(struct ath_hal *ah) len = ee->ee_base.baseEepHeader.length; } len = AH_MIN(len, sizeof(struct ar5416eeprom_4k)) / sizeof(uint16_t); - + /* Apply the checksum, done in native eeprom format */ /* XXX - Need to check to make sure checksum calculation is done * in the correct endian format. Right now, it seems it would diff --git a/sys/dev/ath/ath_hal/ah_internal.h b/sys/dev/ath/ath_hal/ah_internal.h index 6b584c2454b3..87c67d73ddca 100644 --- a/sys/dev/ath/ath_hal/ah_internal.h +++ b/sys/dev/ath/ath_hal/ah_internal.h @@ -849,7 +849,6 @@ typedef struct { uint16_t ee_data; /* write data */ } HAL_DIAG_EEVAL; - typedef struct { u_int offset; /* reg offset */ uint32_t val; /* reg value */ diff --git a/sys/dev/ath/ath_hal/ah_regdomain.c b/sys/dev/ath/ath_hal/ah_regdomain.c index 2901b6960382..c0ae4a94a4c6 100644 --- a/sys/dev/ath/ath_hal/ah_regdomain.c +++ b/sys/dev/ath/ath_hal/ah_regdomain.c @@ -953,7 +953,6 @@ ath_hal_getctl(struct ath_hal *ah, const struct ieee80211_channel *c) return ctl; } - /* * Update the current dfsDomain setting based on the given * country code. @@ -979,7 +978,6 @@ ath_hal_update_dfsdomain(struct ath_hal *ah) __func__, AH_PRIVATE(ah)->ah_dfsDomain); } - /* * Return the max allowed antenna gain and apply any regulatory * domain specific changes. diff --git a/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h b/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h index 6555147b4e60..5956a804b03a 100644 --- a/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h +++ b/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h @@ -64,7 +64,6 @@ W1(_fg) | W1(_fh) | W1(_fi) } static REG_DOMAIN regDomains[] = { - {.regDmnEnum = DEBUG_REG_DMN, .conformanceTestLimit = FCC, .dfsMask = DFS_FCC3, diff --git a/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_freqbands.h b/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_freqbands.h index c7169113c11b..5475c6508972 100644 --- a/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_freqbands.h +++ b/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_freqbands.h @@ -198,7 +198,6 @@ static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = { #define W2_5825_5825 AFTER(W2_5180_5240) }; - /* * 5GHz Turbo (dynamic & static) tags */ @@ -373,7 +372,7 @@ static REG_DMN_FREQ_BAND regDmn2Ghz11gFreq[] = { #define G3_2412_2462 AFTER(G2_2412_2462) { 2412, 2462, 27, 6, 5, 5, NO_DFS, NO_PSCAN }, #define G4_2412_2462 AFTER(G3_2412_2462) - + { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, #define G1_2432_2442 AFTER(G4_2412_2462) diff --git a/sys/dev/ath/ath_hal/ah_soc.h b/sys/dev/ath/ath_hal/ah_soc.h index 3d77b8234857..e391a2c869e8 100644 --- a/sys/dev/ath/ath_hal/ah_soc.h +++ b/sys/dev/ath/ath_hal/ah_soc.h @@ -62,18 +62,18 @@ struct ar531x_boarddata { #define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */ uint16_t resetConfigGpio; /* Reset factory GPIO pin */ uint16_t sysLedGpio; /* System LED GPIO pin */ - + uint32_t cpuFreq; /* CPU core frequency in Hz */ uint32_t sysFreq; /* System frequency in Hz */ uint32_t cntFreq; /* Calculated C0_COUNT frequency */ - + uint8_t wlan0Mac[6]; uint8_t enet0Mac[6]; uint8_t enet1Mac[6]; - + uint16_t pciId; /* Pseudo PCIID for common code */ uint16_t memCap; /* cap bank1 in MB */ - + /* version 3 */ uint8_t wlan1Mac[6]; /* (ar5212) */ }; diff --git a/sys/dev/ath/ath_hal/ar5210/ar5210_recv.c b/sys/dev/ath/ath_hal/ar5210/ar5210_recv.c index 1077886b7d01..a11e0300721f 100644 --- a/sys/dev/ath/ath_hal/ar5210/ar5210_recv.c +++ b/sys/dev/ath/ath_hal/ar5210/ar5210_recv.c @@ -50,7 +50,6 @@ ar5210SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype) OS_REG_WRITE(ah, AR_RXDP, rxdp); } - /* * Set Receive Enable bits. */ diff --git a/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c b/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c index b5656fb36419..bf1b9683a2cc 100644 --- a/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c +++ b/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c @@ -611,7 +611,6 @@ ar5210SetResetReg(struct ath_hal *ah, uint32_t resetMask, u_int delay) return rt; } - /* * Returns: the pcdac value */ diff --git a/sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c b/sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c index 8d703023edb3..7a8ed460ff80 100644 --- a/sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c +++ b/sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c @@ -163,7 +163,6 @@ ar5211SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, if (k->kv_len <= 104 / NBBY) key4 &= 0xff; - /* * Note: WEP key cache hardware requires that each double-word * pair be written in even/odd order (since the destination is diff --git a/sys/dev/ath/ath_hal/ar5211/ar5211_misc.c b/sys/dev/ath/ath_hal/ar5211/ar5211_misc.c index 4395818ab2bd..ea1327b11a6a 100644 --- a/sys/dev/ath/ath_hal/ar5211/ar5211_misc.c +++ b/sys/dev/ath/ath_hal/ar5211/ar5211_misc.c @@ -708,7 +708,6 @@ ar5211Get11nExtBusy(struct ath_hal *ah) return (0); } - /* * There's no channel survey support for the AR5211. */ diff --git a/sys/dev/ath/ath_hal/ar5211/ar5211_phy.c b/sys/dev/ath/ath_hal/ar5211/ar5211_phy.c index 6507c879ed92..42d9665396a1 100644 --- a/sys/dev/ath/ath_hal/ar5211/ar5211_phy.c +++ b/sys/dev/ath/ath_hal/ar5211/ar5211_phy.c @@ -81,7 +81,6 @@ HAL_RATE_TABLE ar5211_11b_table = { #undef CCK #undef TURBO - const HAL_RATE_TABLE * ar5211GetRateTable(struct ath_hal *ah, u_int mode) { diff --git a/sys/dev/ath/ath_hal/ar5211/ar5211_recv.c b/sys/dev/ath/ath_hal/ar5211/ar5211_recv.c index 09462b546a95..1922f8775d54 100644 --- a/sys/dev/ath/ath_hal/ar5211/ar5211_recv.c +++ b/sys/dev/ath/ath_hal/ar5211/ar5211_recv.c @@ -51,7 +51,6 @@ ar5211SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype) HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp); } - /* * Set Receive Enable bits. */ diff --git a/sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c b/sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c index 4bcb8fd6497a..9b32c4de496e 100644 --- a/sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c +++ b/sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c @@ -193,7 +193,6 @@ setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi) AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask); } - /* * Free a tx DCU/QCU combination. */ @@ -677,7 +676,6 @@ ar5211GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int * return AH_FALSE; } - void ar5211SetTxDescLink(struct ath_hal *ah, void *ds, uint32_t link) { diff --git a/sys/dev/ath/ath_hal/ar5211/ar5211phy.h b/sys/dev/ath/ath_hal/ar5211/ar5211phy.h index c344cdc9b054..9e44b903b085 100644 --- a/sys/dev/ath/ath_hal/ar5211/ar5211phy.h +++ b/sys/dev/ath/ath_hal/ar5211/ar5211phy.h @@ -48,7 +48,6 @@ #define AR_PHY_PLL_CTL_40 0x18 /* 40 MHz */ #define AR_PHY_PLL_CTL_20 0x13 /* 20 MHz half rate 11a for emulation */ - #define AR_PHY_RX_DELAY 0x9914 /* PHY analog_power_on_time, in 100ns increments */ #define AR_PHY_RX_DELAY_M 0x00003FFF /* Mask for delay from active assertion (wake up) */ /* to enable_receiver */ diff --git a/sys/dev/ath/ath_hal/ar5211/ar5211reg.h b/sys/dev/ath/ath_hal/ar5211/ar5211reg.h index ef2fb863d815..3cbdacc972c1 100644 --- a/sys/dev/ath/ath_hal/ar5211/ar5211reg.h +++ b/sys/dev/ath/ath_hal/ar5211/ar5211reg.h @@ -808,7 +808,6 @@ #define AR5211_USEC_RX_LAT_M 0x1F800000 /* Rx latency */ #define AR5211_USEC_RX_LAT_S 23 - #define AR_BEACON_PERIOD 0x0000FFFF /* Beacon period in TU/msec */ #define AR_BEACON_PERIOD_S 0 /* Byte offset of PERIOD start*/ #define AR_BEACON_TIM 0x007F0000 /* Byte offset of TIM start */ diff --git a/sys/dev/ath/ath_hal/ar5212/ar2316.c b/sys/dev/ath/ath_hal/ar5212/ar2316.c index 186e72e9856c..1259c777d99c 100644 --- a/sys/dev/ath/ath_hal/ar5212/ar2316.c +++ b/sys/dev/ath/ath_hal/ar5212/ar2316.c @@ -629,7 +629,7 @@ ar2316GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2316 *data) { uint32_t ii; uint16_t Pmax=0,numVpd; - + for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) { /* work forwards cuase lowest pdGain for highest power */ numVpd = data->pDataPerPDGain[ii].numVpd; @@ -664,7 +664,7 @@ ar2316GetChannelMaxMinPower(struct ath_hal *ah, numChannels = pRawDataset->numChannels; data = pRawDataset->pDataPerChannel; - + /* Make sure the channel is in the range of the TP values * (freq piers) */ diff --git a/sys/dev/ath/ath_hal/ar5212/ar2317.c b/sys/dev/ath/ath_hal/ar5212/ar2317.c index 29a9b369f3a5..814e4318b39d 100644 --- a/sys/dev/ath/ath_hal/ar5212/ar2317.c +++ b/sys/dev/ath/ath_hal/ar5212/ar2317.c @@ -608,7 +608,7 @@ ar2317GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2317 *data) uint32_t ii; uint16_t Pmax=0,numVpd; uint16_t vpdmax; - + for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) { /* work forwards cuase lowest pdGain for highest power */ numVpd = data->pDataPerPDGain[ii].numVpd; @@ -644,7 +644,7 @@ ar2317GetChannelMaxMinPower(struct ath_hal *ah, numChannels = pRawDataset->numChannels; data = pRawDataset->pDataPerChannel; - + /* Make sure the channel is in the range of the TP values * (freq piers) */ diff --git a/sys/dev/ath/ath_hal/ar5212/ar2413.c b/sys/dev/ath/ath_hal/ar5212/ar2413.c index e2a8d0203360..3c1ce6805a2a 100644 --- a/sys/dev/ath/ath_hal/ar5212/ar2413.c +++ b/sys/dev/ath/ath_hal/ar5212/ar2413.c @@ -624,7 +624,7 @@ ar2413GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data) { uint32_t ii; uint16_t Pmax=0,numVpd; - + for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) { /* work forwards cuase lowest pdGain for highest power */ numVpd = data->pDataPerPDGain[ii].numVpd; @@ -659,7 +659,7 @@ ar2413GetChannelMaxMinPower(struct ath_hal *ah, numChannels = pRawDataset->numChannels; data = pRawDataset->pDataPerChannel; - + /* Make sure the channel is in the range of the TP values * (freq piers) */ diff --git a/sys/dev/ath/ath_hal/ar5212/ar2425.c b/sys/dev/ath/ath_hal/ar5212/ar2425.c index 9159ad2370d1..979f45b3619e 100644 --- a/sys/dev/ath/ath_hal/ar5212/ar2425.c +++ b/sys/dev/ath/ath_hal/ar5212/ar2425.c @@ -492,7 +492,6 @@ ar2425getGainBoundariesAndPdadcsForPowers(struct ath_hal *ah, uint16_t channel, HALDEBUG(ah, HAL_DEBUG_RFPARAM, "<==%s\n", __func__); } - /* Same as 2413 set power table */ static HAL_BOOL ar2425SetPowerTable(struct ath_hal *ah, @@ -586,7 +585,7 @@ ar2425GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data) { uint32_t ii; uint16_t Pmax=0,numVpd; - + for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) { /* work forwards cuase lowest pdGain for highest power */ numVpd = data->pDataPerPDGain[ii].numVpd; @@ -622,7 +621,7 @@ ar2425GetChannelMaxMinPower(struct ath_hal *ah, numChannels = pRawDataset->numChannels; data = pRawDataset->pDataPerChannel; - + /* Make sure the channel is in the range of the TP values * (freq piers) */ diff --git a/sys/dev/ath/ath_hal/ar5212/ar5111.c b/sys/dev/ath/ath_hal/ar5212/ar5111.c index 128332266b52..fe8acccd0691 100644 --- a/sys/dev/ath/ath_hal/ar5212/ar5111.c +++ b/sys/dev/ath/ath_hal/ar5212/ar5111.c @@ -336,7 +336,6 @@ ar5111SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan, ar5212ModifyRfBuffer(rfReg, rfWaitS, 5, 19, 0); ar5212ModifyRfBuffer(rfReg, rfWaitI, 5, 24, 0); ar5212ModifyRfBuffer(rfReg, rfMaxTime, 2, 49, 0); - } HAL_INI_WRITE_BANK(ah, ar5212Bank7_5111, rfReg, regWrites); diff --git a/sys/dev/ath/ath_hal/ar5212/ar5112.c b/sys/dev/ath/ath_hal/ar5212/ar5112.c index 1e9e20355677..0c3a6032e5fa 100644 --- a/sys/dev/ath/ath_hal/ar5212/ar5112.c +++ b/sys/dev/ath/ath_hal/ar5212/ar5112.c @@ -281,7 +281,7 @@ ar5112SetRfRegs(struct ath_hal *ah, ar5212ModifyRfBuffer(priv->Bank6Data, ob5GHz, 3, 279, 0); ar5212ModifyRfBuffer(priv->Bank6Data, db5GHz, 3, 282, 0); } - + /* Lower synth voltage for X112 Rev 2.0 only */ if (IS_RADX112_REV2(ah)) { /* Non-Reversed analyg registers - so values are pre-reversed */ @@ -763,7 +763,7 @@ ar5112GetMinPower(struct ath_hal *ah, const EXPN_DATA_PER_CHANNEL_5112 *data) retVal = minPwr - (minPcdac*2); return(retVal); } - + static HAL_BOOL ar5112GetChannelMaxMinPower(struct ath_hal *ah, const struct ieee80211_channel *chan, diff --git a/sys/dev/ath/ath_hal/ar5212/ar5212_ani.c b/sys/dev/ath/ath_hal/ar5212/ar5212_ani.c index 4e2cd683df8c..eb9999e1ca5d 100644 --- a/sys/dev/ath/ath_hal/ar5212/ar5212_ani.c +++ b/sys/dev/ath/ath_hal/ar5212/ar5212_ani.c @@ -225,7 +225,7 @@ ar5212AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param) struct ath_hal_5212 *ahp = AH5212(ah); struct ar5212AniState *aniState = ahp->ah_curani; const struct ar5212AniParams *params = AH_NULL; - + /* * This function may be called before there's a current * channel (eg to disable ANI.) @@ -784,7 +784,7 @@ ar5212AniLowerImmunity(struct ath_hal *ah) struct ath_hal_5212 *ahp = AH5212(ah); struct ar5212AniState *aniState; const struct ar5212AniParams *params; - + HALASSERT(ANI_ENA(ah)); aniState = ahp->ah_curani; diff --git a/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c b/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c index ead62adfce48..b52045baea19 100644 --- a/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c +++ b/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c @@ -27,7 +27,6 @@ #include "ar5212/ar5212reg.h" #include "ar5212/ar5212phy.h" - /* * Checks to see if an interrupt is pending on our NIC * diff --git a/sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c b/sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c index fa6936231952..8daaf250ec0b 100644 --- a/sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c +++ b/sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c @@ -245,7 +245,6 @@ ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry, OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); (void) ar5212SetKeyCacheEntryMac(ah, entry, mac); - /* * Write MIC entry according to new or old key layout. * The MISC_MODE register is assumed already set so diff --git a/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c b/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c index 6450c8d6f426..577e1e7491b3 100644 --- a/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c +++ b/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c @@ -623,7 +623,7 @@ ar5212SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now) * timeouts. This value is in core clocks. */ timeout = ACK_CTS_TIMEOUT_11A + (coverageclass * 3 * clkRate); - + /* * Write the values: slot, eifs, ack/cts timeouts. */ @@ -1194,7 +1194,6 @@ ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) val &= ~ AR_PHY_RADAR_0_ENA; if (IS_5413(ah)) { - if (pe->pe_blockradar == 1) OS_REG_SET_BIT(ah, AR_PHY_RADAR_2, AR_PHY_RADAR_2_BLOCKOFDMWEAK); diff --git a/sys/dev/ath/ath_hal/ar5212/ar5212_phy.c b/sys/dev/ath/ath_hal/ar5212/ar5212_phy.c index 6f9c9dc1744b..ba56477fa506 100644 --- a/sys/dev/ath/ath_hal/ar5212/ar5212_phy.c +++ b/sys/dev/ath/ath_hal/ar5212/ar5212_phy.c @@ -129,7 +129,6 @@ HAL_RATE_TABLE ar5212_11b_table = { }, }; - /* Venice TODO: roundUpRate() is broken when the rate table does not represent rates * in increasing order e.g. 5.5, 11, 6, 9. * An average rate of 6 Mbps will currently map to 11 Mbps. diff --git a/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c b/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c index a5e9ca65d056..12fe41b0c19f 100644 --- a/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c +++ b/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c @@ -692,7 +692,7 @@ done: HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); RESTORE_CCK(ah, chan, isBmode); - + OS_MARK(ah, AH_MARK_RESET_DONE, 0); return AH_TRUE; @@ -1192,7 +1192,6 @@ ar5212MacStop(struct ath_hal *ah) return status; } - /* * Write the given reset bit mask into the reset register */ @@ -1923,7 +1922,6 @@ ar5212SetSpurMitigation(struct ath_hal *ah, #undef CHAN_TO_SPUR } - /* * Delta slope coefficient computation. * Required for OFDM operation. diff --git a/sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c b/sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c index 6b8730b0d063..cebaa989ef8d 100644 --- a/sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c +++ b/sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c @@ -107,7 +107,6 @@ ar5212GetTxQueueProps(struct ath_hal *ah, int q, HAL_TXQ_INFO *qInfo) struct ath_hal_5212 *ahp = AH5212(ah); HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; - if (q >= pCap->halTotalQueues) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n", __func__, q); @@ -346,7 +345,7 @@ ar5212ResetTxQueue(struct ath_hal *ah, u_int q) SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT) | AR_Q_RDYTIMECFG_ENA); } - + OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) | (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); @@ -473,7 +472,7 @@ ar5212ResetTxQueue(struct ath_hal *ah, u_int q) OS_REG_READ(ah, AR_Q0_MISC + 4*q) | AR_Q_MISC_QCU_COMP_EN); } - + /* * Always update the secondary interrupt mask registers - this * could be a new queue getting enabled in a running system or diff --git a/sys/dev/ath/ath_hal/ar5212/ar5212phy.h b/sys/dev/ath/ath_hal/ar5212/ar5212phy.h index a91f2c10ee87..74ccb268fa0d 100644 --- a/sys/dev/ath/ath_hal/ar5212/ar5212phy.h +++ b/sys/dev/ath/ath_hal/ar5212/ar5212phy.h @@ -78,7 +78,6 @@ #define AR_PHY_TSTDAC_CONST_Q_S 9 #define AR_PHY_TSTDAC_CONST_I 0x000001FF - #define AR_PHY_SETTLING 0x9844 #define AR_PHY_SETTLING_AGC 0x0000007F #define AR_PHY_SETTLING_AGC_S 0 diff --git a/sys/dev/ath/ath_hal/ar5212/ar5413.c b/sys/dev/ath/ath_hal/ar5212/ar5413.c index 1d57b9ec7450..1b1817c6c3c4 100644 --- a/sys/dev/ath/ath_hal/ar5212/ar5413.c +++ b/sys/dev/ath/ath_hal/ar5212/ar5413.c @@ -241,7 +241,6 @@ ar5413SetRfRegs(struct ath_hal *ah, } else { ar5212ModifyRfBuffer(priv->Bank6Data, ob5GHz, 3, 247, 0); ar5212ModifyRfBuffer(priv->Bank6Data, db5GHz, 3, 244, 0); - } /* Bank 7 Setup */ @@ -668,7 +667,7 @@ ar5413GetMaxPower(struct ath_hal *ah, const RAW_DATA_PER_CHANNEL_2413 *data) { uint32_t ii; uint16_t Pmax=0,numVpd; - + for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) { /* work forwards cuase lowest pdGain for highest power */ numVpd = data->pDataPerPDGain[ii].numVpd; @@ -705,7 +704,7 @@ ar5413GetChannelMaxMinPower(struct ath_hal *ah, numChannels = pRawDataset->numChannels; data = pRawDataset->pDataPerChannel; - + /* Make sure the channel is in the range of the TP values * (freq piers) */ diff --git a/sys/dev/ath/ath_hal/ar5312/ar5312_eeprom.c b/sys/dev/ath/ath_hal/ar5312/ar5312_eeprom.c index 9b79c36c323f..74a7394665ee 100644 --- a/sys/dev/ath/ath_hal/ar5312/ar5312_eeprom.c +++ b/sys/dev/ath/ath_hal/ar5312/ar5312_eeprom.c @@ -20,7 +20,6 @@ */ #include "opt_ah.h" - #ifdef AH_SUPPORT_AR5312 #include "ah.h" @@ -39,7 +38,7 @@ ar5312EepromRead(struct ath_hal *ah, u_int off, uint16_t *dataIn) int i,offset; const char *eepromAddr = AR5312_RADIOCONFIG(ah); uint8_t *data; - + data = (uint8_t *) dataIn; for (i=0,offset=2*off; i<2; i++,offset++) { data[i] = eepromAddr[offset]; diff --git a/sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c b/sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c index 809904d649b5..84bfd50099c3 100644 --- a/sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c +++ b/sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c @@ -129,5 +129,4 @@ ar5312GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel) (void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO); } - #endif /* AH_SUPPORT_AR5312 */ diff --git a/sys/dev/ath/ath_hal/ar5312/ar5312_interrupts.c b/sys/dev/ath/ath_hal/ar5312/ar5312_interrupts.c index 43cdda719db6..926fcc2863e1 100644 --- a/sys/dev/ath/ath_hal/ar5312/ar5312_interrupts.c +++ b/sys/dev/ath/ath_hal/ar5312/ar5312_interrupts.c @@ -29,7 +29,6 @@ #include "ar5312/ar5312reg.h" #include "ar5312/ar5312phy.h" - /* * Checks to see if an interrupt is pending on our NIC * diff --git a/sys/dev/ath/ath_hal/ar5312/ar5312_reset.c b/sys/dev/ath/ath_hal/ar5312/ar5312_reset.c index ebc12277a736..2daea4007c98 100644 --- a/sys/dev/ath/ath_hal/ar5312/ar5312_reset.c +++ b/sys/dev/ath/ath_hal/ar5312/ar5312_reset.c @@ -271,7 +271,7 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode, /* Set the mute mask to the correct default */ OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F); } - + if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) { /* Clear reg to alllow RX_CLEAR line debug */ OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0); @@ -827,12 +827,10 @@ ar5312MacReset(struct ath_hal *ah, unsigned int RCMask) OS_REG_READ(ah, (AR5315_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5315_RESET)); - } else #endif { - switch(wlanNum) { case 0: resetBB = AR5312_RC_BB0_CRES | AR5312_RC_WBB0_RES; diff --git a/sys/dev/ath/ath_hal/ar5312/ar5312reg.h b/sys/dev/ath/ath_hal/ar5312/ar5312reg.h index 0e78a52dfe9e..34c8aef51ef1 100644 --- a/sys/dev/ath/ath_hal/ar5312/ar5312reg.h +++ b/sys/dev/ath/ath_hal/ar5312/ar5312reg.h @@ -29,7 +29,6 @@ /* Register base addresses for modules which are not wmac modules */ /* 531X has a fixed memory map */ - #define REG_WRITE(_reg,_val) *((volatile uint32_t *)(_reg)) = (_val); #define REG_READ(_reg) *((volatile uint32_t *)(_reg)) /* @@ -129,7 +128,6 @@ #define AR5312_RC_WMAC1_RES 0x00020000 /* Warm reset to WMAC1 */ #define AR5312_RC_WBB1_RES 0x00040000 /* Warm reset to WBB */ - #define AR_RAD2112_SREV_MAJOR 0x40 /* 2112 Major Rev */ enum AR5312PowerMode { diff --git a/sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c b/sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c index 5fe8eec6c225..41a7bd6cfb38 100644 --- a/sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c +++ b/sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c @@ -128,5 +128,4 @@ ar5315GpioSetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel) (void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO); } - #endif /* AH_SUPPORT_2316 || AH_SUPPORT_2317 */ diff --git a/sys/dev/ath/ath_hal/ar5416/ar2133.c b/sys/dev/ath/ath_hal/ar5416/ar2133.c index 96d5792ba99a..1cb5432609d7 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar2133.c +++ b/sys/dev/ath/ath_hal/ar5416/ar2133.c @@ -278,7 +278,7 @@ ar2133SetRfRegs(struct ath_hal *ah, const struct ieee80211_channel *chan, /* Setup Bank 6 Write */ ath_hal_ini_bank_setup(priv->Bank6Data, &AH5416(ah)->ah_ini_bank6, modesIndex); - + /* Only the 5 or 2 GHz OB/DB need to be set for a mode */ if (IEEE80211_IS_CHAN_2GHZ(chan)) { HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: 2ghz: OB_2:%d, DB_2:%d\n", @@ -473,7 +473,6 @@ ar2133GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[]) "NF calibrated [ctl] [chain 1] is %d\n", nf); nfarray[1] = nf; - nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); if (nf & 0x100) nf = 0 - ((nf ^ 0x1ff) + 1); @@ -522,7 +521,7 @@ ar2133RfDetach(struct ath_hal *ah) ath_hal_free(ahp->ah_rfHal); ahp->ah_rfHal = AH_NULL; } - + /* * Allocate memory for analog bank scratch buffers * Scratch Buffer will be reinitialized every reset so no need to zero now diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c b/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c index a10d884aaaf8..340d67f2e52b 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c @@ -223,7 +223,6 @@ ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param) return AH_FALSE; } - switch (cmd) { case HAL_ANI_NOISE_IMMUNITY_LEVEL: { u_int level = param; @@ -727,7 +726,7 @@ ar5416AniLowerImmunity(struct ath_hal *ah) struct ath_hal_5212 *ahp = AH5212(ah); struct ar5212AniState *aniState; const struct ar5212AniParams *params; - + HALASSERT(ANI_ENA(ah)); aniState = ahp->ah_curani; diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c b/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c index 6d8dfd3b8567..369e4b0bb551 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c @@ -721,7 +721,6 @@ ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); OS_REG_WRITE(ah, AR_PHY_TIMING11, new); - /* * ============================================ * pilot mask 1 [31:0] = +6..-26, no 0 bin @@ -893,7 +892,7 @@ ar5416FillCapabilityInfo(struct ath_hal *ah) struct ath_hal_private *ahpriv = AH_PRIVATE(ah); HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; uint16_t val; - + /* Construct wireless mode from EEPROM */ pCap->halWirelessModes = 0; if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c b/sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c index 7de707b3293c..e1b61bb3ccb4 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c @@ -155,7 +155,7 @@ ar5416SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs) uint32_t nextTbtt, nextdtim,beaconintval, dtimperiod; HALASSERT(bs->bs_intval != 0); - + /* NB: no cfp setting since h/w automatically takes care */ OS_REG_WRITE(ah, AR_NEXT_TBTT, TU_TO_USEC(bs->bs_nexttbtt)); diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c b/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c index 106833fe6303..44b436c4f389 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c @@ -196,7 +196,6 @@ ar5416RunInitCals(struct ath_hal *ah, int init_cal_count) } #endif - /* * AGC calibration for the AR5416, AR9130, AR9160, AR9280. */ @@ -623,7 +622,6 @@ ar5416LoadNF(struct ath_hal *ah, const struct ieee80211_channel *chan) h = AH5416(ah)->ah_cal.nfCalHist; HALDEBUG(ah, HAL_DEBUG_NFCAL, "CCA: "); for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) { - /* Don't write to EXT radio CCA registers unless in HT/40 mode */ /* XXX this check should really be cleaner! */ if (i > 2 && !IEEE80211_IS_CHAN_HT40(chan)) @@ -674,7 +672,6 @@ ar5416LoadNF(struct ath_hal *ah, const struct ieee80211_channel *chan) * of next noise floor calibration the baseband does. */ for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) { - /* Don't write to EXT radio CCA registers unless in HT/40 mode */ /* XXX this check should really be cleaner! */ if (i > 2 && !IEEE80211_IS_CHAN_HT40(chan)) @@ -781,7 +778,6 @@ ar5416SanitizeNF(struct ath_hal *ah, int16_t *nf) } } - /* * Read the NF and check it against the noise floor threshold * diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_cal.h b/sys/dev/ath/ath_hal/ar5416/ar5416_cal.h index 5cf1ed0ef108..73a6a87499eb 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_cal.h +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_cal.h @@ -20,7 +20,7 @@ */ #ifndef _ATH_AR5416_CAL_H_ #define _ATH_AR5416_CAL_H_ - + typedef enum { ADC_DC_INIT_CAL = 0x1, ADC_GAIN_CAL = 0x2, diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c b/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c index 1695eda2c5f6..e1d1320d0852 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c @@ -131,7 +131,7 @@ ar5416GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type) return AH_TRUE; #undef N } - + /* * Configure GPIO Input lines */ diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_power.c b/sys/dev/ath/ath_hal/ar5416/ar5416_power.c index bcd5fd9807a8..ac1366fedefa 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_power.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_power.c @@ -114,7 +114,7 @@ static void ar5416SetPowerModeNetworkSleep(struct ath_hal *ah, int setChip) { OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); - + if (setChip) OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); } diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c b/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c index 7501885be6f5..f3d6fcab0d68 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c @@ -386,7 +386,6 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode, AR_PCU_MISC_MODE2_ENABLE_AGGWEP); } - /* * disable seq number generation in hw */ @@ -606,7 +605,7 @@ ar5416InitDMA(struct ath_hal *ah) * Setup receive FIFO threshold to hold off TX activities */ OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); - + /* * reduce the number of usable entries in PCU TXBUF to avoid * wrap around. @@ -645,7 +644,7 @@ ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *chan) /* Activate the PHY (includes baseband activate and synthesizer on) */ OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); - + /* * If the AP starts the calibration before the base band timeout * completes we could get rx_clear false triggering. Add an @@ -1049,7 +1048,6 @@ ar5416WriteTxPowerRateRegisters(struct ath_hal *ah, #undef POW_SM } - /************************************************************** * ar5416SetTransmitPower * @@ -1096,7 +1094,7 @@ ar5416SetTransmitPower(struct ath_hal *ah, if (IS_EEP_MINOR_V2(ah)) { AH5416(ah)->ah_ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; } - + if (!ar5416SetPowerPerRateTable(ah, pEepData, chan, &AH5416(ah)->ah_ratesArray[0], cfgCtl, @@ -1525,7 +1523,7 @@ ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) pll |= SM(0xb, AR_RTC_PLL_DIV); } else pll |= SM(0xb, AR_RTC_PLL_DIV); - + OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); /* TODO: @@ -1657,7 +1655,6 @@ ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) ar5416SetDefGainValues(ah, pModal, eep, txRxAttenLocal, regChainOffset, i); - } if (AR_SREV_MERLIN_10_OR_LATER(ah)) { @@ -2804,7 +2801,6 @@ ar5416MarkPhyInactive(struct ath_hal *ah) #define AR5416_HALF_RATE_USEC_44 21 /* ((44 / 2) - 1 ) */ #define AR5416_QUARTER_RATE_USEC_44 10 /* ((44 / 4) - 1 ) */ - /* XXX What should these be for 40/44MHz clocks (and half/quarter) ? */ #define AR5416_RX_NON_FULL_RATE_LATENCY 63 #define AR5416_TX_HALF_RATE_LATENCY 108 @@ -2903,4 +2899,3 @@ ar5416SetIFSTiming(struct ath_hal *ah, const struct ieee80211_channel *chan) OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_USEC_DURATION, init_usec); } - diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c b/sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c index a5f1251607a8..496abbf4e9b4 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c @@ -243,4 +243,3 @@ ar5416RestoreSpectralConfig(struct ath_hal *ah, uint32_t restoreval) } return; } - diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c b/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c index 869d5fbea30a..e3330fe820b8 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c +++ b/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c @@ -266,7 +266,6 @@ ar5416GetTxRatePower(struct ath_hal *ah, uint8_t rate, uint8_t tx_chainmask, */ if (AR_SREV_MERLIN_20_OR_LATER(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { - if (rate == 0x19 || rate == 0x1a || rate == 0x1b || rate == (0x19 | 0x04) || rate == (0x1a | 0x04) || rate == (0x1b | 0x04)) { @@ -543,7 +542,7 @@ ar5416ChainTxDesc(struct ath_hal *ah, struct ath_desc *ds, int isaggr = 0; uint32_t last_aggr = 0; - + (void) hdrLen; (void) ah; @@ -613,7 +612,7 @@ ar5416ChainTxDesc(struct ath_hal *ah, struct ath_desc *ds, } ds_txstatus[0] = ds_txstatus[1] = 0; ds_txstatus[9] &= ~AR_TxDone; - + return AH_TRUE; } @@ -631,7 +630,7 @@ ar5416SetupFirstTxDesc(struct ath_hal *ah, struct ath_desc *ds, HALASSERT(isValidTxRate(txRate0)); HALASSERT((flags & RTSCTS) != RTSCTS); /* XXX validate antMode */ - + txPower = (txPower + ahp->ah_txPowerIndexOffset ); if(txPower > 63) txPower=63; @@ -646,7 +645,7 @@ ar5416SetupFirstTxDesc(struct ath_hal *ah, struct ath_desc *ds, | SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel1) | SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel2) | SM(AH5416(ah)->ah_tx_chainmask, AR_ChainSel3); - + /* NB: no V1 WAR */ ads->ds_ctl8 = SM(0, AR_AntCtl0); ads->ds_ctl9 = SM(0, AR_AntCtl1) | SM(txPower, AR_XmitPower1); @@ -673,7 +672,7 @@ ar5416SetupFirstTxDesc(struct ath_hal *ah, struct ath_desc *ds, ads->ds_ctl10 = SM(0, AR_AntCtl2) | SM(0, AR_XmitPower2); ads->ds_ctl11 = SM(0, AR_AntCtl3) | SM(0, AR_XmitPower3); } - + return AH_TRUE; #undef RTSCTS } @@ -1114,7 +1113,6 @@ ar5416GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int * return AH_TRUE; } - /* * TX queue management routines - AR5416 and later chipsets */ @@ -1326,7 +1324,7 @@ ar5416ResetTxQueue(struct ath_hal *ah, u_int q) SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT) | AR_Q_RDYTIMECFG_ENA); } - + OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) | (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); @@ -1464,7 +1462,7 @@ ar5416ResetTxQueue(struct ath_hal *ah, u_int q) OS_REG_READ(ah, AR_Q0_MISC + 4*q) | AR_Q_MISC_QCU_COMP_EN); } - + /* * Always update the secondary interrupt mask registers - this * could be a new queue getting enabled in a running system or diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416desc.h b/sys/dev/ath/ath_hal/ar5416/ar5416desc.h index 0e58bc61eba8..efe56a11965f 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416desc.h +++ b/sys/dev/ath/ath_hal/ar5416/ar5416desc.h @@ -64,7 +64,6 @@ struct ar5416_rx_desc { /* rx desc has 2 control words + 9 status words */ uint32_t status8; }; - struct ar5416_desc { uint32_t ds_link; /* link pointer */ uint32_t ds_data; /* data buffer pointer */ diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416reg.h b/sys/dev/ath/ath_hal/ar5416/ar5416reg.h index ff4f558efa83..85c1d6454952 100644 --- a/sys/dev/ath/ath_hal/ar5416/ar5416reg.h +++ b/sys/dev/ath/ath_hal/ar5416/ar5416reg.h @@ -669,7 +669,6 @@ #define AR_XSREV_VERSION_OWL_PCI 0x0D #define AR_XSREV_VERSION_OWL_PCIE 0x0C - /* * These are from ath9k/Atheros and assume an AR_SREV version mask * of 0x07, rather than 0x0F which is being used in the FreeBSD HAL. @@ -808,7 +807,6 @@ (AR_SREV_KIWI(_ah) && \ AH_PRIVATE((_ah))->ah_macRev >= AR_XSREV_REVISION_KIWI_13) - /* Not yet implemented chips */ #define AR_SREV_9271(_ah) 0 diff --git a/sys/dev/ath/ath_hal/ar9001/ar9130_attach.c b/sys/dev/ath/ath_hal/ar9001/ar9130_attach.c index 85389792219e..70277cc6ca2a 100644 --- a/sys/dev/ath/ath_hal/ar9001/ar9130_attach.c +++ b/sys/dev/ath/ath_hal/ar9001/ar9130_attach.c @@ -243,7 +243,6 @@ ar9130Attach(uint16_t devid, HAL_SOFTC sc, AH_PRIVATE(ah)->ah_currentRDext = ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); - /* * ah_miscMode is populated by ar5416FillCapabilityInfo() * starting from griffin. Set here to make sure that diff --git a/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c b/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c index d6336bef734c..17604e720cef 100644 --- a/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c +++ b/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c @@ -434,7 +434,6 @@ ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) OS_DELAY(1000); } - /* * Set PCIe workaround bits * diff --git a/sys/dev/ath/ath_hal/ar9002/ar9280_olc.c b/sys/dev/ath/ath_hal/ar9002/ar9280_olc.c index 5eeb420d5d3a..9d75e3b43131 100644 --- a/sys/dev/ath/ath_hal/ar9002/ar9280_olc.c +++ b/sys/dev/ath/ath_hal/ar9002/ar9280_olc.c @@ -171,7 +171,6 @@ ar9280olcTemperatureCompensation(struct ath_hal *ah) } } - static int16_t ar9280ChangeGainBoundarySettings(struct ath_hal *ah, uint16_t *gb, uint16_t numXpdGain, uint16_t pdGainOverlap_t2, int8_t pwr_table_offset, @@ -302,7 +301,6 @@ ar9280SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); - if (IS_EEP_MINOR_V2(ah)) { pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap; } else { diff --git a/sys/dev/ath/ath_hal/ar9002/ar9285.c b/sys/dev/ath/ath_hal/ar9002/ar9285.c index c4362637c173..0044f73a97c5 100644 --- a/sys/dev/ath/ath_hal/ar9002/ar9285.c +++ b/sys/dev/ath/ath_hal/ar9002/ar9285.c @@ -52,7 +52,6 @@ ar9285GetNoiseFloor(struct ath_hal *ah, int16_t nfarray[]) "NF calibrated [ctl] [chain 0] is %d\n", nf); nfarray[0] = nf; - nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); if (nf & 0x100) nf = 0 - ((nf ^ 0x1ff) + 1); diff --git a/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c b/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c index 718a89995df3..7fc6b96a25c9 100644 --- a/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c +++ b/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c @@ -196,7 +196,7 @@ ar9285Attach(uint16_t devid, HAL_SOFTC sc, AH5416(ah)->ah_writeIni = ar9285WriteIni; AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK; AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK; - + ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD >> 1; if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { diff --git a/sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c b/sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c index 3a168ae45ead..0596f19c3b64 100644 --- a/sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c +++ b/sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c @@ -150,5 +150,3 @@ ar9285BTCoexSetParameter(struct ath_hal *ah, u_int32_t type, u_int32_t value) break; } } - - diff --git a/sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c b/sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c index 3da59311e5dc..25ae031da2af 100644 --- a/sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c +++ b/sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c @@ -77,7 +77,7 @@ ar9285SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) /* Store settings */ AH5212(ah)->ah_antControl = settings; AH5212(ah)->ah_diversity = (settings == HAL_ANT_VARIABLE); - + /* XXX don't fiddle if the PHY is in sleep mode or ! chan */ /* Begin setting the relevant registers */ diff --git a/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c b/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c index 961e25e89efa..7b598a05720c 100644 --- a/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c +++ b/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c @@ -107,7 +107,7 @@ ar9285SetTransmitPower(struct ath_hal *ah, if (IS_EEP_MINOR_V2(ah)) { AH5416(ah)->ah_ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; } - + if (!ar9285SetPowerPerRateTable(ah, pEepData, chan, &AH5416(ah)->ah_ratesArray[0],cfgCtl, twiceAntennaReduction, diff --git a/sys/dev/ath/ath_hal/ar9002/ar9287_attach.c b/sys/dev/ath/ath_hal/ar9002/ar9287_attach.c index b5173dab309e..3cd13f73b772 100644 --- a/sys/dev/ath/ath_hal/ar9002/ar9287_attach.c +++ b/sys/dev/ath/ath_hal/ar9002/ar9287_attach.c @@ -146,7 +146,6 @@ ar9287Attach(uint16_t devid, HAL_SOFTC sc, ah->ah_eepromdata = eepromdata; } - /* XXX override with 9280 specific state */ /* override 5416 methods for our needs */ AH5416(ah)->ah_initPLL = ar9280InitPLL; diff --git a/sys/dev/ath/ath_hal/ar9002/ar9287_cal.c b/sys/dev/ath/ath_hal/ar9002/ar9287_cal.c index 09940a187e7d..3bdb4c7f0810 100644 --- a/sys/dev/ath/ath_hal/ar9002/ar9287_cal.c +++ b/sys/dev/ath/ath_hal/ar9002/ar9287_cal.c @@ -41,7 +41,6 @@ #include "ar9002/ar9287_cal.h" - void ar9287PACal(struct ath_hal *ah, HAL_BOOL is_reset) { @@ -55,7 +54,7 @@ HAL_BOOL ar9287InitCalHardware(struct ath_hal *ah, const struct ieee80211_channel *chan) { OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); - + /* Calibrate the AGC */ OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); diff --git a/sys/dev/ath/ath_hal/ar9002/ar9287_reset.c b/sys/dev/ath/ath_hal/ar9002/ar9287_reset.c index 372d6c476d12..e4b6eed5bfec 100644 --- a/sys/dev/ath/ath_hal/ar9002/ar9287_reset.c +++ b/sys/dev/ath/ath_hal/ar9002/ar9287_reset.c @@ -113,7 +113,6 @@ ar9287SetPowerCalTable(struct ath_hal *ah, *pTxPowerIndexOffset = 0; } - /* XXX hard-coded values? */ #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 |