diff options
| author | Michael Zhilin <mizhka@FreeBSD.org> | 2017-05-28 12:05:16 +0000 |
|---|---|---|
| committer | Michael Zhilin <mizhka@FreeBSD.org> | 2017-05-28 12:05:16 +0000 |
| commit | 97721228b8df7b9fdb9bb7cc0fd2acec37a58249 (patch) | |
| tree | de3378b91ff4a085626d5e897071760708ff9396 /sys/dev/bhnd | |
| parent | 34498213768e9727097571efa32a3638d7c0b42c (diff) | |
Notes
Diffstat (limited to 'sys/dev/bhnd')
| -rw-r--r-- | sys/dev/bhnd/cores/chipc/chipcreg.h | 2 | ||||
| -rw-r--r-- | sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c | 12 |
2 files changed, 10 insertions, 4 deletions
diff --git a/sys/dev/bhnd/cores/chipc/chipcreg.h b/sys/dev/bhnd/cores/chipc/chipcreg.h index b94adca847b4..87de8d674837 100644 --- a/sys/dev/bhnd/cores/chipc/chipcreg.h +++ b/sys/dev/bhnd/cores/chipc/chipcreg.h @@ -280,7 +280,7 @@ enum { #define CHIPC_PLL_TYPE1 0x2 /* 48MHz base, 3 dividers */ #define CHIPC_PLL_TYPE2 0x4 /* 48MHz, 4 dividers */ #define CHIPC_PLL_TYPE3 0x6 /* 25MHz, 2 dividers */ -#define CHIPC_PLL_TYPE4 0x8 /* 48MHz, 4 dividers */ +#define CHIPC_PLL_TYPE4 0x1 /* 48MHz, 4 dividers */ #define CHIPC_PLL_TYPE5 0x3 /* 25MHz, 4 dividers */ #define CHIPC_PLL_TYPE6 0x5 /* 100/200 or 120/240 only */ #define CHIPC_PLL_TYPE7 0x7 /* 25MHz, 4 dividers */ diff --git a/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c b/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c index 4cd23b3e2dac..9d5052c89c39 100644 --- a/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c +++ b/sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c @@ -374,7 +374,7 @@ bhnd_pwrctl_slowclk_freq(struct bhnd_pwrctl_softc *sc, bool max_freq) } else if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) { div = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL); div = CHIPC_GET_BITS(div, CHIPC_SCC_CD); - div *= 4; + div = 4 * (div + 1); } else if (PWRCTL_QUIRK(sc, INSTACLK_CTL)) { if (max_freq) { div = 1; @@ -503,7 +503,10 @@ bhnd_pwrctl_setclk(struct bhnd_pwrctl_softc *sc, bhnd_clock clock) if (bhnd_get_hwrev(sc->chipc_dev) == 10) return (ENODEV); - scc = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL); + if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) + scc = bhnd_bus_read_4(sc->res, CHIPC_PLL_SLOWCLK_CTL); + else + scc = bhnd_bus_read_4(sc->res, CHIPC_SYS_CLK_CTL); switch (clock) { case BHND_CLOCK_HT: @@ -520,7 +523,10 @@ bhnd_pwrctl_setclk(struct bhnd_pwrctl_softc *sc, bhnd_clock clock) return (ENODEV); } - bhnd_bus_write_4(sc->res, CHIPC_PLL_SLOWCLK_CTL, scc); + if (PWRCTL_QUIRK(sc, SLOWCLK_CTL)) + bhnd_bus_write_4(sc->res, CHIPC_PLL_SLOWCLK_CTL, scc); + else + bhnd_bus_write_4(sc->res, CHIPC_SYS_CLK_CTL, scc); DELAY(CHIPC_PLL_DELAY); break; |