diff options
author | Adrian Chadd <adrian@FreeBSD.org> | 2016-05-19 04:22:58 +0000 |
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committer | Adrian Chadd <adrian@FreeBSD.org> | 2016-05-19 04:22:58 +0000 |
commit | 923840c646c624bfcefb9b88f74148605ae8a4b1 (patch) | |
tree | 738117b09bf87540955f6468b51cafa45b964d81 /sys/dev/bwn | |
parent | af8366c44849c3a5abdb123839328a2152093da6 (diff) | |
download | src-923840c646c624bfcefb9b88f74148605ae8a4b1.tar.gz src-923840c646c624bfcefb9b88f74148605ae8a4b1.zip |
Notes
Diffstat (limited to 'sys/dev/bwn')
-rw-r--r-- | sys/dev/bwn/if_bwn_phy_common.c | 4 | ||||
-rw-r--r-- | sys/dev/bwn/if_bwnreg.h | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/sys/dev/bwn/if_bwn_phy_common.c b/sys/dev/bwn/if_bwn_phy_common.c index 2acb3746f9d7..bcc9dc9dfb60 100644 --- a/sys/dev/bwn/if_bwn_phy_common.c +++ b/sys/dev/bwn/if_bwn_phy_common.c @@ -186,9 +186,9 @@ bwn_mac_phy_clock_set(struct bwn_mac *mac, int enabled) if (bwn_is_bus_siba(mac)) { val = siba_read_4(sc->sc_dev, SIBA_TGSLOW); if (enabled) - val |= BWN_TMSLOW_MACPHYCLKEN; + val |= BWN_TGSLOW_MACPHYCLKEN; else - val &= ~BWN_TMSLOW_MACPHYCLKEN; + val &= ~BWN_TGSLOW_MACPHYCLKEN; siba_write_4(sc->sc_dev, SIBA_TGSLOW, val); } } diff --git a/sys/dev/bwn/if_bwnreg.h b/sys/dev/bwn/if_bwnreg.h index 0eae6daff5d4..8735cbe7fe2e 100644 --- a/sys/dev/bwn/if_bwnreg.h +++ b/sys/dev/bwn/if_bwnreg.h @@ -97,8 +97,8 @@ /* SIBA control registers */ #define BWN_TGSLOW_PHYCLOCK_ENABLE 0x00040000 #define BWN_TGSLOW_PHYRESET 0x00080000 -#define BWN_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */ -#define BWN_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */ +#define BWN_TGSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */ +#define BWN_TGSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */ /* PHY_BANDWIDTH: N-PHY only */ #define BWN_TGSLOW_PHY_BANDWIDTH 0x00C00000 #define BWN_TGSLOW_PHY_BANDWIDTH_10MHZ 0x00000000 |