17 files changed, 1214 insertions, 4340 deletions

diff --git a/sys/dev/bwn/if_bwn.c b/sys/dev/bwn/if_bwn.c
index 5fb008a07eba..5f48cf3dc377 100644
--- a/sys/dev/bwn/if_bwn.c
+++ b/sys/dev/bwn/if_bwn.c
@@ -2,7 +2,12 @@
  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
  *
  * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
+ * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
+ * Copyright (c) 2017 The FreeBSD Foundation
  * All rights reserved.
+ * 
+ * Portions of this software were developed by Landon Fuller
+ * under sponsorship from the FreeBSD Foundation.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -42,6 +47,7 @@ __FBSDID("$FreeBSD$");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
+#include <sys/gpio.h>
 #include <sys/malloc.h>
 #include <sys/module.h>
 #include <sys/endian.h>
@@ -65,16 +71,17 @@ __FBSDID("$FreeBSD$");
 #include <net/if_media.h>
 #include <net/if_types.h>
 
-#include <dev/pci/pcivar.h>
-#include <dev/pci/pcireg.h>
-
 #include <net80211/ieee80211_var.h>
 #include <net80211/ieee80211_radiotap.h>
 #include <net80211/ieee80211_regdomain.h>
 #include <net80211/ieee80211_phy.h>
 #include <net80211/ieee80211_ratectl.h>
 
-#include <dev/bwn/if_bwn_siba.h>
+#include <dev/bhnd/bhnd.h>
+#include <dev/bhnd/bhnd_ids.h>
+
+#include <dev/bhnd/cores/chipc/chipc.h>
+#include <dev/bhnd/cores/pmu/bhnd_pmu.h>
 
 #include <dev/bwn/if_bwnreg.h>
 #include <dev/bwn/if_bwnvar.h>
@@ -87,6 +94,10 @@ __FBSDID("$FreeBSD$");
 #include <dev/bwn/if_bwn_phy_lp.h>
 #include <dev/bwn/if_bwn_phy_n.h>
 
+#include "bhnd_nvram_map.h"
+
+#include "gpio_if.h"
+
 static SYSCTL_NODE(_hw, OID_AUTO, bwn, CTLFLAG_RD, 0,
     "Broadcom driver parameters");
 
@@ -109,8 +120,6 @@ SYSCTL_INT(_hw_bwn, OID_AUTO, bluetooth, CTLFLAG_RW, &bwn_bluetooth, 0,
 static int	bwn_hwpctl = 0;
 SYSCTL_INT(_hw_bwn, OID_AUTO, hwpctl, CTLFLAG_RW, &bwn_hwpctl, 0,
     "uses H/W power control");
-static int	bwn_msi_disable = 0;		/* MSI disabled  */
-TUNABLE_INT("hw.bwn.msi_disable", &bwn_msi_disable);
 static int	bwn_usedma = 1;
 SYSCTL_INT(_hw_bwn, OID_AUTO, usedma, CTLFLAG_RD, &bwn_usedma, 0,
     "uses DMA");
@@ -121,6 +130,8 @@ SYSCTL_INT(_hw_bwn, OID_AUTO, wme, CTLFLAG_RW, &bwn_wme, 0,
 
 static void	bwn_attach_pre(struct bwn_softc *);
 static int	bwn_attach_post(struct bwn_softc *);
+static int	bwn_retain_bus_providers(struct bwn_softc *sc);
+static void	bwn_release_bus_providers(struct bwn_softc *sc);
 static void	bwn_sprom_bugfixes(device_t);
 static int	bwn_init(struct bwn_softc *);
 static void	bwn_parent(struct ieee80211com *);
@@ -153,6 +164,7 @@ static struct ieee80211vap *bwn_vap_create(struct ieee80211com *,
 		    const uint8_t [IEEE80211_ADDR_LEN]);
 static void	bwn_vap_delete(struct ieee80211vap *);
 static void	bwn_stop(struct bwn_softc *);
+static int	bwn_core_forceclk(struct bwn_mac *, bool);
 static int	bwn_core_init(struct bwn_mac *);
 static void	bwn_core_start(struct bwn_mac *);
 static void	bwn_core_exit(struct bwn_mac *);
@@ -211,8 +223,6 @@ static struct bwn_pio_txqueue *bwn_pio_parse_cookie(struct bwn_mac *,
 		    uint16_t, struct bwn_pio_txpkt **);
 static void	bwn_dma_init(struct bwn_mac *);
 static void	bwn_dma_rxdirectfifo(struct bwn_mac *, int, uint8_t);
-static int	bwn_dma_mask2type(uint64_t);
-static uint64_t	bwn_dma_mask(struct bwn_mac *);
 static uint16_t	bwn_dma_base(int, int);
 static void	bwn_dma_ringfree(struct bwn_dma_ring **);
 static void	bwn_dma_32_getdesc(struct bwn_dma_ring *,
@@ -248,7 +258,6 @@ static int	bwn_dma_rx_reset(struct bwn_mac *, uint16_t, int);
 static void	bwn_dma_free_descbuf(struct bwn_dma_ring *,
 		    struct bwn_dmadesc_meta *);
 static void	bwn_dma_set_redzone(struct bwn_dma_ring *, struct mbuf *);
-static int	bwn_dma_gettype(struct bwn_mac *);
 static void	bwn_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
 static int	bwn_dma_freeslot(struct bwn_dma_ring *);
 static int	bwn_dma_nextslot(struct bwn_dma_ring *, int);
@@ -270,7 +279,7 @@ static struct bwn_dma_ring *bwn_dma_select(struct bwn_mac *,
 		    uint8_t);
 static int	bwn_dma_attach(struct bwn_mac *);
 static struct bwn_dma_ring *bwn_dma_ringsetup(struct bwn_mac *,
-		    int, int, int);
+		    int, int);
 static struct bwn_dma_ring *bwn_dma_parse_cookie(struct bwn_mac *,
 		    const struct bwn_txstatus *, uint16_t, int *);
 static void	bwn_dma_free(struct bwn_mac *);
@@ -296,7 +305,7 @@ static void	bwn_phy_exit(struct bwn_mac *);
 static void	bwn_core_stop(struct bwn_mac *);
 static int	bwn_switch_band(struct bwn_softc *,
 		    struct ieee80211_channel *);
-static void	bwn_phy_reset(struct bwn_mac *);
+static int	bwn_phy_reset(struct bwn_mac *);
 static int	bwn_newstate(struct ieee80211vap *, enum ieee80211_state, int);
 static void	bwn_set_pretbtt(struct bwn_mac *);
 static int	bwn_intr(void *);
@@ -346,7 +355,7 @@ static void	bwn_watchdog(void *);
 static void	bwn_dma_stop(struct bwn_mac *);
 static void	bwn_pio_stop(struct bwn_mac *);
 static void	bwn_dma_ringstop(struct bwn_dma_ring **);
-static void	bwn_led_attach(struct bwn_mac *);
+static int	bwn_led_attach(struct bwn_mac *);
 static void	bwn_led_newstate(struct bwn_mac *, enum ieee80211_state);
 static void	bwn_led_event(struct bwn_mac *, int);
 static void	bwn_led_blink_start(struct bwn_mac *, int, int);
@@ -357,16 +366,6 @@ static void	bwn_rf_turnon(struct bwn_mac *);
 static void	bwn_rf_turnoff(struct bwn_mac *);
 static void	bwn_sysctl_node(struct bwn_softc *);
 
-static struct resource_spec bwn_res_spec_legacy[] = {
-	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
-	{ -1,			0,		0 }
-};
-
-static struct resource_spec bwn_res_spec_msi[] = {
-	{ SYS_RES_IRQ,		1,		RF_ACTIVE },
-	{ -1,			0,		0 }
-};
-
 static const struct bwn_channelinfo bwn_chantable_bg = {
 	.channels = {
 		{ 2412,  1, 30 }, { 2417,  2, 30 }, { 2422,  3, 30 },
@@ -449,7 +448,7 @@ static const struct {
 	uint16_t	vid;
 	uint8_t		led_act[BWN_LED_MAX];
 } bwn_vendor_led_act[] = {
-	VENDOR_LED_ACT(COMPAQ),
+	VENDOR_LED_ACT(HP_COMPAQ),
 	VENDOR_LED_ACT(ASUSTEK)
 };
 
@@ -458,6 +457,13 @@ static const uint8_t bwn_default_led_act[BWN_LED_MAX] =
 
 #undef VENDOR_LED_ACT
 
+static const char *bwn_led_vars[] = {
+	BHND_NVAR_LEDBH0,
+	BHND_NVAR_LEDBH1,
+	BHND_NVAR_LEDBH2,
+	BHND_NVAR_LEDBH3
+};
+
 static const struct {
 	int		on_dur;
 	int		off_dur;
@@ -484,89 +490,130 @@ static const uint16_t bwn_wme_shm_offsets[] = {
 	[3] = BWN_WME_VIDEO,
 };
 
-static const struct siba_devid bwn_devs[] = {
-	SIBA_DEV(BROADCOM, 80211, 5, "Revision 5"),
-	SIBA_DEV(BROADCOM, 80211, 6, "Revision 6"),
-	SIBA_DEV(BROADCOM, 80211, 7, "Revision 7"),
-	SIBA_DEV(BROADCOM, 80211, 9, "Revision 9"),
-	SIBA_DEV(BROADCOM, 80211, 10, "Revision 10"),
-	SIBA_DEV(BROADCOM, 80211, 11, "Revision 11"),
-	SIBA_DEV(BROADCOM, 80211, 12, "Revision 12"),
-	SIBA_DEV(BROADCOM, 80211, 13, "Revision 13"),
-	SIBA_DEV(BROADCOM, 80211, 15, "Revision 15"),
-	SIBA_DEV(BROADCOM, 80211, 16, "Revision 16")
+/* Supported D11 core revisions */
+#define	BWN_DEV(_hwrev)	{{					\
+	BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_D11),	\
+	BHND_MATCH_CORE_REV(_hwrev),				\
+}}
+static const struct bhnd_device bwn_devices[] = {
+	BWN_DEV(HWREV_RANGE(5, 16)),
+	BWN_DEV(HWREV_EQ(23)),
+	BHND_DEVICE_END
 };
 
-static const struct bwn_bus_ops *
-bwn_get_bus_ops(device_t dev)
-{
-#if BWN_USE_SIBA
-	return (NULL);
-#else
-	devclass_t	bus_cls;
+/* D11 quirks when bridged via a PCI host bridge core */
+static const struct bhnd_device_quirk pci_bridge_quirks[] = {
+	BHND_CORE_QUIRK	(HWREV_LTE(10),	BWN_QUIRK_UCODE_SLOWCLOCK_WAR),
+	BHND_DEVICE_QUIRK_END
+};
 
-	bus_cls = device_get_devclass(device_get_parent(dev));
-	if (bus_cls == devclass_find("bhnd"))
-		return (&bwn_bhnd_bus_ops);
-	else
-		return (&bwn_siba_bus_ops);
-#endif
-}
+/* D11 quirks when bridged via a PCMCIA host bridge core */
+static const struct bhnd_device_quirk pcmcia_bridge_quirks[] = {
+	BHND_CORE_QUIRK	(HWREV_ANY,	BWN_QUIRK_NODMA),
+	BHND_DEVICE_QUIRK_END
+};
+
+/* Host bridge cores for which D11 quirk flags should be applied */
+static const struct bhnd_device bridge_devices[] = {
+	BHND_DEVICE(BCM, PCI,		NULL, pci_bridge_quirks),
+	BHND_DEVICE(BCM, PCMCIA,	NULL, pcmcia_bridge_quirks),
+	BHND_DEVICE_END
+};
 
 static int
 bwn_probe(device_t dev)
 {
-	struct bwn_softc	*sc;
-	int			 i;
+	const struct bhnd_device *id;
 
-	sc = device_get_softc(dev);
-	sc->sc_bus_ops = bwn_get_bus_ops(dev);
-
-	for (i = 0; i < nitems(bwn_devs); i++) {
-		if (siba_get_vendor(dev) == bwn_devs[i].sd_vendor &&
-		    siba_get_device(dev) == bwn_devs[i].sd_device &&
-		    siba_get_revid(dev) == bwn_devs[i].sd_rev)
-			return (BUS_PROBE_DEFAULT);
-	}
+	id = bhnd_device_lookup(dev, bwn_devices, sizeof(bwn_devices[0]));
+	if (id == NULL)
+		return (ENXIO);
 
-	return (ENXIO);
+	bhnd_set_default_core_desc(dev);
+	return (BUS_PROBE_DEFAULT);
 }
 
-int
+static int
 bwn_attach(device_t dev)
 {
-	struct bwn_mac *mac;
-	struct bwn_softc *sc = device_get_softc(dev);
-	int error, i, msic, reg;
+	struct bwn_mac		*mac;
+	struct bwn_softc	*sc;
+	device_t		 parent, hostb;
+	char			 chip_name[BHND_CHIPID_MAX_NAMELEN];
+	int			 error;
 
+	sc = device_get_softc(dev);
 	sc->sc_dev = dev;
 #ifdef BWN_DEBUG
 	sc->sc_debug = bwn_debug;
 #endif
 
-	sc->sc_bus_ops = bwn_get_bus_ops(dev);
-	if ((error = BWN_BUS_OPS_ATTACH(dev))) {
-		device_printf(sc->sc_dev,
-		    "bus-specific initialization failed (%d)\n", error);
+	mac = NULL;
+
+	/* Determine the driver quirks applicable to this device, including any
+	 * quirks specific to the bus host bridge core (if any) */
+	sc->sc_quirks = bhnd_device_quirks(dev, bwn_devices,
+	    sizeof(bwn_devices[0]));
+
+	parent = device_get_parent(dev);
+	if ((hostb = bhnd_bus_find_hostb_device(parent)) != NULL) {
+		sc->sc_quirks |= bhnd_device_quirks(hostb, bridge_devices,
+		    sizeof(bridge_devices[0]));
+	}
+
+	/* DMA explicitly disabled? */
+	if (!bwn_usedma)
+		sc->sc_quirks |= BWN_QUIRK_NODMA;
+
+	/* Fetch our chip identification and board info */
+	sc->sc_cid = *bhnd_get_chipid(dev);
+	if ((error = bhnd_read_board_info(dev, &sc->sc_board_info))) {
+		device_printf(sc->sc_dev, "couldn't read board info\n");
+		return (error);
+	}
+
+	/* Allocate our D11 register block and PMU state */
+	sc->sc_mem_rid = 0;
+	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
+	    &sc->sc_mem_rid, RF_ACTIVE);
+	if (sc->sc_mem_res == NULL) {
+		device_printf(sc->sc_dev, "couldn't allocate registers\n");
+		return (error);
+	}
+	
+	if ((error = bhnd_alloc_pmu(sc->sc_dev))) {
+		bus_release_resource(sc->sc_dev, SYS_RES_MEMORY,
+		    sc->sc_mem_rid, sc->sc_mem_res);
 		return (error);
 	}
 
+	/* Retain references to all required bus service providers */
+	if ((error = bwn_retain_bus_providers(sc)))
+		goto fail;
+
+	/* Fetch mask of available antennas */
+	error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_AA2G,
+	    &sc->sc_ant2g);
+	if (error) {
+		device_printf(sc->sc_dev, "error determining 2GHz antenna "
+		    "availability from NVRAM: %d\n", error);
+		goto fail;
+	}
+
+	error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_AA5G,
+	    &sc->sc_ant5g);
+	if (error) {
+		device_printf(sc->sc_dev, "error determining 5GHz antenna "
+		    "availability from NVRAM: %d\n", error);
+		goto fail;
+	}
+
 	if ((sc->sc_flags & BWN_FLAG_ATTACHED) == 0) {
 		bwn_attach_pre(sc);
 		bwn_sprom_bugfixes(dev);
 		sc->sc_flags |= BWN_FLAG_ATTACHED;
 	}
 
-	if (!TAILQ_EMPTY(&sc->sc_maclist)) {
-		if (siba_get_pci_device(dev) != 0x4313 &&
-		    siba_get_pci_device(dev) != 0x431a &&
-		    siba_get_pci_device(dev) != 0x4321) {
-			device_printf(sc->sc_dev,
-			    "skip 802.11 cores\n");
-			return (ENODEV);
-		}
-	}
-
 	mac = malloc(sizeof(*mac), M_DEVBUF, M_WAITOK | M_ZERO);
 	mac->mac_sc = sc;
 	mac->mac_status = BWN_MAC_STATUS_UNINIT;
@@ -579,18 +626,19 @@ bwn_attach(device_t dev)
 
 	error = bwn_attach_core(mac);
 	if (error)
-		goto fail0;
-	bwn_led_attach(mac);
+		goto fail;
+	error = bwn_led_attach(mac);
+	if (error)
+		goto fail;
 
-	device_printf(sc->sc_dev, "WLAN (chipid %#x rev %u) "
+	bhnd_format_chip_id(chip_name, sizeof(chip_name), sc->sc_cid.chip_id);
+	device_printf(sc->sc_dev, "WLAN (%s rev %u) "
 	    "PHY (analog %d type %d rev %d) RADIO (manuf %#x ver %#x rev %d)\n",
-	    siba_get_chipid(sc->sc_dev), siba_get_revid(sc->sc_dev),
-	    mac->mac_phy.analog, mac->mac_phy.type, mac->mac_phy.rev,
-	    mac->mac_phy.rf_manuf, mac->mac_phy.rf_ver,
-	    mac->mac_phy.rf_rev);
+	    chip_name, bhnd_get_hwrev(sc->sc_dev), mac->mac_phy.analog,
+	    mac->mac_phy.type, mac->mac_phy.rev, mac->mac_phy.rf_manuf,
+	    mac->mac_phy.rf_ver, mac->mac_phy.rf_rev);
 	if (mac->mac_flags & BWN_MAC_FLAG_DMA)
-		device_printf(sc->sc_dev, "DMA (%d bits)\n",
-		    mac->mac_method.dma.dmatype);
+		device_printf(sc->sc_dev, "DMA (%d bits)\n", mac->mac_dmatype);
 	else
 		device_printf(sc->sc_dev, "PIO\n");
 
@@ -599,49 +647,23 @@ bwn_attach(device_t dev)
 	    "Note: compiled with BWN_GPL_PHY; includes GPLv2 code\n");
 #endif
 
-	/*
-	 * setup PCI resources and interrupt.
-	 */
-	if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
-		msic = pci_msi_count(dev);
-		if (bootverbose)
-			device_printf(sc->sc_dev, "MSI count : %d\n", msic);
-	} else
-		msic = 0;
-
-	mac->mac_intr_spec = bwn_res_spec_legacy;
-	if (msic == BWN_MSI_MESSAGES && bwn_msi_disable == 0) {
-		if (pci_alloc_msi(dev, &msic) == 0) {
-			device_printf(sc->sc_dev,
-			    "Using %d MSI messages\n", msic);
-			mac->mac_intr_spec = bwn_res_spec_msi;
-			mac->mac_msi = 1;
-		}
-	}
+	mac->mac_rid_irq = 0;
+	mac->mac_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
+	    &mac->mac_rid_irq, RF_ACTIVE | RF_SHAREABLE);
 
-	error = bus_alloc_resources(dev, mac->mac_intr_spec,
-	    mac->mac_res_irq);
-	if (error) {
-		device_printf(sc->sc_dev,
-		    "couldn't allocate IRQ resources (%d)\n", error);
-		goto fail1;
+	if (mac->mac_res_irq == NULL) {
+		device_printf(sc->sc_dev, "couldn't allocate IRQ resource\n");
+		error = ENXIO;
+		goto fail;
 	}
 
-	if (mac->mac_msi == 0)
-		error = bus_setup_intr(dev, mac->mac_res_irq[0],
-		    INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac,
-		    &mac->mac_intrhand[0]);
-	else {
-		for (i = 0; i < BWN_MSI_MESSAGES; i++) {
-			error = bus_setup_intr(dev, mac->mac_res_irq[i],
-			    INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac,
-			    &mac->mac_intrhand[i]);
-			if (error != 0) {
-				device_printf(sc->sc_dev,
-				    "couldn't setup interrupt (%d)\n", error);
-				break;
-			}
-		}
+	error = bus_setup_intr(dev, mac->mac_res_irq,
+	    INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac,
+	    &mac->mac_intrhand);
+	if (error != 0) {
+		device_printf(sc->sc_dev, "couldn't setup interrupt (%d)\n",
+		    error);
+		goto fail;
 	}
 
 	TAILQ_INSERT_TAIL(&sc->sc_maclist, mac, mac_list);
@@ -653,30 +675,85 @@ bwn_attach(device_t dev)
 		bwn_attach_post(sc);
 
 	return (0);
-fail1:
-	if (msic == BWN_MSI_MESSAGES && bwn_msi_disable == 0)
-		pci_release_msi(dev);
-fail0:
-	BWN_BUS_OPS_DETACH(dev);
+fail:
+	if (mac != NULL && mac->mac_res_irq != NULL) {
+		bus_release_resource(dev, SYS_RES_IRQ, mac->mac_rid_irq,
+		    mac->mac_res_irq);
+	}
+
 	free(mac, M_DEVBUF);
+	bhnd_release_pmu(dev);
+	bwn_release_bus_providers(sc);
+	
+	if (sc->sc_mem_res != NULL) {
+		bus_release_resource(sc->sc_dev, SYS_RES_MEMORY,
+		    sc->sc_mem_rid, sc->sc_mem_res);
+	}
+
 	return (error);
 }
 
 static int
-bwn_is_valid_ether_addr(uint8_t *addr)
+bwn_retain_bus_providers(struct bwn_softc *sc)
 {
-	char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
+	struct chipc_caps *ccaps;
+
+	sc->sc_chipc = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_CHIPC);
+	if (sc->sc_chipc == NULL) {
+		device_printf(sc->sc_dev, "ChipCommon device not found\n");
+		goto failed;
+	}
 
-	if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN)))
-		return (FALSE);
+	ccaps = BHND_CHIPC_GET_CAPS(sc->sc_chipc);
+
+	sc->sc_gpio = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_GPIO);
+	if (sc->sc_gpio == NULL) {
+		device_printf(sc->sc_dev, "GPIO device not found\n");
+		goto failed;
+	}
+
+	if (ccaps->pmu) {
+		sc->sc_pmu = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_PMU);
+		if (sc->sc_pmu == NULL) {
+			device_printf(sc->sc_dev, "PMU device not found\n");
+			goto failed;
+		}
+	}
 
-	return (TRUE);
+	return (0);
+
+failed:
+	bwn_release_bus_providers(sc);
+	return (ENXIO);
+}
+
+static void
+bwn_release_bus_providers(struct bwn_softc *sc)
+{
+#define	BWN_RELEASE_PROV(_sc, _prov, _service)	do {			\
+	if ((_sc)-> _prov != NULL) {					\
+		bhnd_release_provider((_sc)->sc_dev, (_sc)-> _prov,	\
+		    (_service));					\
+		(_sc)-> _prov = NULL;					\
+	}								\
+} while (0)
+
+	BWN_RELEASE_PROV(sc, sc_chipc, BHND_SERVICE_CHIPC);
+	BWN_RELEASE_PROV(sc, sc_gpio, BHND_SERVICE_GPIO);
+	BWN_RELEASE_PROV(sc, sc_pmu, BHND_SERVICE_PMU);
+
+#undef	BWN_RELEASE_PROV
 }
 
 static int
 bwn_attach_post(struct bwn_softc *sc)
 {
-	struct ieee80211com *ic = &sc->sc_ic;
+	struct ieee80211com	*ic;
+	const char		*mac_varname;
+	u_int			 core_unit;
+	int			 error;
+
+	ic = &sc->sc_ic;
 
 	ic->ic_softc = sc;
 	ic->ic_name = device_get_nameunit(sc->sc_dev);
@@ -699,10 +776,35 @@ bwn_attach_post(struct bwn_softc *sc)
 
 	ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS;	/* s/w bmiss */
 
-	IEEE80211_ADDR_COPY(ic->ic_macaddr,
-	    bwn_is_valid_ether_addr(siba_sprom_get_mac_80211a(sc->sc_dev)) ?
-	    siba_sprom_get_mac_80211a(sc->sc_dev) :
-	    siba_sprom_get_mac_80211bg(sc->sc_dev));
+	/* Determine the NVRAM variable containing our MAC address */
+	core_unit = bhnd_get_core_unit(sc->sc_dev);
+	mac_varname = NULL;
+	if (sc->sc_board_info.board_srom_rev <= 2) {
+		if (core_unit == 0) {
+			mac_varname = BHND_NVAR_IL0MACADDR;
+		} else if (core_unit == 1) {
+			mac_varname = BHND_NVAR_ET1MACADDR;
+		}
+	} else {
+		if (core_unit == 0) {
+			mac_varname = BHND_NVAR_MACADDR;
+		}
+	}
+
+	if (mac_varname == NULL) {
+		device_printf(sc->sc_dev, "missing MAC address variable for "
+		    "D11 core %u", core_unit);
+		return (ENXIO);
+	}
+
+	/* Read the MAC address from NVRAM */
+	error = bhnd_nvram_getvar_array(sc->sc_dev, mac_varname, ic->ic_macaddr,
+	    sizeof(ic->ic_macaddr), BHND_NVRAM_TYPE_UINT8_ARRAY);
+	if (error) {
+		device_printf(sc->sc_dev, "error reading %s: %d\n", mac_varname,
+		    error);
+		return (error);
+	}
 
 	/* call MI attach routine. */
 	ieee80211_ifattach(ic);
@@ -743,13 +845,12 @@ bwn_phy_detach(struct bwn_mac *mac)
 		mac->mac_phy.detach(mac);
 }
 
-int
+static int
 bwn_detach(device_t dev)
 {
 	struct bwn_softc *sc = device_get_softc(dev);
 	struct bwn_mac *mac = sc->sc_curmac;
 	struct ieee80211com *ic = &sc->sc_ic;
-	int i;
 
 	sc->sc_flags |= BWN_FLAG_INVALID;
 
@@ -770,20 +871,22 @@ bwn_detach(device_t dev)
 	taskqueue_drain(sc->sc_tq, &mac->mac_intrtask);
 	taskqueue_free(sc->sc_tq);
 
-	for (i = 0; i < BWN_MSI_MESSAGES; i++) {
-		if (mac->mac_intrhand[i] != NULL) {
-			bus_teardown_intr(dev, mac->mac_res_irq[i],
-			    mac->mac_intrhand[i]);
-			mac->mac_intrhand[i] = NULL;
-		}
+	if (mac->mac_intrhand != NULL) {
+		bus_teardown_intr(dev, mac->mac_res_irq, mac->mac_intrhand);
+		mac->mac_intrhand = NULL;
 	}
-	bus_release_resources(dev, mac->mac_intr_spec, mac->mac_res_irq);
-	if (mac->mac_msi != 0)
-		pci_release_msi(dev);
+
+	bhnd_release_pmu(dev);
+	bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
+	    sc->sc_mem_res);
+	bus_release_resource(dev, SYS_RES_IRQ, mac->mac_rid_irq,
+	    mac->mac_res_irq);
 	mbufq_drain(&sc->sc_snd);
 	bwn_release_firmware(mac);
 	BWN_LOCK_DESTROY(sc);
-	BWN_BUS_OPS_DETACH(dev);
+
+	bwn_release_bus_providers(sc);
+
 	return (0);
 }
 
@@ -806,32 +909,28 @@ bwn_attach_pre(struct bwn_softc *sc)
 static void
 bwn_sprom_bugfixes(device_t dev)
 {
-#define	BWN_ISDEV(_vendor, _device, _subvendor, _subdevice)		\
-	((siba_get_pci_vendor(dev) == PCI_VENDOR_##_vendor) &&		\
-	 (siba_get_pci_device(dev) == _device) &&			\
-	 (siba_get_pci_subvendor(dev) == PCI_VENDOR_##_subvendor) &&	\
-	 (siba_get_pci_subdevice(dev) == _subdevice))
+	struct bwn_softc *sc = device_get_softc(dev);
 
-	if (siba_get_pci_subvendor(dev) == PCI_VENDOR_APPLE &&
-	    siba_get_pci_subdevice(dev) == 0x4e &&
-	    siba_get_pci_revid(dev) > 0x40)
-		siba_sprom_set_bf_lo(dev,
-		    siba_sprom_get_bf_lo(dev) | BWN_BFL_PACTRL);
-	if (siba_get_pci_subvendor(dev) == SIBA_BOARDVENDOR_DELL &&
-	    siba_get_chipid(dev) == 0x4301 && siba_get_pci_revid(dev) == 0x74)
-		siba_sprom_set_bf_lo(dev,
-		    siba_sprom_get_bf_lo(dev) | BWN_BFL_BTCOEXIST);
-	if (siba_get_type(dev) == SIBA_TYPE_PCI) {
-		if (BWN_ISDEV(BROADCOM, 0x4318, ASUSTEK, 0x100f) ||
-		    BWN_ISDEV(BROADCOM, 0x4320, DELL, 0x0003) ||
-		    BWN_ISDEV(BROADCOM, 0x4320, HP, 0x12f8) ||
-		    BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0013) ||
-		    BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0014) ||
-		    BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0015) ||
-		    BWN_ISDEV(BROADCOM, 0x4320, MOTOROLA, 0x7010))
-			siba_sprom_set_bf_lo(dev,
-			    siba_sprom_get_bf_lo(dev) & ~BWN_BFL_BTCOEXIST);
-	}
+#define	BWN_ISDEV(_device, _subvendor, _subdevice)		\
+	((sc->sc_board_info.board_devid == PCI_DEVID_##_device) &&	\
+	 (sc->sc_board_info.board_vendor == PCI_VENDOR_##_subvendor) &&	\
+	 (sc->sc_board_info.board_type == _subdevice))
+
+	 /* A subset of Apple Airport Extreme (BCM4306 rev 2) devices
+	  * were programmed with a missing PACTRL boardflag */
+	 if (sc->sc_board_info.board_vendor == PCI_VENDOR_APPLE &&
+	     sc->sc_board_info.board_type == 0x4e &&
+	     sc->sc_board_info.board_rev > 0x40)
+		 sc->sc_board_info.board_flags |= BHND_BFL_PACTRL;
+
+	if (BWN_ISDEV(BCM4318_D11G, ASUSTEK, 0x100f) ||
+	    BWN_ISDEV(BCM4306_D11G, DELL, 0x0003) ||
+	    BWN_ISDEV(BCM4306_D11G, HP, 0x12f8) ||
+	    BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0013) ||
+	    BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0014) ||
+	    BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0015) ||
+	    BWN_ISDEV(BCM4306_D11G, MOTOROLA, 0x7010))
+		sc->sc_board_info.board_flags &= ~BHND_BFL_BTCOEX;
 #undef	BWN_ISDEV
 }
 
@@ -1008,7 +1107,7 @@ bwn_pio_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni, struct mbuf *m)
 	tq->tq_used += roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4);
 	tq->tq_free--;
 
-	if (siba_get_revid(sc->sc_dev) >= 8) {
+	if (bhnd_get_hwrev(sc->sc_dev) >= 8) {
 		/*
 		 * XXX please removes m_defrag(9)
 		 */
@@ -1181,29 +1280,37 @@ bwn_attach_core(struct bwn_mac *mac)
 {
 	struct bwn_softc *sc = mac->mac_sc;
 	int error, have_bg = 0, have_a = 0;
-	uint32_t high;
+	uint16_t iost;
 
-	KASSERT(siba_get_revid(sc->sc_dev) >= 5,
-	    ("unsupported revision %d", siba_get_revid(sc->sc_dev)));
+	KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 5,
+	    ("unsupported revision %d", bhnd_get_hwrev(sc->sc_dev)));
 
-	siba_powerup(sc->sc_dev, 0);
-	high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH);
-	have_a = (high & BWN_TGSHIGH_HAVE_5GHZ) ? 1 : 0;
-	have_bg = (high & BWN_TGSHIGH_HAVE_2GHZ) ? 1 : 0;
-	if (high & BWN_TGSHIGH_DUALPHY) {
+	if ((error = bwn_core_forceclk(mac, true)))
+		return (error);
+
+	if ((error = bhnd_read_iost(sc->sc_dev, &iost))) {
+		device_printf(sc->sc_dev, "error reading I/O status flags: "
+		    "%d\n", error);
+		return (error);
+	}
+
+	have_a = (iost & BWN_IOST_HAVE_5GHZ) ? 1 : 0;
+	have_bg = (iost & BWN_IOST_HAVE_2GHZ) ? 1 : 0;
+	if (iost & BWN_IOST_DUALPHY) {
 		have_bg = 1;
 		have_a = 1;
 	}
+	
 
 #if 0
-	device_printf(sc->sc_dev, "%s: high=0x%08x, have_a=%d, have_bg=%d,"
+	device_printf(sc->sc_dev, "%s: iost=0x%04hx, have_a=%d, have_bg=%d,"
 	    " deviceid=0x%04x, siba_deviceid=0x%04x\n",
 	    __func__,
-	    high,
+	    iost,
 	    have_a,
 	    have_bg,
-	    siba_get_pci_device(sc->sc_dev),
-	    siba_get_chipid(sc->sc_dev));
+	    sc->sc_board_info.board_devid,
+	    sc->sc_cid.chip_id);
 #endif
 
 	/*
@@ -1211,7 +1318,29 @@ bwn_attach_core(struct bwn_mac *mac)
 	 * This is just used for resetting the core to probe things;
 	 * we will re-guess once it's all up and working.
 	 */
-	bwn_reset_core(mac, have_bg);
+	error = bwn_reset_core(mac, have_bg);
+	if (error)
+		goto fail;
+
+	/*
+	 * Determine the DMA engine type
+	 */
+	if (iost & BHND_IOST_DMA64) {
+		mac->mac_dmatype = BHND_DMA_ADDR_64BIT;
+	} else {
+		uint32_t tmp;
+		uint16_t base;
+
+		base = bwn_dma_base(0, 0);
+		BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL,
+		    BWN_DMA32_TXADDREXT_MASK);
+		tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL);
+		if (tmp & BWN_DMA32_TXADDREXT_MASK) {
+			mac->mac_dmatype = BHND_DMA_ADDR_32BIT;
+		} else {
+			mac->mac_dmatype = BHND_DMA_ADDR_30BIT;
+		}
+	}
 
 	/*
 	 * Get the PHY version.
@@ -1224,12 +1353,12 @@ bwn_attach_core(struct bwn_mac *mac)
 	 * This is the whitelist of devices which we "believe"
 	 * the SPROM PHY config from.  The rest are "guessed".
 	 */
-	if (siba_get_pci_device(sc->sc_dev) != 0x4312 &&
-	    siba_get_pci_device(sc->sc_dev) != 0x4315 &&
-	    siba_get_pci_device(sc->sc_dev) != 0x4319 &&
-	    siba_get_pci_device(sc->sc_dev) != 0x4324 &&
-	    siba_get_pci_device(sc->sc_dev) != 0x4328 &&
-	    siba_get_pci_device(sc->sc_dev) != 0x432b) {
+	if (sc->sc_board_info.board_devid != PCI_DEVID_BCM4311_D11DUAL &&
+	    sc->sc_board_info.board_devid != PCI_DEVID_BCM4328_D11G &&
+	    sc->sc_board_info.board_devid != PCI_DEVID_BCM4318_D11DUAL &&
+	    sc->sc_board_info.board_devid != PCI_DEVID_BCM4306_D11DUAL &&
+	    sc->sc_board_info.board_devid != PCI_DEVID_BCM4321_D11N &&
+	    sc->sc_board_info.board_devid != PCI_DEVID_BCM4322_D11N) {
 		have_a = have_bg = 0;
 		if (mac->mac_phy.type == BWN_PHYTYPE_A)
 			have_a = 1;
@@ -1330,7 +1459,9 @@ bwn_attach_core(struct bwn_mac *mac)
 		}
 	}
 
-	bwn_reset_core(mac, have_bg);
+	error = bwn_reset_core(mac, have_bg);
+	if (error)
+		goto fail;
 
 	error = bwn_chiptest(mac);
 	if (error)
@@ -1352,46 +1483,64 @@ bwn_attach_core(struct bwn_mac *mac)
 
 	mac->mac_phy.switch_analog(mac, 0);
 
-	siba_dev_down(sc->sc_dev, 0);
 fail:
-	siba_powerdown(sc->sc_dev);
+	bhnd_suspend_hw(sc->sc_dev, 0);
 	bwn_release_firmware(mac);
 	return (error);
 }
 
 /*
- * Reset - SIBA.
+ * Reset
  */
-void
+int
 bwn_reset_core(struct bwn_mac *mac, int g_mode)
 {
-	struct bwn_softc *sc = mac->mac_sc;
-	uint32_t low, ctl;
-	uint32_t flags = 0;
+	struct bwn_softc	*sc;
+	uint32_t		 ctl;
+	uint16_t		 ioctl, ioctl_mask;
+	int			 error;
+
+	sc = mac->mac_sc;
 
 	DPRINTF(sc, BWN_DEBUG_RESET, "%s: g_mode=%d\n", __func__, g_mode);
 
-	flags |= (BWN_TGSLOW_PHYCLOCK_ENABLE | BWN_TGSLOW_PHYRESET);
+	/* Reset core */
+	ioctl = (BWN_IOCTL_PHYCLOCK_ENABLE | BWN_IOCTL_PHYRESET);
 	if (g_mode)
-		flags |= BWN_TGSLOW_SUPPORT_G;
+		ioctl |= BWN_IOCTL_SUPPORT_G;
 
 	/* XXX N-PHY only; and hard-code to 20MHz for now */
 	if (mac->mac_phy.type == BWN_PHYTYPE_N)
-		flags |= BWN_TGSLOW_PHY_BANDWIDTH_20MHZ;
+		ioctl |= BWN_IOCTL_PHY_BANDWIDTH_20MHZ;
+
+	if ((error = bhnd_reset_hw(sc->sc_dev, ioctl, ioctl))) {
+		device_printf(sc->sc_dev, "core reset failed: %d", error);
+		return (error);
+	}
 
-	siba_dev_up(sc->sc_dev, flags);
 	DELAY(2000);
 
 	/* Take PHY out of reset */
-	low = (siba_read_4(sc->sc_dev, SIBA_TGSLOW) | SIBA_TGSLOW_FGC) &
-	    ~(BWN_TGSLOW_PHYRESET | BWN_TGSLOW_PHYCLOCK_ENABLE);
-	siba_write_4(sc->sc_dev, SIBA_TGSLOW, low);
-	siba_read_4(sc->sc_dev, SIBA_TGSLOW);
+	ioctl = BHND_IOCTL_CLK_FORCE;
+	ioctl_mask = BHND_IOCTL_CLK_FORCE |
+		     BWN_IOCTL_PHYRESET |
+		     BWN_IOCTL_PHYCLOCK_ENABLE;
+
+	if ((error = bhnd_write_ioctl(sc->sc_dev, ioctl, ioctl_mask))) {
+		device_printf(sc->sc_dev, "failed to set core ioctl flags: "
+		    "%d\n", error);
+		return (error);
+	}
+
 	DELAY(2000);
-	low &= ~SIBA_TGSLOW_FGC;
-	low |= BWN_TGSLOW_PHYCLOCK_ENABLE;
-	siba_write_4(sc->sc_dev, SIBA_TGSLOW, low);
-	siba_read_4(sc->sc_dev, SIBA_TGSLOW);
+
+	ioctl = BWN_IOCTL_PHYCLOCK_ENABLE;
+	if ((error = bhnd_write_ioctl(sc->sc_dev, ioctl, ioctl_mask))) {
+		device_printf(sc->sc_dev, "failed to set core ioctl flags: "
+		    "%d\n", error);
+		return (error);
+	}
+
 	DELAY(2000);
 
 	if (mac->mac_phy.switch_analog != NULL)
@@ -1401,6 +1550,8 @@ bwn_reset_core(struct bwn_mac *mac, int g_mode)
 	if (g_mode)
 		ctl |= BWN_MACCTL_GMODE;
 	BWN_WRITE_4(mac, BWN_MACCTL, ctl | BWN_MACCTL_IHR_ON);
+
+	return (0);
 }
 
 static int
@@ -1426,19 +1577,11 @@ bwn_phy_getinfo(struct bwn_mac *mac, int gmode)
 		goto unsupphy;
 
 	/* RADIO */
-	if (siba_get_chipid(sc->sc_dev) == 0x4317) {
-		if (siba_get_chiprev(sc->sc_dev) == 0)
-			tmp = 0x3205017f;
-		else if (siba_get_chiprev(sc->sc_dev) == 1)
-			tmp = 0x4205017f;
-		else
-			tmp = 0x5205017f;
-	} else {
-		BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
-		tmp = BWN_READ_2(mac, BWN_RFDATALO);
-		BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
-		tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16;
-	}
+	BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
+	tmp = BWN_READ_2(mac, BWN_RFDATALO);
+	BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
+	tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16;
+
 	phy->rf_rev = (tmp & 0xf0000000) >> 28;
 	phy->rf_ver = (tmp & 0x0ffff000) >> 12;
 	phy->rf_manuf = (tmp & 0x00000fff);
@@ -1495,8 +1638,8 @@ bwn_chiptest(struct bwn_mac *mac)
 
 	bwn_shm_write_4(mac, BWN_SHARED, 0, backup);
 
-	if ((siba_get_revid(sc->sc_dev) >= 3) &&
-	    (siba_get_revid(sc->sc_dev) <= 10)) {
+	if ((bhnd_get_hwrev(sc->sc_dev) >= 3) &&
+	    (bhnd_get_hwrev(sc->sc_dev) <= 10)) {
 		BWN_WRITE_2(mac, BWN_TSF_CFP_START, 0xaaaa);
 		BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0xccccbbbb);
 		if (BWN_READ_2(mac, BWN_TSF_CFP_START_LOW) != 0xbbbb)
@@ -2027,6 +2170,34 @@ bwn_wme_clear(struct bwn_softc *sc)
 }
 
 static int
+bwn_core_forceclk(struct bwn_mac *mac, bool force)
+{
+	struct bwn_softc	*sc;
+	bhnd_clock		 clock;
+	int			 error;
+
+	sc = mac->mac_sc;
+
+	/* On PMU equipped devices, we do not need to force the HT clock */
+	if (sc->sc_pmu != NULL)
+		return (0);
+
+	/* Issue a PMU clock request */
+	if (force)
+		clock = BHND_CLOCK_HT;
+	else
+		clock = BHND_CLOCK_DYN;
+
+	if ((error = bhnd_request_clock(sc->sc_dev, clock))) {
+		device_printf(sc->sc_dev, "%d clock request failed: %d\n",
+		    clock, error);
+		return (error);
+	}
+
+	return (0);
+}
+
+static int
 bwn_core_init(struct bwn_mac *mac)
 {
 	struct bwn_softc *sc = mac->mac_sc;
@@ -2038,9 +2209,13 @@ bwn_core_init(struct bwn_mac *mac)
 
 	DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
 
-	siba_powerup(sc->sc_dev, 0);
-	if (!siba_dev_isup(sc->sc_dev))
-		bwn_reset_core(mac, mac->mac_phy.gmode);
+	if ((error = bwn_core_forceclk(mac, true)))
+		return (error);
+
+	if (bhnd_is_hw_suspended(sc->sc_dev)) {
+		if ((error = bwn_reset_core(mac, mac->mac_phy.gmode)))
+			goto fail0;
+	}
 
 	mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID;
 	mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON;
@@ -2062,9 +2237,6 @@ bwn_core_init(struct bwn_mac *mac)
 
 	mac->mac_phy.init_pre(mac);
 
-	siba_pcicore_intr(sc->sc_dev);
-
-	siba_fix_imcfglobug(sc->sc_dev);
 	bwn_bt_disable(mac);
 	if (mac->mac_phy.prepare_hw) {
 		error = mac->mac_phy.prepare_hw(mac);
@@ -2076,11 +2248,11 @@ bwn_core_init(struct bwn_mac *mac)
 	if (error)
 		goto fail0;
 	bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_COREREV,
-	    siba_get_revid(sc->sc_dev));
+	    bhnd_get_hwrev(sc->sc_dev));
 	hf = bwn_hf_read(mac);
 	if (mac->mac_phy.type == BWN_PHYTYPE_G) {
 		hf |= BWN_HF_GPHY_SYM_WORKAROUND;
-		if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL)
+		if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL)
 			hf |= BWN_HF_PAGAINBOOST_OFDM_ON;
 		if (mac->mac_phy.rev == 1)
 			hf |= BWN_HF_GPHY_DC_CANCELFILTER;
@@ -2091,16 +2263,15 @@ bwn_core_init(struct bwn_mac *mac)
 		if (mac->mac_phy.rf_rev == 6)
 			hf |= BWN_HF_4318_TSSI;
 	}
-	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW)
+	if (sc->sc_board_info.board_flags & BHND_BFL_NOPLLDOWN)
 		hf |= BWN_HF_SLOWCLOCK_REQ_OFF;
-	if ((siba_get_type(sc->sc_dev) == SIBA_TYPE_PCI) &&
-	    (siba_get_pcicore_revid(sc->sc_dev) <= 10))
+	if (sc->sc_quirks & BWN_QUIRK_UCODE_SLOWCLOCK_WAR)
 		hf |= BWN_HF_PCI_SLOWCLOCK_WORKAROUND;
 	hf &= ~BWN_HF_SKIP_CFP_UPDATE;
 	bwn_hf_write(mac, hf);
 
 	/* Tell the firmware about the MAC capabilities */
-	if (siba_get_revid(sc->sc_dev) >= 13) {
+	if (bhnd_get_hwrev(sc->sc_dev) >= 13) {
 		uint32_t cap;
 		cap = BWN_READ_4(mac, BWN_MAC_HW_CAP);
 		DPRINTF(sc, BWN_DEBUG_RESET,
@@ -2124,7 +2295,7 @@ bwn_core_init(struct bwn_mac *mac)
 	    (mac->mac_phy.type == BWN_PHYTYPE_B) ? 0x1f : 0xf);
 	bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MAX, 0x3ff);
 
-	if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0)
+	if (sc->sc_quirks & BWN_QUIRK_NODMA)
 		bwn_pio_init(mac);
 	else
 		bwn_dma_init(mac);
@@ -2133,8 +2304,11 @@ bwn_core_init(struct bwn_mac *mac)
 	bwn_bt_enable(mac);
 
 	DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: powerup\n", __func__);
-	siba_powerup(sc->sc_dev,
-	    !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW));
+	if (sc->sc_board_info.board_flags & BHND_BFL_NOPLLDOWN)
+		bwn_core_forceclk(mac, true);
+	else
+		bwn_core_forceclk(mac, false);
+
 	bwn_set_macaddr(mac);
 	bwn_crypt_init(mac);
 
@@ -2146,7 +2320,7 @@ bwn_core_init(struct bwn_mac *mac)
 	return (error);
 
 fail0:
-	siba_powerdown(sc->sc_dev);
+	bhnd_suspend_hw(sc->sc_dev, 0);
 	KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT,
 	    ("%s:%d: fail", __func__, __LINE__));
 	DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: fail\n", __func__);
@@ -2162,7 +2336,7 @@ bwn_core_start(struct bwn_mac *mac)
 	KASSERT(mac->mac_status == BWN_MAC_STATUS_INITED,
 	    ("%s:%d: fail", __func__, __LINE__));
 
-	if (siba_get_revid(sc->sc_dev) < 5)
+	if (bhnd_get_hwrev(sc->sc_dev) < 5)
 		return;
 
 	while (1) {
@@ -2203,8 +2377,7 @@ bwn_core_exit(struct bwn_mac *mac)
 	bwn_pio_stop(mac);
 	bwn_chip_exit(mac);
 	mac->mac_phy.switch_analog(mac, 0);
-	siba_dev_down(sc->sc_dev, 0);
-	siba_powerdown(sc->sc_dev);
+	bhnd_suspend_hw(sc->sc_dev, 0);
 }
 
 static void
@@ -2222,6 +2395,7 @@ bwn_chip_init(struct bwn_mac *mac)
 	struct bwn_softc *sc = mac->mac_sc;
 	struct bwn_phy *phy = &mac->mac_phy;
 	uint32_t macctl;
+	u_int delay;
 	int error;
 
 	macctl = BWN_MACCTL_IHR_ON | BWN_MACCTL_SHM_ON | BWN_MACCTL_STA;
@@ -2241,16 +2415,14 @@ bwn_chip_init(struct bwn_mac *mac)
 		return (error);
 
 	error = bwn_fw_loadinitvals(mac);
-	if (error) {
-		siba_gpio_set(sc->sc_dev, 0);
+	if (error)
 		return (error);
-	}
+
 	phy->switch_analog(mac, 1);
 	error = bwn_phy_init(mac);
-	if (error) {
-		siba_gpio_set(sc->sc_dev, 0);
+	if (error)
 		return (error);
-	}
+
 	if (phy->set_im)
 		phy->set_im(mac, BWN_IMMODE_NONE);
 	if (phy->set_antenna)
@@ -2260,7 +2432,7 @@ bwn_chip_init(struct bwn_mac *mac)
 	if (phy->type == BWN_PHYTYPE_B)
 		BWN_WRITE_2(mac, 0x005e, BWN_READ_2(mac, 0x005e) | 0x0004);
 	BWN_WRITE_4(mac, 0x0100, 0x01000000);
-	if (siba_get_revid(sc->sc_dev) < 5)
+	if (bhnd_get_hwrev(sc->sc_dev) < 5)
 		BWN_WRITE_4(mac, 0x010c, 0x01000000);
 
 	BWN_WRITE_4(mac, BWN_MACCTL,
@@ -2270,7 +2442,7 @@ bwn_chip_init(struct bwn_mac *mac)
 	bwn_shm_write_2(mac, BWN_SHARED, 0x0074, 0x0000);
 
 	bwn_set_opmode(mac);
-	if (siba_get_revid(sc->sc_dev) < 3) {
+	if (bhnd_get_hwrev(sc->sc_dev) < 3) {
 		BWN_WRITE_2(mac, 0x060e, 0x0000);
 		BWN_WRITE_2(mac, 0x0610, 0x8000);
 		BWN_WRITE_2(mac, 0x0604, 0x0000);
@@ -2289,9 +2461,22 @@ bwn_chip_init(struct bwn_mac *mac)
 
 	bwn_mac_phy_clock_set(mac, true);
 
-	/* SIBA powerup */
-	BWN_WRITE_2(mac, BWN_POWERUP_DELAY, siba_get_cc_powerdelay(sc->sc_dev));
-	return (error);
+	/* Provide the HT clock transition latency to the MAC core */
+	error = bhnd_get_clock_latency(sc->sc_dev, BHND_CLOCK_HT, &delay);
+	if (error) {
+		device_printf(sc->sc_dev, "failed to fetch HT clock latency: "
+		    "%d\n", error);
+		return (error);
+	}
+
+	if (delay > UINT16_MAX) {
+		device_printf(sc->sc_dev, "invalid HT clock latency: %u\n",
+		    delay);
+		return (ENXIO);
+	}
+
+	BWN_WRITE_2(mac, BWN_POWERUP_DELAY, delay);
+	return (0);
 }
 
 /* read hostflags */
@@ -2459,7 +2644,7 @@ bwn_pio_set_txqueue(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
 	tq->tq_index = index;
 
 	tq->tq_free = BWN_PIO_MAX_TXPACKETS;
-	if (siba_get_revid(sc->sc_dev) >= 8)
+	if (bhnd_get_hwrev(sc->sc_dev) >= 8)
 		tq->tq_size = 1920;
 	else {
 		tq->tq_size = bwn_pio_read_2(mac, tq, BWN_PIO_TXQBUFSIZE);
@@ -2498,7 +2683,7 @@ bwn_pio_idx2base(struct bwn_mac *mac, int index)
 		BWN_PIO11_BASE5,
 	};
 
-	if (siba_get_revid(sc->sc_dev) >= 11) {
+	if (bhnd_get_hwrev(sc->sc_dev) >= 11) {
 		if (index >= N(bases_rev11))
 			device_printf(sc->sc_dev, "%s: warning\n", __func__);
 		return (bases_rev11[index]);
@@ -2515,7 +2700,7 @@ bwn_pio_setupqueue_rx(struct bwn_mac *mac, struct bwn_pio_rxqueue *prq,
 	struct bwn_softc *sc = mac->mac_sc;
 
 	prq->prq_mac = mac;
-	prq->prq_rev = siba_get_revid(sc->sc_dev);
+	prq->prq_rev = bhnd_get_hwrev(sc->sc_dev);
 	prq->prq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_RXQOFFSET(mac);
 	bwn_dma_rxdirectfifo(mac, index, 1);
 }
@@ -2547,12 +2732,10 @@ static void
 bwn_dma_rxdirectfifo(struct bwn_mac *mac, int idx, uint8_t enable)
 {
 	uint32_t ctl;
-	int type;
 	uint16_t base;
 
-	type = bwn_dma_mask2type(bwn_dma_mask(mac));
-	base = bwn_dma_base(type, idx);
-	if (type == BWN_DMA_64BIT) {
+	base = bwn_dma_base(mac->mac_dmatype, idx);
+	if (mac->mac_dmatype == BHND_DMA_ADDR_64BIT) {
 		ctl = BWN_READ_4(mac, base + BWN_DMA64_RXCTL);
 		ctl &= ~BWN_DMA64_RXDIRECTFIFO;
 		if (enable)
@@ -2567,38 +2750,6 @@ bwn_dma_rxdirectfifo(struct bwn_mac *mac, int idx, uint8_t enable)
 	}
 }
 
-static uint64_t
-bwn_dma_mask(struct bwn_mac *mac)
-{
-	uint32_t tmp;
-	uint16_t base;
-
-	tmp = BWN_READ_4(mac, SIBA_TGSHIGH);
-	if (tmp & SIBA_TGSHIGH_DMA64)
-		return (BWN_DMA_BIT_MASK(64));
-	base = bwn_dma_base(0, 0);
-	BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, BWN_DMA32_TXADDREXT_MASK);
-	tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL);
-	if (tmp & BWN_DMA32_TXADDREXT_MASK)
-		return (BWN_DMA_BIT_MASK(32));
-
-	return (BWN_DMA_BIT_MASK(30));
-}
-
-static int
-bwn_dma_mask2type(uint64_t dmamask)
-{
-
-	if (dmamask == BWN_DMA_BIT_MASK(30))
-		return (BWN_DMA_30BIT);
-	if (dmamask == BWN_DMA_BIT_MASK(32))
-		return (BWN_DMA_32BIT);
-	if (dmamask == BWN_DMA_BIT_MASK(64))
-		return (BWN_DMA_64BIT);
-	KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
-	return (BWN_DMA_30BIT);
-}
-
 static void
 bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *tq)
 {
@@ -2634,7 +2785,7 @@ bwn_dma_base(int type, int controller_idx)
 		BWN_DMA32_BASE5,
 	};
 
-	if (type == BWN_DMA_64BIT) {
+	if (type == BHND_DMA_ADDR_64BIT) {
 		KASSERT(controller_idx >= 0 && controller_idx < N(map64),
 		    ("%s:%d: fail", __func__, __LINE__));
 		return (map64[controller_idx]);
@@ -2661,7 +2812,7 @@ bwn_dma_init(struct bwn_mac *mac)
 
 static struct bwn_dma_ring *
 bwn_dma_ringsetup(struct bwn_mac *mac, int controller_index,
-    int for_tx, int type)
+    int for_tx)
 {
 	struct bwn_dma *dma = &mac->mac_method.dma;
 	struct bwn_dma_ring *dr;
@@ -2682,11 +2833,11 @@ bwn_dma_ringsetup(struct bwn_mac *mac, int controller_index,
 	if (dr->dr_meta == NULL)
 		goto fail0;
 
-	dr->dr_type = type;
+	dr->dr_type = mac->mac_dmatype;
 	dr->dr_mac = mac;
-	dr->dr_base = bwn_dma_base(type, controller_index);
+	dr->dr_base = bwn_dma_base(dr->dr_type, controller_index);
 	dr->dr_index = controller_index;
-	if (type == BWN_DMA_64BIT) {
+	if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
 		dr->getdesc = bwn_dma_64_getdesc;
 		dr->setdesc = bwn_dma_64_setdesc;
 		dr->start_transfer = bwn_dma_64_start_transfer;
@@ -2886,18 +3037,22 @@ bwn_dma_32_setdesc(struct bwn_dma_ring *dr,
     struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize,
     int start, int end, int irq)
 {
-	struct bwn_dmadesc32 *descbase = dr->dr_ring_descbase;
-	struct bwn_softc *sc = dr->dr_mac->mac_sc;
-	uint32_t addr, addrext, ctl;
-	int slot;
+	struct bwn_dmadesc32		*descbase;
+	struct bwn_dma			*dma;
+	struct bhnd_dma_translation	*dt;
+	uint32_t			 addr, addrext, ctl;
+	int				 slot;
+	
+	descbase = dr->dr_ring_descbase;
+	dma = &dr->dr_mac->mac_method.dma;
+	dt = &dma->translation;
 
 	slot = (int)(&(desc->dma.dma32) - descbase);
 	KASSERT(slot >= 0 && slot < dr->dr_numslots,
 	    ("%s:%d: fail", __func__, __LINE__));
 
-	addr = (uint32_t) (dmaaddr & ~SIBA_DMA_TRANSLATION_MASK);
-	addrext = (uint32_t) (dmaaddr & SIBA_DMA_TRANSLATION_MASK) >> 30;
-	addr |= siba_dma_translation(sc->sc_dev);
+	addr = (dmaaddr & dt->addr_mask) | dt->base_addr;
+	addrext = ((dmaaddr & dt->addrext_mask) >> dma->addrext_shift);
 	ctl = bufsize & BWN_DMA32_DCTL_BYTECNT;
 	if (slot == dr->dr_numslots - 1)
 		ctl |= BWN_DMA32_DCTL_DTABLEEND;
@@ -2975,22 +3130,30 @@ bwn_dma_64_setdesc(struct bwn_dma_ring *dr,
     struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize,
     int start, int end, int irq)
 {
-	struct bwn_dmadesc64 *descbase = dr->dr_ring_descbase;
-	struct bwn_softc *sc = dr->dr_mac->mac_sc;
-	int slot;
-	uint32_t ctl0 = 0, ctl1 = 0;
-	uint32_t addrlo, addrhi;
-	uint32_t addrext;
+	struct bwn_dmadesc64		*descbase;
+	struct bwn_dma			*dma;
+	struct bhnd_dma_translation	*dt;
+	bhnd_addr_t			 addr;
+	uint32_t			 addrhi, addrlo;
+	uint32_t			 addrext;
+	uint32_t			 ctl0, ctl1;
+	int				 slot;
+	
+	
+	descbase = dr->dr_ring_descbase;
+	dma = &dr->dr_mac->mac_method.dma;
+	dt = &dma->translation;
 
 	slot = (int)(&(desc->dma.dma64) - descbase);
 	KASSERT(slot >= 0 && slot < dr->dr_numslots,
 	    ("%s:%d: fail", __func__, __LINE__));
 
-	addrlo = (uint32_t) (dmaaddr & 0xffffffff);
-	addrhi = (((uint64_t) dmaaddr >> 32) & ~SIBA_DMA_TRANSLATION_MASK);
-	addrext = (((uint64_t) dmaaddr >> 32) & SIBA_DMA_TRANSLATION_MASK) >>
-	    30;
-	addrhi |= (siba_dma_translation(sc->sc_dev) << 1);
+	addr = (dmaaddr & dt->addr_mask) | dt->base_addr;
+	addrhi = (addr >> 32);
+	addrlo = (addr & UINT32_MAX);
+	addrext = ((dmaaddr & dt->addrext_mask) >> dma->addrext_shift);
+
+	ctl0 = 0;
 	if (slot == dr->dr_numslots - 1)
 		ctl0 |= BWN_DMA64_DCTL0_DTABLEEND;
 	if (start)
@@ -2999,6 +3162,8 @@ bwn_dma_64_setdesc(struct bwn_dma_ring *dr,
 		ctl0 |= BWN_DMA64_DCTL0_FRAMEEND;
 	if (irq)
 		ctl0 |= BWN_DMA64_DCTL0_IRQ;
+
+	ctl1 = 0;
 	ctl1 |= bufsize & BWN_DMA64_DCTL1_BYTECNT;
 	ctl1 |= (addrext << BWN_DMA64_DCTL1_ADDREXT_SHIFT)
 	    & BWN_DMA64_DCTL1_ADDREXT_MASK;
@@ -3100,38 +3265,40 @@ bwn_dma_allocringmemory(struct bwn_dma_ring *dr)
 static void
 bwn_dma_setup(struct bwn_dma_ring *dr)
 {
-	struct bwn_softc *sc = dr->dr_mac->mac_sc;
-	uint64_t ring64;
-	uint32_t addrext, ring32, value;
-	uint32_t trans = siba_dma_translation(sc->sc_dev);
+	struct bwn_mac			*mac;
+	struct bwn_dma			*dma;
+	struct bhnd_dma_translation	*dt;
+	bhnd_addr_t			 addr, paddr;
+	uint32_t			 addrhi, addrlo, addrext, value;
+
+	mac = dr->dr_mac;
+	dma = &mac->mac_method.dma;
+	dt = &dma->translation;
+
+	paddr = dr->dr_ring_dmabase;
+	addr = (paddr & dt->addr_mask) | dt->base_addr;
+	addrhi = (addr >> 32);
+	addrlo = (addr & UINT32_MAX);
+	addrext = ((paddr & dt->addrext_mask) >> dma->addrext_shift);
 
 	if (dr->dr_tx) {
 		dr->dr_curslot = -1;
 
-		if (dr->dr_type == BWN_DMA_64BIT) {
-			ring64 = (uint64_t)(dr->dr_ring_dmabase);
-			addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK)
-			    >> 30;
+		if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
 			value = BWN_DMA64_TXENABLE;
 			value |= BWN_DMA64_TXPARITY_DISABLE;
 			value |= (addrext << BWN_DMA64_TXADDREXT_SHIFT)
 			    & BWN_DMA64_TXADDREXT_MASK;
 			BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, value);
-			BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO,
-			    (ring64 & 0xffffffff));
-			BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI,
-			    ((ring64 >> 32) &
-			    ~SIBA_DMA_TRANSLATION_MASK) | (trans << 1));
+			BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, addrlo);
+			BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, addrhi);
 		} else {
-			ring32 = (uint32_t)(dr->dr_ring_dmabase);
-			addrext = (ring32 & SIBA_DMA_TRANSLATION_MASK) >> 30;
 			value = BWN_DMA32_TXENABLE;
 			value |= BWN_DMA32_TXPARITY_DISABLE;
 			value |= (addrext << BWN_DMA32_TXADDREXT_SHIFT)
 			    & BWN_DMA32_TXADDREXT_MASK;
 			BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, value);
-			BWN_DMA_WRITE(dr, BWN_DMA32_TXRING,
-			    (ring32 & ~SIBA_DMA_TRANSLATION_MASK) | trans);
+			BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, addrlo);
 		}
 		return;
 	}
@@ -3141,32 +3308,25 @@ bwn_dma_setup(struct bwn_dma_ring *dr)
 	 */
 	dr->dr_usedslot = dr->dr_numslots;
 
-	if (dr->dr_type == BWN_DMA_64BIT) {
-		ring64 = (uint64_t)(dr->dr_ring_dmabase);
-		addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK) >> 30;
+	if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
 		value = (dr->dr_frameoffset << BWN_DMA64_RXFROFF_SHIFT);
 		value |= BWN_DMA64_RXENABLE;
 		value |= BWN_DMA64_RXPARITY_DISABLE;
 		value |= (addrext << BWN_DMA64_RXADDREXT_SHIFT)
 		    & BWN_DMA64_RXADDREXT_MASK;
 		BWN_DMA_WRITE(dr, BWN_DMA64_RXCTL, value);
-		BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, (ring64 & 0xffffffff));
-		BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI,
-		    ((ring64 >> 32) & ~SIBA_DMA_TRANSLATION_MASK)
-		    | (trans << 1));
+		BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, addrlo);
+		BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, addrhi);
 		BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX, dr->dr_numslots *
 		    sizeof(struct bwn_dmadesc64));
 	} else {
-		ring32 = (uint32_t)(dr->dr_ring_dmabase);
-		addrext = (ring32 & SIBA_DMA_TRANSLATION_MASK) >> 30;
 		value = (dr->dr_frameoffset << BWN_DMA32_RXFROFF_SHIFT);
 		value |= BWN_DMA32_RXENABLE;
 		value |= BWN_DMA32_RXPARITY_DISABLE;
 		value |= (addrext << BWN_DMA32_RXADDREXT_SHIFT)
 		    & BWN_DMA32_RXADDREXT_MASK;
 		BWN_DMA_WRITE(dr, BWN_DMA32_RXCTL, value);
-		BWN_DMA_WRITE(dr, BWN_DMA32_RXRING,
-		    (ring32 & ~SIBA_DMA_TRANSLATION_MASK) | trans);
+		BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, addrlo);
 		BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX, dr->dr_numslots *
 		    sizeof(struct bwn_dmadesc32));
 	}
@@ -3187,14 +3347,14 @@ bwn_dma_cleanup(struct bwn_dma_ring *dr)
 
 	if (dr->dr_tx) {
 		bwn_dma_tx_reset(dr->dr_mac, dr->dr_base, dr->dr_type);
-		if (dr->dr_type == BWN_DMA_64BIT) {
+		if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
 			BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, 0);
 			BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, 0);
 		} else
 			BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, 0);
 	} else {
 		bwn_dma_rx_reset(dr->dr_mac, dr->dr_base, dr->dr_type);
-		if (dr->dr_type == BWN_DMA_64BIT) {
+		if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
 			BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, 0);
 			BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, 0);
 		} else
@@ -3246,10 +3406,10 @@ bwn_dma_tx_reset(struct bwn_mac *mac, uint16_t base,
 	uint16_t offset;
 
 	for (i = 0; i < 10; i++) {
-		offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXSTATUS :
+		offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXSTATUS :
 		    BWN_DMA32_TXSTATUS;
 		value = BWN_READ_4(mac, base + offset);
-		if (type == BWN_DMA_64BIT) {
+		if (type == BHND_DMA_ADDR_64BIT) {
 			value &= BWN_DMA64_TXSTAT;
 			if (value == BWN_DMA64_TXSTAT_DISABLED ||
 			    value == BWN_DMA64_TXSTAT_IDLEWAIT ||
@@ -3264,13 +3424,14 @@ bwn_dma_tx_reset(struct bwn_mac *mac, uint16_t base,
 		}
 		DELAY(1000);
 	}
-	offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXCTL : BWN_DMA32_TXCTL;
+	offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXCTL :
+	    BWN_DMA32_TXCTL;
 	BWN_WRITE_4(mac, base + offset, 0);
 	for (i = 0; i < 10; i++) {
-		offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXSTATUS :
-						   BWN_DMA32_TXSTATUS;
+		offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXSTATUS :
+		    BWN_DMA32_TXSTATUS;
 		value = BWN_READ_4(mac, base + offset);
-		if (type == BWN_DMA_64BIT) {
+		if (type == BHND_DMA_ADDR_64BIT) {
 			value &= BWN_DMA64_TXSTAT;
 			if (value == BWN_DMA64_TXSTAT_DISABLED) {
 				i = -1;
@@ -3303,13 +3464,14 @@ bwn_dma_rx_reset(struct bwn_mac *mac, uint16_t base,
 	int i;
 	uint16_t offset;
 
-	offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_RXCTL : BWN_DMA32_RXCTL;
+	offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_RXCTL :
+	    BWN_DMA32_RXCTL;
 	BWN_WRITE_4(mac, base + offset, 0);
 	for (i = 0; i < 10; i++) {
-		offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_RXSTATUS :
+		offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_RXSTATUS :
 		    BWN_DMA32_RXSTATUS;
 		value = BWN_READ_4(mac, base + offset);
-		if (type == BWN_DMA_64BIT) {
+		if (type == BHND_DMA_ADDR_64BIT) {
 			value &= BWN_DMA64_RXSTAT;
 			if (value == BWN_DMA64_RXSTAT_DISABLED) {
 				i = -1;
@@ -3408,13 +3570,13 @@ bwn_bt_enable(struct bwn_mac *mac)
 
 	if (bwn_bluetooth == 0)
 		return;
-	if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCOEXIST) == 0)
+	if ((sc->sc_board_info.board_flags & BHND_BFL_BTCOEX) == 0)
 		return;
 	if (mac->mac_phy.type != BWN_PHYTYPE_B && !mac->mac_phy.gmode)
 		return;
 
 	hf = bwn_hf_read(mac);
-	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCMOD)
+	if (sc->sc_board_info.board_flags & BHND_BFL_BTC2WIRE_ALTGPIO)
 		hf |= BWN_HF_BT_COEXISTALT;
 	else
 		hf |= BWN_HF_BT_COEXIST;
@@ -3454,12 +3616,12 @@ bwn_crypt_init(struct bwn_mac *mac)
 {
 	struct bwn_softc *sc = mac->mac_sc;
 
-	mac->mac_max_nr_keys = (siba_get_revid(sc->sc_dev) >= 5) ? 58 : 20;
+	mac->mac_max_nr_keys = (bhnd_get_hwrev(sc->sc_dev) >= 5) ? 58 : 20;
 	KASSERT(mac->mac_max_nr_keys <= N(mac->mac_key),
 	    ("%s:%d: fail", __func__, __LINE__));
 	mac->mac_ktp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_KEY_TABLEP);
 	mac->mac_ktp *= 2;
-	if (siba_get_revid(sc->sc_dev) >= 5)
+	if (bhnd_get_hwrev(sc->sc_dev) >= 5)
 		BWN_WRITE_2(mac, BWN_RCMTA_COUNT, mac->mac_max_nr_keys - 8);
 	bwn_clear_keys(mac);
 }
@@ -3467,10 +3629,7 @@ bwn_crypt_init(struct bwn_mac *mac)
 static void
 bwn_chip_exit(struct bwn_mac *mac)
 {
-	struct bwn_softc *sc = mac->mac_sc;
-
 	bwn_phy_exit(mac);
-	siba_gpio_set(sc->sc_dev, 0);
 }
 
 static int
@@ -3487,36 +3646,72 @@ bwn_fw_fillinfo(struct bwn_mac *mac)
 	return (error);
 }
 
+/**
+ * Request that the GPIO controller tristate all pins set in @p mask, granting
+ * the MAC core control over the pins.
+ * 
+ * @param mac	bwn MAC state.
+ * @param pins	If the bit position for a pin number is set to one, tristate the
+ *		pin.
+ */
+int
+bwn_gpio_control(struct bwn_mac *mac, uint32_t pins)
+{
+	struct bwn_softc	*sc;
+	uint32_t		 flags[32];
+	int			 error;
+
+	sc = mac->mac_sc;
+
+	/* Determine desired pin flags */
+	for (size_t pin = 0; pin < nitems(flags); pin++) {
+		uint32_t pinbit = (1 << pin);
+
+		if (pins & pinbit) {
+			/* Tristate output */
+			flags[pin] = GPIO_PIN_OUTPUT|GPIO_PIN_TRISTATE;
+		} else {
+			/* Leave unmodified */
+			flags[pin] = 0;
+		}
+	}
+
+	/* Configure all pins */
+	error = GPIO_PIN_CONFIG_32(sc->sc_gpio, 0, nitems(flags), flags);
+	if (error) {
+		device_printf(sc->sc_dev, "error configuring %s pin flags: "
+		    "%d\n", device_get_nameunit(sc->sc_gpio), error);
+		return (error);
+	}
+
+	return (0);
+}
+
+
 static int
 bwn_gpio_init(struct bwn_mac *mac)
 {
-	struct bwn_softc *sc = mac->mac_sc;
-	uint32_t mask = 0x1f, set = 0xf, value;
+	struct bwn_softc	*sc;
+	uint32_t		 pins;
+
+	sc = mac->mac_sc;
+
+	pins = 0xF;
 
 	BWN_WRITE_4(mac, BWN_MACCTL,
 	    BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GPOUT_MASK);
 	BWN_WRITE_2(mac, BWN_GPIO_MASK,
-	    BWN_READ_2(mac, BWN_GPIO_MASK) | 0x000f);
+	    BWN_READ_2(mac, BWN_GPIO_MASK) | pins);
 
-	if (siba_get_chipid(sc->sc_dev) == 0x4301) {
-		mask |= 0x0060;
-		set |= 0x0060;
-	}
-	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL) {
+	if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL) {
+		/* MAC core is responsible for toggling PAREF via gpio9 */
 		BWN_WRITE_2(mac, BWN_GPIO_MASK,
-		    BWN_READ_2(mac, BWN_GPIO_MASK) | 0x0200);
-		mask |= 0x0200;
-		set |= 0x0200;
-	}
-	if (siba_get_revid(sc->sc_dev) >= 2)
-		mask |= 0x0010;
+		    BWN_READ_2(mac, BWN_GPIO_MASK) | BHND_GPIO_BOARD_PACTRL);
 
-	value = siba_gpio_get(sc->sc_dev);
-	if (value == -1)
-		return (0);
-	siba_gpio_set(sc->sc_dev, (value & mask) | set);
+		pins |= BHND_GPIO_BOARD_PACTRL;
+	}
 
-	return (0);
+	return (bwn_gpio_control(mac, pins));
 }
 
 static int
@@ -3614,15 +3809,15 @@ bwn_set_opmode(struct bwn_mac *mac)
 		ctl &= ~BWN_MACCTL_STA;
 	ctl |= sc->sc_filters;
 
-	if (siba_get_revid(sc->sc_dev) <= 4)
+	if (bhnd_get_hwrev(sc->sc_dev) <= 4)
 		ctl |= BWN_MACCTL_PROMISC;
 
 	BWN_WRITE_4(mac, BWN_MACCTL, ctl);
 
 	cfp_pretbtt = 2;
 	if ((ctl & BWN_MACCTL_STA) && !(ctl & BWN_MACCTL_HOSTAP)) {
-		if (siba_get_chipid(sc->sc_dev) == 0x4306 &&
-		    siba_get_chiprev(sc->sc_dev) == 3)
+		if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4306 &&
+		    sc->sc_cid.chip_rev == 3)
 			cfp_pretbtt = 100;
 		else
 			cfp_pretbtt = 50;
@@ -3630,24 +3825,6 @@ bwn_set_opmode(struct bwn_mac *mac)
 	BWN_WRITE_2(mac, 0x612, cfp_pretbtt);
 }
 
-static int
-bwn_dma_gettype(struct bwn_mac *mac)
-{
-	uint32_t tmp;
-	uint16_t base;
-
-	tmp = BWN_READ_4(mac, SIBA_TGSHIGH);
-	if (tmp & SIBA_TGSHIGH_DMA64)
-		return (BWN_DMA_64BIT);
-	base = bwn_dma_base(0, 0);
-	BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, BWN_DMA32_TXADDREXT_MASK);
-	tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL);
-	if (tmp & BWN_DMA32_TXADDREXT_MASK)
-		return (BWN_DMA_32BIT);
-
-	return (BWN_DMA_30BIT);
-}
-
 static void
 bwn_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
 {
@@ -3683,7 +3860,7 @@ bwn_dummy_transmission(struct bwn_mac *mac, int ofdm, int paon)
 
 	BWN_WRITE_2(mac, 0x0568, 0x0000);
 	BWN_WRITE_2(mac, 0x07c0,
-	    (siba_get_revid(sc->sc_dev) < 11) ? 0x0000 : 0x0100);
+	    (bhnd_get_hwrev(sc->sc_dev) < 11) ? 0x0000 : 0x0100);
 
 	value = (ofdm ? 0x41 : 0x40);
 	BWN_WRITE_2(mac, 0x050c, value);
@@ -3752,7 +3929,7 @@ bwn_ram_write(struct bwn_mac *mac, uint16_t offset, uint32_t val)
 		printf("TODO: need swap\n");
 
 	BWN_WRITE_4(mac, BWN_RAM_CONTROL, offset);
-	BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE);
+	BWN_BARRIER(mac, BWN_RAM_CONTROL, 4, BUS_SPACE_BARRIER_WRITE);
 	BWN_WRITE_4(mac, BWN_RAM_DATA, val);
 }
 
@@ -3842,7 +4019,7 @@ bwn_psctl(struct bwn_mac *mac, uint32_t flags)
 	    (BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_AWAKE) &
 	    ~BWN_MACCTL_HWPS);
 	BWN_READ_4(mac, BWN_MACCTL);
-	if (siba_get_revid(sc->sc_dev) >= 5) {
+	if (bhnd_get_hwrev(sc->sc_dev) >= 5) {
 		for (i = 0; i < 100; i++) {
 			ucstat = bwn_shm_read_2(mac, BWN_SHARED,
 			    BWN_SHARED_UCODESTAT);
@@ -3860,9 +4037,9 @@ bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type)
 {
 	struct bwn_softc *sc = mac->mac_sc;
 	struct bwn_fw *fw = &mac->mac_fw;
-	const uint8_t rev = siba_get_revid(sc->sc_dev);
+	const uint8_t rev = bhnd_get_hwrev(sc->sc_dev);
 	const char *filename;
-	uint32_t high;
+	uint16_t iost;
 	int error;
 
 	/* microcode */
@@ -3967,12 +4144,15 @@ bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type)
 	}
 
 	/* initvals */
-	high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH);
+	error = bhnd_read_iost(sc->sc_dev, &iost);
+	if (error)
+		goto fail1;
+
 	switch (mac->mac_phy.type) {
 	case BWN_PHYTYPE_A:
 		if (rev < 5 || rev > 10)
 			goto fail1;
-		if (high & BWN_TGSHIGH_HAVE_2GHZ)
+		if (iost & BWN_IOST_HAVE_2GHZ)
 			filename = "a0g1initvals5";
 		else
 			filename = "a0g0initvals5";
@@ -4024,7 +4204,7 @@ bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type)
 	switch (mac->mac_phy.type) {
 	case BWN_PHYTYPE_A:
 		if (rev >= 5 && rev <= 10) {
-			if (high & BWN_TGSHIGH_HAVE_2GHZ)
+			if (iost & BWN_IOST_HAVE_2GHZ)
 				filename = "a0g1bsinitvals5";
 			else
 				filename = "a0g0bsinitvals5";
@@ -4569,7 +4749,7 @@ bwn_key_macwrite(struct bwn_mac *mac, uint8_t index, const uint8_t *addr)
 		addrtmp[1] |= ((uint32_t) (addr[5]) << 8);
 	}
 
-	if (siba_get_revid(sc->sc_dev) >= 5) {
+	if (bhnd_get_hwrev(sc->sc_dev) >= 5) {
 		bwn_shm_write_4(mac, BWN_RCMTA, (index * 2) + 0, addrtmp[0]);
 		bwn_shm_write_2(mac, BWN_RCMTA, (index * 2) + 1, addrtmp[1]);
 	} else {
@@ -4694,8 +4874,11 @@ bwn_switch_band(struct bwn_softc *sc, struct ieee80211_channel *chan)
 	if (status >= BWN_MAC_STATUS_INITED)
 		bwn_core_exit(down_dev);
 
-	if (down_dev != up_dev)
-		bwn_phy_reset(down_dev);
+	if (down_dev != up_dev) {
+		err = bwn_phy_reset(down_dev);
+		if (err)
+			goto fail;
+	}
 
 	up_dev->mac_phy.gmode = gmode;
 	if (status >= BWN_MAC_STATUS_INITED) {
@@ -4745,18 +4928,31 @@ bwn_rf_turnoff(struct bwn_mac *mac)
 /*
  * PHY reset.
  */
-static void
+static int
 bwn_phy_reset(struct bwn_mac *mac)
 {
-	struct bwn_softc *sc = mac->mac_sc;
+	struct bwn_softc	*sc;
+	uint16_t		 iost, mask;
+	int			 error;
+
+	sc = mac->mac_sc;
+
+	iost = BWN_IOCTL_PHYRESET | BHND_IOCTL_CLK_FORCE;
+	mask = iost | BWN_IOCTL_SUPPORT_G;
+
+	if ((error = bhnd_write_ioctl(sc->sc_dev, iost, mask)))
+		return (error);
 
-	siba_write_4(sc->sc_dev, SIBA_TGSLOW,
-	    ((siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~BWN_TGSLOW_SUPPORT_G) |
-	     BWN_TGSLOW_PHYRESET) | SIBA_TGSLOW_FGC);
 	DELAY(1000);
-	siba_write_4(sc->sc_dev, SIBA_TGSLOW,
-	    (siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~SIBA_TGSLOW_FGC));
+
+	iost &= ~BHND_IOCTL_CLK_FORCE;
+
+	if ((error = bhnd_write_ioctl(sc->sc_dev, iost, mask)))
+		return (error);
+
 	DELAY(1000);
+
+	return (0);
 }
 
 static int
@@ -4868,8 +5064,7 @@ bwn_intr(void *arg)
 
 	mac->mac_reason_intr = reason;
 
-	BWN_BARRIER(mac, BUS_SPACE_BARRIER_READ);
-	BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE);
+	BWN_BARRIER(mac, 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
 
 	taskqueue_enqueue(sc->sc_tq, &mac->mac_intrtask);
 	return (FILTER_HANDLED);
@@ -4982,8 +5177,7 @@ bwn_intrtask(void *arg, int npending)
 	if (mbufq_first(&sc->sc_snd) != NULL)
 		bwn_start(sc);
 
-	BWN_BARRIER(mac, BUS_SPACE_BARRIER_READ);
-	BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE);
+	BWN_BARRIER(mac, 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
 
 	BWN_UNLOCK(sc);
 }
@@ -5512,12 +5706,15 @@ bwn_pio_rxeof(struct bwn_pio_rxqueue *prq)
 	device_printf(sc->sc_dev, "%s: timed out\n", __func__);
 	return (1);
 ready:
-	if (prq->prq_rev >= 8)
-		siba_read_multi_4(sc->sc_dev, &rxhdr, sizeof(rxhdr),
-		    prq->prq_base + BWN_PIO8_RXDATA);
-	else
-		siba_read_multi_2(sc->sc_dev, &rxhdr, sizeof(rxhdr),
-		    prq->prq_base + BWN_PIO_RXDATA);
+	if (prq->prq_rev >= 8) {
+		bus_read_multi_4(sc->sc_mem_res,
+		    prq->prq_base + BWN_PIO8_RXDATA, (void *)&rxhdr,
+		    sizeof(rxhdr));
+	} else {
+		bus_read_multi_2(sc->sc_mem_res,
+		    prq->prq_base + BWN_PIO_RXDATA, (void *)&rxhdr,
+		    sizeof(rxhdr));
+	}
 	len = le16toh(rxhdr.frame_len);
 	if (len > 0x700) {
 		device_printf(sc->sc_dev, "%s: len is too big\n", __func__);
@@ -5555,8 +5752,8 @@ ready:
 	}
 	mp = mtod(m, unsigned char *);
 	if (prq->prq_rev >= 8) {
-		siba_read_multi_4(sc->sc_dev, mp, (totlen & ~3),
-		    prq->prq_base + BWN_PIO8_RXDATA);
+		bus_read_multi_4(sc->sc_mem_res,
+		    prq->prq_base + BWN_PIO8_RXDATA, (void *)mp, (totlen & ~3));
 		if (totlen & 3) {
 			v32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXDATA);
 			data = &(mp[totlen - 1]);
@@ -5572,8 +5769,8 @@ ready:
 			}
 		}
 	} else {
-		siba_read_multi_2(sc->sc_dev, mp, (totlen & ~1),
-		    prq->prq_base + BWN_PIO_RXDATA);
+		bus_read_multi_2(sc->sc_mem_res,
+		    prq->prq_base + BWN_PIO_RXDATA, (void *)mp, (totlen & ~1));
 		if (totlen & 1) {
 			v16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXDATA);
 			mp[totlen - 1] = v16;
@@ -5741,8 +5938,8 @@ bwn_rx_rssi_calc(struct bwn_mac *mac, uint8_t in_rssi,
 			else
 				tmp -= 3;
 		} else {
-			if (siba_sprom_get_bf_lo(mac->mac_sc->sc_dev)
-			    & BWN_BFL_RSSI) {
+			if (mac->mac_sc->sc_board_info.board_flags
+			    & BHND_BFL_ADCDIV) {
 				if (in_rssi > 63)
 					in_rssi = 63;
 				tmp = gphy->pg_nrssi_lt[in_rssi];
@@ -6043,8 +6240,8 @@ bwn_phy_txpower_check(struct bwn_mac *mac, uint32_t flags)
 		return;
 	phy->nexttime = now + 2 * 1000;
 
-	if (siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM &&
-	    siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BU4306)
+	if (sc->sc_board_info.board_vendor == PCI_VENDOR_BROADCOM &&
+	    sc->sc_board_info.board_type == BHND_BOARD_BU4306)
 		return;
 
 	if (phy->recalc_txpwr != NULL) {
@@ -6527,9 +6724,9 @@ bwn_antenna_sanitize(struct bwn_mac *mac, uint8_t n)
 	if (n == 0)
 		return (0);
 	if (mac->mac_phy.gmode)
-		mask = siba_sprom_get_ant_bg(sc->sc_dev);
+		mask = sc->sc_ant2g;
 	else
-		mask = siba_sprom_get_ant_a(sc->sc_dev);
+		mask = sc->sc_ant5g;
 	if (!(mask & (1 << (n - 1))))
 		return (0);
 	return (n);
@@ -6588,8 +6785,8 @@ bwn_pio_write_multi_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
 	    BWN_PIO8_TXCTL_16_23 | BWN_PIO8_TXCTL_24_31;
 	bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl);
 
-	siba_write_multi_4(sc->sc_dev, data, (len & ~3),
-	    tq->tq_base + BWN_PIO8_TXDATA);
+	bus_write_multi_4(sc->sc_mem_res, tq->tq_base + BWN_PIO8_TXDATA,
+	    __DECONST(void *, data), (len & ~3));
 	if (len & 3) {
 		ctl &= ~(BWN_PIO8_TXCTL_8_15 | BWN_PIO8_TXCTL_16_23 |
 		    BWN_PIO8_TXCTL_24_31);
@@ -6631,8 +6828,8 @@ bwn_pio_write_multi_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
 	ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI;
 	BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
 
-	siba_write_multi_2(sc->sc_dev, data, (len & ~1),
-	    tq->tq_base + BWN_PIO_TXDATA);
+	bus_write_multi_2(sc->sc_mem_res, tq->tq_base + BWN_PIO_TXDATA,
+	    __DECONST(void *, data), (len & ~1));
 	if (len & 1) {
 		ctl &= ~BWN_PIO_TXCTL_WRITEHI;
 		BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
@@ -6941,7 +7138,7 @@ bwn_tsf_read(struct bwn_mac *mac, uint64_t *tsf)
 {
 	uint32_t low, high;
 
-	KASSERT(siba_get_revid(mac->mac_sc->sc_dev) >= 3,
+	KASSERT(bhnd_get_hwrev(mac->mac_sc->sc_dev) >= 3,
 	    ("%s:%d: fail", __func__, __LINE__));
 
 	low = BWN_READ_4(mac, BWN_REV3PLUS_TSF_LOW);
@@ -6954,30 +7151,98 @@ bwn_tsf_read(struct bwn_mac *mac, uint64_t *tsf)
 static int
 bwn_dma_attach(struct bwn_mac *mac)
 {
-	struct bwn_dma *dma = &mac->mac_method.dma;
-	struct bwn_softc *sc = mac->mac_sc;
-	bus_addr_t lowaddr = 0;
-	int error;
+	struct bwn_dma			*dma;
+	struct bwn_softc		*sc;
+	struct bhnd_dma_translation	*dt, dma_translation;
+	bhnd_addr_t			 addrext_req;
+	bus_dma_tag_t			 dmat;
+	bus_addr_t			 lowaddr;
+	u_int				 addrext_shift, addr_width;
+	int				 error;
 
-	if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0)
+	dma = &mac->mac_method.dma;
+	sc = mac->mac_sc;
+	dt = NULL;
+
+	if (sc->sc_quirks & BWN_QUIRK_NODMA)
 		return (0);
 
-	KASSERT(siba_get_revid(sc->sc_dev) >= 5, ("%s: fail", __func__));
+	KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 5, ("%s: fail", __func__));
+
+	/* Use the DMA engine's maximum host address width to determine the
+	 * addrext constraints, and supported device address width. */
+	switch (mac->mac_dmatype) {
+	case BHND_DMA_ADDR_30BIT:
+		/* 32-bit engine without addrext support */
+		addrext_req = 0x0;
+		addrext_shift = 0;
+
+		/* We can address the full 32-bit device address space */
+		addr_width = BHND_DMA_ADDR_32BIT;
+		break;
 
+	case BHND_DMA_ADDR_32BIT:
+		/* 32-bit engine with addrext support */
+		addrext_req = BWN_DMA32_ADDREXT_MASK;
+		addrext_shift = BWN_DMA32_ADDREXT_SHIFT;
+		addr_width = BHND_DMA_ADDR_32BIT;
+		break;
+
+	case BHND_DMA_ADDR_64BIT:
+		/* 64-bit engine with addrext support */
+		addrext_req = BWN_DMA64_ADDREXT_MASK;
+		addrext_shift = BWN_DMA64_ADDREXT_SHIFT;
+		addr_width = BHND_DMA_ADDR_64BIT;
+		break;
+
+	default:
+		device_printf(sc->sc_dev, "unsupported DMA address width: %d\n",
+		    mac->mac_dmatype);
+		return (ENXIO);
+	}
+
+
+	/* Fetch our device->host DMA translation and tag */
+	error = bhnd_get_dma_translation(sc->sc_dev, addr_width, 0, &dmat,
+	    &dma_translation);
+	if (error) {
+		device_printf(sc->sc_dev, "error fetching DMA translation: "
+		    "%d\n", error);
+		return (error);
+	}
+
+	/* Verify that our DMA engine's addrext constraints are compatible with
+	 * our DMA translation */
+	if (addrext_req != 0x0 &&
+	    (dma_translation.addrext_mask & addrext_req) != addrext_req)
+	{
+		device_printf(sc->sc_dev, "bus addrext mask %#jx incompatible "
+		    "with device addrext mask %#jx, disabling extended address "
+		    "support\n", (uintmax_t)dma_translation.addrext_mask,
+		    (uintmax_t)addrext_req);
+
+		addrext_req = 0x0;
+		addrext_shift = 0;
+	}
+
+	/* Apply our addrext translation constraint */
+	dma_translation.addrext_mask = addrext_req;
+
+	/* Initialize our DMA engine configuration */
 	mac->mac_flags |= BWN_MAC_FLAG_DMA;
 
-	dma->dmatype = bwn_dma_gettype(mac);
-	if (dma->dmatype == BWN_DMA_30BIT)
-		lowaddr = BWN_BUS_SPACE_MAXADDR_30BIT;
-	else if (dma->dmatype == BWN_DMA_32BIT)
-		lowaddr = BUS_SPACE_MAXADDR_32BIT;
-	else
-		lowaddr = BUS_SPACE_MAXADDR;
+	dma->addrext_shift = addrext_shift;
+	dma->translation = dma_translation;
+
+	dt = &dma->translation;
+
+	/* Dermine our translation's maximum supported address */
+	lowaddr = MIN((dt->addr_mask | dt->addrext_mask), BUS_SPACE_MAXADDR);
 
 	/*
 	 * Create top level DMA tag
 	 */
-	error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),	/* parent */
+	error = bus_dma_tag_create(dmat,		/* parent */
 			       BWN_ALIGN, 0,		/* alignment, bounds */
 			       lowaddr,			/* lowaddr */
 			       BUS_SPACE_MAXADDR,	/* highaddr */
@@ -7029,26 +7294,26 @@ bwn_dma_attach(struct bwn_mac *mac)
 		goto fail1;
 	}
 
-	dma->wme[WME_AC_BK] = bwn_dma_ringsetup(mac, 0, 1, dma->dmatype);
+	dma->wme[WME_AC_BK] = bwn_dma_ringsetup(mac, 0, 1);
 	if (!dma->wme[WME_AC_BK])
 		goto fail2;
 
-	dma->wme[WME_AC_BE] = bwn_dma_ringsetup(mac, 1, 1, dma->dmatype);
+	dma->wme[WME_AC_BE] = bwn_dma_ringsetup(mac, 1, 1);
 	if (!dma->wme[WME_AC_BE])
 		goto fail3;
 
-	dma->wme[WME_AC_VI] = bwn_dma_ringsetup(mac, 2, 1, dma->dmatype);
+	dma->wme[WME_AC_VI] = bwn_dma_ringsetup(mac, 2, 1);
 	if (!dma->wme[WME_AC_VI])
 		goto fail4;
 
-	dma->wme[WME_AC_VO] = bwn_dma_ringsetup(mac, 3, 1, dma->dmatype);
+	dma->wme[WME_AC_VO] = bwn_dma_ringsetup(mac, 3, 1);
 	if (!dma->wme[WME_AC_VO])
 		goto fail5;
 
-	dma->mcast = bwn_dma_ringsetup(mac, 4, 1, dma->dmatype);
+	dma->mcast = bwn_dma_ringsetup(mac, 4, 1);
 	if (!dma->mcast)
 		goto fail6;
-	dma->rx = bwn_dma_ringsetup(mac, 0, 0, dma->dmatype);
+	dma->rx = bwn_dma_ringsetup(mac, 0, 0);
 	if (!dma->rx)
 		goto fail7;
 
@@ -7157,19 +7422,19 @@ bwn_pio_stop(struct bwn_mac *mac)
 	bwn_destroy_queue_tx(&pio->wme[WME_AC_BK]);
 }
 
-static void
+static int
 bwn_led_attach(struct bwn_mac *mac)
 {
 	struct bwn_softc *sc = mac->mac_sc;
 	const uint8_t *led_act = NULL;
-	uint16_t val[BWN_LED_MAX];
+	int error;
 	int i;
 
 	sc->sc_led_idle = (2350 * hz) / 1000;
 	sc->sc_led_blink = 1;
 
 	for (i = 0; i < N(bwn_vendor_led_act); ++i) {
-		if (siba_get_pci_subvendor(sc->sc_dev) ==
+		if (sc->sc_board_info.board_vendor ==
 		    bwn_vendor_led_act[i].vid) {
 			led_act = bwn_vendor_led_act[i].led_act;
 			break;
@@ -7178,20 +7443,31 @@ bwn_led_attach(struct bwn_mac *mac)
 	if (led_act == NULL)
 		led_act = bwn_default_led_act;
 
-	val[0] = siba_sprom_get_gpio0(sc->sc_dev);
-	val[1] = siba_sprom_get_gpio1(sc->sc_dev);
-	val[2] = siba_sprom_get_gpio2(sc->sc_dev);
-	val[3] = siba_sprom_get_gpio3(sc->sc_dev);
+	_Static_assert(nitems(bwn_led_vars) == BWN_LED_MAX,
+	    "invalid NVRAM variable name array");
 
 	for (i = 0; i < BWN_LED_MAX; ++i) {
-		struct bwn_led *led = &sc->sc_leds[i];
+		struct bwn_led	*led;
+		uint8_t		 val;
+
+		led = &sc->sc_leds[i];
 
-		if (val[i] == 0xff) {
+		KASSERT(i < nitems(bwn_led_vars), ("unknown LED index"));
+		error = bhnd_nvram_getvar_uint8(sc->sc_dev, bwn_led_vars[i],
+		    &val);
+		if (error) {
+			if (error != ENOENT) {
+				device_printf(sc->sc_dev, "NVRAM variable %s "
+				    "unreadable: %d", bwn_led_vars[i], error);
+				return (error);
+			}
+
+			/* Not found; use default */
 			led->led_act = led_act[i];
 		} else {
-			if (val[i] & BWN_LED_ACT_LOW)
+			if (val & BWN_LED_ACT_LOW)
 				led->led_flags |= BWN_LED_F_ACTLOW;
-			led->led_act = val[i] & BWN_LED_ACT_MASK;
+			led->led_act = val & BWN_LED_ACT_MASK;
 		}
 		led->led_mask = (1 << i);
 
@@ -7216,6 +7492,8 @@ bwn_led_attach(struct bwn_mac *mac)
 		    led->led_act, led->led_flags & BWN_LED_F_ACTLOW);
 	}
 	callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0);
+
+	return (0);
 }
 
 static __inline uint16_t
@@ -7486,15 +7764,14 @@ static device_method_t bwn_methods[] = {
 	DEVMETHOD(device_resume,	bwn_resume),
 	DEVMETHOD_END
 };
-driver_t bwn_driver = {
+static driver_t bwn_driver = {
 	"bwn",
 	bwn_methods,
 	sizeof(struct bwn_softc)
 };
 static devclass_t bwn_devclass;
-DRIVER_MODULE(bwn, siba_bwn, bwn_driver, bwn_devclass, 0, 0);
-MODULE_DEPEND(bwn, bwn_pci, 1, 1, 1);
-MODULE_DEPEND(bwn, siba_bwn, 1, 1, 1);
+DRIVER_MODULE(bwn, bhnd, bwn_driver, bwn_devclass, 0, 0);
+MODULE_DEPEND(bwn, bhnd, 1, 1, 1);
 MODULE_DEPEND(bwn, gpiobus, 1, 1, 1);
 MODULE_DEPEND(bwn, wlan, 1, 1, 1);		/* 802.11 media layer */
 MODULE_DEPEND(bwn, firmware, 1, 1, 1);		/* firmware support */
diff --git a/sys/dev/bwn/if_bwn_bhnd.c b/sys/dev/bwn/if_bwn_bhnd.c
deleted file mode 100644
index 305fee0243c9..000000000000
--- a/sys/dev/bwn/if_bwn_bhnd.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
- * Copyright (c) 2017 The FreeBSD Foundation
- * All rights reserved.
- * 
- * Portions of this software were developed by Landon Fuller
- * under sponsorship from the FreeBSD Foundation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include "opt_bwn.h"
-#include "opt_wlan.h"
-
-#include <sys/param.h>
-#include <sys/kernel.h>
-#include <sys/module.h>
-#include <sys/systm.h>
-#include <sys/socket.h>
-#include <sys/sockio.h>
-
-#include <machine/bus.h>
-#include <sys/rman.h>
-#include <machine/resource.h>
-
-#include <net/ethernet.h>
-#include <net/if.h>
-#include <net/if_var.h>
-#include <net/if_arp.h>
-#include <net/if_dl.h>
-#include <net/if_llc.h>
-#include <net/if_media.h>
-#include <net/if_types.h>
-
-#include <net80211/ieee80211_var.h>
-#include <net80211/ieee80211_radiotap.h>
-#include <net80211/ieee80211_regdomain.h>
-#include <net80211/ieee80211_phy.h>
-#include <net80211/ieee80211_ratectl.h>
-
-#include <dev/bhnd/bhnd.h>
-#include <dev/bhnd/bhnd_ids.h>
-
-#include "if_bwnvar.h"
-
-/* Supported device identifiers */
-#define	BWN_DEV(_hwrev)	{{					\
-	BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_D11),	\
-	BHND_MATCH_CORE_REV(_hwrev),				\
-}}
-
-static const struct bhnd_device bwn_devices[] = {
-	BWN_DEV(HWREV_RANGE(5, 16)),
-	BWN_DEV(HWREV_EQ(23)),
-
-	BHND_DEVICE_END
-};
-
-static int
-bwn_bhnd_probe(device_t dev)
-{
-	const struct bhnd_device *id;
-
-	id = bhnd_device_lookup(dev, bwn_devices, sizeof(bwn_devices[0]));
-	if (id == NULL)
-		return (ENXIO);
-
-	bhnd_set_default_core_desc(dev);
-	return (BUS_PROBE_DEFAULT);
-}
-
-static device_method_t bwn_bhnd_methods[] = {
-	/* Device interface */
-	DEVMETHOD(device_probe,		bwn_bhnd_probe),
-
-	DEVMETHOD_END
-};
-
-static devclass_t bwn_devclass;
-
-DEFINE_CLASS_1(bwn, bwn_bhnd_driver, bwn_bhnd_methods, sizeof(struct bwn_softc),
-    bwn_driver);
-
-DRIVER_MODULE(bwn_bhnd, bhnd, bwn_bhnd_driver, bwn_devclass, 0, 0);
-MODULE_DEPEND(bwn_bhnd, bhnd, 1, 1, 1);
-MODULE_VERSION(bwn_bhnd, 1);
diff --git a/sys/dev/bwn/if_bwn_chipid.h b/sys/dev/bwn/if_bwn_chipid.h
deleted file mode 100644
index 333c980e2d6b..000000000000
--- a/sys/dev/bwn/if_bwn_chipid.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*-
- * Copyright (c) 2016 Adrian Chadd <adrian@FreeBSD.org>.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer,
- *    without modification.
- * 2. Redistributions in binary form must reproduce at minimum a disclaimer
- *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
- *    redistribution must be conditioned upon including a substantially
- *    similar Disclaimer requirement for further binary redistribution.
- *
- * NO WARRANTY
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
- * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
- * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
- * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- * THE POSSIBILITY OF SUCH DAMAGES.
- *
- * $FreeBSD$
- */
-#ifndef	__IF_BWN_CHIPID_H__
-#define	__IF_BWN_CHIPID_H__
-
-/*
- * BCMA chip identifiers.
- */
-#define	BCMA_CHIP_ID_BCM4313		0x4313
-#define	BCMA_CHIP_ID_BCM43142		43142
-#define	BCMA_CHIP_ID_BCM43131		43131
-#define	BCMA_CHIP_ID_BCM43217		43217
-#define	BCMA_CHIP_ID_BCM43222		43222
-#define	BCMA_CHIP_ID_BCM43224		43224
-#define	 BCMA_PKG_ID_BCM43224_FAB_CSM	0x8
-#define	 BCMA_PKG_ID_BCM43224_FAB_SMIC	0xa
-#define	BCMA_CHIP_ID_BCM43225		43225
-#define	BCMA_CHIP_ID_BCM43227		43227
-#define	BCMA_CHIP_ID_BCM43228		43228
-#define	BCMA_CHIP_ID_BCM43421		43421
-#define	BCMA_CHIP_ID_BCM43428		43428
-#define	BCMA_CHIP_ID_BCM43431		43431
-#define	BCMA_CHIP_ID_BCM43460		43460
-#define	BCMA_CHIP_ID_BCM4331		0x4331
-#define	BCMA_CHIP_ID_BCM6362		0x6362
-#define	BCMA_CHIP_ID_BCM4360		0x4360
-#define	BCMA_CHIP_ID_BCM4352		0x4352
-#define	BCMA_CHIP_ID_BCM4706		0x5300
-#define	BCMA_CHIP_ID_BCM4716		0x4716
-#define	BCMA_CHIP_ID_BCM47162		47162
-#define	BCMA_CHIP_ID_BCM4748		0x4748
-#define	BCMA_CHIP_ID_BCM4749		0x4749
-#define	BCMA_CHIP_ID_BCM5356		0x5356
-#define	BCMA_CHIP_ID_BCM5357		0x5357
-#define	BCMA_CHIP_ID_BCM53572		53572
-#define	BCMA_CHIP_ID_BCM4707		53010
-#define	BCMA_CHIP_ID_BCM47094		53030
-#define	BCMA_CHIP_ID_BCM53018		53018
-
-#define	BCMA_BOARD_TYPE_BCM943224M93		0x008B
-#define	BCMA_BOARD_TYPE_BCM943224M93A		0x0090
-
-#endif	/* __IF_BWN_CHIPID_H__ */
diff --git a/sys/dev/bwn/if_bwn_misc.h b/sys/dev/bwn/if_bwn_misc.h
index 37df75f21414..76d6b8445524 100644
--- a/sys/dev/bwn/if_bwn_misc.h
+++ b/sys/dev/bwn/if_bwn_misc.h
@@ -40,6 +40,8 @@
 
 struct bwn_mac;
 
+extern int	bwn_gpio_control(struct bwn_mac *, uint32_t);
+
 extern uint64_t	bwn_hf_read(struct bwn_mac *);
 extern void	bwn_hf_write(struct bwn_mac *, uint64_t);
 
@@ -59,8 +61,7 @@ extern uint32_t	bwn_shm_read_4(struct bwn_mac *, uint16_t, uint16_t);
 extern void	bwn_shm_write_4(struct bwn_mac *, uint16_t, uint16_t,
 		    uint32_t);
 
-/* This is only for SIBA core */
-extern	void bwn_reset_core(struct bwn_mac *, int g_mode);
+extern int	bwn_reset_core(struct bwn_mac *, int g_mode);
 
 extern void	bwn_psctl(struct bwn_mac *, uint32_t);
 
diff --git a/sys/dev/bwn/if_bwn_pci.c b/sys/dev/bwn/if_bwn_pci.c
index 41489603bf74..6aa8dd734443 100644
--- a/sys/dev/bwn/if_bwn_pci.c
+++ b/sys/dev/bwn/if_bwn_pci.c
@@ -54,10 +54,6 @@ __FBSDID("$FreeBSD$");
 static int attach_untested = 0; 
 TUNABLE_INT("hw.bwn_pci.attach_untested", &attach_untested);
 
-/* If non-zero, probe at a higher priority than the stable if_bwn driver. */
-static int prefer_new_driver = 1;
-TUNABLE_INT("hw.bwn_pci.preferred", &prefer_new_driver);
-
 /* SIBA Devices */
 static const struct bwn_pci_device siba_devices[] = {
 	BWN_BCM_DEV(BCM4306_D11A,	"BCM4306 802.11a",
@@ -169,15 +165,7 @@ bwn_pci_probe(device_t dev)
 		return (ENXIO);
 
 	device_set_desc(dev, ident->desc);
-
-	/* Until this driver is complete, require explicit opt-in before
-	 * superceding if_bwn/siba_bwn. */
-	if (prefer_new_driver)
-		return (BUS_PROBE_DEFAULT+1);
-	else
-		return (BUS_PROBE_LOW_PRIORITY);
-
-	// return (BUS_PROBE_DEFAULT);
+	return (BUS_PROBE_DEFAULT);
 }
 
 static int
@@ -309,6 +297,7 @@ DRIVER_MODULE_ORDERED(bwn_pci, pci, bwn_pci_driver, bwn_pci_devclass, NULL,
     NULL, SI_ORDER_ANY);
 DRIVER_MODULE(bhndb, bwn_pci, bhndb_pci_driver, bhndb_devclass, NULL, NULL);
 
+MODULE_DEPEND(bwn_pci, bwn, 1, 1, 1);
 MODULE_DEPEND(bwn_pci, bhnd, 1, 1, 1);
 MODULE_DEPEND(bwn_pci, bhndb, 1, 1, 1);
 MODULE_DEPEND(bwn_pci, bhndb_pci, 1, 1, 1);
diff --git a/sys/dev/bwn/if_bwn_phy_common.c b/sys/dev/bwn/if_bwn_phy_common.c
index 22dde9f95d24..704348f19294 100644
--- a/sys/dev/bwn/if_bwn_phy_common.c
+++ b/sys/dev/bwn/if_bwn_phy_common.c
@@ -73,65 +73,72 @@ __FBSDID("$FreeBSD$");
 #include <net80211/ieee80211_phy.h>
 #include <net80211/ieee80211_ratectl.h>
 
-#include <dev/bwn/if_bwn_siba.h>
+#include <dev/bhnd/bhnd.h>
+#include <dev/bhnd/bhnd_ids.h>
+
+#include <dev/bhnd/cores/chipc/chipc.h>
+#include <dev/bhnd/cores/pmu/bhnd_pmu.h>
 
 #include <dev/bwn/if_bwnreg.h>
 #include <dev/bwn/if_bwnvar.h>
 
-#include <dev/bwn/if_bwn_chipid.h>
 #include <dev/bwn/if_bwn_debug.h>
 #include <dev/bwn/if_bwn_misc.h>
 #include <dev/bwn/if_bwn_phy_common.h>
 
 void
-bwn_mac_switch_freq(struct bwn_mac *mac, int spurmode)
+bwn_mac_switch_freq(struct bwn_mac *mac, bhnd_pmu_spuravoid spurmode)
 {
 	struct bwn_softc *sc = mac->mac_sc;
-	uint16_t chip_id = siba_get_chipid(sc->sc_dev);
+	uint16_t chip_id = sc->sc_cid.chip_id;
 
-	if (chip_id == BCMA_CHIP_ID_BCM4331) {
+	if (chip_id == BHND_CHIPID_BCM4331) {
 		switch (spurmode) {
-		case 2: /* 168 Mhz: 2^26/168 = 0x61862 */
+		case BHND_PMU_SPURAVOID_M2: /* 168 Mhz: 2^26/168 = 0x61862 */
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x1862);
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x6);
 			break;
-		case 1: /* 164 Mhz: 2^26/164 = 0x63e70 */
+		case BHND_PMU_SPURAVOID_M1: /* 164 Mhz: 2^26/164 = 0x63e70 */
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x3e70);
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x6);
 			break;
-		default: /* 160 Mhz: 2^26/160 = 0x66666 */
+		case BHND_PMU_SPURAVOID_NONE: /* 160 Mhz: 2^26/160 = 0x66666 */
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x6666);
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x6);
 			break;
 		}
-	} else if (chip_id == BCMA_CHIP_ID_BCM43131 ||
-	    chip_id == BCMA_CHIP_ID_BCM43217 ||
-	    chip_id == BCMA_CHIP_ID_BCM43222 ||
-	    chip_id == BCMA_CHIP_ID_BCM43224 ||
-	    chip_id == BCMA_CHIP_ID_BCM43225 ||
-	    chip_id == BCMA_CHIP_ID_BCM43227 ||
-	    chip_id == BCMA_CHIP_ID_BCM43228) {
+	} else if (chip_id == BHND_CHIPID_BCM43131 ||
+	    chip_id == BHND_CHIPID_BCM43217 ||
+	    chip_id == BHND_CHIPID_BCM43222 ||
+	    chip_id == BHND_CHIPID_BCM43224 ||
+	    chip_id == BHND_CHIPID_BCM43225 ||
+	    chip_id == BHND_CHIPID_BCM43227 ||
+	    chip_id == BHND_CHIPID_BCM43228) {
 		switch (spurmode) {
-		case 2: /* 126 Mhz */
+		case BHND_PMU_SPURAVOID_M2: /* 126 Mhz */
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x2082);
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x8);
 			break;
-		case 1: /* 123 Mhz */
+		case BHND_PMU_SPURAVOID_M1: /* 123 Mhz */
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x5341);
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x8);
 			break;
-		default: /* 120 Mhz */
+		case BHND_PMU_SPURAVOID_NONE: /* 120 Mhz */
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x8889);
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x8);
 			break;
 		}
 	} else if (mac->mac_phy.type == BWN_PHYTYPE_LCN) {
 		switch (spurmode) {
-		case 1: /* 82 Mhz */
+		case BHND_PMU_SPURAVOID_M2:
+			device_printf(sc->sc_dev, "invalid spuravoid mode: "
+			    "%d\n", spurmode);
+			break;
+		case BHND_PMU_SPURAVOID_M1: /* 82 Mhz */
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x7CE0);
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0xC);
 			break;
-		default: /* 80 Mhz */
+		case BHND_PMU_SPURAVOID_NONE: /* 80 Mhz */
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0xCCCD);
 			BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0xC);
 			break;
@@ -140,20 +147,30 @@ bwn_mac_switch_freq(struct bwn_mac *mac, int spurmode)
 }
 
 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
-void
+int
 bwn_phy_force_clock(struct bwn_mac *mac, int force)
 {
-	struct bwn_softc *sc = mac->mac_sc;
-	uint32_t tmp;
+	struct bwn_softc	*sc;
+	uint32_t		 val, mask;
+	int			 error;
+
+	sc = mac->mac_sc;
 
 	/* XXX Only for N, HT and AC PHYs */
+	mask = BHND_IOCTL_CLK_FORCE;
+	if (force) {
+		val = BHND_IOCTL_CLK_FORCE;
+	} else {
+		val = 0;
+	}
 
-	tmp = siba_read_4(sc->sc_dev, SIBA_TGSLOW);
-	if (force)
-		tmp |= SIBA_TGSLOW_FGC;
-	else
-		tmp &= ~SIBA_TGSLOW_FGC;
-	siba_write_4(sc->sc_dev, SIBA_TGSLOW, tmp);
+	if ((error = bhnd_write_ioctl(sc->sc_dev, val, mask))) {
+		device_printf(sc->sc_dev, "failed to set CLK_FORCE ioctl flag: "
+		    "%d\n", error);
+		return (error);
+	}
+
+	return (0);
 }
 
 int
@@ -172,28 +189,49 @@ bwn_radio_wait_value(struct bwn_mac *mac, uint16_t offset, uint16_t mask,
 	return (0);
 }
 
-void
+int
 bwn_mac_phy_clock_set(struct bwn_mac *mac, int enabled)
 {
-	struct bwn_softc *sc = mac->mac_sc;
-	uint32_t val;
+	struct bwn_softc	*sc;
+	uint32_t		 val, mask;
+	int			 error;
+
+	sc = mac->mac_sc;
 
-	val = siba_read_4(sc->sc_dev, SIBA_TGSLOW);
-	if (enabled)
-		    val |= BWN_TGSLOW_MACPHYCLKEN;
-	else
-		    val &= ~BWN_TGSLOW_MACPHYCLKEN;
-	siba_write_4(sc->sc_dev, SIBA_TGSLOW, val);
+	mask = BWN_IOCTL_MACPHYCLKEN;
+	if (enabled) {
+		val = BWN_IOCTL_MACPHYCLKEN;
+	} else {
+		val = 0;
+	}
+
+	if ((error = bhnd_write_ioctl(sc->sc_dev, val, mask))) {
+		device_printf(sc->sc_dev, "failed to set MACPHYCLKEN ioctl "
+		    "flag: %d\n", error);
+		return (error);
+	}
+
+	return (0);
 }
 
 /* http://bcm-v4.sipsolutions.net/802.11/PHY/BmacCorePllReset */
-void
+int
 bwn_wireless_core_phy_pll_reset(struct bwn_mac *mac)
 {
-	struct bwn_softc *sc = mac->mac_sc;
+	struct bwn_softc	*sc;
+	uint32_t		 pll_flag;
+
+	sc = mac->mac_sc;
+
+	if (sc->sc_pmu == NULL) {
+		device_printf(sc->sc_dev, "PMU device not found\n");
+		return (ENXIO);
+	}
+
+	pll_flag = 0x4;
+	bhnd_pmu_write_chipctrl(sc->sc_pmu, 0x0, 0x0, pll_flag);
+	bhnd_pmu_write_chipctrl(sc->sc_pmu, 0x0, pll_flag, pll_flag);	
+	bhnd_pmu_write_chipctrl(sc->sc_pmu, 0x0, 0x0, pll_flag);
 
-	siba_cc_write32(sc->sc_dev, SIBA_CC_CHIPCTL_ADDR, 0);
-	siba_cc_mask32(sc->sc_dev, SIBA_CC_CHIPCTL_DATA, ~0x4);
-	siba_cc_set32(sc->sc_dev, SIBA_CC_CHIPCTL_DATA, 0x4);
-	siba_cc_mask32(sc->sc_dev, SIBA_CC_CHIPCTL_DATA, ~0x4);
+	return (0);
 }
diff --git a/sys/dev/bwn/if_bwn_phy_common.h b/sys/dev/bwn/if_bwn_phy_common.h
index 687fc78388bb..a10976b2b62c 100644
--- a/sys/dev/bwn/if_bwn_phy_common.h
+++ b/sys/dev/bwn/if_bwn_phy_common.h
@@ -31,11 +31,12 @@
 #ifndef	__PHY_COMMON_H__
 #define	__PHY_COMMON_H__
 
-extern	void bwn_mac_switch_freq(struct bwn_mac *mac, int spurmode);
-extern	void bwn_phy_force_clock(struct bwn_mac *mac, int force);
+extern	void bwn_mac_switch_freq(struct bwn_mac *mac,
+	    bhnd_pmu_spuravoid spurmode);
+extern	int bwn_phy_force_clock(struct bwn_mac *mac, int force);
 extern	int bwn_radio_wait_value(struct bwn_mac *mac, uint16_t offset,
 	    uint16_t mask, uint16_t value, int delay, int timeout);
-extern	void bwn_mac_phy_clock_set(struct bwn_mac *mac, int enabled);
-extern	void bwn_wireless_core_phy_pll_reset(struct bwn_mac *mac);
+extern	int bwn_mac_phy_clock_set(struct bwn_mac *mac, int enabled);
+extern	int bwn_wireless_core_phy_pll_reset(struct bwn_mac *mac);
 
 #endif	/* __PHY_COMMON_H__ */
diff --git a/sys/dev/bwn/if_bwn_phy_g.c b/sys/dev/bwn/if_bwn_phy_g.c
index f0e76f6ec82d..280e52156974 100644
--- a/sys/dev/bwn/if_bwn_phy_g.c
+++ b/sys/dev/bwn/if_bwn_phy_g.c
@@ -72,8 +72,6 @@ __FBSDID("$FreeBSD$");
 #include <net80211/ieee80211_phy.h>
 #include <net80211/ieee80211_ratectl.h>
 
-#include <dev/bwn/if_bwn_siba.h>
-
 #include <dev/bwn/if_bwnreg.h>
 #include <dev/bwn/if_bwnvar.h>
 
@@ -81,6 +79,8 @@ __FBSDID("$FreeBSD$");
 #include <dev/bwn/if_bwn_misc.h>
 #include <dev/bwn/if_bwn_phy_g.h>
 
+#include "bhnd_nvram_map.h"
+
 static void	bwn_phy_g_init_sub(struct bwn_mac *);
 static uint8_t	bwn_has_hwpctl(struct bwn_mac *);
 static void	bwn_phy_init_b5(struct bwn_mac *);
@@ -157,14 +157,27 @@ bwn_phy_g_attach(struct bwn_mac *mac)
 	int16_t pab0, pab1, pab2;
 	static int8_t bwn_phy_g_tssi2dbm_table[] = BWN_PHY_G_TSSI2DBM_TABLE;
 	int8_t bg;
+	int error;
 
-	bg = (int8_t)siba_sprom_get_tssi_bg(sc->sc_dev);
-	pab0 = (int16_t)siba_sprom_get_pa0b0(sc->sc_dev);
-	pab1 = (int16_t)siba_sprom_get_pa0b1(sc->sc_dev);
-	pab2 = (int16_t)siba_sprom_get_pa0b2(sc->sc_dev);
+	/* Fetch SPROM configuration */
+#define	BWN_PHY_G_READVAR(_dev, _type, _name, _result)		\
+do {									\
+	error = bhnd_nvram_getvar_ ##_type((_dev), (_name), (_result));	\
+	if (error) {							\
+		device_printf((_dev), "NVRAM variable %s unreadable: "	\
+		    "%d\n", (_name), error);				\
+		return (error);						\
+	}								\
+} while(0)
 
-	if ((siba_get_chipid(sc->sc_dev) == 0x4301) && (phy->rf_ver != 0x2050))
-		device_printf(sc->sc_dev, "not supported anymore\n");
+	BWN_PHY_G_READVAR(sc->sc_dev, int8, BHND_NVAR_PA0ITSSIT, &bg);
+	BWN_PHY_G_READVAR(sc->sc_dev, int16, BHND_NVAR_PA0B0, &pab0);
+	BWN_PHY_G_READVAR(sc->sc_dev, int16, BHND_NVAR_PA0B1, &pab1);
+	BWN_PHY_G_READVAR(sc->sc_dev, int16, BHND_NVAR_PA0B2, &pab2);
+	BWN_PHY_G_READVAR(sc->sc_dev, int16, BHND_NVAR_PA0MAXPWR,
+	    &pg->pg_pa0maxpwr);
+
+#undef	BWN_PHY_G_READVAR
 
 	pg->pg_flags = 0;
 	if (pab0 == 0 || pab1 == 0 || pab2 == 0 || pab0 == -1 || pab1 == -1 ||
@@ -289,12 +302,12 @@ bwn_phy_g_prepare_hw(struct bwn_mac *mac)
 	/* prepare Radio Attenuation */
 	pg->pg_rfatt.padmix = 0;
 
-	if (siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM &&
-	    siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BCM4309G) {
-		if (siba_get_pci_revid(sc->sc_dev) < 0x43) {
+	if (sc->sc_board_info.board_vendor == PCI_VENDOR_BROADCOM &&
+	    sc->sc_board_info.board_type == BHND_BOARD_BCM94309G) {
+		if (sc->sc_board_info.board_rev < 0x43) {
 			pg->pg_rfatt.att = 2;
 			goto done;
-		} else if (siba_get_pci_revid(sc->sc_dev) < 0x51) {
+		} else if (sc->sc_board_info.board_rev < 0x51) {
 			pg->pg_rfatt.att = 3;
 			goto done;
 		}
@@ -313,25 +326,25 @@ bwn_phy_g_prepare_hw(struct bwn_mac *mac)
 			goto done;
 		case 1:
 			if (phy->type == BWN_PHYTYPE_G) {
-				if (siba_get_pci_subvendor(sc->sc_dev) ==
-				    SIBA_BOARDVENDOR_BCM &&
-				    siba_get_pci_subdevice(sc->sc_dev) ==
-				    SIBA_BOARD_BCM4309G &&
-				    siba_get_pci_revid(sc->sc_dev) >= 30)
+				if (sc->sc_board_info.board_vendor ==
+				    PCI_VENDOR_BROADCOM &&
+				    sc->sc_board_info.board_type ==
+				    BHND_BOARD_BCM94309G &&
+				    sc->sc_board_info.board_rev >= 30)
 					pg->pg_rfatt.att = 3;
-				else if (siba_get_pci_subvendor(sc->sc_dev) ==
-				    SIBA_BOARDVENDOR_BCM &&
-				    siba_get_pci_subdevice(sc->sc_dev) ==
-				    SIBA_BOARD_BU4306)
+				else if (sc->sc_board_info.board_vendor ==
+				    PCI_VENDOR_BROADCOM &&
+				    sc->sc_board_info.board_type ==
+				    BHND_BOARD_BU4306)
 					pg->pg_rfatt.att = 3;
 				else
 					pg->pg_rfatt.att = 1;
 			} else {
-				if (siba_get_pci_subvendor(sc->sc_dev) ==
-				    SIBA_BOARDVENDOR_BCM &&
-				    siba_get_pci_subdevice(sc->sc_dev) ==
-				    SIBA_BOARD_BCM4309G &&
-				    siba_get_pci_revid(sc->sc_dev) >= 30)
+				if (sc->sc_board_info.board_vendor ==
+				    PCI_VENDOR_BROADCOM &&
+				    sc->sc_board_info.board_type ==
+				    BHND_BOARD_BCM94309G &&
+				    sc->sc_board_info.board_rev >= 30)
 					pg->pg_rfatt.att = 7;
 				else
 					pg->pg_rfatt.att = 6;
@@ -339,18 +352,19 @@ bwn_phy_g_prepare_hw(struct bwn_mac *mac)
 			goto done;
 		case 2:
 			if (phy->type == BWN_PHYTYPE_G) {
-				if (siba_get_pci_subvendor(sc->sc_dev) ==
-				    SIBA_BOARDVENDOR_BCM &&
-				    siba_get_pci_subdevice(sc->sc_dev) ==
-				    SIBA_BOARD_BCM4309G &&
-				    siba_get_pci_revid(sc->sc_dev) >= 30)
+				if (sc->sc_board_info.board_vendor ==
+				    PCI_VENDOR_BROADCOM &&
+				    sc->sc_board_info.board_type ==
+				    BHND_BOARD_BCM94309G &&
+				    sc->sc_board_info.board_rev >= 30)
 					pg->pg_rfatt.att = 3;
-				else if (siba_get_pci_subvendor(sc->sc_dev) ==
-				    SIBA_BOARDVENDOR_BCM &&
-				    siba_get_pci_subdevice(sc->sc_dev) ==
-				    SIBA_BOARD_BU4306)
+				else if (sc->sc_board_info.board_vendor ==
+				    PCI_VENDOR_BROADCOM &&
+				    sc->sc_board_info.board_type ==
+				    BHND_BOARD_BU4306)
 					pg->pg_rfatt.att = 5;
-				else if (siba_get_chipid(sc->sc_dev) == 0x4320)
+				else if (sc->sc_cid.chip_id ==
+				    BHND_CHIPID_BCM4320)
 					pg->pg_rfatt.att = 4;
 				else
 					pg->pg_rfatt.att = 3;
@@ -656,13 +670,13 @@ bwn_phy_g_recalc_txpwr(struct bwn_mac *mac, int ignore_tssi)
 	pg->pg_avgtssi = tssi;
 	KASSERT(tssi < BWN_TSSI_MAX, ("%s:%d: fail", __func__, __LINE__));
 
-	max = siba_sprom_get_maxpwr_bg(sc->sc_dev);
-	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL)
+	max = pg->pg_pa0maxpwr;
+	if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL)
 		max -= 3;
 	if (max >= 120) {
 		device_printf(sc->sc_dev, "invalid max TX-power value\n");
 		max = 80;
-		siba_sprom_set_maxpwr_bg(sc->sc_dev, max);
+		pg->pg_pa0maxpwr = max;
 	}
 
 	power = MIN(MAX((phy->txpower < 0) ? 0 : (phy->txpower << 2), 0), max) -
@@ -706,8 +720,8 @@ bwn_phy_g_set_txpwr(struct bwn_mac *mac)
 				txctl = BWN_TXCTL_PA2DB | BWN_TXCTL_TXMIX;
 				rfatt += 2;
 				bbatt += 2;
-			} else if (siba_sprom_get_bf_lo(sc->sc_dev) &
-			    BWN_BFL_PACTRL) {
+			} else if (sc->sc_board_info.board_flags &
+			    BHND_BFL_PACTRL) {
 				bbatt += 4 * (rfatt - 2);
 				rfatt = 2;
 			}
@@ -805,7 +819,7 @@ bwn_phy_g_task_60s(struct bwn_mac *mac)
 	struct bwn_softc *sc = mac->mac_sc;
 	uint8_t old = phy->chan;
 
-	if (!(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_RSSI))
+	if (!(sc->sc_board_info.board_flags & BHND_BFL_ADCDIV))
 		return;
 
 	bwn_mac_suspend(mac);
@@ -892,7 +906,7 @@ bwn_phy_g_init_sub(struct bwn_mac *mac)
 		BWN_PHY_SETMASK(mac, BWN_PHY_CCK(0x36), 0x0fff,
 		    (pg->pg_loctl.tx_bias << 12));
 	}
-	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL)
+	if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL)
 		BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2e), 0x8075);
 	else
 		BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2e), 0x807f);
@@ -905,7 +919,7 @@ bwn_phy_g_init_sub(struct bwn_mac *mac)
 		BWN_PHY_WRITE(mac, BWN_PHY_LO_MASK, 0x8078);
 	}
 
-	if (!(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_RSSI)) {
+	if (!(sc->sc_board_info.board_flags & BHND_BFL_ADCDIV)) {
 		for (i = 0; i < 64; i++) {
 			BWN_PHY_WRITE(mac, BWN_PHY_NRSSI_CTRL, i);
 			BWN_PHY_WRITE(mac, BWN_PHY_NRSSI_DATA,
@@ -924,8 +938,8 @@ bwn_phy_g_init_sub(struct bwn_mac *mac)
 	if (phy->rf_rev == 8)
 		BWN_PHY_WRITE(mac, BWN_PHY_EXTG(0x05), 0x3230);
 	bwn_phy_hwpctl_init(mac);
-	if ((siba_get_chipid(sc->sc_dev) == 0x4306
-	     && siba_get_chippkg(sc->sc_dev) == 2) || 0) {
+	if ((sc->sc_cid.chip_id == BHND_CHIPID_BCM4306
+	     && sc->sc_cid.chip_pkg == 2) || 0) {
 		BWN_PHY_MASK(mac, BWN_PHY_CRS0, 0xbfff);
 		BWN_PHY_MASK(mac, BWN_PHY_OFDM(0xc3), 0x7fff);
 	}
@@ -942,8 +956,8 @@ bwn_phy_init_b5(struct bwn_mac *mac)
 
 	if (phy->analog == 1)
 		BWN_RF_SET(mac, 0x007a, 0x0050);
-	if ((siba_get_pci_subvendor(sc->sc_dev) != SIBA_BOARDVENDOR_BCM) &&
-	    (siba_get_pci_subdevice(sc->sc_dev) != SIBA_BOARD_BU4306)) {
+	if ((sc->sc_board_info.board_vendor != PCI_VENDOR_BROADCOM) &&
+	    (sc->sc_board_info.board_type != BHND_BOARD_BU4306)) {
 		value = 0x2120;
 		for (offset = 0x00a8; offset < 0x00c7; offset++) {
 			BWN_PHY_WRITE(mac, offset, value);
@@ -1111,7 +1125,7 @@ bwn_loopback_calcgain(struct bwn_mac *mac)
 	BWN_PHY_SET(mac, BWN_PHY_RFOVER, 0x0100);
 	BWN_PHY_MASK(mac, BWN_PHY_RFOVERVAL, 0xcfff);
 
-	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA) {
+	if (sc->sc_board_info.board_flags & BHND_BFL_EXTLNA) {
 		if (phy->rev >= 7) {
 			BWN_PHY_SET(mac, BWN_PHY_RFOVER, 0x0800);
 			BWN_PHY_SET(mac, BWN_PHY_RFOVERVAL, 0x8000);
@@ -1441,7 +1455,7 @@ bwn_phy_init_b6(struct bwn_mac *mac)
 		BWN_RF_WRITE(mac, 0x5a, 0x88);
 		BWN_RF_WRITE(mac, 0x5b, 0x6b);
 		BWN_RF_WRITE(mac, 0x5c, 0x0f);
-		if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_ALTIQ) {
+		if (sc->sc_board_info.board_flags & BHND_BFL_ALTIQ) {
 			BWN_RF_WRITE(mac, 0x5d, 0xfa);
 			BWN_RF_WRITE(mac, 0x5e, 0xd8);
 		} else {
@@ -1539,7 +1553,7 @@ bwn_phy_init_a(struct bwn_mac *mac)
 	bwn_wa_init(mac);
 
 	if (phy->type == BWN_PHYTYPE_G &&
-	    (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL))
+	    (sc->sc_board_info.board_flags & BHND_BFL_PACTRL))
 		BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x6e), 0xe000, 0x3cf);
 }
 
@@ -1809,9 +1823,9 @@ bwn_wa_init(struct bwn_mac *mac)
 		KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
 	}
 
-	if (siba_get_pci_subvendor(sc->sc_dev) != SIBA_BOARDVENDOR_BCM ||
-	    siba_get_pci_subdevice(sc->sc_dev) != SIBA_BOARD_BU4306 ||
-	    siba_get_pci_revid(sc->sc_dev) != 0x17) {
+	if (sc->sc_board_info.board_vendor != PCI_VENDOR_BROADCOM ||
+	    sc->sc_board_info.board_type != BHND_BOARD_BU4306 ||
+	    sc->sc_board_info.board_rev != 0x17) {
 		if (phy->rev < 2) {
 			bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX_R1, 1,
 			    0x0002);
@@ -1820,8 +1834,8 @@ bwn_wa_init(struct bwn_mac *mac)
 		} else {
 			bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX, 1, 0x0002);
 			bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX, 2, 0x0001);
-			if ((siba_sprom_get_bf_lo(sc->sc_dev) &
-			     BWN_BFL_EXTLNA) &&
+			if ((sc->sc_board_info.board_flags &
+			     BHND_BFL_EXTLNA) &&
 			    (phy->rev >= 7)) {
 				BWN_PHY_MASK(mac, BWN_PHY_EXTG(0x11), 0xf7ff);
 				bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX,
@@ -1839,7 +1853,7 @@ bwn_wa_init(struct bwn_mac *mac)
 			}
 		}
 	}
-	if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM) {
+	if (sc->sc_board_info.board_flags & BHND_BFL_FEM) {
 		BWN_PHY_WRITE(mac, BWN_PHY_GTABCTL, 0x3120);
 		BWN_PHY_WRITE(mac, BWN_PHY_GTABDATA, 0xc480);
 	}
@@ -1927,7 +1941,7 @@ bwn_lo_calcfeed(struct bwn_mac *mac,
 		trsw_rx &= (BWN_PHY_RFOVERVAL_TRSWRX | BWN_PHY_RFOVERVAL_BW);
 
 		rfover = BWN_PHY_RFOVERVAL_UNK | pga | lna | trsw_rx;
-		if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA) &&
+		if ((sc->sc_board_info.board_flags & BHND_BFL_EXTLNA) &&
 		    phy->rev > 6)
 			rfover |= BWN_PHY_RFOVERVAL_EXTLNA;
 
@@ -2216,8 +2230,8 @@ bwn_lo_save(struct bwn_mac *mac, struct bwn_lo_g_value *sav)
 		BWN_PHY_MASK(mac, BWN_PHY_ANALOGOVERVAL, 0xfffc);
 		if (phy->type == BWN_PHYTYPE_G) {
 			if ((phy->rev >= 7) &&
-			    (siba_sprom_get_bf_lo(sc->sc_dev) &
-			     BWN_BFL_EXTLNA)) {
+			    (sc->sc_board_info.board_flags &
+			     BHND_BFL_EXTLNA)) {
 				BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, 0x933);
 			} else {
 				BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, 0x133);
@@ -2675,7 +2689,7 @@ bwn_nrssi_threshold(struct bwn_mac *mac)
 
 	KASSERT(phy->type == BWN_PHYTYPE_G, ("%s: fail", __func__));
 
-	if (phy->gmode && (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_RSSI)) {
+	if (phy->gmode && (sc->sc_board_info.board_flags & BHND_BFL_ADCDIV)) {
 		if (!pg->pg_aci_wlan_automatic && pg->pg_aci_enable) {
 			a = 0x13;
 			b = 0x12;
@@ -3118,8 +3132,8 @@ bwn_phy_hwpctl_init(struct bwn_mac *mac)
 	KASSERT(phy->type == BWN_PHYTYPE_G,
 	    ("%s:%d: fail", __func__, __LINE__));
 
-	if ((siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM) &&
-	    (siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BU4306))
+	if ((sc->sc_board_info.board_vendor == PCI_VENDOR_BROADCOM) &&
+	    (sc->sc_board_info.board_type == BHND_BOARD_BU4306))
 		return;
 
 	BWN_PHY_WRITE(mac, 0x0028, 0x8018);
@@ -3256,7 +3270,8 @@ bwn_hwpctl_init_gphy(struct bwn_mac *mac)
 static void
 bwn_phy_g_switch_chan(struct bwn_mac *mac, int channel, uint8_t spu)
 {
-	struct bwn_softc *sc = mac->mac_sc;
+	struct bwn_softc	*sc = mac->mac_sc;
+	int			 error;
 
 	if (spu != 0)
 		bwn_spu_workaround(mac, channel);
@@ -3264,7 +3279,17 @@ bwn_phy_g_switch_chan(struct bwn_mac *mac, int channel, uint8_t spu)
 	BWN_WRITE_2(mac, BWN_CHANNEL, bwn_phy_g_chan2freq(channel));
 
 	if (channel == 14) {
-		if (siba_sprom_get_ccode(sc->sc_dev) == SIBA_CCODE_JAPAN)
+		uint8_t cc;
+
+		error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_CC, &cc);
+		if (error) {
+			device_printf(sc->sc_dev, "error reading country code "
+			    "from NVRAM, assuming channel 14 unavailable: %d\n",
+			    error);
+			cc = BWN_SPROM1_CC_WORLDWIDE;
+		}
+
+		if (cc == BWN_SPROM1_CC_JP)
 			bwn_hf_write(mac,
 			    bwn_hf_read(mac) & ~BWN_HF_JAPAN_CHAN14_OFF);
 		else
@@ -3381,7 +3406,7 @@ bwn_rf_2050_rfoverval(struct bwn_mac *mac, uint16_t reg, uint32_t lpd)
 		}
 
 		if ((phy->rev < 7) ||
-		    !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA)) {
+		    !(sc->sc_board_info.board_flags & BHND_BFL_EXTLNA)) {
 			if (reg == BWN_PHY_RFOVER) {
 				return (0x1b3);
 			} else if (reg == BWN_PHY_RFOVERVAL) {
@@ -3425,7 +3450,7 @@ bwn_rf_2050_rfoverval(struct bwn_mac *mac, uint16_t reg, uint32_t lpd)
 	}
 
 	if ((phy->rev < 7) ||
-	    !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA)) {
+	    !(sc->sc_board_info.board_flags & BHND_BFL_EXTLNA)) {
 		if (reg == BWN_PHY_RFOVER) {
 			return (0x1b3);
 		} else if (reg == BWN_PHY_RFOVERVAL) {
@@ -3562,8 +3587,8 @@ bwn_phy_lock(struct bwn_mac *mac)
 	struct bwn_softc *sc = mac->mac_sc;
 	struct ieee80211com *ic = &sc->sc_ic;
 
-	KASSERT(siba_get_revid(sc->sc_dev) >= 3,
-	    ("%s: unsupported rev %d", __func__, siba_get_revid(sc->sc_dev)));
+	KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 3,
+	    ("%s: unsupported rev %d", __func__, bhnd_get_hwrev(sc->sc_dev)));
 
 	if (ic->ic_opmode != IEEE80211_M_HOSTAP)
 		bwn_psctl(mac, BWN_PS_AWAKE);
@@ -3575,8 +3600,8 @@ bwn_phy_unlock(struct bwn_mac *mac)
 	struct bwn_softc *sc = mac->mac_sc;
 	struct ieee80211com *ic = &sc->sc_ic;
 
-	KASSERT(siba_get_revid(sc->sc_dev) >= 3,
-	    ("%s: unsupported rev %d", __func__, siba_get_revid(sc->sc_dev)));
+	KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 3,
+	    ("%s: unsupported rev %d", __func__, bhnd_get_hwrev(sc->sc_dev)));
 
 	if (ic->ic_opmode != IEEE80211_M_HOSTAP)
 		bwn_psctl(mac, 0);
diff --git a/sys/dev/bwn/if_bwn_phy_lp.c b/sys/dev/bwn/if_bwn_phy_lp.c
index 0faee2d8625d..bec003ee9fda 100644
--- a/sys/dev/bwn/if_bwn_phy_lp.c
+++ b/sys/dev/bwn/if_bwn_phy_lp.c
@@ -72,7 +72,10 @@ __FBSDID("$FreeBSD$");
 #include <net80211/ieee80211_phy.h>
 #include <net80211/ieee80211_ratectl.h>
 
-#include <dev/bwn/if_bwn_siba.h>
+#include <dev/bhnd/bhnd.h>
+#include <dev/bhnd/bhnd_ids.h>
+
+#include <dev/bhnd/cores/pmu/bhnd_pmu.h>
 
 #include <dev/bwn/if_bwnreg.h>
 #include <dev/bwn/if_bwnvar.h>
@@ -83,7 +86,9 @@ __FBSDID("$FreeBSD$");
 #include <dev/bwn/if_bwn_phy_common.h>
 #include <dev/bwn/if_bwn_phy_lp.h>
 
-static void	bwn_phy_lp_readsprom(struct bwn_mac *);
+#include "bhnd_nvram_map.h"
+
+static int	bwn_phy_lp_readsprom(struct bwn_mac *);
 static void	bwn_phy_lp_bbinit(struct bwn_mac *);
 static void	bwn_phy_lp_txpctl_init(struct bwn_mac *);
 static void	bwn_phy_lp_calib(struct bwn_mac *);
@@ -99,10 +104,10 @@ static void	bwn_phy_lp_digflt_restore(struct bwn_mac *);
 static void	bwn_phy_lp_tblinit(struct bwn_mac *);
 static void	bwn_phy_lp_bbinit_r2(struct bwn_mac *);
 static void	bwn_phy_lp_bbinit_r01(struct bwn_mac *);
-static void	bwn_phy_lp_b2062_init(struct bwn_mac *);
-static void	bwn_phy_lp_b2063_init(struct bwn_mac *);
-static void	bwn_phy_lp_rxcal_r2(struct bwn_mac *);
-static void	bwn_phy_lp_rccal_r12(struct bwn_mac *);
+static int	bwn_phy_lp_b2062_init(struct bwn_mac *);
+static int	bwn_phy_lp_b2063_init(struct bwn_mac *);
+static int	bwn_phy_lp_rxcal_r2(struct bwn_mac *);
+static int	bwn_phy_lp_rccal_r12(struct bwn_mac *);
 static void	bwn_phy_lp_set_rccap(struct bwn_mac *);
 static uint32_t	bwn_phy_lp_roundup(uint32_t, uint32_t, uint8_t);
 static void	bwn_phy_lp_b2062_reset_pllbias(struct bwn_mac *);
@@ -409,7 +414,16 @@ bwn_phy_lp_init(struct bwn_mac *mac)
 	int i, error;
 	uint16_t tmp;
 
-	bwn_phy_lp_readsprom(mac);	/* XXX bad place */
+	/* All LP-PHY devices have a PMU */
+	if (sc->sc_pmu == NULL) {
+		device_printf(sc->sc_dev, "no PMU; cannot configure PAREF "
+		    "LDO\n");
+		return (ENXIO);
+	}
+
+	if ((error = bwn_phy_lp_readsprom(mac)))
+		return (error);
+
 	bwn_phy_lp_bbinit(mac);
 
 	/* initialize RF */
@@ -418,10 +432,12 @@ bwn_phy_lp_init(struct bwn_mac *mac)
 	BWN_PHY_MASK(mac, BWN_PHY_4WIRECTL, 0xfffd);
 	DELAY(1);
 
-	if (mac->mac_phy.rf_ver == 0x2062)
-		bwn_phy_lp_b2062_init(mac);
-	else {
-		bwn_phy_lp_b2063_init(mac);
+	if (mac->mac_phy.rf_ver == 0x2062) {
+		if ((error = bwn_phy_lp_b2062_init(mac)))
+			return (error);
+	} else {
+		if ((error = bwn_phy_lp_b2063_init(mac)))
+			return (error);
 
 		/* synchronize stx table. */
 		for (i = 0; i < N(tables); i++) {
@@ -439,11 +455,14 @@ bwn_phy_lp_init(struct bwn_mac *mac)
 	}
 
 	/* calibrate RC */
-	if (mac->mac_phy.rev >= 2)
-		bwn_phy_lp_rxcal_r2(mac);
-	else if (!plp->plp_rccap) {
-		if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
-			bwn_phy_lp_rccal_r12(mac);
+	if (mac->mac_phy.rev >= 2) {
+		if ((error = bwn_phy_lp_rxcal_r2(mac)))
+			return (error);
+	} else if (!plp->plp_rccap) {
+		if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
+			if ((error = bwn_phy_lp_rccal_r12(mac)))
+				return (error);
+		}
 	} else
 		bwn_phy_lp_set_rccap(mac);
 
@@ -586,31 +605,62 @@ bwn_phy_lp_task_60s(struct bwn_mac *mac)
 	bwn_phy_lp_calib(mac);
 }
 
-static void
+static int
 bwn_phy_lp_readsprom(struct bwn_mac *mac)
 {
 	struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
 	struct bwn_softc *sc = mac->mac_sc;
 	struct ieee80211com *ic = &sc->sc_ic;
 
+#define	BWN_PHY_LP_READVAR(_dev, _type, _name, _result)		\
+do {									\
+	int error;							\
+									\
+	error = bhnd_nvram_getvar_ ##_type((_dev), (_name), (_result));	\
+	if (error) {							\
+		device_printf((_dev), "NVRAM variable %s unreadable: "	\
+		    "%d\n", (_name), error);				\
+		return (error);						\
+	}								\
+} while(0)
+
 	if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) {
-		plp->plp_txisoband_m = siba_sprom_get_tri2g(sc->sc_dev);
-		plp->plp_bxarch = siba_sprom_get_bxa2g(sc->sc_dev);
-		plp->plp_rxpwroffset = siba_sprom_get_rxpo2g(sc->sc_dev);
-		plp->plp_rssivf = siba_sprom_get_rssismf2g(sc->sc_dev);
-		plp->plp_rssivc = siba_sprom_get_rssismc2g(sc->sc_dev);
-		plp->plp_rssigs = siba_sprom_get_rssisav2g(sc->sc_dev);
-		return;
+		BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI2G,
+		    &plp->plp_txisoband_m);
+		BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_BXA2G,
+		    &plp->plp_bxarch);
+		BWN_PHY_LP_READVAR(sc->sc_dev, int8, BHND_NVAR_RXPO2G,
+		    &plp->plp_rxpwroffset);
+		BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMF2G,
+		    &plp->plp_rssivf);
+		BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMC2G,
+		    &plp->plp_rssivc);
+		BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISAV2G,
+		    &plp->plp_rssigs);
+
+		return (0);
 	}
 
-	plp->plp_txisoband_l = siba_sprom_get_tri5gl(sc->sc_dev);
-	plp->plp_txisoband_m = siba_sprom_get_tri5g(sc->sc_dev);
-	plp->plp_txisoband_h = siba_sprom_get_tri5gh(sc->sc_dev);
-	plp->plp_bxarch = siba_sprom_get_bxa5g(sc->sc_dev);
-	plp->plp_rxpwroffset = siba_sprom_get_rxpo5g(sc->sc_dev);
-	plp->plp_rssivf = siba_sprom_get_rssismf5g(sc->sc_dev);
-	plp->plp_rssivc = siba_sprom_get_rssismc5g(sc->sc_dev);
-	plp->plp_rssigs = siba_sprom_get_rssisav5g(sc->sc_dev);
+	BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5GL,
+	    &plp->plp_txisoband_l);
+	BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5G,
+	    &plp->plp_txisoband_m);
+	BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5GH,
+	    &plp->plp_txisoband_h);
+	BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_BXA5G,
+	    &plp->plp_bxarch);
+	BWN_PHY_LP_READVAR(sc->sc_dev, int8, BHND_NVAR_RXPO5G,
+	    &plp->plp_rxpwroffset);
+	BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMF5G,
+	    &plp->plp_rssivf);
+	BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMC5G,
+	    &plp->plp_rssivc);
+	BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISAV5G,
+	    &plp->plp_rssigs);
+
+#undef	BWN_PHY_LP_READVAR
+
+	return (0);
 }
 
 static void
@@ -686,7 +736,7 @@ bwn_phy_lp_calib(struct bwn_mac *mac)
 		bwn_phy_lp_digflt_restore(mac);
 
 	/* do RX IQ Calculation; assumes that noise is true. */
-	if (siba_get_chipid(sc->sc_dev) == 0x5354) {
+	if (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) {
 		for (i = 0; i < N(bwn_rxcompco_5354); i++) {
 			if (bwn_rxcompco_5354[i].rc_chan == plp->plp_chan)
 				rc = &bwn_rxcompco_5354[i];
@@ -766,10 +816,11 @@ bwn_phy_lp_b2063_switch_channel(struct bwn_mac *mac, uint8_t chan)
 {
 	static const struct bwn_b206x_chan *bc = NULL;
 	struct bwn_softc *sc = mac->mac_sc;
-	uint32_t count, freqref, freqvco, freqxtal, val[3], timeout, timeoutref,
+	uint32_t count, freqref, freqvco, val[3], timeout, timeoutref,
 	    tmp[6];
 	uint16_t old, scale, tmp16;
-	int i, div;
+	u_int freqxtal;
+	int error, i, div;
 
 	for (i = 0; i < N(bwn_b2063_chantable); i++) {
 		if (bwn_b2063_chantable[i].bc_chan == chan) {
@@ -780,6 +831,13 @@ bwn_phy_lp_b2063_switch_channel(struct bwn_mac *mac, uint8_t chan)
 	if (bc == NULL)
 		return (EINVAL);
 
+	error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal);
+	if (error) {
+		device_printf(sc->sc_dev, "failed to fetch clock frequency: %d",
+		    error);
+		return (error);
+	}
+
 	BWN_RF_WRITE(mac, BWN_B2063_LOGEN_VCOBUF1, bc->bc_data[0]);
 	BWN_RF_WRITE(mac, BWN_B2063_LOGEN_MIXER2, bc->bc_data[1]);
 	BWN_RF_WRITE(mac, BWN_B2063_LOGEN_BUF2, bc->bc_data[2]);
@@ -796,7 +854,6 @@ bwn_phy_lp_b2063_switch_channel(struct bwn_mac *mac, uint8_t chan)
 	old = BWN_RF_READ(mac, BWN_B2063_COM15);
 	BWN_RF_SET(mac, BWN_B2063_COM15, 0x1e);
 
-	freqxtal = siba_get_cc_pmufreq(sc->sc_dev) * 1000;
 	freqvco = bc->bc_freq << ((bc->bc_freq > 4000) ? 1 : 2);
 	freqref = freqxtal * 3;
 	div = (freqxtal <= 26000000 ? 1 : 2);
@@ -897,9 +954,9 @@ bwn_phy_lp_b2062_switch_channel(struct bwn_mac *mac, uint8_t chan)
 	struct bwn_softc *sc = mac->mac_sc;
 	struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
 	const struct bwn_b206x_chan *bc = NULL;
-	uint32_t freqxtal = siba_get_cc_pmufreq(sc->sc_dev) * 1000;
 	uint32_t tmp[9];
-	int i;
+	u_int freqxtal;
+	int error, i;
 
 	for (i = 0; i < N(bwn_b2062_chantable); i++) {
 		if (bwn_b2062_chantable[i].bc_chan == chan) {
@@ -911,6 +968,13 @@ bwn_phy_lp_b2062_switch_channel(struct bwn_mac *mac, uint8_t chan)
 	if (bc == NULL)
 		return (EINVAL);
 
+	error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal);
+	if (error) {
+		device_printf(sc->sc_dev, "failed to fetch clock frequency: %d",
+		    error);
+		return (error);
+	}
+
 	BWN_RF_SET(mac, BWN_B2062_S_RFPLLCTL14, 0x04);
 	BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE0, bc->bc_data[0]);
 	BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE2, bc->bc_data[1]);
@@ -1301,7 +1365,7 @@ bwn_phy_lp_bbinit_r2(struct bwn_mac *mac)
 	BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x4000);
 	BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x2000);
 	BWN_PHY_SET(mac, BWN_PHY_OFDM(0x10a), 0x1);
-	if (siba_get_pci_revid(sc->sc_dev) >= 0x18) {
+	if (sc->sc_board_info.board_rev >= 0x18) {
 		bwn_tab_write(mac, BWN_TAB_4(17, 65), 0xec);
 		BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x10a), 0xff01, 0x14);
 	} else {
@@ -1318,8 +1382,8 @@ bwn_phy_lp_bbinit_r2(struct bwn_mac *mac)
 	BWN_PHY_SETMASK(mac, BWN_PHY_CLIPCTRTHRESH, 0xfc1f, 0xa0);
 	BWN_PHY_SETMASK(mac, BWN_PHY_GAINDIRECTMISMATCH, 0xe0ff, 0x300);
 	BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0x00ff, 0x2a00);
-	if ((siba_get_chipid(sc->sc_dev) == 0x4325) &&
-	    (siba_get_chiprev(sc->sc_dev) == 0)) {
+	if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 &&
+	    sc->sc_cid.chip_pkg == 0) {
 		BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x2100);
 		BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0xa);
 	} else {
@@ -1328,8 +1392,8 @@ bwn_phy_lp_bbinit_r2(struct bwn_mac *mac)
 	}
 	for (i = 0; i < N(v3); i++)
 		BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask, v3[i].set);
-	if ((siba_get_chipid(sc->sc_dev) == 0x4325) &&
-	    (siba_get_chiprev(sc->sc_dev) == 0)) {
+	if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 &&
+	    sc->sc_cid.chip_pkg == 0) {
 		bwn_tab_write(mac, BWN_TAB_2(0x08, 0x14), 0);
 		bwn_tab_write(mac, BWN_TAB_2(0x08, 0x12), 0x40);
 	}
@@ -1354,8 +1418,8 @@ bwn_phy_lp_bbinit_r2(struct bwn_mac *mac)
 	    0x2000 | ((uint16_t)plp->plp_rssigs << 10) |
 	    ((uint16_t)plp->plp_rssivc << 4) | plp->plp_rssivf);
 
-	if ((siba_get_chipid(sc->sc_dev) == 0x4325) &&
-	    (siba_get_chiprev(sc->sc_dev) == 0)) {
+	if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 &&
+	    sc->sc_cid.chip_pkg == 0) {
 		BWN_PHY_SET(mac, BWN_PHY_AFE_ADC_CTL_0, 0x1c);
 		BWN_PHY_SETMASK(mac, BWN_PHY_AFE_CTL, 0x00ff, 0x8800);
 		BWN_PHY_SETMASK(mac, BWN_PHY_AFE_ADC_CTL_1, 0xfc3c, 0x0400);
@@ -1427,7 +1491,7 @@ bwn_phy_lp_bbinit_r01(struct bwn_mac *mac)
 		{ BWN_PHY_TR_LOOKUP_4, 0xffc0, 0x0006 },
 		{ BWN_PHY_TR_LOOKUP_4, 0xc0ff, 0x0700 }
 	};
-	int i;
+	int error, i;
 	uint16_t tmp, tmp2;
 
 	BWN_PHY_MASK(mac, BWN_PHY_AFE_DAC_CTL, 0xf7ff);
@@ -1449,23 +1513,38 @@ bwn_phy_lp_bbinit_r01(struct bwn_mac *mac)
 		BWN_PHY_SETMASK(mac, v1[i].offset, v1[i].mask, v1[i].set);
 	BWN_PHY_SETMASK(mac, BWN_PHY_INPUT_PWRDB,
 	    0xff00, plp->plp_rxpwroffset);
-	if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM) &&
+	if ((sc->sc_board_info.board_flags & BHND_BFL_FEM) &&
 	    ((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) ||
-	   (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_LDO_PAREF))) {
-		siba_cc_pmu_set_ldovolt(sc->sc_dev, SIBA_LDO_PAREF, 0x28);
-		siba_cc_pmu_set_ldoparef(sc->sc_dev, 1);
+	   (sc->sc_board_info.board_flags & BHND_BFL_PAREF))) {
+		error = bhnd_pmu_set_voltage_raw(sc->sc_pmu,
+		    BHND_REGULATOR_PAREF_LDO, 0x28);
+		if (error)
+			device_printf(sc->sc_dev, "failed to set PAREF LDO "
+			    "voltage: %d\n", error);
+
+		error = bhnd_pmu_enable_regulator(sc->sc_pmu,
+		    BHND_REGULATOR_PAREF_LDO);
+		if (error)
+			device_printf(sc->sc_dev, "failed to enable PAREF LDO "
+			    "regulator: %d\n", error);
+
 		if (mac->mac_phy.rev == 0)
 			BWN_PHY_SETMASK(mac, BWN_PHY_LP_RF_SIGNAL_LUT,
 			    0xffcf, 0x0010);
 		bwn_tab_write(mac, BWN_TAB_2(11, 7), 60);
 	} else {
-		siba_cc_pmu_set_ldoparef(sc->sc_dev, 0);
+		error = bhnd_pmu_disable_regulator(sc->sc_pmu,
+		    BHND_REGULATOR_PAREF_LDO);
+		if (error)
+			device_printf(sc->sc_dev, "failed to disable PAREF LDO "
+			    "regulator: %d\n", error);
+
 		BWN_PHY_SETMASK(mac, BWN_PHY_LP_RF_SIGNAL_LUT, 0xffcf, 0x0020);
 		bwn_tab_write(mac, BWN_TAB_2(11, 7), 100);
 	}
 	tmp = plp->plp_rssivf | plp->plp_rssivc << 4 | 0xa000;
 	BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_0, tmp);
-	if (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_RSSIINV)
+	if (sc->sc_board_info.board_flags & BHND_BFL_RSSIINV)
 		BWN_PHY_SETMASK(mac, BWN_PHY_AFE_RSSI_CTL_1, 0xf000, 0x0aaa);
 	else
 		BWN_PHY_SETMASK(mac, BWN_PHY_AFE_RSSI_CTL_1, 0xf000, 0x02aa);
@@ -1473,19 +1552,19 @@ bwn_phy_lp_bbinit_r01(struct bwn_mac *mac)
 	BWN_PHY_SETMASK(mac, BWN_PHY_RX_RADIO_CTL,
 	    0xfff9, (plp->plp_bxarch << 1));
 	if (mac->mac_phy.rev == 1 &&
-	    (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_FEM_BT)) {
+	    (sc->sc_board_info.board_flags & BHND_BFL_FEM_BT)) {
 		for (i = 0; i < N(v2); i++)
 			BWN_PHY_SETMASK(mac, v2[i].offset, v2[i].mask,
 			    v2[i].set);
 	} else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ||
-	    (siba_get_pci_subdevice(sc->sc_dev) == 0x048a) ||
+	    (sc->sc_board_info.board_type == 0x048a) ||
 	    ((mac->mac_phy.rev == 0) &&
-	     (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM))) {
+	     (sc->sc_board_info.board_flags & BHND_BFL_FEM))) {
 		for (i = 0; i < N(v3); i++)
 			BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask,
 			    v3[i].set);
 	} else if (mac->mac_phy.rev == 1 ||
-		  (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM)) {
+		  (sc->sc_board_info.board_flags & BHND_BFL_FEM)) {
 		for (i = 0; i < N(v4); i++)
 			BWN_PHY_SETMASK(mac, v4[i].offset, v4[i].mask,
 			    v4[i].set);
@@ -1495,15 +1574,15 @@ bwn_phy_lp_bbinit_r01(struct bwn_mac *mac)
 			    v5[i].set);
 	}
 	if (mac->mac_phy.rev == 1 &&
-	    (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_LDO_PAREF)) {
+	    (sc->sc_board_info.board_flags & BHND_BFL_PAREF)) {
 		BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_5, BWN_PHY_TR_LOOKUP_1);
 		BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_6, BWN_PHY_TR_LOOKUP_2);
 		BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_7, BWN_PHY_TR_LOOKUP_3);
 		BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_8, BWN_PHY_TR_LOOKUP_4);
 	}
-	if ((siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_FEM_BT) &&
-	    (siba_get_chipid(sc->sc_dev) == 0x5354) &&
-	    (siba_get_chippkg(sc->sc_dev) == SIBA_CHIPPACK_BCM4712S)) {
+	if ((sc->sc_board_info.board_flags & BHND_BFL_FEM_BT) &&
+	    (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) &&
+	    (sc->sc_cid.chip_pkg == BHND_PKGID_BCM4712SMALL)) {
 		BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x0006);
 		BWN_PHY_WRITE(mac, BWN_PHY_GPIO_SELECT, 0x0005);
 		BWN_PHY_WRITE(mac, BWN_PHY_GPIO_OUTEN, 0xffff);
@@ -1543,7 +1622,7 @@ struct bwn_b2062_freq {
 	uint8_t			value[6];
 };
 
-static void
+static int
 bwn_phy_lp_b2062_init(struct bwn_mac *mac)
 {
 #define	CALC_CTL7(freq, div)						\
@@ -1574,8 +1653,17 @@ bwn_phy_lp_b2062_init(struct bwn_mac *mac)
 		{ BWN_B2062_N_CALIB_TS, 0 }
 	};
 	const struct bwn_b2062_freq *f = NULL;
-	uint32_t xtalfreq, ref;
+	uint32_t ref;
+	u_int xtalfreq;
 	unsigned int i;
+	int error;
+
+	error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &xtalfreq);
+	if (error) {
+		device_printf(sc->sc_dev, "failed to fetch clock frequency: %d",
+		    error);
+		return (error);
+	}
 
 	bwn_phy_lp_b2062_tblinit(mac);
 
@@ -1589,11 +1677,6 @@ bwn_phy_lp_b2062_init(struct bwn_mac *mac)
 	else
 		BWN_RF_MASK(mac, BWN_B2062_N_TSSI_CTL0, ~0x1);
 
-	KASSERT(siba_get_cc_caps(sc->sc_dev) & SIBA_CC_CAPS_PMU,
-	    ("%s:%d: fail", __func__, __LINE__));
-	xtalfreq = siba_get_cc_pmufreq(sc->sc_dev) * 1000;
-	KASSERT(xtalfreq != 0, ("%s:%d: fail", __func__, __LINE__));
-
 	if (xtalfreq <= 30000000) {
 		plp->plp_div = 1;
 		BWN_RF_MASK(mac, BWN_B2062_S_RFPLLCTL1, 0xfffb);
@@ -1625,12 +1708,14 @@ bwn_phy_lp_b2062_init(struct bwn_mac *mac)
 	    ((uint16_t)(f->value[3]) << 4) | f->value[2]);
 	BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL10, f->value[4]);
 	BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL11, f->value[5]);
+
+	return (0);
 #undef CALC_CTL7
 #undef CALC_CTL18
 #undef CALC_CTL19
 }
 
-static void
+static int
 bwn_phy_lp_b2063_init(struct bwn_mac *mac)
 {
 
@@ -1650,9 +1735,11 @@ bwn_phy_lp_b2063_init(struct bwn_mac *mac)
 		BWN_RF_WRITE(mac, BWN_B2063_PA_SP3, 0x20);
 		BWN_RF_WRITE(mac, BWN_B2063_PA_SP2, 0x20);
 	}
+
+	return (0);
 }
 
-static void
+static int
 bwn_phy_lp_rxcal_r2(struct bwn_mac *mac)
 {
 	struct bwn_softc *sc = mac->mac_sc;
@@ -1673,10 +1760,17 @@ bwn_phy_lp_rxcal_r2(struct bwn_mac *mac)
 		{ BWN_B2063_RC_CALIB_CTL2, 0x55 },
 		{ BWN_B2063_RC_CALIB_CTL3, 0x76 }
 	};
-	uint32_t freqxtal = siba_get_cc_pmufreq(sc->sc_dev) * 1000;
-	int i;
+	u_int freqxtal;
+	int error, i;
 	uint8_t tmp;
 
+	error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal);
+	if (error) {
+		device_printf(sc->sc_dev, "failed to fetch clock frequency: %d",
+		    error);
+		return (error);
+	}
+
 	tmp = BWN_RF_READ(mac, BWN_B2063_RX_BB_SP8) & 0xff;
 
 	for (i = 0; i < 2; i++)
@@ -1713,9 +1807,11 @@ bwn_phy_lp_rxcal_r2(struct bwn_mac *mac)
 	if (!(BWN_RF_READ(mac, BWN_B2063_RC_CALIB_CTL6) & 0x2))
 		BWN_RF_WRITE(mac, BWN_B2063_TX_BB_SP3, tmp);
 	BWN_RF_WRITE(mac, BWN_B2063_RC_CALIB_CTL1, 0x7e);
+
+	return (0);
 }
 
-static void
+static int
 bwn_phy_lp_rccal_r12(struct bwn_mac *mac)
 {
 	struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp;
@@ -1831,6 +1927,8 @@ done:
 	bwn_phy_lp_set_txpctlmode(mac, txpctlmode);
 	if (plp->plp_rccap)
 		bwn_phy_lp_set_rccap(mac);
+
+	return (0);
 }
 
 static void
@@ -1876,7 +1974,7 @@ bwn_phy_lp_b2062_reset_pllbias(struct bwn_mac *mac)
 
 	BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 0xff);
 	DELAY(20);
-	if (siba_get_chipid(sc->sc_dev) == 0x5354) {
+	if (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) {
 		BWN_RF_WRITE(mac, BWN_B2062_N_COM1, 4);
 		BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 4);
 	} else {
@@ -2735,8 +2833,8 @@ bwn_phy_lp_tblinit_r2(struct bwn_mac *mac)
 	bwn_tab_write_multi(mac, BWN_TAB_4(9, 0), N(papdeps), papdeps);
 	bwn_tab_write_multi(mac, BWN_TAB_4(10, 0), N(papdmult), papdmult);
 
-	if ((siba_get_chipid(sc->sc_dev) == 0x4325) &&
-	    (siba_get_chiprev(sc->sc_dev) == 0)) {
+	if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 &&
+	    sc->sc_cid.chip_pkg == 0) {
 		bwn_tab_write_multi(mac, BWN_TAB_4(13, 0), N(gainidx_a0),
 		    gainidx_a0);
 		bwn_tab_write_multi(mac, BWN_TAB_2(14, 0), N(auxgainidx_a0),
@@ -3353,7 +3451,7 @@ bwn_phy_lp_tblinit_txgain(struct bwn_mac *mac)
 	};
 
 	if (mac->mac_phy.rev != 0 && mac->mac_phy.rev != 1) {
-		if (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_NOPA)
+		if (sc->sc_board_info.board_flags & BHND_BFL_NOPA)
 			bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r2);
 		else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
 			bwn_phy_lp_gaintbl_write_multi(mac, 0, 128,
@@ -3365,8 +3463,8 @@ bwn_phy_lp_tblinit_txgain(struct bwn_mac *mac)
 	}
 
 	if (mac->mac_phy.rev == 0) {
-		if ((siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_NOPA) ||
-		    (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_HGPA))
+		if ((sc->sc_board_info.board_flags & BHND_BFL_NOPA) ||
+		    (sc->sc_board_info.board_flags & BHND_BFL_HGPA))
 			bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r0);
 		else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
 			bwn_phy_lp_gaintbl_write_multi(mac, 0, 128,
@@ -3377,8 +3475,8 @@ bwn_phy_lp_tblinit_txgain(struct bwn_mac *mac)
 		return;
 	}
 
-	if ((siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_NOPA) ||
-	    (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_HGPA))
+	if ((sc->sc_board_info.board_flags & BHND_BFL_NOPA) ||
+	    (sc->sc_board_info.board_flags & BHND_BFL_HGPA))
 		bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r1);
 	else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
 		bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_2ghz_r1);
diff --git a/sys/dev/bwn/if_bwn_phy_n.c b/sys/dev/bwn/if_bwn_phy_n.c
index 1a01c2c12d44..937bd9352da5 100644
--- a/sys/dev/bwn/if_bwn_phy_n.c
+++ b/sys/dev/bwn/if_bwn_phy_n.c
@@ -72,8 +72,6 @@ __FBSDID("$FreeBSD$");
 #include <net80211/ieee80211_phy.h>
 #include <net80211/ieee80211_ratectl.h>
 
-#include <dev/bwn/if_bwn_siba.h>
-
 #include <dev/bwn/if_bwnreg.h>
 #include <dev/bwn/if_bwnvar.h>
 
@@ -121,8 +119,7 @@ bwn_phy_n_prepare_hw(struct bwn_mac *mac)
 {
 
 #ifdef	BWN_GPL_PHY
-	bwn_nphy_op_prepare_structs(mac);
-	return (0);
+	return (bwn_nphy_op_prepare_structs(mac));
 #else
 	return (ENXIO);
 #endif
diff --git a/sys/dev/bwn/if_bwn_siba.c b/sys/dev/bwn/if_bwn_siba.c
deleted file mode 100644
index f01381636a8a..000000000000
--- a/sys/dev/bwn/if_bwn_siba.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/bus.h>
-#include <sys/systm.h>
-
-#include <machine/bus.h>
-#include <sys/rman.h>
-#include <machine/resource.h>
-
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-
-#define	BWN_USE_SIBA	1
-#include "if_bwn_siba.h"
-
-/** Legacy siba(4) bus operations */
-
-static int
-bwn_siba_bus_ops_init(device_t dev)
-{
-	return (0);
-}
-
-static void
-bwn_siba_bus_ops_fini(device_t dev)
-{
-}
-
-const struct bwn_bus_ops bwn_siba_bus_ops = {
-	.init				= bwn_siba_bus_ops_init,
-	.fini				= bwn_siba_bus_ops_fini,
-	.pci_find_cap			= pci_find_cap,
-	.pci_alloc_msi			= pci_alloc_msi,
-	.pci_release_msi		= pci_release_msi,
-	.pci_msi_count			= pci_msi_count,
-	.get_vendor			= siba_get_vendor,
-	.get_device			= siba_get_device,
-	.get_revid			= siba_get_revid,
-	.get_pci_vendor			= siba_get_pci_vendor,
-	.get_pci_device			= siba_get_pci_device,
-	.get_pci_subvendor		= siba_get_pci_subvendor,
-	.get_pci_subdevice		= siba_get_pci_subdevice,
-	.get_pci_revid			= siba_get_pci_revid,
-	.get_chipid			= siba_get_chipid,
-	.get_chiprev			= siba_get_chiprev,
-	.get_chippkg			= siba_get_chippkg,
-	.get_type			= siba_get_type,
-	.get_cc_pmufreq			= siba_get_cc_pmufreq,
-	.get_cc_caps			= siba_get_cc_caps,
-	.get_cc_powerdelay		= siba_get_cc_powerdelay,
-	.get_pcicore_revid		= siba_get_pcicore_revid,
-	.sprom_get_rev			= siba_sprom_get_rev,
-	.sprom_get_mac_80211bg		= siba_sprom_get_mac_80211bg,
-	.sprom_get_mac_80211a		= siba_sprom_get_mac_80211a,
-	.sprom_get_brev			= siba_sprom_get_brev,
-	.sprom_get_ccode		= siba_sprom_get_ccode,
-	.sprom_get_ant_a		= siba_sprom_get_ant_a,
-	.sprom_get_ant_bg		= siba_sprom_get_ant_bg,
-	.sprom_get_pa0b0		= siba_sprom_get_pa0b0,
-	.sprom_get_pa0b1		= siba_sprom_get_pa0b1,
-	.sprom_get_pa0b2		= siba_sprom_get_pa0b2,
-	.sprom_get_gpio0		= siba_sprom_get_gpio0,
-	.sprom_get_gpio1		= siba_sprom_get_gpio1,
-	.sprom_get_gpio2		= siba_sprom_get_gpio2,
-	.sprom_get_gpio3		= siba_sprom_get_gpio3,
-	.sprom_get_maxpwr_bg		= siba_sprom_get_maxpwr_bg,
-	.sprom_set_maxpwr_bg		= siba_sprom_set_maxpwr_bg,
-	.sprom_get_rxpo2g		= siba_sprom_get_rxpo2g,
-	.sprom_get_rxpo5g		= siba_sprom_get_rxpo5g,
-	.sprom_get_tssi_bg		= siba_sprom_get_tssi_bg,
-	.sprom_get_tri2g		= siba_sprom_get_tri2g,
-	.sprom_get_tri5gl		= siba_sprom_get_tri5gl,
-	.sprom_get_tri5g		= siba_sprom_get_tri5g,
-	.sprom_get_tri5gh		= siba_sprom_get_tri5gh,
-	.sprom_get_rssisav2g		= siba_sprom_get_rssisav2g,
-	.sprom_get_rssismc2g		= siba_sprom_get_rssismc2g,
-	.sprom_get_rssismf2g		= siba_sprom_get_rssismf2g,
-	.sprom_get_bxa2g		= siba_sprom_get_bxa2g,
-	.sprom_get_rssisav5g		= siba_sprom_get_rssisav5g,
-	.sprom_get_rssismc5g		= siba_sprom_get_rssismc5g,
-	.sprom_get_rssismf5g		= siba_sprom_get_rssismf5g,
-	.sprom_get_bxa5g		= siba_sprom_get_bxa5g,
-	.sprom_get_cck2gpo		= siba_sprom_get_cck2gpo,
-	.sprom_get_ofdm2gpo		= siba_sprom_get_ofdm2gpo,
-	.sprom_get_ofdm5glpo		= siba_sprom_get_ofdm5glpo,
-	.sprom_get_ofdm5gpo		= siba_sprom_get_ofdm5gpo,
-	.sprom_get_ofdm5ghpo		= siba_sprom_get_ofdm5ghpo,
-	.sprom_get_bf_lo		= siba_sprom_get_bf_lo,
-	.sprom_set_bf_lo		= siba_sprom_set_bf_lo,
-	.sprom_get_bf_hi		= siba_sprom_get_bf_hi,
-	.sprom_get_bf2_lo		= siba_sprom_get_bf2_lo,
-	.sprom_get_bf2_hi		= siba_sprom_get_bf2_hi,
-	.sprom_get_fem_2ghz_tssipos	= siba_sprom_get_fem_2ghz_tssipos,
-	.sprom_get_fem_2ghz_extpa_gain	= siba_sprom_get_fem_2ghz_extpa_gain,
-	.sprom_get_fem_2ghz_pdet_range	= siba_sprom_get_fem_2ghz_pdet_range,
-	.sprom_get_fem_2ghz_tr_iso	= siba_sprom_get_fem_2ghz_tr_iso,
-	.sprom_get_fem_2ghz_antswlut	= siba_sprom_get_fem_2ghz_antswlut,
-	.sprom_get_fem_5ghz_extpa_gain	= siba_sprom_get_fem_5ghz_extpa_gain,
-	.sprom_get_fem_5ghz_pdet_range	= siba_sprom_get_fem_5ghz_pdet_range,
-	.sprom_get_fem_5ghz_antswlut	= siba_sprom_get_fem_5ghz_antswlut,
-	.sprom_get_txpid_2g_0		= siba_sprom_get_txpid_2g_0,
-	.sprom_get_txpid_2g_1		= siba_sprom_get_txpid_2g_1,
-	.sprom_get_txpid_5gl_0		= siba_sprom_get_txpid_5gl_0,
-	.sprom_get_txpid_5gl_1		= siba_sprom_get_txpid_5gl_1,
-	.sprom_get_txpid_5g_0		= siba_sprom_get_txpid_5g_0,
-	.sprom_get_txpid_5g_1		= siba_sprom_get_txpid_5g_1,
-	.sprom_get_txpid_5gh_0		= siba_sprom_get_txpid_5gh_0,
-	.sprom_get_txpid_5gh_1		= siba_sprom_get_txpid_5gh_1,
-	.sprom_get_stbcpo		= siba_sprom_get_stbcpo,
-	.sprom_get_cddpo		= siba_sprom_get_cddpo,
-	.powerup			= siba_powerup,
-	.powerdown			= siba_powerdown,
-	.read_2				= siba_read_2,
-	.write_2			= siba_write_2,
-	.read_4				= siba_read_4,
-	.write_4			= siba_write_4,
-	.dev_up				= siba_dev_up,
-	.dev_down			= siba_dev_down,
-	.dev_isup			= siba_dev_isup,
-	.pcicore_intr			= siba_pcicore_intr,
-	.dma_translation		= siba_dma_translation,
-	.read_multi_2			= siba_read_multi_2,
-	.read_multi_4			= siba_read_multi_4,
-	.write_multi_2			= siba_write_multi_2,
-	.write_multi_4			= siba_write_multi_4,
-	.barrier			= siba_barrier,
-	.cc_pmu_set_ldovolt		= siba_cc_pmu_set_ldovolt,
-	.cc_pmu_set_ldoparef		= siba_cc_pmu_set_ldoparef,
-	.gpio_set			= siba_gpio_set,
-	.gpio_get			= siba_gpio_get,
-	.fix_imcfglobug			= siba_fix_imcfglobug,
-	.sprom_get_core_power_info	= siba_sprom_get_core_power_info,
-	.sprom_get_mcs2gpo		= siba_sprom_get_mcs2gpo,
-	.sprom_get_mcs5glpo		= siba_sprom_get_mcs5glpo,
-	.sprom_get_mcs5gpo		= siba_sprom_get_mcs5gpo,
-	.sprom_get_mcs5ghpo		= siba_sprom_get_mcs5ghpo,
-	.pmu_spuravoid_pllupdate	= siba_pmu_spuravoid_pllupdate,
-	.cc_set32			= siba_cc_set32,
-	.cc_mask32			= siba_cc_mask32,
-	.cc_write32			= siba_cc_write32,
-};
diff --git a/sys/dev/bwn/if_bwn_siba.h b/sys/dev/bwn/if_bwn_siba.h
deleted file mode 100644
index db97516c0d33..000000000000
--- a/sys/dev/bwn/if_bwn_siba.h
+++ /dev/null
@@ -1,491 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2016 Landon J. Fuller <landonf@FreeBSD.org>.
- * Copyright (c) 2007 Bruce M. Simpson.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _IF_BWN_SIBA_H_
-#define _IF_BWN_SIBA_H_
-
-/** If true, expose legacy siba_pci headers directly. Otherwise,
-  * we expose our siba/bhnd compatibility shims. */
-#ifndef	BWN_USE_SIBA
-#define	BWN_USE_SIBA	0
-#endif
-
-struct bwn_softc;
-struct siba_sprom_core_pwr_info;
-
-/*
- * Legacy siba(4) bus API compatibility shims.
- */
-struct bwn_bus_ops {
-	/* bus-specific initialization/finalization */
-	int		(*init)(device_t);
-	void		(*fini)(device_t);
-
-	/* compatibility shims */
-	int		(*pci_find_cap)(device_t, int, int *);
-	int		(*pci_alloc_msi)(device_t, int *);
-	int		(*pci_release_msi)(device_t);
-	int		(*pci_msi_count)(device_t);
-	uint16_t	(*get_vendor)(device_t);
-	uint16_t	(*get_device)(device_t);
-	uint8_t		(*get_revid)(device_t);
-	uint16_t	(*get_pci_vendor)(device_t);
-	uint16_t	(*get_pci_device)(device_t);
-	uint16_t	(*get_pci_subvendor)(device_t);
-	uint16_t	(*get_pci_subdevice)(device_t);
-	uint8_t		(*get_pci_revid)(device_t);
-	uint16_t	(*get_chipid)(device_t);
-	uint16_t	(*get_chiprev)(device_t);
-	uint8_t		(*get_chippkg)(device_t);
-	enum siba_type	(*get_type)(device_t);
-	uint32_t	(*get_cc_pmufreq)(device_t);
-	uint32_t	(*get_cc_caps)(device_t);
-	uint16_t	(*get_cc_powerdelay)(device_t);
-	uint8_t		(*get_pcicore_revid)(device_t);
-	uint8_t		(*sprom_get_rev)(device_t);
-	uint8_t		*(*sprom_get_mac_80211bg)(device_t);
-	uint8_t		*(*sprom_get_mac_80211a)(device_t);
-	uint8_t		(*sprom_get_brev)(device_t);
-	uint8_t		(*sprom_get_ccode)(device_t);
-	uint8_t		(*sprom_get_ant_a)(device_t);
-	uint8_t		(*sprom_get_ant_bg)(device_t);
-	uint16_t	(*sprom_get_pa0b0)(device_t);
-	uint16_t	(*sprom_get_pa0b1)(device_t);
-	uint16_t	(*sprom_get_pa0b2)(device_t);
-	uint8_t		(*sprom_get_gpio0)(device_t);
-	uint8_t		(*sprom_get_gpio1)(device_t);
-	uint8_t		(*sprom_get_gpio2)(device_t);
-	uint8_t		(*sprom_get_gpio3)(device_t);
-	uint16_t	(*sprom_get_maxpwr_bg)(device_t);
-	void		(*sprom_set_maxpwr_bg)(device_t, uint16_t);
-	uint8_t		(*sprom_get_rxpo2g)(device_t);
-	uint8_t		(*sprom_get_rxpo5g)(device_t);
-	uint8_t		(*sprom_get_tssi_bg)(device_t);
-	uint8_t		(*sprom_get_tri2g)(device_t);
-	uint8_t		(*sprom_get_tri5gl)(device_t);
-	uint8_t		(*sprom_get_tri5g)(device_t);
-	uint8_t		(*sprom_get_tri5gh)(device_t);
-	uint8_t		(*sprom_get_rssisav2g)(device_t);
-	uint8_t		(*sprom_get_rssismc2g)(device_t);
-	uint8_t		(*sprom_get_rssismf2g)(device_t);
-	uint8_t		(*sprom_get_bxa2g)(device_t);
-	uint8_t		(*sprom_get_rssisav5g)(device_t);
-	uint8_t		(*sprom_get_rssismc5g)(device_t);
-	uint8_t		(*sprom_get_rssismf5g)(device_t);
-	uint8_t		(*sprom_get_bxa5g)(device_t);
-	uint16_t	(*sprom_get_cck2gpo)(device_t);
-	uint32_t	(*sprom_get_ofdm2gpo)(device_t);
-	uint32_t	(*sprom_get_ofdm5glpo)(device_t);
-	uint32_t	(*sprom_get_ofdm5gpo)(device_t);
-	uint32_t	(*sprom_get_ofdm5ghpo)(device_t);
-	uint16_t	(*sprom_get_bf_lo)(device_t);
-	void		(*sprom_set_bf_lo)(device_t, uint16_t);
-	uint16_t	(*sprom_get_bf_hi)(device_t);
-	uint16_t	(*sprom_get_bf2_lo)(device_t);
-	uint16_t	(*sprom_get_bf2_hi)(device_t);
-	uint8_t		(*sprom_get_fem_2ghz_tssipos)(device_t);
-	uint8_t		(*sprom_get_fem_2ghz_extpa_gain)(device_t);
-	uint8_t		(*sprom_get_fem_2ghz_pdet_range)(device_t);
-	uint8_t		(*sprom_get_fem_2ghz_tr_iso)(device_t);
-	uint8_t		(*sprom_get_fem_2ghz_antswlut)(device_t);
-	uint8_t		(*sprom_get_fem_5ghz_extpa_gain)(device_t);
-	uint8_t		(*sprom_get_fem_5ghz_pdet_range)(device_t);
-	uint8_t		(*sprom_get_fem_5ghz_antswlut)(device_t);
-	uint8_t		(*sprom_get_txpid_2g_0)(device_t);
-	uint8_t		(*sprom_get_txpid_2g_1)(device_t);
-	uint8_t		(*sprom_get_txpid_5gl_0)(device_t);
-	uint8_t		(*sprom_get_txpid_5gl_1)(device_t);
-	uint8_t		(*sprom_get_txpid_5g_0)(device_t);
-	uint8_t		(*sprom_get_txpid_5g_1)(device_t);
-	uint8_t		(*sprom_get_txpid_5gh_0)(device_t);
-	uint8_t		(*sprom_get_txpid_5gh_1)(device_t);
-	uint16_t	(*sprom_get_stbcpo)(device_t);
-	uint16_t	(*sprom_get_cddpo)(device_t);
-	void		(*powerup)(device_t, int);
-	int		(*powerdown)(device_t);
-	uint16_t	(*read_2)(device_t, uint16_t);
-	void		(*write_2)(device_t, uint16_t, uint16_t);
-	uint32_t	(*read_4)(device_t, uint16_t);
-	void		(*write_4)(device_t, uint16_t, uint32_t);
-	void		(*dev_up)(device_t, uint32_t);
-	void		(*dev_down)(device_t, uint32_t);
-	int		(*dev_isup)(device_t);
-	void		(*pcicore_intr)(device_t);
-	uint32_t	(*dma_translation)(device_t);
-	void		(*read_multi_2)(device_t, void *, size_t, uint16_t);
-	void		(*read_multi_4)(device_t, void *, size_t, uint16_t);
-	void		(*write_multi_2)(device_t, const void *, size_t, uint16_t);
-	void		(*write_multi_4)(device_t, const void *, size_t, uint16_t);
-	void		(*barrier)(device_t, int);
-	void		(*cc_pmu_set_ldovolt)(device_t, int, uint32_t);
-	void		(*cc_pmu_set_ldoparef)(device_t, uint8_t);
-	void		(*gpio_set)(device_t, uint32_t);
-	uint32_t	(*gpio_get)(device_t);
-	void		(*fix_imcfglobug)(device_t);
-	int		(*sprom_get_core_power_info)(device_t, int, struct siba_sprom_core_pwr_info *);
-	int		(*sprom_get_mcs2gpo)(device_t, uint16_t *);
-	int		(*sprom_get_mcs5glpo)(device_t, uint16_t *);
-	int		(*sprom_get_mcs5gpo)(device_t, uint16_t *);
-	int		(*sprom_get_mcs5ghpo)(device_t, uint16_t *);
-	void		(*pmu_spuravoid_pllupdate)(device_t, int);
-	void		(*cc_set32)(device_t, uint32_t, uint32_t);
-	void		(*cc_mask32)(device_t, uint32_t, uint32_t);
-	void		(*cc_write32)(device_t, uint32_t, uint32_t);
-};
-
-#if BWN_USE_SIBA
-
-#include <dev/siba/siba_ids.h>
-#include <dev/siba/sibareg.h>
-#include <dev/siba/sibavar.h>
-
-#define	BWN_BUS_OPS_ATTACH(_dev)	(0)
-#define	BWN_BUS_OPS_DETACH(_dev)
-
-#else /* !BWN_USE_SIBA */
-
-struct bwn_bus_ops;
-
-extern const struct bwn_bus_ops bwn_siba_bus_ops;
-extern const struct bwn_bus_ops bwn_bhnd_bus_ops;
-
-/*
- * Declared in:
- *    /usr/home/landonf/Documents/Code/FreeBSD/svn/head/sys/dev/siba/siba_ids.h
- */
-
-struct siba_devid {
-    uint16_t sd_vendor;
-    uint16_t sd_device;
-    uint8_t sd_rev;
-    char *sd_desc;
-};
-
-#define	SIBA_DEV(_vendor, _cid, _rev, _msg)	\
-	{ SIBA_VID_##_vendor, SIBA_DEVID_##_cid, _rev, _msg }
-
-#define	SIBA_DEVID_80211		0x812
-#define	SIBA_VID_BROADCOM		0x4243
-
-/*
- * Declared in:
- *    /usr/home/landonf/Documents/Code/FreeBSD/svn/head/sys/dev/siba/sibareg.h
- */
-
-#define	SIBA_CC_CAPS_PMU		0x10000000
-#define	SIBA_CC_CHIPCTL			0x0028
-#define	SIBA_CC_CHIPCTL_ADDR		0x0650
-#define	SIBA_CC_CHIPCTL_DATA		0x0654
-
-#define	SIBA_DMA_TRANSLATION_MASK	0xc0000000
-
-#define	SIBA_TGSLOW			0x0f98
-#define	SIBA_TGSLOW_FGC			0x00020000
-
-#define	SIBA_TGSHIGH			0x0f9c
-#define	SIBA_TGSHIGH_DMA64		0x10000000
-
-#define	SIBA_BOARDVENDOR_DELL		0x1028
-#define	SIBA_BOARDVENDOR_BCM		0x14e4
-
-#define	SIBA_BOARD_BCM4309G		0x0421
-#define	SIBA_BOARD_BU4306		0x0416
-#define	SIBA_BOARD_BCM4321		0x046d
-
-#define	SIBA_CHIPPACK_BCM4712S		1
-
-
-/*
- * Declared in:
- *    /usr/home/landonf/Documents/Code/FreeBSD/svn/head/sys/dev/siba/sibavar.h
- */
-
-enum siba_type {
-	SIBA_TYPE_SSB			/* unused */,
-	SIBA_TYPE_PCI,
-	SIBA_TYPE_PCMCIA
-};
-
-/* TODO: need a real country code table */
-enum {
-	SIBA_CCODE_JAPAN,
-	SIBA_CCODE_UNKNOWN
-};
-
-struct siba_sprom_core_pwr_info {
-    uint8_t itssi_2g;
-    uint8_t itssi_5g;
-    uint8_t maxpwr_2g;
-    uint8_t maxpwr_5gl;
-    uint8_t maxpwr_5g;
-    uint8_t maxpwr_5gh;
-    int16_t pa_2g[3];
-    int16_t pa_5gl[4];
-    int16_t pa_5g[4];
-    int16_t pa_5gh[4];
-};
-
-#define	SIBA_LDO_PAREF	0
-
-#define	BWN_BUS_OPS_SC(_sc)	\
-	((_sc)->sc_bus_ops)
-
-#define	BWN_BUS_OPS(_dev)	\
-	BWN_BUS_OPS_SC((struct bwn_softc *)device_get_softc(_dev))
-
-#define	BWN_BUS_OPS_ATTACH(_dev)	\
-	BWN_BUS_OPS(_dev)->init(_dev)
-#define	BWN_BUS_OPS_DETACH(_dev)	\
-	BWN_BUS_OPS(_dev)->fini(_dev)
-
-#define	pci_find_cap(_dev, capability, capreg)	\
-	BWN_BUS_OPS(_dev)->pci_find_cap(_dev, capability, capreg)
-#define	pci_alloc_msi(_dev, count)	\
-	BWN_BUS_OPS(_dev)->pci_alloc_msi(_dev, count)
-#define	pci_release_msi(_dev)	\
-	BWN_BUS_OPS(_dev)->pci_release_msi(_dev)
-#define	pci_msi_count(_dev)	\
-	BWN_BUS_OPS(_dev)->pci_msi_count(_dev)
-
-#define	siba_get_vendor(_dev)	\
-	BWN_BUS_OPS(_dev)->get_vendor(_dev)
-#define	siba_get_device(_dev)	\
-	BWN_BUS_OPS(_dev)->get_device(_dev)
-#define	siba_get_revid(_dev)	\
-	BWN_BUS_OPS(_dev)->get_revid(_dev)
-#define	siba_get_pci_vendor(_dev)	\
-	BWN_BUS_OPS(_dev)->get_pci_vendor(_dev)
-#define	siba_get_pci_device(_dev)	\
-	BWN_BUS_OPS(_dev)->get_pci_device(_dev)
-#define	siba_get_pci_subvendor(_dev)	\
-	BWN_BUS_OPS(_dev)->get_pci_subvendor(_dev)
-#define	siba_get_pci_subdevice(_dev)	\
-	BWN_BUS_OPS(_dev)->get_pci_subdevice(_dev)
-#define	siba_get_pci_revid(_dev)	\
-	BWN_BUS_OPS(_dev)->get_pci_revid(_dev)
-#define	siba_get_chipid(_dev)	\
-	BWN_BUS_OPS(_dev)->get_chipid(_dev)
-#define	siba_get_chiprev(_dev)	\
-	BWN_BUS_OPS(_dev)->get_chiprev(_dev)
-#define	siba_get_chippkg(_dev)	\
-	BWN_BUS_OPS(_dev)->get_chippkg(_dev)
-#define	siba_get_type(_dev)	\
-	BWN_BUS_OPS(_dev)->get_type(_dev)
-#define	siba_get_cc_pmufreq(_dev)	\
-	BWN_BUS_OPS(_dev)->get_cc_pmufreq(_dev)
-#define	siba_get_cc_caps(_dev)	\
-	BWN_BUS_OPS(_dev)->get_cc_caps(_dev)
-#define	siba_get_cc_powerdelay(_dev)	\
-	BWN_BUS_OPS(_dev)->get_cc_powerdelay(_dev)
-#define	siba_get_pcicore_revid(_dev)	\
-	BWN_BUS_OPS(_dev)->get_pcicore_revid(_dev)
-#define	siba_sprom_get_rev(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rev(_dev)
-#define	siba_sprom_get_mac_80211bg(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_mac_80211bg(_dev)
-#define	siba_sprom_get_mac_80211a(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_mac_80211a(_dev)
-#define	siba_sprom_get_brev(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_brev(_dev)
-#define	siba_sprom_get_ccode(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_ccode(_dev)
-#define	siba_sprom_get_ant_a(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_ant_a(_dev)
-#define	siba_sprom_get_ant_bg(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_ant_bg(_dev)
-#define	siba_sprom_get_pa0b0(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_pa0b0(_dev)
-#define	siba_sprom_get_pa0b1(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_pa0b1(_dev)
-#define	siba_sprom_get_pa0b2(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_pa0b2(_dev)
-#define	siba_sprom_get_gpio0(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_gpio0(_dev)
-#define	siba_sprom_get_gpio1(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_gpio1(_dev)
-#define	siba_sprom_get_gpio2(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_gpio2(_dev)
-#define	siba_sprom_get_gpio3(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_gpio3(_dev)
-#define	siba_sprom_get_maxpwr_bg(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_maxpwr_bg(_dev)
-#define	siba_sprom_set_maxpwr_bg(_dev, t)	\
-	BWN_BUS_OPS(_dev)->sprom_set_maxpwr_bg(_dev, t)
-#define	siba_sprom_get_rxpo2g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rxpo2g(_dev)
-#define	siba_sprom_get_rxpo5g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rxpo5g(_dev)
-#define	siba_sprom_get_tssi_bg(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_tssi_bg(_dev)
-#define	siba_sprom_get_tri2g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_tri2g(_dev)
-#define	siba_sprom_get_tri5gl(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_tri5gl(_dev)
-#define	siba_sprom_get_tri5g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_tri5g(_dev)
-#define	siba_sprom_get_tri5gh(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_tri5gh(_dev)
-#define	siba_sprom_get_rssisav2g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rssisav2g(_dev)
-#define	siba_sprom_get_rssismc2g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rssismc2g(_dev)
-#define	siba_sprom_get_rssismf2g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rssismf2g(_dev)
-#define	siba_sprom_get_bxa2g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_bxa2g(_dev)
-#define	siba_sprom_get_rssisav5g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rssisav5g(_dev)
-#define	siba_sprom_get_rssismc5g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rssismc5g(_dev)
-#define	siba_sprom_get_rssismf5g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_rssismf5g(_dev)
-#define	siba_sprom_get_bxa5g(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_bxa5g(_dev)
-#define	siba_sprom_get_cck2gpo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_cck2gpo(_dev)
-#define	siba_sprom_get_ofdm2gpo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_ofdm2gpo(_dev)
-#define	siba_sprom_get_ofdm5glpo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_ofdm5glpo(_dev)
-#define	siba_sprom_get_ofdm5gpo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_ofdm5gpo(_dev)
-#define	siba_sprom_get_ofdm5ghpo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_ofdm5ghpo(_dev)
-#define	siba_sprom_get_bf_lo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_bf_lo(_dev)
-#define	siba_sprom_set_bf_lo(_dev, t)	\
-	BWN_BUS_OPS(_dev)->sprom_set_bf_lo(_dev, t)
-#define	siba_sprom_get_bf_hi(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_bf_hi(_dev)
-#define	siba_sprom_get_bf2_lo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_bf2_lo(_dev)
-#define	siba_sprom_get_bf2_hi(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_bf2_hi(_dev)
-#define	siba_sprom_get_fem_2ghz_tssipos(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_fem_2ghz_tssipos(_dev)
-#define	siba_sprom_get_fem_2ghz_extpa_gain(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_fem_2ghz_extpa_gain(_dev)
-#define	siba_sprom_get_fem_2ghz_pdet_range(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_fem_2ghz_pdet_range(_dev)
-#define	siba_sprom_get_fem_2ghz_tr_iso(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_fem_2ghz_tr_iso(_dev)
-#define	siba_sprom_get_fem_2ghz_antswlut(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_fem_2ghz_antswlut(_dev)
-#define	siba_sprom_get_fem_5ghz_extpa_gain(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_fem_5ghz_extpa_gain(_dev)
-#define	siba_sprom_get_fem_5ghz_pdet_range(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_fem_5ghz_pdet_range(_dev)
-#define	siba_sprom_get_fem_5ghz_antswlut(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_fem_5ghz_antswlut(_dev)
-#define	siba_sprom_get_txpid_2g_0(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_txpid_2g_0(_dev)
-#define	siba_sprom_get_txpid_2g_1(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_txpid_2g_1(_dev)
-#define	siba_sprom_get_txpid_5gl_0(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_txpid_5gl_0(_dev)
-#define	siba_sprom_get_txpid_5gl_1(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_txpid_5gl_1(_dev)
-#define	siba_sprom_get_txpid_5g_0(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_txpid_5g_0(_dev)
-#define	siba_sprom_get_txpid_5g_1(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_txpid_5g_1(_dev)
-#define	siba_sprom_get_txpid_5gh_0(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_txpid_5gh_0(_dev)
-#define	siba_sprom_get_txpid_5gh_1(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_txpid_5gh_1(_dev)
-#define	siba_sprom_get_stbcpo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_stbcpo(_dev)
-#define	siba_sprom_get_cddpo(_dev)	\
-	BWN_BUS_OPS(_dev)->sprom_get_cddpo(_dev)
-#define	siba_powerup(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->powerup(_dev, _arg1)
-#define	siba_powerdown(_dev)	\
-	BWN_BUS_OPS(_dev)->powerdown(_dev)
-#define	siba_read_2(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->read_2(_dev, _arg1)
-#define	siba_write_2(_dev, _arg1, _arg2)	\
-	BWN_BUS_OPS(_dev)->write_2(_dev, _arg1, _arg2)
-#define	siba_read_4(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->read_4(_dev, _arg1)
-#define	siba_write_4(_dev, _arg1, _arg2)	\
-	BWN_BUS_OPS(_dev)->write_4(_dev, _arg1, _arg2)
-#define	siba_dev_up(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->dev_up(_dev, _arg1)
-#define	siba_dev_down(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->dev_down(_dev, _arg1)
-#define	siba_dev_isup(_dev)	\
-	BWN_BUS_OPS(_dev)->dev_isup(_dev)
-#define	siba_pcicore_intr(_dev)	\
-	BWN_BUS_OPS(_dev)->pcicore_intr(_dev)
-#define	siba_dma_translation(_dev)	\
-	BWN_BUS_OPS(_dev)->dma_translation(_dev)
-#define	siba_read_multi_2(_dev, _arg1, _arg2, _arg3)	\
-	BWN_BUS_OPS(_dev)->read_multi_2(_dev, _arg1, _arg2, _arg3)
-#define	siba_read_multi_4(_dev, _arg1, _arg2, _arg3)	\
-	BWN_BUS_OPS(_dev)->read_multi_4(_dev, _arg1, _arg2, _arg3)
-#define	siba_write_multi_2(_dev, _arg1, _arg2, _arg3)	\
-	BWN_BUS_OPS(_dev)->write_multi_2(_dev, _arg1, _arg2, _arg3)
-#define	siba_write_multi_4(_dev, _arg1, _arg2, _arg3)	\
-	BWN_BUS_OPS(_dev)->write_multi_4(_dev, _arg1, _arg2, _arg3)
-#define	siba_barrier(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->barrier(_dev, _arg1)
-#define	siba_cc_pmu_set_ldovolt(_dev, _arg1, _arg2)	\
-	BWN_BUS_OPS(_dev)->cc_pmu_set_ldovolt(_dev, _arg1, _arg2)
-#define	siba_cc_pmu_set_ldoparef(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->cc_pmu_set_ldoparef(_dev, _arg1)
-#define	siba_gpio_set(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->gpio_set(_dev, _arg1)
-#define	siba_gpio_get(_dev)	\
-	BWN_BUS_OPS(_dev)->gpio_get(_dev)
-#define	siba_fix_imcfglobug(_dev)	\
-	BWN_BUS_OPS(_dev)->fix_imcfglobug(_dev)
-#define	siba_sprom_get_core_power_info(_dev, _arg1, _arg2)	\
-	BWN_BUS_OPS(_dev)->sprom_get_core_power_info(_dev, _arg1, _arg2)
-#define	siba_sprom_get_mcs2gpo(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->sprom_get_mcs2gpo(_dev, _arg1)
-#define	siba_sprom_get_mcs5glpo(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->sprom_get_mcs5glpo(_dev, _arg1)
-#define	siba_sprom_get_mcs5gpo(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->sprom_get_mcs5gpo(_dev, _arg1)
-#define	siba_sprom_get_mcs5ghpo(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->sprom_get_mcs5ghpo(_dev, _arg1)
-#define	siba_pmu_spuravoid_pllupdate(_dev, _arg1)	\
-	BWN_BUS_OPS(_dev)->pmu_spuravoid_pllupdate(_dev, _arg1)
-#define	siba_cc_set32(_dev, _arg1, _arg2)	\
-	BWN_BUS_OPS(_dev)->cc_set32(_dev, _arg1, _arg2)
-#define	siba_cc_mask32(_dev, _arg1, _arg2)	\
-	BWN_BUS_OPS(_dev)->cc_mask32(_dev, _arg1, _arg2)
-#define	siba_cc_write32(_dev, _arg1, _arg2)	\
-	BWN_BUS_OPS(_dev)->cc_write32(_dev, _arg1, _arg2)
-
-#endif /* BWN_USE_SIBA */
-
-#endif /* _IF_BWN_SIBA_H_ */
diff --git a/sys/dev/bwn/if_bwn_siba_compat.c b/sys/dev/bwn/if_bwn_siba_compat.c
deleted file mode 100644
index bd59c0097256..000000000000
--- a/sys/dev/bwn/if_bwn_siba_compat.c
+++ /dev/null
@@ -1,2577 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
- * Copyright (c) 2017 The FreeBSD Foundation
- * All rights reserved.
- * 
- * Portions of this software were developed by Landon Fuller
- * under sponsorship from the FreeBSD Foundation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include <sys/param.h>
-#include <sys/bus.h>
-#include <sys/gpio.h>
-#include <sys/kernel.h>
-#include <sys/systm.h>
-#include <sys/socket.h>
-#include <sys/sockio.h>
-
-#include <machine/bus.h>
-#include <sys/rman.h>
-#include <machine/resource.h>
-
-#include <net/ethernet.h>
-#include <net/if.h>
-#include <net/if_var.h>
-#include <net/if_arp.h>
-#include <net/if_dl.h>
-#include <net/if_llc.h>
-#include <net/if_media.h>
-#include <net/if_types.h>
-
-#include <dev/pci/pcireg.h>
-#include <dev/pci/pcivar.h>
-
-#include <net80211/ieee80211_var.h>
-#include <net80211/ieee80211_radiotap.h>
-#include <net80211/ieee80211_regdomain.h>
-#include <net80211/ieee80211_phy.h>
-#include <net80211/ieee80211_ratectl.h>
-
-#include <dev/bhnd/bhnd.h>
-#include <dev/bhnd/siba/sibareg.h>
-
-#include <dev/bhnd/cores/chipc/chipc.h>
-#include <dev/bhnd/cores/pci/bhnd_pcireg.h>
-#include <dev/bhnd/cores/pmu/bhnd_pmu.h>
-
-#include "gpio_if.h"
-
-#include "bhnd_nvram_map.h"
-
-#include "if_bwn_siba_compat.h"
-
-static int		bwn_bhnd_populate_nvram_data(device_t dev,
-			    struct bwn_bhnd_ctx *ctx);
-static inline bool	bwn_bhnd_is_siba_reg(device_t dev, uint16_t offset);
-
-#define	BWN_ASSERT_VALID_REG(_dev, _offset)				\
-	KASSERT(!bwn_bhnd_is_siba_reg(_dev, _offset),			\
-	    ("%s: accessing siba-specific register %#jx", __FUNCTION__,	\
-		(uintmax_t)(_offset)));
-
-static int
-bwn_bhnd_bus_ops_init(device_t dev)
-{
-	struct bwn_bhnd_ctx	*ctx;
-	struct bwn_softc	*sc;
-	const struct chipc_caps	*ccaps;
-	int			 error;
-
-	sc = device_get_softc(dev);
-	ctx = NULL;
-
-	sc->sc_mem_rid = 0;
-	sc->sc_mem_res = bhnd_alloc_resource_any(dev, SYS_RES_MEMORY,
-	    &sc->sc_mem_rid, RF_ACTIVE);
-	if (sc->sc_mem_res == NULL) {
-		return (ENXIO);
-	}
-
-	/* Allocate PMU state */
-	if ((error = bhnd_alloc_pmu(dev))) {
-		device_printf(dev, "PMU allocation failed: %d\n", error);
-		goto failed;
-	}
-
-	/* Allocate our context */
-	ctx = malloc(sizeof(struct bwn_bhnd_ctx), M_DEVBUF, M_WAITOK|M_ZERO);
-
-	/* Locate the ChipCommon device */
-	ctx->chipc_dev = bhnd_retain_provider(dev, BHND_SERVICE_CHIPC);
-	if (ctx->chipc_dev == NULL) {
-		device_printf(dev, "ChipCommon not found\n");
-		error = ENXIO;
-		goto failed;
-	}
-
-	/* Locate the GPIO device */
-	ctx->gpio_dev = bhnd_retain_provider(dev, BHND_SERVICE_GPIO);
-	if (ctx->gpio_dev == NULL) {
-		device_printf(dev, "GPIO not found\n");
-		error = ENXIO;
-		goto failed;
-	}
-
-	/* Locate the PMU device (if any) */
-	ccaps = BHND_CHIPC_GET_CAPS(ctx->chipc_dev);
-	if (ccaps->pmu) {
-		ctx->pmu_dev = bhnd_retain_provider(dev, BHND_SERVICE_PMU);
-		if (ctx->pmu_dev == NULL) {
-			device_printf(dev, "PMU not found\n");
-			error = ENXIO;
-			goto failed;
-		}
-	}
-
-	/* Populate NVRAM data */
-	if ((error = bwn_bhnd_populate_nvram_data(dev, ctx)))
-		goto failed;
-
-	/* Initialize bwn_softc */
-	sc->sc_bus_ctx = ctx;
-	return (0);
-
-failed:
-	bhnd_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
-	    sc->sc_mem_res);
-
-	if (ctx != NULL) {
-		if (ctx->chipc_dev != NULL) {
-			bhnd_release_provider(dev, ctx->chipc_dev,
-			    BHND_SERVICE_CHIPC);
-		}
-
-		if (ctx->gpio_dev != NULL) {
-			bhnd_release_provider(dev, ctx->gpio_dev,
-			    BHND_SERVICE_GPIO);
-		}
-
-		if (ctx->pmu_dev != NULL) {
-			bhnd_release_provider(dev, ctx->pmu_dev,
-			    BHND_SERVICE_PMU);
-		}
-
-		free(ctx, M_DEVBUF);
-	}
-
-	return (error);
-}
-
-static void
-bwn_bhnd_bus_ops_fini(device_t dev)
-{
-	struct bwn_bhnd_ctx	*ctx;
-	struct bwn_softc	*sc;
-
-	sc = device_get_softc(dev);
-	ctx = sc->sc_bus_ctx;
-
-	bhnd_release_pmu(dev);
-	bhnd_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
-	    sc->sc_mem_res);
-
-	bhnd_release_provider(dev, ctx->chipc_dev, BHND_SERVICE_CHIPC);
-	bhnd_release_provider(dev, ctx->gpio_dev, BHND_SERVICE_GPIO);
-
-	if (ctx->pmu_dev != NULL)
-		bhnd_release_provider(dev, ctx->pmu_dev, BHND_SERVICE_PMU);
-
-	free(ctx, M_DEVBUF);
-	sc->sc_bus_ctx = NULL;
-}
-
-
-/**
- * Return true if @p offset is within a siba-specific configuration register
- * block.
- */
-static inline bool
-bwn_bhnd_is_siba_reg(device_t dev, uint16_t offset)
-{
-	if (offset >= SIBA_CFG0_OFFSET &&
-	    offset <= SIBA_CFG0_OFFSET + SIBA_CFG_SIZE)
-		return (true);
-
-	if (offset >= SIBA_CFG1_OFFSET &&
-	    offset <= SIBA_CFG1_OFFSET + SIBA_CFG_SIZE)
-		return (true);
-	
-	return (false);
-}
-
-/* Populate SPROM values from NVRAM */
-static int
-bwn_bhnd_populate_nvram_data(device_t dev, struct bwn_bhnd_ctx *ctx)
-{
-	const char	*mac_80211bg_var, *mac_80211a_var;
-	int	error;
-
-	/* Fetch SROM revision */
-	error = bhnd_nvram_getvar_uint8(dev, BHND_NVAR_SROMREV, &ctx->sromrev);
-	if (error) {
-		device_printf(dev, "error reading %s: %d\n", BHND_NVAR_SROMREV,
-		    error);
-		return (error);
-	}
-
-	/* Fetch board flags */
-	error = bhnd_nvram_getvar_uint32(dev, BHND_NVAR_BOARDFLAGS,
-	    &ctx->boardflags);
-	if (error) {
-		device_printf(dev, "error reading %s: %d\n",
-		    BHND_NVAR_BOARDFLAGS, error);
-		return (error);
-	}
-
-	/* Fetch macaddrs if available; bwn(4) expects any missing macaddr
-	 * values to be initialized with 0xFF octets */
-	memset(ctx->mac_80211bg, 0xFF, sizeof(ctx->mac_80211bg));
-	memset(ctx->mac_80211a, 0xFF, sizeof(ctx->mac_80211a));
-
-	if (ctx->sromrev <= 2) {
-		mac_80211bg_var = BHND_NVAR_IL0MACADDR;
-		mac_80211a_var = BHND_NVAR_ET1MACADDR;
-	} else {
-		mac_80211bg_var = BHND_NVAR_MACADDR;
-		mac_80211a_var = NULL;
-	}
-
-	/* Fetch required D11 core 0 macaddr */
-	error = bhnd_nvram_getvar_array(dev, mac_80211bg_var, ctx->mac_80211bg,
-	    sizeof(ctx->mac_80211bg), BHND_NVRAM_TYPE_UINT8_ARRAY);
-	if (error) {
-		device_printf(dev, "error reading %s: %d\n", mac_80211bg_var,
-		    error);
-		return (error);
-	}
-
-	/* Fetch optional D11 core 1 macaddr */
-	if (mac_80211a_var != NULL) {
-		error = bhnd_nvram_getvar_array(dev, mac_80211a_var,
-		    ctx->mac_80211a, sizeof(ctx->mac_80211a),
-		    BHND_NVRAM_TYPE_UINT8_ARRAY);
-
-		if (error && error != ENOENT) {
-			device_printf(dev, "error reading %s: %d\n",
-			    mac_80211a_var, error);
-			return (error);
-		}
-	};
-
-	/* Fetch pa0maxpwr; bwn(4) expects to be able to modify it */
-	if ((ctx->sromrev >= 1 && ctx->sromrev <= 3) ||
-	    (ctx->sromrev >= 8 && ctx->sromrev <= 10))
-	{
-		error = bhnd_nvram_getvar_uint8(dev, BHND_NVAR_PA0MAXPWR,
-		     &ctx->pa0maxpwr);
-		if (error) {
-			device_printf(dev, "error reading %s: %d\n",
-			    BHND_NVAR_PA0MAXPWR, error);
-			return (error);
-		}
-	}
-
-	return (0);
-}
-
-/*
- * Disable PCI-specific MSI interrupt allocation handling
- */
-
-/*
- * pci_find_cap()
- *
- * Referenced by:
- *   bwn_attach()
- */
-static int
-bhnd_compat_pci_find_cap(device_t dev, int capability, int *capreg)
-{
-	return (ENODEV);
-}
-
-/*
- * pci_alloc_msi()
- *
- * Referenced by:
- *   bwn_attach()
- */
-static int
-bhnd_compat_pci_alloc_msi(device_t dev, int *count)
-{
-	return (ENODEV);
-}
-
-/*
- * pci_release_msi()
- *
- * Referenced by:
- *   bwn_attach()
- *   bwn_detach()
- */
-static int
-bhnd_compat_pci_release_msi(device_t dev)
-{
-	return (ENODEV);
-}
-
-/*
- * pci_msi_count()
- *
- * Referenced by:
- *   bwn_attach()
- */
-static int
-bhnd_compat_pci_msi_count(device_t dev)
-{
-	return (0);
-}
-
-/*
- * siba_get_vendor()
- *
- * Referenced by:
- *   bwn_probe()
- */
-static uint16_t
-bhnd_compat_get_vendor(device_t dev)
-{
-	uint16_t vendor = bhnd_get_vendor(dev);
-
-	switch (vendor) {
-	case BHND_MFGID_BCM:
-		return (SIBA_VID_BROADCOM);
-	default:
-		return (0x0000);
-	}
-}
-
-/*
- * siba_get_device()
- *
- * Referenced by:
- *   bwn_probe()
- */
-static uint16_t
-bhnd_compat_get_device(device_t dev)
-{
-	return (bhnd_get_device(dev));
-}
-
-/*
- * siba_get_revid()
- *
- * Referenced by:
- *   bwn_attach()
- *   bwn_attach_core()
- *   bwn_chip_init()
- *   bwn_chiptest()
- *   bwn_core_init()
- *   bwn_core_start()
- *   bwn_pio_idx2base()
- *   bwn_pio_set_txqueue()
- *   bwn_pio_tx_start()
- *   bwn_probe()
- * ... and 19 others
- * 
- */
-static uint8_t
-bhnd_compat_get_revid(device_t dev)
-{
-	return (bhnd_get_hwrev(dev));
-}
-
-/**
- * Return the PCI bridge root device.
- * 
- * Will panic if a PCI bridge root device is not found.
- */
-static device_t
-bwn_bhnd_get_pci_dev(device_t dev)
-{	device_t bridge_root;
-
-	bridge_root = bhnd_find_bridge_root(dev, devclass_find("pci"));
-	if (bridge_root == NULL)
-		panic("not a PCI device");
-
-	return (bridge_root);
-}
-
-/*
- * siba_get_pci_vendor()
- *
- * Referenced by:
- *   bwn_sprom_bugfixes()
- */
-static uint16_t
-bhnd_compat_get_pci_vendor(device_t dev)
-{
-	return (pci_get_vendor(bwn_bhnd_get_pci_dev(dev)));
-}
-
-/*
- * siba_get_pci_device()
- *
- * Referenced by:
- *   bwn_attach()
- *   bwn_attach_core()
- *   bwn_nphy_op_prepare_structs()
- *   bwn_sprom_bugfixes()
- */
-static uint16_t
-bhnd_compat_get_pci_device(device_t dev)
-{
-	return (pci_get_device(bwn_bhnd_get_pci_dev(dev)));
-}
-
-/*
- * siba_get_pci_subvendor()
- *
- * Referenced by:
- *   bwn_led_attach()
- *   bwn_nphy_op_prepare_structs()
- *   bwn_phy_g_prepare_hw()
- *   bwn_phy_hwpctl_init()
- *   bwn_phy_init_b5()
- *   bwn_phy_initn()
- *   bwn_phy_txpower_check()
- *   bwn_radio_init2055_post()
- *   bwn_sprom_bugfixes()
- *   bwn_wa_init()
- */
-static uint16_t
-bhnd_compat_get_pci_subvendor(device_t dev)
-{
-	return (pci_get_subvendor(bwn_bhnd_get_pci_dev(dev)));
-}
-
-/*
- * siba_get_pci_subdevice()
- *
- * Referenced by:
- *   bwn_nphy_workarounds_rev1_2()
- *   bwn_phy_g_prepare_hw()
- *   bwn_phy_hwpctl_init()
- *   bwn_phy_init_b5()
- *   bwn_phy_initn()
- *   bwn_phy_lp_bbinit_r01()
- *   bwn_phy_txpower_check()
- *   bwn_radio_init2055_post()
- *   bwn_sprom_bugfixes()
- *   bwn_wa_init()
- */
-static uint16_t
-bhnd_compat_get_pci_subdevice(device_t dev)
-{
-	return (pci_get_subdevice(bwn_bhnd_get_pci_dev(dev)));
-}
-
-/*
- * siba_get_pci_revid()
- *
- * Referenced by:
- *   bwn_phy_g_prepare_hw()
- *   bwn_phy_lp_bbinit_r2()
- *   bwn_sprom_bugfixes()
- *   bwn_wa_init()
- */
-static uint8_t
-bhnd_compat_get_pci_revid(device_t dev)
-{
-	return (pci_get_revid(bwn_bhnd_get_pci_dev(dev)));
-}
-
-/*
- * siba_get_chipid()
- *
- * Referenced by:
- *   bwn_attach()
- *   bwn_gpio_init()
- *   bwn_mac_switch_freq()
- *   bwn_phy_g_attach()
- *   bwn_phy_g_init_sub()
- *   bwn_phy_g_prepare_hw()
- *   bwn_phy_getinfo()
- *   bwn_phy_lp_calib()
- *   bwn_set_opmode()
- *   bwn_sprom_bugfixes()
- * ... and 9 others
- * 
- */
-static uint16_t
-bhnd_compat_get_chipid(device_t dev)
-{
-	return (bhnd_get_chipid(dev)->chip_id);
-}
-
-/*
- * siba_get_chiprev()
- *
- * Referenced by:
- *   bwn_phy_getinfo()
- *   bwn_phy_lp_bbinit_r2()
- *   bwn_phy_lp_tblinit_r2()
- *   bwn_set_opmode()
- */
-static uint16_t
-bhnd_compat_get_chiprev(device_t dev)
-{
-	return (bhnd_get_chipid(dev)->chip_rev);
-}
-
-/*
- * siba_get_chippkg()
- *
- * Referenced by:
- *   bwn_phy_g_init_sub()
- *   bwn_phy_lp_bbinit_r01()
- *   bwn_radio_2056_setup()
- */
-static uint8_t
-bhnd_compat_get_chippkg(device_t dev)
-{
-	return (bhnd_get_chipid(dev)->chip_pkg);
-}
-
-/*
- * siba_get_type()
- *
- * Referenced by:
- *   bwn_core_init()
- *   bwn_dma_attach()
- *   bwn_nphy_op_prepare_structs()
- *   bwn_sprom_bugfixes()
- */
-static enum siba_type
-bhnd_compat_get_type(device_t dev)
-{
-	device_t		bus, hostb;
-	bhnd_devclass_t		hostb_devclass;
-
-	bus = device_get_parent(dev);
-	hostb = bhnd_bus_find_hostb_device(bus);
-
-	if (hostb == NULL)
-		return (SIBA_TYPE_SSB);
-
-	hostb_devclass = bhnd_get_class(hostb);
-	switch (hostb_devclass) {
-	case BHND_DEVCLASS_PCCARD:
-		return (SIBA_TYPE_PCMCIA);
-	case BHND_DEVCLASS_PCI:
-	case BHND_DEVCLASS_PCIE:
-		return (SIBA_TYPE_PCI);
-	default:
-		panic("unsupported hostb devclass: %d\n", hostb_devclass);
-	}
-}
-
-/*
- * siba_get_cc_pmufreq()
- *
- * Referenced by:
- *   bwn_phy_lp_b2062_init()
- *   bwn_phy_lp_b2062_switch_channel()
- *   bwn_phy_lp_b2063_switch_channel()
- *   bwn_phy_lp_rxcal_r2()
- */
-static uint32_t
-bhnd_compat_get_cc_pmufreq(device_t dev)
-{
-	u_int	freq;
-	int	error;
-
-	if ((error = bhnd_get_clock_freq(dev, BHND_CLOCK_ALP, &freq)))
-		panic("failed to fetch clock frequency: %d", error);
-
-	/* TODO: bwn(4) immediately multiplies the result by 1000 (MHz -> Hz) */
-	return (freq / 1000);
-}
-
-/*
- * siba_get_cc_caps()
- *
- * Referenced by:
- *   bwn_phy_lp_b2062_init()
- */
-static uint32_t
-bhnd_compat_get_cc_caps(device_t dev)
-{
-	device_t		 chipc;
-	const struct chipc_caps	*ccaps;
-	uint32_t		 result;
-
-	/* Fetch our ChipCommon device */
-	chipc = bhnd_retain_provider(dev, BHND_SERVICE_CHIPC);
-	if (chipc == NULL)
-		panic("missing ChipCommon device");
-
-	/*
-	 * The ChipCommon capability flags are only used in one LP-PHY function,
-	 * to assert that a PMU is in fact available.
-	 *
-	 * We can support this by producing a value containing just that flag. 
-	 */
-	result = 0;
-	ccaps = BHND_CHIPC_GET_CAPS(chipc);
-	if (ccaps->pmu)
-		result |= SIBA_CC_CAPS_PMU;
-
-	bhnd_release_provider(dev, chipc, BHND_SERVICE_CHIPC);
-
-	return (result);
-}
-
-/*
- * siba_get_cc_powerdelay()
- *
- * Referenced by:
- *   bwn_chip_init()
- */
-static uint16_t
-bhnd_compat_get_cc_powerdelay(device_t dev)
-{
-	u_int	 delay;
-	int	 error;
-
-	if ((error = bhnd_get_clock_latency(dev, BHND_CLOCK_HT, &delay)))
-		panic("failed to fetch clock latency: %d", error);
-
-	if (delay > UINT16_MAX)
-		panic("%#x would overflow", delay);
-
-	return (delay);
-}
-
-/*
- * siba_get_pcicore_revid()
- *
- * Referenced by:
- *   bwn_core_init()
- */
-static uint8_t
-bhnd_compat_get_pcicore_revid(device_t dev)
-{
-	device_t	hostb;
-	uint8_t		nomatch_revid;
-
-	/* 
-	 * This is used by bwn(4) in only bwn_core_init(), where a revid <= 10
-	 * results in the BWN_HF_PCI_SLOWCLOCK_WORKAROUND workaround being
-	 * enabled.
-	 * 
-	 * The quirk should only be applied on siba(4) devices using a PCI
-	 * core; we handle around this by returning a bogus value >= 10 here.
-	 * 
-	 * TODO: bwn(4) should match this quirk on:
-	 *	- BHND_CHIPTYPE_SIBA
-	 *	- BHND_COREID_PCI
-	 *	- HWREV_LTE(10)
-	 */
-	nomatch_revid = 0xFF;
-
-	hostb = bhnd_bus_find_hostb_device(device_get_parent(dev));
-	if (hostb == NULL) {
-		/* Not a bridged device */
-		return (nomatch_revid);
-	}
-
-	if (bhnd_get_device(hostb) != BHND_COREID_PCI) {
-		/* Not a PCI core */
-		return (nomatch_revid);
-	}
-
-	/* This is a PCI core; we can return the real core revision */
-	return (bhnd_get_hwrev(hostb));
-}
-
-/*
- * siba_sprom_get_rev()
- *
- * Referenced by:
- *   bwn_nphy_op_prepare_structs()
- *   bwn_nphy_tx_power_ctl_setup()
- *   bwn_nphy_tx_power_fix()
- *   bwn_nphy_workarounds_rev7plus()
- */
-static uint8_t
-bhnd_compat_sprom_get_rev(device_t dev)
-{
-	return (bwn_bhnd_get_ctx(dev)->sromrev);
-}
-
-/*
- * siba_sprom_get_mac_80211bg()
- *
- * Referenced by:
- *   bwn_attach_post()
- */
-static uint8_t *
-bhnd_compat_sprom_get_mac_80211bg(device_t dev)
-{
-	/* 'MAC_80211BG' is il0macaddr or macaddr*/
-	return (bwn_bhnd_get_ctx(dev)->mac_80211bg);
-}
-
-/*
- * siba_sprom_get_mac_80211a()
- *
- * Referenced by:
- *   bwn_attach_post()
- */
-static uint8_t *
-bhnd_compat_sprom_get_mac_80211a(device_t dev)
-{
-	/* 'MAC_80211A' is et1macaddr */
-	return (bwn_bhnd_get_ctx(dev)->mac_80211a);
-}
-
-/*
- * siba_sprom_get_brev()
- *
- * Referenced by:
- *   bwn_radio_init2055_post()
- */
-static uint8_t
-bhnd_compat_sprom_get_brev(device_t dev)
-{
-	/* TODO: bwn(4) needs to switch to uint16_t */
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_BOARDREV);
-}
-
-/*
- * siba_sprom_get_ccode()
- *
- * Referenced by:
- *   bwn_phy_g_switch_chan()
- */
-static uint8_t
-bhnd_compat_sprom_get_ccode(device_t dev)
-{
-	/* This has been replaced with 'ccode' in later SPROM
-	 * revisions, but this API is only called on devices with
-	 * spromrev 1. */
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_CC);
-}
-
-/*
- * siba_sprom_get_ant_a()
- *
- * Referenced by:
- *   bwn_antenna_sanitize()
- */
-static uint8_t
-bhnd_compat_sprom_get_ant_a(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_AA5G);
-}
-
-/*
- * siba_sprom_get_ant_bg()
- *
- * Referenced by:
- *   bwn_antenna_sanitize()
- */
-static uint8_t
-bhnd_compat_sprom_get_ant_bg(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_AA2G);
-}
-
-/*
- * siba_sprom_get_pa0b0()
- *
- * Referenced by:
- *   bwn_phy_g_attach()
- */
-static uint16_t
-bhnd_compat_sprom_get_pa0b0(device_t dev)
-{
-	int16_t value;
-
-	BWN_BHND_NVRAM_FETCH_VAR(dev, int16, BHND_NVAR_PA0B0, &value);
-
-	/* TODO: bwn(4) immediately casts this back to int16_t */
-	return ((uint16_t)value);
-}
-
-/*
- * siba_sprom_get_pa0b1()
- *
- * Referenced by:
- *   bwn_phy_g_attach()
- */
-static uint16_t
-bhnd_compat_sprom_get_pa0b1(device_t dev)
-{
-	int16_t value;
-
-	BWN_BHND_NVRAM_FETCH_VAR(dev, int16, BHND_NVAR_PA0B1, &value);
-
-	/* TODO: bwn(4) immediately casts this back to int16_t */
-	return ((uint16_t)value);
-}
-
-/*
- * siba_sprom_get_pa0b2()
- *
- * Referenced by:
- *   bwn_phy_g_attach()
- */
-static uint16_t
-bhnd_compat_sprom_get_pa0b2(device_t dev)
-{
-	int16_t value;
-
-	BWN_BHND_NVRAM_FETCH_VAR(dev, int16, BHND_NVAR_PA0B2, &value);
-
-	/* TODO: bwn(4) immediately casts this back to int16_t */
-	return ((uint16_t)value);
-}
-
-/**
- * Fetch an led behavior (ledbhX) NVRAM variable value, for use by
- * siba_sprom_get_gpioX().
- * 
- * ('gpioX' are actually the ledbhX NVRAM variables).
- */
-static uint8_t
-bhnd_compat_sprom_get_ledbh(device_t dev, const char *name)
-{
-	uint8_t	value;
-	int	error;
-
-	error = bhnd_nvram_getvar_uint8(dev, name, &value);
-	if (error && error != ENOENT)
-		panic("NVRAM variable %s unreadable: %d", name, error);
-
-	/* For some variables (including ledbhX), a value with all bits set is
-	 * treated as uninitialized in the SPROM format; our SPROM parser
-	 * detects this case and returns ENOENT, but bwn(4) actually expects
-	 * to read the raw value 0xFF value. */
-	if (error == ENOENT)
-		value = 0xFF;
-
-	return (value);
-}
-
-/*
- * siba_sprom_get_gpio0()
- *
- * 'gpioX' are actually the led behavior (ledbh) NVRAM variables.
- *
- * Referenced by:
- *   bwn_led_attach()
- */
-static uint8_t
-bhnd_compat_sprom_get_gpio0(device_t dev)
-{
-	return (bhnd_compat_sprom_get_ledbh(dev, BHND_NVAR_LEDBH0));
-}
-
-/*
- * siba_sprom_get_gpio1()
- *
- * Referenced by:
- *   bwn_led_attach()
- */
-static uint8_t
-bhnd_compat_sprom_get_gpio1(device_t dev)
-{
-	return (bhnd_compat_sprom_get_ledbh(dev, BHND_NVAR_LEDBH1));
-}
-
-/*
- * siba_sprom_get_gpio2()
- *
- * Referenced by:
- *   bwn_led_attach()
- */
-static uint8_t
-bhnd_compat_sprom_get_gpio2(device_t dev)
-{
-	return (bhnd_compat_sprom_get_ledbh(dev, BHND_NVAR_LEDBH2));
-}
-
-/*
- * siba_sprom_get_gpio3()
- *
- * Referenced by:
- *   bwn_led_attach()
- */
-static uint8_t
-bhnd_compat_sprom_get_gpio3(device_t dev)
-{
-	return (bhnd_compat_sprom_get_ledbh(dev, BHND_NVAR_LEDBH3));
-}
-
-/*
- * siba_sprom_get_maxpwr_bg()
- *
- * Referenced by:
- *   bwn_phy_g_recalc_txpwr()
- */
-static uint16_t
-bhnd_compat_sprom_get_maxpwr_bg(device_t dev)
-{
-	return (bwn_bhnd_get_ctx(dev)->pa0maxpwr);
-}
-
-/*
- * siba_sprom_set_maxpwr_bg()
- *
- * Referenced by:
- *   bwn_phy_g_recalc_txpwr()
- */
-static void
-bhnd_compat_sprom_set_maxpwr_bg(device_t dev, uint16_t t)
-{
-	KASSERT(t <= UINT8_MAX, ("invalid maxpwr value %hu", t));
-	bwn_bhnd_get_ctx(dev)->pa0maxpwr = t;
-}
-
-/*
- * siba_sprom_get_rxpo2g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_rxpo2g(device_t dev)
-{
-	/* Should be signed, but bwn(4) expects an unsigned value */
-	BWN_BHND_NVRAM_RETURN_VAR(dev, int8, BHND_NVAR_RXPO2G);
-}
-
-/*
- * siba_sprom_get_rxpo5g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_rxpo5g(device_t dev)
-{
-	/* Should be signed, but bwn(4) expects an unsigned value */
-	BWN_BHND_NVRAM_RETURN_VAR(dev, int8, BHND_NVAR_RXPO5G);
-}
-
-/*
- * siba_sprom_get_tssi_bg()
- *
- * Referenced by:
- *   bwn_phy_g_attach()
- */
-static uint8_t
-bhnd_compat_sprom_get_tssi_bg(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_PA0ITSSIT);
-}
-
-/*
- * siba_sprom_get_tri2g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_tri2g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TRI2G);
-}
-
-/*
- * siba_sprom_get_tri5gl()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_tri5gl(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TRI5GL);
-}
-
-/*
- * siba_sprom_get_tri5g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_tri5g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TRI5G);
-}
-
-/*
- * siba_sprom_get_tri5gh()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_tri5gh(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TRI5GH);
-}
-
-/*
- * siba_sprom_get_rssisav2g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_rssisav2g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISAV2G);
-}
-
-/*
- * siba_sprom_get_rssismc2g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_rssismc2g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISMC2G);
-}
-
-/*
- * siba_sprom_get_rssismf2g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_rssismf2g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISMF2G);
-}
-
-/*
- * siba_sprom_get_bxa2g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_bxa2g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_BXA2G);
-}
-
-/*
- * siba_sprom_get_rssisav5g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_rssisav5g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISAV5G);
-}
-
-/*
- * siba_sprom_get_rssismc5g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_rssismc5g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISMC5G);
-}
-
-/*
- * siba_sprom_get_rssismf5g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_rssismf5g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISMF5G);
-}
-
-/*
- * siba_sprom_get_bxa5g()
- *
- * Referenced by:
- *   bwn_phy_lp_readsprom()
- */
-static uint8_t
-bhnd_compat_sprom_get_bxa5g(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_BXA5G);
-}
-
-/*
- * siba_sprom_get_cck2gpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static uint16_t
-bhnd_compat_sprom_get_cck2gpo(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint16, BHND_NVAR_CCK2GPO);
-}
-
-/*
- * siba_sprom_get_ofdm2gpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static uint32_t
-bhnd_compat_sprom_get_ofdm2gpo(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint32, BHND_NVAR_OFDM2GPO);
-}
-
-/*
- * siba_sprom_get_ofdm5glpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static uint32_t
-bhnd_compat_sprom_get_ofdm5glpo(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint32, BHND_NVAR_OFDM5GLPO);
-}
-
-/*
- * siba_sprom_get_ofdm5gpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static uint32_t
-bhnd_compat_sprom_get_ofdm5gpo(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint32, BHND_NVAR_OFDM5GPO);
-}
-
-/*
- * siba_sprom_get_ofdm5ghpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static uint32_t
-bhnd_compat_sprom_get_ofdm5ghpo(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint32, BHND_NVAR_OFDM5GHPO);
-}
-
-/*
- * siba_sprom_set_bf_lo()
- *
- * Referenced by:
- *   bwn_sprom_bugfixes()
- */
-static void
-bhnd_compat_sprom_set_bf_lo(device_t dev, uint16_t t)
-{
-	struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev);
-	ctx->boardflags &= ~0xFFFF;
-	ctx->boardflags |= t;
-}
-
-/*
- * siba_sprom_get_bf_lo()
- *
- * Referenced by:
- *   bwn_bt_enable()
- *   bwn_core_init()
- *   bwn_gpio_init()
- *   bwn_loopback_calcgain()
- *   bwn_phy_g_init_sub()
- *   bwn_phy_g_recalc_txpwr()
- *   bwn_phy_g_set_txpwr()
- *   bwn_phy_g_task_60s()
- *   bwn_rx_rssi_calc()
- *   bwn_sprom_bugfixes()
- * ... and 11 others
- * 
- */
-static uint16_t
-bhnd_compat_sprom_get_bf_lo(device_t dev)
-{
-	struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev);
-	return (ctx->boardflags & UINT16_MAX);
-}
-
-/*
- * siba_sprom_get_bf_hi()
- *
- * Referenced by:
- *   bwn_nphy_gain_ctl_workarounds_rev3()
- *   bwn_phy_lp_bbinit_r01()
- *   bwn_phy_lp_tblinit_txgain()
- */
-static uint16_t
-bhnd_compat_sprom_get_bf_hi(device_t dev)
-{
-	struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev);
-	return (ctx->boardflags >> 16);
-}
-
-/*
- * siba_sprom_get_bf2_lo()
- *
- * Referenced by:
- *   bwn_nphy_op_prepare_structs()
- *   bwn_nphy_workarounds_rev1_2()
- *   bwn_nphy_workarounds_rev3plus()
- *   bwn_phy_initn()
- *   bwn_radio_2056_setup()
- *   bwn_radio_init2055_post()
- */
-static uint16_t
-bhnd_compat_sprom_get_bf2_lo(device_t dev)
-{
-	uint32_t bf2;
-
-	BWN_BHND_NVRAM_FETCH_VAR(dev, uint32, BHND_NVAR_BOARDFLAGS2, &bf2);
-	return (bf2 & UINT16_MAX);
-}
-
-/*
- * siba_sprom_get_bf2_hi()
- *
- * Referenced by:
- *   bwn_nphy_workarounds_rev7plus()
- *   bwn_phy_initn()
- *   bwn_radio_2056_setup()
- */
-static uint16_t
-bhnd_compat_sprom_get_bf2_hi(device_t dev)
-{
-	uint32_t bf2;
-
-	BWN_BHND_NVRAM_FETCH_VAR(dev, uint32, BHND_NVAR_BOARDFLAGS2, &bf2);
-	return (bf2 >> 16);
-}
-
-/*
- * siba_sprom_get_fem_2ghz_tssipos()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_ctl_setup()
- */
-static uint8_t
-bhnd_compat_sprom_get_fem_2ghz_tssipos(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TSSIPOS2G);
-}
-
-/*
- * siba_sprom_get_fem_2ghz_extpa_gain()
- *
- * Referenced by:
- *   bwn_nphy_op_prepare_structs()
- */
-static uint8_t
-bhnd_compat_sprom_get_fem_2ghz_extpa_gain(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_EXTPAGAIN2G);
-}
-
-/*
- * siba_sprom_get_fem_2ghz_pdet_range()
- *
- * Referenced by:
- *   bwn_nphy_workarounds_rev3plus()
- */
-static uint8_t
-bhnd_compat_sprom_get_fem_2ghz_pdet_range(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_PDETRANGE2G);
-}
-
-/*
- * siba_sprom_get_fem_2ghz_tr_iso()
- *
- * Referenced by:
- *   bwn_nphy_get_gain_ctl_workaround_ent()
- */
-static uint8_t
-bhnd_compat_sprom_get_fem_2ghz_tr_iso(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TRISO2G);
-}
-
-/*
- * siba_sprom_get_fem_2ghz_antswlut()
- *
- * Referenced by:
- *   bwn_nphy_tables_init_rev3()
- *   bwn_nphy_tables_init_rev7_volatile()
- */
-static uint8_t
-bhnd_compat_sprom_get_fem_2ghz_antswlut(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_ANTSWCTL2G);
-}
-
-/*
- * siba_sprom_get_fem_5ghz_extpa_gain()
- *
- * Referenced by:
- *   bwn_nphy_get_tx_gain_table()
- *   bwn_nphy_op_prepare_structs()
- */
-static uint8_t
-bhnd_compat_sprom_get_fem_5ghz_extpa_gain(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_EXTPAGAIN5G);
-}
-
-/*
- * siba_sprom_get_fem_5ghz_pdet_range()
- *
- * Referenced by:
- *   bwn_nphy_workarounds_rev3plus()
- */
-static uint8_t
-bhnd_compat_sprom_get_fem_5ghz_pdet_range(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_PDETRANGE5G);
-}
-
-/*
- * siba_sprom_get_fem_5ghz_antswlut()
- *
- * Referenced by:
- *   bwn_nphy_tables_init_rev3()
- *   bwn_nphy_tables_init_rev7_volatile()
- */
-static uint8_t
-bhnd_compat_sprom_get_fem_5ghz_antswlut(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_ANTSWCTL5G);
-}
-
-/*
- * siba_sprom_get_txpid_2g_0()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_fix()
- */
-static uint8_t
-bhnd_compat_sprom_get_txpid_2g_0(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID2GA0);
-}
-
-/*
- * siba_sprom_get_txpid_2g_1()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_fix()
- */
-static uint8_t
-bhnd_compat_sprom_get_txpid_2g_1(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID2GA1);
-}
-
-/*
- * siba_sprom_get_txpid_5gl_0()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_fix()
- */
-static uint8_t
-bhnd_compat_sprom_get_txpid_5gl_0(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GLA0);
-}
-
-/*
- * siba_sprom_get_txpid_5gl_1()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_fix()
- */
-static uint8_t
-bhnd_compat_sprom_get_txpid_5gl_1(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GLA1);
-}
-
-/*
- * siba_sprom_get_txpid_5g_0()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_fix()
- */
-static uint8_t
-bhnd_compat_sprom_get_txpid_5g_0(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GA0);
-}
-
-/*
- * siba_sprom_get_txpid_5g_1()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_fix()
- */
-static uint8_t
-bhnd_compat_sprom_get_txpid_5g_1(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GA1);
-}
-
-/*
- * siba_sprom_get_txpid_5gh_0()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_fix()
- */
-static uint8_t
-bhnd_compat_sprom_get_txpid_5gh_0(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GHA0);
-}
-
-/*
- * siba_sprom_get_txpid_5gh_1()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_fix()
- */
-static uint8_t
-bhnd_compat_sprom_get_txpid_5gh_1(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GHA1);
-}
-
-/*
- * siba_sprom_get_stbcpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static uint16_t
-bhnd_compat_sprom_get_stbcpo(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint16, BHND_NVAR_STBCPO);
-}
-
-/*
- * siba_sprom_get_cddpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static uint16_t
-bhnd_compat_sprom_get_cddpo(device_t dev)
-{
-	BWN_BHND_NVRAM_RETURN_VAR(dev, uint16, BHND_NVAR_CDDPO);
-}
-
-/*
- * siba_powerup()
- *
- * Referenced by:
- *   bwn_attach_core()
- *   bwn_core_init()
- */
-static void
-bhnd_compat_powerup(device_t dev, int dynamic)
-{
-	struct bwn_bhnd_ctx	*ctx;
-	bhnd_clock		 clock;
-	int			 error;
-
-	ctx = bwn_bhnd_get_ctx(dev);
-
-	/* On PMU equipped devices, we do not need to issue a clock request
-	 * at powerup */
-	if (ctx->pmu_dev != NULL)
-		return;
-
-	/* Issue a PMU clock request */
-	if (dynamic)
-		clock = BHND_CLOCK_DYN;
-	else
-		clock = BHND_CLOCK_HT;
-
-	if ((error = bhnd_request_clock(dev, clock))) {
-		device_printf(dev, "%d clock request failed: %d\n",
-		    clock, error);
-	}
-
-}
-
-/*
- * siba_powerdown()
- *
- * Referenced by:
- *   bwn_attach_core()
- *   bwn_core_exit()
- *   bwn_core_init()
- */
-static int
-bhnd_compat_powerdown(device_t dev)
-{
-	int	error;
-
-	/* Suspend the core */
-	if ((error = bhnd_suspend_hw(dev, 0)))
-		return (error);
-
-	return (0);
-}
-
-/*
- * siba_read_2()
- *
- * Referenced by:
- *   bwn_chip_init()
- *   bwn_chiptest()
- *   bwn_dummy_transmission()
- *   bwn_gpio_init()
- *   bwn_phy_getinfo()
- *   bwn_pio_read_2()
- *   bwn_shm_read_2()
- *   bwn_shm_read_4()
- *   bwn_wme_init()
- *   bwn_wme_loadparams()
- * ... and 23 others
- * 
- */
-static uint16_t
-bhnd_compat_read_2(device_t dev, uint16_t offset)
-{
-	struct bwn_softc *sc = device_get_softc(dev);
-
-	BWN_ASSERT_VALID_REG(dev, offset);
-
-	return (bhnd_bus_read_2(sc->sc_mem_res, offset));
-}
-
-/*
- * siba_write_2()
- *
- * Referenced by:
- *   bwn_chip_init()
- *   bwn_chiptest()
- *   bwn_crypt_init()
- *   bwn_gpio_init()
- *   bwn_phy_getinfo()
- *   bwn_pio_tx_start()
- *   bwn_set_opmode()
- *   bwn_shm_write_2()
- *   bwn_shm_write_4()
- *   bwn_wme_init()
- * ... and 43 others
- * 
- */
-static void
-bhnd_compat_write_2(device_t dev, uint16_t offset, uint16_t value)
-{
-	struct bwn_softc *sc = device_get_softc(dev);
-
-	BWN_ASSERT_VALID_REG(dev, offset);
-
-	return (bhnd_bus_write_2(sc->sc_mem_res, offset, value));
-}
-
-/*
- * siba_read_4()
- *
- * Referenced by:
- *   bwn_attach_core()
- *   bwn_chip_init()
- *   bwn_chiptest()
- *   bwn_core_exit()
- *   bwn_core_init()
- *   bwn_core_start()
- *   bwn_pio_init()
- *   bwn_pio_tx_start()
- *   bwn_reset_core()
- *   bwn_shm_read_4()
- * ... and 42 others
- * 
- */
-static uint32_t
-bhnd_compat_read_4(device_t dev, uint16_t offset)
-{
-	struct bwn_softc	*sc = device_get_softc(dev);
-	uint16_t		 ioreg;
-	int			 error;
-
-	/* bwn(4) fetches IOCTL/IOST values directly from siba-specific target
-	 * state registers; we map these directly to bhnd_read_(ioctl|iost) */
-	switch (offset) {
-	case SB0_REG_ABS(SIBA_CFG0_TMSTATELOW):
-		if ((error = bhnd_read_ioctl(dev, &ioreg)))
-			panic("error reading IOCTL: %d\n", error);
-
-		return (((uint32_t)ioreg) << SIBA_TML_SICF_SHIFT);
-
-	case SB0_REG_ABS(SIBA_CFG0_TMSTATEHIGH):
-		if ((error = bhnd_read_iost(dev, &ioreg)))
-			panic("error reading IOST: %d\n", error);
-
-		return (((uint32_t)ioreg) << SIBA_TMH_SISF_SHIFT);
-	}
-
-	/* Otherwise, perform a standard bus read */
-	BWN_ASSERT_VALID_REG(dev, offset);
-	return (bhnd_bus_read_4(sc->sc_mem_res, offset));
-}
-
-/*
- * siba_write_4()
- *
- * Referenced by:
- *   bwn_chip_init()
- *   bwn_chiptest()
- *   bwn_core_exit()
- *   bwn_core_start()
- *   bwn_dma_mask()
- *   bwn_dma_rxdirectfifo()
- *   bwn_pio_init()
- *   bwn_reset_core()
- *   bwn_shm_ctlword()
- *   bwn_shm_write_4()
- * ... and 37 others
- * 
- */
-static void
-bhnd_compat_write_4(device_t dev, uint16_t offset, uint32_t value)
-{
-	struct bwn_softc	*sc = device_get_softc(dev);
-	uint16_t		 ioctl;
-	int			 error;
-
-	/* bwn(4) writes IOCTL values directly to siba-specific target state
-	 * registers; we map these directly to bhnd_write_ioctl() */
-	if (offset == SB0_REG_ABS(SIBA_CFG0_TMSTATELOW)) {
-		/* shift IOCTL flags back down to their original values */
-		if (value & ~SIBA_TML_SICF_MASK)
-			panic("%s: non-IOCTL flags provided", __FUNCTION__);
-
-		ioctl = (value & SIBA_TML_SICF_MASK) >> SIBA_TML_SICF_SHIFT;
-
-		if ((error = bhnd_write_ioctl(dev, ioctl, UINT16_MAX)))
-			panic("error writing IOCTL: %d\n", error);
-	} else {
-		/* Otherwise, perform a standard bus write */
-		BWN_ASSERT_VALID_REG(dev, offset);
-
-		bhnd_bus_write_4(sc->sc_mem_res, offset, value);
-	}
-
-	return;
-}
-
-/*
- * siba_dev_up()
- *
- * Referenced by:
- *   bwn_reset_core()
- */
-static void
-bhnd_compat_dev_up(device_t dev, uint32_t flags)
-{
-	uint16_t	ioctl;
-	int		error;
-
-	/* shift IOCTL flags back down to their original values */
-	if (flags & ~SIBA_TML_SICF_MASK)
-		panic("%s: non-IOCTL flags provided", __FUNCTION__);
-
-	ioctl = (flags & SIBA_TML_SICF_MASK) >> SIBA_TML_SICF_SHIFT;
-
-	/* Perform core reset; note that bwn(4) incorrectly assumes that both
-	 * RESET and post-RESET ioctl flags should be identical */
-	if ((error = bhnd_reset_hw(dev, ioctl, ioctl)))
-		panic("%s: core reset failed: %d", __FUNCTION__, error);
-}
-
-/*
- * siba_dev_down()
- *
- * Referenced by:
- *   bwn_attach_core()
- *   bwn_core_exit()
- */
-static void
-bhnd_compat_dev_down(device_t dev, uint32_t flags)
-{
-	uint16_t	ioctl;
-	int		error;
-
-	/* shift IOCTL flags back down to their original values */
-	if (flags & ~SIBA_TML_SICF_MASK)
-		panic("%s: non-IOCTL flags provided", __FUNCTION__);
-
-	ioctl = (flags & SIBA_TML_SICF_MASK) >> SIBA_TML_SICF_SHIFT;
-
-	/* Put core into RESET state */
-	if ((error = bhnd_suspend_hw(dev, ioctl)))
-		panic("%s: core suspend failed: %d", __FUNCTION__, error);
-}
-
-/*
- * siba_dev_isup()
- *
- * Referenced by:
- *   bwn_core_init()
- */
-static int
-bhnd_compat_dev_isup(device_t dev)
-{
-	return (!bhnd_is_hw_suspended(dev));
-}
-
-/*
- * siba_pcicore_intr()
- *
- * Referenced by:
- *   bwn_core_init()
- */
-static void
-bhnd_compat_pcicore_intr(device_t dev)
-{
-	/* This is handled by bhnd_bhndb on the first call to
-	 * bus_setup_intr() */
-}
-
-/*
- * siba_dma_translation()
- *
- * Referenced by:
- *   bwn_dma_32_setdesc()
- *   bwn_dma_64_setdesc()
- *   bwn_dma_setup()
- */
-static uint32_t
-bhnd_compat_dma_translation(device_t dev)
-{
-	struct bhnd_dma_translation	 dt;
-	struct bwn_softc		*sc;
-	struct bwn_mac			*mac;
-	u_int				 width;
-	int				 error;
-
-	sc = device_get_softc(dev);
-	mac = sc->sc_curmac;
-	KASSERT(mac != NULL, ("no MAC"));
-
-	/*
-	 * Use the DMA engine's maximum host address width to determine the
-	 * supported device address width.
-	 */
-	switch (mac->mac_method.dma.dmatype) {
-		case BWN_DMA_32BIT:
-		case BWN_DMA_30BIT:
-			/* The 32-bit engine is always capable of addressing
-			 * a full 32-bit device address */
-			width = BHND_DMA_ADDR_32BIT;
-			break;
-
-		case BWN_DMA_64BIT:
-			width = BHND_DMA_ADDR_64BIT;
-			break;
-
-		default:
-			panic("unknown dma type %d",
-			    mac->mac_method.dma.dmatype);
-	}
-
-
-	/* Fetch our DMA translation */
-	if ((error = bhnd_get_dma_translation(dev, width, 0, NULL, &dt)))
-		panic("error requesting DMA translation: %d\n", error);
-
-	/*
-	 * TODO: bwn(4) needs to switch to bhnd_get_dma_translation().
-	 *
-	 * Currently, bwn(4) incorrectly assumes that:
-	 *  - The 32-bit translation mask is always SIBA_DMA_TRANSLATION_MASK.
-	 *  - The 32-bit mask can simply be applied to the top 32-bits of a
-	 *    64-bit DMA address.
-	 *  - The 64-bit address translation is always derived by shifting the
-	 *    32-bit siba_dma_translation() left by 1 bit.
-	 *
-	 * In practice, these assumptions won't result in any bugs on known
-	 * PCI/PCIe Wi-Fi hardware:
-	 *  - The 32-bit mask _is_ always SIBA_DMA_TRANSLATION_MASK on
-	 *    the subset of devices supported by bwn(4).
-	 *  - The 64-bit mask used by bwn(4) is a superset of the real
-	 *    mask, and thus:
-	 *	- Our DMA tag will still have valid constraints.
-	 *	- Our address translation will not be corrupted by
-	 *	  applying the mask.
-	 *  - The mask falls within the top 16 address bits, and our
-	 *    supported 64-bit architectures are all still limited
-	 *    to 48-bit addresses anyway; we don't need to worry about
-	 *    addressing >= 48-bit host memory.
-	 *
-	 * However, we will need to resolve these issues in bwn(4) if DMA is to
-	 * work on new hardware (e.g. WiSoCs).
-	 */
-	switch (width) {
-	case BHND_DMA_ADDR_32BIT:
-		KASSERT((~dt.addr_mask & BHND_DMA_ADDR_BITMASK(32)) ==
-		    SIBA_DMA_TRANSLATION_MASK, ("unexpected DMA mask: %#jx",
-		    (uintmax_t)dt.addr_mask));
-
-		return (dt.base_addr);
-
-	case BHND_DMA_ADDR_64BIT:
-		/* bwn(4) will shift this left by 32+1 bits before applying it
-		 * to the top 32-bits of the DMA address */
-		KASSERT((~dt.addr_mask & BHND_DMA_ADDR_BITMASK(33)) == 0,
-		    ("DMA64 translation %#jx masks low 33-bits",
-		     (uintmax_t)dt.addr_mask));
-
-		return (dt.base_addr >> 33);
-
-	default:
-		panic("unsupported address width: %u", width);
-	}
-}
-
-/*
- * siba_read_multi_2()
- *
- * Referenced by:
- *   bwn_pio_rxeof()
- */
-static void
-bhnd_compat_read_multi_2(device_t dev, void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct bwn_softc *sc = device_get_softc(dev);
-
-	BWN_ASSERT_VALID_REG(dev, offset);
-	return (bhnd_bus_read_multi_2(sc->sc_mem_res, offset, buffer, count));
-}
-
-/*
- * siba_read_multi_4()
- *
- * Referenced by:
- *   bwn_pio_rxeof()
- */
-static void
-bhnd_compat_read_multi_4(device_t dev, void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct bwn_softc *sc = device_get_softc(dev);
-
-	BWN_ASSERT_VALID_REG(dev, offset);
-	return (bhnd_bus_read_multi_4(sc->sc_mem_res, offset, buffer, count));
-}
-
-/*
- * siba_write_multi_2()
- *
- * Referenced by:
- *   bwn_pio_write_multi_2()
- */
-static void
-bhnd_compat_write_multi_2(device_t dev, const void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct bwn_softc *sc = device_get_softc(dev);
-
-	BWN_ASSERT_VALID_REG(dev, offset);
-
-	/* XXX discarding const to maintain API compatibility with
-	 * siba_write_multi_2() */
-	bhnd_bus_write_multi_2(sc->sc_mem_res, offset,
-	    __DECONST(void *, buffer), count);
-}
-
-/*
- * siba_write_multi_4()
- *
- * Referenced by:
- *   bwn_pio_write_multi_4()
- */
-static void
-bhnd_compat_write_multi_4(device_t dev, const void *buffer, size_t count,
-    uint16_t offset)
-{
-	struct bwn_softc *sc = device_get_softc(dev);
-
-	BWN_ASSERT_VALID_REG(dev, offset);
-
-	/* XXX discarding const to maintain API compatibility with
-	 * siba_write_multi_4() */
-	bhnd_bus_write_multi_4(sc->sc_mem_res, offset,
-	    __DECONST(void *, buffer), count);
-}
-
-/*
- * siba_barrier()
- *
- * Referenced by:
- *   bwn_intr()
- *   bwn_intrtask()
- *   bwn_ram_write()
- */
-static void
-bhnd_compat_barrier(device_t dev, int flags)
-{
-	struct bwn_softc *sc = device_get_softc(dev);
-
-	/* XXX is siba_barrier()'s use of an offset and length of 0
-	 * correct? */
-	BWN_ASSERT_VALID_REG(dev, 0);
-	bhnd_bus_barrier(sc->sc_mem_res, 0, 0, flags);
-}
-
-/*
- * siba_cc_pmu_set_ldovolt()
- *
- * Referenced by:
- *   bwn_phy_lp_bbinit_r01()
- */
-static void
-bhnd_compat_cc_pmu_set_ldovolt(device_t dev, int id, uint32_t volt)
-{
-	struct bwn_bhnd_ctx	*ctx;
-	int			 error;
-
-	ctx = bwn_bhnd_get_ctx(dev);
-
-	/* Only ever used to set the PAREF LDO voltage */
-	if (id != SIBA_LDO_PAREF)
-		panic("invalid LDO id: %d", id);
-
-	/* Configuring regulator voltage requires a PMU */
-	if (ctx->pmu_dev == NULL)
-		panic("no PMU; cannot set LDO voltage");
-
-	error = bhnd_pmu_set_voltage_raw(ctx->pmu_dev, BHND_REGULATOR_PAREF_LDO,
-	    volt);
-	if (error)
-		panic("failed to set LDO voltage: %d", error);
-}
-
-/*
- * siba_cc_pmu_set_ldoparef()
- *
- * Referenced by:
- *   bwn_phy_lp_bbinit_r01()
- */
-static void
-bhnd_compat_cc_pmu_set_ldoparef(device_t dev, uint8_t on)
-{
-	struct bwn_bhnd_ctx	*ctx;
-	int			 error;
-
-	ctx = bwn_bhnd_get_ctx(dev);
-
-	/* Enabling/disabling regulators requires a PMU */
-	if (ctx->pmu_dev == NULL)
-		panic("no PMU; cannot set LDO voltage");
-
-	if (on) {
-		error = bhnd_pmu_enable_regulator(ctx->pmu_dev,
-		    BHND_REGULATOR_PAREF_LDO);
-	} else {
-		error = bhnd_pmu_disable_regulator(ctx->pmu_dev,
-		    BHND_REGULATOR_PAREF_LDO);
-	}
-
-	if (error) {
-		panic("failed to %s PAREF_LDO: %d", on ? "enable" : "disable",
-		    error);
-	}
-}
-
-/*
- * siba_gpio_set()
- *
- * Referenced by:
- *   bwn_chip_exit()
- *   bwn_chip_init()
- *   bwn_gpio_init()
- *   bwn_nphy_superswitch_init()
- */
-static void
-bhnd_compat_gpio_set(device_t dev, uint32_t value)
-{
-	struct bwn_bhnd_ctx	*ctx;
-	uint32_t		 flags[32];
-	int			 error;
-
-	ctx = bwn_bhnd_get_ctx(dev);
-
-	for (size_t i = 0; i < nitems(flags); i++) {
-		if (value & (1 << i)) {
-			/* Tristate pin */
-			flags[i] = (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
-		} else {
-			/* Leave unmodified */
-			flags[i] = 0;
-		}
-	}
-
-	error = GPIO_PIN_CONFIG_32(ctx->gpio_dev, 0, nitems(flags), flags);
-	if (error)
-		panic("error configuring pin flags: %d", error);
-}
-
-/*
- * siba_gpio_get()
- *
- * Referenced by:
- *   bwn_gpio_init()
- */
-static uint32_t
-bhnd_compat_gpio_get(device_t dev)
-{
-	struct bwn_bhnd_ctx	*ctx;
-	uint32_t		 ctrl;
-	int			 npin;
-	int			 error;
-
-	/*
-	 * We recreate the expected GPIOCTRL register value for bwn_gpio_init()
-	 * by querying pins individually for GPIO_PIN_TRISTATE.
-	 * 
-	 * Once we drop these compatibility shims, the GPIO_PIN_CONFIG_32 method
-	 * can be used to set pin configuration without bwn(4) externally
-	 * implementing RMW.
-	 */
-
-	/* Fetch the total pin count */
-	ctx = bwn_bhnd_get_ctx(dev);
-	if ((error = GPIO_PIN_MAX(ctx->gpio_dev, &npin)))
-		panic("failed to fetch max pin: %d", error);
-
-	/* Must be representable within a 32-bit GPIOCTRL register value */
-	KASSERT(npin <= 32, ("unsupported pin count: %u", npin));
-
-	ctrl = 0;
-	for (uint32_t pin = 0; pin < npin; pin++) {
-		uint32_t flags;
-
-		if ((error = GPIO_PIN_GETFLAGS(ctx->gpio_dev, pin, &flags)))
-			panic("error fetching pin%u flags: %d", pin, error);
-
-		if (flags & GPIO_PIN_TRISTATE)
-			ctrl |= (1 << pin);
-	}
-
-	return (ctrl);
-}
-
-/*
- * siba_fix_imcfglobug()
- *
- * Referenced by:
- *   bwn_core_init()
- */
-static void
-bhnd_compat_fix_imcfglobug(device_t dev)
-{
-	/* This is handled by siba_bhndb during attach/resume */
-}
-
-
-/* Core power NVRAM variables, indexed by D11 core unit number */
-static const struct bwn_power_vars {
-	const char *itt2ga;
-	const char *itt5ga;
-	const char *maxp2ga;
-	const char *pa2ga;
-	const char *pa5ga;
-} bwn_power_vars[BWN_BHND_NUM_CORE_PWR] = {
-#define	BHND_POWER_NVAR(_idx)					\
-	{ BHND_NVAR_ITT2GA ## _idx, BHND_NVAR_ITT5GA ## _idx,	\
-	  BHND_NVAR_MAXP2GA ## _idx, BHND_NVAR_PA2GA ## _idx,	\
-	  BHND_NVAR_PA5GA ## _idx }
-	BHND_POWER_NVAR(0),
-	BHND_POWER_NVAR(1),
-	BHND_POWER_NVAR(2),
-	BHND_POWER_NVAR(3)
-#undef BHND_POWER_NVAR
-};
-
-static int
-bwn_get_core_power_info_r11(device_t dev, const struct bwn_power_vars *v,
-    struct siba_sprom_core_pwr_info *c)
-{
-	int16_t	pa5ga[12];
-	int	error;
-
-	/* BHND_NVAR_PA2GA[core] */
-	error = bhnd_nvram_getvar_array(dev, v->pa2ga, c->pa_2g,
-	    sizeof(c->pa_2g), BHND_NVRAM_TYPE_INT16);
-	if (error)
-		return (error);
-
-	/* 
-	 * BHND_NVAR_PA5GA
-	 * 
-	 * The NVRAM variable is defined as a single pa5ga[12] array; we have
-	 * to split this into pa_5gl[4], pa_5g[4], and pa_5gh[4] for use
-	 * by bwn(4);
-	 */
-	_Static_assert(nitems(pa5ga) == nitems(c->pa_5g) + nitems(c->pa_5gh) +
-	    nitems(c->pa_5gl), "cannot split pa5ga into pa_5gl/pa_5g/pa_5gh");
-
-	error = bhnd_nvram_getvar_array(dev, v->pa5ga, pa5ga, sizeof(pa5ga),
-	    BHND_NVRAM_TYPE_INT16);
-	if (error)
-		return (error);
-
-	memcpy(c->pa_5gl, &pa5ga[0], sizeof(c->pa_5gl));
-	memcpy(c->pa_5g, &pa5ga[4], sizeof(c->pa_5g));
-	memcpy(c->pa_5gh, &pa5ga[8], sizeof(c->pa_5gh));
-	return (0);
-}
-
-static int
-bwn_get_core_power_info_r4_r10(device_t dev,
-    const struct bwn_power_vars *v, struct siba_sprom_core_pwr_info *c)
-{
-	int error;
-
-	/* BHND_NVAR_ITT2GA[core] */
-	if ((error = bhnd_nvram_getvar_uint8(dev, v->itt2ga, &c->itssi_2g)))
-		return (error);
-
-	/* BHND_NVAR_ITT5GA[core] */
-	if ((error = bhnd_nvram_getvar_uint8(dev, v->itt5ga, &c->itssi_5g)))
-		return (error);
-
-	return (0);
-}
-
-/*
- * siba_sprom_get_core_power_info()
- *
- * Referenced by:
- *   bwn_nphy_tx_power_ctl_setup()
- *   bwn_ppr_load_max_from_sprom()
- */
-static int
-bhnd_compat_sprom_get_core_power_info(device_t dev, int core,
-    struct siba_sprom_core_pwr_info *c)
-{
-	struct bwn_bhnd_ctx		*ctx;
-	const struct bwn_power_vars	*v;
-	int				 error;
-
-	if (core < 0 || core >= nitems(bwn_power_vars))
-		return (EINVAL);
-
-	ctx = bwn_bhnd_get_ctx(dev);
-	if (ctx->sromrev < 4)
-		return (ENXIO);
-
-	v = &bwn_power_vars[core];
-
-	/* Any power variables not found in NVRAM (or returning a
-	 * shorter array for a particular NVRAM revision) should be zero
-	 * initialized */
-	memset(c, 0x0, sizeof(*c));
-
-	/* Populate SPROM revision-independent values */
-	if ((error = bhnd_nvram_getvar_uint8(dev, v->maxp2ga, &c->maxpwr_2g)))
-		return (error);
-
-	/* Populate SPROM revision-specific values */
-	if (ctx->sromrev >= 4 && ctx->sromrev <= 10)
-		return (bwn_get_core_power_info_r4_r10(dev, v, c));
-	else
-		return (bwn_get_core_power_info_r11(dev, v, c));
-}
-
-/*
- * siba_sprom_get_mcs2gpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static int
-bhnd_compat_sprom_get_mcs2gpo(device_t dev, uint16_t *c)
-{
-	static const char *varnames[] = {
-		BHND_NVAR_MCS2GPO0,
-		BHND_NVAR_MCS2GPO1,
-		BHND_NVAR_MCS2GPO2,
-		BHND_NVAR_MCS2GPO3,
-		BHND_NVAR_MCS2GPO4,
-		BHND_NVAR_MCS2GPO5,
-		BHND_NVAR_MCS2GPO6,
-		BHND_NVAR_MCS2GPO7
-	};
-
-	for (size_t i = 0; i < nitems(varnames); i++) {
-		const char *name = varnames[i];
-		BWN_BHND_NVRAM_FETCH_VAR(dev, uint16, name, &c[i]);
-	}
-
-	return (0);
-}
-
-/*
- * siba_sprom_get_mcs5glpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static int
-bhnd_compat_sprom_get_mcs5glpo(device_t dev, uint16_t *c)
-{
-	static const char *varnames[] = {
-		BHND_NVAR_MCS5GLPO0,
-		BHND_NVAR_MCS5GLPO1,
-		BHND_NVAR_MCS5GLPO2,
-		BHND_NVAR_MCS5GLPO3,
-		BHND_NVAR_MCS5GLPO4,
-		BHND_NVAR_MCS5GLPO5,
-		BHND_NVAR_MCS5GLPO6,
-		BHND_NVAR_MCS5GLPO7
-	};
-
-	for (size_t i = 0; i < nitems(varnames); i++) {
-		const char *name = varnames[i];
-		BWN_BHND_NVRAM_FETCH_VAR(dev, uint16, name, &c[i]);
-	}
-
-	return (0);
-}
-
-/*
- * siba_sprom_get_mcs5gpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static int
-bhnd_compat_sprom_get_mcs5gpo(device_t dev, uint16_t *c)
-{
-	static const char *varnames[] = {
-		BHND_NVAR_MCS5GPO0,
-		BHND_NVAR_MCS5GPO1,
-		BHND_NVAR_MCS5GPO2,
-		BHND_NVAR_MCS5GPO3,
-		BHND_NVAR_MCS5GPO4,
-		BHND_NVAR_MCS5GPO5,
-		BHND_NVAR_MCS5GPO6,
-		BHND_NVAR_MCS5GPO7
-	};
-
-	for (size_t i = 0; i < nitems(varnames); i++) {
-		const char *name = varnames[i];
-		BWN_BHND_NVRAM_FETCH_VAR(dev, uint16, name, &c[i]);
-	}
-
-	return (0);
-}
-
-/*
- * siba_sprom_get_mcs5ghpo()
- *
- * Referenced by:
- *   bwn_ppr_load_max_from_sprom()
- */
-static int
-bhnd_compat_sprom_get_mcs5ghpo(device_t dev, uint16_t *c)
-{
-	static const char *varnames[] = {
-		BHND_NVAR_MCS5GHPO0,
-		BHND_NVAR_MCS5GHPO1,
-		BHND_NVAR_MCS5GHPO2,
-		BHND_NVAR_MCS5GHPO3,
-		BHND_NVAR_MCS5GHPO4,
-		BHND_NVAR_MCS5GHPO5,
-		BHND_NVAR_MCS5GHPO6,
-		BHND_NVAR_MCS5GHPO7
-	};
-
-	for (size_t i = 0; i < nitems(varnames); i++) {
-		const char *name = varnames[i];
-		BWN_BHND_NVRAM_FETCH_VAR(dev, uint16, name, &c[i]);
-	}
-
-	return (0);
-}
-
-/*
- * siba_pmu_spuravoid_pllupdate()
- *
- * Referenced by:
- *   bwn_nphy_pmu_spur_avoid()
- */
-static void
-bhnd_compat_pmu_spuravoid_pllupdate(device_t dev, int spur_avoid)
-{
-	struct bwn_bhnd_ctx	*ctx;
-	bhnd_pmu_spuravoid	 mode;
-	int			 error;
-
-	ctx = bwn_bhnd_get_ctx(dev);
-
-	if (ctx->pmu_dev == NULL)
-		panic("requested spuravoid on non-PMU device");
-
-	switch (spur_avoid) {
-	case 0:
-		mode = BHND_PMU_SPURAVOID_NONE;
-		break;
-	case 1:
-		mode = BHND_PMU_SPURAVOID_M1;
-		break;
-	default:
-		panic("unknown spur_avoid: %d", spur_avoid);
-	}
-
-	if ((error = bhnd_pmu_request_spuravoid(ctx->pmu_dev, mode)))
-		panic("spuravoid request failed: %d", error);
-}
-
-/*
- * siba_cc_set32()
- *
- * Referenced by:
- *   bwn_phy_initn()
- *   bwn_wireless_core_phy_pll_reset()
- */
-static void
-bhnd_compat_cc_set32(device_t dev, uint32_t reg, uint32_t val)
-{
-	struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev);
-	
-	/*
-	 * OR with the current value.
-	 *
-	 * This function is only ever used to write to either ChipCommon's
-	 * chipctrl register or chipctl_data register. Note that chipctl_data
-	 * is actually a PMU register; it is not actually mapped by ChipCommon
-	 * on Always-on-Bus (AOB) devices with a standalone PMU core.
-	 */
-	if (dev != ctx->chipc_dev)
-		panic("unsupported device: %s", device_get_nameunit(dev));
-
-	switch (reg) {
-	case SIBA_CC_CHIPCTL:
-		BHND_CHIPC_WRITE_CHIPCTRL(ctx->chipc_dev, val, val);
-		break;
-	case SIBA_CC_CHIPCTL_DATA:
-		bhnd_pmu_write_chipctrl(ctx->pmu_dev, ctx->pmu_cctl_addr, val,
-		    val);
-		break;
-	default:
-		panic("unsupported register: %#x", reg);
-	}
-}
-
-/*
- * siba_cc_mask32()
- *
- * Referenced by:
- *   bwn_wireless_core_phy_pll_reset()
- */
-static void
-bhnd_compat_cc_mask32(device_t dev, uint32_t reg, uint32_t mask)
-{
-	struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev);
-
-	/*
-	 * AND with the current value.
-	 *
-	 * This function is only ever used to write to ChipCommon's chipctl_data
-	 * register. Note that chipctl_data is actually a PMU register; it is
-	 * not actually mapped by ChipCommon on Always-on-Bus (AOB) devices with
-	 * a standalone PMU core.
-	 */
-	if (dev != ctx->chipc_dev)
-		panic("unsupported device: %s", device_get_nameunit(dev));
-
-	switch (reg) {
-	case SIBA_CC_CHIPCTL_DATA:
-		bhnd_pmu_write_chipctrl(ctx->pmu_dev, ctx->pmu_cctl_addr, 0,
-		    ~mask);
-		break;
-	default:
-		panic("unsupported register: %#x", reg);
-	}
-}
-
-/*
- * siba_cc_write32()
- *
- * Referenced by:
- *   bwn_wireless_core_phy_pll_reset()
- */
-static void
-bhnd_compat_cc_write32(device_t dev, uint32_t reg, uint32_t val)
-{
-	struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev);
-
-	/*
-	 * This function is only ever used to write to ChipCommon's chipctl_addr
-	 * register; setting chipctl_addr is handled atomically by
-	 * bhnd_pmu_write_chipctrl(), so we merely cache the intended address
-	 * for later use when chipctl_data is written.
-	 *
-	 * Also, note that chipctl_addr is actually a PMU register; it is
-	 * not actually mapped by ChipCommon on Always-on-Bus (AOB) devices with
-	 * a standalone PMU core.
-	 */
-	if (dev != ctx->chipc_dev)
-		panic("unsupported device: %s", device_get_nameunit(dev));
-
-	switch (reg) {
-	case SIBA_CC_CHIPCTL_ADDR:
-		ctx->pmu_cctl_addr = val;
-		break;
-	default:
-		panic("unsupported register: %#x", reg);
-	}
-}
-
-const struct bwn_bus_ops bwn_bhnd_bus_ops = {
-	.init				= bwn_bhnd_bus_ops_init,
-	.fini				= bwn_bhnd_bus_ops_fini,
-	.pci_find_cap			= bhnd_compat_pci_find_cap,
-	.pci_alloc_msi			= bhnd_compat_pci_alloc_msi,
-	.pci_release_msi		= bhnd_compat_pci_release_msi,
-	.pci_msi_count			= bhnd_compat_pci_msi_count,
-	.get_vendor			= bhnd_compat_get_vendor,
-	.get_device			= bhnd_compat_get_device,
-	.get_revid			= bhnd_compat_get_revid,
-	.get_pci_vendor			= bhnd_compat_get_pci_vendor,
-	.get_pci_device			= bhnd_compat_get_pci_device,
-	.get_pci_subvendor		= bhnd_compat_get_pci_subvendor,
-	.get_pci_subdevice		= bhnd_compat_get_pci_subdevice,
-	.get_pci_revid			= bhnd_compat_get_pci_revid,
-	.get_chipid			= bhnd_compat_get_chipid,
-	.get_chiprev			= bhnd_compat_get_chiprev,
-	.get_chippkg			= bhnd_compat_get_chippkg,
-	.get_type			= bhnd_compat_get_type,
-	.get_cc_pmufreq			= bhnd_compat_get_cc_pmufreq,
-	.get_cc_caps			= bhnd_compat_get_cc_caps,
-	.get_cc_powerdelay		= bhnd_compat_get_cc_powerdelay,
-	.get_pcicore_revid		= bhnd_compat_get_pcicore_revid,
-	.sprom_get_rev			= bhnd_compat_sprom_get_rev,
-	.sprom_get_mac_80211bg		= bhnd_compat_sprom_get_mac_80211bg,
-	.sprom_get_mac_80211a		= bhnd_compat_sprom_get_mac_80211a,
-	.sprom_get_brev			= bhnd_compat_sprom_get_brev,
-	.sprom_get_ccode		= bhnd_compat_sprom_get_ccode,
-	.sprom_get_ant_a		= bhnd_compat_sprom_get_ant_a,
-	.sprom_get_ant_bg		= bhnd_compat_sprom_get_ant_bg,
-	.sprom_get_pa0b0		= bhnd_compat_sprom_get_pa0b0,
-	.sprom_get_pa0b1		= bhnd_compat_sprom_get_pa0b1,
-	.sprom_get_pa0b2		= bhnd_compat_sprom_get_pa0b2,
-	.sprom_get_gpio0		= bhnd_compat_sprom_get_gpio0,
-	.sprom_get_gpio1		= bhnd_compat_sprom_get_gpio1,
-	.sprom_get_gpio2		= bhnd_compat_sprom_get_gpio2,
-	.sprom_get_gpio3		= bhnd_compat_sprom_get_gpio3,
-	.sprom_get_maxpwr_bg		= bhnd_compat_sprom_get_maxpwr_bg,
-	.sprom_set_maxpwr_bg		= bhnd_compat_sprom_set_maxpwr_bg,
-	.sprom_get_rxpo2g		= bhnd_compat_sprom_get_rxpo2g,
-	.sprom_get_rxpo5g		= bhnd_compat_sprom_get_rxpo5g,
-	.sprom_get_tssi_bg		= bhnd_compat_sprom_get_tssi_bg,
-	.sprom_get_tri2g		= bhnd_compat_sprom_get_tri2g,
-	.sprom_get_tri5gl		= bhnd_compat_sprom_get_tri5gl,
-	.sprom_get_tri5g		= bhnd_compat_sprom_get_tri5g,
-	.sprom_get_tri5gh		= bhnd_compat_sprom_get_tri5gh,
-	.sprom_get_rssisav2g		= bhnd_compat_sprom_get_rssisav2g,
-	.sprom_get_rssismc2g		= bhnd_compat_sprom_get_rssismc2g,
-	.sprom_get_rssismf2g		= bhnd_compat_sprom_get_rssismf2g,
-	.sprom_get_bxa2g		= bhnd_compat_sprom_get_bxa2g,
-	.sprom_get_rssisav5g		= bhnd_compat_sprom_get_rssisav5g,
-	.sprom_get_rssismc5g		= bhnd_compat_sprom_get_rssismc5g,
-	.sprom_get_rssismf5g		= bhnd_compat_sprom_get_rssismf5g,
-	.sprom_get_bxa5g		= bhnd_compat_sprom_get_bxa5g,
-	.sprom_get_cck2gpo		= bhnd_compat_sprom_get_cck2gpo,
-	.sprom_get_ofdm2gpo		= bhnd_compat_sprom_get_ofdm2gpo,
-	.sprom_get_ofdm5glpo		= bhnd_compat_sprom_get_ofdm5glpo,
-	.sprom_get_ofdm5gpo		= bhnd_compat_sprom_get_ofdm5gpo,
-	.sprom_get_ofdm5ghpo		= bhnd_compat_sprom_get_ofdm5ghpo,
-	.sprom_get_bf_lo		= bhnd_compat_sprom_get_bf_lo,
-	.sprom_set_bf_lo		= bhnd_compat_sprom_set_bf_lo,
-	.sprom_get_bf_hi		= bhnd_compat_sprom_get_bf_hi,
-	.sprom_get_bf2_lo		= bhnd_compat_sprom_get_bf2_lo,
-	.sprom_get_bf2_hi		= bhnd_compat_sprom_get_bf2_hi,
-	.sprom_get_fem_2ghz_tssipos	= bhnd_compat_sprom_get_fem_2ghz_tssipos,
-	.sprom_get_fem_2ghz_extpa_gain	= bhnd_compat_sprom_get_fem_2ghz_extpa_gain,
-	.sprom_get_fem_2ghz_pdet_range	= bhnd_compat_sprom_get_fem_2ghz_pdet_range,
-	.sprom_get_fem_2ghz_tr_iso	= bhnd_compat_sprom_get_fem_2ghz_tr_iso,
-	.sprom_get_fem_2ghz_antswlut	= bhnd_compat_sprom_get_fem_2ghz_antswlut,
-	.sprom_get_fem_5ghz_extpa_gain	= bhnd_compat_sprom_get_fem_5ghz_extpa_gain,
-	.sprom_get_fem_5ghz_pdet_range	= bhnd_compat_sprom_get_fem_5ghz_pdet_range,
-	.sprom_get_fem_5ghz_antswlut	= bhnd_compat_sprom_get_fem_5ghz_antswlut,
-	.sprom_get_txpid_2g_0		= bhnd_compat_sprom_get_txpid_2g_0,
-	.sprom_get_txpid_2g_1		= bhnd_compat_sprom_get_txpid_2g_1,
-	.sprom_get_txpid_5gl_0		= bhnd_compat_sprom_get_txpid_5gl_0,
-	.sprom_get_txpid_5gl_1		= bhnd_compat_sprom_get_txpid_5gl_1,
-	.sprom_get_txpid_5g_0		= bhnd_compat_sprom_get_txpid_5g_0,
-	.sprom_get_txpid_5g_1		= bhnd_compat_sprom_get_txpid_5g_1,
-	.sprom_get_txpid_5gh_0		= bhnd_compat_sprom_get_txpid_5gh_0,
-	.sprom_get_txpid_5gh_1		= bhnd_compat_sprom_get_txpid_5gh_1,
-	.sprom_get_stbcpo		= bhnd_compat_sprom_get_stbcpo,
-	.sprom_get_cddpo		= bhnd_compat_sprom_get_cddpo,
-	.powerup			= bhnd_compat_powerup,
-	.powerdown			= bhnd_compat_powerdown,
-	.read_2				= bhnd_compat_read_2,
-	.write_2			= bhnd_compat_write_2,
-	.read_4				= bhnd_compat_read_4,
-	.write_4			= bhnd_compat_write_4,
-	.dev_up				= bhnd_compat_dev_up,
-	.dev_down			= bhnd_compat_dev_down,
-	.dev_isup			= bhnd_compat_dev_isup,
-	.pcicore_intr			= bhnd_compat_pcicore_intr,
-	.dma_translation		= bhnd_compat_dma_translation,
-	.read_multi_2			= bhnd_compat_read_multi_2,
-	.read_multi_4			= bhnd_compat_read_multi_4,
-	.write_multi_2			= bhnd_compat_write_multi_2,
-	.write_multi_4			= bhnd_compat_write_multi_4,
-	.barrier			= bhnd_compat_barrier,
-	.cc_pmu_set_ldovolt		= bhnd_compat_cc_pmu_set_ldovolt,
-	.cc_pmu_set_ldoparef		= bhnd_compat_cc_pmu_set_ldoparef,
-	.gpio_set			= bhnd_compat_gpio_set,
-	.gpio_get			= bhnd_compat_gpio_get,
-	.fix_imcfglobug			= bhnd_compat_fix_imcfglobug,
-	.sprom_get_core_power_info	= bhnd_compat_sprom_get_core_power_info,
-	.sprom_get_mcs2gpo		= bhnd_compat_sprom_get_mcs2gpo,
-	.sprom_get_mcs5glpo		= bhnd_compat_sprom_get_mcs5glpo,
-	.sprom_get_mcs5gpo		= bhnd_compat_sprom_get_mcs5gpo,
-	.sprom_get_mcs5ghpo		= bhnd_compat_sprom_get_mcs5ghpo,
-	.pmu_spuravoid_pllupdate	= bhnd_compat_pmu_spuravoid_pllupdate,
-	.cc_set32			= bhnd_compat_cc_set32,
-	.cc_mask32			= bhnd_compat_cc_mask32,
-	.cc_write32			= bhnd_compat_cc_write32,
-};
diff --git a/sys/dev/bwn/if_bwn_siba_compat.h b/sys/dev/bwn/if_bwn_siba_compat.h
deleted file mode 100644
index 36bd9783e52d..000000000000
--- a/sys/dev/bwn/if_bwn_siba_compat.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
- *
- * Copyright (c) 2016 Landon J. Fuller <landonf@FreeBSD.org>.
- * Copyright (c) 2017 The FreeBSD Foundation
- * All rights reserved.
- *
- * Portions of this software were developed by Landon Fuller
- * under sponsorship from the FreeBSD Foundation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _IF_BWN_SIBA_COMPAT_H_
-#define _IF_BWN_SIBA_COMPAT_H_
-
-#define	BWN_USE_SIBA	0
-#include "if_bwn_siba.h"
-
-#include "if_bwnvar.h"
-
-#define	BWN_BHND_NUM_CORE_PWR	4
-
-/**
- * Compatiblity shim state.
- */
-struct bwn_bhnd_ctx {
-	device_t	chipc_dev;	/**< ChipCommon device */
-	device_t	gpio_dev;	/**< GPIO device */
-
-	device_t	pmu_dev;	/**< PMU device, or NULL if no PMU */
-	uint32_t	pmu_cctl_addr;	/**< chipctrl_addr target of
-					     reads/writes to/from the
-					     chipctrl_data register */
-
-	uint8_t		sromrev;	/**< SROM format revision */
-
-	/* NVRAM variables for which bwn(4) expects the bus to manage storage
-	 * for (and in some cases, allow writes). */	
-	uint8_t		mac_80211bg[6];	/**< D11 unit 0 */
-	uint8_t		mac_80211a[6];	/**< D11 unit 1 */
-
-	uint32_t	boardflags;	/**< boardflags (bwn-writable) */
-	uint8_t		pa0maxpwr;	/**< 2GHz max power (bwn-writable) */
-};
-
-/**
- * Return the bwn(4) device's bhnd compatiblity context.
- */
-static inline struct bwn_bhnd_ctx *
-bwn_bhnd_get_ctx(device_t dev)
-{
-	struct bwn_softc *sc = device_get_softc(dev);
-	return (sc->sc_bus_ctx);
-}
-
-/**
- * Fetch an NVRAM variable via bhnd_nvram_getvar_*().
- */
-#define	BWN_BHND_NVRAM_FETCH_VAR(_dev, _type, _name, _result)		\
-do {									\
-	int error;							\
-									\
-	error = bhnd_nvram_getvar_ ## _type(_dev, _name, _result);	\
-	if (error) {							\
-		panic("NVRAM variable %s unreadable: %d", _name,	\
-		    error);						\
-	}								\
-} while(0)
-
-/**
- * Fetch and return an NVRAM variable via bhnd_nvram_getvar_*().
- */
-#define	BWN_BHND_NVRAM_RETURN_VAR(_dev, _type, _name)			\
-do {									\
-	_type ## _t	value;						\
-	BWN_BHND_NVRAM_FETCH_VAR(_dev, _type, _name, &value);		\
-	return (value);							\
-} while(0)
-
-#endif /* _IF_BWN_SIBA_COMPAT_H_ */
diff --git a/sys/dev/bwn/if_bwn_util.c b/sys/dev/bwn/if_bwn_util.c
index c1799d09172a..41aa94f1aaec 100644
--- a/sys/dev/bwn/if_bwn_util.c
+++ b/sys/dev/bwn/if_bwn_util.c
@@ -72,12 +72,9 @@ __FBSDID("$FreeBSD$");
 #include <net80211/ieee80211_phy.h>
 #include <net80211/ieee80211_ratectl.h>
 
-#include <dev/bwn/if_bwn_siba.h>
-
 #include <dev/bwn/if_bwnreg.h>
 #include <dev/bwn/if_bwnvar.h>
 
-#include <dev/bwn/if_bwn_chipid.h>
 #include <dev/bwn/if_bwn_debug.h>
 #include <dev/bwn/if_bwn_misc.h>
 #include <dev/bwn/if_bwn_util.h>
diff --git a/sys/dev/bwn/if_bwnreg.h b/sys/dev/bwn/if_bwnreg.h
index 2437a68e0513..87bc4cb021c8 100644
--- a/sys/dev/bwn/if_bwnreg.h
+++ b/sys/dev/bwn/if_bwnreg.h
@@ -34,83 +34,22 @@
 #ifndef _IF_BWNREG_H
 #define	_IF_BWNREG_H
 
-#define	PCI_VENDOR_COMPAQ		0x0e11
-#define	PCI_VENDOR_DELL			0x1028
-#define	PCI_VENDOR_HP			0x103c
-#define	PCI_VENDOR_ASUSTEK		0x1043
-#define	PCI_VENDOR_MOTOROLA		0x1057
-#define	PCI_VENDOR_APPLE		0x106b
-#define	PCI_VENDOR_BROADCOM		0x14e4
-#define	PCI_VENDOR_LINKSYS		0x1737
-
-/* SPROM flags */
-#define	BWN_BFL_BTCOEXIST		0x0001  /* implements Bluetooth coexistance */
-#define	BWN_BFL_PACTRL			0x0002  /* GPIO 9 controlling the PA */
-#define	BWN_BFL_AIRLINEMODE		0x0004  /* implements GPIO 13 radio disable indication */
-#define	BWN_BFL_RSSI			0x0008  /* software calculates nrssi slope. */
-#define	BWN_BFL_ENETSPI			0x0010  /* has ephy roboswitch spi */
-#define	BWN_BFL_CRYSTAL_NOSLOW		0x0020  /* no slow clock available */
-#define	BWN_BFL_CCKHIPWR		0x0040  /* can do high power CCK transmission */
-#define	BWN_BFL_ENETADM			0x0080  /* has ADMtek switch */
-#define	BWN_BFL_ENETVLAN		0x0100  /* can do vlan */
-#define	BWN_BFL_AFTERBURNER		0x0200  /* supports Afterburner mode */
-#define	BWN_BFL_NOPCI			0x0400  /* leaves PCI floating */
-#define	BWN_BFL_FEM			0x0800  /* supports the Front End Module */
-#define	BWN_BFL_EXTLNA			0x1000  /* has an external LNA */
-#define	BWN_BFL_HGPA			0x2000  /* had high gain PA */
-#define	BWN_BFL_BTCMOD			0x4000  /* BFL_BTCOEXIST is given in alternate GPIOs */
-#define	BWN_BFL_ALTIQ			0x8000  /* alternate I/Q settings */
-
-/* SPROM boardflags_hi values */
-#define	BWN_BFH_NOPA			0x0001  /* has no PA */
-#define	BWN_BFH_RSSIINV			0x0002  /* RSSI uses positive slope (not TSSI) */
-#define	BWN_BFH_LDO_PAREF		0x0004  /* uses the PARef LDO */
-#define	BWN_BFH_3TSWITCH		0x0008  /* uses a triple throw switch shared
-						 * with bluetooth */
-#define	BWN_BFH_PHASESHIFT		0x0010  /* can support phase shifter */
-#define	BWN_BFH_BUCKBOOST		0x0020  /* has buck/booster */
-#define	BWN_BFH_FEM_BT			0x0040  /* has FEM and switch to share antenna
-						 * with bluetooth */
-#define	BWN_BFH_NOCBUCK			0x0080
-#define	BWN_BFH_PALDO			0x0200
-#define	BWN_BFH_EXTLNA_5GHZ		0x1000  /* has an external LNA (5GHz mode) */
-
-/* SPROM boardflags2_lo values */
-#define	BWN_BFL2_RXBB_INT_REG_DIS	0x0001  /* external RX BB regulator present */
-#define	BWN_BFL2_APLL_WAR		0x0002  /* alternative A-band PLL settings implemented */
-#define	BWN_BFL2_TXPWRCTRL_EN		0x0004  /* permits enabling TX Power Control */
-#define	BWN_BFL2_2X4_DIV		0x0008  /* 2x4 diversity switch */
-#define	BWN_BFL2_5G_PWRGAIN		0x0010  /* supports 5G band power gain */
-#define	BWN_BFL2_PCIEWAR_OVR		0x0020  /* overrides ASPM and Clkreq settings */
-#define	BWN_BFL2_CAESERS_BRD		0x0040  /* is Caesers board (unused) */
-#define	BWN_BFL2_BTC3WIRE		0x0080  /* used 3-wire bluetooth coexist */
-#define	BWN_BFL2_SKWRKFEM_BRD		0x0100  /* 4321mcm93 uses Skyworks FEM */
-#define	BWN_BFL2_SPUR_WAR		0x0200  /* has a workaround for clock-harmonic spurs */
-#define	BWN_BFL2_GPLL_WAR		0x0400  /* altenative G-band PLL settings implemented */
-#define	BWN_BFL2_SINGLEANT_CCK		0x1000
-#define	BWN_BFL2_2G_SPUR_WAR		0x2000
-
-/* SPROM boardflags2_hi values */
-#define	BWN_BFH2_GPLL_WAR2		0x0001
-#define	BWN_BFH2_IPALVLSHIFT_3P3	0x0002
-#define	BWN_BFH2_INTERNDET_TXIQCAL	0x0004
-#define	BWN_BFH2_XTALBUFOUTEN		0x0008
-
-/* SIBA control registers */
-#define	BWN_TGSLOW_PHYCLOCK_ENABLE	0x00040000
-#define	BWN_TGSLOW_PHYRESET		0x00080000
-#define	BWN_TGSLOW_MACPHYCLKEN		0x00100000      /* MAC PHY Clock Control Enable (rev >= 5) */
-#define	BWN_TGSLOW_PLLREFSEL		0x00200000      /* PLL Frequency Reference Select (rev >= 5) */
+/* D11-specific I/O control flags */
+#define	BWN_IOCTL_PHYCLOCK_ENABLE	0x0004
+#define	BWN_IOCTL_PHYRESET		0x0008
+#define	BWN_IOCTL_MACPHYCLKEN		0x0010	/* MAC PHY Clock Control Enable (rev >= 5) */
+#define	BWN_IOCTL_PLLREFSEL		0x0020	/* PLL Frequency Reference Select (rev >= 5) */
 /* PHY_BANDWIDTH: N-PHY only */
-#define	BWN_TGSLOW_PHY_BANDWIDTH	0x00C00000
-#define	BWN_TGSLOW_PHY_BANDWIDTH_10MHZ	0x00000000
-#define	BWN_TGSLOW_PHY_BANDWIDTH_20MHZ	0x00400000
-#define	BWN_TGSLOW_PHY_BANDWIDTH_40MHZ	0x00800000
-#define	BWN_TGSLOW_SUPPORT_G		0x20000000
+#define	BWN_IOCTL_PHY_BANDWIDTH		0x00C0
+#define	BWN_IOCTL_PHY_BANDWIDTH_10MHZ	0x0000
+#define	BWN_IOCTL_PHY_BANDWIDTH_20MHZ	0x0040
+#define	BWN_IOCTL_PHY_BANDWIDTH_40MHZ	0x0080
+#define	BWN_IOCTL_SUPPORT_G		0x2000
 
-#define	BWN_TGSHIGH_HAVE_2GHZ		0x00010000
-#define	BWN_TGSHIGH_HAVE_5GHZ		0x00020000
-#define	BWN_TGSHIGH_DUALPHY		0x00080000
+/* D11-specific I/O status flags */
+#define	BWN_IOST_HAVE_2GHZ		0x0001
+#define	BWN_IOST_HAVE_5GHZ		0x0002
+#define	BWN_IOST_DUALPHY		0x0008
 
 #define	BWN_PHYTYPE_A			0x00
 #define	BWN_PHYTYPE_B			0x01
@@ -433,6 +372,8 @@
 #define	BWN_DMA32_RXDPTR		0x00000fff
 #define	BWN_DMA32_RXSTATE		0x0000f000
 #define	BWN_DMA32_RXSTAT_DISABLED	0x00000000
+#define	BWN_DMA32_ADDREXT_MASK		0xC0000000
+#define	BWN_DMA32_ADDREXT_SHIFT		30
 #define	BWN_DMA64_TXCTL			0x00
 #define	BWN_DMA64_TXENABLE		0x00000001
 #define	BWN_DMA64_TXSUSPEND		0x00000002
@@ -461,6 +402,8 @@
 #define	BWN_DMA64_RXSTATDPTR		0x00001fff
 #define	BWN_DMA64_RXSTAT		0xf0000000
 #define	BWN_DMA64_RXSTAT_DISABLED	0x00000000
+#define	BWN_DMA64_ADDREXT_MASK		0xC000000000000000ULL
+#define	BWN_DMA64_ADDREXT_SHIFT		62
 #define	BWN_DMA_RINGMEMSIZE		PAGE_SIZE
 #define	BWN_DMA0_RX_FRAMEOFFSET_FW351	30
 #define	BWN_DMA0_RX_FRAMEOFFSET_FW598	38
@@ -724,6 +667,23 @@
 #define	BWN_TAB_NOISESCALE_SIZE		27
 
 /*
+ * SPROM rev 1 locale codes. Later SPROM revisions use a two-character
+ * country code.
+ */
+enum {
+	BWN_SPROM1_CC_WORLDWIDE	= 0,
+	BWN_SPROM1_CC_THAILAND	= 1,
+	BWN_SPROM1_CC_ISRAEL	= 2,
+	BWN_SPROM1_CC_JORDAN	= 3,
+	BWN_SPROM1_CC_CHINA	= 4,
+	BWN_SPROM1_CC_JP	= 5,
+	BWN_SPROM1_CC_USA	= 6,
+	BWN_SPROM1_CC_EUROPE	= 7,
+	BWN_SPROM1_CC_US_LOW	= 8,
+	BWN_SPROM1_CC_JP_HIGH	= 9,
+};
+
+/*
  * SPROM GPIO
  */
 #define	BWN_LED_ACT_LOW			0x80
@@ -741,7 +701,7 @@
 #define	BWN_LED_ACT_ASSOC		10
 #define	BWN_LED_ACT_NULL		11
 
-#define	BWN_VENDOR_LED_ACT_COMPAQ	\
+#define	BWN_VENDOR_LED_ACT_HP_COMPAQ	\
 	BWN_LED_ACT_RF_ENABLED,		\
 	BWN_LED_ACT_2GHZ,		\
 	BWN_LED_ACT_5GHZ,		\
diff --git a/sys/dev/bwn/if_bwnvar.h b/sys/dev/bwn/if_bwnvar.h
index 686b671df290..2d77f8c4db46 100644
--- a/sys/dev/bwn/if_bwnvar.h
+++ b/sys/dev/bwn/if_bwnvar.h
@@ -34,19 +34,13 @@
 #ifndef _IF_BWNVAR_H
 #define	_IF_BWNVAR_H
 
-#include "if_bwn_siba.h"
+#include <dev/bhnd/bhnd.h>
 
 struct bwn_softc;
 struct bwn_mac;
 
-extern driver_t bwn_driver;
-
-int	bwn_attach(device_t dev);
-int	bwn_detach(device_t dev);
-
 #define	N(a)			(sizeof(a) / sizeof(a[0]))
 #define	BWN_ALIGN			0x1000
-#define	BWN_BUS_SPACE_MAXADDR_30BIT	0x3fffffff
 #define	BWN_RETRY_SHORT			7
 #define	BWN_RETRY_LONG			4
 #define	BWN_STAID_MAX			64
@@ -73,10 +67,12 @@ int	bwn_detach(device_t dev);
 	((uint16_t)((((uint16_t)tq->tq_index + 1) << 12) | tp->tp_index))
 #define	BWN_DMA_COOKIE(dr, slot)					\
 	((uint16_t)(((uint16_t)dr->dr_index + 1) << 12) | (uint16_t)slot)
-#define	BWN_READ_2(mac, o)		(siba_read_2(mac->mac_sc->sc_dev, o))
-#define	BWN_READ_4(mac, o)		(siba_read_4(mac->mac_sc->sc_dev, o))
+#define	BWN_READ_2(mac, o)						\
+	(bus_read_2((mac)->mac_sc->sc_mem_res, (o)))
+#define	BWN_READ_4(mac, o)						\
+	(bus_read_4((mac)->mac_sc->sc_mem_res, (o)))
 #define	BWN_WRITE_2(mac, o, v)						\
-	(siba_write_2(mac->mac_sc->sc_dev, o, v))
+	(bus_write_2((mac)->mac_sc->sc_mem_res, (o), (v)))
 #define	BWN_WRITE_2_F(mac, o, v) do { \
 	(BWN_WRITE_2(mac, o, v)); \
 	BWN_READ_2(mac, o); \
@@ -84,13 +80,13 @@ int	bwn_detach(device_t dev);
 #define	BWN_WRITE_SETMASK2(mac, offset, mask, set)			\
 	BWN_WRITE_2(mac, offset, (BWN_READ_2(mac, offset) & mask) | set)
 #define	BWN_WRITE_4(mac, o, v)						\
-	(siba_write_4(mac->mac_sc->sc_dev, o, v))
+	(bus_write_4((mac)->mac_sc->sc_mem_res, (o), (v)))
 #define	BWN_WRITE_SETMASK4(mac, offset, mask, set)			\
 	BWN_WRITE_4(mac, offset, (BWN_READ_4(mac, offset) & mask) | set)
 #define	BWN_PIO_TXQOFFSET(mac)						\
-	((siba_get_revid(mac->mac_sc->sc_dev) >= 11) ? 0x18 : 0)
+	((bhnd_get_hwrev(mac->mac_sc->sc_dev) >= 11) ? 0x18 : 0)
 #define	BWN_PIO_RXQOFFSET(mac)						\
-	((siba_get_revid(mac->mac_sc->sc_dev) >= 11) ? 0x38 : 8)
+	((bhnd_get_hwrev(mac->mac_sc->sc_dev) >= 11) ? 0x38 : 8)
 #define	BWN_SEC_NEWAPI(mac)		(mac->mac_fw.rev >= 351)
 #define	BWN_SEC_KEY2FW(mac, idx)					\
 	(BWN_SEC_NEWAPI(mac) ? idx : ((idx >= 4) ? idx - 4 : idx))
@@ -144,7 +140,6 @@ int	bwn_detach(device_t dev);
 #define BWN_LO_CALIB_EXPIRE		(1000 * (30 - 2))
 #define BWN_LO_PWRVEC_EXPIRE		(1000 * (30 - 2))
 #define BWN_LO_TXCTL_EXPIRE		(1000 * (180 - 4))
-#define	BWN_DMA_BIT_MASK(n)		(((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
 #define BWN_LPD(L, P, D)		(((L) << 2) | ((P) << 1) | ((D) << 0))
 #define BWN_BITREV4(tmp)		(BWN_BITREV8(tmp) >> 4)
 #define	BWN_BITREV8(byte)		(bwn_bitrev_table[byte])
@@ -159,7 +154,8 @@ int	bwn_detach(device_t dev);
 	(rate == BWN_CCK_RATE_1MB || rate == BWN_CCK_RATE_2MB ||	\
 	 rate == BWN_CCK_RATE_5MB || rate == BWN_CCK_RATE_11MB)
 #define	BWN_ISOFDMRATE(rate)		(!BWN_ISCCKRATE(rate))
-#define	BWN_BARRIER(mac, flags)		siba_barrier(mac->mac_sc->sc_dev, flags)
+#define	BWN_BARRIER(mac, offset, length, flags)			\
+	bus_barrier((mac)->mac_sc->sc_mem_res, (offset), (length), (flags))
 #define	BWN_DMA_READ(dr, offset)				\
 	(BWN_READ_4(dr->dr_mac, dr->dr_base + offset))
 #define	BWN_DMA_WRITE(dr, offset, value)			\
@@ -349,6 +345,7 @@ struct bwn_phy_g {
 	uint16_t			pg_radioctx_overval;
 	uint16_t			pg_minlowsig[2];
 	uint16_t			pg_minlowsigpos[2];
+	uint16_t			pg_pa0maxpwr;
 	int8_t				*pg_tssi2dbm;
 	int				pg_idletssi;
 	int				pg_curtssi;
@@ -606,10 +603,6 @@ struct bwn_noise {
 	int8_t				noi_samples[8][4];
 };
 
-#define	BWN_DMA_30BIT			30
-#define	BWN_DMA_32BIT			32
-#define	BWN_DMA_64BIT			64
-
 struct bwn_dmadesc_meta {
 	bus_dmamap_t			mt_dmap;
 	bus_addr_t			mt_paddr;
@@ -701,10 +694,11 @@ struct bwn_dma_ring {
 };
 
 struct bwn_dma {
-	int				dmatype;
 	bus_dma_tag_t			parent_dtag;
 	bus_dma_tag_t			rxbuf_dtag;
 	bus_dma_tag_t			txbuf_dtag;
+	struct bhnd_dma_translation	translation;
+	u_int				addrext_shift;
 
 	struct bwn_dma_ring		*wme[5];
 	struct bwn_dma_ring		*mcast;
@@ -948,11 +942,9 @@ struct bwn_mac {
 #define	BWN_MAC_FLAG_WME		(1 << 4)
 #define	BWN_MAC_FLAG_HWCRYPTO		(1 << 5)
 
-	struct resource_spec		*mac_intr_spec;
-#define	BWN_MSI_MESSAGES		1
-	struct resource			*mac_res_irq[BWN_MSI_MESSAGES];
-	void				*mac_intrhand[BWN_MSI_MESSAGES];
-	int				mac_msi;
+	struct resource			*mac_res_irq;
+	int				 mac_rid_irq;
+	void				*mac_intrhand;
 
 	struct bwn_noise		mac_noise;
 	struct bwn_phy			mac_phy;
@@ -964,6 +956,7 @@ struct bwn_mac {
 
 	struct bwn_fw			mac_fw;
 
+	int				mac_dmatype;
 	union {
 		struct bwn_dma		dma;
 		struct bwn_pio		pio;
@@ -1009,14 +1002,31 @@ struct bwn_vap {
 #define	BWN_VAP(vap)			((struct bwn_vap *)(vap))
 #define	BWN_VAP_CONST(vap)		((const struct mwl_vap *)(vap))
 
+enum bwn_quirk {
+	/**
+	 * The ucode PCI slowclock workaround is required on this device.
+	 * @see BWN_HF_PCI_SLOWCLOCK_WORKAROUND.
+	 */
+	BWN_QUIRK_UCODE_SLOWCLOCK_WAR	= (1<<0),
+
+	/**
+	 * DMA is unsupported on this device; PIO should be used instead.
+	 */
+	BWN_QUIRK_NODMA			= (1<<1),
+};
+
 struct bwn_softc {
 	device_t			sc_dev;
-	const struct bwn_bus_ops	*sc_bus_ops;
-#if !BWN_USE_SIBA
-	void				*sc_bus_ctx;
-	struct bhnd_resource		*sc_mem_res;
-	int				 sc_mem_rid;
-#endif /* !BWN_USE_SIBA */
+	struct bhnd_board_info		sc_board_info;
+	struct bhnd_chipid		sc_cid;
+	uint32_t			sc_quirks;	/**< @see bwn_quirk */
+	struct resource			*sc_mem_res;
+	int				sc_mem_rid;
+
+	device_t			sc_chipc;	/**< ChipCommon device */
+	device_t			sc_gpio;	/**< GPIO device */
+	device_t			sc_pmu;		/**< PMU device, or NULL if unsupported */
+
 	struct mtx			sc_mtx;
 	struct ieee80211com		sc_ic;
 	struct mbufq			sc_snd;
@@ -1059,6 +1069,9 @@ struct bwn_softc {
 	int				sc_led_idle;
 	int				sc_led_blink;
 
+	uint8_t				sc_ant2g;	/**< available 2GHz antennas */
+	uint8_t				sc_ant5g;	/**< available 5GHz antennas */
+
 	struct bwn_tx_radiotap_header	sc_tx_th;
 	struct bwn_rx_radiotap_header	sc_rx_th;
 };