diff options
| author | Emmanuel Vadot <manu@FreeBSD.org> | 2023-12-25 19:27:20 +0000 |
|---|---|---|
| committer | Emmanuel Vadot <manu@FreeBSD.org> | 2024-01-10 18:20:22 +0000 |
| commit | 77f222415832c58c2e307f74f1200941efe868d9 (patch) | |
| tree | 041ceba696f9b3943e448e3c9c505e88154f0cfb /sys/dev/clk/rockchip | |
| parent | e37e8677fe55ddd0685c764e17ac58707787758a (diff) | |
Diffstat (limited to 'sys/dev/clk/rockchip')
21 files changed, 9084 insertions, 0 deletions
diff --git a/sys/dev/clk/rockchip/rk3288_cru.c b/sys/dev/clk/rockchip/rk3288_cru.c new file mode 100644 index 000000000000..354a293ff7f2 --- /dev/null +++ b/sys/dev/clk/rockchip/rk3288_cru.c @@ -0,0 +1,919 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <machine/bus.h> + +#include <dev/fdt/simplebus.h> + +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> + +#include <dev/extres/clk/clk.h> +#include <dev/extres/clk/clk_div.h> +#include <dev/extres/clk/clk_fixed.h> +#include <dev/extres/clk/clk_mux.h> + +#include <dev/clk/rockchip/rk_cru.h> + +#include <dt-bindings/clock/rk3288-cru.h> + +#define CRU_SOFTRST_SIZE 12 + +#define CRU_APLL_CON(x) (0x000 + (x) * 0x4) +#define CRU_DPLL_CON(x) (0x010 + (x) * 0x4) +#define CRU_CPLL_CON(x) (0x020 + (x) * 0x4) +#define CRU_GPLL_CON(x) (0x030 + (x) * 0x4) +#define CRU_NPLL_CON(x) (0x040 + (x) * 0x4) +#define CRU_MODE_CON 0x050 +#define CRU_CLKSEL_CON(x) (0x060 + (x) * 0x4) +#define CRU_CLKGATE_CON(x) (0x160 + (x) * 0x4) +#define CRU_GLB_SRST_FST_VALUE 0x1b0 +#define CRU_GLB_SRST_SND_VALUE 0x1b4 +#define CRU_SOFTRST_CON(x) (0x1b8 + (x) * 0x4) +#define CRU_MISC_CON 0x1e8 +#define CRU_GLB_CNT_TH 0x1ec +#define CRU_GLB_RST_CON 0x1f0 +#define CRU_GLB_RST_ST 0x1f8 +#define CRU_SDMMC_CON0 0x200 +#define CRU_SDMMC_CON1 0x204 +#define CRU_SDIO0_CON0 0x208 +#define CRU_SDIO0_CON1 0x20c +#define CRU_SDIO1_CON0 0x210 +#define CRU_SDIO1_CON1 0x214 +#define CRU_EMMC_CON0 0x218 +#define CRU_EMMC_CON1 0x21c + +/* GATES */ +#define GATE(_idx, _clkname, _pname, _o, _s) \ +{ \ + .id = _idx, \ + .name = _clkname, \ + .parent_name = _pname, \ + .offset = CRU_CLKGATE_CON(_o), \ + .shift = _s, \ +} + +static struct rk_cru_gate rk3288_gates[] = { + /* CRU_CLKGATE_CON0 */ + GATE(0, "sclk_acc_efuse", "xin24m", 0, 12), + GATE(0, "cpll_aclk_cpu", "cpll", 0, 11), + GATE(0, "gpll_aclk_cpu", "gpll", 0, 10), + GATE(0, "gpll_ddr", "gpll", 0, 9), + GATE(0, "dpll_ddr", "dpll", 0, 8), + GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", 0, 7), + GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_s", 0, 5), + GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_s", 0, 4), + GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0, 3), + GATE(0, "gpll_core", "gpll", 0, 2), + GATE(0, "apll_core", "apll", 0, 1), + + + /* CRU_CLKGATE_CON1 */ + GATE(0, "uart3_frac", "uart3_frac_s", 1, 15), + GATE(0, "uart3_src", "uart3_src_s", 1, 14), + GATE(0, "uart2_frac", "uart2_frac_s", 1, 13), + GATE(0, "uart2_src", "uart2_src_s", 1, 12), + GATE(0, "uart1_frac", "uart1_frac_s", 1, 11), + GATE(0, "uart1_src", "uart1_src_s", 1, 10), + GATE(0, "uart0_frac", "uart0_frac_s", 1, 9), + GATE(0, "uart0_src", "uart0_src_s", 1, 8), + GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 1, 5), + GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 1, 4), + GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 1, 3), + GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 1, 2), + GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 1, 1), + GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 1, 0), + + /* CRU_CLKGATE_CON2 */ + GATE(0, "uart4_frac", "uart4_frac_s", 2, 13), + GATE(0, "uart4_src", "uart4_src_s", 2, 12), + GATE(SCLK_SPI2, "sclk_spi2", "sclk_spi2_s", 2, 11), + GATE(SCLK_SPI1, "sclk_spi1", "sclk_spi1_s", 2, 10), + GATE(SCLK_SPI0, "sclk_spi0", "sclk_spi0_s", 2, 9), + GATE(SCLK_SARADC, "sclk_saradc", "sclk_saradc_s", 2, 8), + GATE(SCLK_TSADC, "sclk_tsadc", "sclk_tsadc_s", 2, 7), + GATE(0, "hsadc_src", "hsadc_src_s", 2, 6), + GATE(0, "mac_pll_src", "mac_pll_src_s", 2, 5), + GATE(PCLK_PERI, "pclk_peri", "pclk_peri_s", 2, 3), + GATE(HCLK_PERI, "hclk_peri", "hclk_peri_s", 2, 2), + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 2, 1), + GATE(0, "aclk_peri_src", "aclk_peri_src_s", 2, 0), + + /* CRU_CLKGATE_CON3 */ + GATE(SCLK_ISP_JPE, "sclk_isp_jpe", "sclk_isp_jpe_s", 3, 15), + GATE(SCLK_ISP, "sclk_isp", "sclk_isp_s", 3, 14), + GATE(SCLK_EDP, "sclk_edp", "sclk_edp_s", 3, 13), + GATE(SCLK_EDP_24M, "sclk_edp_24m", "sclk_edp_24m_s", 3, 12), + GATE(0, "aclk_vdpu", "aclk_vdpu_s", 3, 11), + GATE(0, "hclk_vcodec_pre", "hclk_vcodec_pre_s", 3, 10), + GATE(0, "aclk_vepu", "aclk_vepu_s", 3, 9), + GATE(0, "vip_src", "vip_src_s", 3, 7), +/* 6 - Not in TRM, sclk_hsicphy480m in Linux */ + GATE(0, "aclk_rga_pre", "aclk_rga_pre_s", 3, 5), + GATE(SCLK_RGA, "sclk_rga", "sclk_rga_s", 3, 4), + GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop1_s", 3, 3), + GATE(0, "aclk_vio1", "aclk_vio1_s", 3, 2), + GATE(DCLK_VOP0, "dclk_vop0", "dclk_vop0_s", 3, 1), + GATE(0, "aclk_vio0", "aclk_vio0_s", 3, 0), + + /* CRU_CLKGATE_CON4 */ +/* 15 - Test clock generator */ + GATE(0, "jtag", "ext_jtag", 4, 14), + GATE(0, "sclk_ddrphy1", "ddrphy", 4, 13), + GATE(0, "sclk_ddrphy0", "ddrphy", 4, 12), + GATE(0, "sclk_tspout", "sclk_tspout_s", 4, 11), + GATE(0, "sclk_tsp", "sclk_tsp_s", 4, 10), + GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", 4, 9), + GATE(0, "spdif_8ch_frac", "spdif_8ch_frac_s", 4, 8), + GATE(0, "spdif_8ch_pre", "spdif_8ch_pre_s", 4, 7), + GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", 4, 6), + GATE(0, "spdif_frac", "spdif_frac_s", 4, 5), + GATE(0, "spdif_pre", "spdif_pre_s", 4, 4), + GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", 4, 3), + GATE(0, "i2s_frac", "i2s_frac_s", 4, 2), + GATE(0, "i2s_src", "i2s_src_s", 4, 1), + GATE(SCLK_I2S0_OUT, "i2s0_clkout", "i2s0_clkout_s", 4, 1), + + /* CRU_CLKGATE_CON5 */ + GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 5, 15), + GATE(SCLK_USBPHY480M_SRC, "usbphy480m_src", "usbphy480m_src_s", 5, 14), + GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 5, 13), + GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 5, 12), + GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 5, 11), + GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 5, 10), + GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 5, 9), + GATE(0, "pclk_pd_pmu", "pclk_pd_pmu_s", 5, 8), + GATE(SCLK_GPU, "sclk_gpu", "sclk_gpu_s", 5, 7), + GATE(SCLK_NANDC1, "sclk_nandc1", "sclk_nandc1_s", 5, 6), + GATE(SCLK_NANDC0, "sclk_nandc0", "sclk_nandc0_s", 5, 5), + GATE(SCLK_CRYPTO, "crypto", "crypto_s", 5, 4), + GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 5, 3), + GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 5, 2), + GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 5, 1), + GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 5, 0), + + + /* CRU_CLKGATE_CON6 */ + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 6, 15), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 6, 14), + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 6, 13), + GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 6, 12), + GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 6, 11), + GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 6, 9), + GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 6, 8), + GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 6, 7), + GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 6, 6), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 6, 5), + GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 6, 4), + GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 6, 3), + GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 6, 2), + GATE(0, "pclk_peri_matrix", "pclk_peri", 6, 1), + GATE(0, "hclk_peri_matrix", "hclk_peri", 6, 0), + + + /* CRU_CLKGATE_CON7 */ + GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 7, 15), + GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 7, 14), + GATE(0, "hclk_mem", "hclk_peri", 7, 13), + GATE(0, "hclk_emem", "hclk_peri", 7, 12), + GATE(0, "aclk_peri_niu", "aclk_peri", 7, 11), + GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 7, 10), + GATE(0, "hclk_usb_peri", "hclk_peri", 7, 9), +/* 8 - Not in TRM - hclk_hsic in Linux */ + GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", 7, 7), + GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 7, 6), + GATE(0, "pmu_hclk_otg0", "hclk_peri", 7, 5), + GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", 7, 4), + GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 7, 3), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 7, 2), + GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 7, 1), + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 7, 0), + + /* CRU_CLKGATE_CON8 */ + GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", 8, 12), +/* 11 - 9 27m_tsp, hsadc_1_tsp, hsadc_1_tsp */ + GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 8, 8), + GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 8, 7), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 8, 6), + GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 8, 5), + GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 8, 4), + GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 8, 3), + GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 8, 2), + GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 8, 1), + GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 8, 0), + + /* CRU_CLKGATE_CON9 */ + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 9, 1), + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 9, 0), + + /* CRU_CLKGATE_CON10 */ + GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 10, 15), + GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 10, 14), + GATE(0, "aclk_strc_sys", "aclk_cpu", 10, 13), + GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 10, 12), + GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 10, 11), + GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 10, 10), + GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 10, 9), + GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 10, 8), + GATE(0, "sclk_intmem2", "aclk_cpu", 10, 7), + GATE(0, "sclk_intmem1", "aclk_cpu", 10, 6), + GATE(0, "sclk_intmem0", "aclk_cpu", 10, 5), + GATE(0, "aclk_intmem", "aclk_cpu", 10, 4), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 10, 3), + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 10, 2), + GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 10, 1), + GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 10, 0), + + /* CRU_CLKGATE_CON11 */ + GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 11, 11), + GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 11, 10), + GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 11, 9), + GATE(0, "aclk_ccp", "aclk_cpu", 11, 8), + GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 11, 7), + GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 11, 6), + GATE(0, "nclk_ddrupctl1", "ddrphy", 11, 5), + GATE(0, "nclk_ddrupctl0", "ddrphy", 11, 4), + GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 11, 3), + GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_cpu", 11, 2), + GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 11, 1), + GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 11, 0), + + /* CRU_CLKGATE_CON12 */ + GATE(0, "pclk_core_niu", "pclk_dbg_pre", 12, 11), + GATE(0, "cs_dbg", "pclk_dbg_pre", 12, 10), + GATE(0, "pclk_dbg", "pclk_dbg_pre", 12, 9), + GATE(0, "armcore0", "armcore0_s", 12, 8), + GATE(0, "armcore1", "armcore1_s", 12, 7), + GATE(0, "armcore2", "armcore2_s", 12, 6), + GATE(0, "armcore3", "armcore3_s", 12, 5), + GATE(0, "l2ram", "l2ram_s", 12, 4), + GATE(0, "aclk_core_m0", "aclk_core_m0_s", 12, 3), + GATE(0, "aclk_core_mp", "aclk_core_mp_s", 12, 2), + GATE(0, "atclk", "atclk_s", 12, 1), + GATE(0, "pclk_dbg_pre", "pclk_dbg_pre_s", 12, 0), + + /* CRU_CLKGATE_CON13 */ + GATE(SCLK_HEVC_CORE, "sclk_hevc_core", "sclk_hevc_core_s", 13, 15), + GATE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", "sclk_hevc_cabac_s", 13, 14), + GATE(ACLK_HEVC, "aclk_hevc", "aclk_hevc_s", 13, 13), + GATE(0, "wii", "wifi_frac_s", 13, 12), + GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 13, 11), + GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 13, 10), +/* 9 - Not in TRM - hsicphy12m_xin12m in Linux */ + GATE(0, "c2c_host", "aclk_cpu_src", 13, 8), + GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", 13, 7), + GATE(SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", 13, 6), + GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", 13, 5), + GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 13, 4), + GATE(SCLK_EMMC, "sclk_emmc", "sclk_emmc_s", 13, 3), + GATE(SCLK_SDIO1, "sclk_sdio1", "sclk_sdio1_s", 13, 2), + GATE(SCLK_SDIO0, "sclk_sdio0", "sclk_sdio0_s", 13, 1), + GATE(SCLK_SDMMC, "sclk_sdmmc", "sclk_sdmmc_s", 13, 0), + + /* CRU_CLKGATE_CON14 */ + GATE(0, "pclk_alive_niu", "pclk_pd_alive", 14, 12), + GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", 14, 11), + GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 14, 8), + GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 14, 7), + GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 14, 6), + GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 14, 5), + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 14, 4), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 14, 3), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 14, 2), + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 14, 1), + + /* CRU_CLKGATE_CON15*/ + GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 15, 15), + GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 15, 14), + GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 15, 13), + GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 15, 12), + GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 15, 11), + GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 15, 10), + GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio",15, 9), + GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 15, 8), + GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 15, 7), + GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 15, 6), + GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 15, 5), +/* 4 - aclk_lcdc_iep */ + GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 15, 3), + GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 15, 2), + GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 15, 1), + GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 15, 0), + + /* CRU_CLKGATE_CON16 */ + GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", 16, 11), + GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", 16, 10), + GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 16, 9), + GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", 16, 8), + GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 16, 7), + GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 16, 6), + GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 16, 5), + GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 16, 4), + GATE(PCLK_ISP_IN, "pclk_isp_in", "ext_isp", 16, 3), + GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 16, 2), + GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 16, 1), + GATE(0, "pclk_vip_in", "ext_vip", 16, 0), + + /* CRU_CLKGATE_CON17 */ + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 17, 4), + GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", 17, 3), + GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 17, 2), + GATE(0, "pclk_intmem1", "pclk_pd_pmu", 17, 1), + GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", 17, 0), + + /* CRU_CLKGATE_CON18 */ + GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 18, 0), +}; + +/* + * PLLs + */ +#define PLL_RATE_BA(_hz, _ref, _fb, _post, _ba) \ +{ \ + .freq = _hz, \ + .refdiv = _ref, \ + .fbdiv = _fb, \ + .postdiv1 = _post, \ + .bwadj = _ba, \ +} + +#define PLL_RATE(_mhz, _ref, _fb, _post) \ + PLL_RATE_BA(_mhz, _ref, _fb, _post, ((_fb < 2) ? 1 : _fb >> 1)) + +static struct rk_clk_pll_rate rk3288_pll_rates[] = { + PLL_RATE( 2208000000, 1, 92, 1), + PLL_RATE( 2184000000, 1, 91, 1), + PLL_RATE( 2160000000, 1, 90, 1), + PLL_RATE( 2136000000, 1, 89, 1), + PLL_RATE( 2112000000, 1, 88, 1), + PLL_RATE( 2088000000, 1, 87, 1), + PLL_RATE( 2064000000, 1, 86, 1), + PLL_RATE( 2040000000, 1, 85, 1), + PLL_RATE( 2016000000, 1, 84, 1), + PLL_RATE( 1992000000, 1, 83, 1), + PLL_RATE( 1968000000, 1, 82, 1), + PLL_RATE( 1944000000, 1, 81, 1), + PLL_RATE( 1920000000, 1, 80, 1), + PLL_RATE( 1896000000, 1, 79, 1), + PLL_RATE( 1872000000, 1, 78, 1), + PLL_RATE( 1848000000, 1, 77, 1), + PLL_RATE( 1824000000, 1, 76, 1), + PLL_RATE( 1800000000, 1, 75, 1), + PLL_RATE( 1776000000, 1, 74, 1), + PLL_RATE( 1752000000, 1, 73, 1), + PLL_RATE( 1728000000, 1, 72, 1), + PLL_RATE( 1704000000, 1, 71, 1), + PLL_RATE( 1680000000, 1, 70, 1), + PLL_RATE( 1656000000, 1, 69, 1), + PLL_RATE( 1632000000, 1, 68, 1), + PLL_RATE( 1608000000, 1, 67, 1), + PLL_RATE( 1560000000, 1, 65, 1), + PLL_RATE( 1512000000, 1, 63, 1), + PLL_RATE( 1488000000, 1, 62, 1), + PLL_RATE( 1464000000, 1, 61, 1), + PLL_RATE( 1440000000, 1, 60, 1), + PLL_RATE( 1416000000, 1, 59, 1), + PLL_RATE( 1392000000, 1, 58, 1), + PLL_RATE( 1368000000, 1, 57, 1), + PLL_RATE( 1344000000, 1, 56, 1), + PLL_RATE( 1320000000, 1, 55, 1), + PLL_RATE( 1296000000, 1, 54, 1), + PLL_RATE( 1272000000, 1, 53, 1), + PLL_RATE( 1248000000, 1, 52, 1), + PLL_RATE( 1224000000, 1, 51, 1), + PLL_RATE( 1200000000, 1, 50, 1), + PLL_RATE( 1188000000, 2, 99, 1), + PLL_RATE( 1176000000, 1, 49, 1), + PLL_RATE( 1128000000, 1, 47, 1), + PLL_RATE( 1104000000, 1, 46, 1), + PLL_RATE( 1008000000, 1, 84, 2), + PLL_RATE( 912000000, 1, 76, 2), + PLL_RATE( 891000000, 8, 594, 2), + PLL_RATE( 888000000, 1, 74, 2), + PLL_RATE( 816000000, 1, 68, 2), + PLL_RATE( 798000000, 2, 133, 2), + PLL_RATE( 792000000, 1, 66, 2), + PLL_RATE( 768000000, 1, 64, 2), + PLL_RATE( 742500000, 8, 495, 2), + PLL_RATE( 696000000, 1, 58, 2), + PLL_RATE_BA( 621000000, 1, 207, 8, 1), + PLL_RATE( 600000000, 1, 50, 2), + PLL_RATE_BA( 594000000, 1, 198, 8, 1), + PLL_RATE( 552000000, 1, 46, 2), + PLL_RATE( 504000000, 1, 84, 4), + PLL_RATE( 500000000, 3, 125, 2), + PLL_RATE( 456000000, 1, 76, 4), + PLL_RATE( 428000000, 1, 107, 6), + PLL_RATE( 408000000, 1, 68, 4), + PLL_RATE( 400000000, 3, 100, 2), + PLL_RATE_BA( 394000000, 1, 197, 12, 1), + PLL_RATE( 384000000, 2, 128, 4), + PLL_RATE( 360000000, 1, 60, 4), + PLL_RATE_BA( 356000000, 1, 178, 12, 1), + PLL_RATE_BA( 324000000, 1, 189, 14, 1), + PLL_RATE( 312000000, 1, 52, 4), + PLL_RATE_BA( 308000000, 1, 154, 12, 1), + PLL_RATE_BA( 303000000, 1, 202, 16, 1), + PLL_RATE( 300000000, 1, 75, 6), + PLL_RATE_BA( 297750000, 2, 397, 16, 1), + PLL_RATE_BA( 293250000, 2, 391, 16, 1), + PLL_RATE_BA( 292500000, 1, 195, 16, 1), + PLL_RATE( 273600000, 1, 114, 10), + PLL_RATE_BA( 273000000, 1, 182, 16, 1), + PLL_RATE_BA( 270000000, 1, 180, 16, 1), + PLL_RATE_BA( 266250000, 2, 355, 16, 1), + PLL_RATE_BA( 256500000, 1, 171, 16, 1), + PLL_RATE( 252000000, 1, 84, 8), + PLL_RATE_BA( 250500000, 1, 167, 16, 1), + PLL_RATE_BA( 243428571, 1, 142, 14, 1), + PLL_RATE( 238000000, 1, 119, 12), + PLL_RATE_BA( 219750000, 2, 293, 16, 1), + PLL_RATE_BA( 216000000, 1, 144, 16, 1), + PLL_RATE_BA( 213000000, 1, 142, 16, 1), + PLL_RATE( 195428571, 1, 114, 14), + PLL_RATE( 160000000, 1, 80, 12), + PLL_RATE( 157500000, 1, 105, 16), + PLL_RATE( 126000000, 1, 84, 16), + PLL_RATE( 48000000, 1, 64, 32), + {}, +}; + +static struct rk_clk_armclk_rates rk3288_armclk_rates[] = { + { 1800000000, 1}, + { 1704000000, 1}, + { 1608000000, 1}, + { 1512000000, 1}, + { 1416000000, 1}, + { 1200000000, 1}, + { 1008000000, 1}, + { 816000000, 1}, + { 696000000, 1}, + { 600000000, 1}, + { 408000000, 1}, + { 312000000, 1}, + { 216000000, 1}, + { 126000000, 1}, +}; + +/* Standard PLL. */ +#define PLL(_id, _name, _base, _shift) \ +{ \ + .type = RK3066_CLK_PLL, \ + .clk.pll = &(struct rk_clk_pll_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = pll_src_p, \ + .clkdef.parent_cnt = nitems(pll_src_p), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .base_offset = _base, \ + .mode_reg = CRU_MODE_CON, \ + .mode_shift = _shift, \ + .rates = rk3288_pll_rates, \ + }, \ +} + +#define ARMDIV(_id, _name, _pn, _r, _o, _ds, _dw, _ms, _mw, _mp, _ap) \ +{ \ + .type = RK_CLK_ARMCLK, \ + .clk.armclk = &(struct rk_clk_armclk_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = _pn, \ + .clkdef.parent_cnt = nitems(_pn), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .muxdiv_offset = CRU_CLKSEL_CON(_o), \ + .mux_shift = _ms, \ + .mux_width = _mw, \ + .div_shift = _ds, \ + .div_width = _dw, \ + .main_parent = _mp, \ + .alt_parent = _ap, \ + .rates = _r, \ + .nrates = nitems(_r), \ + }, \ +} + +PLIST(pll_src_p) = {"xin24m", "xin24m", "xin32k"}; +PLIST(armclk_p)= {"apll_core", "gpll_core"}; +PLIST(ddrphy_p) = {"dpll_ddr", "gpll_ddr"}; +PLIST(aclk_cpu_p) = {"cpll_aclk_cpu", "gpll_aclk_cpu"}; + +PLIST(cpll_gpll_p) = {"cpll", "gpll"}; +PLIST(npll_cpll_gpll_p) = {"npll", "cpll", "gpll"}; +PLIST(cpll_gpll_npll_p) = {"cpll", "gpll", "npll"}; +PLIST(cpll_gpll_usb480m_p)= {"cpll", "gpll", "usbphy480m_src"}; +PLIST(cpll_gpll_usb480m_npll_p) = {"cpll", "gpll", "usbphy480m_src", "npll"}; + +PLIST(mmc_p) = {"cpll", "gpll", "xin24m", "xin24m"}; +PLIST(i2s_pre_p) = {"i2s_src", "i2s_frac", "ext_i2s", "xin12m"}; +PLIST(i2s_clkout_p) = {"i2s_pre", "xin12m"}; +PLIST(spdif_p) = {"spdif_pre", "spdif_frac", "xin12m"}; +PLIST(spdif_8ch_p) = {"spdif_8ch_pre", "spdif_8ch_frac", "xin12m"}; +PLIST(uart0_p) = {"uart0_src", "uart0_frac", "xin24m"}; +PLIST(uart1_p) = {"uart1_src", "uart1_frac", "xin24m"}; +PLIST(uart2_p) = {"uart2_src", "uart2_frac", "xin24m"}; +PLIST(uart3_p) = {"uart3_src", "uart3_frac", "xin24m"}; +PLIST(uart4_p) = {"uart4_src", "uart4_frac", "xin24m"}; +PLIST(vip_out_p) = {"vip_src", "xin24m"}; +PLIST(mac_p) = {"mac_pll_src", "ext_gmac"}; +PLIST(hsadcout_p) = {"hsadc_src", "ext_hsadc"}; +PLIST(edp_24m_p) = {"ext_edp_24m", "xin24m"}; +PLIST(tspout_p) = {"cpll", "gpll", "npll", "xin27m"}; +PLIST(wifi_p) = {"cpll", "gpll"}; +PLIST(usbphy480m_p) = {"sclk_otgphy1_480m", "sclk_otgphy2_480m", "sclk_otgphy0_480m"}; + +/* PLIST(aclk_vcodec_pre_p) = {"aclk_vepu", "aclk_vdpu"}; */ + + +static struct rk_clk rk3288_clks[] = { + /* External clocks */ + LINK("xin24m"), + FRATE(0, "xin32k", 32000), + FRATE(0, "xin27m", 27000000), + FRATE(0, "ext_hsadc", 0), + FRATE(0, "ext_jtag", 0), + FRATE(0, "ext_isp", 0), + FRATE(0, "ext_vip", 0), + FRATE(0, "ext_i2s", 0), + FRATE(0, "ext_edp_24m", 0), + + FRATE(0, "sclk_otgphy0_480m", 0), + FRATE(0, "sclk_otgphy1_480m", 0), + FRATE(0, "sclk_otgphy2_480m", 0), + + FRATE(0, "aclk_vcodec_pre", 0), + + /* Fixed dividers */ + FFACT(0, "xin12m", "xin24m", 1, 2), + FFACT(0, "hclk_vcodec_pre_s", "aclk_vcodec_pre", 1, 4), + + PLL(PLL_APLL, "apll", CRU_APLL_CON(0), 0), + PLL(PLL_DPLL, "dpll", CRU_DPLL_CON(0), 4), + PLL(PLL_CPLL, "cpll", CRU_CPLL_CON(0), 8), + PLL(PLL_GPLL, "gpll", CRU_GPLL_CON(0), 12), + PLL(PLL_NPLL, "npll", CRU_NPLL_CON(0), 14), + + /* CRU_CLKSEL0_CON */ + ARMDIV(ARMCLK, "armclk", armclk_p, rk3288_armclk_rates, + 0, 8, 5, 15, 1, 0, 1), + CDIV(0, "aclk_core_mp_s", "armclk", 0, + 0, 4, 4), + CDIV(0, "aclk_core_m0_s", "armclk", 0, + 0, 0, 4), + + /* CRU_CLKSEL1_CON */ + CDIV(0, "pclk_cpu_s", "aclk_cpu_pre", 0, + 1, 12, 3), + CDIV(0, "hclk_cpu_s", "aclk_cpu_pre", RK_CLK_COMPOSITE_DIV_EXP, + 1, 8, 2), + COMP(0, "aclk_cpu_src", aclk_cpu_p, 0, + 1, 3, 5, 15, 1), + CDIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0, + 1, 0, 3), + + /* CRU_CLKSEL2_CON */ +/* 12:8 testout_div */ + CDIV(0, "sclk_tsadc_s", "xin32k", 0, + 2, 0, 6), + + /* CRU_CLKSEL3_CON */ + MUX(SCLK_UART4, "sclk_uart4", uart4_p, 0, + 3, 8, 2), + CDIV(0, "uart4_src_s", "uart_src", 0, + 3, 0, 7), + + /* CRU_CLKSEL4_CON */ + MUX(0, "i2s_pre", i2s_pre_p, 0, + 4, 8, 2), + MUX(0, "i2s0_clkout_s", i2s_clkout_p, 0, + 4, 12, 1), + COMP(0, "i2s_src_s", cpll_gpll_p, 0, + 4, 0, 7, 15, 1), + + /* CRU_CLKSEL5_CON */ + MUX(0, "spdif_src", cpll_gpll_p, 0, + 5, 15, 1), + MUX(0, "spdif_mux", spdif_p, 0, + 5, 8, 2), + CDIV(0, "spdif_pre_s", "spdif_src", 0, + 5, 0, 7), + + /* CRU_CLKSEL6_CON */ + COMP(0, "sclk_isp_jpe_s", cpll_gpll_npll_p, 0, + 6, 8, 6, 14, 2), + COMP(0, "sclk_isp_s", cpll_gpll_npll_p, 0, + 6, 0, 6, 6, 2), + + /* CRU_CLKSEL7_CON */ + FRACT(0, "uart4_frac_s", "uart4_src", 0, + 7), + + /* CRU_CLKSEL8_CON */ + FRACT(0, "i2s_frac_s", "i2s_src", 0, + 8), + + /* CRU_CLKSEL9_CON */ + FRACT(0, "spdif_frac_s", "spdif_src", 0, + 9), + + /* CRU_CLKSEL10_CON */ + CDIV(0, "pclk_peri_s", "aclk_peri_src", RK_CLK_COMPOSITE_DIV_EXP, + 10, 12, 2), + CDIV(0, "hclk_peri_s", "aclk_peri_src", RK_CLK_COMPOSITE_DIV_EXP, + 10, 8, 2), + COMP(0, "aclk_peri_src_s", cpll_gpll_p, 0, + 10, 0, 5, 15, 1), + + /* CRU_CLKSEL11_CON */ + COMP(0, "sclk_sdmmc_s", mmc_p, 0, + 11, 0, 6, 6, 2), + + /* CRU_CLKSEL12_CON */ + COMP(0, "sclk_emmc_s", mmc_p, 0, + 12, 8, 6, 14, 2), + COMP(0, "sclk_sdio0_s", mmc_p, 0, + 12, 0, 6, 6, 2), + + /* CRU_CLKSEL13_CON */ + MUX(0, "uart_src", cpll_gpll_p, 0, + 13, 15, 1), + MUX(0, "usbphy480m_src_s", usbphy480m_p, 0, + 13, 11, 2), + MUX(SCLK_UART0, "sclk_uart0", uart0_p, 0, + 13, 8, 2), + COMP(0, "uart0_src_s", cpll_gpll_usb480m_npll_p, 0, + 13, 0, 7, 13, 2), + + /* CRU_CLKSEL14_CON */ + MUX(SCLK_UART1, "sclk_uart1", uart1_p, 0, + 14, 8, 2), + CDIV(0, "uart1_src_s", "uart_src", 0, + 14, 0, 7), + + + /* CRU_CLKSEL15_CON */ + MUX(SCLK_UART2, "sclk_uart2", uart2_p, 0, + 15, 8, 2), + CDIV(0, "uart2_src_s", "uart_src", 0, + 15, 0, 7), + + /* CRU_CLKSEL16_CON */ + MUX(SCLK_UART3, "sclk_uart3", uart3_p, 0, + 16, 8, 2), + CDIV(0, "uart3_src_s", "uart_src", 0, + 16, 0, 7), + + /* CRU_CLKSEL17_CON */ + FRACT(0, "uart0_frac_s", "uart0_src", 0, + 17), + + /* CRU_CLKSEL18_CON */ + FRACT(0, "uart1_frac_s", "uart1_src", 0, + 18), + + /* CRU_CLKSEL19_CON */ + FRACT(0, "uart2_frac_s", "uart2_src", 0, + 19), + + /* CRU_CLKSEL20_CON */ + FRACT(0, "uart3_frac_s", "uart3_src", 0, + 20), + + /* CRU_CLKSEL21_CON */ + COMP(0, "mac_pll_src_s", npll_cpll_gpll_p, 0, + 21, 8, 5, 0, 2), + MUX(SCLK_MAC, "mac_clk", mac_p, 0, + 21, 4, 1), + + /* CRU_CLKSEL22_CON */ + MUX(0, "sclk_hsadc_out", hsadcout_p, 0, + 22, 4, 1), + COMP(0, "hsadc_src_s", cpll_gpll_p, 0, + 22, 8, 8, 0, 1), + MUX(0, "wifi_src", wifi_p, 0, + 22, 1, 1), +/* 7 - inverter "sclk_hsadc", "sclk_hsadc_out" */ + + /* CRU_CLKSEL23_CON */ + FRACT(0, "wifi_frac_s", "wifi_src", 0, + 23), + + /* CRU_CLKSEL24_CON */ + CDIV(0, "sclk_saradc_s", "xin24m", 0, + 24, 8, 8), + + /* CRU_CLKSEL25_CON */ + COMP(0, "sclk_spi1_s", cpll_gpll_p, 0, + 25, 8, 7, 15, 1), + COMP(0, "sclk_spi0_s", cpll_gpll_p, 0, + 25, 0, 7, 7, 1), + + /* CRU_CLKSEL26_CON */ + COMP(SCLK_VIP_OUT, "sclk_vip_out", vip_out_p, 0, + 26, 9, 5, 15, 1), + MUX(0, "vip_src_s", cpll_gpll_p, 0, + 26, 8, 1), + CDIV(0, "crypto_s", "aclk_cpu_pre", 0, + 26, 6, 2), + COMP(0, "ddrphy", ddrphy_p, RK_CLK_COMPOSITE_DIV_EXP, + 26, 0, 2, 2, 1), + + /* CRU_CLKSEL27_CON */ + COMP(0, "dclk_vop0_s", cpll_gpll_npll_p, 0, + 27, 8, 8, 0, 2), + + MUX(0, "sclk_edp_24m_s", edp_24m_p, 0, + 28, 15, 1), + CDIV(0, "hclk_vio", "aclk_vio0", 0, + 28, 8, 5), + COMP(0, "sclk_edp_s", cpll_gpll_npll_p, 0, + 28, 0, 6, 6, 2), + + /* CRU_CLKSEL29_CON */ + COMP(0, "dclk_vop1_s", cpll_gpll_npll_p, 0, + 29, 8, 8, 6, 2), +/* 4 - inverter "pclk_vip" "pclk_vip_in" */ +/* 3 - inverter "pclk_isp", "pclk_isp_in" */ + + /* CRU_CLKSEL30_CON */ + COMP(0, "sclk_rga_s", cpll_gpll_usb480m_p, 0, + 30, 8, 5, 14, 2), + COMP(0, "aclk_rga_pre_s", cpll_gpll_usb480m_p, 0, + 30, 0, 5, 6, 2), + + /* CRU_CLKSEL31_CON */ + COMP(0, "aclk_vio1_s", cpll_gpll_usb480m_p, 0, + 31, 8, 5, 14, 2), + COMP(0, "aclk_vio0_s", cpll_gpll_usb480m_p, 0, + 31, 0, 5, 6, 2), + + /* CRU_CLKSEL32_CON */ + COMP(0, "aclk_vdpu_s", cpll_gpll_usb480m_p, 0, + 32, 8, 5, 14, 2), + COMP(0, "aclk_vepu_s", cpll_gpll_usb480m_p, 0, + 32, 0, 5, 6, 2), + + /* CRU_CLKSEL33_CON */ + CDIV(0, "pclk_pd_alive", "gpll", 0, + 33, 8, 5), + CDIV(0, "pclk_pd_pmu_s", "gpll", 0, + 33, 0, 5), + + /* CRU_CLKSEL34_CON */ + COMP(0, "sclk_sdio1_s", mmc_p, 0, + 34, 8, 6, 14, 2), + COMP(0, "sclk_gpu_s", cpll_gpll_usb480m_npll_p, 0, + 34, 0, 5, 6, 2), + + /* CRU_CLKSEL35_CON */ + COMP(0, "sclk_tspout_s", tspout_p, 0, + 35, 8, 5, 14, 2), + COMP(0, "sclk_tsp_s", cpll_gpll_npll_p, 0, + 35, 0, 5, 6, 2), + + /* CRU_CLKSEL36_CON */ + CDIV(0, "armcore3_s", "armclk", 0, + 36, 12, 3), + CDIV(0, "armcore2_s", "armclk", 0, + 36, 8, 3), + CDIV(0, "armcore1_s", "armclk", 0, + 36, 4, 3), + CDIV(0, "armcore0_s", "armclk", 0, + 36, 0, 3), + + /* CRU_CLKSEL37_CON */ + CDIV(0, "pclk_dbg_pre_s", "armclk", 0, + 37, 9, 5), + CDIV(0, "atclk_s", "armclk", 0, + 37, 4, 5), + CDIV(0, "l2ram_s", "armclk", 0, + 37, 0, 3), + + /* CRU_CLKSEL38_CON */ + COMP(0, "sclk_nandc1_s", cpll_gpll_p, 0, + 38, 8, 5, 15, 1), + COMP(0, "sclk_nandc0_s", cpll_gpll_p, 0, + 38, 0, 5, 7, 1), + + /* CRU_CLKSEL39_CON */ + COMP(0, "aclk_hevc_s", cpll_gpll_npll_p, 0, + 39, 8, 5, 14, 2), + COMP(0, "sclk_spi2_s", cpll_gpll_p, 0, + 39, 0, 7, 7, 1), + + /* CRU_CLKSEL40_CON */ + CDIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0, + 40, 12, 2), + MUX(0, "spdif_8ch_mux", spdif_8ch_p, 0, + 40, 8, 2), + CDIV(0, "spdif_8ch_pre_s", "spdif_src", 0, + 40, 0, 7), + + /* CRU_CLKSEL41_CON */ + FRACT(0, "spdif_8ch_frac_s", "spdif_8ch_pre", 0, + 41), + + /* CRU_CLKSEL42_CON */ + COMP(0, "sclk_hevc_core_s", cpll_gpll_npll_p, 0, + 42, 8, 5, 14, 2), + COMP(0, "sclk_hevc_cabac_s", cpll_gpll_npll_p, 0, + 42, 0, 5, 6, 2), +/* + * not yet implemented MMC clocks + * id name src reg + * SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK3288_SDMMC_CON0 + * SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1, + + * SCLK_SDIO0_DRV, "sdio0_drv", "sclk_sdio0", RK3288_SDIO0_CON0, 1), + * SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0), + + * SCLK_SDIO1_DRV, "sdio1_drv", "sclk_sdio1", RK3288_SDIO1_CON0, 1), + * SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0), + + * SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3288_EMMC_CON0, 1), + * SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3288_EMMC_CON1, 0), + * + * and GFR based mux for "aclk_vcodec_pre" + */ + +}; + +static int +rk3288_cru_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_is_compatible(dev, "rockchip,rk3288-cru")) { + device_set_desc(dev, "Rockchip RK3288 Clock and Reset Unit"); + return (BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static int +rk3288_cru_attach(device_t dev) +{ + struct rk_cru_softc *sc; + + sc = device_get_softc(dev); + sc->dev = dev; + + sc->gates = rk3288_gates; + sc->ngates = nitems(rk3288_gates); + + sc->clks = rk3288_clks; + sc->nclks = nitems(rk3288_clks); + + sc->reset_num = CRU_SOFTRST_SIZE * 16; + sc->reset_offset = CRU_SOFTRST_CON(0); + + return (rk_cru_attach(dev)); +} + +static device_method_t rk3288_cru_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, rk3288_cru_probe), + DEVMETHOD(device_attach, rk3288_cru_attach), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(rk3288_cru, rk3288_cru_driver, rk3288_cru_methods, + sizeof(struct rk_cru_softc), rk_cru_driver); + +EARLY_DRIVER_MODULE(rk3288_cru, simplebus, rk3288_cru_driver, 0, 0, + BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE + 1); diff --git a/sys/dev/clk/rockchip/rk3328_cru.c b/sys/dev/clk/rockchip/rk3328_cru.c new file mode 100644 index 000000000000..6a9583250516 --- /dev/null +++ b/sys/dev/clk/rockchip/rk3328_cru.c @@ -0,0 +1,1115 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2018-2021 Emmanuel Vadot <manu@freebsd.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <machine/bus.h> + +#include <dev/fdt/simplebus.h> + +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> + +#include <dev/extres/clk/clk_div.h> +#include <dev/extres/clk/clk_fixed.h> +#include <dev/extres/clk/clk_mux.h> + +#include <dev/clk/rockchip/rk_cru.h> + +#define CRU_CLKSEL_CON(x) (0x100 + (x) * 0x4) +#define CRU_CLKGATE_CON(x) (0x200 + (x) * 0x4) + +/* Registers */ +#define RK3328_GRF_SOC_CON4 0x410 +#define RK3328_GRF_MAC_CON1 0x904 +#define RK3328_GRF_MAC_CON2 0x908 + +/* Exported clocks */ + +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_GPLL 4 +#define PLL_NPLL 5 +#define ARMCLK 6 + +/* SCLK */ +#define SCLK_RTC32K 30 +#define SCLK_SDMMC_EXT 31 +#define SCLK_SPI 32 +#define SCLK_SDMMC 33 +#define SCLK_SDIO 34 +#define SCLK_EMMC 35 +#define SCLK_TSADC 36 +#define SCLK_SARADC 37 +#define SCLK_UART0 38 +#define SCLK_UART1 39 +#define SCLK_UART2 40 +#define SCLK_I2S0 41 +#define SCLK_I2S1 42 +#define SCLK_I2S2 43 +#define SCLK_I2S1_OUT 44 +#define SCLK_I2S2_OUT 45 +#define SCLK_SPDIF 46 +#define SCLK_TIMER0 47 +#define SCLK_TIMER1 48 +#define SCLK_TIMER2 49 +#define SCLK_TIMER3 50 +#define SCLK_TIMER4 51 +#define SCLK_TIMER5 52 +#define SCLK_WIFI 53 +#define SCLK_CIF_OUT 54 +#define SCLK_I2C0 55 +#define SCLK_I2C1 56 +#define SCLK_I2C2 57 +#define SCLK_I2C3 58 +#define SCLK_CRYPTO 59 +#define SCLK_PWM 60 +#define SCLK_PDM 61 +#define SCLK_EFUSE 62 +#define SCLK_OTP 63 +#define SCLK_DDRCLK 64 +#define SCLK_VDEC_CABAC 65 +#define SCLK_VDEC_CORE 66 +#define SCLK_VENC_DSP 67 +#define SCLK_VENC_CORE 68 +#define SCLK_RGA 69 +#define SCLK_HDMI_SFC 70 +#define SCLK_HDMI_CEC 71 /* Unused ? */ +#define SCLK_USB3_REF 72 +#define SCLK_USB3_SUSPEND 73 +#define SCLK_SDMMC_DRV 74 +#define SCLK_SDIO_DRV 75 +#define SCLK_EMMC_DRV 76 +#define SCLK_SDMMC_EXT_DRV 77 +#define SCLK_SDMMC_SAMPLE 78 +#define SCLK_SDIO_SAMPLE 79 +#define SCLK_EMMC_SAMPLE 80 +#define SCLK_SDMMC_EXT_SAMPLE 81 +#define SCLK_VOP 82 +#define SCLK_MAC2PHY_RXTX 83 +#define SCLK_MAC2PHY_SRC 84 +#define SCLK_MAC2PHY_REF 85 +#define SCLK_MAC2PHY_OUT 86 +#define SCLK_MAC2IO_RX 87 +#define SCLK_MAC2IO_TX 88 +#define SCLK_MAC2IO_REFOUT 89 +#define SCLK_MAC2IO_REF 90 +#define SCLK_MAC2IO_OUT 91 +#define SCLK_TSP 92 +#define SCLK_HSADC_TSP 93 +#define SCLK_USB3PHY_REF 94 +#define SCLK_REF_USB3OTG 95 +#define SCLK_USB3OTG_REF 96 +#define SCLK_USB3OTG_SUSPEND 97 +#define SCLK_REF_USB3OTG_SRC 98 +#define SCLK_MAC2IO_SRC 99 +#define SCLK_MAC2IO 100 +#define SCLK_MAC2PHY 101 +#define SCLK_MAC2IO_EXT 102 + +/* DCLK */ +#define DCLK_LCDC 120 +#define DCLK_HDMIPHY 121 +#define HDMIPHY 122 +#define USB480M 123 +#define DCLK_LCDC_SRC 124 + +/* ACLK */ +#define ACLK_AXISRAM 130 /* Unused */ +#define ACLK_VOP_PRE 131 +#define ACLK_USB3OTG 132 +#define ACLK_RGA_PRE 133 +#define ACLK_DMAC 134 /* Unused */ +#define ACLK_GPU 135 +#define ACLK_BUS_PRE 136 +#define ACLK_PERI_PRE 137 +#define ACLK_RKVDEC_PRE 138 +#define ACLK_RKVDEC 139 +#define ACLK_RKVENC 140 +#define ACLK_VPU_PRE 141 +#define ACLK_VIO_PRE 142 +#define ACLK_VPU 143 +#define ACLK_VIO 144 +#define ACLK_VOP 145 +#define ACLK_GMAC 146 +#define ACLK_H265 147 +#define ACLK_H264 148 +#define ACLK_MAC2PHY 149 +#define ACLK_MAC2IO 150 +#define ACLK_DCF 151 +#define ACLK_TSP 152 +#define ACLK_PERI 153 +#define ACLK_RGA 154 +#define ACLK_IEP 155 +#define ACLK_CIF 156 +#define ACLK_HDCP 157 + +/* PCLK */ +#define PCLK_GPIO0 200 +#define PCLK_GPIO1 201 +#define PCLK_GPIO2 202 +#define PCLK_GPIO3 203 +#define PCLK_GRF 204 +#define PCLK_I2C0 205 +#define PCLK_I2C1 206 +#define PCLK_I2C2 207 +#define PCLK_I2C3 208 +#define PCLK_SPI 209 +#define PCLK_UART0 210 +#define PCLK_UART1 211 +#define PCLK_UART2 212 +#define PCLK_TSADC 213 +#define PCLK_PWM 214 +#define PCLK_TIMER 215 +#define PCLK_BUS_PRE 216 +#define PCLK_PERI_PRE 217 /* Unused */ +#define PCLK_HDMI_CTRL 218 /* Unused */ +#define PCLK_HDMI_PHY 219 /* Unused */ +#define PCLK_GMAC 220 +#define PCLK_H265 221 +#define PCLK_MAC2PHY 222 +#define PCLK_MAC2IO 223 +#define PCLK_USB3PHY_OTG 224 +#define PCLK_USB3PHY_PIPE 225 +#define PCLK_USB3_GRF 226 +#define PCLK_USB2_GRF 227 +#define PCLK_HDMIPHY 228 +#define PCLK_DDR 229 +#define PCLK_PERI 230 +#define PCLK_HDMI 231 +#define PCLK_HDCP 232 +#define PCLK_DCF 233 +#define PCLK_SARADC 234 +#define PCLK_ACODECPHY 235 +#define PCLK_WDT 236 /* Controlled from the secure GRF */ + +/* HCLK */ +#define HCLK_PERI 308 +#define HCLK_TSP 309 +#define HCLK_GMAC 310 /* Unused */ +#define HCLK_I2S0_8CH 311 +#define HCLK_I2S1_8CH 312 +#define HCLK_I2S2_2CH 313 +#define HCLK_SPDIF_8CH 314 +#define HCLK_VOP 315 +#define HCLK_NANDC 316 /* Unused */ +#define HCLK_SDMMC 317 +#define HCLK_SDIO 318 +#define HCLK_EMMC 319 +#define HCLK_SDMMC_EXT 320 +#define HCLK_RKVDEC_PRE 321 +#define HCLK_RKVDEC 322 +#define HCLK_RKVENC 323 +#define HCLK_VPU_PRE 324 +#define HCLK_VIO_PRE 325 +#define HCLK_VPU 326 +/* 327 doesn't exists */ +#define HCLK_BUS_PRE 328 +#define HCLK_PERI_PRE 329 /* Unused */ +#define HCLK_H264 330 +#define HCLK_CIF 331 +#define HCLK_OTG_PMU 332 +#define HCLK_OTG 333 +#define HCLK_HOST0 334 +#define HCLK_HOST0_ARB 335 +#define HCLK_CRYPTO_MST 336 +#define HCLK_CRYPTO_SLV 337 +#define HCLK_PDM 338 +#define HCLK_IEP 339 +#define HCLK_RGA 340 +#define HCLK_HDCP 341 + +static struct rk_cru_gate rk3328_gates[] = { + /* CRU_CLKGATE_CON0 */ + GATE(0, "core_apll_clk", "apll", 0, 0), + GATE(0, "core_dpll_clk", "dpll", 0, 1), + GATE(0, "core_gpll_clk", "gpll", 0, 2), + /* Bit 3 bus_src_clk_en */ + /* Bit 4 clk_ddrphy_src_en */ + /* Bit 5 clk_ddrpd_src_en */ + /* Bit 6 clk_ddrmon_en */ + /* Bit 7-8 unused */ + /* Bit 9 testclk_en */ + GATE(SCLK_WIFI, "sclk_wifi", "sclk_wifi_c", 0, 10), + GATE(SCLK_RTC32K, "clk_rtc32k", "clk_rtc32k_c", 0, 11), + GATE(0, "core_npll_clk", "npll", 0, 12), + /* Bit 13-15 unused */ + + /* CRU_CLKGATE_CON1 */ + /* Bit 0 unused */ + GATE(0, "clk_i2s0_div", "clk_i2s0_div_c", 1, 1), + GATE(0, "clk_i2s0_frac", "clk_i2s0_frac_f", 1, 2), + GATE(SCLK_I2S0, "clk_i2s0", "clk_i2s0_mux", 1, 3), + GATE(0, "clk_i2s1_div", "clk_i2s1_div_c", 1, 4), + GATE(0, "clk_i2s1_frac", "clk_i2s1_frac_f", 1, 5), + GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", 1, 6), + GATE(0, "clk_i2s1_out", "clk_i2s1_mux", 1, 7), + GATE(0, "clk_i2s2_div", "clk_i2s2_div_c", 1, 8), + GATE(0, "clk_i2s2_frac", "clk_i2s2_frac_f", 1, 9), + GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", 1, 10), + GATE(0, "clk_i2s2_out", "clk_i2s2_mux", 1, 11), + GATE(0, "clk_spdif_div", "clk_spdif_div_c", 1, 12), + GATE(0, "clk_spdif_frac", "clk_spdif_frac_f", 1, 13), + GATE(0, "clk_uart0_div", "clk_uart0_div_c", 1, 14), + GATE(0, "clk_uart0_frac", "clk_uart0_frac_f", 1, 15), + + /* CRU_CLKGATE_CON2 */ + GATE(0, "clk_uart1_div", "clk_uart1_div_c", 2, 0), + GATE(0, "clk_uart1_frac", "clk_uart1_frac_f", 2, 1), + GATE(0, "clk_uart2_div", "clk_uart2_div_c", 2, 2), + GATE(0, "clk_uart2_frac", "clk_uart2_frac_f", 2, 3), + GATE(SCLK_CRYPTO, "clk_crypto", "clk_crypto_c", 2, 4), + GATE(SCLK_TSP, "clk_tsp", "clk_tsp_c", 2, 5), + GATE(SCLK_TSADC, "clk_tsadc_src", "clk_tsadc_c", 2, 6), + GATE(SCLK_SPI, "clk_spi", "clk_spi_c", 2, 7), + GATE(SCLK_PWM, "clk_pwm", "clk_pwm_c", 2, 8), + GATE(SCLK_I2C0, "clk_i2c0_src", "clk_i2c0_c", 2, 9), + GATE(SCLK_I2C1, "clk_i2c1_src", "clk_i2c1_c", 2, 10), + GATE(SCLK_I2C2, "clk_i2c2_src", "clk_i2c2_c", 2, 11), + GATE(SCLK_I2C3, "clk_i2c3_src", "clk_i2c3_c", 2, 12), + GATE(SCLK_EFUSE, "clk_efuse", "clk_efuse_c", 2, 13), + GATE(SCLK_SARADC, "clk_saradc", "clk_saradc_c", 2, 14), + GATE(SCLK_PDM, "clk_pdm", "clk_pdm_c", 2, 15), + + /* CRU_CLKGATE_CON3 */ + GATE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", "clk_mac2phy_src_c", 3, 0), + GATE(SCLK_MAC2IO_SRC, "clk_mac2io_src", "clk_mac2io_src_c", 3, 1), + GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_c", 3, 2), + /* Bit 3 gmac_gpll_src_en Unused ? */ + /* Bit 4 gmac_vpll_src_en Unused ? */ + GATE(SCLK_MAC2IO_OUT, "clk_mac2io_out", "clk_mac2io_out_c", 3, 5), + /* Bit 6-7 unused */ + GATE(SCLK_OTP, "clk_otp", "clk_otp_c", 3, 8), + /* Bit 9-15 unused */ + + /* CRU_CLKGATE_CON4 */ + GATE(0, "periph_gclk_src", "gpll", 4, 0), + GATE(0, "periph_cclk_src", "cpll", 4, 1), + GATE(0, "hdmiphy_peri", "hdmiphy", 4, 2), + GATE(SCLK_SDMMC, "clk_mmc0_src", "clk_sdmmc_c", 4, 3), + GATE(SCLK_SDIO, "clk_sdio_src", "clk_sdio_c", 4, 4), + GATE(SCLK_EMMC, "clk_emmc_src", "clk_emmc_c", 4, 5), + GATE(SCLK_REF_USB3OTG_SRC, "clk_ref_usb3otg_src", "clk_ref_usb3otg_src_c", 4, 6), + GATE(SCLK_USB3OTG_REF, "clk_usb3_otg0_ref", "xin24m", 4, 7), + GATE(SCLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", "clk_usb3otg_suspend_c", 4, 8), + /* Bit 9 clk_usb3phy_ref_25m_en */ + GATE(SCLK_SDMMC_EXT, "clk_sdmmc_ext", "clk_sdmmc_ext_c", 4, 10), + /* Bit 11-15 unused */ + + /* CRU_CLKGATE_CON5 */ + GATE(ACLK_RGA_PRE, "aclk_rga_pre", "aclk_rga_pre_c", 5, 0), + GATE(SCLK_RGA, "sclk_rga", "sclk_rga_c", 5, 0), + GATE(ACLK_VIO_PRE, "aclk_vio_pre", "aclk_vio_pre_c", 5, 2), + GATE(SCLK_CIF_OUT, "clk_cif_src", "clk_cif_src_c", 5, 3), + GATE(SCLK_HDMI_SFC, "clk_hdmi_sfc", "xin24m", 5, 4), + GATE(ACLK_VOP_PRE, "aclk_vop_pre", "aclk_vop_pre_c", 5, 5), + GATE(DCLK_LCDC_SRC, "vop_dclk_src", "vop_dclk_src_c", 5, 6), + /* Bit 7-15 unused */ + + /* CRU_CLKGATE_CON6 */ + GATE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", "aclk_rkvdec_c", 6, 0), + GATE(SCLK_VDEC_CABAC, "sclk_cabac", "sclk_cabac_c", 6, 1), + GATE(SCLK_VDEC_CORE, "sclk_vdec_core", "sclk_vdec_core_c", 6, 2), + GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_c", 6, 3), + GATE(SCLK_VENC_CORE, "sclk_venc", "sclk_venc_c", 6, 4), + GATE(ACLK_VPU_PRE, "aclk_vpu_pre", "aclk_vpu_pre_c", 6, 5), + GATE(0, "aclk_gpu_pre", "aclk_gpu_pre_c", 6, 6), + GATE(SCLK_VENC_DSP, "sclk_venc_dsp", "sclk_venc_dsp_c", 6, 7), + /* Bit 8-15 unused */ + + /* CRU_CLKGATE_CON7 */ + /* Bit 0 aclk_core_en */ + /* Bit 1 clk_core_periph_en */ + /* Bit 2 clk_jtag_en */ + /* Bit 3 unused */ + /* Bit 4 pclk_ddr_en */ + /* Bit 5-15 unused */ + + /* CRU_CLKGATE_CON8 */ + GATE(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_pre_c", 8, 0), + GATE(HCLK_BUS_PRE, "hclk_bus_pre", "hclk_bus_pre_c", 8, 1), + GATE(PCLK_BUS_PRE, "pclk_bus_pre", "pclk_bus_pre_c", 8, 2), + GATE(0, "pclk_bus", "pclk_bus_pre", 8, 3), + GATE(0, "pclk_phy", "pclk_bus_pre", 8, 4), + GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 8, 5), + GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 8, 6), + GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 8, 7), + GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 8, 8), + GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 8, 9), + GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 8, 10), + /* Bit 11-15 unused */ + + /* CRU_CLKGATE_CON9 */ + GATE(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 9, 0), + GATE(SCLK_MAC2PHY_RXTX, "clk_gmac2phy_rx", "clk_mac2phy", 9, 1), + GATE(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy_out_c", 9, 2), + GATE(SCLK_MAC2PHY_REF, "clk_gmac2phy_ref", "clk_mac2phy", 9, 3), + GATE(SCLK_MAC2IO_RX, "clk_gmac2io_rx", "clk_mac2io", 9, 4), + GATE(SCLK_MAC2IO_TX, "clk_gmac2io_tx", "clk_mac2io", 9, 5), + GATE(SCLK_MAC2IO_REFOUT, "clk_gmac2io_refout", "clk_mac2io", 9, 6), + GATE(SCLK_MAC2IO_REF, "clk_gmac2io_ref", "clk_mac2io", 9, 7), + /* Bit 8-15 unused */ + + /* CRU_CLKGATE_CON10 */ + GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 10, 0), + GATE(HCLK_PERI, "hclk_peri", "hclk_peri_c", 10, 1), + GATE(PCLK_PERI, "pclk_peri", "pclk_peri_c", 10, 2), + /* Bit 3-15 unused */ + + /* CRU_CLKGATE_CON11 */ + GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 11, 0), + /* Bit 1-3 unused */ + GATE(HCLK_RKVENC, "hclk_rkvenc", "aclk_rkvenc", 11, 4), + /* Bit 5-7 unused */ + GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 11, 8), + /* Bit 9-15 unused */ + + /* CRU_CLKGATE_CON12 */ + /* unused */ + + /* CRU_CLKGATE_CON13 */ + /* Bit 0 aclk_core_niu_en */ + /* Bit 1 aclk_gic400_en */ + /* Bit 2-15 unused */ + + /* CRU_CLKGATE_CON14 */ + GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 14, 0), + GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 14, 1), + /* Bit 2-15 unused */ + + /* CRU_CLKGATE_CON15*/ + /* Bit 0 aclk_intmem_en Unused */ + /* Bit 1 aclk_dmac_bus_en Unused */ + /* Bit 2 hclk_rom_en Unused */ + GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 15, 3), + GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 15, 4), + GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 15, 5), + GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_bus_pre", 15, 6), + GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 15, 7), + GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 15, 8), + GATE(0, "pclk_efuse", "pclk_bus", 15, 9), + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 15, 10), + GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 15, 11), + GATE(0, "aclk_bus_niu", "aclk_bus_pre", 15, 12), + GATE(0, "hclk_bus_niu", "hclk_bus_pre", 15, 13), + GATE(0, "pclk_bus_niu", "pclk_bus_pre", 15, 14), + GATE(0, "pclk_phy_niu", "pclk_phy", 15, 14), + /* Bit 15 pclk_phy_niu_en */ + + /* CRU_CLKGATE_CON16 */ + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 16, 0), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 16, 1), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 16, 2), + GATE(PCLK_TIMER, "pclk_timer0", "pclk_bus", 16, 3), + GATE(0, "pclk_stimer", "pclk_bus", 16, 4), + GATE(PCLK_SPI, "pclk_spi", "pclk_bus", 16, 5), + GATE(PCLK_PWM, "pclk_pwm", "pclk_bus", 16, 6), + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 16, 7), + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 16, 8), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 16, 9), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 16, 10), + GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 16, 11), + GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 16, 12), + GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 16, 13), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 16, 14), + GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 16, 15), + + /* CRU_CLKGATE_CON17 */ + GATE(PCLK_GRF, "pclk_grf", "pclk_bus", 17, 0), + /* Bit 1 unused */ + GATE(PCLK_USB3_GRF, "pclk_usb3grf", "pclk_phy", 17, 2), + GATE(0, "pclk_ddrphy", "pclk_phy", 17, 3), + GATE(0, "pclk_cru", "pclk_bus", 17, 4), + GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy", 17, 5), + GATE(0, "pclk_sgrf", "pclk_bus", 17, 6), + GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy", 17, 7), + GATE(0, "pclk_vdacphy", "pclk_bus", 17, 8), + /* Bit 9 unused */ + GATE(0, "pclk_sim", "pclk_bus", 17, 10), + GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 17, 11), + GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 17, 12), + /* Bit 13 clk_hsadc_0_tsp_en Depend on a gpio clock ? */ + GATE(PCLK_USB2_GRF, "pclk_usb2grf", "pclk_phy", 17, 14), + GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 17, 15), + + /* CRU_CLKGATE_CON18 */ + /* Bit 0 unused */ + /* Bit 1 pclk_ddr_upctl_en */ + /* Bit 2 pclk_ddr_msch_en */ + /* Bit 3 pclk_ddr_mon_en */ + /* Bit 4 aclk_ddr_upctl_en */ + /* Bit 5 clk_ddr_upctl_en */ + /* Bit 6 clk_ddr_msch_en */ + /* Bit 7 pclk_ddrstdby_en */ + /* Bit 8-15 unused */ + + /* CRU_CLKGATE_CON19 */ + GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 19, 0), + GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 19, 1), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 19, 2), + /* Bit 3-5 unused */ + GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 19, 6), + GATE(HCLK_HOST0_ARB, "hclk_host0_arg", "hclk_peri", 19, 7), + GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 19, 8), + GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 19, 9), + /* Bit 10 unused */ + GATE(0, "aclk_peri_niu", "aclk_peri", 19, 11), + GATE(0, "hclk_peri_niu", "hclk_peri", 19, 12), + GATE(0, "pclk_peri_niu", "hclk_peri", 19, 13), + GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 19, 14), + GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 19, 15), + + /* CRU_CLKGATE_CON20 */ + /* unused */ + + /* CRU_CLKGATE_CON21 */ + /* Bit 0-1 unused */ + GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 21, 2), + GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 21, 3), + GATE(0, "aclk_vop_niu", "aclk_vop_pre", 21, 4), + GATE(0, "hclk_vop_niu", "hclk_vio_pre", 21, 5), + GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 21, 6), + GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 21, 7), + GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 21, 8), + GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 21, 9), + GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 21, 10), + GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 21, 11), + GATE(0, "hclk_ahb1tom", "hclk_vio_pre", 21, 12), + GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 21, 13), + GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 21, 14), + GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 21, 15), + + /* CRU_CLKGATE_CON22 */ + GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 22, 0), + GATE(0, "hclk_vio_niu", "hclk_vio_pre", 22, 1), + GATE(0, "aclk_vio_niu", "aclk_vio_pre", 22, 2), + GATE(0, "aclk_rga_niu", "aclk_rga_pre", 22, 3), + GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 22, 4), + GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 22, 5), + /* Bit 6-15 unused */ + + /* CRU_CLKGATE_CON23 */ + GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 23, 0), + GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 23, 1), + GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 23, 2), + GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 23, 3), + /* Bit 4-15 unused */ + + /* CRU_CLKGATE_CON24 */ + GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 24, 0), + GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 24, 1), + GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", 24, 2), + GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", 24, 3), + /* Bit 4-15 unused */ + + /* CRU_CLKGATE_CON25 */ + GATE(0, "aclk_rkvenc_niu", "aclk_rkvenc", 25, 0), + GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 25, 1), + GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 25, 2), + GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 25, 3), + GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 25, 4), + GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 25, 5), + GATE(0, "aclk_axisram", "hclk_rkvenc", 25, 6), + /* Bit 7-15 unused */ + + /* CRU_CLKGATE_CON26 */ + GATE(ACLK_MAC2PHY, "aclk_gmac2phy", "aclk_gmac", 26, 0), + GATE(PCLK_MAC2PHY, "pclk_gmac2phy", "pclk_gmac", 26, 1), + GATE(ACLK_MAC2IO, "aclk_gmac2io", "aclk_gmac", 26, 2), + GATE(PCLK_MAC2IO, "pclk_gmac2io", "pclk_gmac", 26, 3), + GATE(0, "aclk_gmac_niu", "aclk_gmac", 26, 4), + GATE(0, "pclk_gmac_niu", "pclk_gmac", 26, 5), + /* Bit 6-15 unused */ + + /* CRU_CLKGATE_CON27 */ + /* Bit 0 clk_ddrphy_en */ + /* Bit 1 clk4x_ddrphy_en */ + + /* CRU_CLKGATE_CON28 */ + GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 28, 0), + GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy", 28, 1), + GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy", 28, 2), + GATE(0, "pclk_pmu", "pclk_bus", 28, 3), + GATE(0, "pclk_otp", "pclk_bus", 28, 4) + /* Bit 5-15 unused */ +}; + +/* + * PLLs + */ + +#define PLL_RATE(_hz, _ref, _fb, _post1, _post2, _dspd, _frac) \ +{ \ + .freq = _hz, \ + .refdiv = _ref, \ + .fbdiv = _fb, \ + .postdiv1 = _post1, \ + .postdiv2 = _post2, \ + .dsmpd = _dspd, \ + .frac = _frac, \ +} + +static struct rk_clk_pll_rate rk3328_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), + PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), + PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), + PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), + PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), + PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), + PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), + PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), + PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), + PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), + PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), + PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), + PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), + PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), + PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), + PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), + PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), + PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), + PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), + PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), + PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), + PLL_RATE(984000000, 1, 82, 2, 1, 1, 0), + PLL_RATE(960000000, 1, 80, 2, 1, 1, 0), + PLL_RATE(936000000, 1, 78, 2, 1, 1, 0), + PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), + PLL_RATE(900000000, 4, 300, 2, 1, 1, 0), + PLL_RATE(888000000, 1, 74, 2, 1, 1, 0), + PLL_RATE(864000000, 1, 72, 2, 1, 1, 0), + PLL_RATE(840000000, 1, 70, 2, 1, 1, 0), + PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + PLL_RATE(800000000, 6, 400, 2, 1, 1, 0), + PLL_RATE(700000000, 6, 350, 2, 1, 1, 0), + PLL_RATE(696000000, 1, 58, 2, 1, 1, 0), + PLL_RATE(600000000, 1, 75, 3, 1, 1, 0), + PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), + PLL_RATE(504000000, 1, 63, 3, 1, 1, 0), + PLL_RATE(500000000, 6, 250, 2, 1, 1, 0), + PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), + PLL_RATE(312000000, 1, 52, 2, 2, 1, 0), + PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), + PLL_RATE(96000000, 1, 64, 4, 4, 1, 0), + {}, +}; + +static struct rk_clk_pll_rate rk3328_pll_frac_rates[] = { + PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217), + PLL_RATE(983040000, 24, 983, 1, 1, 0, 671088), + PLL_RATE(491520000, 24, 983, 2, 1, 0, 671088), + PLL_RATE(61440000, 6, 215, 7, 2, 0, 671088), + PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797894), + PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066329), + {}, +}; + +/* Clock parents */ +PLIST(pll_src_p) = {"xin24m"}; +PLIST(xin24m_rtc32k_p) = {"xin24m", "clk_rtc32k"}; + +PLIST(pll_src_cpll_gpll_p) = {"cpll", "gpll"}; +PLIST(pll_src_cpll_gpll_apll_p) = {"cpll", "gpll", "apll"}; +PLIST(pll_src_cpll_gpll_xin24m_p) = {"cpll", "gpll", "xin24m", "xin24m" /* Dummy */}; +PLIST(pll_src_cpll_gpll_usb480m_p) = {"cpll", "gpll", "usb480m"}; +PLIST(pll_src_cpll_gpll_hdmiphy_p) = {"cpll", "gpll", "hdmi_phy"}; +PLIST(pll_src_cpll_gpll_hdmiphy_usb480m_p) = {"cpll", "gpll", "hdmi_phy", "usb480m"}; +PLIST(pll_src_apll_gpll_dpll_npll_p) = {"apll", "gpll", "dpll", "npll"}; +PLIST(pll_src_cpll_gpll_xin24m_usb480m_p) = {"cpll", "gpll", "xin24m", "usb480m"}; +PLIST(mux_ref_usb3otg_p) = { "xin24m", "clk_usb3_otg0_ref" }; +PLIST(mux_mac2io_p) = { "clk_mac2io_src", "gmac_clkin" }; +PLIST(mux_mac2io_ext_p) = { "clk_mac2io", "gmac_clkin" }; +PLIST(mux_mac2phy_p) = { "clk_mac2phy_src", "phy_50m_out" }; +PLIST(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac", "xin12m", "xin12m" }; +PLIST(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac", "clkin_i2s1", "xin12m" }; +PLIST(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac", "clkin_i2s2", "xin12m" }; +PLIST(mux_dclk_lcdc_p) = {"hdmiphy", "vop_dclk_src"}; +PLIST(mux_hdmiphy_p) = {"hdmi_phy", "xin24m"}; +PLIST(mux_usb480m_p) = {"usb480m_phy", "xin24m"}; +PLIST(mux_uart0_p) = {"clk_uart0_div", "clk_uart0_frac", "xin24m", "xin24m"}; +PLIST(mux_uart1_p) = {"clk_uart1_div", "clk_uart1_frac", "xin24m", "xin24m"}; +PLIST(mux_uart2_p) = {"clk_uart2_div", "clk_uart2_frac", "xin24m", "xin24m"}; +PLIST(mux_spdif_p) = {"clk_spdif_div", "clk_spdif_frac", "xin12m", "xin12m"}; +PLIST(mux_cif_p) = {"clk_cif_pll", "xin24m"}; + +static struct rk_clk_pll_def apll = { + .clkdef = { + .id = PLL_APLL, + .name = "apll", + .parent_names = pll_src_p, + .parent_cnt = nitems(pll_src_p), + }, + .base_offset = 0x00, + .gate_offset = 0x200, + .gate_shift = 0, + .mode_reg = 0x80, + .mode_shift = 1, + .flags = RK_CLK_PLL_HAVE_GATE, + .frac_rates = rk3328_pll_frac_rates, +}; + +static struct rk_clk_pll_def dpll = { + .clkdef = { + .id = PLL_DPLL, + .name = "dpll", + .parent_names = pll_src_p, + .parent_cnt = nitems(pll_src_p), + }, + .base_offset = 0x20, + .gate_offset = 0x200, + .gate_shift = 1, + .mode_reg = 0x80, + .mode_shift = 4, + .flags = RK_CLK_PLL_HAVE_GATE, +}; + +static struct rk_clk_pll_def cpll = { + .clkdef = { + .id = PLL_CPLL, + .name = "cpll", + .parent_names = pll_src_p, + .parent_cnt = nitems(pll_src_p), + }, + .base_offset = 0x40, + .mode_reg = 0x80, + .mode_shift = 8, + .rates = rk3328_pll_rates, +}; + +static struct rk_clk_pll_def gpll = { + .clkdef = { + .id = PLL_GPLL, + .name = "gpll", + .parent_names = pll_src_p, + .parent_cnt = nitems(pll_src_p), + }, + .base_offset = 0x60, + .gate_offset = 0x200, + .gate_shift = 2, + .mode_reg = 0x80, + .mode_shift = 12, + .flags = RK_CLK_PLL_HAVE_GATE, + .frac_rates = rk3328_pll_frac_rates, +}; + +static struct rk_clk_pll_def npll = { + .clkdef = { + .id = PLL_NPLL, + .name = "npll", + .parent_names = pll_src_p, + .parent_cnt = nitems(pll_src_p), + }, + .base_offset = 0xa0, + .gate_offset = 0x200, + .gate_shift = 12, + .mode_reg = 0x80, + .mode_shift = 1, + .flags = RK_CLK_PLL_HAVE_GATE, + .rates = rk3328_pll_rates, +}; + +static struct rk_clk_armclk_rates rk3328_armclk_rates[] = { + { + .freq = 1296000000, + .div = 1, + }, + { + .freq = 1200000000, + .div = 1, + }, + { + .freq = 1104000000, + .div = 1, + }, + { + .freq = 1008000000, + .div = 1, + }, + { + .freq = 912000000, + .div = 1, + }, + { + .freq = 816000000, + .div = 1, + }, + { + .freq = 696000000, + .div = 1, + }, + { + .freq = 600000000, + .div = 1, + }, + { + .freq = 408000000, + .div = 1, + }, + { + .freq = 312000000, + .div = 1, + }, + { + .freq = 216000000, + .div = 1, + }, + { + .freq = 96000000, + .div = 1, + }, +}; + +static struct rk_clk_armclk_def armclk = { + .clkdef = { + .id = ARMCLK, + .name = "armclk", + .parent_names = pll_src_apll_gpll_dpll_npll_p, + .parent_cnt = nitems(pll_src_apll_gpll_dpll_npll_p), + }, + .muxdiv_offset = 0x100, + .mux_shift = 6, + .mux_width = 2, + + .div_shift = 0, + .div_width = 5, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX, + .main_parent = 3, /* npll */ + .alt_parent = 0, /* apll */ + + .rates = rk3328_armclk_rates, + .nrates = nitems(rk3328_armclk_rates), +}; + +static struct rk_clk rk3328_clks[] = { + /* External clocks */ + LINK("xin24m"), + LINK("gmac_clkin"), + LINK("hdmi_phy"), + LINK("usb480m_phy"), + FRATE(0, "xin12m", 12000000), + FRATE(0, "phy_50m_out", 50000000), + FRATE(0, "clkin_i2s1", 0), + FRATE(0, "clkin_i2s2", 0), + + /* PLLs */ + { + .type = RK3328_CLK_PLL, + .clk.pll = &apll + }, + { + .type = RK3328_CLK_PLL, + .clk.pll = &dpll + }, + { + .type = RK3328_CLK_PLL, + .clk.pll = &cpll + }, + { + .type = RK3328_CLK_PLL, + .clk.pll = &gpll + }, + { + .type = RK3328_CLK_PLL, + .clk.pll = &npll + }, + + { + .type = RK_CLK_ARMCLK, + .clk.armclk = &armclk, + }, + + /* CRU_CRU_MISC */ + MUXRAW(HDMIPHY, "hdmiphy", mux_hdmiphy_p, 0, 0x84, 13, 1), + MUXRAW(USB480M, "usb480m", mux_usb480m_p, 0, 0x84, 15, 1), + + /* CRU_CLKSEL_CON0 */ + /* COMP clk_core_div_con core_clk_pll_sel */ + COMP(0, "aclk_bus_pre_c", pll_src_cpll_gpll_hdmiphy_p, 0, 0, 8, 5, 13, 2), + + /* CRU_CLKSEL_CON1 */ + /* CDIV clk_core_dbg_div_con */ + /* CDIV aclk_core_div_con */ + CDIV(0, "hclk_bus_pre_c", "aclk_bus_pre", 0, 1, 8, 2), + CDIV(0, "pclk_bus_pre_c", "aclk_bus_pre", 0, 1, 12, 2), + + /* CRU_CLKSEL_CON2 */ + /* CDIV test_div_con */ + /* CDIV func_24m_div_con */ + + /* CRU_CLKSEL_CON3 */ + /* COMP ddr_div_cnt ddr_clk_pll_sel */ + + /* CRU_CLKSEL_CON4 */ + COMP(0, "clk_otp_c", pll_src_cpll_gpll_xin24m_p, 0, 4, 0, 6, 6, 2), + /* COMP pd_ddr_div_con ddrpdclk_clk_pll_sel */ + + /* CRU_CLKSEL_CON5 */ + COMP(0, "clk_efuse_c", pll_src_cpll_gpll_xin24m_p, 0, 5, 8, 5, 14, 2), + + /* CRU_CLKSEL_CON6 */ + MUX(0, "clk_i2s0_mux", mux_i2s0_p, RK_CLK_MUX_REPARENT, 6, 8, 2), + COMP(0, "clk_i2s0_div_c", pll_src_cpll_gpll_p, 0, 6, 0, 7, 15, 1), + + /* CRU_CLKSEL_CON7 */ + FRACT(0, "clk_i2s0_frac_f", "clk_i2s0_div", 0, 7), + + /* CRU_CLKSEL_CON8 */ + MUX(0, "clk_i2s1_mux", mux_i2s1_p, RK_CLK_MUX_REPARENT, 8, 8, 2), + COMP(0, "clk_i2s1_div_c", pll_src_cpll_gpll_p, 0, 8, 0, 7, 15, 1), + /* MUX i2s1_out_sel */ + + /* CRU_CLKSEL_CON9 */ + FRACT(0, "clk_i2s1_frac_f", "clk_i2s1_div", 0, 9), + + /* CRU_CLKSEL_CON10 */ + MUX(0, "clk_i2s2_mux", mux_i2s2_p, RK_CLK_MUX_REPARENT, 10, 8, 2), + COMP(0, "clk_i2s2_div_c", pll_src_cpll_gpll_p, 0, 10, 0, 7, 15, 1), + /* MUX i2s2_out_sel */ + + /* CRU_CLKSEL_CON11 */ + FRACT(0, "clk_i2s2_frac_f", "clk_i2s2_div", 0, 11), + + /* CRU_CLKSEL_CON12 */ + MUX(0, "clk_spdif_pll", pll_src_cpll_gpll_p, 0, 12, 15, 1), + MUX(SCLK_SPDIF, "clk_spdif", mux_spdif_p, 0, 12, 8, 2), + CDIV(0, "clk_spdif_div_c", "clk_spdif_pll", 0, 12, 0, 7), + + /* CRU_CLKSEL_CON13 */ + FRACT(0, "clk_spdif_frac_f", "clk_spdif", 0, 13), + + /* CRU_CLKSEL_CON14 */ + MUX(0, "clk_uart0_pll", pll_src_cpll_gpll_usb480m_p, 0, 14, 12, 2), + MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, 0, 14, 8, 2), + CDIV(0, "clk_uart0_div_c", "clk_uart0_pll", 0, 14, 0, 7), + + /* CRU_CLKSEL_CON15 */ + FRACT(0, "clk_uart0_frac_f", "clk_uart0_pll", 0, 15), + + /* CRU_CLKSEL_CON16 */ + MUX(0, "clk_uart1_pll", pll_src_cpll_gpll_usb480m_p, 0, 16, 12, 2), + MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, 0, 16, 8, 2), + CDIV(0, "clk_uart1_div_c", "clk_uart1_pll", 0, 16, 0, 7), + + /* CRU_CLKSEL_CON17 */ + FRACT(0, "clk_uart1_frac_f", "clk_uart1_pll", 0, 17), + + /* CRU_CLKSEL_CON18 */ + MUX(0, "clk_uart2_pll", pll_src_cpll_gpll_usb480m_p, 0, 18, 12, 2), + MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, 0, 18, 8, 2), + CDIV(0, "clk_uart2_div_c", "clk_uart2_pll", 0, 18, 0, 7), + + /* CRU_CLKSEL_CON19 */ + FRACT(0, "clk_uart2_frac_f", "clk_uart2_pll", 0, 19), + + /* CRU_CLKSEL_CON20 */ + COMP(0, "clk_pdm_c", pll_src_cpll_gpll_apll_p, 0, 20, 8, 5, 14, 2), + COMP(0, "clk_crypto_c", pll_src_cpll_gpll_p, 0, 20, 0, 5, 7, 1), + + /* CRU_CLKSEL_CON21 */ + COMP(0, "clk_tsp_c", pll_src_cpll_gpll_p, 0, 21, 8, 5, 15, 1), + + /* CRU_CLKSEL_CON22 */ + CDIV(0, "clk_tsadc_c", "xin24m", 0, 22, 0, 10), + + /* CRU_CLKSEL_CON23 */ + CDIV(0, "clk_saradc_c", "xin24m", 0, 23, 0, 10), + + /* CRU_CLKSEL_CON24 */ + COMP(0, "clk_pwm_c", pll_src_cpll_gpll_p, 0, 24, 8, 7, 15, 1), + COMP(0, "clk_spi_c", pll_src_cpll_gpll_p, 0, 24, 0, 7, 7, 1), + + /* CRU_CLKSEL_CON25 */ + COMP(0, "aclk_gmac_c", pll_src_cpll_gpll_p, 0, 35, 0, 5, 6, 2), + CDIV(0, "pclk_gmac_c", "pclk_gmac", 0, 25, 8, 3), + + /* CRU_CLKSEL_CON26 */ + CDIV(0, "clk_mac2phy_out_c", "clk_mac2phy", 0, 26, 8, 2), + COMP(0, "clk_mac2phy_src_c", pll_src_cpll_gpll_p, 0, 26, 0, 5, 7, 1), + + /* CRU_CLKSEL_CON27 */ + COMP(0, "clk_mac2io_src_c", pll_src_cpll_gpll_p, 0, 27, 0, 5, 7, 1), + COMP(0, "clk_mac2io_out_c", pll_src_cpll_gpll_p, 0, 27, 8, 5, 15, 1), + + /* CRU_CLKSEL_CON28 */ + COMP(ACLK_PERI_PRE, "aclk_peri_pre", pll_src_cpll_gpll_hdmiphy_p, 0, 28, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON29 */ + CDIV(0, "pclk_peri_c", "aclk_peri_pre", 0, 29, 0, 2), + CDIV(0, "hclk_peri_c", "aclk_peri_pre", 0, 29, 4, 3), + + /* CRU_CLKSEL_CON30 */ + COMP(0, "clk_sdmmc_c", pll_src_cpll_gpll_xin24m_usb480m_p, 0, 30, 0, 8, 8, 2), + + /* CRU_CLKSEL_CON31 */ + COMP(0, "clk_sdio_c", pll_src_cpll_gpll_xin24m_usb480m_p, 0, 31, 0, 8, 8, 2), + + /* CRU_CLKSEL_CON32 */ + COMP(0, "clk_emmc_c", pll_src_cpll_gpll_xin24m_usb480m_p, 0, 32, 0, 8, 8, 2), + + /* CRU_CLKSEL_CON33 */ + COMP(0, "clk_usb3otg_suspend_c", xin24m_rtc32k_p, 0, 33, 0, 10, 15, 1), + + /* CRU_CLKSEL_CON34 */ + COMP(0, "clk_i2c0_c", pll_src_cpll_gpll_p, 0, 34, 0, 7, 7, 1), + COMP(0, "clk_i2c1_c", pll_src_cpll_gpll_p, 0, 34, 8, 7, 15, 1), + + /* CRU_CLKSEL_CON35 */ + COMP(0, "clk_i2c2_c", pll_src_cpll_gpll_p, 0, 35, 0, 7, 7, 1), + COMP(0, "clk_i2c3_c", pll_src_cpll_gpll_p, 0, 35, 8, 7, 15, 1), + + /* CRU_CLKSEL_CON36 */ + COMP(0, "aclk_rga_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 36, 8, 5, 14, 2), + COMP(0, "sclk_rga_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 36, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON37 */ + COMP(0, "aclk_vio_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 37, 0, 5, 6, 2), + CDIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_vio_pre", 0, 37, 8, 5), + + /* CRU_CLKSEL_CON38 */ + COMP(0, "clk_rtc32k_c", pll_src_cpll_gpll_xin24m_p, 0, 38, 0, 14, 14, 2), + + /* CRU_CLKSEL_CON39 */ + COMP(0, "aclk_vop_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 39, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON40 */ + COMP(0, "vop_dclk_src_c", pll_src_cpll_gpll_p, 0, 40, 8, 8, 0, 1), + CDIV(DCLK_HDMIPHY, "hdmiphy_div", "vop_dclk_src", 0, 40, 3, 3), + /* MUX vop_dclk_frac_sel */ + MUX(DCLK_LCDC, "vop_dclk", mux_dclk_lcdc_p, 0, 40, 1, 1), + + /* CRU_CLKSEL_CON41 */ + /* FRACT dclk_vop_frac_div_con */ + + /* CRU_CLKSEL_CON42 */ + MUX(0, "clk_cif_pll", pll_src_cpll_gpll_p, 0, 42, 7, 1), + COMP(0, "clk_cif_src_c", mux_cif_p, 0, 42, 0, 5, 5, 1), + + /* CRU_CLKSEL_CON43 */ + COMP(0, "clk_sdmmc_ext_c", pll_src_cpll_gpll_xin24m_usb480m_p, 0, 43, 0, 8, 8, 2), + + /* CRU_CLKSEL_CON44 */ + COMP(0, "aclk_gpu_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 44, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON45 */ + MUX(SCLK_REF_USB3OTG, "clk_ref_usb3otg", mux_ref_usb3otg_p, 0, 45, 8, 1), + COMP(0, "clk_ref_usb3otg_src_c", pll_src_cpll_gpll_p, 0, 45, 0, 7, 7, 1), + + /* CRU_CLKSEL_CON46 */ + /* Unused */ + + /* CRU_CLKSEL_CON47 */ + /* Unused */ + + /* CRU_CLKSEL_CON48 */ + COMP(0, "sclk_cabac_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 48, 8, 5, 14, 2), + COMP(0, "aclk_rkvdec_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 48, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON49 */ + COMP(0, "sclk_vdec_core_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 49, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON50 */ + COMP(0, "aclk_vpu_pre_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 50, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON51 */ + COMP(0, "sclk_venc_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 51, 8, 5, 14, 2), + COMP(0, "aclk_rkvenc_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 51, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON52 */ + COMP(0, "sclk_venc_dsp_c", pll_src_cpll_gpll_hdmiphy_usb480m_p, 0, 51, 8, 5, 14, 2), + COMP(0, "sclk_wifi_c", pll_src_cpll_gpll_usb480m_p, 0, 51, 0, 6, 6, 2), + + /* GRF_SOC_CON4 */ + MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, 0, RK3328_GRF_SOC_CON4, 14, 1), + + /* GRF_MAC_CON1 */ + MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_p, 0, RK3328_GRF_MAC_CON1, 10, 1), + + /* GRF_MAC_CON2 */ + MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_p, 0, RK3328_GRF_MAC_CON2, 10, 1), + + /* + * This clock is controlled in the secure world + */ + FFACT(PCLK_WDT, "pclk_wdt", "pclk_bus", 1, 1), +}; + +static int +rk3328_cru_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_is_compatible(dev, "rockchip,rk3328-cru")) { + device_set_desc(dev, "Rockchip RK3328 Clock and Reset Unit"); + return (BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static int +rk3328_cru_attach(device_t dev) +{ + struct rk_cru_softc *sc; + + sc = device_get_softc(dev); + sc->dev = dev; + + sc->gates = rk3328_gates; + sc->ngates = nitems(rk3328_gates); + + sc->clks = rk3328_clks; + sc->nclks = nitems(rk3328_clks); + + sc->reset_offset = 0x300; + sc->reset_num = 184; + + return (rk_cru_attach(dev)); +} + +static device_method_t rk3328_cru_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, rk3328_cru_probe), + DEVMETHOD(device_attach, rk3328_cru_attach), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(rk3328_cru, rk3328_cru_driver, rk3328_cru_methods, + sizeof(struct rk_cru_softc), rk_cru_driver); + +EARLY_DRIVER_MODULE(rk3328_cru, simplebus, rk3328_cru_driver, 0, 0, + BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); diff --git a/sys/dev/clk/rockchip/rk3399_cru.c b/sys/dev/clk/rockchip/rk3399_cru.c new file mode 100644 index 000000000000..45d6592ceb73 --- /dev/null +++ b/sys/dev/clk/rockchip/rk3399_cru.c @@ -0,0 +1,1270 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org> + * Copyright (c) 2018 Val Packett <val@packett.cool> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <machine/bus.h> + +#include <dev/fdt/simplebus.h> + +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> + +#include <dev/extres/clk/clk_div.h> +#include <dev/extres/clk/clk_fixed.h> +#include <dev/extres/clk/clk_mux.h> + +#include <dev/clk/rockchip/rk_cru.h> + +#include <dev/clk/rockchip/rk3399_cru_dt.h> + +#define CRU_CLKSEL_CON(x) (0x100 + (x) * 0x4) +#define CRU_CLKGATE_CON(x) (0x300 + (x) * 0x4) + +/* GATES */ + +static struct rk_cru_gate rk3399_gates[] = { + /* CRU_CLKGATE_CON0 */ + /* 15-8 unused */ + GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0, 7), + GATE(0, "pclk_dbg_core_l", "pclk_dbg_core_l_c", 0, 6), + GATE(0, "atclk_core_l", "atclk_core_l_c", 0, 5), + GATE(0, "aclkm_core_l", "aclkm_core_l_c", 0, 4), + GATE(0, "clk_core_l_gpll_src", "gpll", 0, 3), + GATE(0, "clk_core_l_dpll_src", "dpll", 0, 2), + GATE(0, "clk_core_l_bpll_src", "bpll", 0, 1), + GATE(0, "clk_core_l_lpll_src", "lpll", 0, 0), + + /* CRU_CLKGATE_CON1 */ + /* 15 - 8 unused */ + GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 1, 7), + GATE(0, "pclk_dbg_core_b","pclk_dbg_core_b_c", 1, 6), + GATE(0, "atclk_core_b", "atclk_core_b_c", 1, 5), + GATE(0, "aclkm_core_b", "aclkm_core_b_c", 1, 4), + GATE(0, "clk_core_b_gpll_src", "gpll", 1, 3), + GATE(0, "clk_core_b_dpll_src", "dpll", 1, 2), + GATE(0, "clk_core_b_bpll_src", "bpll", 1, 1), + GATE(0, "clk_core_b_lpll_src", "lpll", 1, 0), + + /* CRU_CLKGATE_CON2 */ + /* 15 - 11 unused */ + GATE(0, "npll_cs", "npll", 2, 10), + GATE(0, "gpll_cs", "gpll", 2, 9), + GATE(0, "cpll_cs", "cpll", 2, 8), + GATE(SCLK_CCI_TRACE, "clk_cci_trace", "clk_cci_trace_c", 2, 7), + GATE(0, "gpll_cci_trace", "gpll", 2, 6), + GATE(0, "cpll_cci_trace", "cpll", 2, 5), + GATE(0, "aclk_cci_pre", "aclk_cci_pre_c", 2, 4), + GATE(0, "vpll_aclk_cci_src", "vpll", 2, 3), + GATE(0, "npll_aclk_cci_src", "npll", 2, 2), + GATE(0, "gpll_aclk_cci_src", "gpll", 2, 1), + GATE(0, "cpll_aclk_cci_src", "cpll", 2, 0), + + /* CRU_CLKGATE_CON3 */ + /* 15 - 8 unused */ + GATE(0, "aclk_center", "aclk_center_c", 3, 7), + /* 6 unused */ + /* 5 unused */ + GATE(PCLK_DDR, "pclk_ddr", "pclk_ddr_c", 3, 4), + GATE(0, "clk_ddrc_gpll_src", "gpll", 3, 3), + GATE(0, "clk_ddrc_dpll_src", "dpll", 3, 2), + GATE(0, "clk_ddrc_bpll_src", "bpll", 3, 1), + GATE(0, "clk_ddrc_lpll_src", "lpll", 3, 0), + + /* CRU_CLKGATE_CON4 */ + /* 15 - 12 unused */ + GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 4, 11), + GATE(0, "clk_rga_core", "clk_rga_core_c", 4, 10), + GATE(0, "hclk_rga_pre", "hclk_rga_pre_c", 4, 9), + GATE(0, "aclk_rga_pre", "aclk_rga_pre_c", 4, 8), + GATE(0, "hclk_iep_pre", "hclk_iep_pre_c", 4, 7), + GATE(0, "aclk_iep_pre", "aclk_iep_pre_c", 4, 6), + GATE(SCLK_VDU_CA, "clk_vdu_ca", "clk_vdu_ca_c", 4, 5), + GATE(SCLK_VDU_CORE, "clk_vdu_core", "clk_vdu_core_c", 4, 4), + GATE(0, "hclk_vdu_pre", "hclk_vdu_pre_c", 4, 3), + GATE(0, "aclk_vdu_pre", "aclk_vdu_pre_c", 4, 2), + GATE(0, "hclk_vcodec_pre", "hclk_vcodec_pre_c", 4, 1), + GATE(0, "aclk_vcodec_pre", "aclk_vcodec_pre_c", 4, 0), + + /* CRU_CLKGATE_CON5 */ + /* 15 - 10 unused */ + GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 5, 9), + GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 5, 8), + GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 5, 7), + GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 5, 6), + GATE(SCLK_MAC, "clk_gmac", "clk_gmac_c", 5, 5), + GATE(PCLK_PERIHP, "pclk_perihp", "pclk_perihp_c", 5, 4), + GATE(HCLK_PERIHP, "hclk_perihp", "hclk_perihp_c", 5, 3), + GATE(ACLK_PERIHP, "aclk_perihp", "aclk_perihp_c", 5, 2), + GATE(0, "cpll_aclk_perihp_src", "cpll", 5, 1), + GATE(0, "gpll_aclk_perihp_src", "gpll", 5, 0), + + /* CRU_CLKGATE_CON6 */ + /* 15 unused */ + GATE(SCLK_EMMC, "clk_emmc", "clk_emmc_c", 6, 14), + GATE(0, "cpll_aclk_emmc_src", "cpll", 6, 13), + GATE(0, "gpll_aclk_emmc_src", "gpll", 6, 12), + GATE(0, "pclk_gmac_pre", "pclk_gmac_pre_c", 6, 11), + GATE(0, "aclk_gmac_pre", "aclk_gmac_pre_c", 6, 10), + GATE(0, "cpll_aclk_gmac_src", "cpll", 6, 9), + GATE(0, "gpll_aclk_gmac_src", "gpll", 6, 8), + /* 7 unused */ + GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", 6, 6), + GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", 6, 5), + GATE(SCLK_HSICPHY, "clk_hsicphy", "clk_hsicphy_c", 6, 4), + GATE(0, "clk_pcie_core_cru", "clk_pcie_core_cru_c", 6, 3), + GATE(SCLK_PCIE_PM, "clk_pcie_pm", "clk_pcie_pm_c", 6, 2), + GATE(SCLK_SDMMC, "clk_sdmmc", "clk_sdmmc_c", 6, 1), + GATE(SCLK_SDIO, "clk_sdio", "clk_sdio_c", 6, 0), + + /* CRU_CLKGATE_CON7 */ + /* 15 - 10 unused */ + GATE(FCLK_CM0S, "fclk_cm0s", "fclk_cm0s_c", 7, 9), + GATE(SCLK_CRYPTO1, "clk_crypto1", "clk_crypto1_c", 7, 8), + GATE(SCLK_CRYPTO0, "clk_crypto0", "clk_crypto0_c", 7, 7), + GATE(0, "cpll_fclk_cm0s_src", "cpll", 7, 6), + GATE(0, "gpll_fclk_cm0s_src", "gpll", 7, 5), + GATE(PCLK_PERILP0, "pclk_perilp0", "pclk_perilp0_c", 7, 4), + GATE(HCLK_PERILP0, "hclk_perilp0", "hclk_perilp0_c", 7, 3), + GATE(ACLK_PERILP0, "aclk_perilp0", "aclk_perilp0_c", 7, 2), + GATE(0, "cpll_aclk_perilp0_src", "cpll", 7, 1), + GATE(0, "gpll_aclk_perilp0_src", "gpll", 7, 0), + + /* CRU_CLKGATE_CON8 */ + GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", 8, 15), + GATE(0, "clk_spdif_frac", "clk_spdif_frac_c", 8, 14), + GATE(0, "clk_spdif_div", "clk_spdif_div_c", 8, 13), + GATE(SCLK_I2S_8CH_OUT, "clk_i2sout", "clk_i2sout_c", 8, 12), + GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", 8, 11), + GATE(0, "clk_i2s2_frac", "clk_i2s2_frac_c", 8, 10), + GATE(0, "clk_i2s2_div", "clk_i2s2_div_c", 8, 9), + GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", 8, 8), + GATE(0, "clk_i2s1_frac", "clk_i2s1_frac_c", 8, 7), + GATE(0, "clk_i2s1_div", "clk_i2s1_div_c", 8, 6), + GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", 8, 5), + GATE(0, "clk_i2s0_frac","clk_i2s0_frac_c", 8, 4), + GATE(0, "clk_i2s0_div","clk_i2s0_div_c", 8, 3), + GATE(PCLK_PERILP1, "pclk_perilp1", "pclk_perilp1_c", 8, 2), + GATE(HCLK_PERILP1, "cpll_hclk_perilp1_src", "cpll", 8, 1), + GATE(0, "gpll_hclk_perilp1_src", "gpll", 8, 0), + + /* CRU_CLKGATE_CON9 */ + GATE(SCLK_SPI4, "clk_spi4", "clk_spi4_c", 9, 15), + GATE(SCLK_SPI2, "clk_spi2", "clk_spi2_c", 9, 14), + GATE(SCLK_SPI1, "clk_spi1", "clk_spi1_c", 9, 13), + GATE(SCLK_SPI0, "clk_spi0", "clk_spi0_c", 9, 12), + GATE(SCLK_SARADC, "clk_saradc", "clk_saradc_c", 9, 11), + GATE(SCLK_TSADC, "clk_tsadc", "clk_tsadc_c", 9, 10), + /* 9 - 8 unused */ + GATE(0, "clk_uart3_frac", "clk_uart3_frac_c", 9, 7), + GATE(0, "clk_uart3_div", "clk_uart3_div_c", 9, 6), + GATE(0, "clk_uart2_frac", "clk_uart2_frac_c", 9, 5), + GATE(0, "clk_uart2_div", "clk_uart2_div_c", 9, 4), + GATE(0, "clk_uart1_frac", "clk_uart1_frac_c", 9, 3), + GATE(0, "clk_uart1_div", "clk_uart1_div_c", 9, 2), + GATE(0, "clk_uart0_frac", "clk_uart0_frac_c", 9, 1), + GATE(0, "clk_uart0_div", "clk_uart0_div_c", 9, 0), + + /* CRU_CLKGATE_CON10 */ + GATE(SCLK_VOP1_PWM, "clk_vop1_pwm", "clk_vop1_pwm_c", 10, 15), + GATE(SCLK_VOP0_PWM, "clk_vop0_pwm", "clk_vop0_pwm_c", 10, 14), + GATE(DCLK_VOP0_DIV, "dclk_vop0_div", "dclk_vop0_div_c", 10, 12), + GATE(DCLK_VOP1_DIV, "dclk_vop1_div", "dclk_vop1_div_c", 10, 13), + GATE(0, "hclk_vop1_pre", "hclk_vop1_pre_c", 10, 11), + GATE(ACLK_VOP1_PRE, "aclk_vop1_pre", "aclk_vop1_pre_c", 10, 10), + GATE(0, "hclk_vop0_pre", "hclk_vop0_pre_c", 10, 9), + GATE(ACLK_VOP0_PRE, "aclk_vop0_pre", "aclk_vop0_pre_c", 10, 8), + GATE(0, "clk_cifout_src", "clk_cifout_src_c", 10, 7), + GATE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", "clk_spdif_rec_dptx_c", 10, 6), + GATE(SCLK_I2C7, "clk_i2c7", "clk_i2c7_c", 10, 5), + GATE(SCLK_I2C3, "clk_i2c3", "clk_i2c3_c", 10, 4), + GATE(SCLK_I2C6, "clk_i2c6", "clk_i2c6_c", 10, 3), + GATE(SCLK_I2C2, "clk_i2c2", "clk_i2c2_c", 10, 2), + GATE(SCLK_I2C5, "clk_i2c5", "clk_i2c5_c", 10, 1), + GATE(SCLK_I2C1, "clk_i2c1", "clk_i2c1_c", 10, 0), + + /* CRU_CLKGATE_CON11 */ + GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 11, 15), + GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 11, 14), + /* 13-12 unused */ + GATE(PCLK_EDP, "pclk_edp", "pclk_edp_c", 11, 11), + GATE(PCLK_HDCP, "pclk_hdcp", "pclk_hdcp_c", 11, 10), + /* 9 unuwsed */ + GATE(SCLK_DP_CORE, "clk_dp_core", "clk_dp_core_c", 11, 8), + GATE(SCLK_HDMI_CEC, "clk_hdmi_cec", "clk_hdmi_cec_c", 11, 7), + GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 11, 6), + GATE(SCLK_ISP1, "clk_isp1", "clk_isp1_c", 11, 5), + GATE(SCLK_ISP0, "clk_isp0", "clk_isp0_c", 11, 4), + GATE(HCLK_HDCP, "hclk_hdcp", "hclk_hdcp_c", 11, 3), + GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_c", 11, 2), + GATE(PCLK_VIO, "pclk_vio", "pclk_vio_c", 11, 1), + GATE(ACLK_VIO, "aclk_vio", "aclk_vio_c", 11, 0), + + /* CRU_CLKGATE_CON12 */ + /* 15 - 14 unused */ + GATE(HCLK_SD, "hclk_sd", "hclk_sd_c", 12, 13), + GATE(ACLK_GIC_PRE, "aclk_gic_pre", "aclk_gic_pre_c", 12, 12), + GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_c", 12, 11), + GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_c", 12, 10), + GATE(HCLK_ISP0, "hclk_isp0", "hclk_isp0_c", 12, 9), + GATE(ACLK_ISP0, "aclk_isp0", "aclk_isp0_c", 12, 8), + /* 7 unused */ + GATE(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "clk_pciephy_ref100m_c", 12, 6), + /* 5 unused */ + GATE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", "clk_usb3otg1_suspend_c", 12, 4), + GATE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", "clk_usb3otg0_suspend_c", 12, 3), + GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 12, 2), + GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 12, 1), + GATE(ACLK_USB3, "aclk_usb3", "aclk_usb3_c", 12, 0), + + /* CRU_CLKGATE_CON13 */ + GATE(SCLK_TESTCLKOUT2, "clk_testout2", "clk_testout2_c", 13, 15), + GATE(SCLK_TESTCLKOUT1, "clk_testout1", "clk_testout1_c", 13, 14), + GATE(SCLK_SPI5, "clk_spi5", "clk_spi5_c", 13, 13), + GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 13, 12), + GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 13, 12), + GATE(0, "clk_test", "clk_test_c", 13, 11), + /* 10 unused */ + GATE(0, "clk_test_frac", "clk_test_frac_c", 13, 9), + /* 8 unused */ + GATE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", "clk_uphy1_tcpdcore_c", 13, 7), + GATE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", "clk_uphy1_tcpdphy_ref_c", 13, 6), + GATE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", "clk_uphy0_tcpdcore_c", 13, 5), + GATE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", "clk_uphy0_tcpdphy_ref_c", 13, 4), + /* 3 - 2 unused */ + GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 13, 1), + GATE(0, "aclk_gpu_pre", "aclk_gpu_pre_c", 13, 0), + + /* CRU_CLKGATE_CON14 */ + /* 15 - 14 unused */ + GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", 14, 13), + GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", 14, 12), + GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", 14, 11), + GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", 14, 10), + GATE(0, "clk_dbg_pd_core_l", "armclkl", 14, 9), + /* 8 - 7 unused */ + GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", 14, 6), + GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", 14, 5), + GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", 14, 4), + GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", 14, 3), + GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", 14, 2), + GATE(0, "clk_dbg_pd_core_b", "armclkb", 14, 1), + /* 0 unused */ + + /* CRU_CLKGATE_CON15 */ + /* 15 - 8 unused */ + GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", 15, 7), + GATE(0, "clk_dbg_noc", "clk_cs", 15, 6), + GATE(0, "clk_dbg_cxcs", "clk_cs", 15, 5), + GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", 15, 4), + GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", 15, 3), + GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", 15, 2), + GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", 15, 1), + GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", 15, 0), + + /* CRU_CLKGATE_CON16 */ + /* 15 - 12 unused */ + GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", 16, 11), + GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 16, 10), + GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", 16, 9), + GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 16, 8), + /* 7 - 4 unused */ + GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", 16, 3), + GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 16, 2), + GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", 16, 1), + GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 16, 0), + + /* CRU_CLKGATE_CON17 */ + /* 15 - 12 unused */ + GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", 17, 11), + GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 17, 10), + GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", 17, 9), + GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 17, 8), + GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", 17, 3), + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 17, 2), + GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", 17, 1), + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 17, 0), + + /* CRU_CLKGATE_CON18 */ + GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", 18, 15), + GATE(0, "clk_ddr_mon_timer", "xin24m", 18, 14), + GATE(0, "clk_ddr_mon", "clk_ddrc_div2", 18, 13), + GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 18, 12), + GATE(0, "clk_ddr_cic", "clk_ddrc_div2", 18, 11), + GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", 18, 10), + GATE(0, "clk_ddrcfg_msch1", "clk_ddrc_div2", 18, 9), + GATE(0, "clk_ddrphy1", "clk_ddrc_div2", 18, 8), + GATE(0, "clk_ddrphy_ctrl1", "clk_ddrc_div2", 18, 7), + GATE(0, "clk_ddrc1", "clk_ddrc_div2", 18, 6), + GATE(0, "clk_ddr1_msch", "clk_ddrc_div2", 18, 5), + GATE(0, "clk_ddrcfg_msch0", "clk_ddrc_div2", 18, 4), + GATE(0, "clk_ddrphy0", "clk_ddrc_div2", 18, 3), + GATE(0, "clk_ddrphy_ctrl0", "clk_ddrc_div2", 18, 2), + GATE(0, "clk_ddrc0", "clk_ddrc_div2", 18, 1), + + /* CRU_CLKGATE_CON19 */ + /* 15 - 3 unused */ + GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", 19, 2), + GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", 19, 1), + GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", 19, 0), + + /* CRU_CLKGATE_CON20 */ + GATE(0, "hclk_ahb1tom", "hclk_perihp", 20, 15), + GATE(0, "pclk_perihp_noc", "pclk_perihp", 20, 14), + GATE(0, "hclk_perihp_noc", "hclk_perihp", 20, 13), + GATE(0, "aclk_perihp_noc", "aclk_perihp", 20, 12), + GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 20, 11), + GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 20, 10), + GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 20, 9), + GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 20, 8), + GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 20, 7), + GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 20, 6), + GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 20, 5), + GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", 20, 4), + GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 20, 2), + /* 1 - 0 unused */ + + /* CRU_CLKGATE_CON21 */ + /* 15 - 10 unused */ + GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", 21, 9), + GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", 21, 8), + /* 7 unused */ + GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", 21, 6), + GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", 21, 5), + GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", 21, 4), + GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", 21, 3), + GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", 21, 2), + GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", 21, 1), + GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", 21, 0), + + /* CRU_CLKGATE_CON22 */ + GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 22, 15), + GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 22, 14), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 22, 13), + GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 22, 12), + GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 22, 11), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_perilp1", 22, 10), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_perilp1", 22, 9), + GATE(PCLK_I2C6, "pclk_i2c6", "pclk_perilp1", 22, 8), + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_perilp1", 22, 7), + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_perilp1", 22, 6), + GATE(PCLK_I2C7, "pclk_i2c7", "pclk_perilp1", 22, 5), + GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 22, 3), + GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 22, 2), + GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 22, 1), + GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 22, 0), + + /* CRU_CLKGATE_CON23 */ + /* 15 - 14 unused */ + GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 23, 13), + GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 23, 12), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 23, 11), + GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 23, 10), + GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 23, 9), + GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 23, 8), + GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", 23, 7), + GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", 23, 6), + GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", 23, 5), + GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", 23, 4), + GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", 23, 3), + GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", 23, 2), + GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", 23, 1), + GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", 23, 0), + + /* CRU_CLKGATE_CON24 */ + GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 24, 15), + GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 24, 14), + GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 24, 13), + GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 24, 11), + GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 24, 10), + GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 24, 9), + GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 24, 8), + /* 7 - unused */ + GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 24, 6), + GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 24, 5), + GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", 24, 4), + /* 3 - 0 unused */ + + /* CRU_CLKGATE_CON25 */ + /* 15 - 13 unused */ + GATE(0, "hclk_sdio_noc", "hclk_perilp1", 25, 12), + GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", 25, 11), + GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 25, 10), + GATE(0, "hclk_perilp1_noc", "hclk_perilp1", 25, 9), + GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", 25, 8), + GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", 25, 7), + GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 25, 6), + GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 25, 5), + /* 4 - 0 unused */ + + /* CRU_CLKGATE_CON26 */ + /* 15 - 12 unused */ + GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 26, 11), + GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 26, 10), + GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 26, 9), + GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 26, 8), + GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 26, 7), + GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 26, 6), + GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 26, 5), + GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 26, 4), + GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 26, 3), + GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 26, 2), + GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 26, 1), + GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 26, 0), + + /* CRU_CLKGATE_CON27 */ + /* 15 - 9 unused */ + GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 27, 8), + GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 27, 7), + GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 27, 6), + GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 27, 5), + GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 27, 4), + GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", 27, 3), + GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", 27, 2), + GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", 27, 1), + GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", 27, 0), + + /* CRU_CLKGATE_CON28 */ + /* 15 - 8 unused */ + GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 28, 7), + GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 28, 6), + GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", 28, 5), + GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", 28, 4), + GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 28, 3), + GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 28, 2), + GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", 28, 1), + GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", 28, 0), + + /* CRU_CLKGATE_CON29 */ + /* 15 - 13 unused */ + GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", 29, 12), + GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 29, 11), + GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 29, 10), + GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 29, 9), + GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 29, 8), + GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 29, 7), + GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 29, 6), + GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", 29, 5), + GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", 29, 4), + GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", 29, 3), + GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 29, 2), + GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 29, 1), + GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", 29, 0), + + /* CRU_CLKGATE_CON30 */ + /* 15 - 12 unused */ + GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 30, 11), + GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 30, 10), + /* 9 unused */ + GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 30, 8), + /* 7 - 5 unused */ + GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 30, 4), + GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 30, 3), + GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 30, 2), + GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 30, 1), + GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", 30, 0), + + /* CRU_CLKGATE_CON31 */ + /* 15 - 11 unused */ + GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", 31, 10), + GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", 31, 9), + GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 31, 8), + GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 31, 7), + GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 31, 6), + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 31, 5), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 31, 4), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 31, 3), + GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", 31, 2), + GATE(PCLK_GRF, "pclk_grf", "pclk_alive", 31, 1), + /* 0 unused */ + + /* CRU_CLKGATE_CON32 */ + /* 15 - 14 unused */ + GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 32, 13), + GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", 32, 12), + /* 11 unused */ + GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", 32, 10), + GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", 32, 9), + GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", 32, 8), + /* 7 - 5 unused */ + GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 32, 4), + GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", 32, 3), + GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 32, 2), + GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", 32, 1), + GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 32, 0), + + /* CRU_CLKGATE_CON33 */ + /* 15 - 10 unused */ + GATE(0, "hclk_sdmmc_noc", "hclk_sd", 33, 9), + GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 33, 8), + GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", 33, 5), + GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", 33, 4), + GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", 33, 3), + GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", 33, 2), + GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", 33, 1), + GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", 33, 0), + + /* CRU_CLKGATE_CON34 */ + /* 15 - 7 unused */ + GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", 34, 6), + GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 34, 5), + GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 34, 4), + GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 34, 3), + GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 34, 2), + GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 34, 1), + GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 34, 0), +}; + +#define PLL_RATE(_hz, _ref, _fb, _post1, _post2, _dspd) \ +{ \ + .freq = _hz, \ + .refdiv = _ref, \ + .fbdiv = _fb, \ + .postdiv1 = _post1, \ + .postdiv2 = _post2, \ + .dsmpd = _dspd, \ +} + +static struct rk_clk_pll_rate rk3399_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + PLL_RATE(2208000000, 1, 92, 1, 1, 1), + PLL_RATE(2184000000, 1, 91, 1, 1, 1), + PLL_RATE(2160000000, 1, 90, 1, 1, 1), + PLL_RATE(2136000000, 1, 89, 1, 1, 1), + PLL_RATE(2112000000, 1, 88, 1, 1, 1), + PLL_RATE(2088000000, 1, 87, 1, 1, 1), + PLL_RATE(2064000000, 1, 86, 1, 1, 1), + PLL_RATE(2040000000, 1, 85, 1, 1, 1), + PLL_RATE(2016000000, 1, 84, 1, 1, 1), + PLL_RATE(1992000000, 1, 83, 1, 1, 1), + PLL_RATE(1968000000, 1, 82, 1, 1, 1), + PLL_RATE(1944000000, 1, 81, 1, 1, 1), + PLL_RATE(1920000000, 1, 80, 1, 1, 1), + PLL_RATE(1896000000, 1, 79, 1, 1, 1), + PLL_RATE(1872000000, 1, 78, 1, 1, 1), + PLL_RATE(1848000000, 1, 77, 1, 1, 1), + PLL_RATE(1824000000, 1, 76, 1, 1, 1), + PLL_RATE(1800000000, 1, 75, 1, 1, 1), + PLL_RATE(1776000000, 1, 74, 1, 1, 1), + PLL_RATE(1752000000, 1, 73, 1, 1, 1), + PLL_RATE(1728000000, 1, 72, 1, 1, 1), + PLL_RATE(1704000000, 1, 71, 1, 1, 1), + PLL_RATE(1680000000, 1, 70, 1, 1, 1), + PLL_RATE(1656000000, 1, 69, 1, 1, 1), + PLL_RATE(1632000000, 1, 68, 1, 1, 1), + PLL_RATE(1608000000, 1, 67, 1, 1, 1), + PLL_RATE(1600000000, 3, 200, 1, 1, 1), + PLL_RATE(1584000000, 1, 66, 1, 1, 1), + PLL_RATE(1560000000, 1, 65, 1, 1, 1), + PLL_RATE(1536000000, 1, 64, 1, 1, 1), + PLL_RATE(1512000000, 1, 63, 1, 1, 1), + PLL_RATE(1488000000, 1, 62, 1, 1, 1), + PLL_RATE(1464000000, 1, 61, 1, 1, 1), + PLL_RATE(1440000000, 1, 60, 1, 1, 1), + PLL_RATE(1416000000, 1, 59, 1, 1, 1), + PLL_RATE(1392000000, 1, 58, 1, 1, 1), + PLL_RATE(1368000000, 1, 57, 1, 1, 1), + PLL_RATE(1344000000, 1, 56, 1, 1, 1), + PLL_RATE(1320000000, 1, 55, 1, 1, 1), + PLL_RATE(1296000000, 1, 54, 1, 1, 1), + PLL_RATE(1272000000, 1, 53, 1, 1, 1), + PLL_RATE(1248000000, 1, 52, 1, 1, 1), + PLL_RATE(1200000000, 1, 50, 1, 1, 1), + PLL_RATE(1188000000, 2, 99, 1, 1, 1), + PLL_RATE(1104000000, 1, 46, 1, 1, 1), + PLL_RATE(1100000000, 12, 550, 1, 1, 1), + PLL_RATE(1008000000, 1, 84, 2, 1, 1), + PLL_RATE(1000000000, 1, 125, 3, 1, 1), + PLL_RATE( 984000000, 1, 82, 2, 1, 1), + PLL_RATE( 960000000, 1, 80, 2, 1, 1), + PLL_RATE( 936000000, 1, 78, 2, 1, 1), + PLL_RATE( 912000000, 1, 76, 2, 1, 1), + PLL_RATE( 900000000, 4, 300, 2, 1, 1), + PLL_RATE( 888000000, 1, 74, 2, 1, 1), + PLL_RATE( 864000000, 1, 72, 2, 1, 1), + PLL_RATE( 840000000, 1, 70, 2, 1, 1), + PLL_RATE( 816000000, 1, 68, 2, 1, 1), + PLL_RATE( 800000000, 1, 100, 3, 1, 1), + PLL_RATE( 700000000, 6, 350, 2, 1, 1), + PLL_RATE( 696000000, 1, 58, 2, 1, 1), + PLL_RATE( 676000000, 3, 169, 2, 1, 1), + PLL_RATE( 600000000, 1, 75, 3, 1, 1), + PLL_RATE( 594000000, 1, 99, 4, 1, 1), + PLL_RATE( 533250000, 8, 711, 4, 1, 1), + PLL_RATE( 504000000, 1, 63, 3, 1, 1), + PLL_RATE( 500000000, 6, 250, 2, 1, 1), + PLL_RATE( 408000000, 1, 68, 2, 2, 1), + PLL_RATE( 312000000, 1, 52, 2, 2, 1), + PLL_RATE( 297000000, 1, 99, 4, 2, 1), + PLL_RATE( 216000000, 1, 72, 4, 2, 1), + PLL_RATE( 148500000, 1, 99, 4, 4, 1), + PLL_RATE( 106500000, 1, 71, 4, 4, 1), + PLL_RATE( 96000000, 1, 64, 4, 4, 1), + PLL_RATE( 74250000, 2, 99, 4, 4, 1), + PLL_RATE( 65000000, 1, 65, 6, 4, 1), + PLL_RATE( 54000000, 1, 54, 6, 4, 1), + PLL_RATE( 27000000, 1, 27, 6, 4, 1), + {}, +}; + +static struct rk_clk_armclk_rates rk3399_cpu_l_rates[] = { + {1800000000, 1}, + {1704000000, 1}, + {1608000000, 1}, + {1512000000, 1}, + {1488000000, 1}, + {1416000000, 1}, + {1200000000, 1}, + {1008000000, 1}, + { 816000000, 1}, + { 696000000, 1}, + { 600000000, 1}, + { 408000000, 1}, + { 312000000, 1}, + { 216000000, 1}, + { 96000000, 1}, +}; + +static struct rk_clk_armclk_rates rk3399_cpu_b_rates[] = { + {2208000000, 1}, + {2184000000, 1}, + {2088000000, 1}, + {2040000000, 1}, + {2016000000, 1}, + {1992000000, 1}, + {1896000000, 1}, + {1800000000, 1}, + {1704000000, 1}, + {1608000000, 1}, + {1512000000, 1}, + {1488000000, 1}, + {1416000000, 1}, + {1200000000, 1}, + {1008000000, 1}, + { 816000000, 1}, + { 696000000, 1}, + { 600000000, 1}, + { 408000000, 1}, + { 312000000, 1}, + { 216000000, 1}, + { 96000000, 1}, +}; + +/* Standard PLL. */ +#define PLL(_id, _name, _base) \ +{ \ + .type = RK3399_CLK_PLL, \ + .clk.pll = &(struct rk_clk_pll_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = pll_src_p, \ + .clkdef.parent_cnt = nitems(pll_src_p), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .base_offset = _base, \ + .rates = rk3399_pll_rates, \ + }, \ +} + +PLIST(pll_src_p) = {"xin24m", "xin32k"}; + +PLIST(armclkl_p) = {"clk_core_l_lpll_src", "clk_core_l_bpll_src", + "clk_core_l_dpll_src", "clk_core_l_gpll_src"}; +PLIST(armclkb_p) = {"clk_core_b_lpll_src", "clk_core_b_bpll_src", + "clk_core_b_dpll_src", "clk_core_b_gpll_src"}; +PLIST(ddrclk_p) = {"clk_ddrc_lpll_src", "clk_ddrc_bpll_src", + "clk_ddrc_dpll_src", "clk_ddrc_gpll_src"}; +PLIST(pll_src_cpll_gpll_p) = {"cpll", "gpll"}; +PLIST(pll_src_cpll_gpll_ppll_p) = {"cpll", "gpll", "ppll"}; +PLIST(pll_src_cpll_gpll_upll_p) = {"cpll", "gpll", "upll"}; +PLIST(pll_src_npll_cpll_gpll_p) = {"npll", "cpll", "gpll"}; +PLIST(pll_src_cpll_gpll_npll_npll_p) = {"cpll", "gpll", "npll", "npll"}; +PLIST(pll_src_cpll_gpll_npll_ppll_p) = {"cpll", "gpll", "npll", "ppll" }; +PLIST(pll_src_cpll_gpll_npll_24m_p) = {"cpll", "gpll", "npll", "xin24m" }; +PLIST(pll_src_cpll_gpll_npll_usbphy480m_p)= {"cpll", "gpll", "npll", "clk_usbphy_480m" }; +PLIST(pll_src_ppll_cpll_gpll_npll_upll_p) = { "ppll", "cpll", "gpll", "npll", "upll" }; +PLIST(pll_src_cpll_gpll_npll_upll_24m_p)= { "cpll", "gpll", "npll", "upll", "xin24m" }; +PLIST(pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" }; +PLIST(pll_src_vpll_cpll_gpll_gpll_p) = {"vpll", "cpll", "gpll", "gpll"}; +PLIST(pll_src_vpll_cpll_gpll_npll_p) = {"vpll", "cpll", "gpll", "npll"}; + +PLIST(aclk_cci_p) = {"cpll_aclk_cci_src", "gpll_aclk_cci_src", + "npll_aclk_cci_src", "vpll_aclk_cci_src"}; +PLIST(cci_trace_p) = {"cpll_cci_trace","gpll_cci_trace"}; +PLIST(cs_p)= {"cpll_cs", "gpll_cs", "npll_cs","npll_cs"}; +PLIST(aclk_perihp_p)= {"cpll_aclk_perihp_src", "gpll_aclk_perihp_src" }; +PLIST(dclk_vop0_p) = {"dclk_vop0_div", "dclk_vop0_frac"}; +PLIST(dclk_vop1_p)= {"dclk_vop1_div", "dclk_vop1_frac"}; + +PLIST(clk_cif_p) = {"clk_cifout_src", "xin24m"}; + +PLIST(pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m"}; +PLIST(pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m"}; +PLIST(pll_src_24m_32k_cpll_gpll_p)= {"xin24m", "xin32k", "cpll", "gpll"}; +PLIST(pciecore_cru_phy_p) = {"clk_pcie_core_cru", "clk_pcie_core_phy"}; + +PLIST(aclk_emmc_p) = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src"}; + +PLIST(aclk_perilp0_p) = { "cpll_aclk_perilp0_src", + "gpll_aclk_perilp0_src" }; + +PLIST(fclk_cm0s_p) = { "cpll_fclk_cm0s_src", + "gpll_fclk_cm0s_src" }; + +PLIST(hclk_perilp1_p) = { "cpll_hclk_perilp1_src", + "gpll_hclk_perilp1_src" }; + +PLIST(clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" }; +PLIST(clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" }; + +PLIST(usbphy_480m_p) = { "clk_usbphy0_480m_src", + "clk_usbphy1_480m_src" }; +PLIST(aclk_gmac_p) = { "cpll_aclk_gmac_src", + "gpll_aclk_gmac_src" }; +PLIST(rmii_p) = { "clk_gmac", "clkin_gmac" }; +PLIST(spdif_p) = { "clk_spdif_div", "clk_spdif_frac", + "clkin_i2s", "xin12m" }; +PLIST(i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac", + "clkin_i2s", "xin12m" }; +PLIST(i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac", + "clkin_i2s", "xin12m" }; +PLIST(i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac", + "clkin_i2s", "xin12m" }; +PLIST(i2sch_p) = {"clk_i2s0", "clk_i2s1", "clk_i2s2"}; +PLIST(i2sout_p) = {"clk_i2sout_src", "xin12m"}; + +PLIST(uart0_p)= {"clk_uart0_div", "clk_uart0_frac", "xin24m"}; +PLIST(uart1_p)= {"clk_uart1_div", "clk_uart1_frac", "xin24m"}; +PLIST(uart2_p)= {"clk_uart2_div", "clk_uart2_frac", "xin24m"}; +PLIST(uart3_p)= {"clk_uart3_div", "clk_uart3_frac", "xin24m"}; + +static struct rk_clk rk3399_clks[] = { + /* External clocks */ + LINK("xin24m"), + LINK("xin32k"), + FFACT(0, "xin12m", "xin24m", 1, 2), + FRATE(0, "clkin_i2s", 0), + FRATE(0, "pclkin_cif", 0), + LINK("clk_usbphy0_480m"), + LINK("clk_usbphy1_480m"), + LINK("clkin_gmac"), + FRATE(0, "clk_pcie_core_phy", 0), + FFACT(0, "clk_ddrc_div2", "clk_ddrc", 1, 2), + + /* PLLs */ + PLL(PLL_APLLL, "lpll", 0x00), + PLL(PLL_APLLB, "bpll", 0x20), + PLL(PLL_DPLL, "dpll", 0x40), + PLL(PLL_CPLL, "cpll", 0x60), + PLL(PLL_GPLL, "gpll", 0x80), + PLL(PLL_NPLL, "npll", 0xA0), + PLL(PLL_VPLL, "vpll", 0xC0), + + /* CRU_CLKSEL_CON0 */ + CDIV(0, "aclkm_core_l_c", "armclkl", 0, + 0, 8, 5), + ARMDIV(ARMCLKL, "armclkl", armclkl_p, rk3399_cpu_l_rates, + 0, 0, 5, 6, 2, 0, 3), + /* CRU_CLKSEL_CON1 */ + CDIV(0, "pclk_dbg_core_l_c", "armclkl", 0, + 1, 8, 5), + CDIV(0, "atclk_core_l_c", "armclkl", 0, + 1, 0, 5), + + /* CRU_CLKSEL_CON2 */ + CDIV(0, "aclkm_core_b_c", "armclkb", 0, + 2, 8, 5), + ARMDIV(ARMCLKB, "armclkb", armclkb_p, rk3399_cpu_b_rates, + 2, 0, 5, 6, 2, 1, 3), + + /* CRU_CLKSEL_CON3 */ + CDIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", 0, + 3, 13, 2), + CDIV(0, "pclk_dbg_core_b_c", "armclkb", 0, + 3, 8, 5), + CDIV(0, "atclk_core_b_c", "armclkb", 0, + 3, 0, 5), + + /* CRU_CLKSEL_CON4 */ + COMP(0, "clk_cs", cs_p, 0, + 4, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON5 */ + COMP(0, "clk_cci_trace_c", cci_trace_p, 0, + 5, 8, 5, 15, 1), + COMP(0, "aclk_cci_pre_c", aclk_cci_p, 0, + 5, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON6 */ + COMP(0, "pclk_ddr_c", pll_src_cpll_gpll_p, 0, + 6, 8, 5, 15, 1), + COMP(SCLK_DDRC, "clk_ddrc", ddrclk_p, 0, + 6, 0, 3, 4, 2), + + /* CRU_CLKSEL_CON7 */ + CDIV(0, "hclk_vcodec_pre_c", "aclk_vcodec_pre", 0, + 7, 8, 5), + COMP(0, "aclk_vcodec_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0, + 7, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON8 */ + CDIV(0, "hclk_vdu_pre_c", "aclk_vdu_pre", 0, + 8, 8, 5), + COMP(0, "aclk_vdu_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0, + 8, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON9 */ + COMP(0, "clk_vdu_ca_c", pll_src_cpll_gpll_npll_npll_p, 0, + 9, 8, 5, 14, 2), + COMP(0, "clk_vdu_core_c", pll_src_cpll_gpll_npll_npll_p, 0, + 9, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON10 */ + CDIV(0, "hclk_iep_pre_c", "aclk_iep_pre", 0, + 10, 8, 5), + COMP(0, "aclk_iep_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0, + 10, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON11 */ + CDIV(0, "hclk_rga_pre_c", "aclk_rga_pre", 0, + 11, 8, 5), + COMP(0, "aclk_rga_pre_c", pll_src_cpll_gpll_npll_ppll_p, 0, + 11, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON12 */ + COMP(0, "aclk_center_c", pll_src_cpll_gpll_npll_npll_p, 0, + 12, 8, 5, 14, 2), + COMP(SCLK_RGA_CORE, "clk_rga_core_c", pll_src_cpll_gpll_npll_ppll_p, 0, + 12, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON13 */ + COMP(0, "hclk_sd_c", pll_src_cpll_gpll_p, 0, + 13, 8, 5, 15, 1), + COMP(0, "aclk_gpu_pre_c", pll_src_ppll_cpll_gpll_npll_upll_p, 0, + 13, 0, 5, 5, 3), + + /* CRU_CLKSEL_CON14 */ + MUX(0, "upll", pll_src_24m_usbphy480m_p, 0, + 14, 15, 1), + CDIV(0, "pclk_perihp_c", "aclk_perihp", 0, + 14, 12, 2), + CDIV(0, "hclk_perihp_c", "aclk_perihp", 0, + 14, 8, 2), + MUX(0, "clk_usbphy_480m", usbphy_480m_p, 0, + 14, 6, 1), + COMP(0, "aclk_perihp_c", aclk_perihp_p, 0, + 14, 0, 5, 7, 1), + + /* CRU_CLKSEL_CON15 */ + COMP(0, "clk_sdio_c", pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, + 15, 0, 7, 8, 3), + + /* CRU_CLKSEL_CON16 */ + COMP(0, "clk_sdmmc_c", pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0, + 16, 0, 7, 8, 3), + + /* CRU_CLKSEL_CON17 */ + COMP(0, "clk_pcie_pm_c", pll_src_cpll_gpll_npll_24m_p, 0, + 17, 0, 7, 8, 3), + + /* CRU_CLKSEL_CON18 */ + CDIV(0, "clk_pciephy_ref100m_c", "npll", 0, + 18, 11, 5), + MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", pll_src_24m_pciephy_p, 0, + 18, 10, 1), + MUX(SCLK_PCIE_CORE, "clk_pcie_core", pciecore_cru_phy_p, 0, + 18, 7, 1), + COMP(0, "clk_pcie_core_cru_c", pll_src_cpll_gpll_npll_npll_p, 0, + 18, 0, 7, 8, 2), + + /* CRU_CLKSEL_CON19 */ + CDIV(0, "pclk_gmac_pre_c", "aclk_gmac_pre", 0, + 19, 8, 3), + MUX(SCLK_RMII_SRC, "clk_rmii_src",rmii_p, 0, + 19, 4, 1), + MUX(SCLK_HSICPHY, "clk_hsicphy_c", pll_src_cpll_gpll_npll_usbphy480m_p, 0, + 19, 0, 2), + + /* CRU_CLKSEL_CON20 */ + COMP(0, "clk_gmac_c", pll_src_cpll_gpll_npll_npll_p, 0, + 20, 8, 5, 14, 2), + COMP(0, "aclk_gmac_pre_c", aclk_gmac_p, 0, + 20, 0, 5, 7, 1), + + /* CRU_CLKSEL_CON21 */ + COMP(ACLK_EMMC, "aclk_emmc", aclk_emmc_p, 0, + 21, 0, 5, 7, 1), + + /* CRU_CLKSEL_CON22 */ + COMP(0, "clk_emmc_c", pll_src_cpll_gpll_npll_upll_24m_p, 0, + 22, 0, 7, 8, 3), + + /* CRU_CLKSEL_CON23 */ + CDIV(0, "pclk_perilp0_c", "aclk_perilp0", 0, + 23, 12, 3), + CDIV(0, "hclk_perilp0_c", "aclk_perilp0", 0, + 23, 8, 2), + COMP(0, "aclk_perilp0_c", aclk_perilp0_p, 0, + 23, 0, 5, 7, 1), + + /* CRU_CLKSEL_CON24 */ + COMP(0, "fclk_cm0s_c", fclk_cm0s_p, 0, + 24, 8, 5, 15, 1), + COMP(0, "clk_crypto0_c", pll_src_cpll_gpll_ppll_p, 0, + 24, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON25 */ + CDIV(0, "pclk_perilp1_c", "hclk_perilp1", 0, + 25, 8, 3), + COMP(HCLK_PERILP1, "hclk_perilp1", hclk_perilp1_p, 0, + 25, 0, 5, 7, 1), + + /* CRU_CLKSEL_CON26 */ + CDIV(0, "clk_saradc_c", "xin24m", 0, + 26, 8, 8), + COMP(0, "clk_crypto1_c", pll_src_cpll_gpll_ppll_p, 0, + 26, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON27 */ + COMP(0, "clk_tsadc_c", pll_src_p, 0, + 27, 0, 10, 15, 1), + + /* CRU_CLKSEL_CON28 */ + MUX(0, "clk_i2s0_mux", i2s0_p, RK_CLK_MUX_REPARENT, + 28, 8, 2), + COMP(0, "clk_i2s0_div_c", pll_src_cpll_gpll_p, 0, + 28, 0, 7, 7, 1), + + /* CRU_CLKSEL_CON29 */ + MUX(0, "clk_i2s1_mux", i2s1_p, RK_CLK_MUX_REPARENT, + 29, 8, 2), + COMP(0, "clk_i2s1_div_c", pll_src_cpll_gpll_p, 0, + 29, 0, 7, 7, 1), + + /* CRU_CLKSEL_CON30 */ + MUX(0, "clk_i2s2_mux", i2s2_p, RK_CLK_MUX_REPARENT, + 30, 8, 2), + COMP(0, "clk_i2s2_div_c", pll_src_cpll_gpll_p, 0, + 30, 0, 7, 7, 1), + + /* CRU_CLKSEL_CON31 */ + MUX(0, "clk_i2sout_c", i2sout_p, 0, + 31, 2, 1), + MUX(0, "clk_i2sout_src", i2sch_p, 0, + 31, 0, 2), + + /* CRU_CLKSEL_CON32 */ + COMP(0, "clk_spdif_rec_dptx_c", pll_src_cpll_gpll_p, 0, + 32, 8, 5, 15, 1), + MUX(0, "clk_spdif_mux", spdif_p, 0, + 32, 13, 2), + COMP(0, "clk_spdif_div_c", pll_src_cpll_gpll_p, 0, + 32, 0, 7, 7, 1), + + /* CRU_CLKSEL_CON33 */ + MUX(0, "clk_uart_src", pll_src_cpll_gpll_p, 0, + 33, 15, 1), + MUX(0, "clk_uart0_src", pll_src_cpll_gpll_upll_p, 0, + 33, 12, 2), + MUX(SCLK_UART0, "clk_uart0", uart0_p, 0, + 33, 8, 2), + CDIV(0, "clk_uart0_div_c", "clk_uart0_src", 0, + 33, 0, 7), + + /* CRU_CLKSEL_CON34 */ + MUX(SCLK_UART1, "clk_uart1", uart1_p, 0, + 34, 8, 2), + CDIV(0, "clk_uart1_div_c", "clk_uart_src", 0, + 34, 0, 7), + + /* CRU_CLKSEL_CON35 */ + MUX(SCLK_UART2, "clk_uart2", uart2_p, 0, + 35, 8, 2), + CDIV(0, "clk_uart2_div_c", "clk_uart_src", 0, + 35, 0, 7), + + /* CRU_CLKSEL_CON36 */ + MUX(SCLK_UART3, "clk_uart3", uart3_p, 0, + 36, 8, 2), + CDIV(0, "clk_uart3_div_c", "clk_uart_src", 0, + 36, 0, 7), + + /* CRU_CLKSEL_CON37 */ + /* unused */ + + /* CRU_CLKSEL_CON38 */ + MUX(0, "clk_testout2_pll_src", pll_src_cpll_gpll_npll_npll_p, 0, + 38, 14, 2), + COMP(0, "clk_testout2_c", clk_testout2_p, 0, + 38, 8, 5, 13, 1), + MUX(0, "clk_testout1_pll_src", pll_src_cpll_gpll_npll_npll_p, 0, + 38, 6, 2), + COMP(0, "clk_testout1_c", clk_testout1_p, 0, + 38, 0, 5, 5, 1), + + /* CRU_CLKSEL_CON39 */ + COMP(0, "aclk_usb3_c", pll_src_cpll_gpll_npll_npll_p, 0, + 39, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON40 */ + COMP(0, "clk_usb3otg0_suspend_c", pll_src_p, 0, + 40, 0, 10, 15, 1), + + /* CRU_CLKSEL_CON41 */ + COMP(0, "clk_usb3otg1_suspend_c", pll_src_p, 0, + 41, 0, 10, 15, 1), + + /* CRU_CLKSEL_CON42 */ + COMP(0, "aclk_hdcp_c", pll_src_cpll_gpll_ppll_p, 0, + 42, 8, 5, 14, 2), + COMP(0, "aclk_vio_c", pll_src_cpll_gpll_ppll_p, 0, + 42, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON43 */ + CDIV(0, "pclk_hdcp_c", "aclk_hdcp", 0, + 43, 10, 5), + CDIV(0, "hclk_hdcp_c", "aclk_hdcp", 0, + 43, 5, 5), + CDIV(0, "pclk_vio_c", "aclk_vio", 0, + 43, 0, 5), + + /* CRU_CLKSEL_CON44 */ + COMP(0, "pclk_edp_c", pll_src_cpll_gpll_p, 0, + 44, 8, 6, 15, 1), + + /* CRU_CLKSEL_CON45 - XXX clocks in mux are reversed in TRM !!!*/ + COMP(0, "clk_hdmi_cec_c", pll_src_p, 0, + 45, 0, 10, 15, 1), + + /* CRU_CLKSEL_CON46 */ + COMP(0, "clk_dp_core_c", pll_src_npll_cpll_gpll_p, 0, + 46, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON47 */ + CDIV(0, "hclk_vop0_pre_c", "aclk_vop0_pre_c", 0, + 47, 8, 5), + COMP(0, "aclk_vop0_pre_c", pll_src_vpll_cpll_gpll_npll_p, 0, + 47, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON48 */ + CDIV(0, "hclk_vop1_pre_c", "aclk_vop1_pre", 0, + 48, 8, 5), + COMP(0, "aclk_vop1_pre_c", pll_src_vpll_cpll_gpll_npll_p, 0, + 48, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON49 */ + MUX(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, 0, + 49, 11, 1), + COMP(0, "dclk_vop0_div_c", pll_src_vpll_cpll_gpll_gpll_p, 0, + 49, 0, 8, 8, 2), + + /* CRU_CLKSEL_CON50 */ + MUX(DCLK_VOP1, "dclk_vop1", dclk_vop1_p, 0, + 50, 11, 1), + COMP(0, "dclk_vop1_div_c", pll_src_vpll_cpll_gpll_gpll_p, 0, + 50, 0, 8, 8, 2), + + /* CRU_CLKSEL_CON51 */ + COMP(0, "clk_vop0_pwm_c", pll_src_vpll_cpll_gpll_gpll_p, 0, + 51, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON52 */ + COMP(0, "clk_vop1_pwm_c", pll_src_vpll_cpll_gpll_gpll_p, 0, + 52, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON53 */ + CDIV(0, "hclk_isp0_c", "aclk_isp0", 0, + 53, 8, 5), + COMP(0, "aclk_isp0_c", pll_src_cpll_gpll_ppll_p, 0, + 53, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON54 */ + CDIV(0, "hclk_isp1_c", "aclk_isp1", 0, + 54, 8, 5), + COMP(0, "aclk_isp1_c", pll_src_cpll_gpll_ppll_p, 0, + 54, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON55 */ + COMP(0, "clk_isp1_c", pll_src_cpll_gpll_npll_npll_p, 0, + 55, 8, 5, 14, 2), + COMP(0, "clk_isp0_c", pll_src_cpll_gpll_npll_npll_p, 0, + 55, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON56 */ + COMP(0, "aclk_gic_pre_c", pll_src_cpll_gpll_p, 0, + 56, 8, 5, 15, 1), + MUX(0, "clk_cifout_src_c", pll_src_cpll_gpll_npll_npll_p, 0, + 56, 6, 2), + COMP(SCLK_CIF_OUT, "clk_cifout", clk_cif_p, 0, + 56, 0, 5, 5, 1), + + /* CRU_CLKSEL_CON57 */ + CDIV(0, "clk_test_24m", "xin24m", 0, + 57, 6, 10), + CDIV(PCLK_ALIVE, "pclk_alive", "gpll", 0, + 57, 0, 5), + + /* CRU_CLKSEL_CON58 */ + COMP(0, "clk_spi5_c", pll_src_cpll_gpll_p, 0, + 58, 8, 7, 15, 1), + MUX(0, "clk_test_pre", pll_src_cpll_gpll_p, 0, + 58, 7, 1), + CDIV(0, "clk_test_c", "clk_test_pre", 0, + 58, 0, 5), + + /* CRU_CLKSEL_CON59 */ + COMP(0, "clk_spi1_c", pll_src_cpll_gpll_p, 0, + 59, 8, 7, 15, 1), + COMP(0, "clk_spi0_c", pll_src_cpll_gpll_p, 0, + 59, 0, 7, 7, 1), + + /* CRU_CLKSEL_CON60 */ + COMP(0, "clk_spi4_c", pll_src_cpll_gpll_p, 0, + 60, 8, 7, 15, 1), + COMP(0, "clk_spi2_c", pll_src_cpll_gpll_p, 0, + 60, 0, 7, 7, 1), + + /* CRU_CLKSEL_CON61 */ + COMP(0, "clk_i2c5_c", pll_src_cpll_gpll_p, 0, + 61, 8, 7, 15, 1), + COMP(0, "clk_i2c1_c", pll_src_cpll_gpll_p, 0, + 61, 0, 7, 7, 1), + + /* CRU_CLKSEL_CON62 */ + COMP(0, "clk_i2c6_c", pll_src_cpll_gpll_p, 0, + 62, 8, 7, 15, 1), + COMP(0, "clk_i2c2_c", pll_src_cpll_gpll_p, 0, + 62, 0, 7, 7, 1), + + /* CRU_CLKSEL_CON63 */ + COMP(0, "clk_i2c7_c", pll_src_cpll_gpll_p, 0, + 63, 8, 7, 15, 1), + COMP(0, "clk_i2c3_c", pll_src_cpll_gpll_p, 0, + 63, 0, 7, 7, 1), + + /* CRU_CLKSEL_CON64 */ + COMP(0, "clk_uphy0_tcpdphy_ref_c", pll_src_p, 0, + 64, 8, 5, 15, 1), + COMP(0, "clk_uphy0_tcpdcore_c", pll_src_24m_32k_cpll_gpll_p, 0, + 64, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON65 */ + COMP(0, "clk_uphy1_tcpdphy_ref_c", pll_src_p, 0, + 65, 8, 5, 15, 1), + COMP(0, "clk_uphy1_tcpdcore_c", pll_src_24m_32k_cpll_gpll_p, 0, + 65, 0, 5, 6, 2), + + /* CRU_CLKSEL_CON99 - 107 */ + FRACT(0, "clk_spdif_frac_c", "clk_spdif_div", 0, + 99), + FRACT(0, "clk_i2s0_frac_c", "clk_i2s0_div", 0, + 96), + FRACT(0, "clk_i2s1_frac_c", "clk_i2s1_div", 0, + 97), + FRACT(0, "clk_i2s2_frac_c", "clk_i2s2_div", 0, + 98), + FRACT(0, "clk_uart0_frac_c", "clk_uart0_div", 0, + 100), + FRACT(0, "clk_uart1_frac_c", "clk_uart1_div", 0, + 101), + FRACT(0, "clk_uart2_frac_c", "clk_uart2_div", 0, + 102), + FRACT(0, "clk_uart3_frac_c", "clk_uart3_div", 0, + 103), + FRACT(0, "clk_test_frac_c", "clk_test_pre", 0, + 105), + FRACT(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0, + 106), + FRACT(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0, + 107), + + /* + * This clock is controlled in the secure world + */ + FFACT(PCLK_WDT, "pclk_wdt", "pclk_alive", 1, 1), + +/* Not yet implemented yet + * MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1), + * MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1), + * MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1), + * MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1), + */ + +}; + +static int +rk3399_cru_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_is_compatible(dev, "rockchip,rk3399-cru")) { + device_set_desc(dev, "Rockchip RK3399 Clock and Reset Unit"); + return (BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static int +rk3399_cru_attach(device_t dev) +{ + struct rk_cru_softc *sc; + + sc = device_get_softc(dev); + sc->dev = dev; + + sc->gates = rk3399_gates; + sc->ngates = nitems(rk3399_gates); + + sc->clks = rk3399_clks; + sc->nclks = nitems(rk3399_clks); + + sc->reset_offset = 0x400; + sc->reset_num = 335; + + return (rk_cru_attach(dev)); +} + +static device_method_t rk3399_cru_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, rk3399_cru_probe), + DEVMETHOD(device_attach, rk3399_cru_attach), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(rk3399_cru, rk3399_cru_driver, rk3399_cru_methods, + sizeof(struct rk_cru_softc), rk_cru_driver); + +EARLY_DRIVER_MODULE(rk3399_cru, simplebus, rk3399_cru_driver, 0, 0, + BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); diff --git a/sys/dev/clk/rockchip/rk3399_cru_dt.h b/sys/dev/clk/rockchip/rk3399_cru_dt.h new file mode 100644 index 000000000000..f652f45129ca --- /dev/null +++ b/sys/dev/clk/rockchip/rk3399_cru_dt.h @@ -0,0 +1,320 @@ +#ifndef _RK3399_DT_H_ +#define _RK3399_DT_H_ + +#define PLL_APLLL 1 +#define PLL_APLLB 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define PLL_VPLL 7 +#define ARMCLKL 8 +#define ARMCLKB 9 +#define SCLK_I2C1 65 +#define SCLK_I2C2 66 +#define SCLK_I2C3 67 +#define SCLK_I2C5 68 +#define SCLK_I2C6 69 +#define SCLK_I2C7 70 +#define SCLK_SPI0 71 +#define SCLK_SPI1 72 +#define SCLK_SPI2 73 +#define SCLK_SPI4 74 +#define SCLK_SPI5 75 +#define SCLK_SDMMC 76 +#define SCLK_SDIO 77 +#define SCLK_EMMC 78 +#define SCLK_TSADC 79 +#define SCLK_SARADC 80 +#define SCLK_UART0 81 +#define SCLK_UART1 82 +#define SCLK_UART2 83 +#define SCLK_UART3 84 +#define SCLK_SPDIF_8CH 85 +#define SCLK_I2S0_8CH 86 +#define SCLK_I2S1_8CH 87 +#define SCLK_I2S2_8CH 88 +#define SCLK_I2S_8CH_OUT 89 +#define SCLK_TIMER00 90 +#define SCLK_TIMER01 91 +#define SCLK_TIMER02 92 +#define SCLK_TIMER03 93 +#define SCLK_TIMER04 94 +#define SCLK_TIMER05 95 +#define SCLK_TIMER06 96 +#define SCLK_TIMER07 97 +#define SCLK_TIMER08 98 +#define SCLK_TIMER09 99 +#define SCLK_TIMER10 100 +#define SCLK_TIMER11 101 +#define SCLK_MACREF 102 +#define SCLK_MAC_RX 103 +#define SCLK_MAC_TX 104 +#define SCLK_MAC 105 +#define SCLK_MACREF_OUT 106 +#define SCLK_VOP0_PWM 107 +#define SCLK_VOP1_PWM 108 +#define SCLK_RGA_CORE 109 +#define SCLK_ISP0 110 +#define SCLK_ISP1 111 +#define SCLK_HDMI_CEC 112 +#define SCLK_HDMI_SFR 113 +#define SCLK_DP_CORE 114 +#define SCLK_PVTM_CORE_L 115 +#define SCLK_PVTM_CORE_B 116 +#define SCLK_PVTM_GPU 117 +#define SCLK_PVTM_DDR 118 +#define SCLK_MIPIDPHY_REF 119 +#define SCLK_MIPIDPHY_CFG 120 +#define SCLK_HSICPHY 121 +#define SCLK_USBPHY480M 122 +#define SCLK_USB2PHY0_REF 123 +#define SCLK_USB2PHY1_REF 124 +#define SCLK_UPHY0_TCPDPHY_REF 125 +#define SCLK_UPHY0_TCPDCORE 126 +#define SCLK_UPHY1_TCPDPHY_REF 127 +#define SCLK_UPHY1_TCPDCORE 128 +#define SCLK_USB3OTG0_REF 129 +#define SCLK_USB3OTG1_REF 130 +#define SCLK_USB3OTG0_SUSPEND 131 +#define SCLK_USB3OTG1_SUSPEND 132 +#define SCLK_CRYPTO0 133 +#define SCLK_CRYPTO1 134 +#define SCLK_CCI_TRACE 135 +#define SCLK_CS 136 +#define SCLK_CIF_OUT 137 +#define SCLK_PCIEPHY_REF 138 +#define SCLK_PCIE_CORE 139 +#define SCLK_M0_PERILP 140 +#define SCLK_M0_PERILP_DEC 141 +#define SCLK_CM0S 142 +#define SCLK_DBG_NOC 143 +#define SCLK_DBG_PD_CORE_B 144 +#define SCLK_DBG_PD_CORE_L 145 +#define SCLK_DFIMON0_TIMER 146 +#define SCLK_DFIMON1_TIMER 147 +#define SCLK_INTMEM0 148 +#define SCLK_INTMEM1 149 +#define SCLK_INTMEM2 150 +#define SCLK_INTMEM3 151 +#define SCLK_INTMEM4 152 +#define SCLK_INTMEM5 153 +#define SCLK_SDMMC_DRV 154 +#define SCLK_SDMMC_SAMPLE 155 +#define SCLK_SDIO_DRV 156 +#define SCLK_SDIO_SAMPLE 157 +#define SCLK_VDU_CORE 158 +#define SCLK_VDU_CA 159 +#define SCLK_PCIE_PM 160 +#define SCLK_SPDIF_REC_DPTX 161 +#define SCLK_DPHY_PLL 162 +#define SCLK_DPHY_TX0_CFG 163 +#define SCLK_DPHY_TX1RX1_CFG 164 +#define SCLK_DPHY_RX0_CFG 165 +#define SCLK_RMII_SRC 166 +#define SCLK_PCIEPHY_REF100M 167 +#define SCLK_DDRC 168 +#define SCLK_TESTCLKOUT1 169 +#define SCLK_TESTCLKOUT2 170 +#define DCLK_VOP0 180 +#define DCLK_VOP1 181 +#define DCLK_VOP0_DIV 182 +#define DCLK_VOP1_DIV 183 +#define DCLK_M0_PERILP 184 +#define DCLK_VOP0_FRAC 185 +#define DCLK_VOP1_FRAC 186 +#define FCLK_CM0S 190 +#define ACLK_PERIHP 192 +#define ACLK_PERIHP_NOC 193 +#define ACLK_PERILP0 194 +#define ACLK_PERILP0_NOC 195 +#define ACLK_PERF_PCIE 196 +#define ACLK_PCIE 197 +#define ACLK_INTMEM 198 +#define ACLK_TZMA 199 +#define ACLK_DCF 200 +#define ACLK_CCI 201 +#define ACLK_CCI_NOC0 202 +#define ACLK_CCI_NOC1 203 +#define ACLK_CCI_GRF 204 +#define ACLK_CENTER 205 +#define ACLK_CENTER_MAIN_NOC 206 +#define ACLK_CENTER_PERI_NOC 207 +#define ACLK_GPU 208 +#define ACLK_PERF_GPU 209 +#define ACLK_GPU_GRF 210 +#define ACLK_DMAC0_PERILP 211 +#define ACLK_DMAC1_PERILP 212 +#define ACLK_GMAC 213 +#define ACLK_GMAC_NOC 214 +#define ACLK_PERF_GMAC 215 +#define ACLK_VOP0_NOC 216 +#define ACLK_VOP0 217 +#define ACLK_VOP1_NOC 218 +#define ACLK_VOP1 219 +#define ACLK_RGA 220 +#define ACLK_RGA_NOC 221 +#define ACLK_HDCP 222 +#define ACLK_HDCP_NOC 223 +#define ACLK_HDCP22 224 +#define ACLK_IEP 225 +#define ACLK_IEP_NOC 226 +#define ACLK_VIO 227 +#define ACLK_VIO_NOC 228 +#define ACLK_ISP0 229 +#define ACLK_ISP1 230 +#define ACLK_ISP0_NOC 231 +#define ACLK_ISP1_NOC 232 +#define ACLK_ISP0_WRAPPER 233 +#define ACLK_ISP1_WRAPPER 234 +#define ACLK_VCODEC 235 +#define ACLK_VCODEC_NOC 236 +#define ACLK_VDU 237 +#define ACLK_VDU_NOC 238 +#define ACLK_PERI 239 +#define ACLK_EMMC 240 +#define ACLK_EMMC_CORE 241 +#define ACLK_EMMC_NOC 242 +#define ACLK_EMMC_GRF 243 +#define ACLK_USB3 244 +#define ACLK_USB3_NOC 245 +#define ACLK_USB3OTG0 246 +#define ACLK_USB3OTG1 247 +#define ACLK_USB3_RKSOC_AXI_PERF 248 +#define ACLK_USB3_GRF 249 +#define ACLK_GIC 250 +#define ACLK_GIC_NOC 251 +#define ACLK_GIC_ADB400_CORE_L_2_GIC 252 +#define ACLK_GIC_ADB400_CORE_B_2_GIC 253 +#define ACLK_GIC_ADB400_GIC_2_CORE_L 254 +#define ACLK_GIC_ADB400_GIC_2_CORE_B 255 +#define ACLK_CORE_ADB400_CORE_L_2_CCI500 256 +#define ACLK_CORE_ADB400_CORE_B_2_CCI500 257 +#define ACLK_ADB400M_PD_CORE_L 258 +#define ACLK_ADB400M_PD_CORE_B 259 +#define ACLK_PERF_CORE_L 260 +#define ACLK_PERF_CORE_B 261 +#define ACLK_GIC_PRE 262 +#define ACLK_VOP0_PRE 263 +#define ACLK_VOP1_PRE 264 +#define PCLK_PERIHP 320 +#define PCLK_PERIHP_NOC 321 +#define PCLK_PERILP0 322 +#define PCLK_PERILP1 323 +#define PCLK_PERILP1_NOC 324 +#define PCLK_PERILP_SGRF 325 +#define PCLK_PERIHP_GRF 326 +#define PCLK_PCIE 327 +#define PCLK_SGRF 328 +#define PCLK_INTR_ARB 329 +#define PCLK_CENTER_MAIN_NOC 330 +#define PCLK_CIC 331 +#define PCLK_COREDBG_B 332 +#define PCLK_COREDBG_L 333 +#define PCLK_DBG_CXCS_PD_CORE_B 334 +#define PCLK_DCF 335 +#define PCLK_GPIO2 336 +#define PCLK_GPIO3 337 +#define PCLK_GPIO4 338 +#define PCLK_GRF 339 +#define PCLK_HSICPHY 340 +#define PCLK_I2C1 341 +#define PCLK_I2C2 342 +#define PCLK_I2C3 343 +#define PCLK_I2C5 344 +#define PCLK_I2C6 345 +#define PCLK_I2C7 346 +#define PCLK_SPI0 347 +#define PCLK_SPI1 348 +#define PCLK_SPI2 349 +#define PCLK_SPI4 350 +#define PCLK_SPI5 351 +#define PCLK_UART0 352 +#define PCLK_UART1 353 +#define PCLK_UART2 354 +#define PCLK_UART3 355 +#define PCLK_TSADC 356 +#define PCLK_SARADC 357 +#define PCLK_GMAC 358 +#define PCLK_GMAC_NOC 359 +#define PCLK_TIMER0 360 +#define PCLK_TIMER1 361 +#define PCLK_EDP 362 +#define PCLK_EDP_NOC 363 +#define PCLK_EDP_CTRL 364 +#define PCLK_VIO 365 +#define PCLK_VIO_NOC 366 +#define PCLK_VIO_GRF 367 +#define PCLK_MIPI_DSI0 368 +#define PCLK_MIPI_DSI1 369 +#define PCLK_HDCP 370 +#define PCLK_HDCP_NOC 371 +#define PCLK_HDMI_CTRL 372 +#define PCLK_DP_CTRL 373 +#define PCLK_HDCP22 374 +#define PCLK_GASKET 375 +#define PCLK_DDR 376 +#define PCLK_DDR_MON 377 +#define PCLK_DDR_SGRF 378 +#define PCLK_ISP1_WRAPPER 379 +#define PCLK_WDT 380 +#define PCLK_EFUSE1024NS 381 +#define PCLK_EFUSE1024S 382 +#define PCLK_PMU_INTR_ARB 383 +#define PCLK_MAILBOX0 384 +#define PCLK_USBPHY_MUX_G 385 +#define PCLK_UPHY0_TCPHY_G 386 +#define PCLK_UPHY0_TCPD_G 387 +#define PCLK_UPHY1_TCPHY_G 388 +#define PCLK_UPHY1_TCPD_G 389 +#define PCLK_ALIVE 390 +#define HCLK_PERIHP 448 +#define HCLK_PERILP0 449 +#define HCLK_PERILP1 450 +#define HCLK_PERILP0_NOC 451 +#define HCLK_PERILP1_NOC 452 +#define HCLK_M0_PERILP 453 +#define HCLK_M0_PERILP_NOC 454 +#define HCLK_AHB1TOM 455 +#define HCLK_HOST0 456 +#define HCLK_HOST0_ARB 457 +#define HCLK_HOST1 458 +#define HCLK_HOST1_ARB 459 +#define HCLK_HSIC 460 +#define HCLK_SD 461 +#define HCLK_SDMMC 462 +#define HCLK_SDMMC_NOC 463 +#define HCLK_M_CRYPTO0 464 +#define HCLK_M_CRYPTO1 465 +#define HCLK_S_CRYPTO0 466 +#define HCLK_S_CRYPTO1 467 +#define HCLK_I2S0_8CH 468 +#define HCLK_I2S1_8CH 469 +#define HCLK_I2S2_8CH 470 +#define HCLK_SPDIF 471 +#define HCLK_VOP0_NOC 472 +#define HCLK_VOP0 473 +#define HCLK_VOP1_NOC 474 +#define HCLK_VOP1 475 +#define HCLK_ROM 476 +#define HCLK_IEP 477 +#define HCLK_IEP_NOC 478 +#define HCLK_ISP0 479 +#define HCLK_ISP1 480 +#define HCLK_ISP0_NOC 481 +#define HCLK_ISP1_NOC 482 +#define HCLK_ISP0_WRAPPER 483 +#define HCLK_ISP1_WRAPPER 484 +#define HCLK_RGA 485 +#define HCLK_RGA_NOC 486 +#define HCLK_HDCP 487 +#define HCLK_HDCP_NOC 488 +#define HCLK_HDCP22 489 +#define HCLK_VCODEC 490 +#define HCLK_VCODEC_NOC 491 +#define HCLK_VDU 492 +#define HCLK_VDU_NOC 493 +#define HCLK_SDIO 494 +#define HCLK_SDIO_NOC 495 +#define HCLK_SDIOAUDIO_NOC 496 +#endif diff --git a/sys/dev/clk/rockchip/rk3399_pmucru.c b/sys/dev/clk/rockchip/rk3399_pmucru.c new file mode 100644 index 000000000000..706bf444aaf2 --- /dev/null +++ b/sys/dev/clk/rockchip/rk3399_pmucru.c @@ -0,0 +1,873 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org> + * Copyright (c) 2018 Val Packett <val@packett.cool> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <machine/bus.h> + +#include <dev/fdt/simplebus.h> + +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> + +#include <dev/extres/clk/clk_div.h> +#include <dev/extres/clk/clk_fixed.h> +#include <dev/extres/clk/clk_mux.h> + +#include <dev/clk/rockchip/rk_cru.h> + +#define CRU_CLKSEL_CON(x) (0x80 + (x) * 0x4) +#define CRU_CLKGATE_CON(x) (0x100 + (x) * 0x4) + +#define PLL_PPLL 1 +#define SCLK_32K_SUSPEND_PMU 2 +#define SCLK_SPI3_PMU 3 +#define SCLK_TIMER12_PMU 4 +#define SCLK_TIMER13_PMU 5 +#define SCLK_UART4_PMU 6 +#define SCLK_PVTM_PMU 7 +#define SCLK_WIFI_PMU 8 +#define SCLK_I2C0_PMU 9 +#define SCLK_I2C4_PMU 10 +#define SCLK_I2C8_PMU 11 + +#define PCLK_PMU_SRC 19 +#define PCLK_PMU 20 +#define PCLK_PMUGRF_PMU 21 +#define PCLK_INTMEM1_PMU 22 +#define PCLK_GPIO0_PMU 23 +#define PCLK_GPIO1_PMU 24 +#define PCLK_SGRF_PMU 25 +#define PCLK_NOC_PMU 26 +#define PCLK_I2C0_PMU 27 +#define PCLK_I2C4_PMU 28 +#define PCLK_I2C8_PMU 29 +#define PCLK_RKPWM_PMU 30 +#define PCLK_SPI3_PMU 31 +#define PCLK_TIMER_PMU 32 +#define PCLK_MAILBOX_PMU 33 +#define PCLK_UART4_PMU 34 +#define PCLK_WDT_M0_PMU 35 + +#define FCLK_CM0S_SRC_PMU 44 +#define FCLK_CM0S_PMU 45 +#define SCLK_CM0S_PMU 46 +#define HCLK_CM0S_PMU 47 +#define DCLK_CM0S_PMU 48 +#define PCLK_INTR_ARB_PMU 49 +#define HCLK_NOC_PMU 50 + +/* GATES */ +static struct rk_cru_gate rk3399_pmu_gates[] = { + /* PMUCRU_CLKGATE_CON0 */ + /* 0 Reserved */ + /* 1 fclk_cm0s_pmu_ppll_src_en */ + GATE(SCLK_SPI3_PMU, "clk_spi3_pmu", "clk_spi3_c", 0, 2), + GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_sel", 0, 3), + GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_sel", 0, 4), + GATE(SCLK_UART4_PMU, "clk_uart4_pmu", "clk_uart4_sel", 0, 5), + GATE(0, "clk_uart4_frac", "clk_uart4_frac_frac", 0, 6), + /* 7 clk_pvtm_pmu_en */ + GATE(SCLK_WIFI_PMU, "clk_wifi_pmu", "clk_wifi_sel", 0, 8), + GATE(SCLK_I2C0_PMU, "clk_i2c0_src", "clk_i2c0_div", 0, 9), + GATE(SCLK_I2C4_PMU, "clk_i2c4_src", "clk_i2c4_div", 0, 10), + GATE(SCLK_I2C8_PMU, "clk_i2c8_src", "clk_i2c8_div", 0, 11), + /* 12:15 Reserved */ + + /* PMUCRU_CLKGATE_CON1 */ + GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", 1, 0), + /* 1 pclk_pmugrf_en */ + /* 2 pclk_intmem1_en */ + GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 1, 3), + GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 1, 4), + /* 5 pclk_sgrf_en */ + /* 6 pclk_noc_pmu_en */ + GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 1, 7), + GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 1, 8), + GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 1, 9), + GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 1, 10), + GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 1, 11), + GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 1, 12), + GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 1, 13), + /* 14 pclk_uartm0_en */ + /* 15 pclk_wdt_m0_pmu_en */ + + /* PMUCRU_CLKGATE_CON2 */ + /* 0 fclk_cm0s_en */ + /* 1 sclk_cm0s_en */ + /* 2 hclk_cm0s_en */ + /* 3 dclk_cm0s_en */ + /* 4 Reserved */ + /* 5 hclk_noc_pmu_en */ + /* 6:15 Reserved */ +}; + +/* + * PLLs + */ + +static struct rk_clk_pll_rate rk3399_pll_rates[] = { + { + .freq = 2208000000, + .refdiv = 1, + .fbdiv = 92, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2184000000, + .refdiv = 1, + .fbdiv = 91, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2160000000, + .refdiv = 1, + .fbdiv = 90, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2136000000, + .refdiv = 1, + .fbdiv = 89, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2112000000, + .refdiv = 1, + .fbdiv = 88, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2088000000, + .refdiv = 1, + .fbdiv = 87, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2064000000, + .refdiv = 1, + .fbdiv = 86, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2040000000, + .refdiv = 1, + .fbdiv = 85, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2016000000, + .refdiv = 1, + .fbdiv = 84, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1992000000, + .refdiv = 1, + .fbdiv = 83, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1968000000, + .refdiv = 1, + .fbdiv = 82, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1944000000, + .refdiv = 1, + .fbdiv = 81, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1920000000, + .refdiv = 1, + .fbdiv = 80, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1896000000, + .refdiv = 1, + .fbdiv = 79, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1872000000, + .refdiv = 1, + .fbdiv = 78, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1848000000, + .refdiv = 1, + .fbdiv = 77, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1824000000, + .refdiv = 1, + .fbdiv = 76, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1800000000, + .refdiv = 1, + .fbdiv = 75, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1776000000, + .refdiv = 1, + .fbdiv = 74, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1752000000, + .refdiv = 1, + .fbdiv = 73, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1728000000, + .refdiv = 1, + .fbdiv = 72, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1704000000, + .refdiv = 1, + .fbdiv = 71, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1680000000, + .refdiv = 1, + .fbdiv = 70, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1656000000, + .refdiv = 1, + .fbdiv = 69, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1632000000, + .refdiv = 1, + .fbdiv = 68, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1608000000, + .refdiv = 1, + .fbdiv = 67, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1600000000, + .refdiv = 3, + .fbdiv = 200, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1584000000, + .refdiv = 1, + .fbdiv = 66, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1560000000, + .refdiv = 1, + .fbdiv = 65, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1536000000, + .refdiv = 1, + .fbdiv = 64, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1512000000, + .refdiv = 1, + .fbdiv = 63, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1488000000, + .refdiv = 1, + .fbdiv = 62, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1464000000, + .refdiv = 1, + .fbdiv = 61, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1440000000, + .refdiv = 1, + .fbdiv = 60, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1416000000, + .refdiv = 1, + .fbdiv = 59, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1392000000, + .refdiv = 1, + .fbdiv = 58, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1368000000, + .refdiv = 1, + .fbdiv = 57, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1344000000, + .refdiv = 1, + .fbdiv = 56, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1320000000, + .refdiv = 1, + .fbdiv = 55, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1296000000, + .refdiv = 1, + .fbdiv = 54, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1272000000, + .refdiv = 1, + .fbdiv = 53, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1248000000, + .refdiv = 1, + .fbdiv = 52, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1200000000, + .refdiv = 1, + .fbdiv = 50, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1188000000, + .refdiv = 2, + .fbdiv = 99, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1104000000, + .refdiv = 1, + .fbdiv = 46, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1100000000, + .refdiv = 12, + .fbdiv = 550, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1008000000, + .refdiv = 1, + .fbdiv = 84, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1000000000, + .refdiv = 1, + .fbdiv = 125, + .postdiv1 = 3, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 984000000, + .refdiv = 1, + .fbdiv = 82, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 960000000, + .refdiv = 1, + .fbdiv = 80, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 936000000, + .refdiv = 1, + .fbdiv = 78, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 912000000, + .refdiv = 1, + .fbdiv = 76, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 900000000, + .refdiv = 4, + .fbdiv = 300, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 888000000, + .refdiv = 1, + .fbdiv = 74, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 864000000, + .refdiv = 1, + .fbdiv = 72, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 840000000, + .refdiv = 1, + .fbdiv = 70, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 816000000, + .refdiv = 1, + .fbdiv = 68, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 800000000, + .refdiv = 1, + .fbdiv = 100, + .postdiv1 = 3, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 700000000, + .refdiv = 6, + .fbdiv = 350, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 696000000, + .refdiv = 1, + .fbdiv = 58, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 676000000, + .refdiv = 3, + .fbdiv = 169, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 600000000, + .refdiv = 1, + .fbdiv = 75, + .postdiv1 = 3, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 594000000, + .refdiv = 1, + .fbdiv = 99, + .postdiv1 = 4, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 533250000, + .refdiv = 8, + .fbdiv = 711, + .postdiv1 = 4, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 504000000, + .refdiv = 1, + .fbdiv = 63, + .postdiv1 = 3, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 500000000, + .refdiv = 6, + .fbdiv = 250, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 408000000, + .refdiv = 1, + .fbdiv = 68, + .postdiv1 = 2, + .postdiv2 = 2, + .dsmpd = 1, + }, + { + .freq = 312000000, + .refdiv = 1, + .fbdiv = 52, + .postdiv1 = 2, + .postdiv2 = 2, + .dsmpd = 1, + }, + { + .freq = 297000000, + .refdiv = 1, + .fbdiv = 99, + .postdiv1 = 4, + .postdiv2 = 2, + .dsmpd = 1, + }, + { + .freq = 216000000, + .refdiv = 1, + .fbdiv = 72, + .postdiv1 = 4, + .postdiv2 = 2, + .dsmpd = 1, + }, + { + .freq = 148500000, + .refdiv = 1, + .fbdiv = 99, + .postdiv1 = 4, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 106500000, + .refdiv = 1, + .fbdiv = 71, + .postdiv1 = 4, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 96000000, + .refdiv = 1, + .fbdiv = 64, + .postdiv1 = 4, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 74250000, + .refdiv = 2, + .fbdiv = 99, + .postdiv1 = 4, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 65000000, + .refdiv = 1, + .fbdiv = 65, + .postdiv1 = 6, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 54000000, + .refdiv = 1, + .fbdiv = 54, + .postdiv1 = 6, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 27000000, + .refdiv = 1, + .fbdiv = 27, + .postdiv1 = 6, + .postdiv2 = 4, + .dsmpd = 1, + }, + {}, +}; + +PLIST(xin24m_p) = {"xin24m"}; +PLIST(xin24m_xin32k_p) = {"xin24m", "xin32k"}; +PLIST(xin24m_ppll_p) = {"xin24m", "ppll"}; +PLIST(uart4_p) = {"clk_uart4_c", "clk_uart4_frac", "xin24m"}; +PLIST(wifi_p) = {"clk_wifi_c", "clk_wifi_frac"}; + +static struct rk_clk_pll_def ppll = { + .clkdef = { + .id = PLL_PPLL, + .name = "ppll", + .parent_names = xin24m_p, + .parent_cnt = nitems(xin24m_p), + }, + .base_offset = 0x00, + + .rates = rk3399_pll_rates, +}; + +static struct rk_clk rk3399_pmu_clks[] = { + /* Linked clocks */ + LINK("xin32k"), + + { + .type = RK3399_CLK_PLL, + .clk.pll = &ppll + }, + + /* PMUCRU_CLKSEL_CON0 */ + CDIV(PCLK_PMU_SRC, "pclk_pmu_src", "ppll", 0, 0, 0, 5), + /* 5:7 Reserved */ + /* 8:12 cm0s_div */ + /* 13:14 Reserved */ + /* 15 cm0s_clk_pll_sel */ + + /* PMUCRU_CLKSEL_CON1 */ + COMP(0, "clk_spi3_c", xin24m_ppll_p, 0, 1, 0, 7, 7, 1), + COMP(0, "clk_wifi_c", xin24m_ppll_p, 0, 1, 8, 5, 13, 1), + MUX(0, "clk_wifi_sel", wifi_p, 0, 1, 14, 1), + MUX(0, "clk_timer_sel", xin24m_xin32k_p, 0, 1, 15, 1), + + /* PMUCRU_CLKSEL_CON2 */ + CDIV(0, "clk_i2c0_div", "ppll", 0, 2, 0, 7), + /* 7 Reserved */ + CDIV(0, "clk_i2c8_div", "ppll", 0, 2, 8, 7), + /* 15 Reserved */ + + /* PMUCRU_CLKSEL_CON3 */ + CDIV(0, "clk_i2c4_div", "ppll", 0, 3, 0, 7), + /* 7:15 Reserved */ + + /* PMUCRU_CLKSEL_CON4 */ + /* 0:9 clk_32k_suspend_div */ + /* 10:14 Reserved */ + /* 15 clk_32k_suspend_sel */ + + /* PMUCRU_CLKSEL_CON5 */ + COMP(0, "clk_uart4_c", xin24m_ppll_p, 0, 5, 0, 7, 10, 1), + /* 7 Reserved */ + MUX(0, "clk_uart4_sel", uart4_p, 0, 5, 8, 2), + /* 11:15 Reserved */ + + /* PMUCRU_CLKFRAC_CON0 / PMUCRU_CLKSEL_CON6 */ + FRACT(0, "clk_uart4_frac_frac", "clk_uart4_sel", 0, 6), + + /* PMUCRU_CLKFRAC_CON1 / PMUCRU_CLKSEL_CON7 */ + FRACT(0, "clk_wifi_frac", "clk_wifi_c", 0, 7), +}; + +static int +rk3399_pmucru_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_is_compatible(dev, "rockchip,rk3399-pmucru")) { + device_set_desc(dev, "Rockchip RK3399 PMU Clock and Reset Unit"); + return (BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static int +rk3399_pmucru_attach(device_t dev) +{ + struct rk_cru_softc *sc; + + sc = device_get_softc(dev); + sc->dev = dev; + + sc->gates = rk3399_pmu_gates; + sc->ngates = nitems(rk3399_pmu_gates); + + sc->clks = rk3399_pmu_clks; + sc->nclks = nitems(rk3399_pmu_clks); + + sc->reset_offset = 0x110; + sc->reset_num = 30; + + return (rk_cru_attach(dev)); +} + +static device_method_t rk3399_pmucru_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, rk3399_pmucru_probe), + DEVMETHOD(device_attach, rk3399_pmucru_attach), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(rk3399_pmucru, rk3399_pmucru_driver, rk3399_pmucru_methods, + sizeof(struct rk_cru_softc), rk_cru_driver); + +EARLY_DRIVER_MODULE(rk3399_pmucru, simplebus, rk3399_pmucru_driver, 0, 0, + BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); diff --git a/sys/dev/clk/rockchip/rk3568_cru.c b/sys/dev/clk/rockchip/rk3568_cru.c new file mode 100644 index 000000000000..4d7f569a3de2 --- /dev/null +++ b/sys/dev/clk/rockchip/rk3568_cru.c @@ -0,0 +1,1439 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2021, 2022 Soren Schmidt <sos@deepcore.dk> + * Copyright (c) 2023, Emmanuel Vadot <manu@freebsd.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <machine/bus.h> + +#include <dev/fdt/simplebus.h> + +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> + +#include <dev/extres/clk/clk_div.h> +#include <dev/extres/clk/clk_fixed.h> +#include <dev/extres/clk/clk_mux.h> + +#include <dev/clk/rockchip/rk_cru.h> +#include <contrib/device-tree/include/dt-bindings/clock/rk3568-cru.h> + + +#define RK3568_PLLSEL_CON(x) ((x) * 0x20) +#define CRU_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define CRU_CLKGATE_CON(x) ((x) * 0x4 + 0x300) +#define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400) + +#define RK_PLLRATE(_hz, _ref, _fb, _post1, _post2, _dspd) \ +{ \ + .freq = _hz, \ + .refdiv = _ref, \ + .fbdiv = _fb, \ + .postdiv1 = _post1, \ + .postdiv2 = _post2, \ + .dsmpd = _dspd, \ +} + +/* PLL clock */ +#define RK_PLL(_id, _name, _pnames, _off, _shift) \ +{ \ + .type = RK3328_CLK_PLL, \ + .clk.pll = &(struct rk_clk_pll_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = _pnames, \ + .clkdef.parent_cnt = nitems(_pnames), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .base_offset = RK3568_PLLSEL_CON(_off), \ + .mode_reg = 0xc0, \ + .mode_shift = _shift, \ + .rates = rk3568_pll_rates, \ + }, \ +} + +struct rk_clk_pll_rate rk3568_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd */ + RK_PLLRATE(2208000000, 1, 92, 1, 1, 1), + RK_PLLRATE(2184000000, 1, 91, 1, 1, 1), + RK_PLLRATE(2160000000, 1, 90, 1, 1, 1), + RK_PLLRATE(2088000000, 1, 87, 1, 1, 1), + RK_PLLRATE(2064000000, 1, 86, 1, 1, 1), + RK_PLLRATE(2040000000, 1, 85, 1, 1, 1), + RK_PLLRATE(2016000000, 1, 84, 1, 1, 1), + RK_PLLRATE(1992000000, 1, 83, 1, 1, 1), + RK_PLLRATE(1920000000, 1, 80, 1, 1, 1), + RK_PLLRATE(1896000000, 1, 79, 1, 1, 1), + RK_PLLRATE(1800000000, 1, 75, 1, 1, 1), + RK_PLLRATE(1704000000, 1, 71, 1, 1, 1), + RK_PLLRATE(1608000000, 1, 67, 1, 1, 1), + RK_PLLRATE(1600000000, 3, 200, 1, 1, 1), + RK_PLLRATE(1584000000, 1, 132, 2, 1, 1), + RK_PLLRATE(1560000000, 1, 130, 2, 1, 1), + RK_PLLRATE(1536000000, 1, 128, 2, 1, 1), + RK_PLLRATE(1512000000, 1, 126, 2, 1, 1), + RK_PLLRATE(1488000000, 1, 124, 2, 1, 1), + RK_PLLRATE(1464000000, 1, 122, 2, 1, 1), + RK_PLLRATE(1440000000, 1, 120, 2, 1, 1), + RK_PLLRATE(1416000000, 1, 118, 2, 1, 1), + RK_PLLRATE(1400000000, 3, 350, 2, 1, 1), + RK_PLLRATE(1392000000, 1, 116, 2, 1, 1), + RK_PLLRATE(1368000000, 1, 114, 2, 1, 1), + RK_PLLRATE(1344000000, 1, 112, 2, 1, 1), + RK_PLLRATE(1320000000, 1, 110, 2, 1, 1), + RK_PLLRATE(1296000000, 1, 108, 2, 1, 1), + RK_PLLRATE(1272000000, 1, 106, 2, 1, 1), + RK_PLLRATE(1248000000, 1, 104, 2, 1, 1), + RK_PLLRATE(1200000000, 1, 100, 2, 1, 1), + RK_PLLRATE(1188000000, 1, 99, 2, 1, 1), + RK_PLLRATE(1104000000, 1, 92, 2, 1, 1), + RK_PLLRATE(1100000000, 3, 275, 2, 1, 1), + RK_PLLRATE(1008000000, 1, 84, 2, 1, 1), + RK_PLLRATE(1000000000, 3, 250, 2, 1, 1), + RK_PLLRATE(912000000, 1, 76, 2, 1, 1), + RK_PLLRATE(816000000, 1, 68, 2, 1, 1), + RK_PLLRATE(800000000, 3, 200, 2, 1, 1), + RK_PLLRATE(700000000, 3, 350, 4, 1, 1), + RK_PLLRATE(696000000, 1, 116, 4, 1, 1), + RK_PLLRATE(600000000, 1, 100, 4, 1, 1), + RK_PLLRATE(594000000, 1, 99, 4, 1, 1), + RK_PLLRATE(500000000, 1, 125, 6, 1, 1), + RK_PLLRATE(408000000, 1, 68, 2, 2, 1), + RK_PLLRATE(312000000, 1, 78, 6, 1, 1), + RK_PLLRATE(216000000, 1, 72, 4, 2, 1), + RK_PLLRATE(200000000, 1, 100, 3, 4, 1), + RK_PLLRATE(148500000, 1, 99, 4, 4, 1), + RK_PLLRATE(100000000, 1, 150, 6, 6, 1), + RK_PLLRATE(96000000, 1, 96, 6, 4, 1), + RK_PLLRATE(74250000, 2, 99, 4, 4, 1), + {}, +}; + +static struct rk_clk_armclk_rates rk3568_armclk_rates[] = { + {2208000000, 1}, + {2160000000, 1}, + {2064000000, 1}, + {2016000000, 1}, + {1992000000, 1}, + {1800000000, 1}, + {1704000000, 1}, + {1608000000, 1}, + {1512000000, 1}, + {1488000000, 1}, + {1416000000, 1}, + {1200000000, 1}, + {1104000000, 1}, + {1008000000, 1}, + { 816000000, 1}, + { 696000000, 1}, + { 600000000, 1}, + { 408000000, 1}, + { 312000000, 1}, + { 216000000, 1}, + { 96000000, 1}, + {}, +}; + +/* Parent clock defines */ +PLIST(mux_pll_p) = { "xin24m" }; +PLIST(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc_32k" }; +PLIST(mux_armclk_p) = { "apll", "gpll" }; +PLIST(clk_i2s0_8ch_tx_p) = { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", + "i2s0_mclkin", "xin_osc0_half" }; +PLIST(clk_i2s0_8ch_rx_p) = { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", + "i2s0_mclkin", "xin_osc0_half" }; +PLIST(clk_i2s1_8ch_tx_p) = { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", + "i2s1_mclkin", "xin_osc0_half" }; +PLIST(clk_i2s1_8ch_rx_p) = { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", + "i2s1_mclkin", "xin_osc0_half" }; +PLIST(clk_i2s2_2ch_p) = { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", + "i2s2_mclkin", "xin_osc0_half"}; +PLIST(clk_i2s3_2ch_tx_p) = { "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_frac", + "i2s3_mclkin", "xin_osc0_half" }; +PLIST(clk_i2s3_2ch_rx_p) = { "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_frac", + "i2s3_mclkin", "xin_osc0_half" }; +PLIST(mclk_spdif_8ch_p) = { "mclk_spdif_8ch_src", "mclk_spdif_8ch_frac" }; +PLIST(sclk_audpwm_p) = { "sclk_audpwm_src", "sclk_audpwm_frac" }; +PLIST(sclk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" }; +PLIST(sclk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" }; +PLIST(sclk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" }; +PLIST(sclk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" }; +PLIST(sclk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" }; +PLIST(sclk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" }; +PLIST(sclk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" }; +PLIST(sclk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" }; +PLIST(sclk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" }; +PLIST(mpll_gpll_cpll_npll_p) = { "mpll", "gpll", "cpll", "npll" }; +PLIST(gpll_cpll_npll_p) = { "gpll", "cpll", "npll" }; +PLIST(npll_gpll_p) = { "npll", "gpll" }; +PLIST(cpll_gpll_p) = { "cpll", "gpll" }; +PLIST(gpll_cpll_p) = { "gpll", "cpll" }; +PLIST(gpll_cpll_npll_vpll_p) = { "gpll", "cpll", "npll", "vpll" }; +PLIST(apll_gpll_npll_p) = { "apll", "gpll", "npll" }; +PLIST(sclk_core_pre_p) = { "sclk_core_src", "npll" }; +PLIST(gpll150_gpll100_gpll75_xin24m_p) = { "clk_gpll_div_150m", "clk_gpll_div_100m", "clk_gpll_div_75m", + "xin24m" }; +PLIST(clk_gpu_pre_mux_p) = { "clk_gpu_src", "gpu_pvtpll_out" }; +PLIST(clk_npu_pre_ndft_p) = { "clk_npu_src", "clk_npu_np5"}; +PLIST(clk_npu_p) = { "clk_npu_pre_ndft", "npu_pvtpll_out" }; +PLIST(dpll_gpll_cpll_p) = { "dpll", "gpll", "cpll" }; +PLIST(clk_ddr1x_p) = { "clk_ddrphy1x_src", "dpll" }; +PLIST(gpll200_gpll150_gpll100_xin24m_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", + "clk_gpll_div_100m", "xin24m" }; +PLIST(gpll100_gpll75_gpll50_p) = { "clk_gpll_div_100m", "clk_gpll_div_75m", "clk_cpll_div_50m" }; +PLIST(i2s0_mclkout_tx_p) = { "clk_i2s0_8ch_tx", "xin_osc0_half" }; +PLIST(i2s0_mclkout_rx_p) = { "clk_i2s0_8ch_rx", "xin_osc0_half" }; +PLIST(i2s1_mclkout_tx_p) = { "clk_i2s1_8ch_tx", "xin_osc0_half" }; +PLIST(i2s1_mclkout_rx_p) = { "clk_i2s1_8ch_rx", "xin_osc0_half" }; +PLIST(i2s2_mclkout_p) = { "clk_i2s2_2ch", "xin_osc0_half" }; +PLIST(i2s3_mclkout_tx_p) = { "clk_i2s3_2ch_tx", "xin_osc0_half" }; +PLIST(i2s3_mclkout_rx_p) = { "clk_i2s3_2ch_rx", "xin_osc0_half" }; +PLIST(mclk_pdm_p) = { "clk_gpll_div_300m", "clk_cpll_div_250m", "clk_gpll_div_200m", "clk_gpll_div_100m" }; +PLIST(clk_i2c_p) = { "clk_gpll_div_200m", "clk_gpll_div_100m", "xin24m", "clk_cpll_div_100m" }; +PLIST(gpll200_gpll150_gpll100_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_gpll_div_100m" }; +PLIST(gpll300_gpll200_gpll100_p) = { "clk_gpll_div_300m", "clk_gpll_div_200m", "clk_gpll_div_100m" }; +PLIST(clk_nandc_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_100m", "xin24m" }; +PLIST(sclk_sfc_p) = { "xin24m", "clk_cpll_div_50m", "clk_gpll_div_75m", "clk_gpll_div_100m", + "clk_cpll_div_125m", "clk_gpll_div_150m" }; +PLIST(gpll200_gpll150_cpll125_p) = { "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_125m" }; +PLIST(cclk_emmc_p) = { "xin24m", "clk_gpll_div_200m", "clk_gpll_div_150m", "clk_cpll_div_100m", + "clk_cpll_div_50m", "clk_osc0_div_375k" }; +PLIST(aclk_pipe_p) = { "clk_gpll_div_400m", "clk_gpll_div_300m", "clk_gpll_div_200m", "xin24m" }; +PLIST(gpll200_cpll125_p) = { "clk_gpll_div_200m", "clk_cpll_div_125m" }; +PLIST(gpll300_gpll200_gpll100_xin24m_p) = { "clk_gpll_div_300m", "clk_gpll_div_200m", + "clk_gpll_div_100m", "xin24m" }; +PLIST(clk_sdmmc_p) = { "xin24m", "clk_gpll_div_400m", "clk_gpll_div_300m", "clk_cpll_div_100m", + "clk_cpll_div_50m", "clk_osc0_div_750k" }; +PLIST(cpll125_cpll50_cpll25_xin24m_p) = { "clk_cpll_div_125m", "clk_cpll_div_50m", "clk_cpll_div_25m", + "xin24m" }; +PLIST(clk_gmac_ptp_p) = { "clk_cpll_div_62P5m", "clk_gpll_div_100m", "clk_cpll_div_50m", "xin24m" }; +PLIST(cpll333_gpll300_gpll200_p) = { "clk_cpll_div_333m", "clk_gpll_div_300m", "clk_gpll_div_200m" }; +PLIST(cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" }; +PLIST(gpll_usb480m_xin24m_p) = { "gpll", "usb480m", "xin24m", "xin24m" }; +PLIST(gpll300_cpll250_gpll100_xin24m_p) = { "clk_gpll_div_300m", "clk_cpll_div_250m", + "clk_gpll_div_100m", "xin24m" }; +PLIST(cpll_gpll_hpll_vpll_p) = { "cpll", "gpll", "hpll", "vpll" }; +PLIST(hpll_vpll_gpll_cpll_p) = { "hpll", "vpll", "gpll", "cpll" }; +PLIST(gpll400_cpll333_gpll200_p) = { "clk_gpll_div_400m", "clk_cpll_div_333m", "clk_gpll_div_200m" }; +PLIST(gpll100_gpll75_cpll50_xin24m_p) = { "clk_gpll_div_100m", "clk_gpll_div_75m", "clk_cpll_div_50m", + "xin24m" }; +PLIST(xin24m_gpll100_cpll100_p) = { "xin24m", "clk_gpll_div_100m", "clk_cpll_div_100m" }; +PLIST(gpll_cpll_usb480m_p) = { "gpll", "cpll", "usb480m" }; +PLIST(gpll100_xin24m_cpll100_p) = { "clk_gpll_div_100m", "xin24m", "clk_cpll_div_100m" }; +PLIST(gpll200_xin24m_cpll100_p) = { "clk_gpll_div_200m", "xin24m", "clk_cpll_div_100m" }; +PLIST(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; +PLIST(cpll500_gpll400_gpll300_xin24m_p) = { "clk_cpll_div_500m", "clk_gpll_div_400m", + "clk_gpll_div_300m", "xin24m" }; +PLIST(gpll400_gpll300_gpll200_xin24m_p) = { "clk_gpll_div_400m", "clk_gpll_div_300m", + "clk_gpll_div_200m", "xin24m" }; +PLIST(xin24m_cpll100_p) = { "xin24m", "clk_cpll_div_100m" }; +PLIST(mux_gmac0_p) = { "clk_mac0_2top", "gmac0_clkin" }; +PLIST(mux_gmac0_rgmii_speed_p) = { "clk_gmac0", "clk_gmac0", + "clk_gmac0_tx_div50", "clk_gmac0_tx_div5" }; +PLIST(mux_gmac0_rmii_speed_p) = { "clk_gmac0_rx_div20", "clk_gmac0_rx_div2" }; +PLIST(mux_gmac0_rx_tx_p) = { "clk_gmac0_rgmii_speed", "clk_gmac0_rmii_speed", + "clk_gmac0_xpcs_mii" }; +PLIST(mux_gmac1_p) = { "clk_mac1_2top", "gmac1_clkin" }; +PLIST(mux_gmac1_rgmii_speed_p) = { "clk_gmac1", "clk_gmac1", + "clk_gmac1_tx_div50", "clk_gmac1_tx_div5" }; +PLIST(mux_gmac1_rmii_speed_p) = { "clk_gmac1_rx_div20", "clk_gmac1_rx_div2" }; +PLIST(mux_gmac1_rx_tx_p) = { "clk_gmac1_rgmii_speed", "clk_gmac1_rmii_speed", + "clk_gmac1_xpcs_mii" }; +PLIST(clk_mac_2top_p) = { "clk_cpll_div_125m", "clk_cpll_div_50m", "clk_cpll_div_25m", "ppll" }; +PLIST(aclk_rkvdec_pre_p) = { "gpll", "cpll" }; +PLIST(clk_rkvdec_core_p) = { "gpll", "cpll", "npll", "vpll" }; + +/* CLOCKS */ +static struct rk_clk rk3568_clks[] = { + /* External clocks */ + LINK("xin24m"), + LINK("clk_rtc_32k"), + LINK("usb480m_phy"), + LINK("mpll"), /* It lives in SCRU */ + LINK("i2s0_mclkin"), + LINK("i2s1_mclkin"), + LINK("i2s2_mclkin"), + LINK("i2s3_mclkin"), + LINK("gpu_pvtpll_out"), + LINK("npu_pvtpll_out"), + LINK("gmac0_clkin"), + LINK("gmac1_clkin"), + LINK("clk_gmac0_xpcs_mii"), + LINK("clk_gmac1_xpcs_mii"), + LINK("dummy"), + + /* PLL's */ + RK_PLL(PLL_APLL, "apll", mux_pll_p, 0, 0), + RK_PLL(PLL_DPLL, "dpll", mux_pll_p, 1, 2), + RK_PLL(PLL_GPLL, "gpll", mux_pll_p, 2, 6), + RK_PLL(PLL_CPLL, "cpll", mux_pll_p, 3, 4), + RK_PLL(PLL_NPLL, "npll", mux_pll_p, 4, 10), + RK_PLL(PLL_VPLL, "vpll", mux_pll_p, 5, 12), + ARMDIV(ARMCLK, "armclk", mux_armclk_p, rk3568_armclk_rates, 0, 0, 5, + 6, 1, 0, 1), + FFACT(0, "clk_osc0_div_375k", "clk_osc0_div_750k", 1, 2), + FFACT(0, "xin_osc0_half", "xin24m", 1, 2), + MUX(USB480M, "usb480m", mux_usb480m_p, 0, -16, 14, 2), + + /* Clocks */ + + /* CRU_CLKSEL_CON00 */ + /* 0:4 clk_core0_div DIV */ + /* 5 Reserved */ + /* 6 clk_core_i_sel MUX */ + /* 7 clk_core_ndft_sel MUX */ + /* 8:12 clk_core1_div DIV */ + /* 13:14 Reserved */ + /* 15 clk_core_ndft_mux_sel MUX */ + + /* CRU_CLKSEL_CON01 */ + /* 0:4 clk_core2_div DIV */ + /* 5:7 Reserved */ + /* 8:12 clk_core3_div DIV */ + /* 13:15 Reserved */ + + /* CRU_CLKSEL_CON02 */ + COMP(0, "sclk_core_src_c", apll_gpll_npll_p, 0, 2, 0, 4, 8, 2), + /* 4:7 Reserved */ + /* 10:14 Reserved */ + MUX(0, "sclk_core_pre_sel", sclk_core_pre_p, 0, 2, 15, 1), + + /* CRU_CLKSEL_CON03 */ + CDIV(0, "atclk_core_div", "armclk", 0, 3, 0, 5), + /* 5:7 Reserved */ + CDIV(0, "gicclk_core_div", "armclk", 0, 3, 8, 5), + /* 13:15 Reserved */ + + /* CRU_CLKSEL_CON04 */ + CDIV(0, "pclk_core_pre_div", "armclk", 0, 4, 0, 5), + /* 5:7 Reserved */ + CDIV(0, "periphclk_core_pre_div", "armclk", 0, 4, 8, 5), + /* 13:15 Reserved */ + + /* CRU_CLKSEL_CON05 */ + /* 0:7 Reserved */ + /* 8:12 aclk_core_ndft_div DIV */ + /* 13 Reserved */ + /* 14:15 aclk_core_biu2bus_sel MUX */ + + /* CRU_CLKSEL_CON06 */ + COMP(0, "clk_gpu_pre_c", mpll_gpll_cpll_npll_p, 0, 6, 0, 4, 6, 2), + /* 4:5 Reserved */ + CDIV(0, "aclk_gpu_pre_div", "clk_gpu_pre_c", 0, 6, 8, 2), + /* 10 Reserved */ + MUX(CLK_GPU_PRE_MUX, "clk_gpu_pre_mux_sel", clk_gpu_pre_mux_p, 0, 6, 11, 1), + CDIV(0, "pclk_gpu_pre_div", "clk_gpu_pre_c", 0, 6, 12, 4), + + /* CRU_CLKSEL_CON07 */ + COMP(0, "clk_npu_src_c", npll_gpll_p, 0, 7, 0, 4, 6, 1), + COMP(0, "clk_npu_np5_c", npll_gpll_p, 0, 7, 4, 2, 7, 1), + MUX(CLK_NPU_PRE_NDFT, "clk_npu_pre_ndft", clk_npu_pre_ndft_p, 0, 7, + 8, 1), + /* 9:14 Reserved */ + MUX(CLK_NPU, "clk_npu", clk_npu_p, 0, 7, 15, 1), + + /* CRU_CLKSEL_CON08 */ + CDIV(0, "hclk_npu_pre_div", "clk_npu", 0, 8, 0, 4), + CDIV(0, "pclk_npu_pre_div", "clk_npu", 0, 8, 4, 4), + /* 8:15 Reserved */ + + /* CRU_CLKSEL_CON09 */ + COMP(0, "clk_ddrphy1x_src_c", dpll_gpll_cpll_p, 0, 9, 0, 5, 6, 2), + /* 5 Reserved */ + /* 8:14 Reserved */ + MUX(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, RK_CLK_COMPOSITE_GRF, 9, + 15, 1), + + /* CRU_CLKSEL_CON10 */ + CDIV(0, "clk_msch_div", "clk_ddr1x", 0, 10, 0, 2), + MUX(0, "aclk_perimid_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 10, 4, 2), + MUX(0, "hclk_perimid_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 10, 6, 2), + MUX(0, "aclk_gic_audio_sel", gpll200_gpll150_gpll100_xin24m_p, 0, 10, 8, 2), + MUX(0, "hclk_gic_audio_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 10, 10, 2), + MUX(0, "dclk_sdmmc_buffer_sel", gpll100_gpll75_gpll50_p, 0, 10, 12, 2), + /* 14:15 Reserved */ + + /* CRU_CLKSEL_CON11 */ + COMP(0, "clk_i2s0_8ch_tx_src_c", gpll_cpll_npll_p, 0, 11, 0, 7, 8, 2), + /* 7 Reserved */ + MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, 0, 11, 10, + 2), + /* 12:14 Reserved */ + MUX(0, "i2s0_mclkout_tx_sel", i2s0_mclkout_tx_p, 0, 11, 15, 1), + + /* CRU_CLKSEL_CON12 */ + FRACT(0, "clk_i2s0_8ch_tx_frac_div", "clk_i2s0_8ch_tx_src", 0, 12), + + /* CRU_CLKSEL_CON13 */ + COMP(0, "clk_i2s0_8ch_rx_src_c", gpll_cpll_npll_p, 0, 13, 0, 7, 8, 2), + /* 7 Reserved */ + MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, 0, 13, 10, + 2), + /* 12:14 Reserved */ + MUX(0, "i2s0_mclkout_rx_sel", i2s0_mclkout_rx_p, 0, 13, 15, 1), + + /* CRU_CLKSEL_CON14 */ + FRACT(0, "clk_i2s0_8ch_rx_frac_div", "clk_i2s0_8ch_rx_src", 0, 14), + + /* CRU_CLKSEL_CON15 */ + COMP(0, "clk_i2s1_8ch_tx_src_c", gpll_cpll_npll_p, 0, 15, 0, 7, 8, 2), + /* 7 Reserved */ + MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, 0, 15, 10, + 2), + /* 12:14 Reserved */ + MUX(0, "i2s1_mclkout_tx_sel", i2s1_mclkout_tx_p, 0, 11, 15, 1), + + /* CRU_CLKSEL_CON16 */ + FRACT(0, "clk_i2s1_8ch_tx_frac_div", "clk_i2s1_8ch_tx_src", 0, 16), + + /* CRU_CLKSEL_CON17 */ + COMP(0, "clk_i2s1_8ch_rx_src_c", gpll_cpll_npll_p, 0, 17, 0, 7, 8, 2), + /* 7 Reserved */ + MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, 0, 17, 10, + 2), + /* 12:14 Reserved */ + MUX(0, "i2s1_mclkout_rx_sel", i2s1_mclkout_rx_p, 0, 17, 15, 1), + + /* CRU_CLKSEL_CON18 */ + FRACT(0, "clk_i2s1_8ch_rx_frac_div", "clk_i2s1_8ch_rx_src", 0, 18), + + /* CRU_CLKSEL_CON19 */ + COMP(0, "clk_i2s2_2ch_src_c", gpll_cpll_npll_p, 0, 19, 0, 7, 8, 2), + /* 7 Reserved */ + MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, 0, 19, 10, + 2), + /* 12:14 Reserved */ + MUX(0, "i2s2_mclkout_sel", i2s2_mclkout_p, 0, 19, 15, 1), + + /* CRU_CLKSEL_CON20 */ + FRACT(0, "clk_i2s2_2ch_frac_div", "clk_i2s2_2ch_src", 0, 20), + + /* CRU_CLKSEL_CON21 */ + COMP(0, "clk_i2s3_2ch_tx_src_c", gpll_cpll_npll_p, 0, 21, 0, 7, 8, 2), + /* 7 Reserved */ + MUX(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx", clk_i2s3_2ch_tx_p, 0, 21, 10, + 2), + /* 12:14 Reserved */ + MUX(0, "i2s3_mclkout_tx_sel", i2s3_mclkout_tx_p, 0, 21, 15, 1), + + /* CRU_CLKSEL_CON22 */ + FRACT(0, "clk_i2s3_2ch_tx_frac_div", "clk_i2s3_2ch_tx_src", 0, 22), + + /* CRU_CLKSEL_CON23 */ + COMP(0, "mclk_spdif_8ch_src_c", cpll_gpll_p, 0, 23, 0, 7, 14, 1), + /* 7 Reserved */ + MUX(0, "mclk_pdm_sel", mclk_pdm_p, 0, 23, 8, 2), + MUX(0, "clk_acdcdig_i2c_sel", clk_i2c_p, 0, 23, 10, 2), + /* 12:13 Reserved */ + MUX(MCLK_SPDIF_8CH, "mclk_spdif_8ch", mclk_spdif_8ch_p, 0, 23, 15, + 1), + + /* CRU_CLKSEL_CON24 */ + FRACT(0, "mclk_spdif_8ch_frac_div", "mclk_spdif_8ch_src", 0, 24), + + /* CRU_CLKSEL_CON25 */ + COMP(0, "sclk_audpwm_src_c", gpll_cpll_p, 0, 25, 0, 5, 14, 1), + /* 6:13 Reserved */ + MUX(SCLK_AUDPWM, "sck_audpwm_sel", sclk_audpwm_p, 0, 25, 15, 1), + + /* CRU_CLKSEL_CON26 */ + FRACT(0, "sclk_audpwm_frac_frac", "sclk_audpwm_src", 0, 26), + + /* CRU_CLKSEL_CON27 */ + MUX(0, "aclk_secure_flash_sel", gpll200_gpll150_gpll100_xin24m_p, 0, 27, 0, 2), + MUX(0, "hclk_secure_flash_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 27, 2, 2), + MUX(0, "clk_crypto_ns_core_sel", gpll200_gpll150_gpll100_p, 0, 27, 4, 2), + MUX(0, "clk_crypto_ns_pka_sel", gpll300_gpll200_gpll100_p, 0, 27, 6, 2), + /* 8:15 Reserved */ + + /* CRU_CLKSEL_CON28 */ + MUX(0, "nclk_nandc_sel", clk_nandc_p, 0, 28, 0, 2), + /* 2:3 Reserved */ + MUX(0, "sclk_sfc_sel", sclk_sfc_p, 0, 28, 4, 3), + /* 7 Reserved */ + MUX(0, "bclk_emmc_sel", gpll200_gpll150_cpll125_p, 0, 28, 8, 2), + /* 10:11 Reserved */ + MUX(0, "cclk_emmc_sel", cclk_emmc_p, 0, 28, 12, 3), + /* 15 Reserved */ + + /* CRU_CLKSEL_CON29 */ + MUX(0, "aclk_pipe_sel", aclk_pipe_p, 0, 29, 0, 2), + /* 2:3 Reserved */ + CDIV(0, "pclk_pipe_div", "aclk_pipe", 0, 29, 4, 4), + MUX(0, "clk_usb3otg0_suspend_sel", xin24m_32k_p, 0, 29, 8, 1), + MUX(0, "clk_usb3otg1_suspend_sel", xin24m_32k_p, 0, 29, 9, 1), + /* 10:12 Reserved */ + MUX(0, "clk_xpcs_eee_sel", gpll200_cpll125_p, 0, 29, 13, 1), + /* 14:15 Reserved */ + + /* CRU_CLKSEL_CON30 */ + MUX(0, "aclk_php_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 30, 0, 2), + MUX(0, "hclk_php_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 30, 2, 2), + CDIV(0, "pclk_php_div", "aclk_php", 0, 30, 4, 4), + MUX(0, "clk_sdmmc0_sel", clk_sdmmc_p, 0, 30, 8, 3), + /* 11 Reserved */ + MUX(0, "clk_sdmmc1_sel", clk_sdmmc_p, 0, 30, 12, 3), + /* 15 Reserved */ + + /* CRU_CLKSEL_CON31 */ + MUX(SCLK_GMAC0_RX_TX, "clk_gmac0_rx_tx", mux_gmac0_rx_tx_p, 0, 31, + 0, 2), + MUX(SCLK_GMAC0, "clk_gmac0", mux_gmac0_p, 0, 31, 2, 1), + MUX(SCLK_GMAC0_RMII_SPEED, "clk_gmac0_rmii_speed", + mux_gmac0_rmii_speed_p, 0, 31, 3, 1), + MUX(SCLK_GMAC0_RGMII_SPEED, "clk_gmac0_rgmii_speed", + mux_gmac0_rgmii_speed_p, 0, 31, 4, 2), + MUX(0, "clk_mac0_2top_sel", clk_mac_2top_p, 0, 31, 8, 2), + MUX(0, "clk_gmac0_ptp_ref_sel", clk_gmac_ptp_p, 0, 31, 12, 2), + MUX(0, "clk_mac0_out_sel", cpll125_cpll50_cpll25_xin24m_p, 0, 31, 14, 2), + + FFACT(0, "clk_gmac0_tx_div5", "clk_gmac0", 1, 5), + FFACT(0, "clk_gmac0_tx_div50", "clk_gmac0", 1, 50), + FFACT(0, "clk_gmac0_rx_div2", "clk_gmac0", 1, 2), + FFACT(0, "clk_gmac0_rx_div20", "clk_gmac0", 1, 20), + + /* CRU_CLKSEL_CON32 */ + MUX(0, "aclk_usb_sel", gpll300_gpll200_gpll100_xin24m_p, 0, 32, 0, 2), + MUX(0, "hclk_usb_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 32, 4, 2), + CDIV(0, "pclk_usb_div", "aclk_usb", 0, 32, 4, 4), + MUX(0, "clk_sdmmc2_sel", clk_sdmmc_p, 0, 32, 8, 3), + /* 11:15 Reserved */ + + /* CRU_CLKSEL_CON33 */ + MUX(SCLK_GMAC1_RX_TX, "clk_gmac1_rx_tx", mux_gmac1_rx_tx_p, 0, 33, + 0, 2), + MUX(SCLK_GMAC1, "clk_gmac1", mux_gmac1_p, 0, 33, 2, 1), + MUX(SCLK_GMAC1_RMII_SPEED, "clk_gmac1_rmii_speed", + mux_gmac1_rmii_speed_p, 0, 33, 3, 1), + MUX(SCLK_GMAC1_RGMII_SPEED, "clk_gmac1_rgmii_speed", + mux_gmac1_rgmii_speed_p, 0, 33, 4, 2), + /* 6:7 Reserved */ + MUX(0, "clk_mac1_2top_sel", clk_mac_2top_p, 0, 33, 8, 2), + MUX(0, "clk_gmac1_ptp_ref_sel", clk_gmac_ptp_p, 0, 33, 12, 2), + MUX(0, "clk_mac1_out_sel", cpll125_cpll50_cpll25_xin24m_p, 0, 33, 14, 2), + + FFACT(0, "clk_gmac1_tx_div5", "clk_gmac1", 1, 5), + FFACT(0, "clk_gmac1_tx_div50", "clk_gmac1", 1, 50), + FFACT(0, "clk_gmac1_rx_div2", "clk_gmac1", 1, 2), + FFACT(0, "clk_gmac1_rx_div20", "clk_gmac1", 1, 20), + + /* CRU_CLKSEL_CON34 */ + MUX(0, "aclk_vi_sel", gpll400_gpll300_gpll200_xin24m_p, 0, 34, 0, 2), + /* 2:3 Reserved */ + CDIV(0, "hclk_vi_div", "aclk_vi", 0, 34, 4, 4), + CDIV(0, "pclk_vi_div", "aclk_vi", 0, 34, 8, 4), + /* 12:13 Reserved */ + MUX(0, "dclk_vicap1_sel", cpll333_gpll300_gpll200_p, 0, 34, 14, 2), + + /* CRU_CLKSEL_CON35 */ + COMP(0, "clk_isp_c", cpll_gpll_hpll_p, 0, 35, 0, 5, 6, 2), + /* 5 Reserved */ + COMP(0, "clk_cif_out_c", gpll_usb480m_xin24m_p, 0, 35, 8, 6, 14, 2), + + /* CRU_CLKSEL_CON36 */ + COMP(0, "clk_cam0_out_c", gpll_usb480m_xin24m_p, 0, 36, 0, 6, 6, 2), + COMP(0, "clk_cam1_out_c", gpll_usb480m_xin24m_p, 0, 36, 8, 6, 14, 2), + + /* CRU_CLKSEL_CON37 */ + MUX(0, "aclk_vo_sel", gpll300_cpll250_gpll100_xin24m_p, 0, 37, 0, 2), + /* 2:7 Reserved */ + CDIV(0, "hclk_vo_div", "aclk_vo", 0, 37, 8, 4), + CDIV(0, "pclk_vo_div", "aclk_vo", 0, 37, 12, 4), + + /* CRU_CLKSEL_CON38 */ + COMP(0, "aclk_vop_pre_c", cpll_gpll_hpll_vpll_p, 0, 38, 0, 5, 6, 2), + /* 5 Reserved */ + MUX(0, "clk_edp_200m_sel", gpll200_gpll150_cpll125_p, 0, 38, 8, 2), + /* 10:15 Reserved */ + + /* CRU_CLKSEL_CON39 */ + COMP(0, "dclk_vop0_c", hpll_vpll_gpll_cpll_p, 0, 39, 0, 8, 10, 2), + /* 12:15 Reserved */ + + /* CRU_CLKSEL_CON40 */ + COMP(0, "dclk_vop1_c", hpll_vpll_gpll_cpll_p, 0, 40, 0, 8, 10, 2), + /* 12:15 Reserved */ + + /* CRU_CLKSEL_CON41 */ + COMP(0, "dclk_vop2_c", hpll_vpll_gpll_cpll_p, 0, 41, 0, 8, 10, 2), + /* 12:15 Reserved */ + + /* CRU_CLKSEL_CON42 */ + COMP(0, "aclk_vpu_pre_c", gpll_cpll_p, 0, 42, 0, 5, 7, 1), + /* 5:6 Reserved */ + CDIV(0, "hclk_vpu_pre_div", "aclk_vpu_pre", 0, 42, 8, 4), + /* 12:15 Reserved */ + + /* CRU_CLKSEL_CON43 */ + MUX(0, "aclk_rga_pre_sel", gpll300_cpll250_gpll100_xin24m_p, 0, 43, 0, 2), + MUX(0, "clk_rga_core_sel", gpll300_gpll200_gpll100_p, 0, 43, 2, 2), + MUX(0, "clk_iep_core_sel", gpll300_gpll200_gpll100_p, 0, 43, 4, 2), + MUX(0, "dclk_ebc_sel", gpll400_cpll333_gpll200_p, 0, 43, 6, 2), + CDIV(0, "hclk_rga_pre_div", "aclk_rga_pre", 0, 43, 8, 4), + CDIV(0, "pclk_rga_pre_div", "aclk_rga_pre", 0, 43, 12, 4), + + /* CRU_CLKSEL_CON44 */ + COMP(0, "aclk_rkvenc_pre_c", gpll_cpll_npll_p, 0, 44, 0, 5, 6, 2), + /* 5 Reserved */ + CDIV(0, "hclk_rkvenc_pre_div", "aclk_rkvenc_pre", 0, 44, 8, 4), + /* 12:15 Reserved */ + + /* CRU_CLKSEL_CON45 */ + COMP(0, "clk_rkvenc_core_c", gpll_cpll_npll_vpll_p, 0, 45, 0, 5, 14, 2), + /* 5:13 Reserved */ + + /* CRU_CLKSEL_CON46 */ + + /* CRU_CLKSEL_CON47 */ + COMP(0, "aclk_rkvdec_pre_c", aclk_rkvdec_pre_p, 0, 47, 0, 5, 7, 1), + /* 5:6 Reserved */ + CDIV(0, "hclk_rkvdec_pre_div", "aclk_rkvdec_pre", 0, 47, 8, 4), + /* 12:15 Reserved */ + + /* CRU_CLKSEL_CON48 */ + COMP(0, "clk_rkvdec_ca_c", gpll_cpll_npll_vpll_p, 0, 48, 0, 5, 6, 2), + /* 5 Reserved */ + /* 8:15 Reserved */ + + /* CRU_CLKSEL_CON49 */ + COMP(0, "clk_rkvdec_hevc_ca_c", gpll_cpll_npll_vpll_p, 0, 49, 0, 5, 6, 2), + /* 5 Reserved */ + COMP(0, "clk_rkvdec_core_c", clk_rkvdec_core_p, 0, 49, 8, 5, 14, 2), + /* 13 Reserved */ + + /* CRU_CLKSEL_CON50 */ + MUX(0, "aclk_bus_sel", gpll200_gpll150_gpll100_xin24m_p, 0, 50, 0, 2), + /* 2:3 Reserved */ + MUX(0, "pclk_bus_sel", gpll100_gpll75_cpll50_xin24m_p, 0, 50, 4, 2), + /* 6:15 Reserved */ + + /* CRU_CLKSEL_CON51 */ + COMP(0, "clk_tsadc_tsen_c", xin24m_gpll100_cpll100_p, 0, 51, 0, 3, 4, 2), + /* 6:7 Reserved */ + CDIV(0, "clk_tsadc_div", "clk_tsadc_tsen", 0, 51, 8, 7), + /* 15 Reserved */ + + /* CRU_CLKSEL_CON52 */ + COMP(0, "clk_uart1_src_c", gpll_cpll_usb480m_p, 0, 52, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart1_sel", sclk_uart1_p, 0, 52, 12, 2), + + /* CRU_CLKSEL_CON53 */ + FRACT(0, "clk_uart1_frac_frac", "clk_uart1_src", 0, 53), + + /* CRU_CLKSEL_CON54 */ + COMP(0, "clk_uart2_src_c", gpll_cpll_usb480m_p, 0, 54, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart2_sel", sclk_uart2_p, 0, 52, 12, 2), + + /* CRU_CLKSEL_CON55 */ + FRACT(0, "clk_uart2_frac_frac", "clk_uart2_src", 0, 55), + + /* CRU_CLKSEL_CON56 */ + COMP(0, "clk_uart3_src_c", gpll_cpll_usb480m_p, 0, 54, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart3_sel", sclk_uart3_p, 0, 56, 12, 2), + + /* CRU_CLKSEL_CON57 */ + FRACT(0, "clk_uart3_frac_frac", "clk_uart3_src", 0, 57), + + /* CRU_CLKSEL_CON58 */ + COMP(0, "clk_uart4_src_c", gpll_cpll_usb480m_p, 0, 58, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart4_sel", sclk_uart4_p, 0, 58, 12, 2), + + /* CRU_CLKSEL_CON59 */ + FRACT(0, "clk_uart4_frac_frac", "clk_uart4_src", 0, 59), + + /* CRU_CLKSEL_CON60 */ + COMP(0, "clk_uart5_src_c", gpll_cpll_usb480m_p, 0, 60, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart5_sel", sclk_uart5_p, 0, 60, 12, 2), + + /* CRU_CLKSEL_CON61 */ + FRACT(0, "clk_uart5_frac_frac", "clk_uart5_src", 0, 61), + + /* CRU_CLKSEL_CON62 */ + COMP(0, "clk_uart6_src_c", gpll_cpll_usb480m_p, 0, 62, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart6_sel", sclk_uart6_p, 0, 62, 12, 2), + + /* CRU_CLKSEL_CON63 */ + FRACT(0, "clk_uart6_frac_frac", "clk_uart6_src", 0, 63), + + /* CRU_CLKSEL_CON64 */ + COMP(0, "clk_uart7_src_c", gpll_cpll_usb480m_p, 0, 64, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart7_sel", sclk_uart7_p, 0, 64, 12, 2), + + /* CRU_CLKSEL_CON65 */ + FRACT(0, "clk_uart7_frac_frac", "clk_uart7_src", 0, 65), + + /* CRU_CLKSEL_CON66 */ + COMP(0, "clk_uart8_src_c", gpll_cpll_usb480m_p, 0, 66, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart8_sel", sclk_uart8_p, 0, 66, 12, 2), + + /* CRU_CLKSEL_CON67 */ + FRACT(0, "clk_uart8_frac_frac", "clk_uart8_src", 0, 67), + + /* CRU_CLKSEL_CON68 */ + COMP(0, "clk_uart9_src_c", gpll_cpll_usb480m_p, 0, 68, 0, 7, 8, 2), + /* 7 Reserved */ + /* 10:11 Reserved */ + MUX(0, "sclk_uart9_sel", sclk_uart9_p, 0, 68, 12, 2), + + /* CRU_CLKSEL_CON69 */ + FRACT(0, "clk_uart9_frac_frac", "clk_uart9_src", 0, 69), + + /* CRU_CLKSEL_CON70 */ + COMP(0, "clk_can0_c", gpll_cpll_p, 0, 70, 0, 5, 7, 1), + /* 5:6 Reserved */ + COMP(0, "clk_can1_c", gpll_cpll_p, 0, 70, 8, 5, 15, 1), + /* 13:14 Reserved */ + + /* CRU_CLKSEL_CON71 */ + COMP(0, "clk_can2_c", gpll_cpll_p, 0, 71, 0, 5, 7, 1), + /* 5:6 Reserved */ + MUX(0, "clk_i2c_sel", clk_i2c_p, 0, 71, 8, 2), + /* 10:15 Reserved */ + + /* CRU_CLKSEL_CON72 */ + MUX(0, "clk_spi0_sel", gpll200_xin24m_cpll100_p, 0, 72, 0, 2), + MUX(0, "clk_spi1_sel", gpll200_xin24m_cpll100_p, 0, 72, 2, 2), + MUX(0, "clk_spi2_sel", gpll200_xin24m_cpll100_p, 0, 72, 4, 2), + MUX(0, "clk_spi3_sel", gpll200_xin24m_cpll100_p, 0, 72, 6, 2), + MUX(0, "clk_pwm1_sel", gpll100_xin24m_cpll100_p, 0, 72, 8, 2), + MUX(0, "clk_pwm2_sel", gpll100_xin24m_cpll100_p, 0, 72, 10, 2), + MUX(0, "clk_pwm3_sel", gpll100_xin24m_cpll100_p, 0, 72, 12, 2), + MUX(0, "dbclk_gpio_sel", xin24m_32k_p, 0, 72, 14, 1), + /* 15 Reserved */ + + /* CRU_CLKSEL_CON73 */ + MUX(0, "aclk_top_high_sel", cpll500_gpll400_gpll300_xin24m_p, 0, 73, 0, 2), + /* 2:3 Reserved */ + MUX(0, "aclk_top_low_sel", gpll400_gpll300_gpll200_xin24m_p, 0, 73, 4, 2), + /* 6:7 Reserved */ + MUX(0, "hclk_top_sel", gpll150_gpll100_gpll75_xin24m_p, 0, 73, 8, 2), + /* 10:11 Reserved */ + MUX(0, "pclk_top_sel", gpll100_gpll75_cpll50_xin24m_p, 0, 73, 12, 2), + /* 14 Reserved */ + MUX(0, "clk_optc_arb_sel", xin24m_cpll100_p, 0, 73, 15 , 1), + + /* CRU_CLKSEL_CON74 */ + /* 0:7 clk_testout_div CDIV */ + /* 8:12 clk_testout_sel MUX */ + + /* CRU_CLKSEL_CON75 */ + CDIV(0, "clk_gpll_div_400m_div", "gpll", 0, 75, 0, 5), + CDIV(0, "clk_gpll_div_300m_div", "gpll", 0, 75, 8, 5), + + /* CRU_CLKSEL_CON76 */ + CDIV(0, "clk_gpll_div_200m_div", "gpll", 0, 76, 0, 5), + CDIV(0, "clk_gpll_div_150m_div", "gpll", 0, 76, 8, 5), + + /* CRU_CLKSEL_CON77 */ + CDIV(0, "clk_gpll_div_100m_div", "gpll", 0, 77, 0, 5), + CDIV(0, "clk_gpll_div_75m_div", "gpll", 0, 77, 8, 5), + + /* CRU_CLKSEL_CON78 */ + CDIV(0, "clk_gpll_div_20m_div", "gpll", 0, 78, 0, 6), + CDIV(0, "clk_cpll_div_500m_div", "cpll", 0, 78, 8, 5), + + /* CRU_CLKSEL_CON79 */ + CDIV(0, "clk_cpll_div_333m_div", "cpll", 0, 79, 0, 6), + CDIV(0, "clk_cpll_div_250m_div", "cpll", 0, 79, 8, 5), + + /* CRU_CLKSEL_CON80 */ + CDIV(0, "clk_cpll_div_125m_div", "cpll", 0, 80, 0, 6), + CDIV(0, "clk_cpll_div_62P5m_div", "cpll", 0, 80, 8, 5), + + /* CRU_CLKSEL_CON81 */ + CDIV(0, "clk_cpll_div_50m_div", "cpll", 0, 81, 0, 6), + CDIV(0, "clk_cpll_div_25m_div", "cpll", 0, 81, 8, 5), + + /* CRU_CLKSEL_CON82 */ + CDIV(0, "clk_cpll_div_100m_div", "cpll", 0, 82, 0, 6), + CDIV(0, "clk_osc0_div_750k_div", "xin24m", 0, 82, 8, 5), + + /* CRU_CLKSEL_CON83 */ + CDIV(0, "clk_i2s3_2ch_rx_src_div", "clk_i2s3_2ch_rx_src_sel", 0, 83, 0, 7), + /* 7 Reserved */ + MUX(0, "clk_i2s3_2ch_rx_src_sel", gpll_cpll_npll_p, 0, 83, 8, 2), + MUX(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx", clk_i2s3_2ch_rx_p, 0, 83, 10, + 2), + /* 12:14 Reserved */ + MUX(0, "i2s3_mclkout_rx_sel", i2s3_mclkout_rx_p, 0, 83, 15, 1), + + /* CRU_CLKSEL_CON84 */ + FRACT(0, "clk_i2s3_2ch_rx_frac_div", "clk_i2s3_2ch_rx_src", 0, 84), +}; + +/* GATES */ +static struct rk_cru_gate rk3568_gates[] = { + /* CRU_CLKGATE_CON00 */ + /* 0 clk_core */ + /* 1 clk_core0 */ + /* 2 clk_core1 */ + /* 3 clk_core2 */ + /* 4 clk_core3 */ + GATE(0, "sclk_core_src", "sclk_core_src_c", 0, 5), + /* 6 clk_npll_core */ + /* 7 sclk_core */ + GATE(0, "atclk_core", "atclk_core_div", 0, 8), + GATE(0, "gicclk_core", "gicclk_core_div", 0, 9), + GATE(0, "pclk_core_pre", "pclk_core_pre_div", 0, 10), + GATE(0, "periphclk_core_pre", "periphclk_core_pre_div", 0, 11), + /* 12 pclk_core */ + /* 13 periphclk_core */ + /* 14 tsclk_core */ + /* 15 cntclk_core */ + + /* CRU_CLKGATE_CON01 */ + /* 0 aclk_core */ + /* 1 aclk_core_biuddr */ + /* 2 aclk_core_biu2bus */ + /* 3 pclk_dgb_biu */ + /* 4 pclk_dbg */ + /* 5 pclk_dbg_daplite */ + /* 6 aclk_adb400_core2gic */ + /* 7 aclk_adb400_gic2core */ + /* 8 pclk_core_grf */ + GATE(PCLK_CORE_PVTM, "pclk_core_pvtm", "pclk_core_pre", 1, 9), + GATE(CLK_CORE_PVTM, "clk_core_pvtm", "xin24m", 1, 10), + GATE(CLK_CORE_PVTM_CORE, "clk_core_pvtm_core", "armclk", 1, 11), + GATE(CLK_CORE_PVTPLL, "clk_core_pvtpll", "armclk", 1, 12), + /* 13 clk_core_div2 */ + /* 14 clk_apll_core */ + /* 15 clk_jtag */ + + /* CRU_CLKGATE_CON02 */ + /* 0 clk_gpu_src */ + GATE(CLK_GPU_SRC, "clk_gpu_src", "clk_gpu_pre_c", 2, 0), + /* 1 Reserved */ + GATE(PCLK_GPU_PRE, "pclk_gpu_pre", "pclk_gpu_pre_div", 2, 2), + GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre_c", 2, 3), + /* 4 aclk_gpu_biu */ + /* 5 pclk_gpu_biu */ + GATE(PCLK_GPU_PVTM, "pclk_gpu_pvtm", "pclk_gpu_pre", 2, 6), + GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 2, 7), + GATE(CLK_GPU_PVTM_CORE, "clk_gpu_pvtm_core", "clk_gpu_src", 2, 8), + GATE(CLK_GPU_PVTPLL, "clk_gpu_pvtpll", "clk_gpu_src", 2, 9), + /* 10 clk_gpu_div2 */ + GATE(ACLK_GPU_PRE, "aclk_gpu_pre", "aclk_gpu_pre_div", 2, 11), + /* 12:15 Reserved */ + + /* CRU_CLKGATE_CON03 */ + GATE(CLK_NPU_SRC, "clk_npu_src", "clk_npu_src_c", 3, 0), + GATE(CLK_NPU_NP5, "clk_npu_np5", "clk_npu_np5_c", 3, 1), + GATE(HCLK_NPU_PRE, "hclk_npu_pre", "hclk_npu_pre_div", 3, 2), + GATE(PCLK_NPU_PRE, "pclk_npu_pre", "pclk_npu_pre_div", 3, 3), + /* 4 aclk_npu_biu */ + GATE(ACLK_NPU_PRE, "aclk_npu_pre", "clk_npu", 3, 4), + /* 5 hclk_npu_biu */ + /* 6 pclk_npu_biu */ + GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 3, 7), + GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 3, 8), + GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_pre", 3, 9), + GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 3, 10), + GATE(CLK_NPU_PVTM_CORE, "clk_npu_pvtm_core", "clk_npu_pre_ndft",3, 11), + GATE(CLK_NPU_PVTPLL, "clk_npu_pvtpll", "clk_npu_pre_ndft", 3, 12), + /* 13 clk_npu_div2 */ + /* 14:15 Reserved */ + + /* CRU_CLKGATE_CON04 */ + GATE(CLK_DDRPHY1X_SRC, "clk_ddrphy1x_src", "clk_ddrphy1x_src_c", 4, 0), + /* 1 clk_dpll_ddr */ + GATE(CLK_MSCH, "clk_msch", "clk_msch_div", 4, 2), + /* 3 clk_hwffc_ctrl */ + /* 4 aclk_ddrscramble */ + /* 5 aclk_msch */ + /* 6 clk_ddr_alwayson */ + /* 7 Reserved */ + /* 8 aclk_ddrsplit */ + /* 9 clk_ddrdft_ctl */ + /* 10 Reserved */ + /* 11 aclk_dma2ddr */ + /* 12 Reserved */ + /* 13 clk_ddrmon */ + /* 14 Reserved */ + GATE(CLK24_DDRMON, "clk24_ddrmon", "xin24m", 4, 15), + + /* CRU_CLKGATE_CON05 */ + GATE(ACLK_GIC_AUDIO, "aclk_gic_audio", "aclk_gic_audio_sel", 5, 0), + GATE(HCLK_GIC_AUDIO, "hclk_gic_audio", "hclk_gic_audio_sel", 5, 1), + /* 2 aclk_gic_audio_biu */ + /* 3 hclk_gic_audio_biu */ + GATE(ACLK_GIC600, "aclk_gic600", "aclk_gic_audio", 5, 4), + /* 5 aclk_gicadb_core2gic */ + /* 6 aclk_gicadb_gic2core */ + GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_gic_audio", 5, 7), + GATE(HCLK_SDMMC_BUFFER, "hclk_sdmmc_buffer", "hclk_gic_audio", 5, 8), + GATE(DCLK_SDMMC_BUFFER, "dclk_sdmmc_buffer", "dclk_sdmmc_buffer_sel", 5, 9), + GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_gic_audio", 5, 10), + GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_gic_audio", 5, 11), + GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_gic_audio", 5, 12), + GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_gic_audio", 5, 13), + GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 5, 14), + GATE(MCLK_PDM, "mclk_pdm", "mclk_pdm_sel", 5, 15), + + /* CRU_CLKGATE_CON06 */ + GATE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_src_c", 6, 0), + GATE(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_frac_div", 6, 1), + GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 6, 2), + GATE(I2S0_MCLKOUT_TX, "i2s0_mclkout_tx", "i2s0_mclkout_tx_sel", 6, 3), + GATE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_src_c", 6, 4), + GATE(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_frac_div", 6, 5), + GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 6, 6), + GATE(I2S0_MCLKOUT_RX, "i2s0_mclkout_rx", "i2s0_mclkout_rx_sel", 6, 7), + GATE(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_src_c", 6, 8), + GATE(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_frac_div", 6, 9), + GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 6, 10), + GATE(I2S1_MCLKOUT_TX, "i2s1_mclkout_tx", "i2s1_mclkout_tx_sel", 6, 11), + GATE(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_src_c", 6, 12), + GATE(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_frac_div", 6, 13), + GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 6, 14), + GATE(I2S1_MCLKOUT_RX, "i2s1_mclkout_rx", "i2s1_mclkout_rx_sel", 6, 15), + + /* CRU_CLKGATE_CON07 */ + GATE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", "clk_i2s2_2ch_src_c", 7, 0), + GATE(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_frac_div", 7, 1), + GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 7, 2), + GATE(I2S2_MCLKOUT, "i2s2_mclkout", "i2s2_mclkout_sel", 7, 3), + GATE(CLK_I2S3_2CH_TX, "clk_i2s3_2ch_tx_src", "clk_i2s3_2ch_tx_src_c", 7, 4), + GATE(CLK_I2S3_2CH_TX_FRAC, "clk_i2s3_2ch_tx_frac", "clk_i2s3_2ch_tx_frac_div", 7, 5), + GATE(MCLK_I2S3_2CH_TX, "mclk_i2s3_2ch_tx", "clk_i2s3_2ch_tx", 7, 6), + GATE(I2S3_MCLKOUT_TX, "i2s3_mclkout_tx", "i2s3_mclkout_tx_sel", 7, 7), + GATE(CLK_I2S3_2CH_RX, "clk_i2s3_2ch_rx_src", "clk_i2s3_2ch_rx_src_div", 7, 8), + GATE(CLK_I2S3_2CH_RX_FRAC, "clk_i2s3_2ch_rx_frac", "clk_i2s3_2ch_rx_frac_div", 7, 9), + GATE(MCLK_I2S3_2CH_RX, "mclk_i2s3_2ch_rx", "clk_i2s3_2ch_rx", 7, 10), + GATE(I2S3_MCLKOUT_RX, "i2s3_mclkout_rx", "i2s3_mclkout_rx_sel", 7, 11), + GATE(HCLK_VAD, "hclk_vad", "hclk_gic_audio", 7, 12), + GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_gic_audio", 7, 13), + GATE(MCLK_SPDIF_8CH_SRC, "mclk_spdif_8ch_src", "mclk_spdif_8ch_src_c", 7, 14), + GATE(MCLK_SPDIF_8CH_FRAC, "mclk_spdif_8ch_frac", "mclk_spdif_8ch_frac_div", 7, 15), + + /* CRU_CLKGATE_CON08 */ + GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_gic_audio", 8, 0), + GATE(SCLK_AUDPWM_SRC, "sclk_audpwm_src", "sclk_audpwm_src_c", 8, 1), + GATE(SCLK_AUDPWM_FRAC, "sclk_audpwm_frac", "sclk_audpwm_frac_frac", 8, 2), + GATE(HCLK_ACDCDIG, "hclk_acdcdig", "hclk_gic_audio", 8, 3), + GATE(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", "clk_acdcdig_i2c_sel", 8, 4), + GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s3_2ch_tx", 8, 5), + GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s3_2ch_rx", 8, 6), + GATE(ACLK_SECURE_FLASH, "aclk_secure_flash", "aclk_secure_flash_sel", 8, 7), + GATE(HCLK_SECURE_FLASH, "hclk_secure_flash", "hclk_secure_flash_sel", 8, 8), + /* 9 aclk_secure_flash_biu */ + /* 10 hclk_secure_flash_biu */ + GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_flash", 8, 11), + GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_flash", 8, 12), + GATE(CLK_CRYPTO_NS_CORE, "clk_crypto_ns_core", "clk_crypto_ns_core_sel", 8, 13), + GATE(CLK_CRYPTO_NS_PKA, "clk_crypto_ns_pka", "clk_crypto_ns_pka_sel", 8, 14), + GATE(CLK_CRYPTO_NS_RNG, "clk_crypto_ns_rng", "hclk_secure_flash", 8, 15), + + /* CRU_CLKGATE_CON09 */ + GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 9, 0), + GATE(NCLK_NANDC, "nclk_nandc", "nclk_nandc_sel", 9, 1), + GATE(HCLK_SFC, "hclk_sfc", "hclk_secure_flash", 9, 2), + GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_secure_flash", 9, 3), + GATE(SCLK_SFC, "sclk_sfc", "sclk_sfc_sel", 9, 4), + GATE(ACLK_EMMC, "aclk_emmc", "aclk_secure_flash", 9, 5), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_secure_flash", 9, 6), + GATE(BCLK_EMMC, "bclk_emmc", "bclk_emmc_sel", 9, 7), + GATE(CCLK_EMMC, "cclk_emmc", "cclk_emmc_sel", 9, 8), + GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 9, 9), + GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_flash", 9, 10), + GATE(CLK_TRNG_NS, "clk_trng_ns", "hclk_secure_flash", 9, 11), + /* 12:15 Reserved */ + + /* CRU_CLKGATE_CON10 */ + GATE(ACLK_PIPE, "aclk_pipe", "aclk_pipe_sel", 10, 0), + GATE(PCLK_PIPE, "pclk_pipe", "pclk_pipe_div", 10, 1), + /* 2 aclk_pipe_biu */ + /* 3 pclk_pipe_biu */ + GATE(CLK_XPCS_EEE, "clk_xpcs_eee", "clk_xpcs_eee_sel", 10, 4), + /* 5 clk_xpcs_rx_div10 */ + /* 6 clk_xpcs_tx_div10 */ + /* 7 pclk_pipe_grf */ + GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_pipe", 10, 8), + GATE(CLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 10, 9), + GATE(CLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", "clk_usb3otg0_suspend_sel", 10, 10), + /* 11 clk_usb3otg0_pipe */ + GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_pipe", 10, 12), + GATE(CLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 10, 13), + GATE(CLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", "clk_usb3otg1_suspend_sel", 10, 14), + /* 15 clk_usb3otg1_pipe */ + + /* CRU_CLKGATE_CON11 */ + GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 11, 0), + GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "clk_gpll_div_20m", 11, 1), + GATE(CLK_SATA0_RXOOB, "clk_sata0_rxoob", "clk_cpll_div_50m", 11, 2), + /* 3 clk_sata0_pipe */ + GATE(ACLK_SATA1, "aclk_sata1", "aclk_pipe", 11, 4), + GATE(CLK_SATA1_PMALIVE, "clk_sata1_pmalive", "clk_gpll_div_20m", 11, 5), + GATE(CLK_SATA1_RXOOB, "clk_sata1_rxoob", "clk_cpll_div_50m", 11, 6), + /* 7 clk_sata1_pipe */ + GATE(ACLK_SATA2, "aclk_sata2", "aclk_pipe", 11, 8), + GATE(CLK_SATA2_PMALIVE, "clk_sata2_pmalive", "clk_gpll_div_20m", 11, 9), + GATE(CLK_SATA2_RXOOB, "clk_sata2_rxoob", "clk_cpll_div_50m", 11, 10), + /* 11 clk_sata2_pipe */ + /* 12:15 Reserved */ + + /* CRU_CLKGATE_CON12 */ + GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_pipe", 12, 0), + GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_pipe", 12, 1), + GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_pipe", 12, 2), + GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_pipe", 12, 3), + GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 12, 4), + /* 5 clk_pcie20_pipe */ + /* 6:7 Reserved */ + GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 12, 8), + GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 12, 9), + GATE(ACLK_PCIE30X1_DBI, "aclk_pcie30x1_dbi", "aclk_pipe", 12, 10), + GATE(PCLK_PCIE30X1, "pclk_pcie30x1", "pclk_pipe", 12, 11), + GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 12, 12), + /* 13 clk_pcie30x1_pipe */ + /* 14:15 Reserved */ + + /* CRU_CLKGATE_CON13 */ + GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 13, 0), + GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 13, 1), + GATE(ACLK_PCIE30X2_DBI, "aclk_pcie30x2_dbi", "aclk_pipe", 13, 2), + GATE(PCLK_PCIE30X2, "pclk_pcie30x2", "pclk_pipe", 13, 3), + GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 13, 4), + /* 5 clk_pcie30x2_pipe */ + GATE(PCLK_XPCS, "pclk_xpcs", "pclk_pipe", 13, 6), + /* 7 clk_xpcs_qsgmii_tx */ + /* 8 clk_xpcs_qsgmii_rx */ + /* 9 clk_xpcs_xgxs_tx */ + /* 10 Reserved */ + /* 11 clk_xpcs_xgxs_rx */ + /* 12 clk_xpcs_mii0_tx */ + /* 13 clk_xpcs_mii0_rx */ + /* 14 clk_xpcs_mii1_tx */ + /* 15 clk_xpcs_mii1_rx */ + + /* CRU_CLKGATE_CON14 */ + GATE(ACLK_PERIMID, "aclk_perimid", "aclk_perimid_sel", 14, 0), + GATE(HCLK_PERIMID, "hclk_perimid", "hclk_perimid_sel", 14, 1), + /* 2 aclk_perimid_biu */ + /* 3 hclk_perimid_biu */ + /* 4:7 Reserved */ + GATE(ACLK_PHP, "aclk_php", "aclk_php_sel", 14, 8), + GATE(HCLK_PHP, "hclk_php", "hclk_php_sel", 14, 9), + GATE(PCLK_PHP, "pclk_php", "pclk_php_div", 14, 10), + /* 11 aclk_php_biu */ + /* 12 hclk_php_biu */ + /* 13 pclk_php_biu */ + /* 14:15 Reserved */ + + /* CRU_CLKGATE_CON15 */ + GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_php", 15, 0), + GATE(CLK_SDMMC0, "clk_sdmmc0", "clk_sdmmc0_sel", 15, 1), + GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_php", 15, 2), + GATE(CLK_SDMMC1, "clk_sdmmc1", "clk_sdmmc1_sel", 15, 3), + GATE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", "clk_gmac0_ptp_ref_sel", 15, 4), + GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_php", 15, 5), + GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php", 15, 6), + GATE(CLK_MAC0_2TOP, "clk_mac0_2top", "clk_mac0_2top_sel", 15, 7), + GATE(CLK_MAC0_OUT, "clk_mac0_out", "clk_mac0_out_sel", 15, 8), + /* 9:11 Reserved */ + GATE(CLK_MAC0_REFOUT, "clk_mac0_refout", "clk_mac0_2top", 15, 12), + /* 13:15 Reserved */ + + /* CRU_CLKGATE_CON16 */ + GATE(ACLK_USB, "aclk_usb", "aclk_usb_sel", 16, 0), + GATE(HCLK_USB, "hclk_usb", "hclk_usb_sel", 16, 1), + GATE(PCLK_USB, "pclk_usb", "pclk_usb_div", 16, 2), + /* 3 aclk_usb_biu */ + /* 4 hclk_usb_biu */ + /* 5 pclk_usb_biu */ + /* 6 pclk_usb_grf */ + /* 7:11 Reserved */ + GATE(HCLK_USB2HOST0, "hclk_usb2host0", "hclk_usb", 16, 12), + GATE(HCLK_USB2HOST0_ARB, "hclk_usb2host0_arb", "hclk_usb", 16, 13), + GATE(HCLK_USB2HOST1, "hclk_usb2host1", "hclk_usb", 16, 14), + GATE(HCLK_USB2HOST1_ARB, "hclk_usb2host1_arb", "hclk_usb", 16, 15), + + /* CRU_CLKGATE_CON17 */ + GATE(HCLK_SDMMC2, "hclk_sdmmc2", "hclk_usb", 17, 0), + GATE(CLK_SDMMC2, "clk_sdmmc2", "clk_sdmmc2_sel", 17, 1), + GATE(CLK_GMAC1_PTP_REF, "clK_gmac1_ptp_ref", "clk_gmac1_ptp_ref_sel", 17, 2), + GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_usb", 17, 3), + GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_usb", 17, 4), + GATE(CLK_MAC1_2TOP, "clk_mac1_2top", "clk_mac1_2top_sel", 17, 5), + GATE(CLK_MAC1_OUT, "clk_mac1_out", "clk_mac1_out_sel", 17, 6), + /* 7:9 Reserved */ + GATE(CLK_MAC1_REFOUT, "clk_mac1_refout", "clk_mac1_2top", 17, 10), + /* 11:15 Reserved */ + + /* CRU_CLKGATE_CON18 */ + GATE(ACLK_VI, "aclk_vi", "aclk_vi_sel", 18, 0), + GATE(HCLK_VI, "hclk_vi", "hclk_vi_div", 18, 1), + GATE(PCLK_VI, "pclk_vi", "pclk_vi_div", 18, 2), + /* 3 aclk_vi_biu */ + /* 4 hclk_vi_biu */ + /* 5 pclk_vi_biu */ + /* 6:8 Reserved */ + GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi", 18, 9), + GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 18, 10), + GATE(DCLK_VICAP, "dclk_vicap", "dclk_vicap1_sel", 18, 11), + /* 12:15 Reserved */ + + /* CRU_CLKGATE_CON19 */ + GATE(ACLK_ISP, "aclk_isp", "aclk_vi", 19, 0), + GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 19, 1), + GATE(CLK_ISP, "clk_isp", "clk_isp_c", 19, 2), + /* 3 Reserved */ + GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi", 19, 4), + /* 5:7 Reserved */ + GATE(CLK_CIF_OUT, "clk_cif_out", "clk_cif_out_c", 19, 8), + GATE(CLK_CAM0_OUT, "clk_cam0_out", "clk_cam0_out_c", 19, 9), + GATE(CLK_CAM1_OUT, "clk_cam1_out", "clk_cam1_out_c", 19, 9), + /* 11:15 Reserved */ + + /* CRU_CLKGATE_CON20 */ + /* 0 Reserved or aclk_vo ??? */ + GATE(ACLK_VO, "aclk_vo", "aclk_vo_sel", 20, 0), + GATE(HCLK_VO, "hclk_vo", "hclk_vo_div", 20, 1), + GATE(PCLK_VO, "pclk_vo", "pclk_vo_div", 20, 2), + /* 3 aclk_vo_biu */ + /* 4 hclk_vo_biu */ + /* 5 pclk_vo_biu */ + GATE(ACLK_VOP_PRE, "aclk_vop_pre", "aclk_vop_pre_c", 20, 6), + /* 7 aclk_vop_biu */ + GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 20, 8), + GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 20, 9), + GATE(DCLK_VOP0, "dclk_vop0", "dclk_vop0_c", 20, 10), + GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop1_c", 20, 11), + GATE(DCLK_VOP2, "dclk_vop2", "dclk_vop2_c", 20, 12), + GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 20, 13), + /* 14:15 Reserved */ + + /* CRU_CLKGATE_CON21 */ + GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 21, 0), + GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo", 21, 1), + GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo", 21, 2), + GATE(PCLK_HDMI_HOST, "pclk_hdmi_host", "pclk_vo", 21, 3), + GATE(CLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 21, 4), + GATE(CLK_HDMI_CEC, "clk_hdmi_cec", "clk_rtc_32k", 21, 5), + GATE(PCLK_DSITX_0, "pclk_dsitx_0", "pclk_vo", 21, 6), + GATE(PCLK_DSITX_1, "pclk_dsitx_1", "pclk_vo", 21, 7), + GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_vo", 21, 8), + GATE(CLK_EDP_200M, "clk_edp_200m", "clk_edp_200m_sel", 21, 9), + /* 10:15 Reserved */ + + /* CRU_CLKGATE_CON22 */ + GATE(ACLK_VPU_PRE, "aclk_vpu_pre", "aclk_vpu_pre_c", 22, 0), + GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre_c", 22, 1), + /* 2 aclk_vpu_biu */ + /* 3 hclk_vpu_biu */ + GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 22, 4), + GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 22, 5), + /* 6:11 Reserved */ + GATE(PCLK_RGA_PRE, "pclk_rga_pre", "pclk_rga_pre_div", 22, 12), + /* 13 pclk_rga_biu */ + GATE(PCLK_EINK, "pclk_eink", "pclk_rga_pre", 22, 14), + GATE(HCLK_EINK, "hclk_eink", "hclk_rga_pre", 22, 15), + + /* CRU_CLKGATE_CON23 */ + GATE(ACLK_RGA_PRE, "aclk_rga_pre", "aclk_rga_pre_sel", 23, 0), + GATE(HCLK_RGA_PRE, "hclk_rga_pre", "hclk_rga_pre_div", 23, 1), + /* 2 aclk_rga_biu */ + /* 3 hclk_rga_biu */ + GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 23, 4), + GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 23, 5), + GATE(CLK_RGA_CORE, "clk_rga_core", "clk_rga_core_sel", 23, 6), + GATE(ACLK_IEP, "aclk_iep", "aclk_rga_pre", 23, 7), + GATE(HCLK_IEP, "hclk_iep", "hclk_rga_pre", 23, 8), + GATE(CLK_IEP_CORE, "clk_iep_core", "clk_iep_core_sel", 23, 9), + GATE(HCLK_EBC, "hclk_ebc", "hclk_rga_pre", 23, 10), + GATE(DCLK_EBC, "dclk_ebc", "dclk_ebc_sel", 23, 11), + GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_pre", 23, 12), + GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 23, 13), + GATE(ACLK_JENC, "aclk_jenc", "aclk_rga_pre", 23, 14), + GATE(HCLK_JENC, "hclk_jenc", "hclk_rga_pre", 23, 15), + + /* CRU_CLKGATE_CON24 */ + GATE(ACLK_RKVENC_PRE, "aclk_rkvenc_pre", "aclk_rkvenc_pre_c", 24, 0), + GATE(HCLK_RKVENC_PRE, "hclk_rkvenc_pre", "hclk_rkvenc_pre_div", 24, 1), + /* 2 Reserved */ + /* 3 aclk_rkvenc_biu */ + /* 4 hclk_rkvenc_biu */ + /* 5 Reserved */ + GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_pre", 24, 6), + GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_pre", 24, 7), + GATE(CLK_RKVENC_CORE, "clk_rkvenc_core", "clk_rkvenc_core_c", 24, 8), + /* 9:15 Reserved */ + + /* CRU_CLKGATE_CON25 */ + GATE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", "aclk_rkvdec_pre_c", 25, 0), + GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "hclk_rkvdec_pre_div", 25, 1), + /* 2 aclk_rkvdec_biu */ + /* 3 hclk_rkvdec_biu */ + GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 25, 4), + GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 25, 5), + GATE(CLK_RKVDEC_CA, "clk_rkvdec_ca", "clk_rkvdec_ca_c", 25, 6), + GATE(CLK_RKVDEC_CORE, "clk_rkvdec_core", "clk_rkvdec_core_c", 25, 7), + GATE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", "clk_rkvdec_hevc_ca_c", 25, 8), + /* 9:15 Reserved */ + + /* CRU_CLKGATE_CON26 */ + GATE(ACLK_BUS, "aclk_bus", "aclk_bus_sel", 26, 0), + GATE(PCLK_BUS, "pclk_bus", "pclk_bus_sel", 26, 1), + /* 2 aclk_bus_biu */ + /* 3 pclk_bus_biu */ + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 26, 4), + GATE(CLK_TSADC_TSEN, "clk_tsadc_tsen", "clk_tsadc_tsen_c", 26, 5), + GATE(CLK_TSADC, "clk_tsadc", "clk_tsadc_div", 26, 6), + GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 26, 7), + GATE(CLK_SARADC, "clk_saradc", "xin24m", 26, 8), + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "hclk_secure_flash", 26, 9), + GATE(CLK_OTPC_NS_SBPI, "clk_otpc_ns_sbpi", "xin24m", 26, 10), + GATE(CLK_OTPC_NS_USR, "clk_otpc_ns_usr", "xin_osc0_half", 26, 11), + GATE(PCLK_SCR, "pclk_scr", "pclk_bus", 26, 12), + GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus", 26, 13), + GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 26, 14), + /* 15 Reserved */ + + /* CRU_CLKGATE_CON27 */ + /* 0 pclk_grf */ + /* 1 pclk_grf_vccio12 */ + /* 2 pclk_grf_vccio34 */ + /* 3 pclk_grf_vccio567 */ + GATE(PCLK_CAN0, "pclk_can0", "pclk_bus", 27, 5), + GATE(CLK_CAN0, "clk_can0", "clk_can0_c", 27, 6), + GATE(PCLK_CAN1, "pclk_can1", "pclk_bus", 27, 7), + GATE(CLK_CAN1, "clk_can1", "clk_can1_c", 27, 8), + GATE(PCLK_CAN2, "pclk_can2", "pclk_bus", 27, 9), + GATE(CLK_CAN2, "clk_can2", "clk_can2_c", 27, 10), + /* 11 Reserved */ + GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 27, 12), + GATE(CLK_UART1_SRC, "clk_uart1_src", "clk_uart1_src_c", 27, 13), + GATE(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_frac_frac", 27, 14), + GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_sel", 27, 15), + + /* CRU_CLKGATE_CON28 */ + GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 28, 0), + GATE(CLK_UART2_SRC, "clk_uart2_src", "clk_uart2_src_c", 28, 1), + GATE(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_frac_frac", 28, 2), + GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_sel", 28, 3), + GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 28, 4), + GATE(CLK_UART3_SRC, "clk_uart3_src", "clk_uart3_src_c", 28, 5), + GATE(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_frac_frac", 28, 6), + GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_sel", 28, 7), + GATE(PCLK_UART4, "pclk_uart4", "pclk_bus", 28, 8), + GATE(CLK_UART4_SRC, "clk_uart4_src", "clk_uart4_src_c", 28, 9), + GATE(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_frac_frac", 28, 10), + GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_sel", 28, 11), + GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 28, 12), + GATE(CLK_UART5_SRC, "clk_uart5_src", "clk_uart5_src_c", 28, 13), + GATE(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_frac_frac", 28, 14), + GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_sel", 28, 15), + + /* CRU_CLKGATE_CON29 */ + GATE(PCLK_UART6, "pclk_uart6", "pclk_bus", 29, 0), + GATE(CLK_UART6_SRC, "clk_uart6_src", "clk_uart6_src_c", 29, 1), + GATE(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_frac_frac", 29, 2), + GATE(SCLK_UART6, "sclk_uart6", "sclk_uart6_sel", 29, 3), + GATE(PCLK_UART7, "pclk_uart7", "pclk_bus", 29, 4), + GATE(CLK_UART7_SRC, "clk_uart7_src", "clk_uart7_src_c", 29, 5), + GATE(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_frac_frac", 29, 6), + GATE(SCLK_UART7, "sclk_uart7", "sclk_uart7_sel", 29, 7), + GATE(PCLK_UART8, "pclk_uart8", "pclk_bus", 29, 8), + GATE(CLK_UART8_SRC, "clk_uart8_src", "clk_uart8_src_c", 29, 9), + GATE(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_frac_frac", 29, 10), + GATE(SCLK_UART8, "sclk_uart8", "sclk_uart8_sel", 29, 11), + GATE(PCLK_UART9, "pclk_uart9", "pclk_bus", 29, 12), + GATE(CLK_UART9_SRC, "clk_uart9_src", "clk_uart9_src_c", 29, 13), + GATE(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_frac_frac", 29, 14), + GATE(SCLK_UART9, "sclk_uart9", "sclk_uart9_sel", 29, 15), + + /* CRU_CLKGATE_CON30 */ + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 30, 0), + GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 30, 1), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 30, 2), + GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 30, 3), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 30, 4), + GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 30, 5), + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 30, 6), + GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 30, 7), + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 30, 8), + GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 30, 9), + GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus", 30, 10), + GATE(CLK_SPI0, "clk_spi0", "clk_spi0_sel", 30, 11), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 30, 12), + GATE(CLK_SPI1, "clk_spi1", "clk_spi1_sel", 30, 13), + GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus", 30, 14), + GATE(CLK_SPI2, "clk_spi2", "clk_spi2_sel", 30, 15), + + /* CRU_CLKGATE_CON31 */ + GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus", 31, 0), + GATE(CLK_SPI3, "clk_spi3", "clk_spi3_sel", 31, 1), + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 31, 2), + GATE(DBCLK_GPIO1, "dbclk_gpio1", "dbclk_gpio", 31, 3), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 31, 4), + GATE(DBCLK_GPIO2, "dbclk_gpio2", "dbclk_gpio", 31, 5), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 31, 6), + GATE(DBCLK_GPIO3, "dbclk_gpio3", "dbclk_gpio", 31, 7), + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus", 31, 8), + GATE(DBCLK_GPIO4, "dbclk_gpio4", "dbclk_gpio", 31, 9), + GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 31, 10), + GATE(CLK_PWM1, "clk_pwm1", "clk_pwm1_sel", 31, 11), + GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 31, 12), + GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 31, 13), + GATE(CLK_PWM2, "clk_pwm2", "clk_pwm2_sel", 31, 14), + GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 31, 15), + + /* CRU_CLKGATE_CON32 */ + GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 32, 0), + GATE(CLK_PWM3, "clk_pwm3", "clk_pwm3_sel", 32, 1), + GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 32, 2), + GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 32, 3), + GATE(CLK_TIMER0, "clk_timer0", "xin24m", 32, 4), + GATE(CLK_TIMER1, "clk_timer1", "xin24m", 32, 5), + GATE(CLK_TIMER2, "clk_timer2", "xin24m", 32, 6), + GATE(CLK_TIMER3, "clk_timer3", "xin24m", 32, 7), + GATE(CLK_TIMER4, "clk_timer4", "xin24m", 32, 8), + GATE(CLK_TIMER5, "clk_timer5", "xin24m", 32, 9), + GATE(CLK_I2C, "clk_i2c", "clk_i2c_sel", 32, 10), + GATE(DBCLK_GPIO, "dbclk_gpio", "dbclk_gpio_sel", 32, 11), + /* 12 clk_timer */ + GATE(ACLK_MCU, "aclk_mcu", "aclk_bus", 32, 13), + GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus", 32, 14), + GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 32, 15), + + /* CRU_CLKGATE_CON33 */ + GATE(ACLK_TOP_HIGH, "aclk_top_high", "aclk_top_high_sel", 33, 0), + GATE(ACLK_TOP_LOW, "aclk_top_low", "aclk_top_low_sel", 33, 1), + GATE(HCLK_TOP, "hclk_top", "hclk_top_sel", 33, 2), + GATE(PCLK_TOP, "pclk_top", "pclk_top_sel", 33, 3), + /* 4 aclk_top_high_biu */ + /* 5 aclk_top_low_biu */ + /* 6 hclk_top_biu */ + /* 7 pclk_top_biu */ + GATE(PCLK_PCIE30PHY, "pclk_pcie30phy", "pclk_top", 33, 8), + GATE(CLK_OPTC_ARB, "clk_optc_arb", "clk_optc_arb_sel", 33, 9), + /* 10:11 Reserved */ + /* 12 pclk_top_cru */ + GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top", 33, 13), + GATE(PCLK_MIPIDSIPHY0, "pclk_mipidsiphy0", "pclk_top", 33, 14), + GATE(PCLK_MIPIDSIPHY1, "pclk_mipidsiphy1", "pclk_top", 33, 15), + + /* CRU_CLKGATE_CON34 */ + /* 0 pclk_apb2asb_chip_left */ + /* 1 pclk_apb2asb_chip_bottom */ + /* 2 pclk_asb2apb_chip_left */ + /* 3 pclk_asb2apb_chip_bottom */ + GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 34, 4), + GATE(PCLK_PIPEPHY1, "pclk_pipephy1", "pclk_top", 34, 5), + GATE(PCLK_PIPEPHY2, "pclk_pipephy2", "pclk_top", 34, 6), + /* 7 pclk_usb2phy0_grf */ + /* 8 pclk_usb2phy1_grf */ + /* 9 pclk_ddrphy */ + /* 10 clk_ddrphy */ + GATE(PCLK_CPU_BOOST, "pclk_cpu_boost", "pclk_top", 34, 11), + GATE(CLK_CPU_BOOST, "clk_cpu_boost", "xin24m", 34, 12), + GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_top", 34, 13), + GATE(PCLK_EDPPHY_GRF, "pclk_edpphy_grf", "pclk_top", 34, 14), + /* 15 clk_testout */ + + /* CRU_CLKGATE_CON35 */ + GATE(0, "clk_gpll_div_400m", "clk_gpll_div_400m_div", 35, 0), + GATE(0, "clk_gpll_div_300m", "clk_gpll_div_300m_div", 35, 1), + GATE(0, "clk_gpll_div_200m", "clk_gpll_div_200m_div", 35, 2), + GATE(0, "clk_gpll_div_150m", "clk_gpll_div_150m_div", 35, 3), + GATE(0, "clk_gpll_div_100m", "clk_gpll_div_100m_div", 35, 4), + GATE(0, "clk_gpll_div_75m", "clk_gpll_div_75m_div", 35, 5), + GATE(0, "clk_gpll_div_20m", "clk_gpll_div_20m_div", 35, 6), + GATE(CPLL_500M, "clk_cpll_div_500m", "clk_cpll_div_500m_div", 35, 7), + GATE(CPLL_333M, "clk_cpll_div_333m", "clk_cpll_div_333m_div", 35, 8), + GATE(CPLL_250M, "clk_cpll_div_250m", "clk_cpll_div_250m_div", 35, 9), + GATE(CPLL_125M, "clk_cpll_div_125m", "clk_cpll_div_125m_div", 35, 10), + GATE(CPLL_100M, "clk_cpll_div_100m", "clk_cpll_div_100m_div", 35, 11), + GATE(CPLL_62P5M, "clk_cpll_div_62P5m", "clk_cpll_div_62P5m_div", 35, 12), + GATE(CPLL_50M, "clk_cpll_div_50m", "clk_cpll_div_50m_div", 35, 13), + GATE(CPLL_25M, "clk_cpll_div_25m", "clk_cpll_div_25m_div", 35, 14), + GATE(0, "clk_osc0_div_750k", "clk_osc0_div_750k_div", 35, 15), +}; + + +static int +rk3568_cru_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_is_compatible(dev, "rockchip,rk3568-cru")) { + device_set_desc(dev, "Rockchip RK3568 Clock & Reset Unit"); + return (BUS_PROBE_DEFAULT); + } + return (ENXIO); +} + +static int +rk3568_cru_attach(device_t dev) +{ + struct rk_cru_softc *sc; + + sc = device_get_softc(dev); + sc->dev = dev; + sc->clks = rk3568_clks; + sc->nclks = nitems(rk3568_clks); + sc->gates = rk3568_gates; + sc->ngates = nitems(rk3568_gates); + sc->reset_offset = 0x400; + sc->reset_num = 478; + + return (rk_cru_attach(dev)); +} + +static device_method_t methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, rk3568_cru_probe), + DEVMETHOD(device_attach, rk3568_cru_attach), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(rk3568_cru, rk3568_cru_driver, methods, + sizeof(struct rk_cru_softc), rk_cru_driver); + +EARLY_DRIVER_MODULE(rk3568_cru, simplebus, rk3568_cru_driver, + 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); diff --git a/sys/dev/clk/rockchip/rk3568_pmucru.c b/sys/dev/clk/rockchip/rk3568_pmucru.c new file mode 100644 index 000000000000..0756dc5392bf --- /dev/null +++ b/sys/dev/clk/rockchip/rk3568_pmucru.c @@ -0,0 +1,248 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2021, 2022 Soren Schmidt <sos@deepcore.dk> + * Copyright (c) 2023, Emmanuel Vadot <manu@freebsd.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <machine/bus.h> + +#include <dev/fdt/simplebus.h> + +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> + +#include <dev/extres/clk/clk_div.h> +#include <dev/extres/clk/clk_fixed.h> +#include <dev/extres/clk/clk_mux.h> + +#include <dev/clk/rockchip/rk_cru.h> +#include <contrib/device-tree/include/dt-bindings/clock/rk3568-cru.h> + + +#define CRU_PLLSEL_CON(x) ((x) * 0x20) +#define CRU_CLKSEL_CON(x) ((x) * 0x4 + 0x100) +#define CRU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) + +/* PLL clock */ +#define RK_PLL(_id, _name, _pnames, _off, _shift) \ +{ \ + .type = RK3328_CLK_PLL, \ + .clk.pll = &(struct rk_clk_pll_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = _pnames, \ + .clkdef.parent_cnt = nitems(_pnames), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .base_offset = CRU_PLLSEL_CON(_off), \ + .mode_reg = 0x80, \ + .mode_shift = _shift, \ + .rates = rk3568_pll_rates, \ + }, \ +} + +extern struct rk_clk_pll_rate rk3568_pll_rates[]; + +/* Parent clock defines */ +PLIST(mux_pll_p) = { "xin24m" }; +PLIST(xin24m_32k_p) = { "xin24m", "clk_rtc_32k" }; +PLIST(sclk_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" }; +PLIST(sclk_uart0_div_p) = { "ppll", "usb480m", "cpll", "gpll" }; +PLIST(clk_rtc32k_pmu_p) = { "clk_32k_pvtm", "xin32k", "clk_osc0_div32k" }; +PLIST(clk_usbphy0_ref_p) = { "clk_ref24m", "xin_osc0_usbphy0_g" }; +PLIST(clk_usbphy1_ref_p) = { "clk_ref24m", "xin_osc0_usbphy1_g" }; +PLIST(clk_mipidsiphy0_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy0_g" }; +PLIST(clk_mipidsiphy1_ref_p) = { "clk_ref24m", "xin_osc0_mipidsiphy1_g" }; +PLIST(clk_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" }; +PLIST(clk_pciephy0_ref_p) = { "clk_pciephy0_osc0", "clk_pciephy0_div" }; +PLIST(clk_pciephy1_ref_p) = { "clk_pciephy1_osc0", "clk_pciephy1_div" }; +PLIST(clk_pciephy2_ref_p) = { "clk_pciephy2_osc0", "clk_pciephy2_div" }; +PLIST(clk_hdmi_ref_p) = { "hpll", "hpll_ph0" }; +PLIST(clk_pdpmu_p) = { "ppll", "gpll" }; +PLIST(clk_pwm0_p) = { "xin24m", "clk_pdpmu" }; + +/* CLOCKS */ +static struct rk_clk rk3568_clks[] = { + /* External clocks */ + LINK("xin24m"), + LINK("cpll"), + LINK("gpll"), + LINK("usb480m"), + LINK("clk_32k_pvtm"), + + /* Fixed clocks */ + FFACT(0, "ppll_ph0", "ppll", 1, 2), + FFACT(0, "ppll_ph180", "ppll", 1, 2), + FFACT(0, "hpll_ph0", "hpll", 1, 2), + + /* PLL's */ + RK_PLL(PLL_PPLL, "ppll", mux_pll_p, 0, 0), + RK_PLL(PLL_HPLL, "hpll", mux_pll_p, 2, 2), + + /* PMUCRU_PMUCLKSEL_CON00 */ + CDIV(0, "xin_osc0_div_div", "xin24m", 0, 0, 0, 5), + MUX(0, "clk_rtc_32k_mux", clk_rtc32k_pmu_p, 0, 0, 6, 2), + + /* PMUCRU_PMUCLKSEL_CON01 */ + FRACT(0, "clk_osc0_div32k", "xin24m", 0, 1), + + /* PMUCRU_PMUCLKSEL_CON02 */ + CDIV(0, "pclk_pdpmu_pre", "clk_pdpmu", 0, 2, 0, 5), + MUX(CLK_PDPMU, "clk_pdpmu", clk_pdpmu_p, 0, 2, 15, 1), + + /* PMUCRU_PMUCLKSEL_CON03 */ + CDIV(0, "clk_i2c0_div", "clk_pdpmu", 0, 3, 0, 7), + + /* PMUCRU_PMUCLKSEL_CON04 */ + CDIV(0, "sclk_uart0_div_div", "sclk_uart0_div_sel", 0, 4, 0, 7), + MUX(0, "sclk_uart0_div_sel", sclk_uart0_div_p, 0, 4, 8, 2), + MUX(0, "sclk_uart0_mux", sclk_uart0_p, 0, 4, 10, 2), + + /* PMUCRU_PMUCLKSEL_CON05 */ + FRACT(0, "sclk_uart0_frac_div", "sclk_uart0_div", 0, 5), + + /* PMUCRU_PMUCLKSEL_CON06 */ + CDIV(0, "clk_pwm0_div", "clk_pwm0_sel", 0, 6, 0, 7), + MUX(0, "clk_pwm0_sel", clk_pwm0_p, 0, 6, 7, 1), + MUX(0, "dbclk_gpio0_sel", xin24m_32k_p, 0, 6, 15, 1), + + /* PMUCRU_PMUCLKSEL_CON07 */ + CDIV(0, "clk_ref24m_div", "clk_pdpmu", 0, 7, 0, 6), + + /* PMUCRU_PMUCLKSEL_CON08 */ + MUX(CLK_USBPHY0_REF, "clk_usbphy0_ref", clk_usbphy0_ref_p, 0, 8, 0, 1), + MUX(CLK_USBPHY1_REF, "clk_usbphy1_ref", clk_usbphy1_ref_p, 0, 8, 1, 1), + MUX(CLK_MIPIDSIPHY0_REF, "clk_mipidsiphy0_ref", clk_mipidsiphy0_ref_p, 0, 8, 2, 1), + MUX(CLK_MIPIDSIPHY1_REF, "clk_mipidsiphy1_ref", clk_mipidsiphy1_ref_p, 0, 8, 3, 1), + MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0, 8, 7, 1), + CDIV(0, "clk_wifi_div_div", "clk_pdpmu", 0, 8, 8, 6), + MUX(CLK_WIFI, "clk_wifi", clk_wifi_p, 0, 8, 15, 1), + + /* PMUCRU_PMUCLKSEL_CON09 */ + CDIV(0, "clk_pciephy0_div_div", "ppll_ph0", 0, 9, 0, 3), + MUX(CLK_PCIEPHY0_REF, "clk_pciephy0_ref", + clk_pciephy0_ref_p, 0, 9, 3, 1), + CDIV(0, "clk_pciephy1_div_div", "ppll_ph0", 0, 9, 4, 3), + MUX(CLK_PCIEPHY1_REF, "clk_pciephy1_ref", + clk_pciephy1_ref_p, 0, 9, 7, 1), + CDIV(0, "clk_pciephy2_div_div", "ppll_ph0", 0, 9, 8, 3), + MUX(CLK_PCIEPHY2_REF, "clk_pciephy2_ref", + clk_pciephy2_ref_p, 0, 9, 11, 1), +}; + +/* GATES */ +static struct rk_cru_gate rk3568_gates[] = { + /* PMUCRU_PMUGATE_CON00 */ + GATE(XIN_OSC0_DIV, "xin_osc0_div", "xin_osc0_div_div", 0, 0), + GATE(CLK_RTC_32K, "clk_rtc_32k", "clk_rtc_32k_mux", 0, 1), + GATE(PCLK_PDPMU, "pclk_pdpmu", "pclk_pdpmu_pre", 0, 2), + GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", 0, 6), + GATE(CLK_PMU, "clk_pmu", "xin24m", 0, 7), + + /* PMUCRU_PMUGATE_CON01 */ + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 1, 0), + GATE(CLK_I2C0, "clk_i2c0", "clk_i2c0_div", 1, 1), + GATE(PCLK_UART0, "pclk_uart0", "pclk_pdpmu", 1, 2), + GATE(CLK_UART0_DIV, "sclk_uart0_div", "sclk_uart0_div_div", 1, 3), + GATE(CLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_frac_div", 1, 4), + GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 1, 5), + GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 1, 6), + GATE(CLK_PWM0, "clk_pwm0", "clk_pwm0_div", 1, 7), + GATE(CLK_CAPTURE_PWM0_NDFT, "clk_capture_pwm0_ndft", "xin24m", 1, 8), + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 1, 9), + GATE(DBCLK_GPIO0, "dbclk_gpio0", "dbclk_gpio0_sel", 1, 10), + GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 1, 11), + GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 1, 12), + GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 1, 13), + + /* PMUCRU_PMUGATE_CON02 */ + GATE(CLK_REF24M, "clk_ref24m", "clk_ref24m_div", 2, 0), + GATE(XIN_OSC0_USBPHY0_G, "xin_osc0_usbphy0_g", "xin24m", 2, 1), + GATE(XIN_OSC0_USBPHY1_G, "xin_osc0_usbphy1_g", "xin24m", 2, 2), + GATE(XIN_OSC0_MIPIDSIPHY0_G, "xin_osc0_mipidsiphy0_g", "xin24m", 2, 3), + GATE(XIN_OSC0_MIPIDSIPHY1_G, "xin_osc0_mipidsiphy1_g", "xin24m", 2, 4), + GATE(CLK_WIFI_DIV, "clk_wifi_div", "clk_wifi_div_div", 2, 5), + GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 2, 6), + GATE(CLK_PCIEPHY0_DIV, "clk_pciephy0_div", "clk_pciephy0_div_div", 2, 7), + GATE(CLK_PCIEPHY0_OSC0, "clk_pciephy0_osc0", "xin24m", 2, 8), + GATE(CLK_PCIEPHY1_DIV, "clk_pciephy1_div", "clk_pciephy1_div_div", 2, 9), + GATE(CLK_PCIEPHY1_OSC0, "clk_pciephy1_osc0", "xin24m", 2, 10), + GATE(CLK_PCIEPHY2_DIV, "clk_pciephy2_div", "clk_pciephy2_div_div", 2, 11), + GATE(CLK_PCIEPHY2_OSC0, "clk_pciephy2_osc0", "xin24m", 2, 12), + GATE(CLK_PCIE30PHY_REF_M, "clk_pcie30phy_ref_m", "ppll_ph0", 2, 13), + GATE(CLK_PCIE30PHY_REF_N, "clk_pcie30phy_ref_n", "ppll_ph180", 2, 14), + GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 2, 15), +}; + +static int +rk3568_pmucru_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_is_compatible(dev, "rockchip,rk3568-pmucru")) { + device_set_desc(dev, "Rockchip RK3568 PMU Clock & Reset Unit"); + return (BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static int +rk3568_pmucru_attach(device_t dev) +{ + struct rk_cru_softc *sc; + + sc = device_get_softc(dev); + sc->dev = dev; + sc->clks = rk3568_clks; + sc->nclks = nitems(rk3568_clks); + sc->gates = rk3568_gates; + sc->ngates = nitems(rk3568_gates); + sc->reset_offset = 0x200; + sc->reset_num = 4; + + return (rk_cru_attach(dev)); +} + +static device_method_t methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, rk3568_pmucru_probe), + DEVMETHOD(device_attach, rk3568_pmucru_attach), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(rk3568_pmucru, rk3568_pmucru_driver, methods, + sizeof(struct rk_cru_softc), rk_cru_driver); + +EARLY_DRIVER_MODULE(rk3568_pmucru, simplebus, rk3568_pmucru_driver, + 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); diff --git a/sys/dev/clk/rockchip/rk_clk_armclk.c b/sys/dev/clk/rockchip/rk_clk_armclk.c new file mode 100644 index 000000000000..3d462e74d92b --- /dev/null +++ b/sys/dev/clk/rockchip/rk_clk_armclk.c @@ -0,0 +1,252 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> + +#include <dev/extres/clk/clk.h> + +#include <dev/clk/rockchip/rk_clk_armclk.h> + +#include "clkdev_if.h" + +struct rk_clk_armclk_sc { + uint32_t muxdiv_offset; + uint32_t mux_shift; + uint32_t mux_width; + uint32_t mux_mask; + + uint32_t div_shift; + uint32_t div_width; + uint32_t div_mask; + + uint32_t gate_offset; + uint32_t gate_shift; + + uint32_t flags; + + uint32_t main_parent; + uint32_t alt_parent; + + struct rk_clk_armclk_rates *rates; + int nrates; +}; + +#define WRITE4(_clk, off, val) \ + CLKDEV_WRITE_4(clknode_get_device(_clk), off, val) +#define READ4(_clk, off, val) \ + CLKDEV_READ_4(clknode_get_device(_clk), off, val) +#define DEVICE_LOCK(_clk) \ + CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) +#define DEVICE_UNLOCK(_clk) \ + CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) + +#define RK_ARMCLK_WRITE_MASK_SHIFT 16 + +#if 0 +#define dprintf(format, arg...) \ + printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) +#else +#define dprintf(format, arg...) +#endif + +static int +rk_clk_armclk_init(struct clknode *clk, device_t dev) +{ + struct rk_clk_armclk_sc *sc; + uint32_t val, idx; + + sc = clknode_get_softc(clk); + + idx = 0; + DEVICE_LOCK(clk); + READ4(clk, sc->muxdiv_offset, &val); + DEVICE_UNLOCK(clk); + + idx = (val & sc->mux_mask) >> sc->mux_shift; + + clknode_init_parent_idx(clk, idx); + + return (0); +} + +static int +rk_clk_armclk_set_mux(struct clknode *clk, int index) +{ + struct rk_clk_armclk_sc *sc; + uint32_t val = 0; + + sc = clknode_get_softc(clk); + + dprintf("Set mux to %d\n", index); + DEVICE_LOCK(clk); + val |= index << sc->mux_shift; + val |= sc->mux_mask << RK_ARMCLK_WRITE_MASK_SHIFT; + dprintf("Write: muxdiv_offset=%x, val=%x\n", sc->muxdiv_offset, val); + WRITE4(clk, sc->muxdiv_offset, val); + DEVICE_UNLOCK(clk); + + return (0); +} + +static int +rk_clk_armclk_recalc(struct clknode *clk, uint64_t *freq) +{ + struct rk_clk_armclk_sc *sc; + uint32_t reg, div; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(clk); + + READ4(clk, sc->muxdiv_offset, ®); + dprintf("Read: muxdiv_offset=%x, val=%x\n", sc->muxdiv_offset, reg); + + DEVICE_UNLOCK(clk); + + div = ((reg & sc->div_mask) >> sc->div_shift) + 1; + dprintf("parent_freq=%ju, div=%u\n", *freq, div); + + *freq = *freq / div; + + return (0); +} + +static int +rk_clk_armclk_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, + int flags, int *stop) +{ + struct rk_clk_armclk_sc *sc; + struct clknode *p_main; + const char **p_names; + uint64_t best = 0, best_p = 0; + uint32_t div = 0, val = 0; + int err, i, rate = 0; + + sc = clknode_get_softc(clk); + + dprintf("Finding best parent/div for target freq of %ju\n", *fout); + p_names = clknode_get_parent_names(clk); + p_main = clknode_find_by_name(p_names[sc->main_parent]); + + for (i = 0; i < sc->nrates; i++) { + if (sc->rates[i].freq == *fout) { + best = sc->rates[i].freq; + div = sc->rates[i].div; + best_p = best * div; + rate = i; + dprintf("Best parent %s (%d) with best freq at %ju\n", + clknode_get_name(p_main), + sc->main_parent, + best); + break; + } + } + + if (rate == sc->nrates) + return (0); + + if ((flags & CLK_SET_DRYRUN) != 0) { + *fout = best; + *stop = 1; + return (0); + } + + dprintf("Changing parent (%s) freq to %ju\n", clknode_get_name(p_main), + best_p); + err = clknode_set_freq(p_main, best_p, 0, 1); + if (err != 0) + printf("Cannot set %s to %ju\n", + clknode_get_name(p_main), + best_p); + + clknode_set_parent_by_idx(clk, sc->main_parent); + + clknode_get_freq(p_main, &best_p); + dprintf("main parent freq at %ju\n", best_p); + DEVICE_LOCK(clk); + val |= (div - 1) << sc->div_shift; + val |= sc->div_mask << RK_ARMCLK_WRITE_MASK_SHIFT; + dprintf("Write: muxdiv_offset=%x, val=%x\n", sc->muxdiv_offset, val); + WRITE4(clk, sc->muxdiv_offset, val); + DEVICE_UNLOCK(clk); + + *fout = best; + *stop = 1; + + return (0); +} + +static clknode_method_t rk_clk_armclk_clknode_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, rk_clk_armclk_init), + CLKNODEMETHOD(clknode_set_mux, rk_clk_armclk_set_mux), + CLKNODEMETHOD(clknode_recalc_freq, rk_clk_armclk_recalc), + CLKNODEMETHOD(clknode_set_freq, rk_clk_armclk_set_freq), + CLKNODEMETHOD_END +}; + +DEFINE_CLASS_1(rk_clk_armclk_clknode, rk_clk_armclk_clknode_class, + rk_clk_armclk_clknode_methods, sizeof(struct rk_clk_armclk_sc), + clknode_class); + +int +rk_clk_armclk_register(struct clkdom *clkdom, struct rk_clk_armclk_def *clkdef) +{ + struct clknode *clk; + struct rk_clk_armclk_sc *sc; + + clk = clknode_create(clkdom, &rk_clk_armclk_clknode_class, + &clkdef->clkdef); + if (clk == NULL) + return (1); + + sc = clknode_get_softc(clk); + + sc->muxdiv_offset = clkdef->muxdiv_offset; + + sc->mux_shift = clkdef->mux_shift; + sc->mux_width = clkdef->mux_width; + sc->mux_mask = ((1 << clkdef->mux_width) - 1) << sc->mux_shift; + + sc->div_shift = clkdef->div_shift; + sc->div_width = clkdef->div_width; + sc->div_mask = ((1 << clkdef->div_width) - 1) << sc->div_shift; + + sc->flags = clkdef->flags; + + sc->main_parent = clkdef->main_parent; + sc->alt_parent = clkdef->alt_parent; + + sc->rates = clkdef->rates; + sc->nrates = clkdef->nrates; + + clknode_register(clkdom, clk); + + return (0); +} diff --git a/sys/dev/clk/rockchip/rk_clk_armclk.h b/sys/dev/clk/rockchip/rk_clk_armclk.h new file mode 100644 index 000000000000..0c7f91d21d60 --- /dev/null +++ b/sys/dev/clk/rockchip/rk_clk_armclk.h @@ -0,0 +1,61 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright 2018 Emmanuel Vadot <manu@FreeBSD.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RK_CLK_ARMCLK_H_ +#define _RK_CLK_ARMCLK_H_ + +#include <dev/extres/clk/clk.h> + +struct rk_clk_armclk_rates { + uint64_t freq; + uint32_t div; +}; + +struct rk_clk_armclk_def { + struct clknode_init_def clkdef; + + uint32_t muxdiv_offset; + + uint32_t mux_shift; + uint32_t mux_width; + + uint32_t div_shift; + uint32_t div_width; + + uint32_t flags; + + uint32_t main_parent; + uint32_t alt_parent; + + struct rk_clk_armclk_rates *rates; + int nrates; +}; + +int rk_clk_armclk_register(struct clkdom *clkdom, + struct rk_clk_armclk_def *clkdef); + +#endif /* _RK_CLK_ARMCLK_H_ */ diff --git a/sys/dev/clk/rockchip/rk_clk_composite.c b/sys/dev/clk/rockchip/rk_clk_composite.c new file mode 100644 index 000000000000..a37ddcd6ecb2 --- /dev/null +++ b/sys/dev/clk/rockchip/rk_clk_composite.c @@ -0,0 +1,334 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> + +#include <dev/extres/clk/clk.h> +#include <dev/extres/syscon/syscon.h> + +#include <dev/clk/rockchip/rk_clk_composite.h> + +#include "clkdev_if.h" +#include "syscon_if.h" + +struct rk_clk_composite_sc { + uint32_t muxdiv_offset; + uint32_t mux_shift; + uint32_t mux_width; + uint32_t mux_mask; + + uint32_t div_shift; + uint32_t div_width; + uint32_t div_mask; + + uint32_t flags; + + struct syscon *grf; +}; + +#define WRITE4(_clk, off, val) \ + rk_clk_composite_write_4(_clk, off, val) +#define READ4(_clk, off, val) \ + rk_clk_composite_read_4(_clk, off, val) +#define DEVICE_LOCK(_clk) \ + CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) +#define DEVICE_UNLOCK(_clk) \ + CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) + +#define RK_CLK_COMPOSITE_MASK_SHIFT 16 + +#if 0 +#define dprintf(format, arg...) \ + printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) +#else +#define dprintf(format, arg...) +#endif + +static void +rk_clk_composite_read_4(struct clknode *clk, bus_addr_t addr, uint32_t *val) +{ + struct rk_clk_composite_sc *sc; + + sc = clknode_get_softc(clk); + if (sc->grf) + *val = SYSCON_READ_4(sc->grf, addr); + else + CLKDEV_READ_4(clknode_get_device(clk), addr, val); +} + +static void +rk_clk_composite_write_4(struct clknode *clk, bus_addr_t addr, uint32_t val) +{ + struct rk_clk_composite_sc *sc; + + sc = clknode_get_softc(clk); + if (sc->grf) + SYSCON_WRITE_4(sc->grf, addr, val | (0xffff << 16)); + else + CLKDEV_WRITE_4(clknode_get_device(clk), addr, val); +} + +static struct syscon * +rk_clk_composite_get_grf(struct clknode *clk) +{ + device_t dev; + phandle_t node; + struct syscon *grf; + + grf = NULL; + dev = clknode_get_device(clk); + node = ofw_bus_get_node(dev); + if (OF_hasprop(node, "rockchip,grf") && + syscon_get_by_ofw_property(dev, node, + "rockchip,grf", &grf) != 0) { + return (NULL); + } + + return (grf); +} + +static int +rk_clk_composite_init(struct clknode *clk, device_t dev) +{ + struct rk_clk_composite_sc *sc; + uint32_t val, idx; + + sc = clknode_get_softc(clk); + if ((sc->flags & RK_CLK_COMPOSITE_GRF) != 0) { + sc->grf = rk_clk_composite_get_grf(clk); + if (sc->grf == NULL) + panic("clock %s has GRF flag set but no syscon is available", + clknode_get_name(clk)); + } + + idx = 0; + if ((sc->flags & RK_CLK_COMPOSITE_HAVE_MUX) != 0) { + DEVICE_LOCK(clk); + READ4(clk, sc->muxdiv_offset, &val); + DEVICE_UNLOCK(clk); + + idx = (val & sc->mux_mask) >> sc->mux_shift; + } + + clknode_init_parent_idx(clk, idx); + + return (0); +} + +static int +rk_clk_composite_set_mux(struct clknode *clk, int index) +{ + struct rk_clk_composite_sc *sc; + uint32_t val = 0; + + sc = clknode_get_softc(clk); + + if ((sc->flags & RK_CLK_COMPOSITE_HAVE_MUX) == 0) + return (0); + + dprintf("Set mux to %d\n", index); + DEVICE_LOCK(clk); + val |= (index << sc->mux_shift); + val |= sc->mux_mask << RK_CLK_COMPOSITE_MASK_SHIFT; + dprintf("Write: muxdiv_offset=%x, val=%x\n", sc->muxdiv_offset, val); + WRITE4(clk, sc->muxdiv_offset, val); + DEVICE_UNLOCK(clk); + + return (0); +} + +static int +rk_clk_composite_recalc(struct clknode *clk, uint64_t *freq) +{ + struct rk_clk_composite_sc *sc; + uint32_t reg, div; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(clk); + + READ4(clk, sc->muxdiv_offset, ®); + dprintf("Read: muxdiv_offset=%x, val=%x\n", sc->muxdiv_offset, reg); + + DEVICE_UNLOCK(clk); + + div = ((reg & sc->div_mask) >> sc->div_shift); + if (sc->flags & RK_CLK_COMPOSITE_DIV_EXP) + div = 1 << div; + else + div += 1; + dprintf("parent_freq=%ju, div=%u\n", *freq, div); + *freq = *freq / div; + dprintf("Final freq=%ju\n", *freq); + return (0); +} + +static uint32_t +rk_clk_composite_find_best(struct rk_clk_composite_sc *sc, uint64_t fparent, + uint64_t freq, uint32_t *reg) +{ + uint64_t best, cur; + uint32_t best_div, best_div_reg; + uint32_t div, div_reg; + + best = 0; + best_div = 0; + best_div_reg = 0; + + for (div_reg = 0; div_reg <= ((sc->div_mask >> sc->div_shift) + 1); + div_reg++) { + if (sc->flags == RK_CLK_COMPOSITE_DIV_EXP) + div = 1 << div_reg; + else + div = div_reg + 1; + cur = fparent / div; + if ((freq - cur) < (freq - best)) { + best = cur; + best_div = div; + best_div_reg = div_reg; + break; + } + } + *reg = best_div_reg; + return (best_div); +} + +static int +rk_clk_composite_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, + int flags, int *stop) +{ + struct rk_clk_composite_sc *sc; + struct clknode *p_clk; + const char **p_names; + uint64_t best, cur; + uint32_t div, div_reg, best_div, best_div_reg, val; + int p_idx, best_parent; + + sc = clknode_get_softc(clk); + dprintf("Finding best parent/div for target freq of %ju\n", *fout); + p_names = clknode_get_parent_names(clk); + for (best_div = 0, best = 0, p_idx = 0; + p_idx != clknode_get_parents_num(clk); p_idx++) { + p_clk = clknode_find_by_name(p_names[p_idx]); + clknode_get_freq(p_clk, &fparent); + dprintf("Testing with parent %s (%d) at freq %ju\n", + clknode_get_name(p_clk), p_idx, fparent); + div = rk_clk_composite_find_best(sc, fparent, *fout, &div_reg); + cur = fparent / div; + if ((*fout - cur) < (*fout - best)) { + best = cur; + best_div = div; + best_div_reg = div_reg; + best_parent = p_idx; + dprintf("Best parent so far %s (%d) with best freq at " + "%ju\n", clknode_get_name(p_clk), p_idx, best); + } + } + + *stop = 1; + if (best_div == 0) + return (ERANGE); + + if ((best < *fout) && ((flags & CLK_SET_ROUND_DOWN) == 0)) + return (ERANGE); + + if ((best > *fout) && ((flags & CLK_SET_ROUND_UP) == 0)) { + return (ERANGE); + } + + if ((flags & CLK_SET_DRYRUN) != 0) { + *fout = best; + return (0); + } + + p_idx = clknode_get_parent_idx(clk); + if (p_idx != best_parent) { + dprintf("Switching parent index from %d to %d\n", p_idx, + best_parent); + clknode_set_parent_by_idx(clk, best_parent); + } + + dprintf("Setting divider to %d (reg: %d)\n", best_div, best_div_reg); + dprintf(" div_mask: 0x%X, div_shift: %d\n", sc->div_mask, + sc->div_shift); + + DEVICE_LOCK(clk); + val = best_div_reg << sc->div_shift; + val |= sc->div_mask << RK_CLK_COMPOSITE_MASK_SHIFT; + dprintf("Write: muxdiv_offset=%x, val=%x\n", sc->muxdiv_offset, val); + WRITE4(clk, sc->muxdiv_offset, val); + DEVICE_UNLOCK(clk); + + *fout = best; + return (0); +} + +static clknode_method_t rk_clk_composite_clknode_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, rk_clk_composite_init), + CLKNODEMETHOD(clknode_set_mux, rk_clk_composite_set_mux), + CLKNODEMETHOD(clknode_recalc_freq, rk_clk_composite_recalc), + CLKNODEMETHOD(clknode_set_freq, rk_clk_composite_set_freq), + CLKNODEMETHOD_END +}; + +DEFINE_CLASS_1(rk_clk_composite_clknode, rk_clk_composite_clknode_class, + rk_clk_composite_clknode_methods, sizeof(struct rk_clk_composite_sc), + clknode_class); + +int +rk_clk_composite_register(struct clkdom *clkdom, + struct rk_clk_composite_def *clkdef) +{ + struct clknode *clk; + struct rk_clk_composite_sc *sc; + + clk = clknode_create(clkdom, &rk_clk_composite_clknode_class, + &clkdef->clkdef); + if (clk == NULL) + return (1); + + sc = clknode_get_softc(clk); + + sc->muxdiv_offset = clkdef->muxdiv_offset; + + sc->mux_shift = clkdef->mux_shift; + sc->mux_width = clkdef->mux_width; + sc->mux_mask = ((1 << clkdef->mux_width) - 1) << sc->mux_shift; + + sc->div_shift = clkdef->div_shift; + sc->div_width = clkdef->div_width; + sc->div_mask = ((1 << clkdef->div_width) - 1) << sc->div_shift; + + sc->flags = clkdef->flags; + + clknode_register(clkdom, clk); + + return (0); +} diff --git a/sys/dev/clk/rockchip/rk_clk_composite.h b/sys/dev/clk/rockchip/rk_clk_composite.h new file mode 100644 index 000000000000..22a052da22c2 --- /dev/null +++ b/sys/dev/clk/rockchip/rk_clk_composite.h @@ -0,0 +1,54 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright 2018 Emmanuel Vadot <manu@FreeBSD.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RK_CLK_COMPOSITE_H_ +#define _RK_CLK_COMPOSITE_H_ + +#include <dev/extres/clk/clk.h> + +struct rk_clk_composite_def { + struct clknode_init_def clkdef; + + uint32_t muxdiv_offset; + + uint32_t mux_shift; + uint32_t mux_width; + + uint32_t div_shift; + uint32_t div_width; + + uint32_t flags; +}; + +#define RK_CLK_COMPOSITE_HAVE_MUX 0x0001 +#define RK_CLK_COMPOSITE_DIV_EXP 0x0002 /* Register 0, 1, 2, 2, ... */ + /* Divider 1, 2, 4, 8, ... */ +#define RK_CLK_COMPOSITE_GRF 0x0004 /* Use syscon registers instead of CRU's */ +int rk_clk_composite_register(struct clkdom *clkdom, + struct rk_clk_composite_def *clkdef); + +#endif /* _RK_CLK_COMPOSITE_H_ */ diff --git a/sys/dev/clk/rockchip/rk_clk_fract.c b/sys/dev/clk/rockchip/rk_clk_fract.c new file mode 100644 index 000000000000..f559e9c71852 --- /dev/null +++ b/sys/dev/clk/rockchip/rk_clk_fract.c @@ -0,0 +1,277 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright 2019 Michal Meloun <mmel@FreeBSD.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> + +#include <dev/extres/clk/clk.h> + +#include <dev/clk/rockchip/rk_clk_fract.h> + +#include "clkdev_if.h" + +#define WR4(_clk, off, val) \ + CLKDEV_WRITE_4(clknode_get_device(_clk), off, val) +#define RD4(_clk, off, val) \ + CLKDEV_READ_4(clknode_get_device(_clk), off, val) +#define MD4(_clk, off, clr, set ) \ + CLKDEV_MODIFY_4(clknode_get_device(_clk), off, clr, set) +#define DEVICE_LOCK(_clk) \ + CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) +#define DEVICE_UNLOCK(_clk) \ + CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) + +#define RK_CLK_FRACT_MASK_SHIFT 16 + +static int rk_clk_fract_init(struct clknode *clk, device_t dev); +static int rk_clk_fract_recalc(struct clknode *clk, uint64_t *req); +static int rk_clk_fract_set_freq(struct clknode *clknode, uint64_t fin, + uint64_t *fout, int flag, int *stop); +static int rk_clk_fract_set_gate(struct clknode *clk, bool enable); + +struct rk_clk_fract_sc { + uint32_t flags; + uint32_t offset; + uint32_t numerator; + uint32_t denominator; + uint32_t gate_offset; + uint32_t gate_shift; +}; + +static clknode_method_t rk_clk_fract_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, rk_clk_fract_init), + CLKNODEMETHOD(clknode_set_gate, rk_clk_fract_set_gate), + CLKNODEMETHOD(clknode_recalc_freq, rk_clk_fract_recalc), + CLKNODEMETHOD(clknode_set_freq, rk_clk_fract_set_freq), + CLKNODEMETHOD_END +}; +DEFINE_CLASS_1(rk_clk_fract, rk_clk_fract_class, rk_clk_fract_methods, + sizeof(struct rk_clk_fract_sc), clknode_class); + +/* + * Compute best rational approximation of input fraction + * for fixed sized fractional divider registers. + * http://en.wikipedia.org/wiki/Continued_fraction + * + * - n_input, d_input Given input fraction + * - n_max, d_max Maximum vaues of divider registers + * - n_out, d_out Computed approximation + */ + +static void +clk_compute_fract_div( + uint64_t n_input, uint64_t d_input, + uint64_t n_max, uint64_t d_max, + uint64_t *n_out, uint64_t *d_out) +{ + uint64_t n_prev, d_prev; /* previous convergents */ + uint64_t n_cur, d_cur; /* current convergents */ + uint64_t n_rem, d_rem; /* fraction remainder */ + uint64_t tmp, fact; + + /* Initialize fraction reminder */ + n_rem = n_input; + d_rem = d_input; + + /* Init convergents to 0/1 and 1/0 */ + n_prev = 0; + d_prev = 1; + n_cur = 1; + d_cur = 0; + + while (d_rem != 0 && n_cur < n_max && d_cur < d_max) { + /* Factor for this step. */ + fact = n_rem / d_rem; + + /* Adjust fraction reminder */ + tmp = d_rem; + d_rem = n_rem % d_rem; + n_rem = tmp; + + /* Compute new nominator and save last one */ + tmp = n_prev + fact * n_cur; + n_prev = n_cur; + n_cur = tmp; + + /* Compute new denominator and save last one */ + tmp = d_prev + fact * d_cur; + d_prev = d_cur; + d_cur = tmp; + } + + if (n_cur > n_max || d_cur > d_max) { + *n_out = n_prev; + *d_out = d_prev; + } else { + *n_out = n_cur; + *d_out = d_cur; + } +} + +static int +rk_clk_fract_init(struct clknode *clk, device_t dev) +{ + uint32_t reg; + struct rk_clk_fract_sc *sc; + + sc = clknode_get_softc(clk); + DEVICE_LOCK(clk); + RD4(clk, sc->offset, ®); + DEVICE_UNLOCK(clk); + + sc->numerator = (reg >> 16) & 0xFFFF; + sc->denominator = reg & 0xFFFF; + if (sc->denominator == 0) + sc->denominator = 1; + clknode_init_parent_idx(clk, 0); + + return(0); +} + +static int +rk_clk_fract_set_gate(struct clknode *clk, bool enable) +{ + struct rk_clk_fract_sc *sc; + uint32_t val = 0; + + sc = clknode_get_softc(clk); + + if ((sc->flags & RK_CLK_FRACT_HAVE_GATE) == 0) + return (0); + + RD4(clk, sc->gate_offset, &val); + + val = 0; + if (!enable) + val |= 1 << sc->gate_shift; + val |= (1 << sc->gate_shift) << RK_CLK_FRACT_MASK_SHIFT; + DEVICE_LOCK(clk); + WR4(clk, sc->gate_offset, val); + DEVICE_UNLOCK(clk); + + return (0); +} + +static int +rk_clk_fract_recalc(struct clknode *clk, uint64_t *freq) +{ + struct rk_clk_fract_sc *sc; + + sc = clknode_get_softc(clk); + if (sc->denominator == 0) { + printf("%s: %s denominator is zero!\n", clknode_get_name(clk), + __func__); + *freq = 0; + return(EINVAL); + } + + *freq *= sc->numerator; + *freq /= sc->denominator; + + return (0); +} + +static int +rk_clk_fract_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout, + int flags, int *stop) +{ + struct rk_clk_fract_sc *sc; + uint64_t div_n, div_d, _fout; + + sc = clknode_get_softc(clk); + + clk_compute_fract_div(*fout, fin, 0xFFFF, 0xFFFF, &div_n, &div_d); + _fout = fin * div_n; + _fout /= div_d; + + /* Rounding. */ + if ((flags & CLK_SET_ROUND_UP) && (_fout < *fout)) { + if (div_n > div_d && div_d > 1) + div_n++; + else + div_d--; + } else if ((flags & CLK_SET_ROUND_DOWN) && (_fout > *fout)) { + if (div_n > div_d && div_n > 1) + div_n--; + else + div_d++; + } + + /* Check range after rounding */ + if (div_n > 0xFFFF || div_d > 0xFFFF) + return (ERANGE); + + if (div_d == 0) { + printf("%s: %s divider is zero!\n", + clknode_get_name(clk), __func__); + return(EINVAL); + } + /* Recompute final output frequency */ + _fout = fin * div_n; + _fout /= div_d; + + *stop = 1; + + if ((flags & CLK_SET_DRYRUN) == 0) { + if (*stop != 0 && + (flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0 && + *fout != _fout) + return (ERANGE); + + sc->numerator = (uint32_t)div_n; + sc->denominator = (uint32_t)div_d; + + DEVICE_LOCK(clk); + WR4(clk, sc->offset, sc->numerator << 16 | sc->denominator); + DEVICE_UNLOCK(clk); + } + + *fout = _fout; + return (0); +} + +int +rk_clk_fract_register(struct clkdom *clkdom, struct rk_clk_fract_def *clkdef) +{ + struct clknode *clk; + struct rk_clk_fract_sc *sc; + + clk = clknode_create(clkdom, &rk_clk_fract_class, &clkdef->clkdef); + if (clk == NULL) + return (1); + + sc = clknode_get_softc(clk); + sc->flags = clkdef->flags; + sc->offset = clkdef->offset; + sc->gate_offset = clkdef->gate_offset; + sc->gate_shift = clkdef->gate_shift; + + clknode_register(clkdom, clk); + return (0); +} diff --git a/sys/dev/clk/rockchip/rk_clk_fract.h b/sys/dev/clk/rockchip/rk_clk_fract.h new file mode 100644 index 000000000000..6923f162f265 --- /dev/null +++ b/sys/dev/clk/rockchip/rk_clk_fract.h @@ -0,0 +1,46 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright 2019 Michal Meloun <mmel@FreeBSD.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RK_CLK_FRACT_H_ +#define _RK_CLK_FRACT_H_ + +#include <dev/extres/clk/clk.h> + +struct rk_clk_fract_def { + struct clknode_init_def clkdef; + uint32_t offset; + uint32_t gate_offset; + uint32_t gate_shift; + uint32_t flags; +}; + +#define RK_CLK_FRACT_HAVE_GATE 0x0001 + +int rk_clk_fract_register(struct clkdom *clkdom, + struct rk_clk_fract_def *clkdef); + +#endif /* _RK_CLK_FRACT_H_ */ diff --git a/sys/dev/clk/rockchip/rk_clk_gate.c b/sys/dev/clk/rockchip/rk_clk_gate.c new file mode 100644 index 000000000000..053236d043e6 --- /dev/null +++ b/sys/dev/clk/rockchip/rk_clk_gate.c @@ -0,0 +1,132 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright 2016 Michal Meloun <mmel@FreeBSD.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> + +#include <dev/extres/clk/clk.h> + +#include <dev/clk/rockchip/rk_clk_gate.h> + +#include "clkdev_if.h" + +#define WR4(_clk, off, val) \ + CLKDEV_WRITE_4(clknode_get_device(_clk), off, val) +#define RD4(_clk, off, val) \ + CLKDEV_READ_4(clknode_get_device(_clk), off, val) +#define MD4(_clk, off, clr, set ) \ + CLKDEV_MODIFY_4(clknode_get_device(_clk), off, clr, set) +#define DEVICE_LOCK(_clk) \ + CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) +#define DEVICE_UNLOCK(_clk) \ + CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) + +static int rk_clk_gate_init(struct clknode *clk, device_t dev); +static int rk_clk_gate_set_gate(struct clknode *clk, bool enable); +struct rk_clk_gate_sc { + uint32_t offset; + uint32_t shift; + uint32_t mask; + uint32_t on_value; + uint32_t off_value; + int gate_flags; + bool ungated; +}; + +static clknode_method_t rk_clk_gate_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, rk_clk_gate_init), + CLKNODEMETHOD(clknode_set_gate, rk_clk_gate_set_gate), + CLKNODEMETHOD_END +}; +DEFINE_CLASS_1(rk_clk_gate, rk_clk_gate_class, rk_clk_gate_methods, + sizeof(struct rk_clk_gate_sc), clknode_class); + +static int +rk_clk_gate_init(struct clknode *clk, device_t dev) +{ + uint32_t reg; + struct rk_clk_gate_sc *sc; + int rv; + + sc = clknode_get_softc(clk); + DEVICE_LOCK(clk); + rv = RD4(clk, sc->offset, ®); + DEVICE_UNLOCK(clk); + if (rv != 0) + return (rv); + reg = (reg >> sc->shift) & sc->mask; + sc->ungated = reg == sc->on_value ? 1 : 0; + clknode_init_parent_idx(clk, 0); + return(0); +} + +static int +rk_clk_gate_set_gate(struct clknode *clk, bool enable) +{ + uint32_t reg; + struct rk_clk_gate_sc *sc; + int rv; + + sc = clknode_get_softc(clk); + sc->ungated = enable; + DEVICE_LOCK(clk); + rv = MD4(clk, sc->offset, sc->mask << sc->shift, + ((sc->ungated ? sc->on_value : sc->off_value) << sc->shift) | + RK_CLK_GATE_MASK); + if (rv != 0) { + DEVICE_UNLOCK(clk); + return (rv); + } + RD4(clk, sc->offset, ®); + DEVICE_UNLOCK(clk); + return(0); +} + +int +rk_clk_gate_register(struct clkdom *clkdom, struct rk_clk_gate_def *clkdef) +{ + struct clknode *clk; + struct rk_clk_gate_sc *sc; + + clk = clknode_create(clkdom, &rk_clk_gate_class, &clkdef->clkdef); + if (clk == NULL) + return (1); + + sc = clknode_get_softc(clk); + sc->offset = clkdef->offset; + sc->shift = clkdef->shift; + sc->mask = clkdef->mask; + sc->on_value = clkdef->on_value; + sc->off_value = clkdef->off_value; + sc->gate_flags = clkdef->gate_flags; + + clknode_register(clkdom, clk); + return (0); +} diff --git a/sys/dev/clk/rockchip/rk_clk_gate.h b/sys/dev/clk/rockchip/rk_clk_gate.h new file mode 100644 index 000000000000..add5cd22aa89 --- /dev/null +++ b/sys/dev/clk/rockchip/rk_clk_gate.h @@ -0,0 +1,47 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright 2018 Emmanuel Vadot <manu@FreeBSD.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RK_CLK_GATE_H_ +#define _RK_CLK_GATE_H_ + +#include <dev/extres/clk/clk.h> + +struct rk_clk_gate_def { + struct clknode_init_def clkdef; + uint32_t offset; + uint32_t shift; + uint32_t mask; + uint32_t on_value; + uint32_t off_value; + int gate_flags; +}; + +#define RK_CLK_GATE_MASK 0xFFFF0000 + +int rk_clk_gate_register(struct clkdom *clkdom, struct rk_clk_gate_def *clkdef); + +#endif /* _RK_CLK_GATE_H_ */ diff --git a/sys/dev/clk/rockchip/rk_clk_mux.c b/sys/dev/clk/rockchip/rk_clk_mux.c new file mode 100644 index 000000000000..e42d5819378a --- /dev/null +++ b/sys/dev/clk/rockchip/rk_clk_mux.c @@ -0,0 +1,239 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright 2016 Michal Meloun <mmel@FreeBSD.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/conf.h> +#include <sys/bus.h> +#include <sys/kernel.h> +#include <sys/systm.h> + +#include <machine/bus.h> + +#include <dev/extres/clk/clk.h> +#include <dev/extres/syscon/syscon.h> + +#include <dev/clk/rockchip/rk_cru.h> +#include <dev/clk/rockchip/rk_clk_mux.h> + +#include "clkdev_if.h" +#include "syscon_if.h" + +#define WR4(_clk, off, val) \ + CLKDEV_WRITE_4(clknode_get_device(_clk), off, val) +#define RD4(_clk, off, val) \ + CLKDEV_READ_4(clknode_get_device(_clk), off, val) +#define MD4(_clk, off, clr, set ) \ + CLKDEV_MODIFY_4(clknode_get_device(_clk), off, clr, set) +#define DEVICE_LOCK(_clk) \ + CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) +#define DEVICE_UNLOCK(_clk) \ + CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) + +#if 0 +#define dprintf(format, arg...) \ + printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) +#else +#define dprintf(format, arg...) +#endif + +static int rk_clk_mux_init(struct clknode *clk, device_t dev); +static int rk_clk_mux_set_mux(struct clknode *clk, int idx); +static int rk_clk_mux_set_freq(struct clknode *clk, uint64_t fparent, + uint64_t *fout, int flags, int *stop); + +struct rk_clk_mux_sc { + uint32_t offset; + uint32_t shift; + uint32_t mask; + int mux_flags; + struct syscon *grf; +}; + +static clknode_method_t rk_clk_mux_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, rk_clk_mux_init), + CLKNODEMETHOD(clknode_set_mux, rk_clk_mux_set_mux), + CLKNODEMETHOD(clknode_set_freq, rk_clk_mux_set_freq), + CLKNODEMETHOD_END +}; +DEFINE_CLASS_1(rk_clk_mux, rk_clk_mux_class, rk_clk_mux_methods, + sizeof(struct rk_clk_mux_sc), clknode_class); + +static struct syscon * +rk_clk_mux_get_grf(struct clknode *clk) +{ + device_t dev; + phandle_t node; + struct syscon *grf; + + grf = NULL; + dev = clknode_get_device(clk); + node = ofw_bus_get_node(dev); + if (OF_hasprop(node, "rockchip,grf") && + syscon_get_by_ofw_property(dev, node, + "rockchip,grf", &grf) != 0) { + return (NULL); + } + + return (grf); +} + +static int +rk_clk_mux_init(struct clknode *clk, device_t dev) +{ + uint32_t reg; + struct rk_clk_mux_sc *sc; + int rv; + + sc = clknode_get_softc(clk); + + if ((sc->mux_flags & RK_CLK_MUX_GRF) != 0) { + sc->grf = rk_clk_mux_get_grf(clk); + if (sc->grf == NULL) + panic("clock %s has GRF flag set but no syscon is available", + clknode_get_name(clk)); + } + + DEVICE_LOCK(clk); + if (sc->grf) { + reg = SYSCON_READ_4(sc->grf, sc->offset); + rv = 0; + } else + rv = RD4(clk, sc->offset, ®); + DEVICE_UNLOCK(clk); + if (rv != 0) { + return (rv); + } + reg = (reg >> sc->shift) & sc->mask; + clknode_init_parent_idx(clk, reg); + return(0); +} + +static int +rk_clk_mux_set_mux(struct clknode *clk, int idx) +{ + uint32_t reg; + struct rk_clk_mux_sc *sc; + int rv; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(clk); + if (sc->grf) + rv = SYSCON_MODIFY_4(sc->grf, sc->offset, sc->mask << sc->shift, + ((idx & sc->mask) << sc->shift) | RK_CLK_MUX_MASK); + else + rv = MD4(clk, sc->offset, sc->mask << sc->shift, + ((idx & sc->mask) << sc->shift) | RK_CLK_MUX_MASK); + if (rv != 0) { + DEVICE_UNLOCK(clk); + return (rv); + } + if (sc->grf == NULL) + RD4(clk, sc->offset, ®); + DEVICE_UNLOCK(clk); + + return(0); +} + +static int +rk_clk_mux_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, + int flags, int *stop) +{ + struct rk_clk_mux_sc *sc; + struct clknode *p_clk, *p_best_clk; + const char **p_names; + int p_idx, best_parent; + int rv; + + sc = clknode_get_softc(clk); + + if ((sc->mux_flags & RK_CLK_MUX_GRF) != 0) { + *stop = 1; + return (ENOTSUP); + } + if ((sc->mux_flags & RK_CLK_MUX_REPARENT) == 0) { + *stop = 0; + return (0); + } + + dprintf("Finding best parent for target freq of %ju\n", *fout); + p_names = clknode_get_parent_names(clk); + for (p_idx = 0; p_idx != clknode_get_parents_num(clk); p_idx++) { + p_clk = clknode_find_by_name(p_names[p_idx]); + dprintf("Testing with parent %s (%d)\n", + clknode_get_name(p_clk), p_idx); + + rv = clknode_set_freq(p_clk, *fout, flags | CLK_SET_DRYRUN, 0); + dprintf("Testing with parent %s (%d) rv=%d\n", + clknode_get_name(p_clk), p_idx, rv); + if (rv == 0) { + best_parent = p_idx; + p_best_clk = p_clk; + *stop = 1; + } + } + + if (!*stop) + return (0); + + if ((flags & CLK_SET_DRYRUN) != 0) + return (0); + + p_idx = clknode_get_parent_idx(clk); + if (p_idx != best_parent) { + dprintf("Switching parent index from %d to %d\n", p_idx, + best_parent); + clknode_set_parent_by_idx(clk, best_parent); + } + + clknode_set_freq(p_best_clk, *fout, flags, 0); + clknode_get_freq(p_best_clk, fout); + + return (0); +} + +int +rk_clk_mux_register(struct clkdom *clkdom, struct rk_clk_mux_def *clkdef) +{ + struct clknode *clk; + struct rk_clk_mux_sc *sc; + + clk = clknode_create(clkdom, &rk_clk_mux_class, &clkdef->clkdef); + if (clk == NULL) + return (1); + + sc = clknode_get_softc(clk); + sc->offset = clkdef->offset; + sc->shift = clkdef->shift; + sc->mask = (1 << clkdef->width) - 1; + sc->mux_flags = clkdef->mux_flags; + + clknode_register(clkdom, clk); + return (0); +} diff --git a/sys/dev/clk/rockchip/rk_clk_mux.h b/sys/dev/clk/rockchip/rk_clk_mux.h new file mode 100644 index 000000000000..b32e0687fac3 --- /dev/null +++ b/sys/dev/clk/rockchip/rk_clk_mux.h @@ -0,0 +1,47 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright 2016 Michal Meloun <mmel@FreeBSD.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#ifndef _RK_CLK_MUX_H_ +#define _RK_CLK_MUX_H_ + +#include <dev/extres/clk/clk.h> + +struct rk_clk_mux_def { + struct clknode_init_def clkdef; + uint32_t offset; + uint32_t shift; + uint32_t width; + int mux_flags; +}; + +#define RK_CLK_MUX_MASK 0xFFFF0000 +#define RK_CLK_MUX_REPARENT (1 << 0) +#define RK_CLK_MUX_GRF (1 << 1) + +int rk_clk_mux_register(struct clkdom *clkdom, struct rk_clk_mux_def *clkdef); + +#endif /* _RK_CLK_MUX_H_ */ diff --git a/sys/dev/clk/rockchip/rk_clk_pll.c b/sys/dev/clk/rockchip/rk_clk_pll.c new file mode 100644 index 000000000000..f89fdeb0c341 --- /dev/null +++ b/sys/dev/clk/rockchip/rk_clk_pll.c @@ -0,0 +1,774 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> + +#include <dev/extres/clk/clk.h> + +#include <dev/clk/rockchip/rk_clk_pll.h> + +#include "clkdev_if.h" + +struct rk_clk_pll_sc { + uint32_t base_offset; + + uint32_t gate_offset; + uint32_t gate_shift; + + uint32_t mode_reg; + uint32_t mode_shift; + + uint32_t flags; + + struct rk_clk_pll_rate *rates; + struct rk_clk_pll_rate *frac_rates; +}; + +#define WRITE4(_clk, off, val) \ + CLKDEV_WRITE_4(clknode_get_device(_clk), off, val) +#define READ4(_clk, off, val) \ + CLKDEV_READ_4(clknode_get_device(_clk), off, val) +#define DEVICE_LOCK(_clk) \ + CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) +#define DEVICE_UNLOCK(_clk) \ + CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk)) + +#define RK_CLK_PLL_MASK_SHIFT 16 + +#if 0 +#define dprintf(format, arg...) \ + printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg) +#else +#define dprintf(format, arg...) +#endif + +static int +rk_clk_pll_set_gate(struct clknode *clk, bool enable) +{ + struct rk_clk_pll_sc *sc; + uint32_t val = 0; + + sc = clknode_get_softc(clk); + + if ((sc->flags & RK_CLK_PLL_HAVE_GATE) == 0) + return (0); + + dprintf("%sabling gate\n", enable ? "En" : "Dis"); + if (!enable) + val |= 1 << sc->gate_shift; + dprintf("sc->gate_shift: %x\n", sc->gate_shift); + val |= (1 << sc->gate_shift) << RK_CLK_PLL_MASK_SHIFT; + dprintf("Write: gate_offset=%x, val=%x\n", sc->gate_offset, val); + DEVICE_LOCK(clk); + WRITE4(clk, sc->gate_offset, val); + DEVICE_UNLOCK(clk); + + return (0); +} + +/* CON0 */ +#define RK3066_CLK_PLL_REFDIV_SHIFT 8 +#define RK3066_CLK_PLL_REFDIV_MASK 0x3F00 +#define RK3066_CLK_PLL_POSTDIV_SHIFT 0 +#define RK3066_CLK_PLL_POSTDIV_MASK 0x000F +/* CON1 */ +#define RK3066_CLK_PLL_LOCK_MASK (1U << 31) +#define RK3066_CLK_PLL_FBDIV_SHIFT 0 +#define RK3066_CLK_PLL_FBDIV_MASK 0x0FFF +/* CON2 */ + +/* CON3 */ +#define RK3066_CLK_PLL_RESET (1 << 5) +#define RK3066_CLK_PLL_TEST (1 << 4) +#define RK3066_CLK_PLL_ENSAT (1 << 3) +#define RK3066_CLK_PLL_FASTEN (1 << 2) +#define RK3066_CLK_PLL_POWER_DOWN (1 << 1) +#define RK3066_CLK_PLL_BYPASS (1 << 0) + +#define RK3066_CLK_PLL_MODE_SLOW 0 +#define RK3066_CLK_PLL_MODE_NORMAL 1 +#define RK3066_CLK_PLL_MODE_DEEP_SLOW 2 +#define RK3066_CLK_PLL_MODE_MASK 0x3 + +static int +rk3066_clk_pll_init(struct clknode *clk, device_t dev) +{ + struct rk_clk_pll_sc *sc; + uint32_t reg; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(clk); + READ4(clk, sc->mode_reg, ®); + DEVICE_UNLOCK(clk); + + reg = (reg >> sc->mode_shift) & RK3066_CLK_PLL_MODE_MASK; + clknode_init_parent_idx(clk, reg); + + return (0); +} + +static int +rk3066_clk_pll_set_mux(struct clknode *clk, int idx) +{ + uint32_t reg; + struct rk_clk_pll_sc *sc; + + sc = clknode_get_softc(clk); + + reg = (idx & RK3066_CLK_PLL_MODE_MASK) << sc->mode_shift; + reg |= (RK3066_CLK_PLL_MODE_MASK << sc->mode_shift) << + RK_CLK_PLL_MASK_SHIFT; + + DEVICE_LOCK(clk); + WRITE4(clk, sc->mode_reg, reg); + DEVICE_UNLOCK(clk); + return(0); +} + +static int +rk3066_clk_pll_recalc(struct clknode *clk, uint64_t *freq) +{ + struct rk_clk_pll_sc *sc; + uint64_t rate; + uint32_t refdiv, fbdiv, postdiv; + uint32_t raw0, raw1, raw2, reg; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(clk); + + READ4(clk, sc->base_offset, &raw0); + READ4(clk, sc->base_offset + 4, &raw1); + READ4(clk, sc->base_offset + 8, &raw2); + READ4(clk, sc->mode_reg, ®); + + DEVICE_UNLOCK(clk); + + reg = (reg >> sc->mode_shift) & RK3066_CLK_PLL_MODE_MASK; + + if (reg != RK3066_CLK_PLL_MODE_NORMAL) + return (0); + + if (!(raw1 & RK3066_CLK_PLL_LOCK_MASK)) { + *freq = 0; + return (0); + } + + /* TODO MUX */ + refdiv = (raw0 & RK3066_CLK_PLL_REFDIV_MASK) >> + RK3066_CLK_PLL_REFDIV_SHIFT; + refdiv += 1; + postdiv = (raw0 & RK3066_CLK_PLL_POSTDIV_MASK) >> + RK3066_CLK_PLL_POSTDIV_SHIFT; + postdiv += 1; + fbdiv = (raw1 & RK3066_CLK_PLL_FBDIV_MASK) >> + RK3066_CLK_PLL_FBDIV_SHIFT; + fbdiv += 1; + + rate = *freq * fbdiv; + rate /= refdiv; + *freq = rate / postdiv; + + return (0); +} + +static int +rk3066_clk_pll_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, + int flags, int *stop) +{ + struct rk_clk_pll_rate *rates; + struct rk_clk_pll_sc *sc; + uint32_t reg; + int rv, timeout; + + sc = clknode_get_softc(clk); + + if (sc->rates == NULL) + return (EINVAL); + + for (rates = sc->rates; rates->freq; rates++) { + if (rates->freq == *fout) + break; + } + if (rates->freq == 0) { + *stop = 1; + return (EINVAL); + } + + DEVICE_LOCK(clk); + + /* Setting to slow mode during frequency change */ + reg = (RK3066_CLK_PLL_MODE_MASK << sc->mode_shift) << + RK_CLK_PLL_MASK_SHIFT; + dprintf("Set PLL_MODEREG to %x\n", reg); + WRITE4(clk, sc->mode_reg, reg); + + /* Reset PLL */ + WRITE4(clk, sc->base_offset + 12, RK3066_CLK_PLL_RESET | + RK3066_CLK_PLL_RESET << RK_CLK_PLL_MASK_SHIFT); + + /* Setting postdiv and refdiv */ + reg = 0; + reg |= RK3066_CLK_PLL_POSTDIV_MASK << 16; + reg |= (rates->postdiv1 - 1) << RK3066_CLK_PLL_POSTDIV_SHIFT; + + reg |= RK3066_CLK_PLL_REFDIV_MASK << 16; + reg |= (rates->refdiv - 1)<< RK3066_CLK_PLL_REFDIV_SHIFT; + + dprintf("Set PLL_CON0 to %x\n", reg); + WRITE4(clk, sc->base_offset, reg); + + + /* Setting fbdiv (no write mask)*/ + READ4(clk, sc->base_offset + 4, ®); + reg &= ~RK3066_CLK_PLL_FBDIV_MASK; + reg |= RK3066_CLK_PLL_FBDIV_MASK << 16; + reg = (rates->fbdiv - 1) << RK3066_CLK_PLL_FBDIV_SHIFT; + + dprintf("Set PLL_CON1 to %x\n", reg); + WRITE4(clk, sc->base_offset + 0x4, reg); + + /* PLL loop bandwidth adjust */ + reg = rates->bwadj - 1; + dprintf("Set PLL_CON2 to %x (%x)\n", reg, rates->bwadj); + WRITE4(clk, sc->base_offset + 0x8, reg); + + /* Clear reset */ + WRITE4(clk, sc->base_offset + 12, + RK3066_CLK_PLL_RESET << RK_CLK_PLL_MASK_SHIFT); + DELAY(100000); + + /* Reading lock */ + for (timeout = 1000; timeout >= 0; timeout--) { + READ4(clk, sc->base_offset + 0x4, ®); + if ((reg & RK3066_CLK_PLL_LOCK_MASK) != 0) + break; + DELAY(1); + } + + rv = 0; + if (timeout < 0) { + device_printf(clknode_get_device(clk), + "%s - Timedout while waiting for lock.\n", + clknode_get_name(clk)); + dprintf("PLL_CON1: %x\n", reg); + rv = ETIMEDOUT; + } + + /* Set back to normal mode */ + reg = (RK3066_CLK_PLL_MODE_NORMAL << sc->mode_shift); + reg |= (RK3066_CLK_PLL_MODE_MASK << sc->mode_shift) << + RK_CLK_PLL_MASK_SHIFT; + dprintf("Set PLL_MODEREG to %x\n", reg); + WRITE4(clk, sc->mode_reg, reg); + + DEVICE_UNLOCK(clk); + *stop = 1; + rv = clknode_set_parent_by_idx(clk, 1); + return (rv); +} + +static clknode_method_t rk3066_clk_pll_clknode_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, rk3066_clk_pll_init), + CLKNODEMETHOD(clknode_set_gate, rk_clk_pll_set_gate), + CLKNODEMETHOD(clknode_recalc_freq, rk3066_clk_pll_recalc), + CLKNODEMETHOD(clknode_set_freq, rk3066_clk_pll_set_freq), + CLKNODEMETHOD(clknode_set_mux, rk3066_clk_pll_set_mux), + CLKNODEMETHOD_END +}; + +DEFINE_CLASS_1(rk3066_clk_pll_clknode, rk3066_clk_pll_clknode_class, + rk3066_clk_pll_clknode_methods, sizeof(struct rk_clk_pll_sc), clknode_class); + +int +rk3066_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef) +{ + struct clknode *clk; + struct rk_clk_pll_sc *sc; + + clk = clknode_create(clkdom, &rk3066_clk_pll_clknode_class, + &clkdef->clkdef); + if (clk == NULL) + return (1); + + sc = clknode_get_softc(clk); + + sc->base_offset = clkdef->base_offset; + sc->gate_offset = clkdef->gate_offset; + sc->gate_shift = clkdef->gate_shift; + sc->mode_reg = clkdef->mode_reg; + sc->mode_shift = clkdef->mode_shift; + sc->flags = clkdef->flags; + sc->rates = clkdef->rates; + sc->frac_rates = clkdef->frac_rates; + + clknode_register(clkdom, clk); + + return (0); +} + +#define RK3328_CLK_PLL_FBDIV_OFFSET 0 +#define RK3328_CLK_PLL_FBDIV_SHIFT 0 +#define RK3328_CLK_PLL_FBDIV_MASK 0xFFF + +#define RK3328_CLK_PLL_POSTDIV1_OFFSET 0 +#define RK3328_CLK_PLL_POSTDIV1_SHIFT 12 +#define RK3328_CLK_PLL_POSTDIV1_MASK 0x7000 + +#define RK3328_CLK_PLL_DSMPD_OFFSET 4 +#define RK3328_CLK_PLL_DSMPD_SHIFT 12 +#define RK3328_CLK_PLL_DSMPD_MASK 0x1000 + +#define RK3328_CLK_PLL_REFDIV_OFFSET 4 +#define RK3328_CLK_PLL_REFDIV_SHIFT 0 +#define RK3328_CLK_PLL_REFDIV_MASK 0x3F + +#define RK3328_CLK_PLL_POSTDIV2_OFFSET 4 +#define RK3328_CLK_PLL_POSTDIV2_SHIFT 6 +#define RK3328_CLK_PLL_POSTDIV2_MASK 0x1C0 + +#define RK3328_CLK_PLL_FRAC_OFFSET 8 +#define RK3328_CLK_PLL_FRAC_SHIFT 0 +#define RK3328_CLK_PLL_FRAC_MASK 0xFFFFFF + +#define RK3328_CLK_PLL_LOCK_MASK 0x400 + +#define RK3328_CLK_PLL_MODE_SLOW 0 +#define RK3328_CLK_PLL_MODE_NORMAL 1 +#define RK3328_CLK_PLL_MODE_MASK 0x1 + +static int +rk3328_clk_pll_init(struct clknode *clk, device_t dev) +{ + clknode_init_parent_idx(clk, 0); + + return (0); +} + +static int +rk3328_clk_pll_recalc(struct clknode *clk, uint64_t *freq) +{ + struct rk_clk_pll_sc *sc; + uint64_t rate; + uint32_t dsmpd, refdiv, fbdiv; + uint32_t postdiv1, postdiv2, frac; + uint32_t raw1, raw2, raw3; + + sc = clknode_get_softc(clk); + + DEVICE_LOCK(clk); + + READ4(clk, sc->base_offset, &raw1); + READ4(clk, sc->base_offset + 4, &raw2); + READ4(clk, sc->base_offset + 8, &raw3); + + fbdiv = (raw1 & RK3328_CLK_PLL_FBDIV_MASK) >> RK3328_CLK_PLL_FBDIV_SHIFT; + postdiv1 = (raw1 & RK3328_CLK_PLL_POSTDIV1_MASK) >> RK3328_CLK_PLL_POSTDIV1_SHIFT; + + dsmpd = (raw2 & RK3328_CLK_PLL_DSMPD_MASK) >> RK3328_CLK_PLL_DSMPD_SHIFT; + refdiv = (raw2 & RK3328_CLK_PLL_REFDIV_MASK) >> RK3328_CLK_PLL_REFDIV_SHIFT; + postdiv2 = (raw2 & RK3328_CLK_PLL_POSTDIV2_MASK) >> RK3328_CLK_PLL_POSTDIV2_SHIFT; + + frac = (raw3 & RK3328_CLK_PLL_FRAC_MASK) >> RK3328_CLK_PLL_FRAC_SHIFT; + + DEVICE_UNLOCK(clk); + + rate = *freq * fbdiv / refdiv; + if (dsmpd == 0) { + /* Fractional mode */ + uint64_t frac_rate; + + frac_rate = *freq * frac / refdiv; + rate += frac_rate >> 24; + } + + *freq = rate / postdiv1 / postdiv2; + + if (*freq % 2) + *freq = *freq + 1; + + return (0); +} + +static int +rk3328_clk_pll_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, + int flags, int *stop) +{ + struct rk_clk_pll_rate *rates; + struct rk_clk_pll_sc *sc; + uint32_t reg; + int timeout; + + sc = clknode_get_softc(clk); + + if (sc->rates) + rates = sc->rates; + else if (sc->frac_rates) + rates = sc->frac_rates; + else + return (EINVAL); + + for (; rates->freq; rates++) { + if (rates->freq == *fout) + break; + } + if (rates->freq == 0) { + *stop = 1; + return (EINVAL); + } + + DEVICE_LOCK(clk); + + /* Setting to slow mode during frequency change */ + reg = (RK3328_CLK_PLL_MODE_MASK << sc->mode_shift) << + RK_CLK_PLL_MASK_SHIFT; + dprintf("Set PLL_MODEREG to %x\n", reg); + WRITE4(clk, sc->mode_reg, reg); + + /* Setting postdiv1 and fbdiv */ + reg = (rates->postdiv1 << RK3328_CLK_PLL_POSTDIV1_SHIFT) | + (rates->fbdiv << RK3328_CLK_PLL_FBDIV_SHIFT); + reg |= (RK3328_CLK_PLL_POSTDIV1_MASK | RK3328_CLK_PLL_FBDIV_MASK) << 16; + dprintf("Set PLL_CON0 to %x\n", reg); + WRITE4(clk, sc->base_offset, reg); + + /* Setting dsmpd, postdiv2 and refdiv */ + reg = (rates->dsmpd << RK3328_CLK_PLL_DSMPD_SHIFT) | + (rates->postdiv2 << RK3328_CLK_PLL_POSTDIV2_SHIFT) | + (rates->refdiv << RK3328_CLK_PLL_REFDIV_SHIFT); + reg |= (RK3328_CLK_PLL_DSMPD_MASK | + RK3328_CLK_PLL_POSTDIV2_MASK | + RK3328_CLK_PLL_REFDIV_MASK) << RK_CLK_PLL_MASK_SHIFT; + dprintf("Set PLL_CON1 to %x\n", reg); + WRITE4(clk, sc->base_offset + 0x4, reg); + + /* Setting frac */ + READ4(clk, sc->base_offset + 0x8, ®); + reg &= ~RK3328_CLK_PLL_FRAC_MASK; + reg |= rates->frac << RK3328_CLK_PLL_FRAC_SHIFT; + dprintf("Set PLL_CON2 to %x\n", reg); + WRITE4(clk, sc->base_offset + 0x8, reg); + + /* Reading lock */ + for (timeout = 1000; timeout; timeout--) { + READ4(clk, sc->base_offset + 0x4, ®); + if ((reg & RK3328_CLK_PLL_LOCK_MASK) == 0) + break; + DELAY(1); + } + + /* Set back to normal mode */ + reg = (RK3328_CLK_PLL_MODE_NORMAL << sc->mode_shift); + reg |= (RK3328_CLK_PLL_MODE_MASK << sc->mode_shift) << + RK_CLK_PLL_MASK_SHIFT; + dprintf("Set PLL_MODEREG to %x\n", reg); + WRITE4(clk, sc->mode_reg, reg); + + DEVICE_UNLOCK(clk); + + *stop = 1; + return (0); +} + +static clknode_method_t rk3328_clk_pll_clknode_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, rk3328_clk_pll_init), + CLKNODEMETHOD(clknode_set_gate, rk_clk_pll_set_gate), + CLKNODEMETHOD(clknode_recalc_freq, rk3328_clk_pll_recalc), + CLKNODEMETHOD(clknode_set_freq, rk3328_clk_pll_set_freq), + CLKNODEMETHOD_END +}; + +DEFINE_CLASS_1(rk3328_clk_pll_clknode, rk3328_clk_pll_clknode_class, + rk3328_clk_pll_clknode_methods, sizeof(struct rk_clk_pll_sc), clknode_class); + +int +rk3328_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef) +{ + struct clknode *clk; + struct rk_clk_pll_sc *sc; + + clk = clknode_create(clkdom, &rk3328_clk_pll_clknode_class, + &clkdef->clkdef); + if (clk == NULL) + return (1); + + sc = clknode_get_softc(clk); + + sc->base_offset = clkdef->base_offset; + sc->gate_offset = clkdef->gate_offset; + sc->gate_shift = clkdef->gate_shift; + sc->mode_reg = clkdef->mode_reg; + sc->mode_shift = clkdef->mode_shift; + sc->flags = clkdef->flags; + sc->rates = clkdef->rates; + sc->frac_rates = clkdef->frac_rates; + + clknode_register(clkdom, clk); + + return (0); +} + +#define RK3399_CLK_PLL_FBDIV_OFFSET 0 +#define RK3399_CLK_PLL_FBDIV_SHIFT 0 +#define RK3399_CLK_PLL_FBDIV_MASK 0xFFF + +#define RK3399_CLK_PLL_POSTDIV2_OFFSET 4 +#define RK3399_CLK_PLL_POSTDIV2_SHIFT 12 +#define RK3399_CLK_PLL_POSTDIV2_MASK 0x7000 + +#define RK3399_CLK_PLL_POSTDIV1_OFFSET 4 +#define RK3399_CLK_PLL_POSTDIV1_SHIFT 8 +#define RK3399_CLK_PLL_POSTDIV1_MASK 0x700 + +#define RK3399_CLK_PLL_REFDIV_OFFSET 4 +#define RK3399_CLK_PLL_REFDIV_SHIFT 0 +#define RK3399_CLK_PLL_REFDIV_MASK 0x3F + +#define RK3399_CLK_PLL_FRAC_OFFSET 8 +#define RK3399_CLK_PLL_FRAC_SHIFT 0 +#define RK3399_CLK_PLL_FRAC_MASK 0xFFFFFF + +#define RK3399_CLK_PLL_DSMPD_OFFSET 0xC +#define RK3399_CLK_PLL_DSMPD_SHIFT 3 +#define RK3399_CLK_PLL_DSMPD_MASK 0x8 + +#define RK3399_CLK_PLL_LOCK_OFFSET 8 +#define RK3399_CLK_PLL_LOCK_MASK 0x400 + +#define RK3399_CLK_PLL_MODE_OFFSET 0xC +#define RK3399_CLK_PLL_MODE_MASK 0x300 +#define RK3399_CLK_PLL_MODE_SLOW 0 +#define RK3399_CLK_PLL_MODE_NORMAL 1 +#define RK3399_CLK_PLL_MODE_DEEPSLOW 2 +#define RK3399_CLK_PLL_MODE_SHIFT 8 + +#define RK3399_CLK_PLL_WRITE_MASK 0xFFFF0000 + +static int +rk3399_clk_pll_init(struct clknode *clk, device_t dev) +{ + clknode_init_parent_idx(clk, 0); + + return (0); +} + +static int +rk3399_clk_pll_recalc(struct clknode *clk, uint64_t *freq) +{ + struct rk_clk_pll_sc *sc; + uint32_t dsmpd, refdiv, fbdiv; + uint32_t postdiv1, postdiv2, fracdiv; + uint32_t con1, con2, con3, con4; + uint64_t foutvco; + uint32_t mode; + sc = clknode_get_softc(clk); + + DEVICE_LOCK(clk); + READ4(clk, sc->base_offset, &con1); + READ4(clk, sc->base_offset + 4, &con2); + READ4(clk, sc->base_offset + 8, &con3); + READ4(clk, sc->base_offset + 0xC, &con4); + DEVICE_UNLOCK(clk); + + /* + * if we are in slow mode the output freq + * is the parent one, the 24Mhz external oscillator + * if we are in deep mode the output freq is 32.768khz + */ + mode = (con4 & RK3399_CLK_PLL_MODE_MASK) >> RK3399_CLK_PLL_MODE_SHIFT; + if (mode == RK3399_CLK_PLL_MODE_SLOW) { + dprintf("pll in slow mode, con4=%x\n", con4); + return (0); + } else if (mode == RK3399_CLK_PLL_MODE_DEEPSLOW) { + dprintf("pll in deep slow, con4=%x\n", con4); + *freq = 32768; + return (0); + } + + dprintf("con0: %x\n", con1); + dprintf("con1: %x\n", con2); + dprintf("con2: %x\n", con3); + dprintf("con3: %x\n", con4); + + fbdiv = (con1 & RK3399_CLK_PLL_FBDIV_MASK) + >> RK3399_CLK_PLL_FBDIV_SHIFT; + + postdiv1 = (con2 & RK3399_CLK_PLL_POSTDIV1_MASK) + >> RK3399_CLK_PLL_POSTDIV1_SHIFT; + postdiv2 = (con2 & RK3399_CLK_PLL_POSTDIV2_MASK) + >> RK3399_CLK_PLL_POSTDIV2_SHIFT; + refdiv = (con2 & RK3399_CLK_PLL_REFDIV_MASK) + >> RK3399_CLK_PLL_REFDIV_SHIFT; + + fracdiv = (con3 & RK3399_CLK_PLL_FRAC_MASK) + >> RK3399_CLK_PLL_FRAC_SHIFT; + fracdiv >>= 24; + + dsmpd = (con4 & RK3399_CLK_PLL_DSMPD_MASK) >> RK3399_CLK_PLL_DSMPD_SHIFT; + + dprintf("fbdiv: %d\n", fbdiv); + dprintf("postdiv1: %d\n", postdiv1); + dprintf("postdiv2: %d\n", postdiv2); + dprintf("refdiv: %d\n", refdiv); + dprintf("fracdiv: %d\n", fracdiv); + dprintf("dsmpd: %d\n", dsmpd); + + dprintf("parent freq=%ju\n", *freq); + + if (dsmpd == 0) { + /* Fractional mode */ + foutvco = *freq / refdiv * (fbdiv + fracdiv); + } else { + /* Integer mode */ + foutvco = *freq / refdiv * fbdiv; + } + dprintf("foutvco: %ju\n", foutvco); + + *freq = foutvco / postdiv1 / postdiv2; + dprintf("freq: %ju\n", *freq); + + return (0); +} + +static int +rk3399_clk_pll_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, + int flags, int *stop) +{ + struct rk_clk_pll_rate *rates; + struct rk_clk_pll_sc *sc; + uint32_t reg; + int timeout; + + sc = clknode_get_softc(clk); + + if (sc->rates) + rates = sc->rates; + else if (sc->frac_rates) + rates = sc->frac_rates; + else + return (EINVAL); + + for (; rates->freq; rates++) { + if (rates->freq == *fout) + break; + } + if (rates->freq == 0) { + *stop = 1; + return (EINVAL); + } + + DEVICE_LOCK(clk); + + /* Set to slow mode during frequency change */ + reg = RK3399_CLK_PLL_MODE_SLOW << RK3399_CLK_PLL_MODE_SHIFT; + reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT; + WRITE4(clk, sc->base_offset + 0xC, reg); + + /* Setting fbdiv */ + reg = rates->fbdiv << RK3399_CLK_PLL_FBDIV_SHIFT; + reg |= RK3399_CLK_PLL_FBDIV_MASK << RK_CLK_PLL_MASK_SHIFT; + WRITE4(clk, sc->base_offset, reg); + + /* Setting postdiv1, postdiv2 and refdiv */ + reg = rates->postdiv1 << RK3399_CLK_PLL_POSTDIV1_SHIFT; + reg |= rates->postdiv2 << RK3399_CLK_PLL_POSTDIV2_SHIFT; + reg |= rates->refdiv << RK3399_CLK_PLL_REFDIV_SHIFT; + reg |= (RK3399_CLK_PLL_POSTDIV1_MASK | RK3399_CLK_PLL_POSTDIV2_MASK | + RK3399_CLK_PLL_REFDIV_MASK) << RK_CLK_PLL_MASK_SHIFT; + WRITE4(clk, sc->base_offset + 0x4, reg); + + /* Setting frac */ + READ4(clk, sc->base_offset + 0x8, ®); + reg &= ~RK3399_CLK_PLL_FRAC_MASK; + reg |= rates->frac << RK3399_CLK_PLL_FRAC_SHIFT; + WRITE4(clk, sc->base_offset + 0x8, reg | RK3399_CLK_PLL_WRITE_MASK); + + /* Set dsmpd */ + reg = rates->dsmpd << RK3399_CLK_PLL_DSMPD_SHIFT; + reg |= RK3399_CLK_PLL_DSMPD_MASK << RK_CLK_PLL_MASK_SHIFT; + WRITE4(clk, sc->base_offset + 0xC, reg); + + /* Reading lock */ + for (timeout = 1000; timeout; timeout--) { + READ4(clk, sc->base_offset + RK3399_CLK_PLL_LOCK_OFFSET, ®); + if ((reg & RK3399_CLK_PLL_LOCK_MASK) == 0) + break; + DELAY(1); + } + + /* Set back to normal mode */ + reg = RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT; + reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT; + WRITE4(clk, sc->base_offset + 0xC, reg); + + DEVICE_UNLOCK(clk); + + *stop = 1; + return (0); +} + +static clknode_method_t rk3399_clk_pll_clknode_methods[] = { + /* Device interface */ + CLKNODEMETHOD(clknode_init, rk3399_clk_pll_init), + CLKNODEMETHOD(clknode_set_gate, rk_clk_pll_set_gate), + CLKNODEMETHOD(clknode_recalc_freq, rk3399_clk_pll_recalc), + CLKNODEMETHOD(clknode_set_freq, rk3399_clk_pll_set_freq), + CLKNODEMETHOD_END +}; + +DEFINE_CLASS_1(rk3399_clk_pll_clknode, rk3399_clk_pll_clknode_class, + rk3399_clk_pll_clknode_methods, sizeof(struct rk_clk_pll_sc), clknode_class); + +int +rk3399_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef) +{ + struct clknode *clk; + struct rk_clk_pll_sc *sc; + + clk = clknode_create(clkdom, &rk3399_clk_pll_clknode_class, + &clkdef->clkdef); + if (clk == NULL) + return (1); + + sc = clknode_get_softc(clk); + + sc->base_offset = clkdef->base_offset; + sc->gate_offset = clkdef->gate_offset; + sc->gate_shift = clkdef->gate_shift; + sc->flags = clkdef->flags; + sc->rates = clkdef->rates; + sc->frac_rates = clkdef->frac_rates; + + clknode_register(clkdom, clk); + + return (0); +} diff --git a/sys/dev/clk/rockchip/rk_clk_pll.h b/sys/dev/clk/rockchip/rk_clk_pll.h new file mode 100644 index 000000000000..2d0c0bb67fdf --- /dev/null +++ b/sys/dev/clk/rockchip/rk_clk_pll.h @@ -0,0 +1,66 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright 2018 Emmanuel Vadot <manu@FreeBSD.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _RK_CLK_PLL_H_ +#define _RK_CLK_PLL_H_ + +#include <dev/extres/clk/clk.h> + +struct rk_clk_pll_rate { + uint32_t freq; + uint32_t refdiv; + uint32_t fbdiv; + uint32_t postdiv1; + uint32_t postdiv2; + uint32_t dsmpd; + uint32_t frac; + uint32_t bwadj; +}; + +struct rk_clk_pll_def { + struct clknode_init_def clkdef; + uint32_t base_offset; + + uint32_t gate_offset; + uint32_t gate_shift; + + uint32_t mode_reg; + uint32_t mode_shift; + + uint32_t flags; + + struct rk_clk_pll_rate *rates; + struct rk_clk_pll_rate *frac_rates; +}; + +#define RK_CLK_PLL_HAVE_GATE 0x1 + +int rk3066_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef); +int rk3328_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef); +int rk3399_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef); + +#endif /* _RK_CLK_PLL_H_ */ diff --git a/sys/dev/clk/rockchip/rk_cru.c b/sys/dev/clk/rockchip/rk_cru.c new file mode 100644 index 000000000000..81760bcd74a1 --- /dev/null +++ b/sys/dev/clk/rockchip/rk_cru.c @@ -0,0 +1,305 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * RockChip Clock and Reset Unit + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/kernel.h> +#include <sys/lock.h> +#include <sys/module.h> +#include <sys/mutex.h> +#include <machine/bus.h> + +#include <dev/fdt/simplebus.h> + +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> + +#include <dev/extres/clk/clk.h> +#include <dev/extres/clk/clk_gate.h> +#include <dev/extres/clk/clk_fixed.h> +#include <dev/extres/clk/clk_link.h> +#include <dev/extres/hwreset/hwreset.h> + +#include <dev/clk/rockchip/rk_clk_composite.h> +#include <dev/clk/rockchip/rk_clk_gate.h> +#include <dev/clk/rockchip/rk_clk_mux.h> +#include <dev/clk/rockchip/rk_clk_pll.h> +#include <dev/clk/rockchip/rk_cru.h> + +#include "clkdev_if.h" +#include "hwreset_if.h" + +static struct resource_spec rk_cru_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { -1, 0 } +}; + +#define CCU_READ4(sc, reg) bus_read_4((sc)->res, (reg)) +#define CCU_WRITE4(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) + +void rk3328_cru_register_clocks(struct rk_cru_softc *sc); + +static int +rk_cru_write_4(device_t dev, bus_addr_t addr, uint32_t val) +{ + struct rk_cru_softc *sc; + + sc = device_get_softc(dev); + CCU_WRITE4(sc, addr, val); + return (0); +} + +static int +rk_cru_read_4(device_t dev, bus_addr_t addr, uint32_t *val) +{ + struct rk_cru_softc *sc; + + sc = device_get_softc(dev); + + *val = CCU_READ4(sc, addr); + return (0); +} + +static int +rk_cru_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set) +{ + struct rk_cru_softc *sc; + uint32_t reg; + + sc = device_get_softc(dev); + + reg = CCU_READ4(sc, addr); + reg &= ~clr; + reg |= set; + CCU_WRITE4(sc, addr, reg); + + return (0); +} + +static int +rk_cru_reset_assert(device_t dev, intptr_t id, bool reset) +{ + struct rk_cru_softc *sc; + uint32_t reg; + int bit; + uint32_t val; + + sc = device_get_softc(dev); + + if (id > sc->reset_num) + return (ENXIO); + + reg = sc->reset_offset + id / 16 * 4; + bit = id % 16; + + mtx_lock(&sc->mtx); + val = 0; + if (reset) + val = (1 << bit); + CCU_WRITE4(sc, reg, val | ((1 << bit) << 16)); + mtx_unlock(&sc->mtx); + + return (0); +} + +static int +rk_cru_reset_is_asserted(device_t dev, intptr_t id, bool *reset) +{ + struct rk_cru_softc *sc; + uint32_t reg; + int bit; + uint32_t val; + + sc = device_get_softc(dev); + + if (id > sc->reset_num) + return (ENXIO); + reg = sc->reset_offset + id / 16 * 4; + bit = id % 16; + + mtx_lock(&sc->mtx); + val = CCU_READ4(sc, reg); + mtx_unlock(&sc->mtx); + + *reset = false; + if (val & (1 << bit)) + *reset = true; + + return (0); +} + +static void +rk_cru_device_lock(device_t dev) +{ + struct rk_cru_softc *sc; + + sc = device_get_softc(dev); + mtx_lock(&sc->mtx); +} + +static void +rk_cru_device_unlock(device_t dev) +{ + struct rk_cru_softc *sc; + + sc = device_get_softc(dev); + mtx_unlock(&sc->mtx); +} + +static int +rk_cru_register_gates(struct rk_cru_softc *sc) +{ + struct rk_clk_gate_def def; + int i; + + for (i = 0; i < sc->ngates; i++) { + if (sc->gates[i].name == NULL) + continue; + memset(&def, 0, sizeof(def)); + def.clkdef.id = sc->gates[i].id; + def.clkdef.name = sc->gates[i].name; + def.clkdef.parent_names = &sc->gates[i].parent_name; + def.clkdef.parent_cnt = 1; + def.offset = sc->gates[i].offset; + def.shift = sc->gates[i].shift; + def.mask = 1; + def.on_value = 0; + def.off_value = 1; + rk_clk_gate_register(sc->clkdom, &def); + } + + return (0); +} + +int +rk_cru_attach(device_t dev) +{ + struct rk_cru_softc *sc; + phandle_t node; + int i; + + sc = device_get_softc(dev); + sc->dev = dev; + + node = ofw_bus_get_node(dev); + + if (bus_alloc_resources(dev, rk_cru_spec, &sc->res) != 0) { + device_printf(dev, "cannot allocate resources for device\n"); + return (ENXIO); + } + + mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + sc->clkdom = clkdom_create(dev); + if (sc->clkdom == NULL) + panic("Cannot create clkdom\n"); + + for (i = 0; i < sc->nclks; i++) { + switch (sc->clks[i].type) { + case RK_CLK_UNDEFINED: + break; + case RK3066_CLK_PLL: + rk3066_clk_pll_register(sc->clkdom, + sc->clks[i].clk.pll); + break; + case RK3328_CLK_PLL: + rk3328_clk_pll_register(sc->clkdom, + sc->clks[i].clk.pll); + break; + case RK3399_CLK_PLL: + rk3399_clk_pll_register(sc->clkdom, + sc->clks[i].clk.pll); + break; + case RK_CLK_COMPOSITE: + rk_clk_composite_register(sc->clkdom, + sc->clks[i].clk.composite); + break; + case RK_CLK_MUX: + rk_clk_mux_register(sc->clkdom, sc->clks[i].clk.mux); + break; + case RK_CLK_ARMCLK: + rk_clk_armclk_register(sc->clkdom, + sc->clks[i].clk.armclk); + break; + case RK_CLK_FIXED: + clknode_fixed_register(sc->clkdom, + sc->clks[i].clk.fixed); + break; + case RK_CLK_FRACT: + rk_clk_fract_register(sc->clkdom, + sc->clks[i].clk.fract); + break; + case RK_CLK_LINK: + clknode_link_register(sc->clkdom, + sc->clks[i].clk.link); + break; + default: + device_printf(dev, "Unknown clock type\n"); + return (ENXIO); + } + } + + if (sc->gates) + rk_cru_register_gates(sc); + + if (clkdom_finit(sc->clkdom) != 0) + panic("cannot finalize clkdom initialization\n"); + + if (bootverbose) + clkdom_dump(sc->clkdom); + + clk_set_assigned(dev, node); + + /* register our self as a reset provider */ + hwreset_register_ofw_provider(dev); + + return (0); +} + +static device_method_t rk_cru_methods[] = { + /* clkdev interface */ + DEVMETHOD(clkdev_write_4, rk_cru_write_4), + DEVMETHOD(clkdev_read_4, rk_cru_read_4), + DEVMETHOD(clkdev_modify_4, rk_cru_modify_4), + DEVMETHOD(clkdev_device_lock, rk_cru_device_lock), + DEVMETHOD(clkdev_device_unlock, rk_cru_device_unlock), + + /* Reset interface */ + DEVMETHOD(hwreset_assert, rk_cru_reset_assert), + DEVMETHOD(hwreset_is_asserted, rk_cru_reset_is_asserted), + + DEVMETHOD_END +}; + +DEFINE_CLASS_0(rk_cru, rk_cru_driver, rk_cru_methods, + sizeof(struct rk_cru_softc)); diff --git a/sys/dev/clk/rockchip/rk_cru.h b/sys/dev/clk/rockchip/rk_cru.h new file mode 100644 index 000000000000..3249c8c8f13c --- /dev/null +++ b/sys/dev/clk/rockchip/rk_cru.h @@ -0,0 +1,266 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __RK_CRU_H__ +#define __RK_CRU_H__ + +#include <dev/extres/clk/clk.h> +#include <dev/extres/clk/clk_div.h> +#include <dev/extres/clk/clk_gate.h> +#include <dev/extres/clk/clk_fixed.h> +#include <dev/extres/clk/clk_link.h> + +#include <dev/clk/rockchip/rk_clk_armclk.h> +#include <dev/clk/rockchip/rk_clk_composite.h> +#include <dev/clk/rockchip/rk_clk_fract.h> +#include <dev/clk/rockchip/rk_clk_gate.h> +#include <dev/clk/rockchip/rk_clk_mux.h> +#include <dev/clk/rockchip/rk_clk_pll.h> + +/* Macro for defining various types of clocks. */ + +/* Parent list */ +#define PLIST(_name) static const char *_name[] + +/* Pure gate */ +#define GATE(_idx, _clkname, _pname, _o, _s) \ +{ \ + .id = _idx, \ + .name = _clkname, \ + .parent_name = _pname, \ + .offset = CRU_CLKGATE_CON(_o), \ + .shift = _s, \ +} + +/* Fixed rate clock. */ +#define FRATE(_id, _name, _freq) \ +{ \ + .type = RK_CLK_FIXED, \ + .clk.fixed = &(struct clk_fixed_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = NULL, \ + .clkdef.parent_cnt = 0, \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .freq = _freq, \ + }, \ +} + +/* Fixed factor multipier/divider. */ +#define FFACT(_id, _name, _pname, _mult, _div) \ +{ \ + .type = RK_CLK_FIXED, \ + .clk.fixed = &(struct clk_fixed_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = (const char *[]){_pname}, \ + .clkdef.parent_cnt = 1, \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .mult = _mult, \ + .div = _div, \ + }, \ +} + +/* Linked clock. */ +#define LINK(_name) \ +{ \ + .type = RK_CLK_LINK, \ + .clk.link = &(struct clk_link_def) { \ + .clkdef.id = 0, \ + .clkdef.name = _name, \ + .clkdef.parent_names = NULL, \ + .clkdef.parent_cnt = 0, \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + }, \ +} + +/* Complex clock fo ARM cores. */ +#define ARMDIV(_id, _name, _pn, _r, _o, _ds, _dw, _ms, _mw, _mp, _ap) \ +{ \ + .type = RK_CLK_ARMCLK, \ + .clk.armclk = &(struct rk_clk_armclk_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = _pn, \ + .clkdef.parent_cnt = nitems(_pn), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .muxdiv_offset = CRU_CLKSEL_CON(_o), \ + .mux_shift = _ms, \ + .mux_width = _mw, \ + .div_shift = _ds, \ + .div_width = _dw, \ + .main_parent = _mp, \ + .alt_parent = _ap, \ + .rates = _r, \ + .nrates = nitems(_r), \ + }, \ +} + +/* Fractional rate multipier/divider. */ +#define FRACT(_id, _name, _pname, _f, _o) \ +{ \ + .type = RK_CLK_FRACT, \ + .clk.fract = &(struct rk_clk_fract_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = (const char *[]){_pname}, \ + .clkdef.parent_cnt = 1, \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .offset = CRU_CLKSEL_CON(_o), \ + .flags = _f, \ + }, \ +} + +/* Full composite clock. */ +#define COMP(_id, _name, _pnames, _f, _o, _ds, _dw, _ms, _mw) \ +{ \ + .type = RK_CLK_COMPOSITE, \ + .clk.composite = &(struct rk_clk_composite_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = _pnames, \ + .clkdef.parent_cnt = nitems(_pnames), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .muxdiv_offset = CRU_CLKSEL_CON(_o), \ + .mux_shift = _ms, \ + .mux_width = _mw, \ + .div_shift = _ds, \ + .div_width = _dw, \ + .flags = RK_CLK_COMPOSITE_HAVE_MUX | _f, \ + }, \ +} + +/* Composite clock without mux (divider only). */ +#define CDIV(_id, _name, _pname, _f, _o, _ds, _dw) \ +{ \ + .type = RK_CLK_COMPOSITE, \ + .clk.composite = &(struct rk_clk_composite_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = (const char *[]){_pname}, \ + .clkdef.parent_cnt = 1, \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .muxdiv_offset = CRU_CLKSEL_CON(_o), \ + .div_shift = _ds, \ + .div_width = _dw, \ + .flags = _f, \ + }, \ +} + +/* Complex clock without divider (multiplexer only). */ +#define MUXRAW(_id, _name, _pn, _f, _mo, _ms, _mw) \ +{ \ + .type = RK_CLK_MUX, \ + .clk.mux = &(struct rk_clk_mux_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = _pn, \ + .clkdef.parent_cnt = nitems(_pn), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .offset = _mo, \ + .shift = _ms, \ + .width = _mw, \ + .mux_flags = _f, \ + }, \ +} + +#define MUX(_id, _name, _pn, _f, _mo, _ms, _mw) \ + MUXRAW(_id, _name, _pn, _f, CRU_CLKSEL_CON(_mo), _ms, _mw) + +/* Complex clock without divider (multiplexer only in GRF). */ +#define MUXGRF(_id, _name, _pn, _f, _mo, _ms, _mw) \ +{ \ + .type = RK_CLK_MUX, \ + .clk.mux = &(struct rk_clk_mux_def) { \ + .clkdef.id = _id, \ + .clkdef.name = _name, \ + .clkdef.parent_names = _pn, \ + .clkdef.parent_cnt = nitems(_pn), \ + .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ + .offset = _mo, \ + .shift = _ms, \ + .width = _mw, \ + .mux_flags = RK_CLK_MUX_GRF | _f, \ + }, \ +} + +struct rk_cru_gate { + const char *name; + const char *parent_name; + uint32_t id; + uint32_t offset; + uint32_t shift; +}; + +enum rk_clk_type { + RK_CLK_UNDEFINED = 0, + RK3066_CLK_PLL, + RK3328_CLK_PLL, + RK3399_CLK_PLL, + RK_CLK_COMPOSITE, + RK_CLK_FIXED, + RK_CLK_FRACT, + RK_CLK_MUX, + RK_CLK_ARMCLK, + RK_CLK_LINK, +}; + +struct rk_clk { + enum rk_clk_type type; + union { + struct rk_clk_pll_def *pll; + struct rk_clk_composite_def *composite; + struct rk_clk_mux_def *mux; + struct rk_clk_armclk_def *armclk; + struct clk_fixed_def *fixed; + struct rk_clk_fract_def *fract; + struct clk_link_def *link; + } clk; +}; + +struct rk_cru_softc { + device_t dev; + struct resource *res; + struct clkdom *clkdom; + struct mtx mtx; + int type; + uint32_t reset_offset; + uint32_t reset_num; + struct rk_cru_gate *gates; + int ngates; + struct rk_clk *clks; + int nclks; + struct rk_clk_armclk_def *armclk; + struct rk_clk_armclk_rates *armclk_rates; + int narmclk_rates; +}; + +DECLARE_CLASS(rk_cru_driver); + +int rk_cru_attach(device_t dev); + +#endif /* __RK_CRU_H__ */ |