diff options
| author | Pyun YongHyeon <yongari@FreeBSD.org> | 2008-09-26 00:52:51 +0000 |
|---|---|---|
| committer | Pyun YongHyeon <yongari@FreeBSD.org> | 2008-09-26 00:52:51 +0000 |
| commit | 1cb1a10c9e5f9c991b666482f823ca18aa825193 (patch) | |
| tree | 4dd94666e9dd0b196eccb1f58ee13dcd621e643f /sys/dev/jme | |
| parent | af82b7bd5b71d5f25c4c40e9965899d597437833 (diff) | |
Notes
Diffstat (limited to 'sys/dev/jme')
| -rw-r--r-- | sys/dev/jme/if_jme.c | 14 | ||||
| -rw-r--r-- | sys/dev/jme/if_jmereg.h | 9 |
2 files changed, 20 insertions, 3 deletions
diff --git a/sys/dev/jme/if_jme.c b/sys/dev/jme/if_jme.c index 231f65a009d1..59b1bb7c71b2 100644 --- a/sys/dev/jme/if_jme.c +++ b/sys/dev/jme/if_jme.c @@ -1940,7 +1940,7 @@ static void jme_mac_config(struct jme_softc *sc) { struct mii_data *mii; - uint32_t ghc, rxmac, txmac, txpause; + uint32_t ghc, gpreg, rxmac, txmac, txpause; JME_LOCK_ASSERT(sc); @@ -1996,9 +1996,19 @@ jme_mac_config(struct jme_softc *sc) default: break; } - /* Workaround CRC errors at 100Mbps on JMC250 A2. */ if (sc->jme_rev == DEVICEID_JMC250 && sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { + /* + * Workaround occasional packet loss issue of JMC250 A2 + * when it runs on half-duplex media. + */ + gpreg = CSR_READ_4(sc, JME_GPREG1); + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) + gpreg &= ~GPREG1_HDPX_FIX; + else + gpreg |= GPREG1_HDPX_FIX; + CSR_WRITE_4(sc, JME_GPREG1, gpreg); + /* Workaround CRC errors at 100Mbps on JMC250 A2. */ if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { /* Extend interface FIFO depth. */ jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, diff --git a/sys/dev/jme/if_jmereg.h b/sys/dev/jme/if_jmereg.h index a796a8b452be..9808fa5e9f80 100644 --- a/sys/dev/jme/if_jmereg.h +++ b/sys/dev/jme/if_jmereg.h @@ -574,8 +574,15 @@ #define GPREG0_PHY_ADDR_SHIFT 0 #define GPREG0_PHY_ADDR 1 -/* General purpose register 1. reserved for future use. */ +/* General purpose register 1. */ #define JME_GPREG1 0x080C +#define GPREG1_RSS_IPV6_10_100 0x00000040 /* JMC250 A2 */ +#define GPREG1_HDPX_FIX 0x00000020 /* JMC250 A2 */ +#define GPREG1_INTDLY_UNIT_16US 0x00000018 /* JMC250 A1, A2 */ +#define GPREG1_INTDLY_UNIT_1US 0x00000010 /* JMC250 A1, A2 */ +#define GPREG1_INTDLY_UNIT_256NS 0x00000008 /* JMC250 A1, A2 */ +#define GPREG1_INTDLY_UNIT_16NS 0x00000000 /* JMC250 A1, A2 */ +#define GPREG1_INTDLY_MASK 0x00000007 /* MSIX entry number of interrupt source. */ #define JME_MSINUM_BASE 0x0810 |