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authorEitan Adler <eadler@FreeBSD.org>2018-01-12 06:36:44 +0000
committerEitan Adler <eadler@FreeBSD.org>2018-01-12 06:36:44 +0000
commit02ca39cff2274cfd8f669b8cd1ef17ec44c4bd67 (patch)
treeb6834df571a35e098a6d9ddb5953656282d63d15 /sys/dev/mlx4
parent066ebd56c13b1599f1b3d67b3b77a9d70d648e75 (diff)
Notes
Diffstat (limited to 'sys/dev/mlx4')
-rw-r--r--sys/dev/mlx4/cq.h2
-rw-r--r--sys/dev/mlx4/mlx4_core/mlx4_fw.c2
-rw-r--r--sys/dev/mlx4/mlx4_core/mlx4_mcg.c2
-rw-r--r--sys/dev/mlx4/mlx4_en/mlx4_en_tx.c12
-rw-r--r--sys/dev/mlx4/mlx4_ib/mlx4_ib.h2
-rw-r--r--sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c14
-rw-r--r--sys/dev/mlx4/qp.h8
7 files changed, 21 insertions, 21 deletions
diff --git a/sys/dev/mlx4/cq.h b/sys/dev/mlx4/cq.h
index 6b338d842139..ee8ae4a89798 100644
--- a/sys/dev/mlx4/cq.h
+++ b/sys/dev/mlx4/cq.h
@@ -86,7 +86,7 @@ struct mlx4_ts_cqe {
} __packed;
enum {
- MLX4_CQE_L2_TUNNEL_IPOK = 1 << 31,
+ MLX4_CQE_L2_TUNNEL_IPOK = 1U << 31,
MLX4_CQE_CVLAN_PRESENT_MASK = 1 << 29,
MLX4_CQE_SVLAN_PRESENT_MASK = 1 << 30,
MLX4_CQE_L2_TUNNEL = 1 << 27,
diff --git a/sys/dev/mlx4/mlx4_core/mlx4_fw.c b/sys/dev/mlx4/mlx4_core/mlx4_fw.c
index edd76e924e2b..8ad31b812428 100644
--- a/sys/dev/mlx4/mlx4_core/mlx4_fw.c
+++ b/sys/dev/mlx4/mlx4_core/mlx4_fw.c
@@ -1944,7 +1944,7 @@ int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
#endif
if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT)
- *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31);
+ *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1U << 31);
/* QPC/EEC/CQC/EQC/RDMARC attributes */
diff --git a/sys/dev/mlx4/mlx4_core/mlx4_mcg.c b/sys/dev/mlx4/mlx4_core/mlx4_mcg.c
index d202b77f69c3..2741196783c1 100644
--- a/sys/dev/mlx4/mlx4_core/mlx4_mcg.c
+++ b/sys/dev/mlx4/mlx4_core/mlx4_mcg.c
@@ -1352,7 +1352,7 @@ static int mlx4_QP_ATTACH(struct mlx4_dev *dev, struct mlx4_qp *qp,
qpn = qp->qpn;
qpn |= (prot << 28);
if (attach && block_loopback)
- qpn |= (1 << 31);
+ qpn |= (1U << 31);
err = mlx4_cmd(dev, mailbox->dma, qpn, attach,
MLX4_CMD_QP_ATTACH, MLX4_CMD_TIME_CLASS_A,
diff --git a/sys/dev/mlx4/mlx4_en/mlx4_en_tx.c b/sys/dev/mlx4/mlx4_en/mlx4_en_tx.c
index f3d700502977..a3692712767a 100644
--- a/sys/dev/mlx4/mlx4_en/mlx4_en_tx.c
+++ b/sys/dev/mlx4/mlx4_en/mlx4_en_tx.c
@@ -600,16 +600,16 @@ mlx4_en_store_inline_header(volatile struct mlx4_wqe_data_seg *dseg,
if (unlikely(len < MIN_PKT_LEN)) {
*(volatile uint32_t *)inl =
- SET_BYTE_COUNT((1 << 31) | MIN_PKT_LEN);
+ SET_BYTE_COUNT((1U << 31) | MIN_PKT_LEN);
} else if (len <= spc) {
*(volatile uint32_t *)inl =
- SET_BYTE_COUNT((1 << 31) | len);
+ SET_BYTE_COUNT((1U << 31) | len);
} else {
*(volatile uint32_t *)(inl + 4 + spc) =
- SET_BYTE_COUNT((1 << 31) | (len - spc));
+ SET_BYTE_COUNT((1U << 31) | (len - spc));
wmb();
*(volatile uint32_t *)inl =
- SET_BYTE_COUNT((1 << 31) | spc);
+ SET_BYTE_COUNT((1U << 31) | spc);
}
}
@@ -885,7 +885,7 @@ static int mlx4_en_xmit(struct mlx4_en_priv *priv, int tx_ind, struct mbuf **mbp
dseg->addr = 0;
dseg->lkey = 0;
wmb();
- dseg->byte_count = SET_BYTE_COUNT((1 << 31)|0);
+ dseg->byte_count = SET_BYTE_COUNT((1U << 31)|0);
}
/* fill segment list */
@@ -895,7 +895,7 @@ static int mlx4_en_xmit(struct mlx4_en_priv *priv, int tx_ind, struct mbuf **mbp
dseg->addr = 0;
dseg->lkey = 0;
wmb();
- dseg->byte_count = SET_BYTE_COUNT((1 << 31)|0);
+ dseg->byte_count = SET_BYTE_COUNT((1U << 31)|0);
} else {
dseg--;
dseg->addr = cpu_to_be64((uint64_t)segs[nr_segs].ds_addr);
diff --git a/sys/dev/mlx4/mlx4_ib/mlx4_ib.h b/sys/dev/mlx4/mlx4_ib/mlx4_ib.h
index 87cc448a9046..09f9eeb58794 100644
--- a/sys/dev/mlx4/mlx4_ib/mlx4_ib.h
+++ b/sys/dev/mlx4/mlx4_ib/mlx4_ib.h
@@ -195,7 +195,7 @@ enum mlx4_ib_qp_flags {
/* Mellanox specific flags start from IB_QP_CREATE_RESERVED_START */
MLX4_IB_ROCE_V2_GSI_QP = MLX4_IB_QP_CREATE_ROCE_V2_GSI,
MLX4_IB_SRIOV_TUNNEL_QP = 1 << 30,
- MLX4_IB_SRIOV_SQP = 1 << 31,
+ MLX4_IB_SRIOV_SQP = 1U << 31,
};
struct mlx4_ib_gid_entry {
diff --git a/sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c b/sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c
index 98c1a43cea1d..a3bd86b182cb 100644
--- a/sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c
+++ b/sys/dev/mlx4/mlx4_ib/mlx4_ib_qp.c
@@ -263,7 +263,7 @@ static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
/* Pad the remainder of the WQE with an inline data segment. */
if (size > s) {
inl = wqe + s;
- inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
+ inl->byte_count = cpu_to_be32(1U << 31 | (size - s - sizeof *inl));
}
ctrl->srcrb_flags = 0;
ctrl->fence_size = size / 16;
@@ -274,7 +274,7 @@ static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
wmb();
ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
- (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
+ (n & qp->sq.wqe_cnt ? cpu_to_be32(1U << 31) : 0);
stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
}
@@ -1992,7 +1992,7 @@ static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
for (i = 0; i < qp->sq.wqe_cnt; ++i) {
ctrl = get_send_wqe(qp, i);
- ctrl->owner_opcode = cpu_to_be32(1 << 31);
+ ctrl->owner_opcode = cpu_to_be32(1U << 31);
if (qp->sq_max_wqes_per_wr == 1)
ctrl->fence_size =
1 << (qp->sq.wqe_shift - 4);
@@ -2653,11 +2653,11 @@ static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
spc = MLX4_INLINE_ALIGN -
((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
if (header_size <= spc) {
- inl->byte_count = cpu_to_be32(1 << 31 | header_size);
+ inl->byte_count = cpu_to_be32(1U << 31 | header_size);
memcpy(inl + 1, sqp->header_buf, header_size);
i = 1;
} else {
- inl->byte_count = cpu_to_be32(1 << 31 | spc);
+ inl->byte_count = cpu_to_be32(1U << 31 | spc);
memcpy(inl + 1, sqp->header_buf, spc);
inl = (void *) (inl + 1) + spc;
@@ -2676,7 +2676,7 @@ static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
* of 16 mod 64.
*/
wmb();
- inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
+ inl->byte_count = cpu_to_be32(1U << 31 | (header_size - spc));
i = 2;
}
@@ -3213,7 +3213,7 @@ int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
}
ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
- (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
+ (ind & qp->sq.wqe_cnt ? cpu_to_be32(1U << 31) : 0) | blh;
stamp = ind + qp->sq_spare_wqes;
ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
diff --git a/sys/dev/mlx4/qp.h b/sys/dev/mlx4/qp.h
index fff16de040da..27d96a436a32 100644
--- a/sys/dev/mlx4/qp.h
+++ b/sys/dev/mlx4/qp.h
@@ -283,7 +283,7 @@ enum { /* param3 */
#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
enum {
- MLX4_WQE_CTRL_OWN = 1 << 31,
+ MLX4_WQE_CTRL_OWN = 1U << 31,
MLX4_WQE_CTRL_NEC = 1 << 29,
MLX4_WQE_CTRL_RR = 1 << 6,
MLX4_WQE_CTRL_IIP = 1 << 28,
@@ -371,7 +371,7 @@ struct mlx4_wqe_lso_seg {
enum mlx4_wqe_bind_seg_flags2 {
MLX4_WQE_BIND_ZERO_BASED = (1 << 30),
- MLX4_WQE_BIND_TYPE_2 = (1 << 31),
+ MLX4_WQE_BIND_TYPE_2 = (1U << 31),
};
struct mlx4_wqe_bind_seg {
@@ -388,7 +388,7 @@ enum {
MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29,
MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30,
- MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31
+ MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1U << 31
};
struct mlx4_wqe_fmr_seg {
@@ -445,7 +445,7 @@ struct mlx4_wqe_data_seg {
enum {
MLX4_INLINE_ALIGN = 64,
- MLX4_INLINE_SEG = 1 << 31,
+ MLX4_INLINE_SEG = 1U << 31,
};
struct mlx4_wqe_inline_seg {