1 files changed, 509 insertions, 2 deletions

diff --git a/sys/dev/nctgpio/nctgpio.c b/sys/dev/nctgpio/nctgpio.c
index 607a5f3e56cf..fc3de033968f 100644
--- a/sys/dev/nctgpio/nctgpio.c
+++ b/sys/dev/nctgpio/nctgpio.c
@@ -151,6 +151,73 @@ struct nct_device {
 	struct nct_gpio_group     groups[NCT_MAX_GROUP + 1];
 } nct_devices[] = {
 	{
+		.devid   = 0xa025,
+		.descr   = "GPIO on Winbond 83627DHG IC ver. 5",
+		.ngroups = 5,
+		.groups  = {
+			{
+				.grpnum      = 2,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x01,
+				.data_ldn    = 0x09,
+				.ppod_reg    = 0xe0, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xe3,
+			},
+			{
+				.grpnum      = 3,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x02,
+				.data_ldn    = 0x09,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xf0,
+			},
+			{
+				.grpnum      = 4,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x04,
+				.data_ldn    = 0x09,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xf4,
+			},
+			{
+				.grpnum      = 5,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x08,
+				.data_ldn    = 0x09,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xe0,
+			},
+			{
+				.grpnum      = 6,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x07,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x01,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xf4,
+			},
+		},
+	},
+	{
 		.devid   = 0x1061,
 		.descr   = "GPIO on Nuvoton NCT5104D",
 		.ngroups = 2,
@@ -182,7 +249,7 @@ struct nct_device {
 		},
 	},
 	{
-		.devid   = 0xc452,
+		.devid   = 0xc452, /* FIXME Conflict with Nuvoton NCT6106D. See NetBSD's nct_match. */
 		.descr   = "GPIO on Nuvoton NCT5104D (PC-Engines APU)",
 		.ngroups = 2,
 		.groups  = {
@@ -243,6 +310,445 @@ struct nct_device {
 			},
 		},
 	},
+	{
+		.devid  = 0xd42a,
+		.extid  = 1,
+		.descr  = "GPIO on Nuvoton NCT6796D-E",
+		.ngroups = 10,
+		.groups  = {
+			{
+				.grpnum      = 0,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x08,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x02,
+				.data_ldn    = 0x08,
+				.ppod_reg    = 0xe0, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xe0,
+			},
+			{
+				.grpnum      = 1,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x08,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x80,
+				.data_ldn    = 0x08,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xf0,
+			},
+			{
+				.grpnum      = 2,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x01,
+				.data_ldn    = 0x09,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xe0,
+			},
+			{
+				.grpnum      = 3,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x02,
+				.data_ldn    = 0x09,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 7,
+				.iobase      = 0xe4,
+			},
+			{
+				.grpnum      = 4,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x04,
+				.data_ldn    = 0x09,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xf0, /* FIXME Page 344 say "F0~F2, E8",
+										not "F0~F3". */
+			},
+			{
+				.grpnum      = 5,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x08,
+				.data_ldn    = 0x09,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xf4,
+			},
+			{
+				.grpnum      = 6,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x07,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x01,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xf4,
+			},
+			{
+				.grpnum      = 7,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x07,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x02,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xe0,
+			},
+			{
+				.grpnum      = 8,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x07,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x04,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xe4,
+			},
+			{
+				.grpnum      = 9,
+				.pinbits     = { 0, 1, 2, 3 },
+				.enable_ldn  = 0x07,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x08,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 4,
+				.iobase      = 0xe8,
+			},
+		},
+	},
+	{
+		.devid   = 0xd42a,
+		.extid   = 2,
+		.descr   = "GPIO on Nuvoton NCT5585D",
+		.ngroups = 6,
+		.groups  = {
+			{
+				.grpnum      = 2,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x01,
+				.data_ldn    = 0x09,
+				.ppod_reg    = 0xe1,
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 7,
+				.iobase      = 0xe0,
+			},
+			{
+				.grpnum      = 3,
+				.pinbits     = { 1, 2, 3 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x02,
+				.data_ldn    = 0x09,
+				.ppod_reg    = 0xe2,
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 3,
+				.iobase      = 0xe4,
+			},
+			{
+				.grpnum      = 5,
+				.pinbits     = { 0, 2, 6, 7 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x08,
+				.data_ldn    = 0x09,
+				.ppod_reg    = 0xe4,
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 4,
+				.iobase      = 0xf4,
+			},
+			{
+				.grpnum      = 7,
+				.pinbits     = { 4 },
+				.enable_ldn  = 0x07,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x02,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe6,
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 1,
+				.iobase      = 0xe0,
+			},
+			{
+				.grpnum      = 8,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x07,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x04,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe7,
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xe4,
+			},
+			{
+				.grpnum      = 9,
+				.pinbits     = { 0, 2 },
+				.enable_ldn  = 0x07,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x08,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xea,
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 2,
+				.iobase      = 0xe8,
+			},
+		},
+	},
+	{
+		.devid   = 0xc562,
+		.descr   = "GPIO on Nuvoton NCT6779D",
+		.ngroups = 9,
+		.groups  = {
+			{
+				.grpnum      = 0,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x08,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x01,
+				.data_ldn    = 0x08,
+				.ppod_reg    = 0xe0, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xe0,
+			},
+			{
+				.grpnum      = 1,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x01,
+				.data_ldn    = 0x08,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xf0,
+			},
+			{
+				.grpnum      = 2,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x01,
+				.data_ldn    = 0x09,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xe0,
+			},
+			{
+				.grpnum      = 3,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x02,
+				.data_ldn    = 0x09,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 7,
+				.iobase      = 0xe4,
+			},
+			{
+				.grpnum      = 4,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x04,
+				.data_ldn    = 0x09,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xf0,
+			},
+			{
+				.grpnum      = 5,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x08,
+				.data_ldn    = 0x09,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xf4,
+			},
+			{
+				.grpnum      = 6,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x01,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xf4,
+			},
+			{
+				.grpnum      = 7,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x02,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 7,
+				.iobase      = 0xe0,
+			},
+			{
+				.grpnum      = 8,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x04,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xe4,
+			},
+		},
+	},
+	{
+		.devid   = 0xd282,
+		.descr   = "GPIO on Nuvoton NCT6112D/NCT6114D/NCT6116D",
+		.ngroups = 2,
+		.groups  = {
+			{
+				.grpnum      = 0,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x07,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x01,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe0, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xe0,
+			},
+			{
+				.grpnum      = 1,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x07,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x02,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xe4,
+			},
+			{
+				.grpnum      = 2,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x07,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x04,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xe8,
+			},
+			{
+				.grpnum      = 3,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x07,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x08,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xec,
+			},
+			{
+				.grpnum      = 4,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x07,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x10,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xf0,
+			},
+			{
+				.grpnum      = 5,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x07,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x20,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xf4,
+			},
+			{
+				.grpnum      = 6,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x07,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x40,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xf8,
+			},
+			{
+				.grpnum      = 7,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x07,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x80,
+				.data_ldn    = 0x07,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xfc,
+			},
+			{
+				.grpnum      = 8,
+				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
+				.enable_ldn  = 0x09,
+				.enable_reg  = 0x30,
+				.enable_mask = 0x01,
+				.data_ldn    = 0x09,
+				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
+				.caps        = NCT_GPIO_CAPS,
+				.npins       = 8,
+				.iobase      = 0xf0,
+			},
+		},
+	},
 };
 
 static const char *
@@ -533,6 +1039,7 @@ nct_read_pin(struct nct_softc *sc, uint32_t pin_num)
 	return (val);
 }
 
+/* FIXME Incorret for NCT5585D and probably other chips. */
 static uint8_t
 nct_ppod_reg(struct nct_softc *sc, uint32_t pin_num)
 {
@@ -659,7 +1166,7 @@ nct_attach(device_t dev)
 			sc->curgrp = -1;
 			sc->iorid = 0;
 			err = bus_set_resource(dev, SYS_RES_IOPORT, sc->iorid,
-				iobase, 7);
+				iobase, 7); /* FIXME NCT6796D-E have 8 registers according to table 18.3. */
 			if (err == 0) {
 				sc->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
 					&sc->iorid, RF_ACTIVE);