2 files changed, 24 insertions, 5 deletions

diff --git a/sys/dev/pci/pcireg.h b/sys/dev/pci/pcireg.h
index c48b269789fd..d41a11bdd0b5 100644
--- a/sys/dev/pci/pcireg.h
+++ b/sys/dev/pci/pcireg.h
@@ -265,6 +265,11 @@
 #define	PCIR_BIOS_1	0x38
 #define	PCIR_BRIDGECTL_1 0x3e
 
+#define	PCI_PPBMEMBASE(h,l)  ((((uint64_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
+#define	PCI_PPBMEMLIMIT(h,l) ((((uint64_t)(h) << 32) + ((l)<<16)) | 0xfffff)
+#define	PCI_PPBIOBASE(h,l)   ((((h)<<16) + ((l)<<8)) & ~0xfff)
+#define	PCI_PPBIOLIMIT(h,l)  ((((h)<<16) + ((l)<<8)) | 0xfff)
+
 /* config registers for header type 2 (CardBus) devices */
 
 #define	PCIR_MAX_BAR_2	0
@@ -284,6 +289,9 @@
 #define	PCIR_IOLIMIT0_2	0x30
 #define	PCIR_IOBASE1_2	0x34
 #define	PCIR_IOLIMIT1_2	0x38
+#define	PCIM_CBBIO_16		0x0
+#define	PCIM_CBBIO_32		0x1
+#define	PCIM_CBBIO_MASK		0x3
 
 #define	PCIR_BRIDGECTL_2 0x3e
 
@@ -292,6 +300,11 @@
 
 #define	PCIR_PCCARDIF_2	0x44
 
+#define	PCI_CBBMEMBASE(l)  ((l) & ~0xfffff)
+#define	PCI_CBBMEMLIMIT(l) ((l) | 0xfffff)
+#define	PCI_CBBIOBASE(l)   ((l) & ~0x3)
+#define	PCI_CBBIOLIMIT(l)  ((l) | 0x3)
+
 /* PCI device class, subclass and programming interface definitions */
 
 #define	PCIC_OLD	0x00
@@ -479,6 +492,17 @@
 #define	PCIB_BCR_DISCARD_TIMER_STATUS	0x0400
 #define	PCIB_BCR_DISCARD_TIMER_SERREN	0x0800
 
+#define	CBB_BCR_PERR_ENABLE		0x0001
+#define	CBB_BCR_SERR_ENABLE		0x0002
+#define	CBB_BCR_ISA_ENABLE		0x0004
+#define	CBB_BCR_VGA_ENABLE		0x0008
+#define	CBB_BCR_MASTER_ABORT_MODE	0x0020
+#define	CBB_BCR_CARDBUS_RESET		0x0040
+#define	CBB_BCR_IREQ_INT_ENABLE		0x0080
+#define	CBB_BCR_PREFETCH_0_ENABLE	0x0100
+#define	CBB_BCR_PREFETCH_1_ENABLE	0x0200
+#define	CBB_BCR_WRITE_POSTING_ENABLE	0x0400
+
 /* PCI power manangement */
 #define	PCIR_POWER_CAP		0x2
 #define	PCIM_PCAP_SPEC			0x0007
diff --git a/sys/dev/pci/pcivar.h b/sys/dev/pci/pcivar.h
index b8f64c2d9793..8b1d6a9893ab 100644
--- a/sys/dev/pci/pcivar.h
+++ b/sys/dev/pci/pcivar.h
@@ -211,11 +211,6 @@ typedef struct pcicfg {
 
 /* additional type 1 device config header information (PCI to PCI bridge) */
 
-#define	PCI_PPBMEMBASE(h,l)  ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
-#define	PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
-#define	PCI_PPBIOBASE(h,l)   ((((h)<<16) + ((l)<<8)) & ~0xfff)
-#define	PCI_PPBIOLIMIT(h,l)  ((((h)<<16) + ((l)<<8)) | 0xfff)
-
 typedef struct {
     pci_addr_t	pmembase;	/* base address of prefetchable memory */
     pci_addr_t	pmemlimit;	/* topmost address of prefetchable memory */