diff options
| author | David C Somayajulu <davidcs@FreeBSD.org> | 2018-07-25 02:36:55 +0000 |
|---|---|---|
| committer | David C Somayajulu <davidcs@FreeBSD.org> | 2018-07-25 02:36:55 +0000 |
| commit | 217ec20885fd2a44a9bb369b8d69eb35139ffafc (patch) | |
| tree | fe6503180b7998d70243ee4ae3b1240a4dde3d9e /sys/dev/qlnx/qlnxe/reg_addr.h | |
| parent | eed76687f0105592305a70f243a101ec94a1d4cc (diff) | |
| download | src-217ec20885fd2a44a9bb369b8d69eb35139ffafc.tar.gz src-217ec20885fd2a44a9bb369b8d69eb35139ffafc.zip | |
Notes
Diffstat (limited to 'sys/dev/qlnx/qlnxe/reg_addr.h')
| -rw-r--r-- | sys/dev/qlnx/qlnxe/reg_addr.h | 16225 |
1 files changed, 10324 insertions, 5901 deletions
diff --git a/sys/dev/qlnx/qlnxe/reg_addr.h b/sys/dev/qlnx/qlnxe/reg_addr.h index f915a607557a..a77810d6f76b 100644 --- a/sys/dev/qlnx/qlnxe/reg_addr.h +++ b/sys/dev/qlnx/qlnxe/reg_addr.h @@ -81,61 +81,113 @@ #define PGLCS_REG_SYNCFIFO_POP_UNDERFLOW_K2_E5 0x003830UL //Access:R DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW header sync fifo pop underflow 3 - TXW data sync fifo pop underflow #define PGLCS_REG_SYNCFIFO_PUSH_OVERFLOW_K2_E5 0x003834UL //Access:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header sync fifo push overflow 5:2 - RX data sync fifo push overflow (1 bit per each 128b instance) #define PGLCS_REG_TX_SYNCFIFO_POP_STATUS_K2_E5 0x003838UL //Access:R DataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW header sync fifo pop status 19:15 - TXW data sync fifo pop status -#define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_K2_E5 0x000000UL //Access:RW DataWidth:0x20 // Device ID and Vendor ID Register. - #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_K2_E5 (0xffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_K2_E5 (0xffff<<16) // Device ID. Vendor Assigned Device Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_K2_E5_SHIFT 16 +#define PCIEIP_REG_PCIEEP_ID_E5 0x000000UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_ID_VENDID_E5 (0xffff<<0) // Cavium's vendor ID, writable through PEM()_CFG_WR. During an EPROM Load, if a value of 0xFFFF is loaded to this field and a value of 0xFFFF is loaded to the [DEVID] field of this register, the value will not be loaded, EEPROM load will stop, and the FastLinkEnable bit will be set in the PCIEEP_PORT_CTL register. + #define PCIEIP_REG_PCIEEP_ID_VENDID_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_ID_DEVID_E5 (0xffff<<16) // Device ID for PCIERP, writable through PEM()_CFG_WR. Firmware must configure this field prior to starting the link. _ <15:8> is typically set to the appropriate chip number, from the FUS_FUSE_NUM_E::CHIP_TYPE() fuses, and as enumerated by PCC_PROD_E::CNXXXX. _ <7:0> is typically set to PCC_DEV_IDL_E::PCIERC. + #define PCIEIP_REG_PCIEEP_ID_DEVID_E5_SHIFT 16 +#define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_K2 0x000000UL //Access:RW DataWidth:0x20 // Device ID and Vendor ID Register. + #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_K2 (0xffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_K2_SHIFT 0 + #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_K2 (0xffff<<16) // Device ID. Vendor Assigned Device Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_K2_SHIFT 16 #define PCIEIP_REG_DEVICE_VENDOR_ID_BB 0x000000UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_DEVICE_VENDOR_ID_VENDOR_ID_BB (0xffff<<0) // This register identifies the PCI adapter. This value can be written by firmware through the PCIE private register space VENDOR_ID to modify this read value to the host. Path = i_cfg_func.i_cfg_private #define PCIEIP_REG_DEVICE_VENDOR_ID_VENDOR_ID_BB_SHIFT 0 #define PCIEIP_REG_DEVICE_VENDOR_ID_DEVICE_ID_BB (0xffff<<16) // This register identifies the device on the PCIE adapter. This value can be written by firmware through the PCIE private register space DEVICE_ID, which modifes the value read by host. The default value reflects the value of DEVICE_ID in version.v or strap pins user_device_id depending on build options chosen by user. Path = i_cfg_func.i_cfg_private #define PCIEIP_REG_DEVICE_VENDOR_ID_DEVICE_ID_BB_SHIFT 16 -#define PCIEIP_REG_STATUS_COMMAND_REG_K2_E5 0x000004UL //Access:RW DataWidth:0x20 // Command and Status Register. - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_K2_E5 (0x1<<0) // Enables IO Access Response. You cannot write to this register if your configuration has no IO bars; that is, the internal signal has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_K2_E5_SHIFT 0 - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_K2_E5 (0x1<<1) // Enables Memory Access Response. You cannot write to this register if your configuration has no MEM bars; that is, the internal signal has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_K2_E5_SHIFT 1 - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_K2_E5 (0x1<<2) // Bus Master Enable. Controls Issuing of Memory and I/O Requests. - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_K2_E5_SHIFT 2 - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_K2_E5 (0x1<<3) // Special Cycle Enable. - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_K2_E5_SHIFT 3 - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_K2_E5 (0x1<<4) // Memory Write and Invalidate. - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_K2_E5_SHIFT 4 - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_K2_E5 (0x1<<5) // VGA Palette Snoop. - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_K2_E5_SHIFT 5 - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_K2_E5 (0x1<<6) // Controls Logging of Poisoned TLPs. - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_K2_E5_SHIFT 6 - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_K2_E5 (0x1<<7) // IDSEL Stepping. - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_K2_E5_SHIFT 7 - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_K2_E5 (0x1<<8) // Enables Error Reporting. - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_K2_E5_SHIFT 8 - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_K2_E5 (0x1<<10) // Controls generation of interrupts by a function. - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_K2_E5_SHIFT 10 - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_RESERV_K2_E5 (0x1f<<11) // Reserved. - #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_RESERV_K2_E5_SHIFT 11 - #define PCIEIP_REG_STATUS_COMMAND_REG_INT_STATUS_K2_E5 (0x1<<19) // Emulation interrupt pending. - #define PCIEIP_REG_STATUS_COMMAND_REG_INT_STATUS_K2_E5_SHIFT 19 - #define PCIEIP_REG_STATUS_COMMAND_REG_CAP_LIST_K2_E5 (0x1<<20) // Extended Capability. - #define PCIEIP_REG_STATUS_COMMAND_REG_CAP_LIST_K2_E5_SHIFT 20 - #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_66MHZ_CAP_K2_E5 (0x1<<21) // PCI 66MHz Capability. - #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_66MHZ_CAP_K2_E5_SHIFT 21 - #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_B2B_CAP_K2_E5 (0x1<<23) // Fast Back to Back Transaction Capable and Enable. - #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_B2B_CAP_K2_E5_SHIFT 23 - #define PCIEIP_REG_STATUS_COMMAND_REG_MASTER_DPE_K2_E5 (0x1<<24) // Controls poisoned Completion and Request error reporting. - #define PCIEIP_REG_STATUS_COMMAND_REG_MASTER_DPE_K2_E5_SHIFT 24 - #define PCIEIP_REG_STATUS_COMMAND_REG_DEV_SEL_TIMING_K2_E5 (0x3<<25) // Device Select Timing. - #define PCIEIP_REG_STATUS_COMMAND_REG_DEV_SEL_TIMING_K2_E5_SHIFT 25 - #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_K2_E5 (0x1<<27) // Completer Abort Error. - #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_K2_E5_SHIFT 27 - #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_K2_E5 (0x1<<28) // Completer Abort received. - #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_K2_E5_SHIFT 28 - #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_K2_E5 (0x1<<29) // Unsupported request completion status received. - #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_K2_E5_SHIFT 29 - #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_K2_E5 (0x1<<30) // Fatal or Non-Fatal Error Message sent by function. - #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_K2_E5_SHIFT 30 - #define PCIEIP_REG_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_K2_E5 (0x1<<31) // Poisoned TLP received by function. - #define PCIEIP_REG_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_K2_E5_SHIFT 31 +#define PCIEIP_REG_PCIEEP_CMD_E5 0x000004UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_CMD_ISAE_E5 (0x1<<0) // I/O space access enable. There are no I/O BARs supported. + #define PCIEIP_REG_PCIEEP_CMD_ISAE_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_CMD_MSAE_E5 (0x1<<1) // Memory space access enable. + #define PCIEIP_REG_PCIEEP_CMD_MSAE_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_CMD_ME_E5 (0x1<<2) // Bus master enable. If the PF or any of its VFs try to master the bus when this bit is not set, the request is discarded. An interrupt will be generated setting PEM()_DBG_INFO[BMD_E]. Transactions are dropped in the client. Nonposted transactions returns a fault response to SLI/DPI soon thereafter. Bus master enable mimics the behavior of PEM()_FLR_PF()_STOPREQ. + #define PCIEIP_REG_PCIEEP_CMD_ME_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_CMD_SCSE_E5 (0x1<<3) // Special cycle enable. Not applicable for PCI Express. Must be hardwired to zero. + #define PCIEIP_REG_PCIEEP_CMD_SCSE_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_CMD_MWICE_E5 (0x1<<4) // Memory write and invalidate. Not applicable for PCI Express. Must be hardwired to zero. + #define PCIEIP_REG_PCIEEP_CMD_MWICE_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_CMD_VPS_E5 (0x1<<5) // VGA palette snoop. Not applicable for PCI Express. Must be hardwired to zero. + #define PCIEIP_REG_PCIEEP_CMD_VPS_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_CMD_PER_E5 (0x1<<6) // Parity error response. + #define PCIEIP_REG_PCIEEP_CMD_PER_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_CMD_IDS_WCC_E5 (0x1<<7) // IDSEL stepping/wait cycle control. Not applicable for PCI Express. Must be hardwired to zero. + #define PCIEIP_REG_PCIEEP_CMD_IDS_WCC_E5_SHIFT 7 + #define PCIEIP_REG_PCIEEP_CMD_SEE_E5 (0x1<<8) // SERR# enable. + #define PCIEIP_REG_PCIEEP_CMD_SEE_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_CMD_FBBE_E5 (0x1<<9) // Fast back-to-back transaction enable. Not applicable for PCI Express. Must be hardwired to zero. + #define PCIEIP_REG_PCIEEP_CMD_FBBE_E5_SHIFT 9 + #define PCIEIP_REG_PCIEEP_CMD_I_DIS_E5 (0x1<<10) // INTx assertion disable. + #define PCIEIP_REG_PCIEEP_CMD_I_DIS_E5_SHIFT 10 + #define PCIEIP_REG_PCIEEP_CMD_IMM_READINESS_E5 (0x1<<16) // Reserved. + #define PCIEIP_REG_PCIEEP_CMD_IMM_READINESS_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_CMD_I_STAT_E5 (0x1<<19) // INTx status. + #define PCIEIP_REG_PCIEEP_CMD_I_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_CMD_CL_E5 (0x1<<20) // Capabilities list. Indicates presence of an extended capability item. Hardwired to one. + #define PCIEIP_REG_PCIEEP_CMD_CL_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_CMD_M66_E5 (0x1<<21) // 66 MHz capable. Not applicable for PCI Express. Hardwired to zero. + #define PCIEIP_REG_PCIEEP_CMD_M66_E5_SHIFT 21 + #define PCIEIP_REG_PCIEEP_CMD_FBB_E5 (0x1<<23) // Fast back-to-back capable. Not applicable for PCI Express. Hardwired to zero. + #define PCIEIP_REG_PCIEEP_CMD_FBB_E5_SHIFT 23 + #define PCIEIP_REG_PCIEEP_CMD_MDPE_E5 (0x1<<24) // Master data parity error. + #define PCIEIP_REG_PCIEEP_CMD_MDPE_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_CMD_DEVT_E5 (0x3<<25) // DEVSEL timing. Not applicable for PCI Express. Hardwired to 0x0. + #define PCIEIP_REG_PCIEEP_CMD_DEVT_E5_SHIFT 25 + #define PCIEIP_REG_PCIEEP_CMD_STA_E5 (0x1<<27) // Signaled target abort. + #define PCIEIP_REG_PCIEEP_CMD_STA_E5_SHIFT 27 + #define PCIEIP_REG_PCIEEP_CMD_RTA_E5 (0x1<<28) // Received target abort. + #define PCIEIP_REG_PCIEEP_CMD_RTA_E5_SHIFT 28 + #define PCIEIP_REG_PCIEEP_CMD_RMA_E5 (0x1<<29) // Received master abort. + #define PCIEIP_REG_PCIEEP_CMD_RMA_E5_SHIFT 29 + #define PCIEIP_REG_PCIEEP_CMD_SSE_E5 (0x1<<30) // Signaled system error. + #define PCIEIP_REG_PCIEEP_CMD_SSE_E5_SHIFT 30 + #define PCIEIP_REG_PCIEEP_CMD_DPE_E5 (0x1<<31) // Detected parity error. + #define PCIEIP_REG_PCIEEP_CMD_DPE_E5_SHIFT 31 +#define PCIEIP_REG_STATUS_COMMAND_REG_K2 0x000004UL //Access:RW DataWidth:0x20 // Command and Status Register. + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_K2 (0x1<<0) // Enables IO Access Response. You cannot write to this register if your configuration has no IO bars; that is, the internal signal has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_K2_SHIFT 0 + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_K2 (0x1<<1) // Enables Memory Access Response. You cannot write to this register if your configuration has no MEM bars; that is, the internal signal has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_K2_SHIFT 1 + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_K2 (0x1<<2) // Bus Master Enable. Controls Issuing of Memory and I/O Requests. + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_K2_SHIFT 2 + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_K2 (0x1<<3) // Special Cycle Enable. + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_K2_SHIFT 3 + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_K2 (0x1<<4) // Memory Write and Invalidate. + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_K2_SHIFT 4 + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_K2 (0x1<<5) // VGA Palette Snoop. + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_K2_SHIFT 5 + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_K2 (0x1<<6) // Controls Logging of Poisoned TLPs. + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_K2_SHIFT 6 + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_K2 (0x1<<7) // IDSEL Stepping. + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_K2_SHIFT 7 + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_K2 (0x1<<8) // Enables Error Reporting. + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_K2_SHIFT 8 + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_K2 (0x1<<10) // Controls generation of interrupts by a function. + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_K2_SHIFT 10 + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_RESERV_K2 (0x1f<<11) // Reserved. + #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_RESERV_K2_SHIFT 11 + #define PCIEIP_REG_STATUS_COMMAND_REG_INT_STATUS_K2 (0x1<<19) // Emulation interrupt pending. + #define PCIEIP_REG_STATUS_COMMAND_REG_INT_STATUS_K2_SHIFT 19 + #define PCIEIP_REG_STATUS_COMMAND_REG_CAP_LIST_K2 (0x1<<20) // Extended Capability. + #define PCIEIP_REG_STATUS_COMMAND_REG_CAP_LIST_K2_SHIFT 20 + #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_66MHZ_CAP_K2 (0x1<<21) // PCI 66MHz Capability. + #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_66MHZ_CAP_K2_SHIFT 21 + #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_B2B_CAP_K2 (0x1<<23) // Fast Back to Back Transaction Capable and Enable. + #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_B2B_CAP_K2_SHIFT 23 + #define PCIEIP_REG_STATUS_COMMAND_REG_MASTER_DPE_K2 (0x1<<24) // Controls poisoned Completion and Request error reporting. + #define PCIEIP_REG_STATUS_COMMAND_REG_MASTER_DPE_K2_SHIFT 24 + #define PCIEIP_REG_STATUS_COMMAND_REG_DEV_SEL_TIMING_K2 (0x3<<25) // Device Select Timing. + #define PCIEIP_REG_STATUS_COMMAND_REG_DEV_SEL_TIMING_K2_SHIFT 25 + #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_K2 (0x1<<27) // Completer Abort Error. + #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_K2_SHIFT 27 + #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_K2 (0x1<<28) // Completer Abort received. + #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_K2_SHIFT 28 + #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_K2 (0x1<<29) // Unsupported request completion status received. + #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_K2_SHIFT 29 + #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_K2 (0x1<<30) // Fatal or Non-Fatal Error Message sent by function. + #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_K2_SHIFT 30 + #define PCIEIP_REG_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_K2 (0x1<<31) // Poisoned TLP received by function. + #define PCIEIP_REG_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_K2_SHIFT 31 #define PCIEIP_REG_STATUS_COMMAND_BB 0x000004UL //Access:RW DataWidth:0x20 // This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command) #define PCIEIP_REG_STATUS_COMMAND_IO_SPACE_BB (0x1<<0) // This bit indicates that the device does not support I/O space access because it is zero and can not be modified. IO transactions targeting this device return completion with UR status . Path = i_cfg_func.i_cfg_public.i_cfg_dec #define PCIEIP_REG_STATUS_COMMAND_IO_SPACE_BB_SHIFT 0 @@ -187,31 +239,51 @@ #define PCIEIP_REG_STATUS_COMMAND_PRI_SIG_SERR_BB_SHIFT 30 #define PCIEIP_REG_STATUS_COMMAND_PRI_PAR_ERR_BB (0x1<<31) // When this bit is set, it indicates that the function has received a poisoned TLP Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg #define PCIEIP_REG_STATUS_COMMAND_PRI_PAR_ERR_BB_SHIFT 31 -#define PCIEIP_REG_CLASS_CODE_REVISION_ID_K2_E5 0x000008UL //Access:RW DataWidth:0x20 // Class Code and Revision ID Register. - #define PCIEIP_REG_CLASS_CODE_REVISION_ID_REVISION_ID_K2_E5 (0xff<<0) // Vendor chosen Revision ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_CLASS_CODE_REVISION_ID_REVISION_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_K2_E5 (0xff<<8) // Class Code Programming Interface. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_K2_E5_SHIFT 8 - #define PCIEIP_REG_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_K2_E5 (0xff<<16) // Subclass Code to represent Device Type. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_K2_E5_SHIFT 16 - #define PCIEIP_REG_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_K2_E5 (0xff<<24) // Base Class Code to represent Device Type. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_K2_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_REV_E5 0x000008UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_REV_RID_E5 (0xff<<0) // Revision ID, writable through PEM()_CFG_WR. However, the application must not change this field. See FUS_FUSE_NUM_E::CHIP_ID() for more information. + #define PCIEIP_REG_PCIEEP_REV_RID_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_REV_PI_E5 (0xff<<8) // Programming interface, writable through PEM()_CFG_WR. 0x0 = No standard interface. + #define PCIEIP_REG_PCIEEP_REV_PI_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_REV_SC_E5 (0xff<<16) // Subclass code, writable through PEM()_CFG_WR. 0x80 = Other processors (no encoding exists for ARM.) + #define PCIEIP_REG_PCIEEP_REV_SC_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_REV_BCC_E5 (0xff<<24) // Base class code, writable through PEM()_CFG_WR. 0xB = Processor. + #define PCIEIP_REG_PCIEEP_REV_BCC_E5_SHIFT 24 +#define PCIEIP_REG_CLASS_CODE_REVISION_ID_K2 0x000008UL //Access:RW DataWidth:0x20 // Class Code and Revision ID Register. + #define PCIEIP_REG_CLASS_CODE_REVISION_ID_REVISION_ID_K2 (0xff<<0) // Vendor chosen Revision ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_CLASS_CODE_REVISION_ID_REVISION_ID_K2_SHIFT 0 + #define PCIEIP_REG_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_K2 (0xff<<8) // Class Code Programming Interface. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_K2_SHIFT 8 + #define PCIEIP_REG_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_K2 (0xff<<16) // Subclass Code to represent Device Type. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_K2_SHIFT 16 + #define PCIEIP_REG_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_K2 (0xff<<24) // Base Class Code to represent Device Type. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_K2_SHIFT 24 #define PCIEIP_REG_REV_ID_CLASS_CODE_BB 0x000008UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_REV_ID_CLASS_CODE_REV_ID_BB (0xff<<0) // This register identifies the revision of the PCI adapter. This value is written by firmware through the PCI register space REVISION_ID value to modify the read value to the host. The default value is provided by user_revision_id strap pins. #define PCIEIP_REG_REV_ID_CLASS_CODE_REV_ID_BB_SHIFT 0 #define PCIEIP_REG_REV_ID_CLASS_CODE_CLASS_CODE_BB (0xffffff<<8) // The 24-bit Class Code register identifies the generic function of the device. All of the legal values are specified in the PCI specification. This read value is controlled by the CLASS_CODE valid value in the PCI register space. The default value reflects the value of CLASS_CODE in version.v defined by user. Path = i_cfg_func.i_cfg_private #define PCIEIP_REG_REV_ID_CLASS_CODE_CLASS_CODE_BB_SHIFT 8 -#define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_K2_E5 0x00000cUL //Access:RW DataWidth:0x20 // BIST, Header Type, Cache Line Size, and Latency Timer Registers. - #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_K2_E5 (0xff<<0) // Cache Line Size. Has no effect on PCIe device behavior. - #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_K2_E5_SHIFT 0 - #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2_E5 (0xff<<8) // Does not apply to PCI Express. - #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2_E5_SHIFT 8 - #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_K2_E5 (0x7f<<16) // Specifies Header Type. - #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_K2_E5_SHIFT 16 - #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_K2_E5 (0x1<<23) // Specifies whether device is multifunction. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_K2_E5_SHIFT 23 - #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_K2_E5 (0xff<<24) // Optional for BIST support. - #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_K2_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_CLSIZE_E5 0x00000cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_CLSIZE_CLS_E5 (0xff<<0) // Cache line size. The cache line size register is R/W for legacy compatibility purposes and is not applicable to PCI Express device functionality. Writing to the cache line size register does not impact functionality of the PCI Express bus. + #define PCIEIP_REG_PCIEEP_CLSIZE_CLS_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_CLSIZE_LT_E5 (0xff<<8) // Master latency timer. Not applicable for PCI Express, hardwired to 0x0. + #define PCIEIP_REG_PCIEEP_CLSIZE_LT_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_CLSIZE_CHF_E5 (0x7f<<16) // Configuration header format. Hardwired to 0x0 for type 0. + #define PCIEIP_REG_PCIEEP_CLSIZE_CHF_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_CLSIZE_MFD_E5 (0x1<<23) // Multi function device. The multi function device bit is writable through PEM()_CFG_WR. The application must not write a zero to this bit. + #define PCIEIP_REG_PCIEEP_CLSIZE_MFD_E5_SHIFT 23 + #define PCIEIP_REG_PCIEEP_CLSIZE_BIST_E5 (0xff<<24) // The BIST register functions are not supported. All 8 bits of the BIST register are hardwired to zero. + #define PCIEIP_REG_PCIEEP_CLSIZE_BIST_E5_SHIFT 24 +#define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_K2 0x00000cUL //Access:RW DataWidth:0x20 // BIST, Header Type, Cache Line Size, and Latency Timer Registers. + #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_K2 (0xff<<0) // Cache Line Size. Has no effect on PCIe device behavior. + #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_K2_SHIFT 0 + #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2 (0xff<<8) // Does not apply to PCI Express. + #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2_SHIFT 8 + #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_K2 (0x7f<<16) // Specifies Header Type. + #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_K2_SHIFT 16 + #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_K2 (0x1<<23) // Specifies whether device is multifunction. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_K2_SHIFT 23 + #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_K2 (0xff<<24) // Optional for BIST support. + #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_K2_SHIFT 24 #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_BB 0x00000cUL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_BB (0xff<<0) // This field is implemented by PCIE device as a read/write field for legacy compatibility purposes. Path = i_cfg_func.i_cfg_public.i_cfg_dec #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_BB_SHIFT 0 @@ -221,15 +293,24 @@ #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_BB_SHIFT 16 #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_BIST_BB (0xff<<24) // The 8-bit BIST register is used to initiate and report the results of any Built-In-Self-Test. This value can be written by firmware through the PCI register space BIST register to modify the read value to the host. Path = i_cfg_func.i_cfg_public.i_cfg_dec #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_BIST_BB_SHIFT 24 -#define PCIEIP_REG_BAR0_REG_K2_E5 0x000010UL //Access:RW DataWidth:0x20 // BAR0 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_REG_BAR0_REG_BAR0_MEM_IO_K2_E5 (0x1<<0) // BAR0 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR0_REG_BAR0_MEM_IO_K2_E5_SHIFT 0 - #define PCIEIP_REG_BAR0_REG_BAR0_TYPE_K2_E5 (0x3<<1) // BAR0 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR0_REG_BAR0_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_REG_BAR0_REG_BAR0_PREFETCH_K2_E5 (0x1<<3) // BAR0 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR0_REG_BAR0_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_REG_BAR0_REG_BAR0_START_K2_E5 (0xfffffff<<4) // BAR0 Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled else R - #define PCIEIP_REG_BAR0_REG_BAR0_START_K2_E5_SHIFT 4 +#define PCIEIP_REG_PCIEEP_BAR0L_E5 0x000010UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_BAR0L_MSPC_E5 (0x1<<0) // Memory space indicator. 0 = BAR 0 is a memory BAR. 1 = BAR 0 is an I/O BAR. This field is writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_BAR0L_MSPC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_BAR0L_TYP_E5 (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. This field is writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_BAR0L_TYP_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_BAR0L_PF_E5 (0x1<<3) // Prefetchable. This field is writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_BAR0L_PF_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_BAR0L_LBAB_E5 (0xffff<<16) // Lower bits of the BAR 0 base address. + #define PCIEIP_REG_PCIEEP_BAR0L_LBAB_E5_SHIFT 16 +#define PCIEIP_REG_BAR0_REG_K2 0x000010UL //Access:RW DataWidth:0x20 // BAR0 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_REG_BAR0_REG_BAR0_MEM_IO_K2 (0x1<<0) // BAR0 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR0_REG_BAR0_MEM_IO_K2_SHIFT 0 + #define PCIEIP_REG_BAR0_REG_BAR0_TYPE_K2 (0x3<<1) // BAR0 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR0_REG_BAR0_TYPE_K2_SHIFT 1 + #define PCIEIP_REG_BAR0_REG_BAR0_PREFETCH_K2 (0x1<<3) // BAR0 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR0_REG_BAR0_PREFETCH_K2_SHIFT 3 + #define PCIEIP_REG_BAR0_REG_BAR0_START_K2 (0xfffffff<<4) // BAR0 Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled else R + #define PCIEIP_REG_BAR0_REG_BAR0_START_K2_SHIFT 4 #define PCIEIP_REG_BAR_1_BB 0x000010UL //Access:RW DataWidth:0x20 // The 32-bit BAR_1 register programs the base address for the memory space mapped by the card onto the PCI bus. This register can be combined with BAR_2 to make a 64-bit address for supporting Dual Address cycles systems. Path = i_cfg_func.i_cfg_public.i_cfg_dec #define PCIEIP_REG_BAR_1_MEM_SPACE_BB (0x1<<0) // This bit indicates that BAR_1 maps a memory space and is always read as 0. Path = i_cfg_func.i_cfg_private #define PCIEIP_REG_BAR_1_MEM_SPACE_BB_SHIFT 0 @@ -239,25 +320,35 @@ #define PCIEIP_REG_BAR_1_PREFETCH_BB_SHIFT 3 #define PCIEIP_REG_BAR_1_ADDRESS_BB (0xfffffff<<4) // These bits set the address within a 32-bit address space that will be card will respond in. These bits may be combined with the bits in BAR_2 to create a full 64 bit address decode. Only the bits that address blocks bigger than the setting in the BAR1_SIZE value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_BAR_1_ADDRESS_BB_SHIFT 4 -#define PCIEIP_REG_BAR1_REG_K2_E5 0x000014UL //Access:RW DataWidth:0x20 // BAR1 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_REG_BAR1_REG_BAR1_MEM_IO_K2_E5 (0x1<<0) // BAR1 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR1_REG_BAR1_MEM_IO_K2_E5_SHIFT 0 - #define PCIEIP_REG_BAR1_REG_BAR1_TYPE_K2_E5 (0x3<<1) // BAR1 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR1_REG_BAR1_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_REG_BAR1_REG_BAR1_PREFETCH_K2_E5 (0x1<<3) // BAR1 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR1_REG_BAR1_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_REG_BAR1_REG_BAR1_START_K2_E5 (0xfffffff<<4) // BAR1 Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled else R - #define PCIEIP_REG_BAR1_REG_BAR1_START_K2_E5_SHIFT 4 +#define PCIEIP_REG_PCIEEP_BAR0U_E5 0x000014UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_BAR1_REG_K2 0x000014UL //Access:RW DataWidth:0x20 // BAR1 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_REG_BAR1_REG_BAR1_MEM_IO_K2 (0x1<<0) // BAR1 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR1_REG_BAR1_MEM_IO_K2_SHIFT 0 + #define PCIEIP_REG_BAR1_REG_BAR1_TYPE_K2 (0x3<<1) // BAR1 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR1_REG_BAR1_TYPE_K2_SHIFT 1 + #define PCIEIP_REG_BAR1_REG_BAR1_PREFETCH_K2 (0x1<<3) // BAR1 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR1_REG_BAR1_PREFETCH_K2_SHIFT 3 + #define PCIEIP_REG_BAR1_REG_BAR1_START_K2 (0xfffffff<<4) // BAR1 Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled else R + #define PCIEIP_REG_BAR1_REG_BAR1_START_K2_SHIFT 4 #define PCIEIP_REG_BAR_2_BB 0x000014UL //Access:RW DataWidth:0x20 // The 32-bit BAR_2 register programs the upper half of the base address for the memory space mapped by the card onto the PCI bus. Path = i_cfg_func.i_cfg_public.i_cfg_dec -#define PCIEIP_REG_BAR2_REG_K2_E5 0x000018UL //Access:RW DataWidth:0x20 // BAR2 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_REG_BAR2_REG_BAR2_MEM_IO_K2_E5 (0x1<<0) // BAR2 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR2_REG_BAR2_MEM_IO_K2_E5_SHIFT 0 - #define PCIEIP_REG_BAR2_REG_BAR2_TYPE_K2_E5 (0x3<<1) // BAR2 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR2_REG_BAR2_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_REG_BAR2_REG_BAR2_PREFETCH_K2_E5 (0x1<<3) // BAR2 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR2_REG_BAR2_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_REG_BAR2_REG_BAR2_START_K2_E5 (0xfffffff<<4) // BAR2 Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled else R - #define PCIEIP_REG_BAR2_REG_BAR2_START_K2_E5_SHIFT 4 +#define PCIEIP_REG_PCIEEP_BAR2L_E5 0x000018UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_BAR2L_MSPC_E5 (0x1<<0) // Memory space indicator. 0 = BAR 1 is a memory BAR. 1 = BAR 1 is an I/O BAR. This field is writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_BAR2L_MSPC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_BAR2L_TYP_E5 (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. This field is writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_BAR2L_TYP_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_BAR2L_PF_E5 (0x1<<3) // Prefetchable. This field is writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_BAR2L_PF_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_BAR2L_LBAB_E5 (0xfff<<20) // Lower bits of the BAR 2 base address. + #define PCIEIP_REG_PCIEEP_BAR2L_LBAB_E5_SHIFT 20 +#define PCIEIP_REG_BAR2_REG_K2 0x000018UL //Access:RW DataWidth:0x20 // BAR2 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_REG_BAR2_REG_BAR2_MEM_IO_K2 (0x1<<0) // BAR2 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR2_REG_BAR2_MEM_IO_K2_SHIFT 0 + #define PCIEIP_REG_BAR2_REG_BAR2_TYPE_K2 (0x3<<1) // BAR2 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR2_REG_BAR2_TYPE_K2_SHIFT 1 + #define PCIEIP_REG_BAR2_REG_BAR2_PREFETCH_K2 (0x1<<3) // BAR2 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR2_REG_BAR2_PREFETCH_K2_SHIFT 3 + #define PCIEIP_REG_BAR2_REG_BAR2_START_K2 (0xfffffff<<4) // BAR2 Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled else R + #define PCIEIP_REG_BAR2_REG_BAR2_START_K2_SHIFT 4 #define PCIEIP_REG_BAR_3_BB 0x000018UL //Access:RW DataWidth:0x20 // The 32-bit BAR_3 register programs the 2nd base address for the memory space mapped by the card onto the PCI bus. This register can be combined with BAR_4 to make a 64-bit address for supporting Dual Address cycles systems. #define PCIEIP_REG_BAR_3_MEM_SPACE_BB (0x1<<0) // This bit indicates that BAR_2 maps a memory space and is always read as 0. Path = i_cfg_func.i_cfg_private #define PCIEIP_REG_BAR_3_MEM_SPACE_BB_SHIFT 0 @@ -267,25 +358,35 @@ #define PCIEIP_REG_BAR_3_PREFETCH_BB_SHIFT 3 #define PCIEIP_REG_BAR_3_ADDRESS_BB (0xfffffff<<4) // These bits set the address within a 32-bit address space that will be card will respond in. These bits may be combined with the bits in BAR_4 to create a full 64 bit address decode. Only the bits that address blocks bigger than the setting in the BAR2_SIZE value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_BAR_3_ADDRESS_BB_SHIFT 4 -#define PCIEIP_REG_BAR3_REG_K2_E5 0x00001cUL //Access:RW DataWidth:0x20 // BAR3 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_REG_BAR3_REG_BAR3_MEM_IO_K2_E5 (0x1<<0) // BAR3 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR3_REG_BAR3_MEM_IO_K2_E5_SHIFT 0 - #define PCIEIP_REG_BAR3_REG_BAR3_TYPE_K2_E5 (0x3<<1) // BAR3 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR3_REG_BAR3_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_REG_BAR3_REG_BAR3_PREFETCH_K2_E5 (0x1<<3) // BAR3 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR3_REG_BAR3_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_REG_BAR3_REG_BAR3_START_K2_E5 (0xfffffff<<4) // BAR3 Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled else R - #define PCIEIP_REG_BAR3_REG_BAR3_START_K2_E5_SHIFT 4 +#define PCIEIP_REG_PCIEEP_BAR2U_E5 0x00001cUL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_BAR3_REG_K2 0x00001cUL //Access:RW DataWidth:0x20 // BAR3 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_REG_BAR3_REG_BAR3_MEM_IO_K2 (0x1<<0) // BAR3 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR3_REG_BAR3_MEM_IO_K2_SHIFT 0 + #define PCIEIP_REG_BAR3_REG_BAR3_TYPE_K2 (0x3<<1) // BAR3 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR3_REG_BAR3_TYPE_K2_SHIFT 1 + #define PCIEIP_REG_BAR3_REG_BAR3_PREFETCH_K2 (0x1<<3) // BAR3 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR3_REG_BAR3_PREFETCH_K2_SHIFT 3 + #define PCIEIP_REG_BAR3_REG_BAR3_START_K2 (0xfffffff<<4) // BAR3 Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled else R + #define PCIEIP_REG_BAR3_REG_BAR3_START_K2_SHIFT 4 #define PCIEIP_REG_BAR_4_BB 0x00001cUL //Access:RW DataWidth:0x20 // The 32-bit BAR_4 register programs the upper half of the 2nd base address for the memory space mapped by the card onto the PCI bus. Path = i_cfg_func.i_cfg_public.i_cfg_dec -#define PCIEIP_REG_BAR4_REG_K2_E5 0x000020UL //Access:RW DataWidth:0x20 // BAR4 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_REG_BAR4_REG_BAR4_MEM_IO_K2_E5 (0x1<<0) // BAR4 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR4_REG_BAR4_MEM_IO_K2_E5_SHIFT 0 - #define PCIEIP_REG_BAR4_REG_BAR4_TYPE_K2_E5 (0x3<<1) // BAR4 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR4_REG_BAR4_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_REG_BAR4_REG_BAR4_PREFETCH_K2_E5 (0x1<<3) // BAR4 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR4_REG_BAR4_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_REG_BAR4_REG_BAR4_START_K2_E5 (0xfffffff<<4) // BAR4 Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled else R - #define PCIEIP_REG_BAR4_REG_BAR4_START_K2_E5_SHIFT 4 +#define PCIEIP_REG_PCIEEP_BAR4L_E5 0x000020UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_BAR4L_MSPC_E5 (0x1<<0) // Memory space indicator. 0 = BAR 2 is a memory BAR. 1 = BAR 2 is an I/O BAR. This field is writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_BAR4L_MSPC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_BAR4L_TYP_E5 (0x3<<1) // BAR type. 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. This field is writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_BAR4L_TYP_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_BAR4L_PF_E5 (0x1<<3) // Prefetchable. This field is writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_BAR4L_PF_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_BAR4L_LBAB_E5 (0xffff<<16) // Lower bits of the BAR 4 base address. + #define PCIEIP_REG_PCIEEP_BAR4L_LBAB_E5_SHIFT 16 +#define PCIEIP_REG_BAR4_REG_K2 0x000020UL //Access:RW DataWidth:0x20 // BAR4 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_REG_BAR4_REG_BAR4_MEM_IO_K2 (0x1<<0) // BAR4 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR4_REG_BAR4_MEM_IO_K2_SHIFT 0 + #define PCIEIP_REG_BAR4_REG_BAR4_TYPE_K2 (0x3<<1) // BAR4 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR4_REG_BAR4_TYPE_K2_SHIFT 1 + #define PCIEIP_REG_BAR4_REG_BAR4_PREFETCH_K2 (0x1<<3) // BAR4 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR4_REG_BAR4_PREFETCH_K2_SHIFT 3 + #define PCIEIP_REG_BAR4_REG_BAR4_START_K2 (0xfffffff<<4) // BAR4 Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled else R + #define PCIEIP_REG_BAR4_REG_BAR4_START_K2_SHIFT 4 #define PCIEIP_REG_BAR_5_BB 0x000020UL //Access:RW DataWidth:0x20 // The 32-bit BAR_5 register programs the 3rd base address for the memory space mapped by the card onto the PCI bus. This register can be combined with BAR_4 to make a 64-bit address for supporting Dual Address cycles systems. Path = i_cfg_func.i_cfg_public.i_cfg_dec #define PCIEIP_REG_BAR_5_MEM_SPACE_BB (0x1<<0) // This bit indicates that BAR_3 maps a memory space and is always read as 0. Path = i_cfg_func.i_cfg_private #define PCIEIP_REG_BAR_5_MEM_SPACE_BB_SHIFT 0 @@ -295,33 +396,45 @@ #define PCIEIP_REG_BAR_5_PREFETCH_BB_SHIFT 3 #define PCIEIP_REG_BAR_5_ADDRESS_BB (0xfffffff<<4) // These bits set the address within a 32-bit address space that will be card will respond in. These bits may be combined with the bits in BAR_6 to create a full 64 bit address decode. Only the bits that address blocks bigger than the setting in the BAR3_SIZE value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_BAR_5_ADDRESS_BB_SHIFT 4 -#define PCIEIP_REG_BAR5_REG_K2_E5 0x000024UL //Access:RW DataWidth:0x20 // BAR5 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_REG_BAR5_REG_BAR5_MEM_IO_K2_E5 (0x1<<0) // BAR5 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR5_REG_BAR5_MEM_IO_K2_E5_SHIFT 0 - #define PCIEIP_REG_BAR5_REG_BAR5_TYPE_K2_E5 (0x3<<1) // BAR5 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR5_REG_BAR5_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_REG_BAR5_REG_BAR5_PREFETCH_K2_E5 (0x1<<3) // BAR5 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO - #define PCIEIP_REG_BAR5_REG_BAR5_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_REG_BAR5_REG_BAR5_START_K2_E5 (0xfffffff<<4) // BAR5 Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled else R - #define PCIEIP_REG_BAR5_REG_BAR5_START_K2_E5_SHIFT 4 +#define PCIEIP_REG_PCIEEP_BAR4U_E5 0x000024UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_BAR5_REG_K2 0x000024UL //Access:RW DataWidth:0x20 // BAR5 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_REG_BAR5_REG_BAR5_MEM_IO_K2 (0x1<<0) // BAR5 Memory Space Indicator. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR5_REG_BAR5_MEM_IO_K2_SHIFT 0 + #define PCIEIP_REG_BAR5_REG_BAR5_TYPE_K2 (0x3<<1) // BAR5 32-bit or 64-bit. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR5_REG_BAR5_TYPE_K2_SHIFT 1 + #define PCIEIP_REG_BAR5_REG_BAR5_PREFETCH_K2 (0x1<<3) // BAR5 Prefetchable. Note: The access attributes of this field are as follows: - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO + #define PCIEIP_REG_BAR5_REG_BAR5_PREFETCH_K2_SHIFT 3 + #define PCIEIP_REG_BAR5_REG_BAR5_START_K2 (0xfffffff<<4) // BAR5 Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W if enabled else R + #define PCIEIP_REG_BAR5_REG_BAR5_START_K2_SHIFT 4 #define PCIEIP_REG_BAR_6_BB 0x000024UL //Access:RW DataWidth:0x20 // The 32-bit BAR_4 register programs the upper half of the 3nd base address for the memory space mapped by the card onto the PCI bus. -#define PCIEIP_REG_CARDBUS_CIS_PTR_REG_K2_E5 0x000028UL //Access:RW DataWidth:0x20 // CardBus CIS Pointer Register. +#define PCIEIP_REG_PCIEEP_CARDBUS_E5 0x000028UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_CARDBUS_CIS_PTR_REG_K2 0x000028UL //Access:RW DataWidth:0x20 // CardBus CIS Pointer Register. #define PCIEIP_REG_CARDBUS_CIS_BB 0x000028UL //Access:R DataWidth:0x20 // This register is not supported. Path = i_cfg_func.i_cfg_public.i_cfg_rd_mux -#define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_K2_E5 0x00002cUL //Access:RW DataWidth:0x20 // Subsystem ID and Subsystem Vendor ID Register. - #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_K2_E5 (0xffff<<0) // Subsystem Vendor ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_K2_E5 (0xffff<<16) // Subsystem Device ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_K2_E5_SHIFT 16 +#define PCIEIP_REG_PCIEEP_SUBSYS_E5 0x00002cUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_SUBSYS_SSVID_E5 (0xffff<<0) // Subsystem vendor ID. Assigned by PCI-SIG, writable through PEM()_CFG_WR. + #define PCIEIP_REG_PCIEEP_SUBSYS_SSVID_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_SUBSYS_SSID_E5 (0xffff<<16) // Subsystem ID. Assigned by PCI-SIG, writable through PEM()_CFG_WR. + #define PCIEIP_REG_PCIEEP_SUBSYS_SSID_E5_SHIFT 16 +#define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_K2 0x00002cUL //Access:RW DataWidth:0x20 // Subsystem ID and Subsystem Vendor ID Register. + #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_K2 (0xffff<<0) // Subsystem Vendor ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_K2_SHIFT 0 + #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_K2 (0xffff<<16) // Subsystem Device ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_K2_SHIFT 16 #define PCIEIP_REG_SUBSYSTEM_ID_VENDOR_ID_BB 0x00002cUL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_SUBSYSTEM_ID_VENDOR_ID_SUBSYSTEM_VENDOR_ID_BB (0xffff<<0) // The 16-bit Subsystem Vendor ID register is used by the adapter manufacturer for identification. This value can be written by firmware through the PCI register space SUBSYSTEM_VENDOR_ID value to modify the read value to the host. Path = i_cfg_func.i_cfg_private #define PCIEIP_REG_SUBSYSTEM_ID_VENDOR_ID_SUBSYSTEM_VENDOR_ID_BB_SHIFT 0 #define PCIEIP_REG_SUBSYSTEM_ID_VENDOR_ID_SUBSYSTEM_ID_BB (0xffff<<16) // The 16-bit Subsystem ID register is used by the adapter manufacturer for identification. This value can be written by firmware through the PCI register space SUBSYSTEM_ID value to modify the read value to the host. Default values are the same as the DEVICE_ID register. Path = i_cfg_func.i_cfg_private #define PCIEIP_REG_SUBSYSTEM_ID_VENDOR_ID_SUBSYSTEM_ID_BB_SHIFT 16 -#define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_K2_E5 0x000030UL //Access:RW DataWidth:0x20 // Expansion ROM BAR and Mask Register. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_K2_E5 (0x1<<0) // Expansion ROM Enable. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_K2_E5_SHIFT 0 - #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_K2_E5 (0x1fffff<<11) // Expansion ROM Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_K2_E5_SHIFT 11 +#define PCIEIP_REG_PCIEEP_EBAR_E5 0x000030UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_EBAR_ER_EN_E5 (0x1<<0) // Expansion ROM enable. + #define PCIEIP_REG_PCIEEP_EBAR_ER_EN_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_EBAR_ERADDR_E5 (0xfffff<<12) // Expansion ROM address. + #define PCIEIP_REG_PCIEEP_EBAR_ERADDR_E5_SHIFT 12 +#define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_K2 0x000030UL //Access:RW DataWidth:0x20 // Expansion ROM BAR and Mask Register. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_K2 (0x1<<0) // Expansion ROM Enable. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_K2_SHIFT 0 + #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_K2 (0x1fffff<<11) // Expansion ROM Base Address. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_K2_SHIFT 11 #define PCIEIP_REG_EXP_ROM_BAR_BB 0x000030UL //Access:RW DataWidth:0x20 // The 32-bit Expansion ROM BAR register programs the base address for the memory space mapped by the chip for use as the expansion ROM. For more information on the operation of Expansion ROM, see the Theory of Ops specification. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg #define PCIEIP_REG_EXP_ROM_BAR_BAR_ENA_BB (0x1<<0) // This bit indicates that the Expansion ROM BAR is valid when set to one. If it is zero, the expansion BAR should not be programmed or used. This bit will only be RW if it is enabled by the EXP_ROM_ENA bit which defaults to 0. Path = i_cfg_func.i_cfg_private #define PCIEIP_REG_EXP_ROM_BAR_BAR_ENA_BB_SHIFT 0 @@ -331,17 +444,29 @@ #define PCIEIP_REG_EXP_ROM_BAR_SIZE_BB_SHIFT 11 #define PCIEIP_REG_EXP_ROM_BAR_ADDRESS_BB (0xff<<24) // These bits indicate the address of the Expansion ROM area. #define PCIEIP_REG_EXP_ROM_BAR_ADDRESS_BB_SHIFT 24 -#define PCIEIP_REG_PCI_CAP_PTR_REG_K2_E5 0x000034UL //Access:RW DataWidth:0x20 // Capability Pointer Register. - #define PCIEIP_REG_PCI_CAP_PTR_REG_CAP_POINTER_K2_E5 (0xff<<0) // Pointer to first item in the PCI Capability Structure. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_PCI_CAP_PTR_REG_CAP_POINTER_K2_E5_SHIFT 0 +#define PCIEIP_REG_PCIEEP_CAP_PTR_E5 0x000034UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_CAP_PTR_CP_E5 (0xff<<0) // First capability pointer. Points to power management capability structure by default, writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_CAP_PTR_CP_E5_SHIFT 0 +#define PCIEIP_REG_PCI_CAP_PTR_REG_K2 0x000034UL //Access:RW DataWidth:0x20 // Capability Pointer Register. + #define PCIEIP_REG_PCI_CAP_PTR_REG_CAP_POINTER_K2 (0xff<<0) // Pointer to first item in the PCI Capability Structure. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_PCI_CAP_PTR_REG_CAP_POINTER_K2_SHIFT 0 #define PCIEIP_REG_CAP_POINTER_BB 0x000034UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_CAP_POINTER_CAP_POINTER_BB (0xff<<0) // The 8-bit Capabilities Pointer register specifies an offset in the PCI address space of a linked list of new capabilities. The capabilities are PCI-X, PCI Power Management, Vital Product Data (VPD), and Message Signaled Interrupts (MSI) is supported. The read-only value of this register is controlled by the CAP_ENA register in the PCI register space. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg #define PCIEIP_REG_CAP_POINTER_CAP_POINTER_BB_SHIFT 0 -#define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_K2_E5 0x00003cUL //Access:RW DataWidth:0x20 // Interrupt Line and Pin Register. - #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_K2_E5 (0xff<<0) // PCI Compatible Interrupt Line Routing Register Field. - #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_K2_E5_SHIFT 0 - #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_K2_E5 (0xff<<8) // PCI Compatible Interrupt Pin Register Field. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_K2_E5_SHIFT 8 +#define PCIEIP_REG_PCIEEP_INT_E5 0x00003cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_INT_IL_E5 (0xff<<0) // Interrupt line. + #define PCIEIP_REG_PCIEEP_INT_IL_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_INT_INTA_E5 (0xff<<8) // Interrupt pin. Identifies the legacy interrupt message that the device (or device function) uses. The interrupt pin register is writable through PEM()_CFG_WR. + #define PCIEIP_REG_PCIEEP_INT_INTA_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_INT_MG_E5 (0xff<<16) // Minimum grant (hardwired to 0x0). + #define PCIEIP_REG_PCIEEP_INT_MG_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_INT_ML_E5 (0xff<<24) // Maximum latency (hardwired to 0x0). + #define PCIEIP_REG_PCIEEP_INT_ML_E5_SHIFT 24 +#define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_K2 0x00003cUL //Access:RW DataWidth:0x20 // Interrupt Line and Pin Register. + #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_K2 (0xff<<0) // PCI Compatible Interrupt Line Routing Register Field. + #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_K2_SHIFT 0 + #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_K2 (0xff<<8) // PCI Compatible Interrupt Pin Register Field. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_K2_SHIFT 8 #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_BB 0x00003cUL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_INT_LINE_BB (0xff<<0) // The 8-bit Interrupt Line register is used to communicate interrupt line routing information. This field is set by the host and later used by any driver which needs to know which physical interrupt on the system interrupt controller is assigned to this device. Path = i_cfg_func.i_cfg_private #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_INT_LINE_BB_SHIFT 0 @@ -351,46 +476,84 @@ #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_MIN_GRANT_BB_SHIFT 16 #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_MAXIMUM_LATENCY_BB (0xff<<24) // Hardwired to zero Path = i_cfg_func.i_cfg_public.i_cfg_rd_mux #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_MAXIMUM_LATENCY_BB_SHIFT 24 -#define PCIEIP_REG_CAP_ID_NXT_PTR_REG_K2_E5 0x000040UL //Access:RW DataWidth:0x20 // Power Management Capabilities Register. - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_CAP_ID_K2_E5 (0xff<<0) // Power Management Capability ID. - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_K2_E5 (0xff<<8) // Next Capability Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_K2_E5_SHIFT 8 - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_K2_E5 (0x7<<16) // Power Management Spec Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_K2_E5_SHIFT 16 - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_CLK_K2_E5 (0x1<<19) // PCI Clock Requirement. - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_CLK_K2_E5_SHIFT 19 - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_IMM_READI_RETURN_DO_K2_E5 (0x1<<20) // Immediate Readiness on Return to D0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_IMM_READI_RETURN_DO_K2_E5_SHIFT 20 - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_DSI_K2_E5 (0x1<<21) // Device Specific Initialization Bit. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_DSI_K2_E5_SHIFT 21 - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_AUX_CURR_K2_E5 (0x7<<22) // Auxiliary Current Requirements. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_AUX_CURR_K2_E5_SHIFT 22 - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D1_SUPPORT_K2_E5 (0x1<<25) // D1 State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D1_SUPPORT_K2_E5_SHIFT 25 - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D2_SUPPORT_K2_E5 (0x1<<26) // D2 State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D2_SUPPORT_K2_E5_SHIFT 26 - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_SUPPORT_K2_E5 (0x1f<<27) // Power Management Event Support. The read value from this field is the write value && {sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1}, where D1_SUPPORT and D2_SUPPORT are fields in this register. The reset value PME_SUPPORT_n && {sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1}, where PME_SUPPORT_n is a configuration parameter. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_SUPPORT_K2_E5_SHIFT 27 -#define PCIEIP_REG_CON_STATUS_REG_K2_E5 0x000044UL //Access:RW DataWidth:0x20 // Power Management Control and Status Register. - #define PCIEIP_REG_CON_STATUS_REG_POWER_STATE_K2_E5 (0x3<<0) // Power State. You can write to this register. However, the read-back value is the actual power state, not the write value. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_CON_STATUS_REG_POWER_STATE_K2_E5_SHIFT 0 - #define PCIEIP_REG_CON_STATUS_REG_NO_SOFT_RST_K2_E5 (0x1<<3) // No soft Reset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_CON_STATUS_REG_NO_SOFT_RST_K2_E5_SHIFT 3 - #define PCIEIP_REG_CON_STATUS_REG_PME_ENABLE_K2_E5 (0x1<<8) // PME Enable. The PMC registers this value under aux power. Sometimes it might remember the old value, even if you try to clear it by writing '0'. Note: This register field is sticky. - #define PCIEIP_REG_CON_STATUS_REG_PME_ENABLE_K2_E5_SHIFT 8 - #define PCIEIP_REG_CON_STATUS_REG_DATA_SELECT_K2_E5 (0xf<<9) // Data Select. - #define PCIEIP_REG_CON_STATUS_REG_DATA_SELECT_K2_E5_SHIFT 9 - #define PCIEIP_REG_CON_STATUS_REG_DATA_SCALE_K2_E5 (0x3<<13) // Data Scaling Factor. - #define PCIEIP_REG_CON_STATUS_REG_DATA_SCALE_K2_E5_SHIFT 13 - #define PCIEIP_REG_CON_STATUS_REG_PME_STATUS_K2_E5 (0x1<<15) // PME Status. - #define PCIEIP_REG_CON_STATUS_REG_PME_STATUS_K2_E5_SHIFT 15 - #define PCIEIP_REG_CON_STATUS_REG_B2_B3_SUPPORT_K2_E5 (0x1<<22) // B2B3 Support for D3hot. - #define PCIEIP_REG_CON_STATUS_REG_B2_B3_SUPPORT_K2_E5_SHIFT 22 - #define PCIEIP_REG_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_K2_E5 (0x1<<23) // Bus Power/Clock Control Enable. - #define PCIEIP_REG_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_K2_E5_SHIFT 23 - #define PCIEIP_REG_CON_STATUS_REG_DATA_REG_ADD_INFO_K2_E5 (0xff<<24) // Power Data Information Register. - #define PCIEIP_REG_CON_STATUS_REG_DATA_REG_ADD_INFO_K2_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_PM_CAP_ID_E5 0x000040UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_PMCID_E5 (0xff<<0) // Power management capability ID. + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_PMCID_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_NCP_E5 (0xff<<8) // Next capability pointer. Points to the PCIe capabilities list by default, writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_NCP_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_PMSV_E5 (0x7<<16) // Power management specification version, writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_PMSV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_PME_CLOCK_E5 (0x1<<19) // PME clock, hardwired to zero. + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_PME_CLOCK_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_DSI_E5 (0x1<<21) // Device specific initialization (DSI), writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_DSI_E5_SHIFT 21 + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_AUXC_E5 (0x7<<22) // AUX current, writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_AUXC_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_D1S_E5 (0x1<<25) // D1 support, writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_D1S_E5_SHIFT 25 + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_D2S_E5 (0x1<<26) // D2 support, writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_D2S_E5_SHIFT 26 + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_PMES_E5 (0x1f<<27) // PME_Support. A value of 0x0 for any bit indicates that the device (or function) is not capable of generating PME messages while in that power state: _ Bit 11: If set, PME Messages can be generated from D0. _ Bit 12: If set, PME Messages can be generated from D1. _ Bit 13: If set, PME Messages can be generated from D2. _ Bit 14: If set, PME Messages can be generated from D3hot. _ Bit 15: If set, PME Messages can be generated from D3cold. This field is writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PM_CAP_ID_PMES_E5_SHIFT 27 +#define PCIEIP_REG_CAP_ID_NXT_PTR_REG_K2 0x000040UL //Access:RW DataWidth:0x20 // Power Management Capabilities Register. + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_CAP_ID_K2 (0xff<<0) // Power Management Capability ID. + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_K2 (0xff<<8) // Next Capability Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_K2_SHIFT 8 + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_K2 (0x7<<16) // Power Management Spec Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_K2_SHIFT 16 + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_CLK_K2 (0x1<<19) // PCI Clock Requirement. + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_CLK_K2_SHIFT 19 + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_IMM_READI_RETURN_DO_K2 (0x1<<20) // Immediate Readiness on Return to D0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_IMM_READI_RETURN_DO_K2_SHIFT 20 + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_DSI_K2 (0x1<<21) // Device Specific Initialization Bit. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_DSI_K2_SHIFT 21 + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_AUX_CURR_K2 (0x7<<22) // Auxiliary Current Requirements. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_AUX_CURR_K2_SHIFT 22 + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D1_SUPPORT_K2 (0x1<<25) // D1 State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D1_SUPPORT_K2_SHIFT 25 + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D2_SUPPORT_K2 (0x1<<26) // D2 State Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D2_SUPPORT_K2_SHIFT 26 + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_SUPPORT_K2 (0x1f<<27) // Power Management Event Support. The read value from this field is the write value && {sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1}, where D1_SUPPORT and D2_SUPPORT are fields in this register. The reset value PME_SUPPORT_n && {sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1}, where PME_SUPPORT_n is a configuration parameter. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_SUPPORT_K2_SHIFT 27 +#define PCIEIP_REG_PCIEEP_PM_CTL_E5 0x000044UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PM_CTL_PS_E5 (0x3<<0) // Power state. Controls the device power state: 0x0 = D0. 0x1 = D1. 0x2 = D2. 0x3 = D3. The written value is ignored if the specific state is not supported. + #define PCIEIP_REG_PCIEEP_PM_CTL_PS_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PM_CTL_NSR_E5 (0x1<<3) // No soft reset, writable through PEM()_CFG_WR. + #define PCIEIP_REG_PCIEEP_PM_CTL_NSR_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_PM_CTL_PMEENS_E5 (0x1<<8) // PME enable. A value of one indicates that the device is enabled to generate PME. + #define PCIEIP_REG_PCIEEP_PM_CTL_PMEENS_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_PM_CTL_PMDS_E5 (0xf<<9) // Data select (not supported). + #define PCIEIP_REG_PCIEEP_PM_CTL_PMDS_E5_SHIFT 9 + #define PCIEIP_REG_PCIEEP_PM_CTL_PMEDSIA_E5 (0x3<<13) // Data scale (not supported). + #define PCIEIP_REG_PCIEEP_PM_CTL_PMEDSIA_E5_SHIFT 13 + #define PCIEIP_REG_PCIEEP_PM_CTL_PMESS_E5 (0x1<<15) // PME status. Indicates whether or not a previously enabled PME event occurred. + #define PCIEIP_REG_PCIEEP_PM_CTL_PMESS_E5_SHIFT 15 + #define PCIEIP_REG_PCIEEP_PM_CTL_BD3H_E5 (0x1<<22) // B2/B3 support, hardwired to zero. + #define PCIEIP_REG_PCIEEP_PM_CTL_BD3H_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_PM_CTL_BPCCEE_E5 (0x1<<23) // Bus power/clock control enable, hardwired to zero. + #define PCIEIP_REG_PCIEEP_PM_CTL_BPCCEE_E5_SHIFT 23 + #define PCIEIP_REG_PCIEEP_PM_CTL_PMDIA_E5 (0xff<<24) // Data register for additional information (not supported). + #define PCIEIP_REG_PCIEEP_PM_CTL_PMDIA_E5_SHIFT 24 +#define PCIEIP_REG_CON_STATUS_REG_K2 0x000044UL //Access:RW DataWidth:0x20 // Power Management Control and Status Register. + #define PCIEIP_REG_CON_STATUS_REG_POWER_STATE_K2 (0x3<<0) // Power State. You can write to this register. However, the read-back value is the actual power state, not the write value. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_CON_STATUS_REG_POWER_STATE_K2_SHIFT 0 + #define PCIEIP_REG_CON_STATUS_REG_NO_SOFT_RST_K2 (0x1<<3) // No soft Reset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_CON_STATUS_REG_NO_SOFT_RST_K2_SHIFT 3 + #define PCIEIP_REG_CON_STATUS_REG_PME_ENABLE_K2 (0x1<<8) // PME Enable. The PMC registers this value under aux power. Sometimes it might remember the old value, even if you try to clear it by writing '0'. Note: This register field is sticky. + #define PCIEIP_REG_CON_STATUS_REG_PME_ENABLE_K2_SHIFT 8 + #define PCIEIP_REG_CON_STATUS_REG_DATA_SELECT_K2 (0xf<<9) // Data Select. + #define PCIEIP_REG_CON_STATUS_REG_DATA_SELECT_K2_SHIFT 9 + #define PCIEIP_REG_CON_STATUS_REG_DATA_SCALE_K2 (0x3<<13) // Data Scaling Factor. + #define PCIEIP_REG_CON_STATUS_REG_DATA_SCALE_K2_SHIFT 13 + #define PCIEIP_REG_CON_STATUS_REG_PME_STATUS_K2 (0x1<<15) // PME Status. + #define PCIEIP_REG_CON_STATUS_REG_PME_STATUS_K2_SHIFT 15 + #define PCIEIP_REG_CON_STATUS_REG_B2_B3_SUPPORT_K2 (0x1<<22) // B2B3 Support for D3hot. + #define PCIEIP_REG_CON_STATUS_REG_B2_B3_SUPPORT_K2_SHIFT 22 + #define PCIEIP_REG_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_K2 (0x1<<23) // Bus Power/Clock Control Enable. + #define PCIEIP_REG_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_K2_SHIFT 23 + #define PCIEIP_REG_CON_STATUS_REG_DATA_REG_ADD_INFO_K2 (0xff<<24) // Power Data Information Register. + #define PCIEIP_REG_CON_STATUS_REG_DATA_REG_ADD_INFO_K2_SHIFT 24 #define PCIEIP_REG_PM_CAP_BB 0x000048UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_PM_CAP_PM_CAP_ID_BB (0xff<<0) // The 8-bit Power Management Capability ID is set to 1 to indicate that the next 8 bytes are a Power Management capability block. Hardwired to 1. Path = cfg_defs #define PCIEIP_REG_PM_CAP_PM_CAP_ID_BB_SHIFT 0 @@ -443,21 +606,21 @@ #define PCIEIP_REG_PM_CSR_PM_CSR_BSE_BB_SHIFT 16 #define PCIEIP_REG_PM_CSR_PM_DATA_BB (0xff<<24) // The value for this register is selected from one of eight values by the DATA_SEL bits of the PM_CSR register. The reset value of all 9 of the register values is zero. These values can be written by firmware through the PCI register space (PM_Data_0_prg to PM_Data_8_prg) to modify the read values to the host. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap (for pm_data_select) Path = i_cfg_func.i_cfg_private (pm_data) #define PCIEIP_REG_PM_CSR_PM_DATA_BB_SHIFT 24 -#define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_K2_E5 0x000050UL //Access:RW DataWidth:0x20 // MSI Capability ID, Next Pointer, Capability/Control Registers. - #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_K2_E5 (0xff<<0) // MSI Capability ID. - #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_K2_E5 (0xff<<8) // MSI Capability Next Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_K2_E5_SHIFT 8 - #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_K2_E5 (0x1<<16) // MSI Enable. - #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_K2_E5_SHIFT 16 - #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_K2_E5 (0x7<<17) // MSI Multiple Message Capable. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_K2_E5_SHIFT 17 - #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_K2_E5 (0x7<<20) // MSI Multiple Message Enable. - #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_K2_E5_SHIFT 20 - #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_K2_E5 (0x1<<23) // MSI 64-bit Address Capable. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_K2_E5_SHIFT 23 - #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_K2_E5 (0x1<<24) // MSI Per Vector Masking Capable. - #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_K2_E5_SHIFT 24 +#define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_K2 0x000050UL //Access:RW DataWidth:0x20 // MSI Capability ID, Next Pointer, Capability/Control Registers. + #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_K2 (0xff<<0) // MSI Capability ID. + #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_K2 (0xff<<8) // MSI Capability Next Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_K2_SHIFT 8 + #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_K2 (0x1<<16) // MSI Enable. + #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_K2_SHIFT 16 + #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_K2 (0x7<<17) // MSI Multiple Message Capable. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_K2_SHIFT 17 + #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_K2 (0x7<<20) // MSI Multiple Message Enable. + #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_K2_SHIFT 20 + #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_K2 (0x1<<23) // MSI 64-bit Address Capable. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_K2_SHIFT 23 + #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_K2 (0x1<<24) // MSI Per Vector Masking Capable. + #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_K2_SHIFT 24 #define PCIEIP_REG_VPD_CAP_BB 0x000050UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_VPD_CAP_VPD_CAP_ID_BB (0xff<<0) // The 8-bit VPD Capability ID is set to 3 to indicate that the next 8 bytes are a Vital Product Data capability block. Path = cfg_defs #define PCIEIP_REG_VPD_CAP_VPD_CAP_ID_BB_SHIFT 0 @@ -469,15 +632,15 @@ #define PCIEIP_REG_VPD_CAP_ADDRESS_BB_SHIFT 18 #define PCIEIP_REG_VPD_CAP_FLAG_BB (0x1<<31) // This bit is used to control passing of data between the vpd_data register and Non-Volatile memory. To read a value, this bit is written as zero when the address is written. When the data is available to read, this bit will read as a one. To write data, this bit must written as a one when the address is written. When the bit reads as a zero the write has completed. Path = i_cfg_func.i_cfg_public.i_cfg_vpd_cap #define PCIEIP_REG_VPD_CAP_FLAG_BB_SHIFT 31 -#define PCIEIP_REG_MSI_CAP_OFF_04H_REG_K2_E5 0x000054UL //Access:RW DataWidth:0x20 // MSI Message Lower Address Register. - #define PCIEIP_REG_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_K2_E5 (0x3fffffff<<2) // MSI Message Lower Address Field. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_K2_E5_SHIFT 2 +#define PCIEIP_REG_MSI_CAP_OFF_04H_REG_K2 0x000054UL //Access:RW DataWidth:0x20 // MSI Message Lower Address Register. + #define PCIEIP_REG_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_K2 (0x3fffffff<<2) // MSI Message Lower Address Field. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_K2_SHIFT 2 #define PCIEIP_REG_VPD_DATA_BB 0x000054UL //Access:RW DataWidth:0x20 // This is the VPD data transfer register. See the instructions for the FLAG bit above for usage of this register. Path = i_cfg_func.i_cfg_public.i_cfg_vpd_cap -#define PCIEIP_REG_MSI_CAP_OFF_08H_REG_K2_E5 0x000058UL //Access:RW DataWidth:0x20 // For a 32 bit MSI Message, this register contains Data. For 64 bit it contains the Upper Address. - #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_K2_E5 (0xffff<<0) // For a 32-bit MSI Message, this field contains Data. For 64-bit it contains lower 16 bits of the Upper Address. Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R - #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_K2_E5_SHIFT 0 - #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_K2_E5 (0xffff<<16) // For a 32 bit MSI Message, this is reserved. For 64-bit it contains upper 16 bits of the Upper Address. Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R - #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_K2_E5_SHIFT 16 +#define PCIEIP_REG_MSI_CAP_OFF_08H_REG_K2 0x000058UL //Access:RW DataWidth:0x20 // For a 32 bit MSI Message, this register contains Data. For 64 bit it contains the Upper Address. + #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_K2 (0xffff<<0) // For a 32-bit MSI Message, this field contains Data. For 64-bit it contains lower 16 bits of the Upper Address. Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R + #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_K2_SHIFT 0 + #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_K2 (0xffff<<16) // For a 32 bit MSI Message, this is reserved. For 64-bit it contains upper 16 bits of the Upper Address. Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R + #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_K2_SHIFT 16 #define PCIEIP_REG_MSI_CAP_BB 0x000058UL //Access:RW DataWidth:0x20 // The device driver is prohibited from writing to this register. #define PCIEIP_REG_MSI_CAP_MSI_CAP_ID_BB (0xff<<0) // The 8-bit MSI Capability ID is set to 5 to indicate that the next 8 bytes are a Message Signaled Interrupt capability block. Path = cfg_defs #define PCIEIP_REG_MSI_CAP_MSI_CAP_ID_BB_SHIFT 0 @@ -493,237 +656,472 @@ #define PCIEIP_REG_MSI_CAP_CAP_64BIT_BB_SHIFT 23 #define PCIEIP_REG_MSI_CAP_MSI_PVMASK_CAPABLE_BB (0x1<<24) // This bit indicates if the function supports per vector masking. This value comes from the MSI_PV_MASK_CAP bit in the register space. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap #define PCIEIP_REG_MSI_CAP_MSI_PVMASK_CAPABLE_BB_SHIFT 24 -#define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_K2_E5 0x00005cUL //Access:RW DataWidth:0x20 // For a 64 bit MSI Message, this register contains Data. For 32 bit, it contains Mask Bits if PVM enabled. - #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_K2_E5 (0xffff<<0) // For a 64-bit MSI Message, this field contains Data. For 32-bit, it contains the lower Mask Bits if PVM is enabled. Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R - #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_K2_E5_SHIFT 0 - #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_K2_E5 (0xffff<<16) // For a 64-bit MSI Message, this field contains Data. For 32-bit, it contains the upper Mask Bits if PVM is enabled. Note: The access attributes of this field are as follows: - Dbi: !PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R - #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_K2_E5_SHIFT 16 +#define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_K2 0x00005cUL //Access:RW DataWidth:0x20 // For a 64 bit MSI Message, this register contains Data. For 32 bit, it contains Mask Bits if PVM enabled. + #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_K2 (0xffff<<0) // For a 64-bit MSI Message, this field contains Data. For 32-bit, it contains the lower Mask Bits if PVM is enabled. Note: The access attributes of this field are as follows: - Dbi: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R + #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_K2_SHIFT 0 + #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_K2 (0xffff<<16) // For a 64-bit MSI Message, this field contains Data. For 32-bit, it contains the upper Mask Bits if PVM is enabled. Note: The access attributes of this field are as follows: - Dbi: !PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R + #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_K2_SHIFT 16 #define PCIEIP_REG_MSI_ADDR_L_BB 0x00005cUL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_MSI_ADDR_L_UNUSED0_BB (0x3<<0) // #define PCIEIP_REG_MSI_ADDR_L_UNUSED0_BB_SHIFT 0 #define PCIEIP_REG_MSI_ADDR_L_VAL_BB (0x3fffffff<<2) // This register controls the lower half of the address of the MSI message that are generated. This register is readable in the pci register space. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap #define PCIEIP_REG_MSI_ADDR_L_VAL_BB_SHIFT 2 -#define PCIEIP_REG_MSI_CAP_OFF_10H_REG_K2_E5 0x000060UL //Access:RW DataWidth:0x20 // Used for MSI when Vector Masking Capable. For 32 bit contains Pending Bits. For 64 bit, contains Mask Bits. +#define PCIEIP_REG_MSI_CAP_OFF_10H_REG_K2 0x000060UL //Access:RW DataWidth:0x20 // Used for MSI when Vector Masking Capable. For 32 bit contains Pending Bits. For 64 bit, contains Mask Bits. #define PCIEIP_REG_MSI_ADDR_H_BB 0x000060UL //Access:RW DataWidth:0x20 // This register controls the upper half of the address of the MSI message that are generated. This register is readable in the pci register space. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap -#define PCIEIP_REG_MSI_CAP_OFF_14H_REG_K2_E5 0x000064UL //Access:R DataWidth:0x20 // Used for MSI 64 bit messaging when Vector Masking Capable. Contains Pending Bits. +#define PCIEIP_REG_MSI_CAP_OFF_14H_REG_K2 0x000064UL //Access:R DataWidth:0x20 // Used for MSI 64 bit messaging when Vector Masking Capable. Contains Pending Bits. #define PCIEIP_REG_MSI_DATA_BB 0x000064UL //Access:RW DataWidth:0x20 // This register controls the data value that will be presented on the lower 16 bits of the data bus during MSI messages. The MENA value from the MSI Control register allows a specific number of the lower bits (up to 6) to be modified to indicate different interrupt conditions. This register is readable in the pci register space. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap #define PCIEIP_REG_MSI_DATA_MSI_DATA_BB (0xffff<<0) // #define PCIEIP_REG_MSI_DATA_MSI_DATA_BB_SHIFT 0 -#define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_K2_E5 0x000070UL //Access:RW DataWidth:0x20 // PCI Express Capabilities, ID, Next Pointer Register. - #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_K2_E5 (0xff<<0) // PCIE Capability ID. - #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_K2_E5 (0xff<<8) // PCIE Next Capability Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_K2_E5_SHIFT 8 - #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_K2_E5 (0xf<<16) // PCIE Capability Version Number. - #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_K2_E5_SHIFT 16 - #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_K2_E5 (0xf<<20) // PCIE Device/PortType. - #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_K2_E5_SHIFT 20 - #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_K2_E5 (0x1<<24) // PCIe Slot Implemented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_K2_E5_SHIFT 24 - #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_K2_E5 (0x1f<<25) // PCIE Interrupt Message Number. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_K2_E5_SHIFT 25 - #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_K2_E5 (0x1<<30) // Reserved. - #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_K2_E5_SHIFT 30 -#define PCIEIP_REG_DEVICE_CAPABILITIES_REG_K2_E5 0x000074UL //Access:RW DataWidth:0x20 // Device Capabilities Register. - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_K2_E5 (0x7<<0) // Max Payload Size Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_K2_E5_SHIFT 0 - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_K2_E5 (0x3<<3) // Phantom Functions Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_K2_E5_SHIFT 3 - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_K2_E5 (0x1<<5) // Extended Tag Field Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_K2_E5_SHIFT 5 - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_K2_E5 (0x7<<6) // Applies to endpoints only L0s acceptable latency. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_K2_E5_SHIFT 6 - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_K2_E5 (0x7<<9) // Applies to endpoints only L1 acceptable latency. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_K2_E5_SHIFT 9 - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2_E5 (0x1<<15) // Role-based Error Reporting Implemented. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2_E5_SHIFT 15 - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_K2_E5 (0xff<<18) // Captured Slot Power Limit Value. - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_K2_E5_SHIFT 18 - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_K2_E5 (0x3<<26) // Captured Slot Power Limit Scale. - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_K2_E5_SHIFT 26 - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_K2_E5 (0x1<<28) // Function Level Reset Capability (endpoints only). Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_K2_E5_SHIFT 28 -#define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_K2_E5 0x000078UL //Access:RW DataWidth:0x20 // Device Control and Status Register. - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_K2_E5 (0x1<<0) // Correctable Error Reporting Enable. - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_K2_E5_SHIFT 0 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2_E5 (0x1<<1) // Non-fatal Error Reporting Enable. - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2_E5_SHIFT 1 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_K2_E5 (0x1<<2) // Fatal Error Reporting Enable. - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_K2_E5_SHIFT 2 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_K2_E5 (0x1<<3) // Unsupported Request Reporting Enable. - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_K2_E5_SHIFT 3 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_K2_E5 (0x1<<4) // Enable Relaxed Ordering. - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_K2_E5_SHIFT 4 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_K2_E5 (0x7<<5) // Max Payload Size. Max_Payload_Size . This field sets maximum TLP payload size for the Function. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities register (DEVICE_CAPABILITIES_REG). - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_K2_E5_SHIFT 5 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_K2_E5 (0x1<<8) // Extended Tag Field Enable. The write value is gated with the PCIE_CAP_EXT_TAG_SUPP field of DEVICE_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_K2_E5_SHIFT 8 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_K2_E5 (0x1<<9) // Phantom Functions Enable. The write value is gated with the PCIE_CAP_PHANTOM_FUNC_SUPPORT field of DEVICE_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_K2_E5_SHIFT 9 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_K2_E5 (0x1<<10) // Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. Note: This register field is sticky. - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_K2_E5_SHIFT 10 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_K2_E5 (0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_K2_E5_SHIFT 11 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_K2_E5 (0x7<<12) // Max Read Request Size. - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_K2_E5_SHIFT 12 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_K2_E5 (0x1<<15) // Initiate Function Level Reset (for endpoints). - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_K2_E5_SHIFT 15 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_K2_E5 (0x1<<16) // Correctable Error Detected Status. - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_K2_E5_SHIFT 16 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2_E5 (0x1<<17) // Non-Fatal Error Detected Status. - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2_E5_SHIFT 17 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_K2_E5 (0x1<<18) // Fatal Error Detected Status. - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_K2_E5_SHIFT 18 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_K2_E5 (0x1<<19) // Unsupported Request Detected Status. - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_K2_E5_SHIFT 19 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_K2_E5 (0x1<<20) // Aux Power Detected Status. This bit is derived by sampling the sys_aux_pwr_det input. - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_K2_E5_SHIFT 20 - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_K2_E5 (0x1<<21) // Transactions Pending Status. - #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_K2_E5_SHIFT 21 -#define PCIEIP_REG_LINK_CAPABILITIES_REG_K2_E5 0x00007cUL //Access:RW DataWidth:0x20 // Link Capabilities Register. - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_K2_E5 (0xf<<0) // Maximum Link Speed. In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_K2_E5_SHIFT 0 - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_K2_E5 (0x3f<<4) // Maximum Link Width. In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_K2_E5_SHIFT 4 - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_K2_E5 (0x3<<10) // Level of ASPM (Active State Power Management) Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_K2_E5_SHIFT 10 - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_K2_E5 (0x7<<12) // LOs Exit Latency. There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the core and which one is accessed by a read request. Common Clock operation is supported (possible) in the core when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the core when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_K2_E5_SHIFT 12 - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_K2_E5 (0x7<<15) // L1 Exit Latency. There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the core and which one is accessed by a read request. Common Clock operation is supported (possible) in the core when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the core when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_K2_E5_SHIFT 15 - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_K2_E5 (0x1<<18) // Clock Power Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_K2_E5_SHIFT 18 - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_K2_E5 (0x1<<19) // Surprise Down Error Reporting Capable. - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_K2_E5_SHIFT 19 - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_K2_E5 (0x1<<20) // Data Link Layer Link Active Reporting Capable. - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_K2_E5_SHIFT 20 - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_K2_E5 (0x1<<21) // Link Bandwidth Notification Capable. - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_K2_E5_SHIFT 21 - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_K2_E5 (0x1<<22) // ASPM Optionality Compliance. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_K2_E5_SHIFT 22 - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_K2_E5 (0xff<<24) // Port Number. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_K2_E5_SHIFT 24 -#define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_K2_E5 0x000080UL //Access:RW DataWidth:0x20 // Link Control and Status Register. - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_K2_E5 (0x3<<0) // Active State Power Management (ASPM) Control. - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_K2_E5_SHIFT 0 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_K2_E5 (0x1<<3) // Read Completion Boundary (RCB). Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_K2_E5_SHIFT 3 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_K2_E5 (0x1<<4) // Initiate Link Disable. In a DSP that supports crosslink, the core gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF. Note: The access attributes of this field are as follows: - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_K2_E5_SHIFT 4 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_K2_E5 (0x1<<5) // Initiate Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_K2_E5_SHIFT 5 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_K2_E5 (0x1<<6) // Common Clock Configuration. - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_K2_E5_SHIFT 6 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_K2_E5 (0x1<<7) // Extended Synch. - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_K2_E5_SHIFT 7 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_K2_E5 (0x1<<8) // Enable Clock Power Management. The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RW : RO - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_K2_E5_SHIFT 8 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_K2_E5 (0x1<<9) // Hardware Autonomous Width Disable. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_K2_E5_SHIFT 9 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_K2_E5 (0x1<<10) // Link Bandwidth Management Interrupt Enable. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_K2_E5_SHIFT 10 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_K2_E5 (0x1<<11) // Link Autonomous Bandwidth Management Interrupt Enable. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_K2_E5_SHIFT 11 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_K2_E5 (0x3<<14) // DRS Signaling Control. - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_K2_E5_SHIFT 14 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_K2_E5 (0xf<<16) // Current Link Speed. - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_K2_E5_SHIFT 16 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_K2_E5 (0x3f<<20) // Negotiated Link Width. - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_K2_E5_SHIFT 20 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_K2_E5 (0x1<<27) // LTSSM is in Configuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_K2_E5_SHIFT 27 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_K2_E5 (0x1<<28) // Slot Clock Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_K2_E5_SHIFT 28 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_K2_E5 (0x1<<29) // Data Link Layer Active. - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_K2_E5_SHIFT 29 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_K2_E5 (0x1<<30) // Link Bandwidth Management Status. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_K2_E5_SHIFT 30 - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_K2_E5 (0x1<<31) // Link Autonomous Bandwidth Status. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO - #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_K2_E5_SHIFT 31 -#define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_K2_E5 0x000094UL //Access:R DataWidth:0x20 // Device Capabilities 2 Register. - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_K2_E5 (0xf<<0) // Completion Timeout Ranges Supported. - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_K2_E5_SHIFT 0 - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_K2_E5 (0x1<<4) // Completion Timeout Disable Supported. - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_K2_E5_SHIFT 4 - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_K2_E5 (0x1<<5) // ARI Forwarding Supported. - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_K2_E5_SHIFT 5 - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_K2_E5 (0x1<<6) // Atomic Operation Routing Supported. - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_K2_E5_SHIFT 6 - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2_E5 (0x1<<7) // 32 Bit AtomicOp Completer Supported. - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2_E5_SHIFT 7 - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2_E5 (0x1<<8) // 64 Bit AtomicOp Completer Supported. - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2_E5_SHIFT 8 - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_K2_E5 (0x1<<9) // 128 Bit CAS Completer Supported. - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_K2_E5_SHIFT 9 - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_K2_E5 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing. - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_K2_E5_SHIFT 10 - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_K2_E5 (0x1<<11) // LTR Mechanism Supported. - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_K2_E5_SHIFT 11 - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_K2_E5 (0x1<<12) // TPH Completer Supported Bit 0. - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_K2_E5_SHIFT 12 - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_K2_E5 (0x1<<13) // TPH Completer Supported Bit 1. - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_K2_E5_SHIFT 13 - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_K2_E5 (0x3<<18) // (OBFF) Optimized Buffer Flush/fill Supported. - #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_K2_E5_SHIFT 18 -#define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_K2_E5 0x000098UL //Access:RW DataWidth:0x20 // Device Control 2 and Status 2 Register. - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_K2_E5 (0xf<<0) // Completion Timeout Value. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_K2_E5_SHIFT 0 - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_K2_E5 (0x1<<4) // Completion Timeout Disable. - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_K2_E5_SHIFT 4 - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_K2_E5 (0x1<<5) // ARI Forwarding Enable. - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_K2_E5_SHIFT 5 - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN_K2_E5 (0x1<<6) // AtomicOp Requester Enable. - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN_K2_E5_SHIFT 6 - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_K2_E5 (0x1<<7) // AtomicOp Egress Blocking. - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_K2_E5_SHIFT 7 - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_K2_E5 (0x1<<8) // IDO Request Enable. - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_K2_E5_SHIFT 8 - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN_K2_E5 (0x1<<9) // IDO Completion Enable. - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN_K2_E5_SHIFT 9 - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_K2_E5 (0x1<<10) // LTR Mechanism Enable. The write value is gated with the PCIE_CAP_LTR_SUPP field of DEVICE_CAPABILITIES2_REG. Note: RW for function #0 and RsdvP for all other functions - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_K2_E5_SHIFT 10 - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_OBFF_EN_K2_E5 (0x3<<13) // OBFF Enable. Note: RW for function #0 and RsdvP for all other functions - #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_OBFF_EN_K2_E5_SHIFT 13 -#define PCIEIP_REG_LINK_CAPABILITIES2_REG_K2_E5 0x00009cUL //Access:RW DataWidth:0x20 // Link Capabilities 2 Register. - #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_K2_E5 (0x7f<<1) // Supported Link Speeds Vector. This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register. - #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_K2_E5_SHIFT 1 - #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_K2_E5 (0x1<<8) // Cross Link Supported. - #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_K2_E5_SHIFT 8 - #define PCIEIP_REG_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_K2_E5 (0x1<<31) // DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_K2_E5_SHIFT 31 -#define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_K2_E5 0x0000a0UL //Access:RW DataWidth:0x20 // Link Control 2 and Status 2 Register. - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_K2_E5 (0xf<<0) // Target Link Speed. In M-PCIe mode, the contents of this field are derived from other registers. Note: This register field is sticky. - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_K2_E5_SHIFT 0 - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_K2_E5 (0x1<<4) // Enter Compliance Mode. Note: This register field is sticky. - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_K2_E5_SHIFT 4 - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_K2_E5 (0x1<<5) // Hardware Autonomous Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_K2_E5_SHIFT 5 - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_K2_E5 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. Note: This register field is sticky. - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_K2_E5_SHIFT 6 - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_K2_E5 (0x7<<7) // Controls Transmit Margin for Debug or Compliance. Note: This register field is sticky. - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_K2_E5_SHIFT 7 - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_K2_E5 (0x1<<10) // Enter Modified Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_K2_E5_SHIFT 10 - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_K2_E5 (0x1<<11) // Sets Compliance Skip Ordered Sets transmission. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_K2_E5_SHIFT 11 - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_K2_E5 (0xf<<12) // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_K2_E5_SHIFT 12 - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_K2_E5 (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is always 0x0. In C-PCIe mode, its contents are derived by sampling the PIPE - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_K2_E5_SHIFT 16 - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_K2_E5 (0x1<<17) // Equalization 8.0GT/s Complete. Note: This register field is sticky. - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_K2_E5_SHIFT 17 - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_K2_E5 (0x1<<18) // Equalization 8.0GT/s Phase 1 Successful. Note: This register field is sticky. - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_K2_E5_SHIFT 18 - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_K2_E5 (0x1<<19) // Equalization 8.0GT/s Phase 2 Successful. Note: This register field is sticky. - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_K2_E5_SHIFT 19 - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_K2_E5 (0x1<<20) // Equalization 8.0GT/s Phase 3 Successful. Note: This register field is sticky. - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_K2_E5_SHIFT 20 - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_K2_E5 (0x1<<21) // Link Equalization Request 8.0GT/s. - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_K2_E5_SHIFT 21 - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_K2_E5 (0x7<<28) // Downstream Component Presence. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0. - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_K2_E5_SHIFT 28 - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_K2_E5 (0x1<<31) // DRS Message Received. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0. - #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_K2_E5_SHIFT 31 +#define PCIEIP_REG_PCIEEP_E_CAP_LIST_E5 0x000070UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_E_CAP_LIST_PCIEID_E5 (0xff<<0) // PCI Express capability ID. + #define PCIEIP_REG_PCIEEP_E_CAP_LIST_PCIEID_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_E_CAP_LIST_NCP_E5 (0xff<<8) // Next capability pointer. Points to the MSI-X Capabilities by default, writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_E_CAP_LIST_NCP_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_E_CAP_LIST_PCIECV_E5 (0xf<<16) // PCI Express capability version. + #define PCIEIP_REG_PCIEEP_E_CAP_LIST_PCIECV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_E_CAP_LIST_DPT_E5 (0xf<<20) // Device port type. 0x0 = PCI Express endpoint. 0x1 = Legacy PCI Express endpoint. All other encodings are not supported + #define PCIEIP_REG_PCIEEP_E_CAP_LIST_DPT_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_E_CAP_LIST_SI_E5 (0x1<<24) // Slot implemented. This bit is writable through PEM()_CFG_WR. However, it must be 0 for an endpoint device. Therefore, the application must not write a one to this bit. + #define PCIEIP_REG_PCIEEP_E_CAP_LIST_SI_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_E_CAP_LIST_IMN_E5 (0x1f<<25) // Interrupt message number. Updated by hardware, writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_E_CAP_LIST_IMN_E5_SHIFT 25 +#define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_K2 0x000070UL //Access:RW DataWidth:0x20 // PCI Express Capabilities, ID, Next Pointer Register. + #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_K2 (0xff<<0) // PCIE Capability ID. + #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_K2 (0xff<<8) // PCIE Next Capability Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_K2_SHIFT 8 + #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_K2 (0xf<<16) // PCIE Capability Version Number. + #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_K2_SHIFT 16 + #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_K2 (0xf<<20) // PCIE Device/PortType. + #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_K2_SHIFT 20 + #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_K2 (0x1<<24) // PCIe Slot Implemented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_K2_SHIFT 24 + #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_K2 (0x1f<<25) // PCIE Interrupt Message Number. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_K2_SHIFT 25 + #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_K2 (0x1<<30) // Reserved. + #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_K2_SHIFT 30 +#define PCIEIP_REG_PCIEEP_DEV_CAP_E5 0x000074UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_DEV_CAP_MPSS_E5 (0x7<<0) // Max_Payload_Size supported, writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_DEV_CAP_MPSS_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_DEV_CAP_PFS_E5 (0x3<<3) // Phantom function supported. This field is writable through PEM()_CFG_WR. However, phantom function is not supported. Therefore, the application must not write any value other than 0x0 to this field. + #define PCIEIP_REG_PCIEEP_DEV_CAP_PFS_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_DEV_CAP_ETFS_E5 (0x1<<5) // Extended tag field supported. This bit is writable through PEM()_CFG_WR. + #define PCIEIP_REG_PCIEEP_DEV_CAP_ETFS_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_DEV_CAP_EL0AL_E5 (0x7<<6) // Endpoint L0s acceptable latency, writable through PEM()_CFG_WR. + #define PCIEIP_REG_PCIEEP_DEV_CAP_EL0AL_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_DEV_CAP_EL1AL_E5 (0x7<<9) // Endpoint L1 acceptable latency, writable through PEM()_CFG_WR. + #define PCIEIP_REG_PCIEEP_DEV_CAP_EL1AL_E5_SHIFT 9 + #define PCIEIP_REG_PCIEEP_DEV_CAP_RBER_E5 (0x1<<15) // Role-based error reporting, writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_DEV_CAP_RBER_E5_SHIFT 15 + #define PCIEIP_REG_PCIEEP_DEV_CAP_CSPLV_E5 (0xff<<18) // Captured slot power limit value. From message from RC, upstream port only. + #define PCIEIP_REG_PCIEEP_DEV_CAP_CSPLV_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_DEV_CAP_CSPLS_E5 (0x3<<26) // Captured slot power limit scale. From message from RC, upstream port only. + #define PCIEIP_REG_PCIEEP_DEV_CAP_CSPLS_E5_SHIFT 26 + #define PCIEIP_REG_PCIEEP_DEV_CAP_FLR_CAP_E5 (0x1<<28) // Function level reset capability. Set to 1 for SR-IOV core. + #define PCIEIP_REG_PCIEEP_DEV_CAP_FLR_CAP_E5_SHIFT 28 +#define PCIEIP_REG_DEVICE_CAPABILITIES_REG_K2 0x000074UL //Access:RW DataWidth:0x20 // Device Capabilities Register. + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_K2 (0x7<<0) // Max Payload Size Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_K2_SHIFT 0 + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_K2 (0x3<<3) // Phantom Functions Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_K2_SHIFT 3 + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_K2 (0x1<<5) // Extended Tag Field Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_K2_SHIFT 5 + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_K2 (0x7<<6) // Applies to endpoints only L0s acceptable latency. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_K2_SHIFT 6 + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_K2 (0x7<<9) // Applies to endpoints only L1 acceptable latency. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_K2_SHIFT 9 + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2 (0x1<<15) // Role-based Error Reporting Implemented. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2_SHIFT 15 + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_K2 (0xff<<18) // Captured Slot Power Limit Value. + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_K2_SHIFT 18 + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_K2 (0x3<<26) // Captured Slot Power Limit Scale. + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_K2_SHIFT 26 + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_K2 (0x1<<28) // Function Level Reset Capability (endpoints only). Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_K2_SHIFT 28 +#define PCIEIP_REG_PCIEEP_DEV_CTL_E5 0x000078UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_DEV_CTL_CE_EN_E5 (0x1<<0) // Correctable error reporting enable. + #define PCIEIP_REG_PCIEEP_DEV_CTL_CE_EN_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_DEV_CTL_NFE_EN_E5 (0x1<<1) // Nonfatal error reporting enable. + #define PCIEIP_REG_PCIEEP_DEV_CTL_NFE_EN_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_DEV_CTL_FE_EN_E5 (0x1<<2) // Fatal error reporting enable. + #define PCIEIP_REG_PCIEEP_DEV_CTL_FE_EN_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_DEV_CTL_UR_EN_E5 (0x1<<3) // Unsupported request reporting enable. + #define PCIEIP_REG_PCIEEP_DEV_CTL_UR_EN_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_DEV_CTL_RO_EN_E5 (0x1<<4) // Enable relaxed ordering. + #define PCIEIP_REG_PCIEEP_DEV_CTL_RO_EN_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_DEV_CTL_MPS_E5 (0x7<<5) // Max payload size. Legal values: 0x0 = 128 bytes. 0x1 = 256 bytes. 0x2 = 512 bytes. 0x3 = 1024 bytes. Larger sizes are not supported by CNXXXX. DPI_SLI_PRT()_CFG[MPS] must be set to the same value as this field for proper functionality. + #define PCIEIP_REG_PCIEEP_DEV_CTL_MPS_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_DEV_CTL_ETF_EN_E5 (0x1<<8) // Extended tag field enable. Set this bit to enable extended tags. + #define PCIEIP_REG_PCIEEP_DEV_CTL_ETF_EN_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_DEV_CTL_PF_EN_E5 (0x1<<9) // Phantom function enable. This bit should never be set; CNXXXX requests never uses phantom functions. + #define PCIEIP_REG_PCIEEP_DEV_CTL_PF_EN_E5_SHIFT 9 + #define PCIEIP_REG_PCIEEP_DEV_CTL_AP_EN_E5 (0x1<<10) // AUX power PM enable (not supported). + #define PCIEIP_REG_PCIEEP_DEV_CTL_AP_EN_E5_SHIFT 10 + #define PCIEIP_REG_PCIEEP_DEV_CTL_NS_EN_E5 (0x1<<11) // Enable no snoop. + #define PCIEIP_REG_PCIEEP_DEV_CTL_NS_EN_E5_SHIFT 11 + #define PCIEIP_REG_PCIEEP_DEV_CTL_MRRS_E5 (0x7<<12) // Max read request size. 0x0 =128 bytes. 0x1 = 256 bytes. 0x2 = 512 bytes. 0x3 = 1024 bytes. 0x4 = 2048 bytes. 0x5 = 4096 bytes. DPI_SLI_PRT()_CFG[MRRS] must be set and properly must not exceed the desired max read request size. + #define PCIEIP_REG_PCIEEP_DEV_CTL_MRRS_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_DEV_CTL_I_FLR_E5 (0x1<<15) // Initiate function level reset. [I_FLR] must not be written to one via the indirect PEM()_CFG_WR. It should only ever be written to one via a direct PCIe access. + #define PCIEIP_REG_PCIEEP_DEV_CTL_I_FLR_E5_SHIFT 15 + #define PCIEIP_REG_PCIEEP_DEV_CTL_CE_D_E5 (0x1<<16) // Correctable error detected. Errors are logged in this register regardless of whether or not error reporting is enabled in the device control register. This field is set if we receive any of the errors in PCIEEP_COR_ERR_STAT, for example a replay-timer timeout. Also, it can be set if we get any of the errors in PCIEEP_UCOR_ERR_MSK that has a severity set to nonfatal and meets the advisory nonfatal criteria, which most ECRC errors should. + #define PCIEIP_REG_PCIEEP_DEV_CTL_CE_D_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_DEV_CTL_NFE_D_E5 (0x1<<17) // Nonfatal error detected. Errors are logged in this register regardless of whether or not error reporting is enabled in the device control register. This field is set if we receive any of the errors in PCIEEP_UCOR_ERR_MSK that has a severity set to nonfatal and does not meet advisory nonfatal criteria, which most poisoned TLPs should. + #define PCIEIP_REG_PCIEEP_DEV_CTL_NFE_D_E5_SHIFT 17 + #define PCIEIP_REG_PCIEEP_DEV_CTL_FE_D_E5 (0x1<<18) // Fatal error detected. Errors are logged in this register regardless of whether or not error reporting is enabled in the device control register. This field is set if we receive any of the errors in PCIEEP_UCOR_ERR_MSK that has a severity set to fatal. Malformed TLPs generally fit into this category. + #define PCIEIP_REG_PCIEEP_DEV_CTL_FE_D_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_DEV_CTL_UR_D_E5 (0x1<<19) // Unsupported request detected. Errors are logged in this register regardless of whether or not error reporting is enabled in the device control register. [UR_D] occurs when PEM receives something unsupported. Unsupported requests are nonfatal errors, so [UR_D] should cause [NFE_D]. Receiving a vendor-defined message should cause an unsupported request. + #define PCIEIP_REG_PCIEEP_DEV_CTL_UR_D_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_DEV_CTL_AP_D_E5 (0x1<<20) // AUX power detected. Set to one if AUX power detected. + #define PCIEIP_REG_PCIEEP_DEV_CTL_AP_D_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_DEV_CTL_TP_E5 (0x1<<21) // Transaction pending. Set to 1 when nonposted requests are not yet completed and set to 0 when they are completed. + #define PCIEIP_REG_PCIEEP_DEV_CTL_TP_E5_SHIFT 21 +#define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_K2 0x000078UL //Access:RW DataWidth:0x20 // Device Control and Status Register. + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_K2 (0x1<<0) // Correctable Error Reporting Enable. + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_K2_SHIFT 0 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2 (0x1<<1) // Non-fatal Error Reporting Enable. + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2_SHIFT 1 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_K2 (0x1<<2) // Fatal Error Reporting Enable. + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_K2_SHIFT 2 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_K2 (0x1<<3) // Unsupported Request Reporting Enable. + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_K2_SHIFT 3 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_K2 (0x1<<4) // Enable Relaxed Ordering. + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_K2_SHIFT 4 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_K2 (0x7<<5) // Max Payload Size. Max_Payload_Size . This field sets maximum TLP payload size for the Function. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities register (DEVICE_CAPABILITIES_REG). + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_K2_SHIFT 5 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_K2 (0x1<<8) // Extended Tag Field Enable. The write value is gated with the PCIE_CAP_EXT_TAG_SUPP field of DEVICE_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_K2_SHIFT 8 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_K2 (0x1<<9) // Phantom Functions Enable. The write value is gated with the PCIE_CAP_PHANTOM_FUNC_SUPPORT field of DEVICE_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_K2_SHIFT 9 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_K2 (0x1<<10) // Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. Note: This register field is sticky. + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_K2_SHIFT 10 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_K2 (0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_K2_SHIFT 11 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_K2 (0x7<<12) // Max Read Request Size. + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_K2_SHIFT 12 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_K2 (0x1<<15) // Initiate Function Level Reset (for endpoints). + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_K2_SHIFT 15 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_K2 (0x1<<16) // Correctable Error Detected Status. + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_K2_SHIFT 16 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2 (0x1<<17) // Non-Fatal Error Detected Status. + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2_SHIFT 17 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_K2 (0x1<<18) // Fatal Error Detected Status. + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_K2_SHIFT 18 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_K2 (0x1<<19) // Unsupported Request Detected Status. + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_K2_SHIFT 19 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_K2 (0x1<<20) // Aux Power Detected Status. This bit is derived by sampling the sys_aux_pwr_det input. + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_K2_SHIFT 20 + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_K2 (0x1<<21) // Transactions Pending Status. + #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_K2_SHIFT 21 +#define PCIEIP_REG_PCIEEP_LINK_CAP_E5 0x00007cUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_LINK_CAP_MLS_E5 (0xf<<0) // Maximum link speed. 0x1 = 2.5 GHz supported. 0x2 = 5.0 GHz and 2.5 GHz supported. 0x3 = 8.0 GHz, 5.0 GHz and 2.5 GHz supported. 0x4 = 16.0 GHz, 8.0 Ghz, 5.0 GHz, and 2.5 GHz supported. This field is writable through PEM()_CFG_WR. + #define PCIEIP_REG_PCIEEP_LINK_CAP_MLS_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_LINK_CAP_MLW_E5 (0x3f<<4) // Maximum link width. The reset value of this field is determined by the value read from PEM()_CFG[LANES]. This field is writable through PEM()_CFG_WR. Note that zeroing both [MLW] and [MLS] out of reset, using the EEPROM, will prevent the ltssm from advancing past CONFIG. This can be useful to allow software to locally boot and perform preconfiguration and bug fixes. Setting [MLW] and [MLS] to valid values will then allow the lttsm to advance and the link to come up. + #define PCIEIP_REG_PCIEEP_LINK_CAP_MLW_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_LINK_CAP_ASLPMS_E5 (0x3<<10) // Active state link PM support. Only L1 is supported (L0s not supported). The default value is the value that software specifies during hardware configuration, writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_LINK_CAP_ASLPMS_E5_SHIFT 10 + #define PCIEIP_REG_PCIEEP_LINK_CAP_L0EL_E5 (0x7<<12) // L0s exit latency. The default value is the value that software specifies during hardware configuration, writable through PEM()_CFG_WR. + #define PCIEIP_REG_PCIEEP_LINK_CAP_L0EL_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_LINK_CAP_L1EL_E5 (0x7<<15) // L1 exit latency. The default value is the value that software specifies during hardware configuration, writable through PEM()_CFG_WR. + #define PCIEIP_REG_PCIEEP_LINK_CAP_L1EL_E5_SHIFT 15 + #define PCIEIP_REG_PCIEEP_LINK_CAP_CPM_E5 (0x1<<18) // Clock power management. Indicates that component tolerates the removal of any reference clock(s) via the clock request (PCI_CLKREQ_L) mechanism when the Link is in the L1 and L2/L3 ready link states. + #define PCIEIP_REG_PCIEEP_LINK_CAP_CPM_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_LINK_CAP_SDERC_E5 (0x1<<19) // Surprise down error reporting capable. Set to 0 for endpoint devices. + #define PCIEIP_REG_PCIEEP_LINK_CAP_SDERC_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_LINK_CAP_DLLARC_E5 (0x1<<20) // Data link layer active reporting capable. + #define PCIEIP_REG_PCIEEP_LINK_CAP_DLLARC_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_LINK_CAP_LBNC_E5 (0x1<<21) // Link bandwidth notification capability. Set to 0 for endpoint devices. + #define PCIEIP_REG_PCIEEP_LINK_CAP_LBNC_E5_SHIFT 21 + #define PCIEIP_REG_PCIEEP_LINK_CAP_ASPM_E5 (0x1<<22) // ASPM optionality compliance. + #define PCIEIP_REG_PCIEEP_LINK_CAP_ASPM_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_LINK_CAP_PNUM_E5 (0xff<<24) // Port number, writable through PEM()_CFG_WR. + #define PCIEIP_REG_PCIEEP_LINK_CAP_PNUM_E5_SHIFT 24 +#define PCIEIP_REG_LINK_CAPABILITIES_REG_K2 0x00007cUL //Access:RW DataWidth:0x20 // Link Capabilities Register. + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_K2 (0xf<<0) // Maximum Link Speed. In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_K2_SHIFT 0 + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_K2 (0x3f<<4) // Maximum Link Width. In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_K2_SHIFT 4 + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_K2 (0x3<<10) // Level of ASPM (Active State Power Management) Support. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_K2_SHIFT 10 + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_K2 (0x7<<12) // LOs Exit Latency. There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the core and which one is accessed by a read request. Common Clock operation is supported (possible) in the core when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the core when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_K2_SHIFT 12 + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_K2 (0x7<<15) // L1 Exit Latency. There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the core and which one is accessed by a read request. Common Clock operation is supported (possible) in the core when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the core when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_K2_SHIFT 15 + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_K2 (0x1<<18) // Clock Power Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_K2_SHIFT 18 + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_K2 (0x1<<19) // Surprise Down Error Reporting Capable. + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_K2_SHIFT 19 + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_K2 (0x1<<20) // Data Link Layer Link Active Reporting Capable. + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_K2_SHIFT 20 + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_K2 (0x1<<21) // Link Bandwidth Notification Capable. + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_K2_SHIFT 21 + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_K2 (0x1<<22) // ASPM Optionality Compliance. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_K2_SHIFT 22 + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_K2 (0xff<<24) // Port Number. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_K2_SHIFT 24 +#define PCIEIP_REG_PCIEEP_LINK_CTL_E5 0x000080UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_LINK_CTL_ASLPC_E5 (0x3<<0) // Active state link PM control. + #define PCIEIP_REG_PCIEEP_LINK_CTL_ASLPC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_LINK_CTL_RCB_E5 (0x1<<3) // Read completion boundary (RCB). + #define PCIEIP_REG_PCIEEP_LINK_CTL_RCB_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_LINK_CTL_LD_E5 (0x1<<4) // Link disable. Not applicable for an upstream port or endpoint device. Hardwired to 0. + #define PCIEIP_REG_PCIEEP_LINK_CTL_LD_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_LINK_CTL_RL_E5 (0x1<<5) // Retrain link. Not applicable for an upstream port or endpoint device. Hardwired to 0. + #define PCIEIP_REG_PCIEEP_LINK_CTL_RL_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_LINK_CTL_CCC_E5 (0x1<<6) // Common clock configuration. + #define PCIEIP_REG_PCIEEP_LINK_CTL_CCC_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_LINK_CTL_ES_E5 (0x1<<7) // Extended synch. + #define PCIEIP_REG_PCIEEP_LINK_CTL_ES_E5_SHIFT 7 + #define PCIEIP_REG_PCIEEP_LINK_CTL_ECPM_E5 (0x1<<8) // Enable clock power management. Hardwired to 0 if clock power management is disabled in the link capabilities register. + #define PCIEIP_REG_PCIEEP_LINK_CTL_ECPM_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_LINK_CTL_HAWD_E5 (0x1<<9) // Hardware autonomous width disable. + #define PCIEIP_REG_PCIEEP_LINK_CTL_HAWD_E5_SHIFT 9 + #define PCIEIP_REG_PCIEEP_LINK_CTL_LBM_INT_ENB_E5 (0x1<<10) // Link bandwidth management interrupt enable. This bit is not applicable and is reserved for endpoints. + #define PCIEIP_REG_PCIEEP_LINK_CTL_LBM_INT_ENB_E5_SHIFT 10 + #define PCIEIP_REG_PCIEEP_LINK_CTL_LAB_INT_ENB_E5 (0x1<<11) // Link autonomous bandwidth interrupt enable. This bit is not applicable and is reserved for endpoints. + #define PCIEIP_REG_PCIEEP_LINK_CTL_LAB_INT_ENB_E5_SHIFT 11 + #define PCIEIP_REG_PCIEEP_LINK_CTL_DRS_SC_E5 (0x3<<14) // DRS signaling control. + #define PCIEIP_REG_PCIEEP_LINK_CTL_DRS_SC_E5_SHIFT 14 + #define PCIEIP_REG_PCIEEP_LINK_CTL_LS_E5 (0xf<<16) // Current link speed. The encoded value specifies a bit location in the supported link speeds vector (in the link capabilities 2 register) that corresponds to the current link speed. 0x1 = Supported link speeds vector field bit 0. 0x2 = Supported link speeds vector field bit 1. 0x3 = Supported link speeds vector field bit 2. 0x4 = Supported link speeds vector field bit 3. + #define PCIEIP_REG_PCIEEP_LINK_CTL_LS_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_LINK_CTL_NLW_E5 (0x3f<<20) // Negotiated link width. Set automatically by hardware after link initialization. Value is undefined when link is not up. + #define PCIEIP_REG_PCIEEP_LINK_CTL_NLW_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_LINK_CTL_LT_E5 (0x1<<27) // Link training. Not applicable for an upstream port or endpoint device, hardwired to 0. + #define PCIEIP_REG_PCIEEP_LINK_CTL_LT_E5_SHIFT 27 + #define PCIEIP_REG_PCIEEP_LINK_CTL_SCC_E5 (0x1<<28) // Slot clock configuration. Indicates that the component uses the same physical reference clock that the platform provides on the connector. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_LINK_CTL_SCC_E5_SHIFT 28 + #define PCIEIP_REG_PCIEEP_LINK_CTL_DLLA_E5 (0x1<<29) // Data link layer active. Not applicable for an upstream port or endpoint device, hardwired to 0. + #define PCIEIP_REG_PCIEEP_LINK_CTL_DLLA_E5_SHIFT 29 + #define PCIEIP_REG_PCIEEP_LINK_CTL_LBM_E5 (0x1<<30) // Link bandwidth management status. + #define PCIEIP_REG_PCIEEP_LINK_CTL_LBM_E5_SHIFT 30 + #define PCIEIP_REG_PCIEEP_LINK_CTL_LAB_E5 (0x1<<31) // Link autonomous bandwidth status. + #define PCIEIP_REG_PCIEEP_LINK_CTL_LAB_E5_SHIFT 31 +#define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_K2 0x000080UL //Access:RW DataWidth:0x20 // Link Control and Status Register. + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_K2 (0x3<<0) // Active State Power Management (ASPM) Control. + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_K2_SHIFT 0 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_K2 (0x1<<3) // Read Completion Boundary (RCB). Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_K2_SHIFT 3 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_K2 (0x1<<4) // Initiate Link Disable. In a DSP that supports crosslink, the core gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF. Note: The access attributes of this field are as follows: - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_K2_SHIFT 4 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_K2 (0x1<<5) // Initiate Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_K2_SHIFT 5 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_K2 (0x1<<6) // Common Clock Configuration. + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_K2_SHIFT 6 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_K2 (0x1<<7) // Extended Synch. + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_K2_SHIFT 7 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_K2 (0x1<<8) // Enable Clock Power Management. The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RW : RO + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_K2_SHIFT 8 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_K2 (0x1<<9) // Hardware Autonomous Width Disable. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_K2_SHIFT 9 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_K2 (0x1<<10) // Link Bandwidth Management Interrupt Enable. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_K2_SHIFT 10 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_K2 (0x1<<11) // Link Autonomous Bandwidth Management Interrupt Enable. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_K2_SHIFT 11 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_K2 (0x3<<14) // DRS Signaling Control. + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_K2_SHIFT 14 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_K2 (0xf<<16) // Current Link Speed. + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_K2_SHIFT 16 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_K2 (0x3f<<20) // Negotiated Link Width. + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_K2_SHIFT 20 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_K2 (0x1<<27) // LTSSM is in Configuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_K2_SHIFT 27 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_K2 (0x1<<28) // Slot Clock Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_K2_SHIFT 28 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_K2 (0x1<<29) // Data Link Layer Active. + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_K2_SHIFT 29 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_K2 (0x1<<30) // Link Bandwidth Management Status. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_K2_SHIFT 30 + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_K2 (0x1<<31) // Link Autonomous Bandwidth Status. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO + #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_K2_SHIFT 31 +#define PCIEIP_REG_PCIEEP_DEV_CAP2_E5 0x000094UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_DEV_CAP2_CTRS_E5 (0xf<<0) // Completion timeout ranges supported. + #define PCIEIP_REG_PCIEEP_DEV_CAP2_CTRS_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_DEV_CAP2_CTDS_E5 (0x1<<4) // Completion timeout disable supported. + #define PCIEIP_REG_PCIEEP_DEV_CAP2_CTDS_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_DEV_CAP2_ARI_E5 (0x1<<5) // Alternate routing ID forwarding supported (not applicable for EP). + #define PCIEIP_REG_PCIEEP_DEV_CAP2_ARI_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_DEV_CAP2_ATOM_OPS_E5 (0x1<<6) // AtomicOp routing supported (not applicable for EP). + #define PCIEIP_REG_PCIEEP_DEV_CAP2_ATOM_OPS_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_DEV_CAP2_ATOM32S_E5 (0x1<<7) // 32-bit AtomicOp supported. Note that inbound AtomicOps targeting BAR0 are not supported and are dropped as an unsupported request. + #define PCIEIP_REG_PCIEEP_DEV_CAP2_ATOM32S_E5_SHIFT 7 + #define PCIEIP_REG_PCIEEP_DEV_CAP2_ATOM64S_E5 (0x1<<8) // 64-bit AtomicOp supported. Note that inbound AtomicOps targeting BAR0 are not supported and are dropped as an unsupported request. + #define PCIEIP_REG_PCIEEP_DEV_CAP2_ATOM64S_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_DEV_CAP2_ATOM128S_E5 (0x1<<9) // 128-bit AtomicOp supported. Note that inbound AtomicOps targeting BAR0 are not supported and are dropped as an unsupported request. + #define PCIEIP_REG_PCIEEP_DEV_CAP2_ATOM128S_E5_SHIFT 9 + #define PCIEIP_REG_PCIEEP_DEV_CAP2_NOROPRPR_E5 (0x1<<10) // No RO-enabled PR-PR passing. (This bit applies to RCs.) + #define PCIEIP_REG_PCIEEP_DEV_CAP2_NOROPRPR_E5_SHIFT 10 + #define PCIEIP_REG_PCIEEP_DEV_CAP2_LTRS_E5 (0x1<<11) // Latency tolerance reporting (LTR) mechanism supported. + #define PCIEIP_REG_PCIEEP_DEV_CAP2_LTRS_E5_SHIFT 11 + #define PCIEIP_REG_PCIEEP_DEV_CAP2_TPHS_E5 (0x3<<12) // TPH completer supported. + #define PCIEIP_REG_PCIEEP_DEV_CAP2_TPHS_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_DEV_CAP2_LN_SYS_CLS_E5 (0x3<<14) // LN System CLS (not applicable for EP). + #define PCIEIP_REG_PCIEEP_DEV_CAP2_LN_SYS_CLS_E5_SHIFT 14 + #define PCIEIP_REG_PCIEEP_DEV_CAP2_TAG10B_CPL_SUPP_E5 (0x1<<16) // 10-bit tag completer supported. + #define PCIEIP_REG_PCIEEP_DEV_CAP2_TAG10B_CPL_SUPP_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_DEV_CAP2_TAG10B_REQ_SUPP_E5 (0x1<<17) // 10-bit tag requestor supported. + #define PCIEIP_REG_PCIEEP_DEV_CAP2_TAG10B_REQ_SUPP_E5_SHIFT 17 + #define PCIEIP_REG_PCIEEP_DEV_CAP2_OBFFS_E5 (0x3<<18) // Optimized buffer flush fill (OBFF) supported. + #define PCIEIP_REG_PCIEEP_DEV_CAP2_OBFFS_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_DEV_CAP2_EFFS_E5 (0x1<<20) // Extended fmt field supported. + #define PCIEIP_REG_PCIEEP_DEV_CAP2_EFFS_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_DEV_CAP2_EETPS_E5 (0x1<<21) // End-end TLP prefix supported. + #define PCIEIP_REG_PCIEEP_DEV_CAP2_EETPS_E5_SHIFT 21 + #define PCIEIP_REG_PCIEEP_DEV_CAP2_MEETP_E5 (0x3<<22) // Max end-end TLP prefixes. 0x1 = 1. 0x2 = 2. 0x3 = 3. 0x0 = 4. + #define PCIEIP_REG_PCIEEP_DEV_CAP2_MEETP_E5_SHIFT 22 +#define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_K2 0x000094UL //Access:R DataWidth:0x20 // Device Capabilities 2 Register. + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_K2 (0xf<<0) // Completion Timeout Ranges Supported. + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_K2_SHIFT 0 + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_K2 (0x1<<4) // Completion Timeout Disable Supported. + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_K2_SHIFT 4 + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_K2 (0x1<<5) // ARI Forwarding Supported. + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_K2_SHIFT 5 + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_K2 (0x1<<6) // Atomic Operation Routing Supported. + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_K2_SHIFT 6 + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2 (0x1<<7) // 32 Bit AtomicOp Completer Supported. + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2_SHIFT 7 + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2 (0x1<<8) // 64 Bit AtomicOp Completer Supported. + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2_SHIFT 8 + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_K2 (0x1<<9) // 128 Bit CAS Completer Supported. + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_K2_SHIFT 9 + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_K2 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing. + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_K2_SHIFT 10 + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_K2 (0x1<<11) // LTR Mechanism Supported. + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_K2_SHIFT 11 + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_K2 (0x1<<12) // TPH Completer Supported Bit 0. + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_K2_SHIFT 12 + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_K2 (0x1<<13) // TPH Completer Supported Bit 1. + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_K2_SHIFT 13 + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_K2 (0x3<<18) // (OBFF) Optimized Buffer Flush/fill Supported. + #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_K2_SHIFT 18 +#define PCIEIP_REG_PCIEEP_DEV_CTL2_E5 0x000098UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_DEV_CTL2_CTV_E5 (0xf<<0) // Completion timeout value. 0x0 = Default range: 16 ms to 55 ms. 0x1 = 50 us to 100 us. 0x2 = 1 ms to 10 ms. 0x3 = 16 ms to 55 ms. 0x6 = 65 ms to 210 ms. 0x9 = 260 ms to 900 ms. 0xA = 1 s to 3.5 s. 0xD = 4 s to 13 s. 0xE = 17 s to 64 s. Values not defined are reserved. + #define PCIEIP_REG_PCIEEP_DEV_CTL2_CTV_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_DEV_CTL2_CTD_E5 (0x1<<4) // Completion timeout disable. + #define PCIEIP_REG_PCIEEP_DEV_CTL2_CTD_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_DEV_CTL2_ARI_E5 (0x1<<5) // Alternate routing ID forwarding supported (not applicable for EP). + #define PCIEIP_REG_PCIEEP_DEV_CTL2_ARI_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_DEV_CTL2_ATOM_OP_E5 (0x1<<6) // AtomicOp requester enable. + #define PCIEIP_REG_PCIEEP_DEV_CTL2_ATOM_OP_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_DEV_CTL2_ATOM_OP_EB_E5 (0x1<<7) // AtomicOp egress blocking. + #define PCIEIP_REG_PCIEEP_DEV_CTL2_ATOM_OP_EB_E5_SHIFT 7 + #define PCIEIP_REG_PCIEEP_DEV_CTL2_ID0_RQ_E5 (0x1<<8) // ID based ordering request enable. + #define PCIEIP_REG_PCIEEP_DEV_CTL2_ID0_RQ_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_DEV_CTL2_ID0_CP_E5 (0x1<<9) // ID based ordering completion enable + #define PCIEIP_REG_PCIEEP_DEV_CTL2_ID0_CP_E5_SHIFT 9 + #define PCIEIP_REG_PCIEEP_DEV_CTL2_LTRE_E5 (0x1<<10) // Latency tolerance reporting (LTR) mechanism enable. Only R/W for function 0. Reserved for all other functions. + #define PCIEIP_REG_PCIEEP_DEV_CTL2_LTRE_E5_SHIFT 10 + #define PCIEIP_REG_PCIEEP_DEV_CTL2_TAG10B_REQ_EN_E5 (0x1<<12) // 10-bit tag requester enable. + #define PCIEIP_REG_PCIEEP_DEV_CTL2_TAG10B_REQ_EN_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_DEV_CTL2_OBFFE_E5 (0x3<<13) // Optimized buffer flush fill (OBFF) enabled. + #define PCIEIP_REG_PCIEEP_DEV_CTL2_OBFFE_E5_SHIFT 13 + #define PCIEIP_REG_PCIEEP_DEV_CTL2_EETPB_E5 (0x1<<15) // End-end TLP prefix blocking. + #define PCIEIP_REG_PCIEEP_DEV_CTL2_EETPB_E5_SHIFT 15 +#define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_K2 0x000098UL //Access:RW DataWidth:0x20 // Device Control 2 and Status 2 Register. + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_K2 (0xf<<0) // Completion Timeout Value. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_K2_SHIFT 0 + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_K2 (0x1<<4) // Completion Timeout Disable. + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_K2_SHIFT 4 + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_K2 (0x1<<5) // ARI Forwarding Enable. + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_K2_SHIFT 5 + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN_K2 (0x1<<6) // AtomicOp Requester Enable. + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN_K2_SHIFT 6 + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_K2 (0x1<<7) // AtomicOp Egress Blocking. + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_K2_SHIFT 7 + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_K2 (0x1<<8) // IDO Request Enable. + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_K2_SHIFT 8 + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN_K2 (0x1<<9) // IDO Completion Enable. + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN_K2_SHIFT 9 + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_K2 (0x1<<10) // LTR Mechanism Enable. The write value is gated with the PCIE_CAP_LTR_SUPP field of DEVICE_CAPABILITIES2_REG. Note: RW for function #0 and RsdvP for all other functions + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_K2_SHIFT 10 + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_OBFF_EN_K2 (0x3<<13) // OBFF Enable. Note: RW for function #0 and RsdvP for all other functions + #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_OBFF_EN_K2_SHIFT 13 +#define PCIEIP_REG_PCIEEP_LINK_CAP2_E5 0x00009cUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_LINK_CAP2_SLSV_E5 (0x7f<<1) // Supported link speeds vector. Indicates the supported link speeds of the associated port. For each bit, a value of 1 b indicates that the corresponding link speed is supported; otherwise, the link speed is not supported. Bit definitions are: _ Bit <1> = 2.5 GT/s. _ Bit <2> = 5.0 GT/s. _ Bit <3> = 8.0 GT/s. _ Bit <4> = 16.0 GT/s _ Bits <7:5> are reserved. + #define PCIEIP_REG_PCIEEP_LINK_CAP2_SLSV_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_LINK_CAP2_CLS_E5 (0x1<<8) // Crosslink supported. + #define PCIEIP_REG_PCIEEP_LINK_CAP2_CLS_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_LINK_CAP2_RTDS_E5 (0x1<<23) // Retimer presence detect supported. + #define PCIEIP_REG_PCIEEP_LINK_CAP2_RTDS_E5_SHIFT 23 + #define PCIEIP_REG_PCIEEP_LINK_CAP2_TRTDS_E5 (0x1<<24) // Two retimers presence detect supported. + #define PCIEIP_REG_PCIEEP_LINK_CAP2_TRTDS_E5_SHIFT 24 +#define PCIEIP_REG_LINK_CAPABILITIES2_REG_K2 0x00009cUL //Access:RW DataWidth:0x20 // Link Capabilities 2 Register. + #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_K2 (0x7f<<1) // Supported Link Speeds Vector. This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register. + #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_K2_SHIFT 1 + #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_K2 (0x1<<8) // Cross Link Supported. + #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_K2_SHIFT 8 + #define PCIEIP_REG_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_K2 (0x1<<31) // DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_K2_SHIFT 31 +#define PCIEIP_REG_PCIEEP_LINK_CTL2_E5 0x0000a0UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_LINK_CTL2_TLS_E5 (0xf<<0) // Target link speed. For downstream ports, this field sets an upper limit on link operational speed by restricting the values advertised by the upstream component in its training sequences: 0x1 = 2.5 Gb/s target link speed. 0x2 = 5 Gb/s target link speed. 0x3 = 8 Gb/s target link speed. 0x4 = 16 Gb/s target link speed. All other encodings are reserved. If a value is written to this field that does not correspond to a speed included in the supported link speeds field, the result is undefined. For both upstream and downstream ports, this field is used to set the target compliance mode speed when software is using the enter compliance bit to force a link into compliance mode. The reset value of this field is controlled by the value read from PEM()_CFG[MD]. _ MD is 0x0, reset to 0x1: 2.5 GHz supported. _ MD is 0x1, reset to 0x2: 5.0 GHz and 2.5 GHz supported. _ MD is 0x2, reset to 0x3: 8.0 GHz, 5.0 GHz and 2.5 GHz supported. _ MD is 0x3, reset to 0x3: 8.0 GHz, 5.0 GHz and 2.5 GHz supported (RC Mode). + #define PCIEIP_REG_PCIEEP_LINK_CTL2_TLS_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_EC_E5 (0x1<<4) // Enter compliance. Software is permitted to force a link to enter compliance mode at the speed indicated in the target link speed field by setting this bit to one in both components on a link and then initiating a hot reset on the link. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_EC_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_HASD_E5 (0x1<<5) // Hardware autonomous speed disable. When asserted, the application must disable hardware from changing the link speed for device-specific reasons other than attempting to correct unreliable link operation by reducing link speed. Initial transition to the highest supported common link speed is not blocked by this signal. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_HASD_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_SDE_E5 (0x1<<6) // Selectable deemphasis. Not applicable for an upstream port or endpoint device. Hardwired to 0. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_SDE_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_TM_E5 (0x7<<7) // Transmit margin. This field controls the value of the non-deemphasized voltage level at the transmitter pins: 0x0 = 800-1200 mV for full swing 400-600 mV for half-swing. 0x1-0x2 = Values must be monotonic with a nonzero slope. 0x3 = 200-400 mV for full-swing and 100-200 mV for half-swing. 0x4-0x7 = Reserved. This field is reset to 0x0 on entry to the LTSSM Polling.Compliance substate. When operating in 5.0 GT/s mode with full swing, the deemphasis ratio must be maintained within +/- 1 dB from the specification-defined operational value either -3.5 or -6 dB. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_TM_E5_SHIFT 7 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_EMC_E5 (0x1<<10) // Enter modified compliance. When this bit is set to one, the device transmits a modified compliance pattern if the LTSSM enters Polling.Compliance state. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_EMC_E5_SHIFT 10 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_CSOS_E5 (0x1<<11) // Compliance SOS. When set to one, the LTSSM is required to send SKP ordered sets periodically in between the (modified) compliance patterns. When the link is operating at 2.5 GT/s, the setting of this bit has no effect. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_CSOS_E5_SHIFT 11 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_CDE_E5 (0xf<<12) // Compliance deemphasis. This bit sets the deemphasis level in Polling.Compliance state if the entry occurred due to the TX compliance receive bit being one. 0x0 = -6 dB. 0x1 = -3.5 dB. When the link is operating at 2.5 GT/s, the setting of this bit has no effect. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_CDE_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_CDL_E5 (0x1<<16) // Current deemphasis level. When the link is operating at 5 GT/s speed, this bit reflects the level of deemphasis. 0 = -6 dB. 1 = -3.5 dB. The value in this bit is undefined when the link is operating at 2.5 GT/s speed. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_CDL_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_EQC_E5 (0x1<<17) // Equalization complete. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_EQC_E5_SHIFT 17 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_EP1S_E5 (0x1<<18) // Equalization phase 1 successful. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_EP1S_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_EP2S_E5 (0x1<<19) // Equalization phase 2 successful. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_EP2S_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_EP3S_E5 (0x1<<20) // Equalization phase 3 successful. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_EP3S_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_LER_E5 (0x1<<21) // Link equalization request. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_LER_E5_SHIFT 21 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_RTD_E5 (0x1<<22) // Retimer presence detected. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_RTD_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_TRTD_E5 (0x1<<23) // Two retimers presence detected. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_TRTD_E5_SHIFT 23 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_CLR_E5 (0x3<<24) // Crosslink resolution (not supported). + #define PCIEIP_REG_PCIEEP_LINK_CTL2_CLR_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_DCP_E5 (0x7<<28) // Downstream component presence. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_DCP_E5_SHIFT 28 + #define PCIEIP_REG_PCIEEP_LINK_CTL2_DRS_MR_E5 (0x1<<31) // DRS message received. + #define PCIEIP_REG_PCIEEP_LINK_CTL2_DRS_MR_E5_SHIFT 31 +#define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_K2 0x0000a0UL //Access:RW DataWidth:0x20 // Link Control 2 and Status 2 Register. + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_K2 (0xf<<0) // Target Link Speed. In M-PCIe mode, the contents of this field are derived from other registers. Note: This register field is sticky. + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_K2_SHIFT 0 + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_K2 (0x1<<4) // Enter Compliance Mode. Note: This register field is sticky. + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_K2_SHIFT 4 + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_K2 (0x1<<5) // Hardware Autonomous Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_K2_SHIFT 5 + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_K2 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. Note: This register field is sticky. + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_K2_SHIFT 6 + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_K2 (0x7<<7) // Controls Transmit Margin for Debug or Compliance. Note: This register field is sticky. + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_K2_SHIFT 7 + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_K2 (0x1<<10) // Enter Modified Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_K2_SHIFT 10 + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_K2 (0x1<<11) // Sets Compliance Skip Ordered Sets transmission. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_K2_SHIFT 11 + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_K2 (0xf<<12) // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_K2_SHIFT 12 + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_K2 (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is always 0x0. In C-PCIe mode, its contents are derived by sampling the PIPE + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_K2_SHIFT 16 + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_K2 (0x1<<17) // Equalization 8.0GT/s Complete. Note: This register field is sticky. + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_K2_SHIFT 17 + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_K2 (0x1<<18) // Equalization 8.0GT/s Phase 1 Successful. Note: This register field is sticky. + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_K2_SHIFT 18 + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_K2 (0x1<<19) // Equalization 8.0GT/s Phase 2 Successful. Note: This register field is sticky. + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_K2_SHIFT 19 + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_K2 (0x1<<20) // Equalization 8.0GT/s Phase 3 Successful. Note: This register field is sticky. + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_K2_SHIFT 20 + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_K2 (0x1<<21) // Link Equalization Request 8.0GT/s. + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_K2_SHIFT 21 + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_K2 (0x7<<28) // Downstream Component Presence. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0. + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_K2_SHIFT 28 + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_K2 (0x1<<31) // DRS Message Received. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0. + #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_K2_SHIFT 31 #define PCIEIP_REG_MSIX_CAP_BB 0x0000a0UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_MSIX_CAP_MSIX_CAP_ID_BB (0xff<<0) // Capability ID for MSIX Path = cfg_defs #define PCIEIP_REG_MSIX_CAP_MSIX_CAP_ID_BB_SHIFT 0 @@ -760,17 +1158,28 @@ #define PCIEIP_REG_PCIE_CAPABILITY_SLOT_IMPLEMENTED_BB_SHIFT 24 #define PCIEIP_REG_PCIE_CAPABILITY_MSG_NUM_BB (0x1f<<25) // Interrupt Message Number:indicate which MSI/MSI-X vector is used for the interrupt message generated in association with any of the status bits of this capability structure. For MSI, the value in this register indicates the offset between the base Message Data and the interrupt message that is generated. For MSI-X, the value in this register indicates which MSI-X Table entry is used to generate the interrupt message. The entry must be one of the first 32 entries even if the function implements more than 32 entries. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap #define PCIEIP_REG_PCIE_CAPABILITY_MSG_NUM_BB_SHIFT 25 -#define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_K2_E5 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next Pointer, Control Registers. - #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2_E5 (0xff<<0) // MSI-X Capability ID. - #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2_E5 (0xff<<8) // MSI-X Next Capability Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2_E5_SHIFT 8 - #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_K2_E5 (0x7ff<<16) // MSI-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PCI_MSIX_TABLE_SIZE field in VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG). To write this common value, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_SIZE field in the PF PCI_MSIX_CAP_ID_NEXT_CTRL_REG register. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_K2_E5_SHIFT 16 - #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_K2_E5 (0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_K2_E5_SHIFT 30 - #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_K2_E5 (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_K2_E5_SHIFT 31 +#define PCIEIP_REG_PCIEEP_MSIX_CAP_CNTRL_E5 0x0000b0UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MSIX_CAP_CNTRL_MSIXCID_E5 (0xff<<0) // MSI-X capability ID. + #define PCIEIP_REG_PCIEEP_MSIX_CAP_CNTRL_MSIXCID_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MSIX_CAP_CNTRL_NCP_E5 (0xff<<8) // Next capability pointer + #define PCIEIP_REG_PCIEEP_MSIX_CAP_CNTRL_NCP_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MSIX_CAP_CNTRL_MSIXTS_E5 (0x7ff<<16) // MSI-X table size encoded as (table size - 1). Writable through PEM()_CFG_WR. This field is writable by issuing a PEM()_CFG_WR to PCIEEP_MSIX_CAP_CNTRL when PEM()_CFG_WR[ADDR[16]] is set. + #define PCIEIP_REG_PCIEEP_MSIX_CAP_CNTRL_MSIXTS_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MSIX_CAP_CNTRL_FUNM_E5 (0x1<<30) // Function mask. 0 = Each vectors mask bit determines whether the vector is masked or not. 1 = All vectors associated with the function are masked, regardless of their respective per-vector mask bits. + #define PCIEIP_REG_PCIEEP_MSIX_CAP_CNTRL_FUNM_E5_SHIFT 30 + #define PCIEIP_REG_PCIEEP_MSIX_CAP_CNTRL_MSIXEN_E5 (0x1<<31) // MSI-X enable. If MSI-X is enabled, MSI and INTx must be disabled. + #define PCIEIP_REG_PCIEEP_MSIX_CAP_CNTRL_MSIXEN_E5_SHIFT 31 +#define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_K2 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next Pointer, Control Registers. + #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2 (0xff<<0) // MSI-X Capability ID. + #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2 (0xff<<8) // MSI-X Next Capability Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2_SHIFT 8 + #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_K2 (0x7ff<<16) // MSI-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PCI_MSIX_TABLE_SIZE field in VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG). To write this common value, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_SIZE field in the PF PCI_MSIX_CAP_ID_NEXT_CTRL_REG register. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_K2_SHIFT 16 + #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_K2 (0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_K2_SHIFT 30 + #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_K2 (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_K2_SHIFT 31 #define PCIEIP_REG_DEVICE_CAPABILITY_BB 0x0000b0UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_BB (0x7<<0) // Max Payload Size Supported. These bits are programmable from the register space and default value is based on define in version.v file. Path= i_cfg_func.i_cfg_private #define PCIEIP_REG_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_BB_SHIFT 0 @@ -794,11 +1203,16 @@ #define PCIEIP_REG_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_BB_SHIFT 26 #define PCIEIP_REG_DEVICE_CAPABILITY_FLR_CAP_SUPPORTED_BB (0x1<<28) // FLR capability is advertized when flr_supported bit in private device_capability register space is set. #define PCIEIP_REG_DEVICE_CAPABILITY_FLR_CAP_SUPPORTED_BB_SHIFT 28 -#define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_K2_E5 0x0000b4UL //Access:RW DataWidth:0x20 // MSI-X Table Offset and BIR Register. - #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_K2_E5 (0x7<<0) // MSI-X Table Bar Indicator Register Field. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_K2_E5_SHIFT 0 - #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_K2_E5 (0x1fffffff<<3) // MSI-X Table Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_K2_E5_SHIFT 3 +#define PCIEIP_REG_PCIEEP_MSIX_TABLE_E5 0x0000b4UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MSIX_TABLE_MSIXTBIR_E5 (0x7<<0) // MSI-X table BAR indicator register (BIR). Indicates which BAR is used to map the MSI-X table into memory space. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_MSIX_TABLE_MSIXTBIR_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MSIX_TABLE_MSIXTOFFS_E5 (0x1fffffff<<3) // MSI-X table offset register. Base address of the MSI-X table, as an offset from the base address of the BAR indicated by the table BIR bits. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_MSIX_TABLE_MSIXTOFFS_E5_SHIFT 3 +#define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_K2 0x0000b4UL //Access:RW DataWidth:0x20 // MSI-X Table Offset and BIR Register. + #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_K2 (0x7<<0) // MSI-X Table Bar Indicator Register Field. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_K2_SHIFT 0 + #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_K2 (0x1fffffff<<3) // MSI-X Table Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_K2_SHIFT 3 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_BB 0x0000b4UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_BB (0x1<<0) // Correctable Error Reporting Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap. #define PCIEIP_REG_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_BB_SHIFT 0 @@ -836,11 +1250,16 @@ #define PCIEIP_REG_DEVICE_STATUS_CONTROL_AUX_PWR_DET_BB_SHIFT 20 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_BB (0x1<<21) // This is bit is read back a 1, whenever a non-posted request initiated by PCIE core is pending to be completed. Path= i_tl_top #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_BB_SHIFT 21 -#define PCIEIP_REG_MSIX_PBA_OFFSET_REG_K2_E5 0x0000b8UL //Access:RW DataWidth:0x20 // MSI-X PBA Offset and BIR Register. - #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_K2_E5 (0x7<<0) // MSI-X PBA BIR. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_K2_E5_SHIFT 0 - #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_K2_E5 (0x1fffffff<<3) // MSI-X PBA Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_K2_E5_SHIFT 3 +#define PCIEIP_REG_PCIEEP_MSIX_PBA_E5 0x0000b8UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MSIX_PBA_MSIXPBIR_E5 (0x7<<0) // MSI-X PBA BAR indicator register (BIR). Indicates which BAR is used to map the MSI-X pending bit array into memory space. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_MSIX_PBA_MSIXPBIR_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MSIX_PBA_MSIXPOFFS_E5 (0x1fffffff<<3) // MSI-X table offset register. Base address of the MSI-X PBA, as an offset from the base address of the BAR indicated by the table PBA bits. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_MSIX_PBA_MSIXPOFFS_E5_SHIFT 3 +#define PCIEIP_REG_MSIX_PBA_OFFSET_REG_K2 0x0000b8UL //Access:RW DataWidth:0x20 // MSI-X PBA Offset and BIR Register. + #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_K2 (0x7<<0) // MSI-X PBA BIR. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_K2_SHIFT 0 + #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_K2 (0x1fffffff<<3) // MSI-X PBA Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_K2_SHIFT 3 #define PCIEIP_REG_LINK_CAPABILITY_BB 0x0000b8UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_LINK_CAPABILITY_MAX_LINK_SPEED_BB (0xf<<0) // Path= i_cfg_func.i_cfg_private Value used by internal logic is the smaller of the value programmed for each function #define PCIEIP_REG_LINK_CAPABILITY_MAX_LINK_SPEED_BB_SHIFT 0 @@ -923,15 +1342,24 @@ #define PCIEIP_REG_SLOT_CONTROL_STATUS_SLOT_STATUS_BB_SHIFT 23 #define PCIEIP_REG_ROOT_CAP_CONTROL_BB 0x0000c8UL //Access:R DataWidth:0x20 // For EP this register is not applicable and hardwired to 0. #define PCIEIP_REG_ROOT_STATUS_BB 0x0000ccUL //Access:R DataWidth:0x20 // For EP this register is not applicable and hardwired to 0. -#define PCIEIP_REG_VPD_BASE_K2_E5 0x0000d0UL //Access:RW DataWidth:0x20 // VPD Control and Capabilities Register. - #define PCIEIP_REG_VPD_BASE_VPD_PCIE_EXTENDED_CAP_ID_K2_E5 (0xff<<0) // VPD Extended Capability ID. - #define PCIEIP_REG_VPD_BASE_VPD_PCIE_EXTENDED_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_VPD_BASE_VPD_NEXT_OFFSET_K2_E5 (0xff<<8) // VPD Pointer to Next Capability. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_VPD_BASE_VPD_NEXT_OFFSET_K2_E5_SHIFT 8 - #define PCIEIP_REG_VPD_BASE_VPD_ADDRESS_K2_E5 (0x7fff<<16) // VPD Address. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_VPD_BASE_VPD_ADDRESS_K2_E5_SHIFT 16 - #define PCIEIP_REG_VPD_BASE_VPD_FLAG_K2_E5 (0x1<<31) // VPD Flag. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_VPD_BASE_VPD_FLAG_K2_E5_SHIFT 31 +#define PCIEIP_REG_PCIEEP_VPD_BASE_E5 0x0000d0UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_VPD_BASE_PCIEEC_E5 (0xff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_VPD_BASE_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_VPD_BASE_NCO_E5 (0xff<<8) // Next capability offset. End of list. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_VPD_BASE_NCO_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_VPD_BASE_ADDR_E5 (0x7fff<<16) // VPD address. + #define PCIEIP_REG_PCIEEP_VPD_BASE_ADDR_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_VPD_BASE_FLAG_E5 (0x1<<31) // VPD flag. + #define PCIEIP_REG_PCIEEP_VPD_BASE_FLAG_E5_SHIFT 31 +#define PCIEIP_REG_VPD_BASE_K2 0x0000d0UL //Access:RW DataWidth:0x20 // VPD Control and Capabilities Register. + #define PCIEIP_REG_VPD_BASE_VPD_PCIE_EXTENDED_CAP_ID_K2 (0xff<<0) // VPD Extended Capability ID. + #define PCIEIP_REG_VPD_BASE_VPD_PCIE_EXTENDED_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_VPD_BASE_VPD_NEXT_OFFSET_K2 (0xff<<8) // VPD Pointer to Next Capability. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_VPD_BASE_VPD_NEXT_OFFSET_K2_SHIFT 8 + #define PCIEIP_REG_VPD_BASE_VPD_ADDRESS_K2 (0x7fff<<16) // VPD Address. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_VPD_BASE_VPD_ADDRESS_K2_SHIFT 16 + #define PCIEIP_REG_VPD_BASE_VPD_FLAG_K2 (0x1<<31) // VPD Flag. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_VPD_BASE_VPD_FLAG_K2_SHIFT 31 #define PCIEIP_REG_DEVICE_CAPABILITY_2_BB 0x0000d0UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_BB (0xf<<0) // Completion Timeout Ranges Supported. Programmable through register space Path= i_cfg_func.i_cfg_private #define PCIEIP_REG_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_BB_SHIFT 0 @@ -947,7 +1375,8 @@ #define PCIEIP_REG_DEVICE_CAPABILITY_2_UNUSED1_BB_SHIFT 14 #define PCIEIP_REG_DEVICE_CAPABILITY_2_OBFF_SUPORTED_BB (0x3<<18) // OBFF Supported using WAKE# signaling only. Value is programmable through private register space in Device_cap2. #define PCIEIP_REG_DEVICE_CAPABILITY_2_OBFF_SUPORTED_BB_SHIFT 18 -#define PCIEIP_REG_DATA_REG_K2_E5 0x0000d4UL //Access:RW DataWidth:0x20 // VPD Data Register. +#define PCIEIP_REG_PCIEEP_VPD_DATA_E5 0x0000d4UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_DATA_REG_K2 0x0000d4UL //Access:RW DataWidth:0x20 // VPD Data Register. #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_BB 0x0000d4UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_BB (0xf<<0) // Completion timeout value. The spec specifies a range, the device uses the max value in the range. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_BB_SHIFT 0 @@ -1013,13 +1442,20 @@ #define PCIEIP_REG_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_BB_SHIFT 0 #define PCIEIP_REG_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_BB (0xffff<<16) // Not implemented #define PCIEIP_REG_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_BB_SHIFT 16 -#define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_K2_E5 0x000100UL //Access:RW DataWidth:0x20 // Advanced Error Reporting Extended Capability Header. - #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_CAP_ID_K2_E5 (0xffff<<0) // AER Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_CAP_VERSION_K2_E5 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_CAP_VERSION_K2_E5_SHIFT 16 - #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_K2_E5 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_K2_E5_SHIFT 20 +#define PCIEIP_REG_PCIEEP_EXT_CAP_E5 0x000100UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_EXT_CAP_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_EXT_CAP_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_EXT_CAP_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_EXT_CAP_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_EXT_CAP_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_EXT_CAP_NCO_E5_SHIFT 20 +#define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_K2 0x000100UL //Access:RW DataWidth:0x20 // Advanced Error Reporting Extended Capability Header. + #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_CAP_ID_K2 (0xffff<<0) // AER Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_CAP_VERSION_K2 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_CAP_VERSION_K2_SHIFT 16 + #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_K2 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_K2_SHIFT 20 #define PCIEIP_REG_ADV_ERR_CAP_BB 0x000100UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_ADV_ERR_CAP_ADV_ERR_CAP_ID_BB (0xffff<<0) // PCI Express Extended Capability ID. These bits are hardwired to 0001h indicating the presence of PCI Express Advanced Error Capability. Path= cfg_defs #define PCIEIP_REG_ADV_ERR_CAP_ADV_ERR_CAP_ID_BB_SHIFT 0 @@ -1027,33 +1463,64 @@ #define PCIEIP_REG_ADV_ERR_CAP_VER_BB_SHIFT 16 #define PCIEIP_REG_ADV_ERR_CAP_NEXT_BB (0xfff<<20) // Next Capabilities Pointer is 0x13C which is Power Budget. Path= i_cfg_func.i_cfg_public.i_cfg_ep_reg #define PCIEIP_REG_ADV_ERR_CAP_NEXT_BB_SHIFT 20 -#define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_K2_E5 0x000104UL //Access:RW DataWidth:0x20 // Uncorrectable Error Status Register. - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_K2_E5 (0x1<<4) // Data Link Protocol Error Status. - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_K2_E5_SHIFT 4 - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_SUR_DWN_ERR_STATUS_K2_E5 (0x1<<5) // Surprise Down Error Status (Optional). Note: Not supported. - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_SUR_DWN_ERR_STATUS_K2_E5_SHIFT 5 - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_K2_E5 (0x1<<12) // Poisoned TLP Status. - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_K2_E5_SHIFT 12 - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_K2_E5 (0x1<<13) // Flow Control Protocol Error Status. - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_K2_E5_SHIFT 13 - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_K2_E5 (0x1<<14) // Completion Timeout Status. - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_K2_E5_SHIFT 14 - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_K2_E5 (0x1<<15) // Completer Abort Status. - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_K2_E5_SHIFT 15 - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_K2_E5 (0x1<<16) // Unexpected Completion Status. - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_K2_E5_SHIFT 16 - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_K2_E5 (0x1<<17) // Receiver Overflow Status. - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_K2_E5_SHIFT 17 - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_K2_E5 (0x1<<18) // Malformed TLP Status. - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_K2_E5_SHIFT 18 - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_K2_E5 (0x1<<19) // ECRC Error Status. - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_K2_E5_SHIFT 19 - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_K2_E5 (0x1<<20) // Unsupported Request Error Status. - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_K2_E5_SHIFT 20 - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_K2_E5 (0x1<<22) // Uncorrectable Internal Error Status. The core sets this bit when your application asserts app_err_bus[9]. It does not set this bit when it detects internal uncorrectable internal errors such as parity and ECC failures. You should use the outputs from these errors to drive the app_err_bus[9] input. For more details, see the "Data Integrity (Wire, Datapath, and RAM Protection)" section in the Databook. - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_K2_E5_SHIFT 22 - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS_K2_E5 (0x1<<25) // TLP Prefix Blocked Error Status. Note: Not supported. - #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS_K2_E5_SHIFT 25 +#define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_E5 0x000104UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_DLPES_E5 (0x1<<4) // Data link protocol error status. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_DLPES_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_SDES_E5 (0x1<<5) // Surprise link down error status. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_SDES_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_PTLPS_E5 (0x1<<12) // Poisoned TLP status. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_PTLPS_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_FCPES_E5 (0x1<<13) // Flow control protocol error status. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_FCPES_E5_SHIFT 13 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_CTS_E5 (0x1<<14) // Completion timeout status. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_CTS_E5_SHIFT 14 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_CAS_E5 (0x1<<15) // Completer abort status. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_CAS_E5_SHIFT 15 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_UCS_E5 (0x1<<16) // Unexpected completion status. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_UCS_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_ROS_E5 (0x1<<17) // Receiver overflow status. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_ROS_E5_SHIFT 17 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_MTLPS_E5 (0x1<<18) // Malformed TLP status. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_MTLPS_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_ECRCES_E5 (0x1<<19) // ECRC error status. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_ECRCES_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_URES_E5 (0x1<<20) // Unsupported request error status. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_URES_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_AVS_E5 (0x1<<21) // ACS violation status. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_AVS_E5_SHIFT 21 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_UCIES_E5 (0x1<<22) // Uncorrectable internal error status. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_UCIES_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_UATOMBS_E5 (0x1<<24) // Unsupported AtomicOp egress blocked status. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_UATOMBS_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_TPBES_E5 (0x1<<25) // Unsupported TLP prefix blocked error status. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_STAT_TPBES_E5_SHIFT 25 +#define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_K2 0x000104UL //Access:RW DataWidth:0x20 // Uncorrectable Error Status Register. + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_K2 (0x1<<4) // Data Link Protocol Error Status. + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_K2_SHIFT 4 + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_SUR_DWN_ERR_STATUS_K2 (0x1<<5) // Surprise Down Error Status (Optional). Note: Not supported. + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_SUR_DWN_ERR_STATUS_K2_SHIFT 5 + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_K2 (0x1<<12) // Poisoned TLP Status. + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_K2_SHIFT 12 + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_K2 (0x1<<13) // Flow Control Protocol Error Status. + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_K2_SHIFT 13 + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_K2 (0x1<<14) // Completion Timeout Status. + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_K2_SHIFT 14 + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_K2 (0x1<<15) // Completer Abort Status. + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_K2_SHIFT 15 + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_K2 (0x1<<16) // Unexpected Completion Status. + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_K2_SHIFT 16 + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_K2 (0x1<<17) // Receiver Overflow Status. + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_K2_SHIFT 17 + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_K2 (0x1<<18) // Malformed TLP Status. + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_K2_SHIFT 18 + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_K2 (0x1<<19) // ECRC Error Status. + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_K2_SHIFT 19 + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_K2 (0x1<<20) // Unsupported Request Error Status. + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_K2_SHIFT 20 + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_K2 (0x1<<22) // Uncorrectable Internal Error Status. The core sets this bit when your application asserts app_err_bus[9]. It does not set this bit when it detects internal uncorrectable internal errors such as parity and ECC failures. You should use the outputs from these errors to drive the app_err_bus[9] input. For more details, see the "Data Integrity (Wire, Datapath, and RAM Protection)" section in the Databook. + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_K2_SHIFT 22 + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS_K2 (0x1<<25) // TLP Prefix Blocked Error Status. Note: Not supported. + #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS_K2_SHIFT 25 #define PCIEIP_REG_UC_ERR_STATUS_BB 0x000104UL //Access:RW DataWidth:0x20 // Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap #define PCIEIP_REG_UC_ERR_STATUS_UNUSED0_BB (0xf<<0) // #define PCIEIP_REG_UC_ERR_STATUS_UNUSED0_BB_SHIFT 0 @@ -1079,35 +1546,66 @@ #define PCIEIP_REG_UC_ERR_STATUS_ECRCS_BB_SHIFT 19 #define PCIEIP_REG_UC_ERR_STATUS_URES_BB (0x1<<20) // Unsupported Request Error Status. #define PCIEIP_REG_UC_ERR_STATUS_URES_BB_SHIFT 20 -#define PCIEIP_REG_UNCORR_ERR_MASK_OFF_K2_E5 0x000108UL //Access:RW DataWidth:0x20 // Uncorrectable Error Mask Register. - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_K2_E5 (0x1<<4) // Data Link Protocol Error Mask. Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_K2_E5_SHIFT 4 - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_SUR_DWN_ERR_MASK_K2_E5 (0x1<<5) // Surprise Down Error Mask. Note: Not supported. Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_SUR_DWN_ERR_MASK_K2_E5_SHIFT 5 - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_K2_E5 (0x1<<12) // Poisoned TLP Error Mask. Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_K2_E5_SHIFT 12 - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_K2_E5 (0x1<<13) // Flow Control Protocol Error Mask. Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_K2_E5_SHIFT 13 - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_K2_E5 (0x1<<14) // Completion Timeout Error Mask. Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_K2_E5_SHIFT 14 - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_K2_E5 (0x1<<15) // Completer Abort Error Mask (Optional). Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_K2_E5_SHIFT 15 - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_K2_E5 (0x1<<16) // Unexpected Completion Mask. Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_K2_E5_SHIFT 16 - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_K2_E5 (0x1<<17) // Receiver Overflow Mask (Optional). Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_K2_E5_SHIFT 17 - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_K2_E5 (0x1<<18) // Malformed TLP Mask. Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_K2_E5_SHIFT 18 - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_K2_E5 (0x1<<19) // ECRC Error Mask (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_K2_E5_SHIFT 19 - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_K2_E5 (0x1<<20) // Unsupported Request Error Mask. Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_K2_E5_SHIFT 20 - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_K2_E5 (0x1<<22) // Uncorrectable Internal Error Mask (Optional). Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_K2_E5_SHIFT 22 - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_K2_E5 (0x1<<24) // AtomicOp Egress Block Mask (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_K2_E5_SHIFT 24 - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_K2_E5 (0x1<<25) // TLP Prefix Blocked Error Mask. Note: Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_K2_E5_SHIFT 25 +#define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_E5 0x000108UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_DLPEM_E5 (0x1<<4) // Data link protocol error mask. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_DLPEM_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_SDEM_E5 (0x1<<5) // Surprise down error mask. Set to 0 for endpoint devices. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_SDEM_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_PTLPM_E5 (0x1<<12) // Poisoned TLP mask. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_PTLPM_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_FCPEM_E5 (0x1<<13) // Flow control protocol error mask. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_FCPEM_E5_SHIFT 13 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_CTM_E5 (0x1<<14) // Completion timeout mask. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_CTM_E5_SHIFT 14 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_CAM_E5 (0x1<<15) // Completer abort mask. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_CAM_E5_SHIFT 15 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_UCM_E5 (0x1<<16) // Unexpected completion mask. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_UCM_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_ROM_E5 (0x1<<17) // Receiver overflow mask. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_ROM_E5_SHIFT 17 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_MTLPM_E5 (0x1<<18) // Malformed TLP mask. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_MTLPM_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_ECRCEM_E5 (0x1<<19) // ECRC error mask. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_ECRCEM_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_UREM_E5 (0x1<<20) // Unsupported request error mask. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_UREM_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_ACSVM_E5 (0x1<<21) // ACS violation mask. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_ACSVM_E5_SHIFT 21 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_UCIEM_E5 (0x1<<22) // Uncorrectable internal error mask. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_UCIEM_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_UATOMBM_E5 (0x1<<24) // Unsupported AtomicOp egress blocked mask. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_UATOMBM_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_TPBEM_E5 (0x1<<25) // TLP prefix blocked error mask. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_MSK_TPBEM_E5_SHIFT 25 +#define PCIEIP_REG_UNCORR_ERR_MASK_OFF_K2 0x000108UL //Access:RW DataWidth:0x20 // Uncorrectable Error Mask Register. + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_K2 (0x1<<4) // Data Link Protocol Error Mask. Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_K2_SHIFT 4 + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_SUR_DWN_ERR_MASK_K2 (0x1<<5) // Surprise Down Error Mask. Note: Not supported. Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_SUR_DWN_ERR_MASK_K2_SHIFT 5 + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_K2 (0x1<<12) // Poisoned TLP Error Mask. Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_K2_SHIFT 12 + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_K2 (0x1<<13) // Flow Control Protocol Error Mask. Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_K2_SHIFT 13 + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_K2 (0x1<<14) // Completion Timeout Error Mask. Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_K2_SHIFT 14 + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_K2 (0x1<<15) // Completer Abort Error Mask (Optional). Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_K2_SHIFT 15 + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_K2 (0x1<<16) // Unexpected Completion Mask. Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_K2_SHIFT 16 + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_K2 (0x1<<17) // Receiver Overflow Mask (Optional). Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_K2_SHIFT 17 + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_K2 (0x1<<18) // Malformed TLP Mask. Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_K2_SHIFT 18 + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_K2 (0x1<<19) // ECRC Error Mask (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_K2_SHIFT 19 + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_K2 (0x1<<20) // Unsupported Request Error Mask. Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_K2_SHIFT 20 + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_K2 (0x1<<22) // Uncorrectable Internal Error Mask (Optional). Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_K2_SHIFT 22 + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_K2 (0x1<<24) // AtomicOp Egress Block Mask (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_K2_SHIFT 24 + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_K2 (0x1<<25) // TLP Prefix Blocked Error Mask. Note: Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_K2_SHIFT 25 #define PCIEIP_REG_UCORR_ERR_MASK_BB 0x000108UL //Access:RW DataWidth:0x20 // Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap #define PCIEIP_REG_UCORR_ERR_MASK_UNUSED0_BB (0xf<<0) // #define PCIEIP_REG_UCORR_ERR_MASK_UNUSED0_BB_SHIFT 0 @@ -1135,35 +1633,68 @@ #define PCIEIP_REG_UCORR_ERR_MASK_ECRCEM_BB_SHIFT 19 #define PCIEIP_REG_UCORR_ERR_MASK_UREM_BB (0x1<<20) // Unsupported Request Error Mask. #define PCIEIP_REG_UCORR_ERR_MASK_UREM_BB_SHIFT 20 -#define PCIEIP_REG_UNCORR_ERR_SEV_OFF_K2_E5 0x00010cUL //Access:RW DataWidth:0x20 // Uncorrectable Error Severity Register. - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_K2_E5 (0x1<<4) // Data Link Protocol Error Severity. Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_K2_E5_SHIFT 4 - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_SUR_DWN_ERR_SEVERITY_K2_E5 (0x1<<5) // Surprise Down Error Severity (Optional). Note: Not supported. Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_SUR_DWN_ERR_SEVERITY_K2_E5_SHIFT 5 - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_K2_E5 (0x1<<12) // Poisoned TLP Severity. Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_K2_E5_SHIFT 12 - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_K2_E5 (0x1<<13) // Flow Control Protocol Error Severity (Optional). Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_K2_E5_SHIFT 13 - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_K2_E5 (0x1<<14) // Completion Timeout Error Severity. Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_K2_E5_SHIFT 14 - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_K2_E5 (0x1<<15) // Completer Abort Error Severity (Optional). Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_K2_E5_SHIFT 15 - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_K2_E5 (0x1<<16) // Unexpected Completion Error Severity. Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_K2_E5_SHIFT 16 - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_K2_E5 (0x1<<17) // Receiver Overflow Error Severity (Optional). Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_K2_E5_SHIFT 17 - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_K2_E5 (0x1<<18) // Malformed TLP Severity. Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_K2_E5_SHIFT 18 - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_K2_E5 (0x1<<19) // ECRC Error Severity (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_K2_E5_SHIFT 19 - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_K2_E5 (0x1<<20) // Unsupported Request Error Severity. Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_K2_E5_SHIFT 20 - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_K2_E5 (0x1<<22) // Uncorrectable Internal Error Severity (Optional). Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_K2_E5_SHIFT 22 - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_K2_E5 (0x1<<24) // AtomicOp Egress Blocked Severity (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_K2_E5_SHIFT 24 - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_K2_E5 (0x1<<25) // TLP Prefix Blocked Error Severity (Optional). Note: Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_K2_E5_SHIFT 25 +#define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_E5 0x00010cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_DLPES_E5 (0x1<<4) // Data link protocol error severity. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_DLPES_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_SDES_E5 (0x1<<5) // Surprise down error severity. Set to 1 for endpoint devices. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_SDES_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_PTLPS_E5 (0x1<<12) // Poisoned TLP severity. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_PTLPS_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_FCPES_E5 (0x1<<13) // Flow control protocol error severity. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_FCPES_E5_SHIFT 13 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_CTS_E5 (0x1<<14) // Completion timeout severity. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_CTS_E5_SHIFT 14 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_CAS_E5 (0x1<<15) // Completer abort severity. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_CAS_E5_SHIFT 15 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_UCS_E5 (0x1<<16) // Unexpected completion severity. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_UCS_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_ROS_E5 (0x1<<17) // Receiver overflow severity. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_ROS_E5_SHIFT 17 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_MTLPS_E5 (0x1<<18) // Malformed TLP severity. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_MTLPS_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_ECRCES_E5 (0x1<<19) // ECRC error severity. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_ECRCES_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_URES_E5 (0x1<<20) // Unsupported request error severity. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_URES_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_AVS_E5 (0x1<<21) // AVCS violation severity. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_AVS_E5_SHIFT 21 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_UCIES_E5 (0x1<<22) // Uncorrectable internal error severity. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_UCIES_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_RESERVED_23_23_E5 (0x1<<23) // Reserved. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_RESERVED_23_23_E5_SHIFT 23 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_UATOMBS_E5 (0x1<<24) // Unsupported AtomicOp egress blocked severity. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_UATOMBS_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_TPBES_E5 (0x1<<25) // TLP prefix blocked error severity. + #define PCIEIP_REG_PCIEEP_UCOR_ERR_SEV_TPBES_E5_SHIFT 25 +#define PCIEIP_REG_UNCORR_ERR_SEV_OFF_K2 0x00010cUL //Access:RW DataWidth:0x20 // Uncorrectable Error Severity Register. + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_K2 (0x1<<4) // Data Link Protocol Error Severity. Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_K2_SHIFT 4 + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_SUR_DWN_ERR_SEVERITY_K2 (0x1<<5) // Surprise Down Error Severity (Optional). Note: Not supported. Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_SUR_DWN_ERR_SEVERITY_K2_SHIFT 5 + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_K2 (0x1<<12) // Poisoned TLP Severity. Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_K2_SHIFT 12 + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_K2 (0x1<<13) // Flow Control Protocol Error Severity (Optional). Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_K2_SHIFT 13 + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_K2 (0x1<<14) // Completion Timeout Error Severity. Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_K2_SHIFT 14 + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_K2 (0x1<<15) // Completer Abort Error Severity (Optional). Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_K2_SHIFT 15 + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_K2 (0x1<<16) // Unexpected Completion Error Severity. Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_K2_SHIFT 16 + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_K2 (0x1<<17) // Receiver Overflow Error Severity (Optional). Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_K2_SHIFT 17 + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_K2 (0x1<<18) // Malformed TLP Severity. Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_K2_SHIFT 18 + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_K2 (0x1<<19) // ECRC Error Severity (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_K2_SHIFT 19 + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_K2 (0x1<<20) // Unsupported Request Error Severity. Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_K2_SHIFT 20 + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_K2 (0x1<<22) // Uncorrectable Internal Error Severity (Optional). Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_K2_SHIFT 22 + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_K2 (0x1<<24) // AtomicOp Egress Blocked Severity (Optional). Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_K2_SHIFT 24 + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_K2 (0x1<<25) // TLP Prefix Blocked Error Severity (Optional). Note: Not supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_K2_SHIFT 25 #define PCIEIP_REG_UCORR_ERR_SEVR_BB 0x00010cUL //Access:RW DataWidth:0x20 // Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap #define PCIEIP_REG_UCORR_ERR_SEVR_UNUSED0_BB (0xf<<0) // #define PCIEIP_REG_UCORR_ERR_SEVR_UNUSED0_BB_SHIFT 0 @@ -1191,23 +1722,40 @@ #define PCIEIP_REG_UCORR_ERR_SEVR_ECRCES_BB_SHIFT 19 #define PCIEIP_REG_UCORR_ERR_SEVR_URES_BB (0x1<<20) // Unsupported Request Error Severity. #define PCIEIP_REG_UCORR_ERR_SEVR_URES_BB_SHIFT 20 -#define PCIEIP_REG_CORR_ERR_STATUS_OFF_K2_E5 0x000110UL //Access:RW DataWidth:0x20 // Correctable Error Status Register. - #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_K2_E5 (0x1<<0) // Receiver Error Status (Optional). - #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_K2_E5_SHIFT 0 - #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_K2_E5 (0x1<<6) // Bad TLP Status. - #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_K2_E5_SHIFT 6 - #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_K2_E5 (0x1<<7) // Bad DLLP Status. - #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_K2_E5_SHIFT 7 - #define PCIEIP_REG_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_K2_E5 (0x1<<8) // REPLAY_NUM Rollover Status. - #define PCIEIP_REG_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_K2_E5_SHIFT 8 - #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_K2_E5 (0x1<<12) // Replay Timer Timeout Status. - #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_K2_E5_SHIFT 12 - #define PCIEIP_REG_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_K2_E5 (0x1<<13) // Advisory Non-Fatal Error Status. - #define PCIEIP_REG_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_K2_E5_SHIFT 13 - #define PCIEIP_REG_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_K2_E5 (0x1<<14) // Corrected Internal Error Status (Optional). - #define PCIEIP_REG_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_K2_E5_SHIFT 14 - #define PCIEIP_REG_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_K2_E5 (0x1<<15) // Header Log Overflow Error Status (Optional). - #define PCIEIP_REG_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_K2_E5_SHIFT 15 +#define PCIEIP_REG_PCIEEP_COR_ERR_STAT_E5 0x000110UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_COR_ERR_STAT_RES_E5 (0x1<<0) // Receiver error status. + #define PCIEIP_REG_PCIEEP_COR_ERR_STAT_RES_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_COR_ERR_STAT_BTLPS_E5 (0x1<<6) // Bad TLP status. + #define PCIEIP_REG_PCIEEP_COR_ERR_STAT_BTLPS_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_COR_ERR_STAT_BDLLPS_E5 (0x1<<7) // Bad DLLP status. + #define PCIEIP_REG_PCIEEP_COR_ERR_STAT_BDLLPS_E5_SHIFT 7 + #define PCIEIP_REG_PCIEEP_COR_ERR_STAT_RNRS_E5 (0x1<<8) // REPLAY_NUM rollover status. + #define PCIEIP_REG_PCIEEP_COR_ERR_STAT_RNRS_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_COR_ERR_STAT_RTTS_E5 (0x1<<12) // Replay timer timeout status. + #define PCIEIP_REG_PCIEEP_COR_ERR_STAT_RTTS_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_COR_ERR_STAT_ANFES_E5 (0x1<<13) // Advisory nonfatal error status. + #define PCIEIP_REG_PCIEEP_COR_ERR_STAT_ANFES_E5_SHIFT 13 + #define PCIEIP_REG_PCIEEP_COR_ERR_STAT_CIES_E5 (0x1<<14) // Corrected internal error status. + #define PCIEIP_REG_PCIEEP_COR_ERR_STAT_CIES_E5_SHIFT 14 + #define PCIEIP_REG_PCIEEP_COR_ERR_STAT_CHLO_E5 (0x1<<15) // Corrected header log overflow status. + #define PCIEIP_REG_PCIEEP_COR_ERR_STAT_CHLO_E5_SHIFT 15 +#define PCIEIP_REG_CORR_ERR_STATUS_OFF_K2 0x000110UL //Access:RW DataWidth:0x20 // Correctable Error Status Register. + #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_K2 (0x1<<0) // Receiver Error Status (Optional). + #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_K2_SHIFT 0 + #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_K2 (0x1<<6) // Bad TLP Status. + #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_K2_SHIFT 6 + #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_K2 (0x1<<7) // Bad DLLP Status. + #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_K2_SHIFT 7 + #define PCIEIP_REG_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_K2 (0x1<<8) // REPLAY_NUM Rollover Status. + #define PCIEIP_REG_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_K2_SHIFT 8 + #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_K2 (0x1<<12) // Replay Timer Timeout Status. + #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_K2_SHIFT 12 + #define PCIEIP_REG_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_K2 (0x1<<13) // Advisory Non-Fatal Error Status. + #define PCIEIP_REG_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_K2_SHIFT 13 + #define PCIEIP_REG_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_K2 (0x1<<14) // Corrected Internal Error Status (Optional). + #define PCIEIP_REG_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_K2_SHIFT 14 + #define PCIEIP_REG_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_K2 (0x1<<15) // Header Log Overflow Error Status (Optional). + #define PCIEIP_REG_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_K2_SHIFT 15 #define PCIEIP_REG_CORR_ERR_STATUS_BB 0x000110UL //Access:RW DataWidth:0x20 // Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap #define PCIEIP_REG_CORR_ERR_STATUS_RX_ERR_STATUS_BB (0x1<<0) // Receiver Error Status. #define PCIEIP_REG_CORR_ERR_STATUS_RX_ERR_STATUS_BB_SHIFT 0 @@ -1225,23 +1773,40 @@ #define PCIEIP_REG_CORR_ERR_STATUS_RPLAY_TMR_TO_STATUS_BB_SHIFT 12 #define PCIEIP_REG_CORR_ERR_STATUS_ADVSRY_ERR_STATUS_BB (0x1<<13) // Advisory Non fatal Error Status. Only set if role_based_err_rpt is asserted. #define PCIEIP_REG_CORR_ERR_STATUS_ADVSRY_ERR_STATUS_BB_SHIFT 13 -#define PCIEIP_REG_CORR_ERR_MASK_OFF_K2_E5 0x000114UL //Access:RW DataWidth:0x20 // Correctable Error Mask Register. - #define PCIEIP_REG_CORR_ERR_MASK_OFF_RX_ERR_MASK_K2_E5 (0x1<<0) // Receiver Error Mask (Optional). Note: This register field is sticky. - #define PCIEIP_REG_CORR_ERR_MASK_OFF_RX_ERR_MASK_K2_E5_SHIFT 0 - #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_TLP_MASK_K2_E5 (0x1<<6) // Bad TLP Mask. Note: This register field is sticky. - #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_TLP_MASK_K2_E5_SHIFT 6 - #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_K2_E5 (0x1<<7) // Bad DLLP Mask. Note: This register field is sticky. - #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_K2_E5_SHIFT 7 - #define PCIEIP_REG_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_K2_E5 (0x1<<8) // REPLAY_NUM Rollover Mask. Note: This register field is sticky. - #define PCIEIP_REG_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_K2_E5_SHIFT 8 - #define PCIEIP_REG_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_K2_E5 (0x1<<12) // Replay Timer Timeout Mask. Note: This register field is sticky. - #define PCIEIP_REG_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_K2_E5_SHIFT 12 - #define PCIEIP_REG_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_K2_E5 (0x1<<13) // Advisory Non-Fatal Error Mask. Note: This register field is sticky. - #define PCIEIP_REG_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_K2_E5_SHIFT 13 - #define PCIEIP_REG_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_K2_E5 (0x1<<14) // Corrected Internal Error Mask (Optional). Note: This register field is sticky. - #define PCIEIP_REG_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_K2_E5_SHIFT 14 - #define PCIEIP_REG_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_K2_E5 (0x1<<15) // Header Log Overflow Error Mask (Optional). Note: This register field is sticky. - #define PCIEIP_REG_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_K2_E5_SHIFT 15 +#define PCIEIP_REG_PCIEEP_COR_ERR_MSK_E5 0x000114UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_COR_ERR_MSK_REM_E5 (0x1<<0) // Receiver error mask. + #define PCIEIP_REG_PCIEEP_COR_ERR_MSK_REM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_COR_ERR_MSK_BTLPM_E5 (0x1<<6) // Bad TLP mask. + #define PCIEIP_REG_PCIEEP_COR_ERR_MSK_BTLPM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_COR_ERR_MSK_BDLLPM_E5 (0x1<<7) // Bad DLLP mask. + #define PCIEIP_REG_PCIEEP_COR_ERR_MSK_BDLLPM_E5_SHIFT 7 + #define PCIEIP_REG_PCIEEP_COR_ERR_MSK_RNRM_E5 (0x1<<8) // REPLAY_NUM rollover mask. + #define PCIEIP_REG_PCIEEP_COR_ERR_MSK_RNRM_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_COR_ERR_MSK_RTTM_E5 (0x1<<12) // Replay timer timeout mask. + #define PCIEIP_REG_PCIEEP_COR_ERR_MSK_RTTM_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_COR_ERR_MSK_ANFEM_E5 (0x1<<13) // Advisory nonfatal error mask. + #define PCIEIP_REG_PCIEEP_COR_ERR_MSK_ANFEM_E5_SHIFT 13 + #define PCIEIP_REG_PCIEEP_COR_ERR_MSK_CIEM_E5 (0x1<<14) // Corrected internal error mask. + #define PCIEIP_REG_PCIEEP_COR_ERR_MSK_CIEM_E5_SHIFT 14 + #define PCIEIP_REG_PCIEEP_COR_ERR_MSK_CHLOM_E5 (0x1<<15) // Corrected header log overflow error mask. + #define PCIEIP_REG_PCIEEP_COR_ERR_MSK_CHLOM_E5_SHIFT 15 +#define PCIEIP_REG_CORR_ERR_MASK_OFF_K2 0x000114UL //Access:RW DataWidth:0x20 // Correctable Error Mask Register. + #define PCIEIP_REG_CORR_ERR_MASK_OFF_RX_ERR_MASK_K2 (0x1<<0) // Receiver Error Mask (Optional). Note: This register field is sticky. + #define PCIEIP_REG_CORR_ERR_MASK_OFF_RX_ERR_MASK_K2_SHIFT 0 + #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_TLP_MASK_K2 (0x1<<6) // Bad TLP Mask. Note: This register field is sticky. + #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_TLP_MASK_K2_SHIFT 6 + #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_K2 (0x1<<7) // Bad DLLP Mask. Note: This register field is sticky. + #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_K2_SHIFT 7 + #define PCIEIP_REG_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_K2 (0x1<<8) // REPLAY_NUM Rollover Mask. Note: This register field is sticky. + #define PCIEIP_REG_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_K2_SHIFT 8 + #define PCIEIP_REG_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_K2 (0x1<<12) // Replay Timer Timeout Mask. Note: This register field is sticky. + #define PCIEIP_REG_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_K2_SHIFT 12 + #define PCIEIP_REG_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_K2 (0x1<<13) // Advisory Non-Fatal Error Mask. Note: This register field is sticky. + #define PCIEIP_REG_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_K2_SHIFT 13 + #define PCIEIP_REG_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_K2 (0x1<<14) // Corrected Internal Error Mask (Optional). Note: This register field is sticky. + #define PCIEIP_REG_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_K2_SHIFT 14 + #define PCIEIP_REG_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_K2 (0x1<<15) // Header Log Overflow Error Mask (Optional). Note: This register field is sticky. + #define PCIEIP_REG_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_K2_SHIFT 15 #define PCIEIP_REG_CORR_ERR_MASK_BB 0x000114UL //Access:RW DataWidth:0x20 // Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap #define PCIEIP_REG_CORR_ERR_MASK_RES_BB (0x1<<0) // Receiver Error Mask. #define PCIEIP_REG_CORR_ERR_MASK_RES_BB_SHIFT 0 @@ -1259,21 +1824,38 @@ #define PCIEIP_REG_CORR_ERR_MASK_RTTS_BB_SHIFT 12 #define PCIEIP_REG_CORR_ERR_MASK_ANFM_BB (0x1<<13) // Advisory Non fatal Error Mask #define PCIEIP_REG_CORR_ERR_MASK_ANFM_BB_SHIFT 13 -#define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_K2_E5 0x000118UL //Access:RW DataWidth:0x20 // Advanced Error Capabilities and Control Register. - #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_K2_E5 (0x1f<<0) // First Error Pointer. Note: This register field is sticky. - #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_K2_E5_SHIFT 0 - #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_K2_E5 (0x1<<5) // ECRC Generation Capable. Note: This register field is sticky. - #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_K2_E5_SHIFT 5 - #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_K2_E5 (0x1<<6) // ECRC Generation Enable. Note: This register field is sticky. - #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_K2_E5_SHIFT 6 - #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_K2_E5 (0x1<<7) // ECRC Check Capable. Note: This register field is sticky. - #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_K2_E5_SHIFT 7 - #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_K2_E5 (0x1<<8) // ECRC Check Enable. Note: This register field is sticky. - #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_K2_E5_SHIFT 8 - #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_K2_E5 (0x1<<9) // Multiple Header Recording Capable. Note: This register field is sticky. - #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_K2_E5_SHIFT 9 - #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_K2_E5 (0x1<<10) // Multiple Header Recording Enable. Note: This register field is sticky. - #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_K2_E5_SHIFT 10 +#define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_E5 0x000118UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_FEP_E5 (0x1f<<0) // First error pointer. + #define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_FEP_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_GC_E5 (0x1<<5) // ECRC generation capability. + #define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_GC_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_GE_E5 (0x1<<6) // ECRC generation enable. + #define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_GE_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_CC_E5 (0x1<<7) // ECRC check capable. + #define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_CC_E5_SHIFT 7 + #define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_CE_E5 (0x1<<8) // ECRC check enable. + #define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_CE_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_MULT_HDR_CAP_E5 (0x1<<9) // Multiple header recording capability (not supported). + #define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_MULT_HDR_CAP_E5_SHIFT 9 + #define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_MULT_HDR_EN_E5 (0x1<<10) // Multiple header recording enable (not supported). + #define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_MULT_HDR_EN_E5_SHIFT 10 + #define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_TLP_PLP_E5 (0x1<<11) // TLP prefix log present. + #define PCIEIP_REG_PCIEEP_ADV_ERR_CAP_CNTRL_TLP_PLP_E5_SHIFT 11 +#define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_K2 0x000118UL //Access:RW DataWidth:0x20 // Advanced Error Capabilities and Control Register. + #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_K2 (0x1f<<0) // First Error Pointer. Note: This register field is sticky. + #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_K2_SHIFT 0 + #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_K2 (0x1<<5) // ECRC Generation Capable. Note: This register field is sticky. + #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_K2_SHIFT 5 + #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_K2 (0x1<<6) // ECRC Generation Enable. Note: This register field is sticky. + #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_K2_SHIFT 6 + #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_K2 (0x1<<7) // ECRC Check Capable. Note: This register field is sticky. + #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_K2_SHIFT 7 + #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_K2 (0x1<<8) // ECRC Check Enable. Note: This register field is sticky. + #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_K2_SHIFT 8 + #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_K2 (0x1<<9) // Multiple Header Recording Capable. Note: This register field is sticky. + #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_K2_SHIFT 9 + #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_K2 (0x1<<10) // Multiple Header Recording Enable. Note: This register field is sticky. + #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_K2_SHIFT 10 #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_BB 0x000118UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_FIRST_UERR_PTR_BB (0x1f<<0) // First Error Pointer - These bits correspond to the bit position in which the first error occurred. #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_FIRST_UERR_PTR_BB_SHIFT 0 @@ -1285,67 +1867,73 @@ #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCCAP_BB_SHIFT 7 #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCEN_BB (0x1<<8) // ECRC Check Enable #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCEN_BB_SHIFT 8 -#define PCIEIP_REG_HDR_LOG_0_OFF_K2_E5 0x00011cUL //Access:R DataWidth:0x20 // Header Log Register 0. - #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_K2_E5 (0xff<<0) // Byte 0 of Header log register of First 32 bit Data Word. Note: This register field is sticky. - #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_K2_E5_SHIFT 0 - #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_K2_E5 (0xff<<8) // Byte 1 of Header log register of First 32 bit Data Word. Note: This register field is sticky. - #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_K2_E5_SHIFT 8 - #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_K2_E5 (0xff<<16) // Byte 2 of Header log register of First 32 bit Data Word. Note: This register field is sticky. - #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_K2_E5_SHIFT 16 - #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_K2_E5 (0xff<<24) // Byte 3 of Header log register of First 32 bit Data Word. Note: This register field is sticky. - #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_K2_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_HDR_LOG1_E5 0x00011cUL //Access:R DataWidth:0x20 // The header log registers collect the header for the TLP corresponding to a detected error. +#define PCIEIP_REG_HDR_LOG_0_OFF_K2 0x00011cUL //Access:R DataWidth:0x20 // Header Log Register 0. + #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_K2 (0xff<<0) // Byte 0 of Header log register of First 32 bit Data Word. Note: This register field is sticky. + #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_K2_SHIFT 0 + #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_K2 (0xff<<8) // Byte 1 of Header log register of First 32 bit Data Word. Note: This register field is sticky. + #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_K2_SHIFT 8 + #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_K2 (0xff<<16) // Byte 2 of Header log register of First 32 bit Data Word. Note: This register field is sticky. + #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_K2_SHIFT 16 + #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_K2 (0xff<<24) // Byte 3 of Header log register of First 32 bit Data Word. Note: This register field is sticky. + #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_K2_SHIFT 24 #define PCIEIP_REG_HEADER_LOG1_BB 0x00011cUL //Access:R DataWidth:0x20 // Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap -#define PCIEIP_REG_HDR_LOG_1_OFF_K2_E5 0x000120UL //Access:R DataWidth:0x20 // Header Log Register 1. - #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_K2_E5 (0xff<<0) // Byte 0 of Header log register of Second 32 bit Data Word. Note: This register field is sticky. - #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_K2_E5_SHIFT 0 - #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_K2_E5 (0xff<<8) // Byte 1 of Header log register of Second 32 bit Data Word. Note: This register field is sticky. - #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_K2_E5_SHIFT 8 - #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_K2_E5 (0xff<<16) // Byte 2 of Header log register of Second 32 bit Data Word. Note: This register field is sticky. - #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_K2_E5_SHIFT 16 - #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_K2_E5 (0xff<<24) // Byte 3 of Header log register of Second 32 bit Data Word. Note: This register field is sticky. - #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_K2_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_HDR_LOG2_E5 0x000120UL //Access:R DataWidth:0x20 // The header log registers collect the header for the TLP corresponding to a detected error. +#define PCIEIP_REG_HDR_LOG_1_OFF_K2 0x000120UL //Access:R DataWidth:0x20 // Header Log Register 1. + #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_K2 (0xff<<0) // Byte 0 of Header log register of Second 32 bit Data Word. Note: This register field is sticky. + #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_K2_SHIFT 0 + #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_K2 (0xff<<8) // Byte 1 of Header log register of Second 32 bit Data Word. Note: This register field is sticky. + #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_K2_SHIFT 8 + #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_K2 (0xff<<16) // Byte 2 of Header log register of Second 32 bit Data Word. Note: This register field is sticky. + #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_K2_SHIFT 16 + #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_K2 (0xff<<24) // Byte 3 of Header log register of Second 32 bit Data Word. Note: This register field is sticky. + #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_K2_SHIFT 24 #define PCIEIP_REG_HEADER_LOG2_BB 0x000120UL //Access:R DataWidth:0x20 // Second DW of TLP header associated with Error. Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap -#define PCIEIP_REG_HDR_LOG_2_OFF_K2_E5 0x000124UL //Access:R DataWidth:0x20 // Header Log Register 2. - #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_K2_E5 (0xff<<0) // Byte 0 of Header log register of Third 32 bit Data Word. Note: This register field is sticky. - #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_K2_E5_SHIFT 0 - #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_K2_E5 (0xff<<8) // Byte 1 of Header log register of Third 32 bit Data Word. Note: This register field is sticky. - #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_K2_E5_SHIFT 8 - #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_K2_E5 (0xff<<16) // Byte 2 of Header log register of Third 32 bit Data Word. Note: This register field is sticky. - #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_K2_E5_SHIFT 16 - #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_K2_E5 (0xff<<24) // Byte 3 of Header log register of Third 32 bit Data Word. Note: This register field is sticky. - #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_K2_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_HDR_LOG3_E5 0x000124UL //Access:R DataWidth:0x20 // The header log registers collect the header for the TLP corresponding to a detected error. +#define PCIEIP_REG_HDR_LOG_2_OFF_K2 0x000124UL //Access:R DataWidth:0x20 // Header Log Register 2. + #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_K2 (0xff<<0) // Byte 0 of Header log register of Third 32 bit Data Word. Note: This register field is sticky. + #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_K2_SHIFT 0 + #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_K2 (0xff<<8) // Byte 1 of Header log register of Third 32 bit Data Word. Note: This register field is sticky. + #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_K2_SHIFT 8 + #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_K2 (0xff<<16) // Byte 2 of Header log register of Third 32 bit Data Word. Note: This register field is sticky. + #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_K2_SHIFT 16 + #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_K2 (0xff<<24) // Byte 3 of Header log register of Third 32 bit Data Word. Note: This register field is sticky. + #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_K2_SHIFT 24 #define PCIEIP_REG_HEADER_LOG3_BB 0x000124UL //Access:R DataWidth:0x20 // Third DW of TLP header associated with Error. Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap -#define PCIEIP_REG_HDR_LOG_3_OFF_K2_E5 0x000128UL //Access:R DataWidth:0x20 // Header Log Register 3. - #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_K2_E5 (0xff<<0) // Byte 0 of Header log register of Fourth 32 bit Data Word. Note: This register field is sticky. - #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_K2_E5_SHIFT 0 - #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_K2_E5 (0xff<<8) // Byte 1 of Header log register of Fourth 32 bit Data Word. Note: This register field is sticky. - #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_K2_E5_SHIFT 8 - #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_K2_E5 (0xff<<16) // Byte 2 of Header log register of Fourth 32 bit Data Word. Note: This register field is sticky. - #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_K2_E5_SHIFT 16 - #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_K2_E5 (0xff<<24) // Byte 3 of Header log register of Fourth 32 bit Data Word. Note: This register field is sticky. - #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_K2_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_HDR_LOG4_E5 0x000128UL //Access:R DataWidth:0x20 // The header log registers collect the header for the TLP corresponding to a detected error. +#define PCIEIP_REG_HDR_LOG_3_OFF_K2 0x000128UL //Access:R DataWidth:0x20 // Header Log Register 3. + #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_K2 (0xff<<0) // Byte 0 of Header log register of Fourth 32 bit Data Word. Note: This register field is sticky. + #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_K2_SHIFT 0 + #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_K2 (0xff<<8) // Byte 1 of Header log register of Fourth 32 bit Data Word. Note: This register field is sticky. + #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_K2_SHIFT 8 + #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_K2 (0xff<<16) // Byte 2 of Header log register of Fourth 32 bit Data Word. Note: This register field is sticky. + #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_K2_SHIFT 16 + #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_K2 (0xff<<24) // Byte 3 of Header log register of Fourth 32 bit Data Word. Note: This register field is sticky. + #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_K2_SHIFT 24 #define PCIEIP_REG_HEADER_LOG4_BB 0x000128UL //Access:R DataWidth:0x20 // Fourth DW of TLP header associated with Error. Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap #define PCIEIP_REG_ROOT_ERROR_COMMAND_BB 0x00012cUL //Access:R DataWidth:0x20 // For EP this register is not applicable and hardwired to 0. #define PCIEIP_REG_ROOT_ERROR_STATUS_BB 0x000130UL //Access:R DataWidth:0x20 // For EP this register is not applicable and hardwired to 0. #define PCIEIP_REG_ROOT_ERR_ID_BB 0x000134UL //Access:R DataWidth:0x20 // For EP this register is not applicable and hardwired to 0. -#define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_K2_E5 0x000138UL //Access:R DataWidth:0x20 // TLP Prefix Log Register 1. - #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_K2_E5 (0xff<<0) // Byte 0 of Error TLP Prefix Log 1. Note: This register field is sticky. - #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_K2_E5_SHIFT 0 - #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_K2_E5 (0xff<<8) // Byte 1 of Error TLP Prefix Log 1. Note: This register field is sticky. - #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_K2_E5_SHIFT 8 - #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_K2_E5 (0xff<<16) // Byte 2 of Error TLP Prefix Log 1. Note: This register field is sticky. - #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_K2_E5_SHIFT 16 - #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_K2_E5 (0xff<<24) // Byte 3 of Error TLP Prefix Log 1. Note: This register field is sticky. - #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_K2_E5_SHIFT 24 -#define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_K2_E5 0x00013cUL //Access:R DataWidth:0x20 // TLP Prefix Log Register 2. - #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_K2_E5 (0xff<<0) // Byte 0 Error TLP Prefix Log 2. Note: This register field is sticky. - #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_K2_E5_SHIFT 0 - #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_K2_E5 (0xff<<8) // Byte 1 Error TLP Prefix Log 2. Note: This register field is sticky. - #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_K2_E5_SHIFT 8 - #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_K2_E5 (0xff<<16) // Byte 2 Error TLP Prefix Log 2. Note: This register field is sticky. - #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_K2_E5_SHIFT 16 - #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_K2_E5 (0xff<<24) // Byte 3 Error TLP Prefix Log 2. Note: This register field is sticky. - #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_K2_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_TLP_PLOG1_E5 0x000138UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_K2 0x000138UL //Access:R DataWidth:0x20 // TLP Prefix Log Register 1. + #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_K2 (0xff<<0) // Byte 0 of Error TLP Prefix Log 1. Note: This register field is sticky. + #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_K2_SHIFT 0 + #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_K2 (0xff<<8) // Byte 1 of Error TLP Prefix Log 1. Note: This register field is sticky. + #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_K2_SHIFT 8 + #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_K2 (0xff<<16) // Byte 2 of Error TLP Prefix Log 1. Note: This register field is sticky. + #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_K2_SHIFT 16 + #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_K2 (0xff<<24) // Byte 3 of Error TLP Prefix Log 1. Note: This register field is sticky. + #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_K2_SHIFT 24 +#define PCIEIP_REG_PCIEEP_TLP_PLOG2_E5 0x00013cUL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_K2 0x00013cUL //Access:R DataWidth:0x20 // TLP Prefix Log Register 2. + #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_K2 (0xff<<0) // Byte 0 Error TLP Prefix Log 2. Note: This register field is sticky. + #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_K2_SHIFT 0 + #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_K2 (0xff<<8) // Byte 1 Error TLP Prefix Log 2. Note: This register field is sticky. + #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_K2_SHIFT 8 + #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_K2 (0xff<<16) // Byte 2 Error TLP Prefix Log 2. Note: This register field is sticky. + #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_K2_SHIFT 16 + #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_K2 (0xff<<24) // Byte 3 Error TLP Prefix Log 2. Note: This register field is sticky. + #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_K2_SHIFT 24 #define PCIEIP_REG_DEVICE_SER_NUM_CAP_BB 0x00013cUL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_DEVICE_SER_NUM_CAP_DEVICE_SER_NUM_CAP_ID_BB (0xffff<<0) // Device Serial Number Extended Capability ID. These bits are programmable through register space. Path = i_cfg_func.i_cfg_private #define PCIEIP_REG_DEVICE_SER_NUM_CAP_DEVICE_SER_NUM_CAP_ID_BB_SHIFT 0 @@ -1353,47 +1941,58 @@ #define PCIEIP_REG_DEVICE_SER_NUM_CAP_VER_BB_SHIFT 16 #define PCIEIP_REG_DEVICE_SER_NUM_CAP_NEXT_BB (0xfff<<20) // Next Capabilities Pointer. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg #define PCIEIP_REG_DEVICE_SER_NUM_CAP_NEXT_BB_SHIFT 20 -#define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_K2_E5 0x000140UL //Access:R DataWidth:0x20 // TLP Prefix Log Register 3. - #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_K2_E5 (0xff<<0) // Byte 0 Error TLP Prefix Log 3. Note: This register field is sticky. - #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_K2_E5_SHIFT 0 - #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_K2_E5 (0xff<<8) // Byte 1 Error TLP Prefix Log 3. Note: This register field is sticky. - #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_K2_E5_SHIFT 8 - #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_K2_E5 (0xff<<16) // Byte 2 Error TLP Prefix Log 3. Note: This register field is sticky. - #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_K2_E5_SHIFT 16 - #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_K2_E5 (0xff<<24) // Byte 3 Error TLP Prefix Log 3. Note: This register field is sticky. - #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_K2_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_TLP_PLOG3_E5 0x000140UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_K2 0x000140UL //Access:R DataWidth:0x20 // TLP Prefix Log Register 3. + #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_K2 (0xff<<0) // Byte 0 Error TLP Prefix Log 3. Note: This register field is sticky. + #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_K2_SHIFT 0 + #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_K2 (0xff<<8) // Byte 1 Error TLP Prefix Log 3. Note: This register field is sticky. + #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_K2_SHIFT 8 + #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_K2 (0xff<<16) // Byte 2 Error TLP Prefix Log 3. Note: This register field is sticky. + #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_K2_SHIFT 16 + #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_K2 (0xff<<24) // Byte 3 Error TLP Prefix Log 3. Note: This register field is sticky. + #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_K2_SHIFT 24 #define PCIEIP_REG_LOWER_SER_NUM_BB 0x000140UL //Access:R DataWidth:0x20 // This register has the PCIE Device Serial Number bits [31:0]. This register will contain the data written in the Device Serial Number Access Lower Register (Offset 504h). Path = i_cfg_func.i_cfg_private -#define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_K2_E5 0x000144UL //Access:R DataWidth:0x20 // TLP Prefix Log Register 4. - #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_K2_E5 (0xff<<0) // Byte 0 Error TLP Prefix Log 4. Note: This register field is sticky. - #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_K2_E5_SHIFT 0 - #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_K2_E5 (0xff<<8) // Byte 1 Error TLP Prefix Log 4. Note: This register field is sticky. - #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_K2_E5_SHIFT 8 - #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_K2_E5 (0xff<<16) // Byte 2 Error TLP Prefix Log 4. Note: This register field is sticky. - #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_K2_E5_SHIFT 16 - #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_K2_E5 (0xff<<24) // Byte 3 Error TLP Prefix Log 4. Note: This register field is sticky. - #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_K2_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_TLP_PLOG4_E5 0x000144UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_K2 0x000144UL //Access:R DataWidth:0x20 // TLP Prefix Log Register 4. + #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_K2 (0xff<<0) // Byte 0 Error TLP Prefix Log 4. Note: This register field is sticky. + #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_K2_SHIFT 0 + #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_K2 (0xff<<8) // Byte 1 Error TLP Prefix Log 4. Note: This register field is sticky. + #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_K2_SHIFT 8 + #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_K2 (0xff<<16) // Byte 2 Error TLP Prefix Log 4. Note: This register field is sticky. + #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_K2_SHIFT 16 + #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_K2 (0xff<<24) // Byte 3 Error TLP Prefix Log 4. Note: This register field is sticky. + #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_K2_SHIFT 24 #define PCIEIP_REG_UPPER_SER_NUM_BB 0x000144UL //Access:R DataWidth:0x20 // This register has the PCIE Device Serial Number bits [63:32]. This register will contain the data written in the Device Serial Number Access Upper Register (Offset 508h). Path = i_cfg_func.i_cfg_private -#define PCIEIP_REG_VC_BASE_K2_E5 0x000148UL //Access:RW DataWidth:0x20 // VC Extended Capability Header. - #define PCIEIP_REG_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_K2_E5 (0xffff<<0) // VC Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_VC_BASE_VC_CAP_VERSION_K2_E5 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_VC_BASE_VC_CAP_VERSION_K2_E5_SHIFT 16 - #define PCIEIP_REG_VC_BASE_VC_NEXT_OFFSET_K2_E5 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_VC_BASE_VC_NEXT_OFFSET_K2_E5_SHIFT 20 -#define PCIEIP_REG_VC_CAPABILITIES_REG_1_K2_E5 0x00014cUL //Access:RW DataWidth:0x20 // Port VC Capability Register 1. - #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_K2_E5 (0x7<<0) // Extended VC Count. - #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_K2_E5_SHIFT 0 - #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_K2_E5 (0x7<<4) // Low Priority Extended VC Count. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_K2_E5_SHIFT 4 - #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_K2_E5 (0x3<<8) // Reference Clock. - #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_K2_E5_SHIFT 8 - #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_K2_E5 (0x3<<10) // Port Arbitration Table Entry Size. - #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_K2_E5_SHIFT 10 -#define PCIEIP_REG_VC_CAPABILITIES_REG_2_K2_E5 0x000150UL //Access:RW DataWidth:0x20 // Port VC Capability Register 2. - #define PCIEIP_REG_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_K2_E5 (0xf<<0) // VC Arbitration Capability. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_K2_E5_SHIFT 0 - #define PCIEIP_REG_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_K2_E5 (0xff<<24) // VC Arbitration Table Offset. - #define PCIEIP_REG_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_K2_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_SN_BASE_E5 0x000148UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_SN_BASE_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_SN_BASE_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_SN_BASE_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_SN_BASE_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_SN_BASE_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_SN_BASE_NCO_E5_SHIFT 20 +#define PCIEIP_REG_VC_BASE_K2 0x000148UL //Access:RW DataWidth:0x20 // VC Extended Capability Header. + #define PCIEIP_REG_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_K2 (0xffff<<0) // VC Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_VC_BASE_VC_CAP_VERSION_K2 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_VC_BASE_VC_CAP_VERSION_K2_SHIFT 16 + #define PCIEIP_REG_VC_BASE_VC_NEXT_OFFSET_K2 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_VC_BASE_VC_NEXT_OFFSET_K2_SHIFT 20 +#define PCIEIP_REG_PCIEEP_SN_DW1_E5 0x00014cUL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_VC_CAPABILITIES_REG_1_K2 0x00014cUL //Access:RW DataWidth:0x20 // Port VC Capability Register 1. + #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_K2 (0x7<<0) // Extended VC Count. + #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_K2_SHIFT 0 + #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_K2 (0x7<<4) // Low Priority Extended VC Count. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_K2_SHIFT 4 + #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_K2 (0x3<<8) // Reference Clock. + #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_K2_SHIFT 8 + #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_K2 (0x3<<10) // Port Arbitration Table Entry Size. + #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_K2_SHIFT 10 +#define PCIEIP_REG_PCIEEP_SN_DW2_E5 0x000150UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_VC_CAPABILITIES_REG_2_K2 0x000150UL //Access:RW DataWidth:0x20 // Port VC Capability Register 2. + #define PCIEIP_REG_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_K2 (0xf<<0) // VC Arbitration Capability. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_K2_SHIFT 0 + #define PCIEIP_REG_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_K2 (0xff<<24) // VC Arbitration Table Offset. + #define PCIEIP_REG_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_K2_SHIFT 24 #define PCIEIP_REG_PWR_BDGT_CAP_BB 0x000150UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_PWR_BDGT_CAP_PWR_BDGT_CAP_ID_BB (0xffff<<0) // Power Budgeting Extended Capability ID. Hardwired to 4. Path = cfg_defs #define PCIEIP_REG_PWR_BDGT_CAP_PWR_BDGT_CAP_ID_BB_SHIFT 0 @@ -1401,25 +2000,32 @@ #define PCIEIP_REG_PWR_BDGT_CAP_VER_BB_SHIFT 16 #define PCIEIP_REG_PWR_BDGT_CAP_NEXT_BB (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. The read-only value of this register is controlled by the EXT_CAP_ENA register in the PCI register space. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg #define PCIEIP_REG_PWR_BDGT_CAP_NEXT_BB_SHIFT 20 -#define PCIEIP_REG_VC_STATUS_CONTROL_REG_K2_E5 0x000154UL //Access:RW DataWidth:0x20 // Port VC Control and Status Register. - #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_K2_E5 (0x1<<0) // Requests Hardware to Load VC Arbitration Table. - #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_K2_E5_SHIFT 0 - #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_K2_E5 (0x7<<1) // VC Arbitration Select. - #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_K2_E5_SHIFT 1 - #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_K2_E5 (0x1<<16) // VC Arbitration Table Status. - #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_K2_E5_SHIFT 16 +#define PCIEIP_REG_VC_STATUS_CONTROL_REG_K2 0x000154UL //Access:RW DataWidth:0x20 // Port VC Control and Status Register. + #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_K2 (0x1<<0) // Requests Hardware to Load VC Arbitration Table. + #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_K2_SHIFT 0 + #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_K2 (0x7<<1) // VC Arbitration Select. + #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_K2_SHIFT 1 + #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_K2 (0x1<<16) // VC Arbitration Table Status. + #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_K2_SHIFT 16 #define PCIEIP_REG_PWR_BDGT_DATA_SEL_BB 0x000154UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_PWR_BDGT_DATA_SEL_DS_VALUE_BB (0xff<<0) // This value selects the value visible in the pb_dr. Path = i_cfg_func.i_cfg_public.i_cfg_pw_budget_cap #define PCIEIP_REG_PWR_BDGT_DATA_SEL_DS_VALUE_BB_SHIFT 0 -#define PCIEIP_REG_RESOURCE_CAP_REG_VC0_K2_E5 0x000158UL //Access:R DataWidth:0x20 // VC Resource Capability Register (0). - #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_K2_E5 (0xff<<0) // Port Arbitration Capability. - #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_K2_E5_SHIFT 0 - #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_K2_E5 (0x1<<15) // Reject Snoop Transactions. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_K2_E5_SHIFT 15 - #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_K2_E5 (0x3f<<16) // Maximum Time Slots-1 supported. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_K2_E5_SHIFT 16 - #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_K2_E5 (0xff<<24) // Port Arbitration Table Offset. - #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_K2_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_PB_BASE_E5 0x000158UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PB_BASE_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PB_BASE_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PB_BASE_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PB_BASE_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_PB_BASE_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PB_BASE_NCO_E5_SHIFT 20 +#define PCIEIP_REG_RESOURCE_CAP_REG_VC0_K2 0x000158UL //Access:R DataWidth:0x20 // VC Resource Capability Register (0). + #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_K2 (0xff<<0) // Port Arbitration Capability. + #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_K2_SHIFT 0 + #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_K2 (0x1<<15) // Reject Snoop Transactions. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_K2_SHIFT 15 + #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_K2 (0x3f<<16) // Maximum Time Slots-1 supported. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_K2_SHIFT 16 + #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_K2 (0xff<<24) // Port Arbitration Table Offset. + #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_K2_SHIFT 24 #define PCIEIP_REG_PWR_BDGT_DATA_BB 0x000158UL //Access:R DataWidth:0x20 // This register provides the power budgeting data for the entry number specified by the pwr_bdgt_data_sel register. The data present in this register is selected from one of the POWER BUDGET DATA ACCESS Registers from offset 510h through 52Ch, based on the value written in Power Budget Data Select register. The field definitions for each selected value are the same. Path = i_cfg_func.i_cfg_public.i_cfg_pw_budget_cap #define PCIEIP_REG_PWR_BDGT_DATA_BASE_PWR_BB (0xff<<0) // Base Power #define PCIEIP_REG_PWR_BDGT_DATA_BASE_PWR_BB_SHIFT 0 @@ -1433,27 +2039,43 @@ #define PCIEIP_REG_PWR_BDGT_DATA_TYPE_BB_SHIFT 15 #define PCIEIP_REG_PWR_BDGT_DATA_RAIL_BB (0x7<<18) // Power rail #define PCIEIP_REG_PWR_BDGT_DATA_RAIL_BB_SHIFT 18 -#define PCIEIP_REG_RESOURCE_CON_REG_VC0_K2_E5 0x00015cUL //Access:RW DataWidth:0x20 // VC Resource Control Register (0). - #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_K2_E5 (0x1<<0) // Bit 0 of TC to VC Mapping. - #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_K2_E5_SHIFT 0 - #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_K2_E5 (0x7f<<1) // Bits 7:1 of TC to VC Mapping. - #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_K2_E5_SHIFT 1 - #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_K2_E5 (0x1<<16) // Load Port Arbitration Table. - #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_K2_E5_SHIFT 16 - #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_K2_E5 (0x1<<17) // Port Arbitration Select. - #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_K2_E5_SHIFT 17 - #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ID_VC_K2_E5 (0x7<<24) // VC ID. - #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ID_VC_K2_E5_SHIFT 24 - #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_K2_E5 (0x1<<31) // VC Enable. - #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_K2_E5_SHIFT 31 +#define PCIEIP_REG_PCIEEP_PB_DATA_SEL_E5 0x00015cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PB_DATA_SEL_PB_DATA_SEL_E5 (0xff<<0) // Data select register. + #define PCIEIP_REG_PCIEEP_PB_DATA_SEL_PB_DATA_SEL_E5_SHIFT 0 +#define PCIEIP_REG_RESOURCE_CON_REG_VC0_K2 0x00015cUL //Access:RW DataWidth:0x20 // VC Resource Control Register (0). + #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_K2 (0x1<<0) // Bit 0 of TC to VC Mapping. + #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_K2_SHIFT 0 + #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_K2 (0x7f<<1) // Bits 7:1 of TC to VC Mapping. + #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_K2_SHIFT 1 + #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_K2 (0x1<<16) // Load Port Arbitration Table. + #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_K2_SHIFT 16 + #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_K2 (0x1<<17) // Port Arbitration Select. + #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_K2_SHIFT 17 + #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ID_VC_K2 (0x7<<24) // VC ID. + #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ID_VC_K2_SHIFT 24 + #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_K2 (0x1<<31) // VC Enable. + #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_K2_SHIFT 31 #define PCIEIP_REG_PWR_BDGT_CAPABILITY_BB 0x00015cUL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_PWR_BDGT_CAPABILITY_PCIE_CFG_PB_CAP_SYS_ALLOC_BB (0x1<<0) // The "System Allocated" bit when set indicates that the power budget for the device is included within the system power budget. Reported Power Budgeting Data for this device should be ignored by software for power budgeting decisions if this bit is set. This register is Read Only. The value can be written indirectly by writing into Power Budget Capability Register (0x550[0]) Path = i_cfg_func.i_cfg_private #define PCIEIP_REG_PWR_BDGT_CAPABILITY_PCIE_CFG_PB_CAP_SYS_ALLOC_BB_SHIFT 0 -#define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_K2_E5 0x000160UL //Access:R DataWidth:0x20 // VC Resource Status Register (0). - #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_K2_E5 (0x1<<16) // Port Arbitration Table Status. - #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_K2_E5_SHIFT 16 - #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_K2_E5 (0x1<<17) // VC Negotiation Pending. - #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_K2_E5_SHIFT 17 +#define PCIEIP_REG_PCIEEP_PB_DATA_E5 0x000160UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PB_DATA_BP_E5 (0xff<<0) // Base power. + #define PCIEIP_REG_PCIEEP_PB_DATA_BP_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PB_DATA_DS_E5 (0x3<<8) // Data scale. + #define PCIEIP_REG_PCIEEP_PB_DATA_DS_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_PB_DATA_PSS_E5 (0x7<<10) // PM substate. + #define PCIEIP_REG_PCIEEP_PB_DATA_PSS_E5_SHIFT 10 + #define PCIEIP_REG_PCIEEP_PB_DATA_PS_E5 (0x3<<13) // PM state. + #define PCIEIP_REG_PCIEEP_PB_DATA_PS_E5_SHIFT 13 + #define PCIEIP_REG_PCIEEP_PB_DATA_TYP_E5 (0x7<<15) // Type of operating condition. + #define PCIEIP_REG_PCIEEP_PB_DATA_TYP_E5_SHIFT 15 + #define PCIEIP_REG_PCIEEP_PB_DATA_PRS_E5 (0x7<<18) // Power rail state. + #define PCIEIP_REG_PCIEEP_PB_DATA_PRS_E5_SHIFT 18 +#define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_K2 0x000160UL //Access:R DataWidth:0x20 // VC Resource Status Register (0). + #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_K2 (0x1<<16) // Port Arbitration Table Status. + #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_K2_SHIFT 16 + #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_K2 (0x1<<17) // VC Negotiation Pending. + #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_K2_SHIFT 17 #define PCIEIP_REG_VC_CAP_BB 0x000160UL //Access:R DataWidth:0x20 // The read-back value of this register is controlled by the EXT_CAP_ENA register in the PCI register space. #define PCIEIP_REG_VC_CAP_VC_CAP_ID_BB (0xffff<<0) // Virtual channel Capability ID. Hardwired to 2. Path = cfg_defs #define PCIEIP_REG_VC_CAP_VC_CAP_ID_BB_SHIFT 0 @@ -1461,22 +2083,45 @@ #define PCIEIP_REG_VC_CAP_VC_CAP_VER_BB_SHIFT 16 #define PCIEIP_REG_VC_CAP_VC_NEXT_CAP_OFF_BB (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg #define PCIEIP_REG_VC_CAP_VC_NEXT_CAP_OFF_BB_SHIFT 20 +#define PCIEIP_REG_PCIEEP_PB_CAP_E5 0x000164UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PB_CAP_PB_SYS_ALLOC_E5 (0x1<<0) // System allocated PB. + #define PCIEIP_REG_PCIEEP_PB_CAP_PB_SYS_ALLOC_E5_SHIFT 0 #define PCIEIP_REG_PORT_VC_CAPABILITY_BB 0x000164UL //Access:R DataWidth:0x20 // Not implemented. -#define PCIEIP_REG_SN_BASE_K2_E5 0x000168UL //Access:RW DataWidth:0x20 // Device Serial Number Extended Capability Header. - #define PCIEIP_REG_SN_BASE_SN_PCIE_EXTENDED_CAP_ID_K2_E5 (0xffff<<0) // Serial Number Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_SN_BASE_SN_PCIE_EXTENDED_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_SN_BASE_SN_CAP_VERSION_K2_E5 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_SN_BASE_SN_CAP_VERSION_K2_E5_SHIFT 16 - #define PCIEIP_REG_SN_BASE_SN_NEXT_OFFSET_K2_E5 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_SN_BASE_SN_NEXT_OFFSET_K2_E5_SHIFT 20 +#define PCIEIP_REG_PCIEEP_ARI_CAP_HDR_E5 0x000168UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_ARI_CAP_HDR_ARIID_E5 (0xffff<<0) // PCI Express extended capability. + #define PCIEIP_REG_PCIEEP_ARI_CAP_HDR_ARIID_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_ARI_CAP_HDR_CV_E5 (0xf<<16) // Capability version. + #define PCIEIP_REG_PCIEEP_ARI_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_ARI_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Points to the secondary PCI Express capabilities by default. + #define PCIEIP_REG_PCIEEP_ARI_CAP_HDR_NCO_E5_SHIFT 20 +#define PCIEIP_REG_SN_BASE_K2 0x000168UL //Access:RW DataWidth:0x20 // Device Serial Number Extended Capability Header. + #define PCIEIP_REG_SN_BASE_SN_PCIE_EXTENDED_CAP_ID_K2 (0xffff<<0) // Serial Number Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_SN_BASE_SN_PCIE_EXTENDED_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_SN_BASE_SN_CAP_VERSION_K2 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_SN_BASE_SN_CAP_VERSION_K2_SHIFT 16 + #define PCIEIP_REG_SN_BASE_SN_NEXT_OFFSET_K2 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_SN_BASE_SN_NEXT_OFFSET_K2_SHIFT 20 #define PCIEIP_REG_PORT_VC_CAPABILITY2_BB 0x000168UL //Access:R DataWidth:0x20 // Not implemented. -#define PCIEIP_REG_SER_NUM_REG_DW_1_K2_E5 0x00016cUL //Access:RW DataWidth:0x20 // Serial Number 1 Register. +#define PCIEIP_REG_PCIEEP_ARI_CAP_CTL_E5 0x00016cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_ARI_CAP_CTL_MFVCFGC_E5 (0x1<<0) // MFVC function groups capability. + #define PCIEIP_REG_PCIEEP_ARI_CAP_CTL_MFVCFGC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_ARI_CAP_CTL_ACSFGC_E5 (0x1<<1) // ACS function groups capability. + #define PCIEIP_REG_PCIEEP_ARI_CAP_CTL_ACSFGC_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_ARI_CAP_CTL_NFN_E5 (0xff<<8) // Next function number. + #define PCIEIP_REG_PCIEEP_ARI_CAP_CTL_NFN_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_ARI_CAP_CTL_MFVCFGE_E5 (0x1<<16) // MFVC function groups enable (M). + #define PCIEIP_REG_PCIEEP_ARI_CAP_CTL_MFVCFGE_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_ARI_CAP_CTL_ACSFGE_E5 (0x1<<17) // ACS function groups enable (A). Writable only for Physical Func Num 0. + #define PCIEIP_REG_PCIEEP_ARI_CAP_CTL_ACSFGE_E5_SHIFT 17 + #define PCIEIP_REG_PCIEEP_ARI_CAP_CTL_FG_E5 (0x7<<20) // Function group. + #define PCIEIP_REG_PCIEEP_ARI_CAP_CTL_FG_E5_SHIFT 20 +#define PCIEIP_REG_SER_NUM_REG_DW_1_K2 0x00016cUL //Access:RW DataWidth:0x20 // Serial Number 1 Register. #define PCIEIP_REG_PORT_VC_STATUS_CONTROL_BB 0x00016cUL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_PORT_VC_STATUS_CONTROL_PORT_VC_CONTROL_BB (0xffff<<0) // Not implemented. #define PCIEIP_REG_PORT_VC_STATUS_CONTROL_PORT_VC_CONTROL_BB_SHIFT 0 #define PCIEIP_REG_PORT_VC_STATUS_CONTROL_PORT_VC_STATUS_BB (0xffff<<16) // Not implemented. #define PCIEIP_REG_PORT_VC_STATUS_CONTROL_PORT_VC_STATUS_BB_SHIFT 16 -#define PCIEIP_REG_SER_NUM_REG_DW_2_K2_E5 0x000170UL //Access:RW DataWidth:0x20 // Serial Number 2 Register. +#define PCIEIP_REG_SER_NUM_REG_DW_2_K2 0x000170UL //Access:RW DataWidth:0x20 // Serial Number 2 Register. #define PCIEIP_REG_PORT_ARB_TABLE_BB 0x000170UL //Access:R DataWidth:0x20 // Not implemented. #define PCIEIP_REG_VC_RSRC_CONTROL_BB 0x000174UL //Access:RW DataWidth:0x20 // The read-back value of this register is controlled by the EXT_CAP_ENA register in the PCI register space. #define PCIEIP_REG_VC_RSRC_CONTROL_DEFAULT_VC0_BB (0x1<<0) // This bit is hardwired to one because DUT is only support VC0. Path = i_cfg_func.i_cfg_public.i_cfg_vc_cap @@ -1487,34 +2132,49 @@ #define PCIEIP_REG_VC_RSRC_CONTROL_UNUSED0_BB_SHIFT 8 #define PCIEIP_REG_VC_RSRC_CONTROL_VC_ENABLE_BB (0x1<<31) // Enables virtual channel. This bit is hardwired to 1 for the default VC0 and writing to this filed has no effect. Path = i_cfg_func.i_cfg_public.i_cfg_vc_cap #define PCIEIP_REG_VC_RSRC_CONTROL_VC_ENABLE_BB_SHIFT 31 -#define PCIEIP_REG_PB_BASE_K2_E5 0x000178UL //Access:RW DataWidth:0x20 // Power Budgeting Extended Capability Header. - #define PCIEIP_REG_PB_BASE_PB_PCIE_EXTENDED_CAP_ID_K2_E5 (0xffff<<0) // PB Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_PB_BASE_PB_PCIE_EXTENDED_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_PB_BASE_PB_CAP_VERSION_K2_E5 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_PB_BASE_PB_CAP_VERSION_K2_E5_SHIFT 16 - #define PCIEIP_REG_PB_BASE_PB_NEXT_OFFSET_K2_E5 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_PB_BASE_PB_NEXT_OFFSET_K2_E5_SHIFT 20 +#define PCIEIP_REG_PCIEEP_SCAP_HDR_E5 0x000178UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_SCAP_HDR_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_SCAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_SCAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_SCAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_SCAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_SCAP_HDR_NCO_E5_SHIFT 20 +#define PCIEIP_REG_PB_BASE_K2 0x000178UL //Access:RW DataWidth:0x20 // Power Budgeting Extended Capability Header. + #define PCIEIP_REG_PB_BASE_PB_PCIE_EXTENDED_CAP_ID_K2 (0xffff<<0) // PB Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_PB_BASE_PB_PCIE_EXTENDED_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_PB_BASE_PB_CAP_VERSION_K2 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_PB_BASE_PB_CAP_VERSION_K2_SHIFT 16 + #define PCIEIP_REG_PB_BASE_PB_NEXT_OFFSET_K2 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_PB_BASE_PB_NEXT_OFFSET_K2_SHIFT 20 #define PCIEIP_REG_VC_RSRC_STATUS_BB 0x000178UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_VC_RSRC_STATUS_UNUSED0_BB (0xffff<<0) // #define PCIEIP_REG_VC_RSRC_STATUS_UNUSED0_BB_SHIFT 0 #define PCIEIP_REG_VC_RSRC_STATUS_VC_RSRC_STATUS_BB (0xffff<<16) // Not implemented. #define PCIEIP_REG_VC_RSRC_STATUS_VC_RSRC_STATUS_BB_SHIFT 16 -#define PCIEIP_REG_PB_DATA_SELECT_K2_E5 0x00017cUL //Access:RW DataWidth:0x20 // Data select Register. - #define PCIEIP_REG_PB_DATA_SELECT_PB_DATA_SEL_K2_E5 (0xff<<0) // Data Select Register. - #define PCIEIP_REG_PB_DATA_SELECT_PB_DATA_SEL_K2_E5_SHIFT 0 -#define PCIEIP_REG_DATA_REG_PB_K2_E5 0x000180UL //Access:R DataWidth:0x20 // Data Register. - #define PCIEIP_REG_DATA_REG_PB_PB_BASE_POWER_K2_E5 (0xff<<0) // Base Power. - #define PCIEIP_REG_DATA_REG_PB_PB_BASE_POWER_K2_E5_SHIFT 0 - #define PCIEIP_REG_DATA_REG_PB_PB_DATA_SCALE_K2_E5 (0x3<<8) // Data Scale. - #define PCIEIP_REG_DATA_REG_PB_PB_DATA_SCALE_K2_E5_SHIFT 8 - #define PCIEIP_REG_DATA_REG_PB_PB_PM_SUB_STATE_K2_E5 (0x7<<10) // PM Sub State. - #define PCIEIP_REG_DATA_REG_PB_PB_PM_SUB_STATE_K2_E5_SHIFT 10 - #define PCIEIP_REG_DATA_REG_PB_PB_PM_STATE_K2_E5 (0x3<<13) // PM State. - #define PCIEIP_REG_DATA_REG_PB_PB_PM_STATE_K2_E5_SHIFT 13 - #define PCIEIP_REG_DATA_REG_PB_PB_TYPE_K2_E5 (0x7<<15) // Type of Operating Condition. - #define PCIEIP_REG_DATA_REG_PB_PB_TYPE_K2_E5_SHIFT 15 - #define PCIEIP_REG_DATA_REG_PB_PB_POWER_RAIL_STATE_K2_E5 (0x7<<18) // Power Rail State. - #define PCIEIP_REG_DATA_REG_PB_PB_POWER_RAIL_STATE_K2_E5_SHIFT 18 +#define PCIEIP_REG_PCIEEP_LINK_CTL3_E5 0x00017cUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_LINK_CTL3_PEQ_E5 (0x1<<0) // Perform equalization. + #define PCIEIP_REG_PCIEEP_LINK_CTL3_PEQ_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_LINK_CTL3_EQRIE_E5 (0x1<<1) // Link equalization request interrupt enable. + #define PCIEIP_REG_PCIEEP_LINK_CTL3_EQRIE_E5_SHIFT 1 +#define PCIEIP_REG_PB_DATA_SELECT_K2 0x00017cUL //Access:RW DataWidth:0x20 // Data select Register. + #define PCIEIP_REG_PB_DATA_SELECT_PB_DATA_SEL_K2 (0xff<<0) // Data Select Register. + #define PCIEIP_REG_PB_DATA_SELECT_PB_DATA_SEL_K2_SHIFT 0 +#define PCIEIP_REG_PCIEEP_LANE_ERR_E5 0x000180UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_LANE_ERR_LES_E5 (0xffff<<0) // Lane error status bits. + #define PCIEIP_REG_PCIEEP_LANE_ERR_LES_E5_SHIFT 0 +#define PCIEIP_REG_DATA_REG_PB_K2 0x000180UL //Access:R DataWidth:0x20 // Data Register. + #define PCIEIP_REG_DATA_REG_PB_PB_BASE_POWER_K2 (0xff<<0) // Base Power. + #define PCIEIP_REG_DATA_REG_PB_PB_BASE_POWER_K2_SHIFT 0 + #define PCIEIP_REG_DATA_REG_PB_PB_DATA_SCALE_K2 (0x3<<8) // Data Scale. + #define PCIEIP_REG_DATA_REG_PB_PB_DATA_SCALE_K2_SHIFT 8 + #define PCIEIP_REG_DATA_REG_PB_PB_PM_SUB_STATE_K2 (0x7<<10) // PM Sub State. + #define PCIEIP_REG_DATA_REG_PB_PB_PM_SUB_STATE_K2_SHIFT 10 + #define PCIEIP_REG_DATA_REG_PB_PB_PM_STATE_K2 (0x3<<13) // PM State. + #define PCIEIP_REG_DATA_REG_PB_PB_PM_STATE_K2_SHIFT 13 + #define PCIEIP_REG_DATA_REG_PB_PB_TYPE_K2 (0x7<<15) // Type of Operating Condition. + #define PCIEIP_REG_DATA_REG_PB_PB_TYPE_K2_SHIFT 15 + #define PCIEIP_REG_DATA_REG_PB_PB_POWER_RAIL_STATE_K2 (0x7<<18) // Power Rail State. + #define PCIEIP_REG_DATA_REG_PB_PB_POWER_RAIL_STATE_K2_SHIFT 18 #define PCIEIP_REG_VENDOR_CAP_BB 0x000180UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by setting bit 0 of the EXT_CAP_ENA for EP, or setting bit 0 of RC_EXT_CAP_ENA for RC. By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining VendorCapOn in version.v. When supporting SRIOV, this capability is enabled if PCIE_VF_BAR_STRIDE is defined in version.v #define PCIEIP_REG_VENDOR_CAP_VENDOR_SPEC_CAP_ID_BB (0xffff<<0) // Vendor Specific Extended Capability ID. Hardwired to 0xB. Path = cfg_defs #define PCIEIP_REG_VENDOR_CAP_VENDOR_SPEC_CAP_ID_BB_SHIFT 0 @@ -1522,9 +2182,26 @@ #define PCIEIP_REG_VENDOR_CAP_CAP_VER_BB_SHIFT 16 #define PCIEIP_REG_VENDOR_CAP_NEXT_BB (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg #define PCIEIP_REG_VENDOR_CAP_NEXT_BB_SHIFT 20 -#define PCIEIP_REG_CAP_REG_PB_K2_E5 0x000184UL //Access:RW DataWidth:0x20 // Power Budget Capability Register. - #define PCIEIP_REG_CAP_REG_PB_PB_SYS_ALLOC_K2_E5 (0x1<<0) // System Allocated PB. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_CAP_REG_PB_PB_SYS_ALLOC_K2_E5_SHIFT 0 +#define PCIEIP_REG_PCIEEP_EQ_CTL01_E5 0x000184UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_EQ_CTL01_L0DTP_E5 (0xf<<0) // Lane 0 downstream port transmitter preset. This field reserved if port is operating as a Upstream Port. + #define PCIEIP_REG_PCIEEP_EQ_CTL01_L0DTP_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_EQ_CTL01_L0DRPH_E5 (0x7<<4) // Lane 0 downstream port receiver preset hint. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL01_L0DRPH_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_EQ_CTL01_L0UTP_E5 (0xf<<8) // Lane 0 upstream port transmitter preset. + #define PCIEIP_REG_PCIEEP_EQ_CTL01_L0UTP_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_EQ_CTL01_L0URPH_E5 (0x7<<12) // Lane 0 upstream port receiver preset hint. + #define PCIEIP_REG_PCIEEP_EQ_CTL01_L0URPH_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_EQ_CTL01_L1DTP_E5 (0xf<<16) // Lane 1 downstream port transmitter preset. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL01_L1DTP_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_EQ_CTL01_L1DRPH_E5 (0x7<<20) // Lane 1 downstream port receiver preset hint. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL01_L1DRPH_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_EQ_CTL01_L1UTP_E5 (0xf<<24) // Lane 1 upstream port transmitter preset. + #define PCIEIP_REG_PCIEEP_EQ_CTL01_L1UTP_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_EQ_CTL01_L1URPH_E5 (0x7<<28) // Lane 1 upstream port receiver preset hint. + #define PCIEIP_REG_PCIEEP_EQ_CTL01_L1URPH_E5_SHIFT 28 +#define PCIEIP_REG_CAP_REG_PB_K2 0x000184UL //Access:RW DataWidth:0x20 // Power Budget Capability Register. + #define PCIEIP_REG_CAP_REG_PB_PB_SYS_ALLOC_K2 (0x1<<0) // System Allocated PB. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_CAP_REG_PB_PB_SYS_ALLOC_K2_SHIFT 0 #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_BB 0x000184UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by setting bit 0 of the EXT_CAP_ENA for EP, or setting bit 0 of RC_EXT_CAP_ENA for RC. By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining VendorCapOn in version.v #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_ID_BB (0xffff<<0) // VSEC ID. This field is a vendor-defined ID number that indicates the nature and format of the VSEC structure. Software must qualify the Vendor ID before interpreting this field. Path = i_cfg_func.i_cfg_private #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_ID_BB_SHIFT 0 @@ -1532,126 +2209,254 @@ #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_REV_BB_SHIFT 16 #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_BB (0xfff<<20) // VSEC Length. This field indicates the number of bytes in the entire VSEC structure, including the PCI Express Enhanced Capability header, the Vendor-Specific header, and the Vendor-Specific Registers. Path = i_cfg_func.i_cfg_private #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_BB_SHIFT 20 -#define PCIEIP_REG_ARI_BASE_K2_E5 0x000188UL //Access:RW DataWidth:0x20 // ARI Capability Header. - #define PCIEIP_REG_ARI_BASE_ARI_PCIE_EXTENDED_CAP_ID_K2_E5 (0xffff<<0) // ARI Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_ARI_BASE_ARI_PCIE_EXTENDED_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_ARI_BASE_ARI_CAP_VERSION_K2_E5 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_ARI_BASE_ARI_CAP_VERSION_K2_E5_SHIFT 16 - #define PCIEIP_REG_ARI_BASE_ARI_NEXT_OFFSET_K2_E5 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_ARI_BASE_ARI_NEXT_OFFSET_K2_E5_SHIFT 20 +#define PCIEIP_REG_PCIEEP_EQ_CTL23_E5 0x000188UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_EQ_CTL23_L2DTP_E5 (0xf<<0) // Lane 2 downstream port transmitter preset. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL23_L2DTP_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_EQ_CTL23_L2DRPH_E5 (0x7<<4) // Lane 2 downstream port receiver preset hint. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL23_L2DRPH_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_EQ_CTL23_L2UTP_E5 (0xf<<8) // Lane 2 upstream port transmitter preset. + #define PCIEIP_REG_PCIEEP_EQ_CTL23_L2UTP_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_EQ_CTL23_L2URPH_E5 (0x7<<12) // Lane 2 upstream port receiver preset hint. + #define PCIEIP_REG_PCIEEP_EQ_CTL23_L2URPH_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_EQ_CTL23_L3DTP_E5 (0xf<<16) // Lane 3 downstream port transmitter preset. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL23_L3DTP_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_EQ_CTL23_L3DRPH_E5 (0x7<<20) // Lane 3 downstream port receiver preset hint. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL23_L3DRPH_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_EQ_CTL23_L3UTP_E5 (0xf<<24) // Lane 3 upstream port transmitter preset. + #define PCIEIP_REG_PCIEEP_EQ_CTL23_L3UTP_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_EQ_CTL23_L3URPH_E5 (0x7<<28) // Lane 3 upstream port receiver preset hint. + #define PCIEIP_REG_PCIEEP_EQ_CTL23_L3URPH_E5_SHIFT 28 +#define PCIEIP_REG_ARI_BASE_K2 0x000188UL //Access:RW DataWidth:0x20 // ARI Capability Header. + #define PCIEIP_REG_ARI_BASE_ARI_PCIE_EXTENDED_CAP_ID_K2 (0xffff<<0) // ARI Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_ARI_BASE_ARI_PCIE_EXTENDED_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_ARI_BASE_ARI_CAP_VERSION_K2 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_ARI_BASE_ARI_CAP_VERSION_K2_SHIFT 16 + #define PCIEIP_REG_ARI_BASE_ARI_NEXT_OFFSET_K2 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_ARI_BASE_ARI_NEXT_OFFSET_K2_SHIFT 20 #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_BB 0x000188UL //Access:RW DataWidth:0x20 // If bit 0 of the EXT_CAP_ENA for EP or bit 0 of RC_EXT_CAP_ENA for RC is reset to '0', reading this register will return all 0's. By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining VendorCapOn or PCIE_VF_BAR_STRIDE in version.v #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_VF_BAR0_STRIDE_BITS_BB (0x7fffffff<<0) // This field defines alignment and stride of VF BAR0 address space. The bits are a power of 2 value that multiplies the PF VF Bar0 value to compute the starting address and alignment of the BAR0 for each VF. This field may only have 1 bit set.This field is ignored when bit 31 is 0. #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_VF_BAR0_STRIDE_BITS_BB_SHIFT 0 #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_VF_BAR0_STRIDE_EN_BB (0x1<<31) // Enable VF Bar0 Stride. When this bit bit is clear, computation of the VF BAR0 offset from the PF SRIOV capability structure is unchanged. #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_VF_BAR0_STRIDE_EN_BB_SHIFT 31 -#define PCIEIP_REG_CAP_REG_K2_E5 0x00018cUL //Access:R DataWidth:0x20 // ARI Capability and Control Register. - #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_CAP_K2_E5 (0x1<<0) // Multi Functional Virtual Channel (MFVC) Function Groups Capability. - #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_CAP_K2_E5_SHIFT 0 - #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_CAP_K2_E5 (0x1<<1) // ACS Function Groups Capability. - #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_CAP_K2_E5_SHIFT 1 - #define PCIEIP_REG_CAP_REG_ARI_NEXT_FUN_NUM_K2_E5 (0xff<<8) // Next Function Number. - #define PCIEIP_REG_CAP_REG_ARI_NEXT_FUN_NUM_K2_E5_SHIFT 8 - #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_EN_K2_E5 (0x1<<16) // MFVC Function Groups Enable. - #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_EN_K2_E5_SHIFT 16 - #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_EN_K2_E5 (0x1<<17) // ACS Function Groups Enable. - #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_EN_K2_E5_SHIFT 17 - #define PCIEIP_REG_CAP_REG_ARI_FUN_GRP_K2_E5 (0x7<<20) // Function Group. - #define PCIEIP_REG_CAP_REG_ARI_FUN_GRP_K2_E5_SHIFT 20 +#define PCIEIP_REG_PCIEEP_EQ_CTL45_E5 0x00018cUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_EQ_CTL45_L4DTP_E5 (0xf<<0) // Lane 4 downstream port transmitter preset. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL45_L4DTP_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_EQ_CTL45_L4DRPH_E5 (0x7<<4) // Lane 4 downstream port receiver preset hint. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL45_L4DRPH_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_EQ_CTL45_L4UTP_E5 (0xf<<8) // Lane 4 upstream port transmitter preset. + #define PCIEIP_REG_PCIEEP_EQ_CTL45_L4UTP_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_EQ_CTL45_L4URPH_E5 (0x7<<12) // Lane 4 upstream port receiver preset hint. + #define PCIEIP_REG_PCIEEP_EQ_CTL45_L4URPH_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_EQ_CTL45_L5DTP_E5 (0xf<<16) // Lane 5 downstream port transmitter preset. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL45_L5DTP_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_EQ_CTL45_L5DRPH_E5 (0x7<<20) // Lane 5 downstream port receiver preset hint. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL45_L5DRPH_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_EQ_CTL45_L5UTP_E5 (0xf<<24) // Lane 5 upstream port transmitter preset. + #define PCIEIP_REG_PCIEEP_EQ_CTL45_L5UTP_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_EQ_CTL45_L5URPH_E5 (0x7<<28) // Lane 5 upstream port receiver preset hint. + #define PCIEIP_REG_PCIEEP_EQ_CTL45_L5URPH_E5_SHIFT 28 +#define PCIEIP_REG_CAP_REG_K2 0x00018cUL //Access:R DataWidth:0x20 // ARI Capability and Control Register. + #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_CAP_K2 (0x1<<0) // Multi Functional Virtual Channel (MFVC) Function Groups Capability. + #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_CAP_K2_SHIFT 0 + #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_CAP_K2 (0x1<<1) // ACS Function Groups Capability. + #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_CAP_K2_SHIFT 1 + #define PCIEIP_REG_CAP_REG_ARI_NEXT_FUN_NUM_K2 (0xff<<8) // Next Function Number. + #define PCIEIP_REG_CAP_REG_ARI_NEXT_FUN_NUM_K2_SHIFT 8 + #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_EN_K2 (0x1<<16) // MFVC Function Groups Enable. + #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_EN_K2_SHIFT 16 + #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_EN_K2 (0x1<<17) // ACS Function Groups Enable. + #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_EN_K2_SHIFT 17 + #define PCIEIP_REG_CAP_REG_ARI_FUN_GRP_K2 (0x7<<20) // Function Group. + #define PCIEIP_REG_CAP_REG_ARI_FUN_GRP_K2_SHIFT 20 #define PCIEIP_REG_VENDOR_SPECIFIC_REG2_BB 0x00018cUL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_EQ_CTL67_E5 0x000190UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_EQ_CTL67_L6DTP_E5 (0xf<<0) // Lane 6 downstream port transmitter preset. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL67_L6DTP_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_EQ_CTL67_L6DRPH_E5 (0x7<<4) // Lane 6 downstream port receiver preset hint. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL67_L6DRPH_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_EQ_CTL67_L6UTP_E5 (0xf<<8) // Lane 6 upstream port transmitter preset. + #define PCIEIP_REG_PCIEEP_EQ_CTL67_L6UTP_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_EQ_CTL67_L6URPH_E5 (0x7<<12) // Lane 6 upstream port receiver preset hint. + #define PCIEIP_REG_PCIEEP_EQ_CTL67_L6URPH_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_EQ_CTL67_L7DTP_E5 (0xf<<16) // Lane 7 downstream port transmitter preset. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL67_L7DTP_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_EQ_CTL67_L7DRPH_E5 (0x7<<20) // Lane 7 downstream port receiver preset hint. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL67_L7DRPH_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_EQ_CTL67_L7UTP_E5 (0xf<<24) // Lane 7 upstream port transmitter preset. + #define PCIEIP_REG_PCIEEP_EQ_CTL67_L7UTP_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_EQ_CTL67_L7URPH_E5 (0x7<<28) // Lane 7 upstream port receiver preset hint. + #define PCIEIP_REG_PCIEEP_EQ_CTL67_L7URPH_E5_SHIFT 28 #define PCIEIP_REG_VENDOR_SPECIFIC_REG3_BB 0x000190UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_VENDOR_SPECIFIC_REG3_VF_BAR2_STRIDE_BITS_BB (0x7fffffff<<0) // This field defines alignment and stride of VF BAR2 address space. The bits are a power of 2 value that multiplies the PF VF Bar2 value to compute the starting address and alignment of the BAR2 for each VF. This field may only have 1 bit set.This field is ignored when bit 31 is 0. #define PCIEIP_REG_VENDOR_SPECIFIC_REG3_VF_BAR2_STRIDE_BITS_BB_SHIFT 0 #define PCIEIP_REG_VENDOR_SPECIFIC_REG3_VF_BAR2_STRIDE_EN_BB (0x1<<31) // Enable VF Bar2 Stride. When this bit bit is clear, computation of the VF BAR2 offset from the PF SRIOV capability structure is unchanged. #define PCIEIP_REG_VENDOR_SPECIFIC_REG3_VF_BAR2_STRIDE_EN_BB_SHIFT 31 +#define PCIEIP_REG_PCIEEP_EQ_CTL89_E5 0x000194UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_EQ_CTL89_L8DTP_E5 (0xf<<0) // Lane 8 downstream port transmitter preset. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL89_L8DTP_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_EQ_CTL89_L8DRPH_E5 (0x7<<4) // Lane 8 downstream port receiver preset hint. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL89_L8DRPH_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_EQ_CTL89_L8UTP_E5 (0xf<<8) // Lane 8 upstream port transmitter preset. + #define PCIEIP_REG_PCIEEP_EQ_CTL89_L8UTP_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_EQ_CTL89_L8URPH_E5 (0x7<<12) // Lane 8 upstream port receiver preset hint. + #define PCIEIP_REG_PCIEEP_EQ_CTL89_L8URPH_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_EQ_CTL89_L9DTP_E5 (0xf<<16) // Lane 9 downstream port transmitter preset. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL89_L9DTP_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_EQ_CTL89_L9DRPH_E5 (0x7<<20) // Lane 9 downstream port receiver preset hint. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL89_L9DRPH_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_EQ_CTL89_L9UTP_E5 (0xf<<24) // Lane 9 upstream port transmitter preset. + #define PCIEIP_REG_PCIEEP_EQ_CTL89_L9UTP_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_EQ_CTL89_L9URPH_E5 (0x7<<28) // Lane 9 upstream port receiver preset hint. + #define PCIEIP_REG_PCIEEP_EQ_CTL89_L9URPH_E5_SHIFT 28 #define PCIEIP_REG_VENDOR_SPECIFIC_REG4_BB 0x000194UL //Access:R DataWidth:0x20 // -#define PCIEIP_REG_SPCIE_CAP_HEADER_REG_K2_E5 0x000198UL //Access:RW DataWidth:0x20 // SPCIE Capability Header. - #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_K2_E5 (0xffff<<0) // Secondary PCI Express Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_CAP_VERSION_K2_E5 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_CAP_VERSION_K2_E5_SHIFT 16 - #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_K2_E5 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_K2_E5_SHIFT 20 +#define PCIEIP_REG_PCIEEP_EQ_CTL1011_E5 0x000198UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L10DTP_E5 (0xf<<0) // Lane 10 downstream port transmitter preset. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L10DTP_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L10DRPH_E5 (0x7<<4) // Lane 10 downstream port receiver preset hint. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L10DRPH_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L10UTP_E5 (0xf<<8) // Lane 10 upstream port transmitter preset. + #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L10UTP_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L10URPH_E5 (0x7<<12) // Lane 10 upstream port receiver preset hint. + #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L10URPH_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L11DTP_E5 (0xf<<16) // Lane 11 downstream port transmitter preset. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L11DTP_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L11DRPH_E5 (0x7<<20) // Lane 11 downstream port receiver preset hint. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L11DRPH_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L11UTP_E5 (0xf<<24) // Lane 11 upstream port transmitter preset. + #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L11UTP_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L11URPH_E5 (0x7<<28) // Lane 11 upstream port reeiver preset hint. + #define PCIEIP_REG_PCIEEP_EQ_CTL1011_L11URPH_E5_SHIFT 28 +#define PCIEIP_REG_SPCIE_CAP_HEADER_REG_K2 0x000198UL //Access:RW DataWidth:0x20 // SPCIE Capability Header. + #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_K2 (0xffff<<0) // Secondary PCI Express Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_EXTENDED_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_CAP_VERSION_K2 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_CAP_VERSION_K2_SHIFT 16 + #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_K2 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_SPCIE_CAP_HEADER_REG_NEXT_OFFSET_K2_SHIFT 20 #define PCIEIP_REG_VENDOR_SPECIFIC_REG5_BB 0x000198UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_VENDOR_SPECIFIC_REG5_VF_BAR4_STRIDE_BITS_BB (0x7fffffff<<0) // This field defines alignment and stride of VF BAR4 address space. The bits are a power of 2 value that multiplies the PF VF Bar4 value to compute the starting address and alignment of the BAR4 for each VF. This field may only have 1 bit set.This field is ignored when bit 31 is 0. #define PCIEIP_REG_VENDOR_SPECIFIC_REG5_VF_BAR4_STRIDE_BITS_BB_SHIFT 0 #define PCIEIP_REG_VENDOR_SPECIFIC_REG5_VF_BAR4_STRIDE_EN_BB (0x1<<31) // Enable VF Bar4 Stride. When this bit bit is clear, computation of the VF BAR4 offset from the PF SRIOV capability structure is unchanged. #define PCIEIP_REG_VENDOR_SPECIFIC_REG5_VF_BAR4_STRIDE_EN_BB_SHIFT 31 -#define PCIEIP_REG_LINK_CONTROL3_REG_K2_E5 0x00019cUL //Access:R DataWidth:0x20 // Link Control 3 Register. - #define PCIEIP_REG_LINK_CONTROL3_REG_PERFORM_EQ_K2_E5 (0x1<<0) // Perform Equalization. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_LINK_CONTROL3_REG_PERFORM_EQ_K2_E5_SHIFT 0 - #define PCIEIP_REG_LINK_CONTROL3_REG_EQ_REQ_INT_EN_K2_E5 (0x1<<1) // Link Equalization Request Interrupt Enable. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_LINK_CONTROL3_REG_EQ_REQ_INT_EN_K2_E5_SHIFT 1 -#define PCIEIP_REG_LANE_ERR_STATUS_REG_K2_E5 0x0001a0UL //Access:RW DataWidth:0x20 // Lane Error Status Register. - #define PCIEIP_REG_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_K2_E5 (0xff<<0) // Lane Error Status Bits per Lane. - #define PCIEIP_REG_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_K2_E5_SHIFT 0 -#define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_K2_E5 0x0001a4UL //Access:R DataWidth:0x20 // Lane Equalization Control Register for lanes 1 and 0. - #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_K2_E5 (0xf<<0) // Downstream Port 8.0 GT/s Transmitter Preset 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_K2_E5_SHIFT 0 - #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_K2_E5 (0x7<<4) // Downstream Port 8.0 GT/s Receiver Preset Hint 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_K2_E5_SHIFT 4 - #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_K2_E5 (0xf<<8) // Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS - #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_K2_E5_SHIFT 8 - #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_K2_E5 (0x7<<12) // Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS - #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_K2_E5_SHIFT 12 - #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_K2_E5 (0xf<<16) // Downstream Port 8.0 GT/s Transmitter Preset 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_K2_E5_SHIFT 16 - #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_K2_E5 (0x7<<20) // Downstream Port 8.0 GT/s Receiver Preset Hint 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_K2_E5_SHIFT 20 - #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_K2_E5 (0xf<<24) // Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS - #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_K2_E5_SHIFT 24 - #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_K2_E5 (0x7<<28) // Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS - #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_K2_E5_SHIFT 28 -#define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_K2_E5 0x0001a8UL //Access:R DataWidth:0x20 // Lane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #2. The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL. - #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_K2_E5 (0xf<<0) // Downstream Port 8.0 GT/s Transmitter Preset2. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_K2_E5_SHIFT 0 - #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_K2_E5 (0x7<<4) // Downstream Port 8.0 GT/s Receiver Preset Hint2. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_K2_E5_SHIFT 4 - #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_K2_E5 (0xf<<8) // Upstream Port 8.0 GT/s Transmitter Preset2. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS - #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_K2_E5_SHIFT 8 - #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_K2_E5 (0x7<<12) // Upstream Port 8.0 GT/s Receiver Preset Hint2. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS - #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_K2_E5_SHIFT 12 - #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_K2_E5 (0xf<<16) // Downstream Port 8.0 GT/s Transmitter Preset3. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_K2_E5_SHIFT 16 - #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_K2_E5 (0x7<<20) // Downstream Port 8.0 GT/s Receiver Preset Hint3. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_K2_E5_SHIFT 20 - #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_K2_E5 (0xf<<24) // Upstream Port 8.0 GT/s Transmitter Preset3. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS - #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_K2_E5_SHIFT 24 - #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_K2_E5 (0x7<<28) // Upstream Port 8.0 GT/s Receiver Preset Hint3. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS - #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_K2_E5_SHIFT 28 -#define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_K2_E5 0x0001acUL //Access:R DataWidth:0x20 // Lane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #4. The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL. - #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_K2_E5 (0xf<<0) // Downstream Port 8.0 GT/s Transmitter Preset4. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_K2_E5_SHIFT 0 - #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_K2_E5 (0x7<<4) // Downstream Port 8.0 GT/s Receiver Preset Hint4. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_K2_E5_SHIFT 4 - #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_K2_E5 (0xf<<8) // Upstream Port 8.0 GT/s Transmitter Preset4. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS - #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_K2_E5_SHIFT 8 - #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_K2_E5 (0x7<<12) // Upstream Port 8.0 GT/s Receiver Preset Hint4. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS - #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_K2_E5_SHIFT 12 - #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_K2_E5 (0xf<<16) // Downstream Port 8.0 GT/s Transmitter Preset5. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_K2_E5_SHIFT 16 - #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_K2_E5 (0x7<<20) // Downstream Port 8.0 GT/s Receiver Preset Hint5. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_K2_E5_SHIFT 20 - #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_K2_E5 (0xf<<24) // Upstream Port 8.0 GT/s Transmitter Preset5. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS - #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_K2_E5_SHIFT 24 - #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_K2_E5 (0x7<<28) // Upstream Port 8.0 GT/s Receiver Preset Hint5. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS - #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_K2_E5_SHIFT 28 -#define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_K2_E5 0x0001b0UL //Access:R DataWidth:0x20 // Lane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #6. The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL. - #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_K2_E5 (0xf<<0) // Downstream Port 8.0 GT/s Transmitter Preset6. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_K2_E5_SHIFT 0 - #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_K2_E5 (0x7<<4) // Downstream Port 8.0 GT/s Receiver Preset Hint6. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_K2_E5_SHIFT 4 - #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_K2_E5 (0xf<<8) // Upstream Port 8.0 GT/s Transmitter Preset6. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS - #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_K2_E5_SHIFT 8 - #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_K2_E5 (0x7<<12) // Upstream Port 8.0 GT/s Receiver Preset Hint6. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS - #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_K2_E5_SHIFT 12 - #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_K2_E5 (0xf<<16) // Downstream Port 8.0 GT/s Transmitter Preset7. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_K2_E5_SHIFT 16 - #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_K2_E5 (0x7<<20) // Downstream Port 8.0 GT/s Receiver Preset Hint7. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_K2_E5_SHIFT 20 - #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_K2_E5 (0xf<<24) // Upstream Port 8.0 GT/s Transmitter Preset7. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS - #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_K2_E5_SHIFT 24 - #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_K2_E5 (0x7<<28) // Upstream Port 8.0 GT/s Receiver Preset Hint7. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS - #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_K2_E5_SHIFT 28 +#define PCIEIP_REG_PCIEEP_EQ_CTL1213_E5 0x00019cUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_EQ_CTL1213_L12DTP_E5 (0xf<<0) // Lane 12 downstream port transmitter preset. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL1213_L12DTP_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_EQ_CTL1213_L12DRPH_E5 (0x7<<4) // Lane 12 downstream port receiver preset hint. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL1213_L12DRPH_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_EQ_CTL1213_L12UTP_E5 (0xf<<8) // Lane 12 upstream port transmitter preset. + #define PCIEIP_REG_PCIEEP_EQ_CTL1213_L12UTP_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_EQ_CTL1213_L12URPH_E5 (0x7<<12) // Lane 12 upstream port receiver preset hint. + #define PCIEIP_REG_PCIEEP_EQ_CTL1213_L12URPH_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_EQ_CTL1213_L13DTP_E5 (0xf<<16) // Lane 13 downstream port transmitter preset. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL1213_L13DTP_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_EQ_CTL1213_L13DRPH_E5 (0x7<<20) // Lane 13 downstream port receiver preset hint. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL1213_L13DRPH_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_EQ_CTL1213_L13UTP_E5 (0xf<<24) // Lane 13 upstream port transmitter preset. + #define PCIEIP_REG_PCIEEP_EQ_CTL1213_L13UTP_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_EQ_CTL1213_L13URPH_E5 (0x7<<28) // Lane 13 upstream port receiver preset hint. + #define PCIEIP_REG_PCIEEP_EQ_CTL1213_L13URPH_E5_SHIFT 28 +#define PCIEIP_REG_LINK_CONTROL3_REG_K2 0x00019cUL //Access:R DataWidth:0x20 // Link Control 3 Register. + #define PCIEIP_REG_LINK_CONTROL3_REG_PERFORM_EQ_K2 (0x1<<0) // Perform Equalization. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_LINK_CONTROL3_REG_PERFORM_EQ_K2_SHIFT 0 + #define PCIEIP_REG_LINK_CONTROL3_REG_EQ_REQ_INT_EN_K2 (0x1<<1) // Link Equalization Request Interrupt Enable. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_LINK_CONTROL3_REG_EQ_REQ_INT_EN_K2_SHIFT 1 +#define PCIEIP_REG_PCIEEP_EQ_CTL1415_E5 0x0001a0UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_EQ_CTL1415_L14DTP_E5 (0xf<<0) // Lane 14 downstream port transmitter preset. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL1415_L14DTP_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_EQ_CTL1415_L14DRPH_E5 (0x7<<4) // Lane 14 downstream port receiver preset hint. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL1415_L14DRPH_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_EQ_CTL1415_L14UTP_E5 (0xf<<8) // Lane 14 upstream port transmitter preset. + #define PCIEIP_REG_PCIEEP_EQ_CTL1415_L14UTP_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_EQ_CTL1415_L14URPH_E5 (0x7<<12) // Lane 14 upstream port receiver preset hint. + #define PCIEIP_REG_PCIEEP_EQ_CTL1415_L14URPH_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_EQ_CTL1415_L15DTP_E5 (0xf<<16) // Lane 15 downstream port transmitter preset. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL1415_L15DTP_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_EQ_CTL1415_L15DRPH_E5 (0x7<<20) // Lane 15 downstream port receiver preset hint. This field reserved if port is operating as a upstream port. + #define PCIEIP_REG_PCIEEP_EQ_CTL1415_L15DRPH_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_EQ_CTL1415_L15UTP_E5 (0xf<<24) // Lane 15 upstream port transmitter preset. + #define PCIEIP_REG_PCIEEP_EQ_CTL1415_L15UTP_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_EQ_CTL1415_L15URPH_E5 (0x7<<28) // Lane 15 upstream port receiver preset hint. + #define PCIEIP_REG_PCIEEP_EQ_CTL1415_L15URPH_E5_SHIFT 28 +#define PCIEIP_REG_LANE_ERR_STATUS_REG_K2 0x0001a0UL //Access:RW DataWidth:0x20 // Lane Error Status Register. + #define PCIEIP_REG_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_K2 (0xff<<0) // Lane Error Status Bits per Lane. + #define PCIEIP_REG_LANE_ERR_STATUS_REG_LANE_ERR_STATUS_K2_SHIFT 0 +#define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_K2 0x0001a4UL //Access:R DataWidth:0x20 // Lane Equalization Control Register for lanes 1 and 0. + #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_K2 (0xf<<0) // Downstream Port 8.0 GT/s Transmitter Preset 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET0_K2_SHIFT 0 + #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_K2 (0x7<<4) // Downstream Port 8.0 GT/s Receiver Preset Hint 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT0_K2_SHIFT 4 + #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_K2 (0xf<<8) // Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS + #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET0_K2_SHIFT 8 + #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_K2 (0x7<<12) // Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS + #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT0_K2_SHIFT 12 + #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_K2 (0xf<<16) // Downstream Port 8.0 GT/s Transmitter Preset 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_TX_PRESET1_K2_SHIFT 16 + #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_K2 (0x7<<20) // Downstream Port 8.0 GT/s Receiver Preset Hint 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_DSP_RX_PRESET_HINT1_K2_SHIFT 20 + #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_K2 (0xf<<24) // Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS + #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_TX_PRESET1_K2_SHIFT 24 + #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_K2 (0x7<<28) // Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS + #define PCIEIP_REG_SPCIE_CAP_OFF_0CH_REG_USP_RX_PRESET_HINT1_K2_SHIFT 28 +#define PCIEIP_REG_PCIEEP_PL16G_EXT_CAP_HDR_E5 0x0001a8UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PL16G_EXT_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PL16G_EXT_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PL16G_EXT_CAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PL16G_EXT_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_PL16G_EXT_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PL16G_EXT_CAP_HDR_NCO_E5_SHIFT 20 +#define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_K2 0x0001a8UL //Access:R DataWidth:0x20 // Lane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #2. The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL. + #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_K2 (0xf<<0) // Downstream Port 8.0 GT/s Transmitter Preset2. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET2_K2_SHIFT 0 + #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_K2 (0x7<<4) // Downstream Port 8.0 GT/s Receiver Preset Hint2. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT2_K2_SHIFT 4 + #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_K2 (0xf<<8) // Upstream Port 8.0 GT/s Transmitter Preset2. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS + #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET2_K2_SHIFT 8 + #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_K2 (0x7<<12) // Upstream Port 8.0 GT/s Receiver Preset Hint2. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS + #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT2_K2_SHIFT 12 + #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_K2 (0xf<<16) // Downstream Port 8.0 GT/s Transmitter Preset3. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_TX_PRESET3_K2_SHIFT 16 + #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_K2 (0x7<<20) // Downstream Port 8.0 GT/s Receiver Preset Hint3. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_DSP_RX_PRESET_HINT3_K2_SHIFT 20 + #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_K2 (0xf<<24) // Upstream Port 8.0 GT/s Transmitter Preset3. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS + #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_TX_PRESET3_K2_SHIFT 24 + #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_K2 (0x7<<28) // Upstream Port 8.0 GT/s Receiver Preset Hint3. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS + #define PCIEIP_REG_SPCIE_CAP_OFF_10H_REG_USP_RX_PRESET_HINT3_K2_SHIFT 28 +#define PCIEIP_REG_PCIEEP_PL16G_CAP_E5 0x0001acUL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_K2 0x0001acUL //Access:R DataWidth:0x20 // Lane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #4. The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL. + #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_K2 (0xf<<0) // Downstream Port 8.0 GT/s Transmitter Preset4. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET4_K2_SHIFT 0 + #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_K2 (0x7<<4) // Downstream Port 8.0 GT/s Receiver Preset Hint4. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT4_K2_SHIFT 4 + #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_K2 (0xf<<8) // Upstream Port 8.0 GT/s Transmitter Preset4. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS + #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET4_K2_SHIFT 8 + #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_K2 (0x7<<12) // Upstream Port 8.0 GT/s Receiver Preset Hint4. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS + #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT4_K2_SHIFT 12 + #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_K2 (0xf<<16) // Downstream Port 8.0 GT/s Transmitter Preset5. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_TX_PRESET5_K2_SHIFT 16 + #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_K2 (0x7<<20) // Downstream Port 8.0 GT/s Receiver Preset Hint5. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_DSP_RX_PRESET_HINT5_K2_SHIFT 20 + #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_K2 (0xf<<24) // Upstream Port 8.0 GT/s Transmitter Preset5. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS + #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_TX_PRESET5_K2_SHIFT 24 + #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_K2 (0x7<<28) // Upstream Port 8.0 GT/s Receiver Preset Hint5. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS + #define PCIEIP_REG_SPCIE_CAP_OFF_14H_REG_USP_RX_PRESET_HINT5_K2_SHIFT 28 +#define PCIEIP_REG_PCIEEP_PL16G_CTL_E5 0x0001b0UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_K2 0x0001b0UL //Access:R DataWidth:0x20 // Lane Equalization Control Register (LEC) or Lane Equalization Control Register 2 (LEC2) #6. The function of this register is dependent on your actual configuration. - Gen3: LEC or RSVD depending on the value of CX_NL. - Gen4: LEC or LEC2 or RSVD depending on the value of CX_NL. + #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_K2 (0xf<<0) // Downstream Port 8.0 GT/s Transmitter Preset6. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET6_K2_SHIFT 0 + #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_K2 (0x7<<4) // Downstream Port 8.0 GT/s Receiver Preset Hint6. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT6_K2_SHIFT 4 + #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_K2 (0xf<<8) // Upstream Port 8.0 GT/s Transmitter Preset6. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS + #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET6_K2_SHIFT 8 + #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_K2 (0x7<<12) // Upstream Port 8.0 GT/s Receiver Preset Hint6. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS + #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT6_K2_SHIFT 12 + #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_K2 (0xf<<16) // Downstream Port 8.0 GT/s Transmitter Preset7. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_TX_PRESET7_K2_SHIFT 16 + #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_K2 (0x7<<20) // Downstream Port 8.0 GT/s Receiver Preset Hint7. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_DSP_RX_PRESET_HINT7_K2_SHIFT 20 + #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_K2 (0xf<<24) // Upstream Port 8.0 GT/s Transmitter Preset7. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS + #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_TX_PRESET7_K2_SHIFT 24 + #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_K2 (0x7<<28) // Upstream Port 8.0 GT/s Receiver Preset Hint7. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. Note: The access attributes of this field are as follows: - Dbi: DSP || USP && PCIE_CAP_CROSS_LINK_SUPPORT ? (if (DBI_RO_WR_EN == 1) then R/W (sticky) else R) : ROS + #define PCIEIP_REG_SPCIE_CAP_OFF_18H_REG_USP_RX_PRESET_HINT7_K2_SHIFT 28 #define PCIEIP_REG_LTR_CAP_BB 0x0001b0UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by setting bit 5 of the EXT_CAP_ENA for EP, By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining LTR_ENABLED in version.v and setting bit 5 of EXT_CAP_ENA. This capability when present , will only exist in function 0 of a multi-function device. #define PCIEIP_REG_LTR_CAP_LTR_EXT_CAP_ID_BB (0xffff<<0) // Vendor Specific Extended Capability ID. #define PCIEIP_REG_LTR_CAP_LTR_EXT_CAP_ID_BB_SHIFT 0 @@ -1659,6 +2464,17 @@ #define PCIEIP_REG_LTR_CAP_CAP_VER_BB_SHIFT 16 #define PCIEIP_REG_LTR_CAP_NEXT_BB (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. #define PCIEIP_REG_LTR_CAP_NEXT_BB_SHIFT 20 +#define PCIEIP_REG_PCIEEP_PL16G_STATUS_E5 0x0001b4UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PL16G_STATUS_EQ_CPL_E5 (0x1<<0) // Equalization 16.0 GT/s complete. + #define PCIEIP_REG_PCIEEP_PL16G_STATUS_EQ_CPL_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PL16G_STATUS_EQ_CPL_P1_E5 (0x1<<1) // Equalization 16.0 GT/s phase 3 successful. + #define PCIEIP_REG_PCIEEP_PL16G_STATUS_EQ_CPL_P1_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_PL16G_STATUS_EQ_CPL_P2_E5 (0x1<<2) // Equalization 16.0 GT/s phase 3 successful. + #define PCIEIP_REG_PCIEEP_PL16G_STATUS_EQ_CPL_P2_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_PL16G_STATUS_EQ_CPL_P3_E5 (0x1<<3) // Equalization 16.0 GT/s phase 3 successful. + #define PCIEIP_REG_PCIEEP_PL16G_STATUS_EQ_CPL_P3_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_PL16G_STATUS_LEQ_REQ_E5 (0x1<<4) // Link equalization request 16.0 GT/s + #define PCIEIP_REG_PCIEEP_PL16G_STATUS_LEQ_REQ_E5_SHIFT 4 #define PCIEIP_REG_LATENCY_REGISTER_BB 0x0001b4UL //Access:RW DataWidth:0x20 // The RW value of this register is controlled by setting bit 5 of the EXT_CAP_ENA for EP. By default, this capability is disabled (i.e. reading this register will return zeroes). #define PCIEIP_REG_LATENCY_REGISTER_MAX_SNOOP_LATE_VALUE_BB (0x3ff<<0) // Max Snoop Latency Value. Along with Max snoop latency scale field, this register specifies the maximum no-snoop latency that a device is premitted to request. Software should set this to the platforms max supported latency or less. #define PCIEIP_REG_LATENCY_REGISTER_MAX_SNOOP_LATE_VALUE_BB_SHIFT 0 @@ -1670,13 +2486,16 @@ #define PCIEIP_REG_LATENCY_REGISTER_MAX_NO_SNOOP_LATE_VALUE_BB_SHIFT 16 #define PCIEIP_REG_LATENCY_REGISTER_MAX_NO_SNOOP_LATE_SCALE_BB (0x7<<26) // Max No Snoop Latency Scale. This register provides a scale for the value contained within the max_no_snoop_late_value field. #define PCIEIP_REG_LATENCY_REGISTER_MAX_NO_SNOOP_LATE_SCALE_BB_SHIFT 26 -#define PCIEIP_REG_SRIOV_BASE_REG_K2_E5 0x0001b8UL //Access:RW DataWidth:0x20 // SR-IOV Capability Header. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_PCIE_EXTENDED_CAP_ID_K2_E5 (0xffff<<0) // SRIOV Extended Capability ID. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_PCIE_EXTENDED_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_CAP_VERSION_K2_E5 (0xf<<16) // Capability Version. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_CAP_VERSION_K2_E5_SHIFT 16 - #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_NEXT_OFFSET_K2_E5 (0xfff<<20) // Next Capability Offset. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_NEXT_OFFSET_K2_E5_SHIFT 20 +#define PCIEIP_REG_PCIEEP_PL16G_LC_DPAR_STAT_E5 0x0001b8UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PL16G_LC_DPAR_STAT_LDP_STATUS_E5 (0xffff<<0) // Local data parity mismatch status. + #define PCIEIP_REG_PCIEEP_PL16G_LC_DPAR_STAT_LDP_STATUS_E5_SHIFT 0 +#define PCIEIP_REG_SRIOV_BASE_REG_K2 0x0001b8UL //Access:RW DataWidth:0x20 // SR-IOV Capability Header. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_PCIE_EXTENDED_CAP_ID_K2 (0xffff<<0) // SRIOV Extended Capability ID. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_PCIE_EXTENDED_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_CAP_VERSION_K2 (0xf<<16) // Capability Version. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_CAP_VERSION_K2_SHIFT 16 + #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_NEXT_OFFSET_K2 (0xfff<<20) // Next Capability Offset. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_NEXT_OFFSET_K2_SHIFT 20 #define PCIEIP_REG_ARI_CAP_BB 0x0001b8UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by setting bit 6 of the EXT_CAP_ENA for EP, The capability can be enabled by default by defining SRIOV in version.v . #define PCIEIP_REG_ARI_CAP_ARI_EXT_CAP_ID_BB (0xffff<<0) // ARI Extended Capability ID. Hardwired to 0xE. #define PCIEIP_REG_ARI_CAP_ARI_EXT_CAP_ID_BB_SHIFT 0 @@ -1684,13 +2503,16 @@ #define PCIEIP_REG_ARI_CAP_CAP_VER_BB_SHIFT 16 #define PCIEIP_REG_ARI_CAP_NEXT_BB (0xfff<<20) // #define PCIEIP_REG_ARI_CAP_NEXT_BB_SHIFT 20 -#define PCIEIP_REG_CAPABILITIES_REG_K2_E5 0x0001bcUL //Access:RW DataWidth:0x20 // SR-IOV Capability Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_CAP_K2_E5 (0x1<<0) // VF Migration Capable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_CAP_K2_E5_SHIFT 0 - #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_ARI_CAP_HIER_PRESERVED_K2_E5 (0x1<<1) // ARI Capable Hierarchy Preserved. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_ARI_CAP_HIER_PRESERVED_K2_E5_SHIFT 1 - #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_INT_MSG_NUM_K2_E5 (0x3ff<<21) // VF Migration Interrupt Message Number. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_INT_MSG_NUM_K2_E5_SHIFT 21 +#define PCIEIP_REG_PCIEEP_PL16G_FRET_DPAR_STAT_E5 0x0001bcUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PL16G_FRET_DPAR_STAT_FRT_DP_STATUS_E5 (0xffff<<0) // First retimer data parity mismatch status. + #define PCIEIP_REG_PCIEEP_PL16G_FRET_DPAR_STAT_FRT_DP_STATUS_E5_SHIFT 0 +#define PCIEIP_REG_CAPABILITIES_REG_K2 0x0001bcUL //Access:RW DataWidth:0x20 // SR-IOV Capability Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_CAP_K2 (0x1<<0) // VF Migration Capable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_CAP_K2_SHIFT 0 + #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_ARI_CAP_HIER_PRESERVED_K2 (0x1<<1) // ARI Capable Hierarchy Preserved. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_ARI_CAP_HIER_PRESERVED_K2_SHIFT 1 + #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_INT_MSG_NUM_K2 (0x3ff<<21) // VF Migration Interrupt Message Number. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_INT_MSG_NUM_K2_SHIFT 21 #define PCIEIP_REG_ARI_CONTROL_REGISTER_BB 0x0001bcUL //Access:R DataWidth:0x20 // The RW value of this register is controlled by setting bit 6 of the EXT_CAP_ENA for EP. By default, this capability is disabled (i.e. reading this register will return zeroes). #define PCIEIP_REG_ARI_CONTROL_REGISTER_MFVC_FUNC_GROUP_CAP_BB (0x1<<0) // Hardwired to 0 #define PCIEIP_REG_ARI_CONTROL_REGISTER_MFVC_FUNC_GROUP_CAP_BB_SHIFT 0 @@ -1702,17 +2524,20 @@ #define PCIEIP_REG_ARI_CONTROL_REGISTER_NEXT_FUNCTION_NUMBER_BB_SHIFT 8 #define PCIEIP_REG_ARI_CONTROL_REGISTER_ARI_CTRL_BB (0xffff<<16) // Field is unused and is hardwired to 0. #define PCIEIP_REG_ARI_CONTROL_REGISTER_ARI_CTRL_BB_SHIFT 16 -#define PCIEIP_REG_STATUS_CONTROL_REG_K2_E5 0x0001c0UL //Access:RW DataWidth:0x20 // SR-IOV Control and Status Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_ENABLE_K2_E5 (0x1<<0) // VF Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_ENABLE_K2_E5_SHIFT 0 - #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_ENABLE_K2_E5 (0x1<<1) // VF Migration Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_ENABLE_K2_E5_SHIFT 1 - #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_INT_ENABLE_K2_E5 (0x1<<2) // VF Migration Interrupt Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_INT_ENABLE_K2_E5_SHIFT 2 - #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MSE_K2_E5 (0x1<<3) // VF Memory Space Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MSE_K2_E5_SHIFT 3 - #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_ARI_CAPABLE_HIER_K2_E5 (0x1<<4) // ARI Capable Hierarchy (Applies to endpoint only). For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W but read-value is not always same as write-value - #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_ARI_CAPABLE_HIER_K2_E5_SHIFT 4 +#define PCIEIP_REG_PCIEEP_PL16G_SRET_DPAR_STAT_E5 0x0001c0UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PL16G_SRET_DPAR_STAT_SRT_DP_STATUS_E5 (0xffff<<0) // Second retimer data parity mismatch status. + #define PCIEIP_REG_PCIEEP_PL16G_SRET_DPAR_STAT_SRT_DP_STATUS_E5_SHIFT 0 +#define PCIEIP_REG_STATUS_CONTROL_REG_K2 0x0001c0UL //Access:RW DataWidth:0x20 // SR-IOV Control and Status Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_ENABLE_K2 (0x1<<0) // VF Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_ENABLE_K2_SHIFT 0 + #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_ENABLE_K2 (0x1<<1) // VF Migration Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_ENABLE_K2_SHIFT 1 + #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_INT_ENABLE_K2 (0x1<<2) // VF Migration Interrupt Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_INT_ENABLE_K2_SHIFT 2 + #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MSE_K2 (0x1<<3) // VF Memory Space Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MSE_K2_SHIFT 3 + #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_ARI_CAPABLE_HIER_K2 (0x1<<4) // ARI Capable Hierarchy (Applies to endpoint only). For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W but read-value is not always same as write-value + #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_ARI_CAPABLE_HIER_K2_SHIFT 4 #define PCIEIP_REG_SRIOV_CAP_BB 0x0001c0UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by setting bit 7 of the EXT_CAP_ENA for EP, The capability can be enabled by default by defining SRIOV in version.v . #define PCIEIP_REG_SRIOV_CAP_SRIOV_EXT_CAP_ID_BB (0xffff<<0) // SRIOV Extended Capability ID. Hardwired to 0xE. #define PCIEIP_REG_SRIOV_CAP_SRIOV_EXT_CAP_ID_BB_SHIFT 0 @@ -1720,11 +2545,11 @@ #define PCIEIP_REG_SRIOV_CAP_SRCAP_VER_BB_SHIFT 16 #define PCIEIP_REG_SRIOV_CAP_NEXT_BB (0xfff<<20) // #define PCIEIP_REG_SRIOV_CAP_NEXT_BB_SHIFT 20 -#define PCIEIP_REG_SRIOV_INITIAL_VFS_K2_E5 0x0001c4UL //Access:RW DataWidth:0x20 // TotalVFs InitialVFs Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_REG_SRIOV_INITIAL_VFS_SRIOV_INITIAL_VFS_K2_E5 (0xffff<<0) // InitialVFs. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two InitialVFs registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_SRIOV_INITIAL_VFS_SRIOV_INITIAL_VFS_K2_E5_SHIFT 0 - #define PCIEIP_REG_SRIOV_INITIAL_VFS_SRIOV_TOTAL_VFS_K2_E5 (0xffff<<16) // Total VFs (Max Number of VFs). For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) - #define PCIEIP_REG_SRIOV_INITIAL_VFS_SRIOV_TOTAL_VFS_K2_E5_SHIFT 16 +#define PCIEIP_REG_SRIOV_INITIAL_VFS_K2 0x0001c4UL //Access:RW DataWidth:0x20 // TotalVFs InitialVFs Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_REG_SRIOV_INITIAL_VFS_SRIOV_INITIAL_VFS_K2 (0xffff<<0) // InitialVFs. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two InitialVFs registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_SRIOV_INITIAL_VFS_SRIOV_INITIAL_VFS_K2_SHIFT 0 + #define PCIEIP_REG_SRIOV_INITIAL_VFS_SRIOV_TOTAL_VFS_K2 (0xffff<<16) // Total VFs (Max Number of VFs). For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) + #define PCIEIP_REG_SRIOV_INITIAL_VFS_SRIOV_TOTAL_VFS_K2_SHIFT 16 #define PCIEIP_REG_SRIOV_CAPABILITIES_BB 0x0001c4UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_SRIOV_CAPABILITIES_UNUSED_1A_BB (0x1<<0) // The capability is hardwired to 0. #define PCIEIP_REG_SRIOV_CAPABILITIES_UNUSED_1A_BB_SHIFT 0 @@ -1732,11 +2557,28 @@ #define PCIEIP_REG_SRIOV_CAPABILITIES_ARI_CAP_HIER_PRESERVED_BB_SHIFT 1 #define PCIEIP_REG_SRIOV_CAPABILITIES_UNUSED_1_BB (0x3fffffff<<2) // The capability is hardwired to 0. #define PCIEIP_REG_SRIOV_CAPABILITIES_UNUSED_1_BB_SHIFT 2 -#define PCIEIP_REG_SRIOV_NUM_VFS_K2_E5 0x0001c8UL //Access:RW DataWidth:0x20 // NumVFs and Function Dependency Link Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two of these registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. - #define PCIEIP_REG_SRIOV_NUM_VFS_SRIOV_NUM_VFS_K2_E5 (0xffff<<0) // Number of Visible VFs. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: STATUS_CONTROL_REG.SRIOV_VF_ENABLE ? RW : RO - #define PCIEIP_REG_SRIOV_NUM_VFS_SRIOV_NUM_VFS_K2_E5_SHIFT 0 - #define PCIEIP_REG_SRIOV_NUM_VFS_SRIOV_FDL_K2_E5 (0xff<<16) // Functional Dependency Link. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_REG_SRIOV_NUM_VFS_SRIOV_FDL_K2_E5_SHIFT 16 +#define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_E5 0x0001c8UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L0DTP_E5 (0xf<<0) // Downstream port 16.0 GT/s transmitter preset 0. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L0DTP_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L0UTP_E5 (0xf<<4) // Upstream port 16.0 GT/s transmitter preset 0. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L0UTP_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L1DTP_E5 (0xf<<8) // Downstream port 16.0 GT/s transmitter preset 1. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L1DTP_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L1UTP_E5 (0xf<<12) // Upstream port 16.0 GT/s transmitter preset 1. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L1UTP_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L2DTP_E5 (0xf<<16) // Downstream port 16.0 GT/s transmitter preset 2. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L2DTP_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L2UTP_E5 (0xf<<20) // Upstream port 16.0 GT/s transmitter preset 2. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L2UTP_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L3DTP_E5 (0xf<<24) // Downstream port 16.0 GT/s transmitter preset 3. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L3DTP_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L3UTP_E5 (0xf<<28) // Upstream port 16.0 GT/s transmitter preset 3. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL0123_L3UTP_E5_SHIFT 28 +#define PCIEIP_REG_SRIOV_NUM_VFS_K2 0x0001c8UL //Access:RW DataWidth:0x20 // NumVFs and Function Dependency Link Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two of these registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. + #define PCIEIP_REG_SRIOV_NUM_VFS_SRIOV_NUM_VFS_K2 (0xffff<<0) // Number of Visible VFs. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: STATUS_CONTROL_REG.SRIOV_VF_ENABLE ? RW : RO + #define PCIEIP_REG_SRIOV_NUM_VFS_SRIOV_NUM_VFS_K2_SHIFT 0 + #define PCIEIP_REG_SRIOV_NUM_VFS_SRIOV_FDL_K2 (0xff<<16) // Functional Dependency Link. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_REG_SRIOV_NUM_VFS_SRIOV_FDL_K2_SHIFT 16 #define PCIEIP_REG_SRIOV_CONTROL_BB 0x0001c8UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_SRIOV_CONTROL_VF_ENABLE_BB (0x1<<0) // Enables/Disables VFs. #define PCIEIP_REG_SRIOV_CONTROL_VF_ENABLE_BB_SHIFT 0 @@ -1752,19 +2594,53 @@ #define PCIEIP_REG_SRIOV_CONTROL_UNUSED_2_BB_SHIFT 5 #define PCIEIP_REG_SRIOV_CONTROL_SRIOV_STATUS_BB (0xffff<<16) // The Status is hardwired to 0. #define PCIEIP_REG_SRIOV_CONTROL_SRIOV_STATUS_BB_SHIFT 16 -#define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_K2_E5 0x0001ccUL //Access:RW DataWidth:0x20 // VF Stride and Offset Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_SRIOV_VF_OFFSET_K2_E5 (0xffff<<0) // First VF Offset. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two First VF Offset registers at this address location; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register" determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_SRIOV_VF_OFFSET_K2_E5_SHIFT 0 - #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_SRIOV_VF_STRIDE_K2_E5 (0xffff<<16) // VF Stride. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two VF Stride registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register". determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_SRIOV_VF_STRIDE_K2_E5_SHIFT 16 +#define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_E5 0x0001ccUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L4DTP_E5 (0xf<<0) // Downstream port 16.0 GT/s transmitter preset 4. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L4DTP_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L4UTP_E5 (0xf<<4) // Upstream port 16.0 GT/s transmitter preset 4. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L4UTP_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L5DTP_E5 (0xf<<8) // Downstream port 16.0 GT/s transmitter preset 5. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L5DTP_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L5UTP_E5 (0xf<<12) // Upstream port 16.0 GT/s transmitter preset 5. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L5UTP_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L6DTP_E5 (0xf<<16) // Downstream port 16.0 GT/s transmitter preset 6. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L6DTP_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L6UTP_E5 (0xf<<20) // Upstream port 16.0 GT/s transmitter preset 6. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L6UTP_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L7DTP_E5 (0xf<<24) // Downstream port 16.0 GT/s transmitter preset 7. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L7DTP_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L7UTP_E5 (0xf<<28) // Upstream port 16.0 GT/s transmitter preset 7. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL4567_L7UTP_E5_SHIFT 28 +#define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_K2 0x0001ccUL //Access:RW DataWidth:0x20 // VF Stride and Offset Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_SRIOV_VF_OFFSET_K2 (0xffff<<0) // First VF Offset. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two First VF Offset registers at this address location; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register" determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_SRIOV_VF_OFFSET_K2_SHIFT 0 + #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_SRIOV_VF_STRIDE_K2 (0xffff<<16) // VF Stride. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two VF Stride registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register". determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_SRIOV_VF_STRIDE_K2_SHIFT 16 #define PCIEIP_REG_SRIOV_INITIALVF_BB 0x0001ccUL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_SRIOV_INITIALVF_INITIALVF_BB (0xffff<<0) // The Value in this register is based on programming in the private space at 0x600. This field indicates the number of VFs that are initially associated with the PF. #define PCIEIP_REG_SRIOV_INITIALVF_INITIALVF_BB_SHIFT 0 #define PCIEIP_REG_SRIOV_INITIALVF_TOTALVF_BB (0xffff<<16) // The Value in this register is based on programming in the private space at 0x600. This field indicates the maximum number of VFs that could be associated with PF. #define PCIEIP_REG_SRIOV_INITIALVF_TOTALVF_BB_SHIFT 16 -#define PCIEIP_REG_VF_DEVICE_ID_REG_K2_E5 0x0001d0UL //Access:RW DataWidth:0x20 // VF Device ID For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_REG_VF_DEVICE_ID_REG_SRIOV_VF_DEVICE_ID_K2_E5 (0xffff<<16) // VF Device ID. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_VF_DEVICE_ID_REG_SRIOV_VF_DEVICE_ID_K2_E5_SHIFT 16 +#define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_E5 0x0001d0UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L8DTP_E5 (0xf<<0) // Downstream port 16.0 GT/s transmitter preset 8. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L8DTP_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L8UTP_E5 (0xf<<4) // Upstream port 16.0 GT/s transmitter preset 8. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L8UTP_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L9DTP_E5 (0xf<<8) // Downstream port 16.0 GT/s transmitter preset 9. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L9DTP_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L9UTP_E5 (0xf<<12) // Upstream port 16.0 GT/s transmitter preset 9. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L9UTP_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L10DTP_E5 (0xf<<16) // Downstream port 16.0 GT/s transmitter preset 10. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L10DTP_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L10UTP_E5 (0xf<<20) // Upstream port 16.0 GT/s transmitter preset 10. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L10UTP_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L11DTP_E5 (0xf<<24) // Downstream port 16.0 GT/s transmitter preset 11. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L11DTP_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L11UTP_E5 (0xf<<28) // Upstream port 16.0 GT/s transmitter preset 11. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL891011_L11UTP_E5_SHIFT 28 +#define PCIEIP_REG_VF_DEVICE_ID_REG_K2 0x0001d0UL //Access:RW DataWidth:0x20 // VF Device ID For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_REG_VF_DEVICE_ID_REG_SRIOV_VF_DEVICE_ID_K2 (0xffff<<16) // VF Device ID. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_VF_DEVICE_ID_REG_SRIOV_VF_DEVICE_ID_K2_SHIFT 16 #define PCIEIP_REG_SRIOV_NUMVF_BB 0x0001d0UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_SRIOV_NUMVF_NUMVF_BB (0xffff<<0) // This field controls the number of VFs that are available. S/W sets this as part of creating VF. #define PCIEIP_REG_SRIOV_NUMVF_NUMVF_BB_SHIFT 0 @@ -1772,41 +2648,106 @@ #define PCIEIP_REG_SRIOV_NUMVF_FUNC_DEPENDENCY_LINK_BB_SHIFT 16 #define PCIEIP_REG_SRIOV_NUMVF_RSVD_1_BB (0xff<<24) // #define PCIEIP_REG_SRIOV_NUMVF_RSVD_1_BB_SHIFT 24 -#define PCIEIP_REG_SUP_PAGE_SIZES_REG_K2_E5 0x0001d4UL //Access:RW DataWidth:0x20 // Supported Page Sizes. +#define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_E5 0x0001d4UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L12DTP_E5 (0xf<<0) // Downstream port 16.0 GT/s transmitter preset 12. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L12DTP_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L12UTP_E5 (0xf<<4) // Upstream port 16.0 GT/s transmitter preset 12. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L12UTP_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L13DTP_E5 (0xf<<8) // Downstream port 16.0 GT/s transmitter preset 13. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L13DTP_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L13UTP_E5 (0xf<<12) // Upstream port 16.0 GT/s transmitter preset 13. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L13UTP_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L14DTP_E5 (0xf<<16) // Downstream port 16.0 GT/s transmitter preset 14. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L14DTP_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L14UTP_E5 (0xf<<20) // Upstream port 16.0 GT/s transmitter preset 14. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L14UTP_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L15DTP_E5 (0xf<<24) // Downstream port 16.0 GT/s transmitter preset 15. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L15DTP_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L15UTP_E5 (0xf<<28) // Upstream port 16.0 GT/s transmitter preset 15. + #define PCIEIP_REG_PCIEEP_PL16G_EQ_CTL12131415_L15UTP_E5_SHIFT 28 +#define PCIEIP_REG_SUP_PAGE_SIZES_REG_K2 0x0001d4UL //Access:RW DataWidth:0x20 // Supported Page Sizes. #define PCIEIP_REG_SRIOV_VFOFFSET_BB 0x0001d4UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_SRIOV_VFOFFSET_VF_OFFSET_BB (0xffff<<0) // The value in this register is based on programming in private space at 0x604. This field defines the Routing ID offset of the first VF associated with the PF. The First VFs RID is calculated by adding this field to the RID of the PF. #define PCIEIP_REG_SRIOV_VFOFFSET_VF_OFFSET_BB_SHIFT 0 #define PCIEIP_REG_SRIOV_VFOFFSET_VF_STRIDE_BB (0xffff<<16) // This field is hardwired to 1. #define PCIEIP_REG_SRIOV_VFOFFSET_VF_STRIDE_BB_SHIFT 16 -#define PCIEIP_REG_SYSTEM_PAGE_SIZE_REG_K2_E5 0x0001d8UL //Access:RW DataWidth:0x20 // System Page Size. +#define PCIEIP_REG_PCIEEP_MARGIN_EXT_CAP_HDR_E5 0x0001d8UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MARGIN_EXT_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCIE Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_MARGIN_EXT_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MARGIN_EXT_CAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_MARGIN_EXT_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MARGIN_EXT_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_MARGIN_EXT_CAP_HDR_NCO_E5_SHIFT 20 +#define PCIEIP_REG_SYSTEM_PAGE_SIZE_REG_K2 0x0001d8UL //Access:RW DataWidth:0x20 // System Page Size. #define PCIEIP_REG_SRIOV_VF_DEVICEID_BB 0x0001d8UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_SRIOV_VF_DEVICEID_RESERVED_BB (0xffff<<0) // #define PCIEIP_REG_SRIOV_VF_DEVICEID_RESERVED_BB_SHIFT 0 #define PCIEIP_REG_SRIOV_VF_DEVICEID_VF_DEVICEID_BB (0xffff<<16) // The value in this register is based on programming in private space at 0x604. This field contains Device ID for every VF belonging to this PF. #define PCIEIP_REG_SRIOV_VF_DEVICEID_VF_DEVICEID_BB_SHIFT 16 -#define PCIEIP_REG_SRIOV_BAR0_REG_K2_E5 0x0001dcUL //Access:RW DataWidth:0x20 // VF BAR0. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_TYPE_K2_E5 (0x3<<1) // VF BAR0 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_PREFETCH_K2_E5 (0x1<<3) // VF BAR0 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_START_K2_E5 (0xfffffff<<4) // VF BAR0 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_START_K2_E5_SHIFT 4 +#define PCIEIP_REG_PCIEEP_MRG_PORT_CAP_STAT_E5 0x0001dcUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_PORT_CAP_STAT_M_DRV_E5 (0x1<<0) // Margining uses driver software. + #define PCIEIP_REG_PCIEEP_MRG_PORT_CAP_STAT_M_DRV_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_PORT_CAP_STAT_M_RDY_E5 (0x1<<16) // Margining ready. + #define PCIEIP_REG_PCIEEP_MRG_PORT_CAP_STAT_M_RDY_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_PORT_CAP_STAT_M_SWRDY_E5 (0x1<<17) // Margining software ready. + #define PCIEIP_REG_PCIEEP_MRG_PORT_CAP_STAT_M_SWRDY_E5_SHIFT 17 +#define PCIEIP_REG_SRIOV_BAR0_REG_K2 0x0001dcUL //Access:RW DataWidth:0x20 // VF BAR0. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_TYPE_K2 (0x3<<1) // VF BAR0 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_TYPE_K2_SHIFT 1 + #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_PREFETCH_K2 (0x1<<3) // VF BAR0 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_PREFETCH_K2_SHIFT 3 + #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_START_K2 (0xfffffff<<4) // VF BAR0 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_START_K2_SHIFT 4 #define PCIEIP_REG_SRIOV_SUPPORTEDPAGESIZE_BB 0x0001dcUL //Access:R DataWidth:0x20 // This value in this register is based on programming in private space at 0x60C. Default indicates support from 4K to 4M. -#define PCIEIP_REG_SRIOV_BAR1_REG_K2_E5 0x0001e0UL //Access:RW DataWidth:0x20 // VF BAR1. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_TYPE_K2_E5 (0x3<<1) // VF BAR1 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_PREFETCH_K2_E5 (0x1<<3) // VF BAR1 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_START_K2_E5 (0xfffffff<<4) // VF BAR1 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_START_K2_E5_SHIFT 4 +#define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_E5 0x0001e0UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_RNUM_E5 (0x7<<0) // Receiver number for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_RNUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_MT_E5 (0x7<<3) // Margin type for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_MT_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_UM_E5 (0x1<<6) // Usage model for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_UM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_MPL_E5 (0xff<<8) // Margin payload for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_MPL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_RNUM_STAT_E5 (0x7<<16) // Receiver number (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_RNUM_STAT_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_MT_STAT_E5 (0x7<<19) // Margin type (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_MT_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_UM_STAT_E5 (0x1<<22) // Usage model (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_UM_STAT_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT0_PL_STAT_E5_SHIFT 24 +#define PCIEIP_REG_SRIOV_BAR1_REG_K2 0x0001e0UL //Access:RW DataWidth:0x20 // VF BAR1. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_TYPE_K2 (0x3<<1) // VF BAR1 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_TYPE_K2_SHIFT 1 + #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_PREFETCH_K2 (0x1<<3) // VF BAR1 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_PREFETCH_K2_SHIFT 3 + #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_START_K2 (0xfffffff<<4) // VF BAR1 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_START_K2_SHIFT 4 #define PCIEIP_REG_SRIOV_SYSTEMPAGESIZE_BB 0x0001e0UL //Access:RW DataWidth:0x20 // Default value is 4K . This field defines the page size system will use to map VFs mem address. -#define PCIEIP_REG_SRIOV_BAR2_REG_K2_E5 0x0001e4UL //Access:RW DataWidth:0x20 // VF BAR2. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_TYPE_K2_E5 (0x3<<1) // VF BAR2 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_PREFETCH_K2_E5 (0x1<<3) // VF BAR2 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_START_K2_E5 (0xfffffff<<4) // VF BAR2 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_START_K2_E5_SHIFT 4 +#define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_E5 0x0001e4UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_RNUM_E5 (0x7<<0) // Receiver number for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_RNUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_MT_E5 (0x7<<3) // Margin type for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_MT_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_UM_E5 (0x1<<6) // Usage model for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_UM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_MPL_E5 (0xff<<8) // Margin payload for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_MPL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_RNUM_STAT_E5 (0x7<<16) // Receiver number (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_RNUM_STAT_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_MT_STAT_E5 (0x7<<19) // Margin type (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_MT_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_UM_STAT_E5 (0x1<<22) // Usage model (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_UM_STAT_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT1_PL_STAT_E5_SHIFT 24 +#define PCIEIP_REG_SRIOV_BAR2_REG_K2 0x0001e4UL //Access:RW DataWidth:0x20 // VF BAR2. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_TYPE_K2 (0x3<<1) // VF BAR2 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_TYPE_K2_SHIFT 1 + #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_PREFETCH_K2 (0x1<<3) // VF BAR2 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_PREFETCH_K2_SHIFT 3 + #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_START_K2 (0xfffffff<<4) // VF BAR2 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_START_K2_SHIFT 4 #define PCIEIP_REG_VF_BAR0_BB 0x0001e4UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR0 register programs the base address for the memory space mapped by the VFs belonging to this PF. This register can be combined with VF_BAR2 to make a 64-bit address. Each VF BAR describes the amount of address space consumed by a single VF. Path = i_cfg_func.i_cfg_public.i_cfg_dec #define PCIEIP_REG_VF_BAR0_MEM_SPACE_BB (0x1<<0) // This bit indicates that VF_BAR0 maps a memory space and is always read as 0. #define PCIEIP_REG_VF_BAR0_MEM_SPACE_BB_SHIFT 0 @@ -1818,21 +2759,55 @@ #define PCIEIP_REG_VF_BAR0_UNUSED0_BB_SHIFT 4 #define PCIEIP_REG_VF_BAR0_ADDRESS_BB (0xfffff<<12) // These bits set the address within a 32-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR1 to create a full 64 bit address decode. Only the bits that addresses blocks bigger than the setting in the VFBAR0_SIZE(reg 0x608) value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_VF_BAR0_ADDRESS_BB_SHIFT 12 -#define PCIEIP_REG_SRIOV_BAR3_REG_K2_E5 0x0001e8UL //Access:RW DataWidth:0x20 // VF BAR3. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_TYPE_K2_E5 (0x3<<1) // VF BAR3 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_PREFETCH_K2_E5 (0x1<<3) // VF BAR3 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_START_K2_E5 (0xfffffff<<4) // VF BAR3 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_START_K2_E5_SHIFT 4 +#define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_E5 0x0001e8UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_RNUM_E5 (0x7<<0) // Receiver number for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_RNUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_MT_E5 (0x7<<3) // Margin type for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_MT_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_UM_E5 (0x1<<6) // Usage model for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_UM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_MPL_E5 (0xff<<8) // Margin payload for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_MPL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_RNUM_STAT_E5 (0x7<<16) // Receiver number (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_RNUM_STAT_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_MT_STAT_E5 (0x7<<19) // Margin type (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_MT_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_UM_STAT_E5 (0x1<<22) // Usage model (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_UM_STAT_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT2_PL_STAT_E5_SHIFT 24 +#define PCIEIP_REG_SRIOV_BAR3_REG_K2 0x0001e8UL //Access:RW DataWidth:0x20 // VF BAR3. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_TYPE_K2 (0x3<<1) // VF BAR3 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_TYPE_K2_SHIFT 1 + #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_PREFETCH_K2 (0x1<<3) // VF BAR3 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_PREFETCH_K2_SHIFT 3 + #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_START_K2 (0xfffffff<<4) // VF BAR3 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_START_K2_SHIFT 4 #define PCIEIP_REG_VF_BAR1_BB 0x0001e8UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR1 register programs the upper half of the base address for the memory space mapped by the card onto the PCI bus. -#define PCIEIP_REG_SRIOV_BAR4_REG_K2_E5 0x0001ecUL //Access:RW DataWidth:0x20 // VF BAR4. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_TYPE_K2_E5 (0x3<<1) // VF BAR4 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_PREFETCH_K2_E5 (0x1<<3) // VF BAR4 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_START_K2_E5 (0xfffff<<4) // VF BAR4 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_START_K2_E5_SHIFT 4 +#define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_E5 0x0001ecUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_RNUM_E5 (0x7<<0) // Receiver number for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_RNUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_MT_E5 (0x7<<3) // Margin type for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_MT_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_UM_E5 (0x1<<6) // Usage model for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_UM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_MPL_E5 (0xff<<8) // Margin payload for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_MPL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_RNUM_STAT_E5 (0x7<<16) // Receiver number (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_RNUM_STAT_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_MT_STAT_E5 (0x7<<19) // Margin type (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_MT_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_UM_STAT_E5 (0x1<<22) // Usage model (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_UM_STAT_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT3_PL_STAT_E5_SHIFT 24 +#define PCIEIP_REG_SRIOV_BAR4_REG_K2 0x0001ecUL //Access:RW DataWidth:0x20 // VF BAR4. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_TYPE_K2 (0x3<<1) // VF BAR4 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_TYPE_K2_SHIFT 1 + #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_PREFETCH_K2 (0x1<<3) // VF BAR4 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_PREFETCH_K2_SHIFT 3 + #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_START_K2 (0xfffff<<4) // VF BAR4 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_START_K2_SHIFT 4 #define PCIEIP_REG_VF_BAR2_BB 0x0001ecUL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR2 register programs the base address for the memory space mapped by the VFs belonging to this PF. This register can be combined with VF_BAR3 to make a 64-bit address. Each VF BAR describes the amount of address space consumed by a single VF. Path = i_cfg_func.i_cfg_public.i_cfg_dec #define PCIEIP_REG_VF_BAR2_MEM_SPACE_BB (0x1<<0) // This bit indicates that VF_BAR2 maps a memory space and is always read as 0. #define PCIEIP_REG_VF_BAR2_MEM_SPACE_BB_SHIFT 0 @@ -1844,19 +2819,53 @@ #define PCIEIP_REG_VF_BAR2_UNUSED0_BB_SHIFT 4 #define PCIEIP_REG_VF_BAR2_ADDRESS_BB (0xfffff<<12) // These bits set the address within a 32-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR3 to create a full 64 bit address decode. Only the bits that addresses blocks bigger than the setting in the VFBAR2_SIZE(reg 0x608) value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_VF_BAR2_ADDRESS_BB_SHIFT 12 -#define PCIEIP_REG_SRIOV_BAR5_REG_K2_E5 0x0001f0UL //Access:RW DataWidth:0x20 // VF BAR5. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_TYPE_K2_E5 (0x3<<1) // VF BAR5 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_PREFETCH_K2_E5 (0x1<<3) // VF BAR5 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_START_K2_E5 (0xfffffff<<4) // VF BAR5 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_START_K2_E5_SHIFT 4 +#define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_E5 0x0001f0UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_RNUM_E5 (0x7<<0) // Receiver number for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_RNUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_MT_E5 (0x7<<3) // Margin type for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_MT_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_UM_E5 (0x1<<6) // Usage model for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_UM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_MPL_E5 (0xff<<8) // Margin payload for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_MPL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_RNUM_STAT_E5 (0x7<<16) // Receiver number (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_RNUM_STAT_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_MT_STAT_E5 (0x7<<19) // Margin type (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_MT_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_UM_STAT_E5 (0x1<<22) // Usage model (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_UM_STAT_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT4_PL_STAT_E5_SHIFT 24 +#define PCIEIP_REG_SRIOV_BAR5_REG_K2 0x0001f0UL //Access:RW DataWidth:0x20 // VF BAR5. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_TYPE_K2 (0x3<<1) // VF BAR5 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_TYPE_K2_SHIFT 1 + #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_PREFETCH_K2 (0x1<<3) // VF BAR5 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_PREFETCH_K2_SHIFT 3 + #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_START_K2 (0xfffffff<<4) // VF BAR5 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_START_K2_SHIFT 4 #define PCIEIP_REG_VF_BAR3_BB 0x0001f0UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR3 register programs the upper half of the base address for the memory space mapped by the card onto the PCI bus. -#define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_K2_E5 0x0001f4UL //Access:R DataWidth:0x20 // VF Migration State Array Offset For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_BIR_K2_E5 (0x7<<0) // VF Migration State BIR. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_BIR_K2_E5_SHIFT 0 - #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_OFFSET_K2_E5 (0x1fffffff<<3) // VF Migration State Offset. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_OFFSET_K2_E5_SHIFT 3 +#define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_E5 0x0001f4UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_RNUM_E5 (0x7<<0) // Receiver number for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_RNUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_MT_E5 (0x7<<3) // Margin type for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_MT_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_UM_E5 (0x1<<6) // Usage model for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_UM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_MPL_E5 (0xff<<8) // Margin payload for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_MPL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_RNUM_STAT_E5 (0x7<<16) // Receiver number (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_RNUM_STAT_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_MT_STAT_E5 (0x7<<19) // Margin type (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_MT_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_UM_STAT_E5 (0x1<<22) // Usage model (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_UM_STAT_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT5_PL_STAT_E5_SHIFT 24 +#define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_K2 0x0001f4UL //Access:R DataWidth:0x20 // VF Migration State Array Offset For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_BIR_K2 (0x7<<0) // VF Migration State BIR. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_BIR_K2_SHIFT 0 + #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_OFFSET_K2 (0x1fffffff<<3) // VF Migration State Offset. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_OFFSET_K2_SHIFT 3 #define PCIEIP_REG_VF_BAR4_BB 0x0001f4UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR4 register programs the base address for the memory space mapped by the VFs belonging to this PF. This register can be combined with VF_BAR5 to make a 64-bit address. Each VF BAR describes the amount of address space consumed by a single VF. Path = i_cfg_func.i_cfg_public.i_cfg_dec #define PCIEIP_REG_VF_BAR4_MEM_SPACE_BB (0x1<<0) // This bit indicates that VF_BAR4 maps a memory space and is always read as 0. #define PCIEIP_REG_VF_BAR4_MEM_SPACE_BB_SHIFT 0 @@ -1868,34 +2877,85 @@ #define PCIEIP_REG_VF_BAR4_UNUSED0_BB_SHIFT 4 #define PCIEIP_REG_VF_BAR4_ADDRESS_BB (0xfffff<<12) // These bits set the address within a 32-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR5 to create a full 64 bit address decode. Only the bits that addresses blocks bigger than the setting in the VFBAR4_SIZE(reg 0x620) value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_VF_BAR4_ADDRESS_BB_SHIFT 12 -#define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_K2_E5 0x0001f8UL //Access:RW DataWidth:0x20 // TPH Extended Capability Header. - #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_K2_E5 (0xffff<<0) // TPH Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_K2_E5 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_K2_E5_SHIFT 16 - #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_K2_E5 (0xfff<<20) // Next Capability Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_K2_E5_SHIFT 20 +#define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_E5 0x0001f8UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_RNUM_E5 (0x7<<0) // Receiver number for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_RNUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_MT_E5 (0x7<<3) // Margin type for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_MT_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_UM_E5 (0x1<<6) // Usage model for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_UM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_MPL_E5 (0xff<<8) // Margin payload for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_MPL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_RNUM_STAT_E5 (0x7<<16) // Receiver number (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_RNUM_STAT_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_MT_STAT_E5 (0x7<<19) // Margin type (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_MT_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_UM_STAT_E5 (0x1<<22) // Usage model (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_UM_STAT_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT6_PL_STAT_E5_SHIFT 24 +#define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_K2 0x0001f8UL //Access:RW DataWidth:0x20 // TPH Extended Capability Header. + #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_K2 (0xffff<<0) // TPH Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_K2 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_K2_SHIFT 16 + #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_K2 (0xfff<<20) // Next Capability Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_K2_SHIFT 20 #define PCIEIP_REG_VF_BAR5_BB 0x0001f8UL //Access:RW DataWidth:0x20 // The 32-bit VF_BAR5 register programs the upper half of the base address for the memory space mapped by the card onto the PCI bus. -#define PCIEIP_REG_TPH_REQ_CAP_REG_REG_K2_E5 0x0001fcUL //Access:RW DataWidth:0x20 // TPH Requestor Capability Register. SRIOV Note: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common register, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PF TPH_REQ_CAP_REG_REG register. - #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_K2_E5 (0x1<<0) // No ST Mode Supported. - #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_K2_E5_SHIFT 0 - #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_K2_E5 (0x1<<1) // Interrupt Vector Mode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_K2_E5_SHIFT 1 - #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_K2_E5 (0x1<<2) // Device Specific Mode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_K2_E5_SHIFT 2 - #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_K2_E5 (0x1<<8) // Extended TPH Requester Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_K2_E5_SHIFT 8 - #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_K2_E5 (0x1<<9) // ST Table Location Bit 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_K2_E5_SHIFT 9 - #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_K2_E5 (0x1<<10) // ST Table Location Bit 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_K2_E5_SHIFT 10 - #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_K2_E5 (0x7ff<<16) // ST Table Size. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky. - #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_K2_E5_SHIFT 16 -#define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_K2_E5 0x000200UL //Access:RW DataWidth:0x20 // TPH Requestor Control Register. - #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_K2_E5 (0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_K2_E5_SHIFT 0 - #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_K2_E5 (0x3<<8) // TPH Requester Enable Bit. - #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_K2_E5_SHIFT 8 +#define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_E5 0x0001fcUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_RNUM_E5 (0x7<<0) // Receiver number for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_RNUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_MT_E5 (0x7<<3) // Margin type for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_MT_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_UM_E5 (0x1<<6) // Usage model for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_UM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_MPL_E5 (0xff<<8) // Margin payload for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_MPL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_RNUM_STAT_E5 (0x7<<16) // Receiver number (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_RNUM_STAT_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_MT_STAT_E5 (0x7<<19) // Margin type (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_MT_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_UM_STAT_E5 (0x1<<22) // Usage model (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_UM_STAT_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT7_PL_STAT_E5_SHIFT 24 +#define PCIEIP_REG_TPH_REQ_CAP_REG_REG_K2 0x0001fcUL //Access:RW DataWidth:0x20 // TPH Requestor Capability Register. SRIOV Note: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common register, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PF TPH_REQ_CAP_REG_REG register. + #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_K2 (0x1<<0) // No ST Mode Supported. + #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_K2_SHIFT 0 + #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_K2 (0x1<<1) // Interrupt Vector Mode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_K2_SHIFT 1 + #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_K2 (0x1<<2) // Device Specific Mode Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_K2_SHIFT 2 + #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_K2 (0x1<<8) // Extended TPH Requester Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_K2_SHIFT 8 + #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_K2 (0x1<<9) // ST Table Location Bit 0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_K2_SHIFT 9 + #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_K2 (0x1<<10) // ST Table Location Bit 1. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_K2_SHIFT 10 + #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_K2 (0x7ff<<16) // ST Table Size. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky. + #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_K2_SHIFT 16 +#define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_E5 0x000200UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_RNUM_E5 (0x7<<0) // Receiver number for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_RNUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_MT_E5 (0x7<<3) // Margin type for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_MT_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_UM_E5 (0x1<<6) // Usage model for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_UM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_MPL_E5 (0xff<<8) // Margin payload for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_MPL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_RNUM_STAT_E5 (0x7<<16) // Receiver number (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_RNUM_STAT_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_MT_STAT_E5 (0x7<<19) // Margin type (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_MT_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_UM_STAT_E5 (0x1<<22) // Usage model (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_UM_STAT_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT8_PL_STAT_E5_SHIFT 24 +#define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_K2 0x000200UL //Access:RW DataWidth:0x20 // TPH Requestor Control Register. + #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_K2 (0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_K2_SHIFT 0 + #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_K2 (0x3<<8) // TPH Requester Enable Bit. + #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_K2_SHIFT 8 #define PCIEIP_REG_PTM_EXTENDED_CAP_BB 0x000200UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by setting bit 0 of the EXT3_CAP_ENA for EP, The capability can be enabled by default by defining PCIE_PTM_SUPP in version.v and setting bit 0 of EXT3_CAP_ENA. #define PCIEIP_REG_PTM_EXTENDED_CAP_PTM_EXT_CAP_ID_BB (0xffff<<0) // Vendor Specific Extended Capability ID. #define PCIEIP_REG_PTM_EXTENDED_CAP_PTM_EXT_CAP_ID_BB_SHIFT 0 @@ -1903,14 +2963,48 @@ #define PCIEIP_REG_PTM_EXTENDED_CAP_CAP_VER_BB_SHIFT 16 #define PCIEIP_REG_PTM_EXTENDED_CAP_NEXT_BB (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. #define PCIEIP_REG_PTM_EXTENDED_CAP_NEXT_BB_SHIFT 20 -#define PCIEIP_REG_TPH_ST_TABLE_REG_0_K2_E5 0x000204UL //Access:RW DataWidth:0x20 // TPH ST Table Register 0. - #define PCIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_K2_E5 (0xff<<0) // ST Table 0 Lower Byte. Note: The access attributes of this field are as follows: - Dbi: this field is RW or Tie to 0 by table size configure - #define PCIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_K2_E5_SHIFT 0 - #define PCIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_K2_E5 (0xff<<8) // ST Table 0 Upper Byte. Note: The access attributes of this field are as follows: - Dbi: this field is RW or Tie to 0 by table size configure - #define PCIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_K2_E5_SHIFT 8 +#define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_E5 0x000204UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_RNUM_E5 (0x7<<0) // Receiver number for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_RNUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_MT_E5 (0x7<<3) // Margin type for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_MT_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_UM_E5 (0x1<<6) // Usage model for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_UM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_MPL_E5 (0xff<<8) // Margin payload for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_MPL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_RNUM_STAT_E5 (0x7<<16) // Receiver number (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_RNUM_STAT_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_MT_STAT_E5 (0x7<<19) // Margin type (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_MT_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_UM_STAT_E5 (0x1<<22) // Usage model (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_UM_STAT_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT9_PL_STAT_E5_SHIFT 24 +#define PCIEIP_REG_TPH_ST_TABLE_REG_0_K2 0x000204UL //Access:RW DataWidth:0x20 // TPH ST Table Register 0. + #define PCIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_K2 (0xff<<0) // ST Table 0 Lower Byte. Note: The access attributes of this field are as follows: - Dbi: this field is RW or Tie to 0 by table size configure + #define PCIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_K2_SHIFT 0 + #define PCIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_K2 (0xff<<8) // ST Table 0 Upper Byte. Note: The access attributes of this field are as follows: - Dbi: this field is RW or Tie to 0 by table size configure + #define PCIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_K2_SHIFT 8 #define PCIEIP_REG_PTM_CAP_REG_BB 0x000204UL //Access:R DataWidth:0x20 // The RW value of this register is controlled by setting bit 0 of the EXT3_CAP_ENA for EP. #define PCIEIP_REG_PTM_CAP_REG_PTM_REQUESTER_CAPABLE_BB (0x1<<0) // Device implements the PTM Requester role. #define PCIEIP_REG_PTM_CAP_REG_PTM_REQUESTER_CAPABLE_BB_SHIFT 0 +#define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_E5 0x000208UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_RNUM_E5 (0x7<<0) // Receiver number for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_RNUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_MT_E5 (0x7<<3) // Margin type for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_MT_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_UM_E5 (0x1<<6) // Usage model for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_UM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_MPL_E5 (0xff<<8) // Margin payload for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_MPL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_RNUM_STAT_E5 (0x7<<16) // Receiver number (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_RNUM_STAT_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_MT_STAT_E5 (0x7<<19) // Margin type (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_MT_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_UM_STAT_E5 (0x1<<22) // Usage model (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_UM_STAT_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT10_PL_STAT_E5_SHIFT 24 #define PCIEIP_REG_PTM_CTRL_REG_BB 0x000208UL //Access:RW DataWidth:0x20 // The RW value of this register is controlled by setting bit 0 of the EXT3_CAP_ENA for EP. #define PCIEIP_REG_PTM_CTRL_REG_PTM_ENABLED_BB (0x1<<0) // When Set, Function is permitted to participate in PTM mechanism #define PCIEIP_REG_PTM_CTRL_REG_PTM_ENABLED_BB_SHIFT 0 @@ -1920,6 +3014,40 @@ #define PCIEIP_REG_PTM_CTRL_REG_UNUSED0_BB_SHIFT 2 #define PCIEIP_REG_PTM_CTRL_REG_PTM_EFFECTIVE_GRANULARITY_BB (0xff<<8) // Field provides information on the expected accuracy of the PTM clock. For endpoints, system software programs this field to the value representing the max Local Clock granularity reported by the PTM Root. #define PCIEIP_REG_PTM_CTRL_REG_PTM_EFFECTIVE_GRANULARITY_BB_SHIFT 8 +#define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_E5 0x00020cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_RNUM_E5 (0x7<<0) // Receiver number for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_RNUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_MT_E5 (0x7<<3) // Margin type for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_MT_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_UM_E5 (0x1<<6) // Usage model for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_UM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_MPL_E5 (0xff<<8) // Margin payload for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_MPL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_RNUM_STAT_E5 (0x7<<16) // Receiver number (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_RNUM_STAT_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_MT_STAT_E5 (0x7<<19) // Margin type (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_MT_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_UM_STAT_E5 (0x1<<22) // Usage model (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_UM_STAT_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT11_PL_STAT_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_E5 0x000210UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_RNUM_E5 (0x7<<0) // Receiver number for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_RNUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_MT_E5 (0x7<<3) // Margin type for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_MT_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_UM_E5 (0x1<<6) // Usage model for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_UM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_MPL_E5 (0xff<<8) // Margin payload for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_MPL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_RNUM_STAT_E5 (0x7<<16) // Receiver number (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_RNUM_STAT_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_MT_STAT_E5 (0x7<<19) // Margin type (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_MT_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_UM_STAT_E5 (0x1<<22) // Usage model (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_UM_STAT_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT12_PL_STAT_E5_SHIFT 24 #define PCIEIP_REG_ATS_CAP_BB 0x000210UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by setting bit 9 of the EXT_CAP_ENA for EP, The capability can be enabled by default by defining ATS_ON in version.v . #define PCIEIP_REG_ATS_CAP_ATS_EXT_CAP_ID_BB (0xffff<<0) // ATS Extended Capability ID. Hardwired to 0xF. #define PCIEIP_REG_ATS_CAP_ATS_EXT_CAP_ID_BB_SHIFT 0 @@ -1927,6 +3055,23 @@ #define PCIEIP_REG_ATS_CAP_ATSCAP_VER_BB_SHIFT 16 #define PCIEIP_REG_ATS_CAP_ATS_NEXT_BB (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. #define PCIEIP_REG_ATS_CAP_ATS_NEXT_BB_SHIFT 20 +#define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_E5 0x000214UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_RNUM_E5 (0x7<<0) // Receiver number for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_RNUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_MT_E5 (0x7<<3) // Margin type for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_MT_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_UM_E5 (0x1<<6) // Usage model for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_UM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_MPL_E5 (0xff<<8) // Margin payload for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_MPL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_RNUM_STAT_E5 (0x7<<16) // Receiver number (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_RNUM_STAT_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_MT_STAT_E5 (0x7<<19) // Margin type (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_MT_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_UM_STAT_E5 (0x1<<22) // Usage model (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_UM_STAT_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT13_PL_STAT_E5_SHIFT 24 #define PCIEIP_REG_ATS_CONTROL_BB 0x000214UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_ATS_CONTROL_ATS_INVLD_QDEPTH_BB (0x1f<<0) // The number of Invalidate Requests that the function can accept before putting backpressure on the upstream request. the value in this field is controlled by programming in private register at 0x630 #define PCIEIP_REG_ATS_CONTROL_ATS_INVLD_QDEPTH_BB_SHIFT 0 @@ -1940,6 +3085,47 @@ #define PCIEIP_REG_ATS_CONTROL_RESERVED_Z_BB_SHIFT 21 #define PCIEIP_REG_ATS_CONTROL_ATS_ENABLE_BB (0x1<<31) // When set, function is enabled to cache translations. #define PCIEIP_REG_ATS_CONTROL_ATS_ENABLE_BB_SHIFT 31 +#define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_E5 0x000218UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_RNUM_E5 (0x7<<0) // Receiver number for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_RNUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_MT_E5 (0x7<<3) // Margin type for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_MT_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_UM_E5 (0x1<<6) // Usage model for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_UM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_MPL_E5 (0xff<<8) // Margin payload for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_MPL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_RNUM_STAT_E5 (0x7<<16) // Receiver number (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_RNUM_STAT_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_MT_STAT_E5 (0x7<<19) // Margin type (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_MT_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_UM_STAT_E5 (0x1<<22) // Usage model (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_UM_STAT_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT14_PL_STAT_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_E5 0x00021cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_RNUM_E5 (0x7<<0) // Receiver number for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_RNUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_MT_E5 (0x7<<3) // Margin type for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_MT_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_UM_E5 (0x1<<6) // Usage model for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_UM_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_MPL_E5 (0xff<<8) // Margin payload for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_MPL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_RNUM_STAT_E5 (0x7<<16) // Receiver number (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_RNUM_STAT_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_MT_STAT_E5 (0x7<<19) // Margin type (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_MT_STAT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_UM_STAT_E5 (0x1<<22) // Usage model (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_UM_STAT_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_PL_STAT_E5 (0xff<<24) // Margin payload (status) for this lane. + #define PCIEIP_REG_PCIEEP_MRG_LANE_CTL_STAT15_PL_STAT_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_SRIOV_CAP_HDR_E5 0x000220UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_SRIOV_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCIE Express extended capability. + #define PCIEIP_REG_PCIEEP_SRIOV_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_SRIOV_CAP_HDR_CV_E5 (0xf<<16) // Capability version. + #define PCIEIP_REG_PCIEEP_SRIOV_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_SRIOV_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. + #define PCIEIP_REG_PCIEEP_SRIOV_CAP_HDR_NCO_E5_SHIFT 20 #define PCIEIP_REG_RBAR_EXT_CAP_BB 0x000220UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by setting bit 8 of the EXT_CAP_ENA for EP, The capability can be enabled by default by defining RESIZE_BAR in version.v . #define PCIEIP_REG_RBAR_EXT_CAP_RBAR_EXT_CAP_ID_BB (0xffff<<0) // RBAR Extended Capability ID. Hardwired to 0x15. #define PCIEIP_REG_RBAR_EXT_CAP_RBAR_EXT_CAP_ID_BB_SHIFT 0 @@ -1947,6 +3133,15 @@ #define PCIEIP_REG_RBAR_EXT_CAP_RBARCAP_VER_BB_SHIFT 16 #define PCIEIP_REG_RBAR_EXT_CAP_RBAR_NEXT_BB (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. #define PCIEIP_REG_RBAR_EXT_CAP_RBAR_NEXT_BB_SHIFT 20 +#define PCIEIP_REG_PCIEEP_SRIOV_CAP_E5 0x000224UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_SRIOV_CAP_VFMC_E5 (0x1<<0) // VF migration capable. + #define PCIEIP_REG_PCIEEP_SRIOV_CAP_VFMC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_SRIOV_CAP_ARICHP_E5 (0x1<<1) // ARI capable hierarchy preserved. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_SRIOV_CAP_ARICHP_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_SRIOV_CAP_TENBIT_TRC_E5 (0x1<<2) // VF 10-bit tag requester supported. + #define PCIEIP_REG_PCIEEP_SRIOV_CAP_TENBIT_TRC_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_SRIOV_CAP_VFMIMN_E5 (0x3ff<<21) // VF migration interrupt message number. + #define PCIEIP_REG_PCIEEP_SRIOV_CAP_VFMIMN_E5_SHIFT 21 #define PCIEIP_REG_RBAR_CAP_BB 0x000224UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_RBAR_CAP_SIZE_CAPABILITY_BB (0xf<<0) // unused #define PCIEIP_REG_RBAR_CAP_SIZE_CAPABILITY_BB_SHIFT 0 @@ -1974,6 +3169,21 @@ #define PCIEIP_REG_RBAR_CAP_SIZE_1G_CAPABILITY_BB_SHIFT 14 #define PCIEIP_REG_RBAR_CAP_SIZE_512G_TO_2G_CAPABILITY_BB (0x1ff<<15) // unsupported. #define PCIEIP_REG_RBAR_CAP_SIZE_512G_TO_2G_CAPABILITY_BB_SHIFT 15 +#define PCIEIP_REG_PCIEEP_SRIOV_CTL_E5 0x000228UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_SRIOV_CTL_VFE_E5 (0x1<<0) // VF enable. + #define PCIEIP_REG_PCIEEP_SRIOV_CTL_VFE_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_SRIOV_CTL_ME_E5 (0x1<<1) // VF migration enable. + #define PCIEIP_REG_PCIEEP_SRIOV_CTL_ME_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_SRIOV_CTL_MIE_E5 (0x1<<2) // VF migration interrupt enable. + #define PCIEIP_REG_PCIEEP_SRIOV_CTL_MIE_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_SRIOV_CTL_MSE_E5 (0x1<<3) // VF MSE. + #define PCIEIP_REG_PCIEEP_SRIOV_CTL_MSE_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_SRIOV_CTL_ACH_E5 (0x1<<4) // ARI capable hierarchy. 0 = All PFs have non-ARI capable hierarchy. 1 = All PFs have ARI capable hierarchy. The value in this field in PF0 is used for all other physical functions. + #define PCIEIP_REG_PCIEEP_SRIOV_CTL_ACH_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_SRIOV_CTL_TENBIT_TRE_E5 (0x1<<5) // VF 10-bit Tag Requester Enable. + #define PCIEIP_REG_PCIEEP_SRIOV_CTL_TENBIT_TRE_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_SRIOV_CTL_MS_E5 (0x1<<16) // VF migration status. + #define PCIEIP_REG_PCIEEP_SRIOV_CTL_MS_E5_SHIFT 16 #define PCIEIP_REG_RBAR_CTRL_BB 0x000228UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_RBAR_CTRL_RBAR_INDX_BB (0x7<<0) // Indicates which BAR supports a negotiable size. #define PCIEIP_REG_RBAR_CTRL_RBAR_INDX_BB_SHIFT 0 @@ -1983,6 +3193,16 @@ #define PCIEIP_REG_RBAR_CTRL_NUM_RBAR_BB_SHIFT 5 #define PCIEIP_REG_RBAR_CTRL_BAR_SIZE_BB (0x1f<<8) // When this reg is programmed, value is immediately reflected in the size of the resource, as encoded in the number of RO bits in BAR. #define PCIEIP_REG_RBAR_CTRL_BAR_SIZE_BB_SHIFT 8 +#define PCIEIP_REG_PCIEEP_SRIOV_VFS_E5 0x00022cUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_SRIOV_VFS_IVF_E5 (0xffff<<0) // Initial VFs. This field is writable through PEM()_CFG_WR. + #define PCIEIP_REG_PCIEEP_SRIOV_VFS_IVF_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_SRIOV_VFS_TVF_E5 (0xffff<<16) // Total VFs. Read-only copy of PCIEEP_SRIOV_VFS[IVF]. + #define PCIEIP_REG_PCIEEP_SRIOV_VFS_TVF_E5_SHIFT 16 +#define PCIEIP_REG_PCIEEP_SRIOV_NVF_E5 0x000230UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_SRIOV_NVF_NVF_E5 (0xffff<<0) // Number of VFs that are visible. + #define PCIEIP_REG_PCIEEP_SRIOV_NVF_NVF_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_SRIOV_NVF_FDL_E5 (0xff<<16) // Function dependency link. Enables support for VF dependency link. + #define PCIEIP_REG_PCIEEP_SRIOV_NVF_FDL_E5_SHIFT 16 #define PCIEIP_REG_TPH_EXTENDED_CAP_BB 0x000230UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by setting bit 0 of the EXT2_CAP_ENA for EP, By default, this capability is enabled The capability can be enabled by default by defining TPH_ON in version.v and setting bit 0 of EXT2_CAP_ENA. #define PCIEIP_REG_TPH_EXTENDED_CAP_TPH_EXT_CAP_ID_BB (0xffff<<0) // Vendor Specific Extended Capability ID. #define PCIEIP_REG_TPH_EXTENDED_CAP_TPH_EXT_CAP_ID_BB_SHIFT 0 @@ -1990,6 +3210,11 @@ #define PCIEIP_REG_TPH_EXTENDED_CAP_CAP_VER_BB_SHIFT 16 #define PCIEIP_REG_TPH_EXTENDED_CAP_NEXT_BB (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. #define PCIEIP_REG_TPH_EXTENDED_CAP_NEXT_BB_SHIFT 20 +#define PCIEIP_REG_PCIEEP_SRIOV_FO_E5 0x000234UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_SRIOV_FO_FO_E5 (0xffff<<0) // First VF offset. Reset values: _ PF0: 0x1. There are two first VF offset registers; one for each ARI capable and non-ARI capable hierarchies. The PCIEEP_SRIOV_CTL[ACH] determines which one is being used for SR-IOV, and which one is accessed by a read request. This field is writable through PEM()_CFG_WR, PEM()_CFG_WR[ADDR[16]] determines which register is updated. 0 = Accesses non-ARI capable hierarchy copy. 1 = Accesses ARI capable hierarchy copy. + #define PCIEIP_REG_PCIEEP_SRIOV_FO_FO_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_SRIOV_FO_VFS_E5 (0xffff<<16) // VF stride. Reset values: _ ARI: 0x1. _ non-ARI: 0x1. There are two VF stride registers; one for each ARI capable and non-ARI capable hierarchies. The PCIEEP_SRIOV_CTL[ACH] determines which one is being used for SR-IOV, and which one is accessed by a read request. This field is writable through PEM()_CFG_WR, PEM()_CFG_WR[ADDR[16]] determines which VFS register is updated. 0 = accesses non-ARI capable hierarchy copy of VFS. 1 = accesses ARI capable hierarchy copy of VFS. + #define PCIEIP_REG_PCIEEP_SRIOV_FO_VFS_E5_SHIFT 16 #define PCIEIP_REG_TPH_REQ_CAPABILITY_BB 0x000234UL //Access:R DataWidth:0x20 // The RW value of this register is controlled by setting bit 0 of the EXT2_CAP_ENA for EP. By default, this capability is disabled (i.e. reading this register will return zeroes). #define PCIEIP_REG_TPH_REQ_CAPABILITY_NO_ST_MODE_SUPPORTED_BB (0x1<<0) // Function supports NO ST mode of operation. This mode is required to be supported. #define PCIEIP_REG_TPH_REQ_CAPABILITY_NO_ST_MODE_SUPPORTED_BB_SHIFT 0 @@ -2007,6 +3232,9 @@ #define PCIEIP_REG_TPH_REQ_CAPABILITY_UNUSED1_BB_SHIFT 11 #define PCIEIP_REG_TPH_REQ_CAPABILITY_ST_TABLE_SIZE_BB (0x7ff<<16) // Software reads this field to determine the STTable Size N, whihc is encoded as N-1. So a returned value of 16, indicates a table size of 17. The value in this field can be programmed by programming the TPH_CAP register in the private space. #define PCIEIP_REG_TPH_REQ_CAPABILITY_ST_TABLE_SIZE_BB_SHIFT 16 +#define PCIEIP_REG_PCIEEP_SRIOV_DEV_E5 0x000238UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_SRIOV_DEV_VFDEV_E5 (0xffff<<16) // VF device ID. + #define PCIEIP_REG_PCIEEP_SRIOV_DEV_VFDEV_E5_SHIFT 16 #define PCIEIP_REG_TPH_REQ_CONTROL_BB 0x000238UL //Access:RW DataWidth:0x20 // The RW value of this register is controlled by setting bit 0 of the EXT2_CAP_ENA for EP. #define PCIEIP_REG_TPH_REQ_CONTROL_ST_MODE_SELECT_BB (0x7<<0) // Value indicates ST mode of operation #define PCIEIP_REG_TPH_REQ_CONTROL_ST_MODE_SELECT_BB_SHIFT 0 @@ -2014,6 +3242,8 @@ #define PCIEIP_REG_TPH_REQ_CONTROL_UNUSED0_BB_SHIFT 3 #define PCIEIP_REG_TPH_REQ_CONTROL_TPH_REQUESTER_ENABLE_BB (0x3<<8) // Value indicates if and how TPH is enabled #define PCIEIP_REG_TPH_REQ_CONTROL_TPH_REQUESTER_ENABLE_BB_SHIFT 8 +#define PCIEIP_REG_PCIEEP_SRIOV_SUPPS_E5 0x00023cUL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_SRIOV_PS_E5 0x000240UL //Access:RW DataWidth:0x20 // #define PCIEIP_REG_PML1SUB_CAPID_BB 0x000240UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by setting bit 2 of the EXT2_CAP_ENA for EP, By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining PMCR_L1_SUBSTATES_ENA in version.v and setting bit 2 of EXT2_CAP_ENA. This capability when present , will only exist in function 0 of a multi-function device. #define PCIEIP_REG_PML1SUB_CAPID_L1SUB_EXT_CAP_ID_BB (0xffff<<0) // Vendor Specific Extended Capability ID. Value is from corresponding field in private register. #define PCIEIP_REG_PML1SUB_CAPID_L1SUB_EXT_CAP_ID_BB_SHIFT 0 @@ -2021,6 +3251,15 @@ #define PCIEIP_REG_PML1SUB_CAPID_CAP_VER_BB_SHIFT 16 #define PCIEIP_REG_PML1SUB_CAPID_NEXT_BB (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. #define PCIEIP_REG_PML1SUB_CAPID_NEXT_BB_SHIFT 20 +#define PCIEIP_REG_PCIEEP_SRIOV_BAR0L_E5 0x000244UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_SRIOV_BAR0L_MSPC_E5 (0x1<<0) // Memory space indicator: 0 = BAR 0 is a memory BAR. 1 = BAR 0 is an I/O BAR. + #define PCIEIP_REG_PCIEEP_SRIOV_BAR0L_MSPC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_SRIOV_BAR0L_TYP_E5 (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. + #define PCIEIP_REG_PCIEEP_SRIOV_BAR0L_TYP_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_SRIOV_BAR0L_PF_E5 (0x1<<3) // Prefetchable. + #define PCIEIP_REG_PCIEEP_SRIOV_BAR0L_PF_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_SRIOV_BAR0L_LBAB_E5 (0x1ffff<<15) // Lower bits of the VF BAR 0 base address. + #define PCIEIP_REG_PCIEEP_SRIOV_BAR0L_LBAB_E5_SHIFT 15 #define PCIEIP_REG_PML1_SUB_CAP_REG_BB 0x000244UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_PML1_SUB_CAP_REG_PM_L1_2_SUPP_BB (0x1<<0) // Advertize L1_2 capability support for PM #define PCIEIP_REG_PML1_SUB_CAP_REG_PM_L1_2_SUPP_BB_SHIFT 0 @@ -2044,6 +3283,7 @@ #define PCIEIP_REG_PML1_SUB_CAP_REG_L1SUB_PWR_ON_VALUE_BB_SHIFT 19 #define PCIEIP_REG_PML1_SUB_CAP_REG_RESERVED_BB (0xff<<24) // #define PCIEIP_REG_PML1_SUB_CAP_REG_RESERVED_BB_SHIFT 24 +#define PCIEIP_REG_PCIEEP_SRIOV_BAR0U_E5 0x000248UL //Access:RW DataWidth:0x20 // #define PCIEIP_REG_PML1_SUB_CONTROL1_BB 0x000248UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_PML1_SUB_CONTROL1_PM_L1_2_ENABLE_BB (0x1<<0) // When set, PM L1.2 is enabled. #define PCIEIP_REG_PML1_SUB_CONTROL1_PM_L1_2_ENABLE_BB_SHIFT 0 @@ -2065,6 +3305,13 @@ #define PCIEIP_REG_PML1_SUB_CONTROL1_RESERVED_BB_SHIFT 26 #define PCIEIP_REG_PML1_SUB_CONTROL1_LTR_L1_2_THRESHOLD_SCALE_BB (0x7<<29) // Provides a scale for the L1_2 LTR threshold value #define PCIEIP_REG_PML1_SUB_CONTROL1_LTR_L1_2_THRESHOLD_SCALE_BB_SHIFT 29 +#define PCIEIP_REG_PCIEEP_SRIOV_BAR2L_E5 0x00024cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_SRIOV_BAR2L_TYP_E5 (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. + #define PCIEIP_REG_PCIEEP_SRIOV_BAR2L_TYP_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_SRIOV_BAR2L_PF_E5 (0x1<<3) // Prefetchable. + #define PCIEIP_REG_PCIEEP_SRIOV_BAR2L_PF_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_SRIOV_BAR2L_LBAB_E5 (0xfff<<20) // Lower bits of the VF BAR 2 base address. + #define PCIEIP_REG_PCIEEP_SRIOV_BAR2L_LBAB_E5_SHIFT 20 #define PCIEIP_REG_PML1_SUB_CONTROL2_BB 0x00024cUL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_PML1_SUB_CONTROL2_T_POWER_ON_SCALE_BB (0x3<<0) // This field along with value sets the min amount of time that the Port must wait in L1.2 exit after sampling CLKREQ# asserted before actively driving the interface. This field specifies the scale used #define PCIEIP_REG_PML1_SUB_CONTROL2_T_POWER_ON_SCALE_BB_SHIFT 0 @@ -2074,118 +3321,230 @@ #define PCIEIP_REG_PML1_SUB_CONTROL2_T_POWER_ON_VALUE_BB_SHIFT 3 #define PCIEIP_REG_PML1_SUB_CONTROL2_RSVD_BB (0xffffff<<8) // #define PCIEIP_REG_PML1_SUB_CONTROL2_RSVD_BB_SHIFT 8 -#define PCIEIP_REG_LTR_CAP_HDR_REG_K2_E5 0x000284UL //Access:RW DataWidth:0x20 // LTR Extended Capability Header. - #define PCIEIP_REG_LTR_CAP_HDR_REG_CAP_ID_K2_E5 (0xffff<<0) // LTR Extended Capacity ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_LTR_CAP_HDR_REG_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_LTR_CAP_HDR_REG_CAP_VERSION_K2_E5 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_LTR_CAP_HDR_REG_CAP_VERSION_K2_E5_SHIFT 16 - #define PCIEIP_REG_LTR_CAP_HDR_REG_NEXT_OFFSET_K2_E5 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_LTR_CAP_HDR_REG_NEXT_OFFSET_K2_E5_SHIFT 20 -#define PCIEIP_REG_LTR_LATENCY_REG_K2_E5 0x000288UL //Access:RW DataWidth:0x20 // LTR Max Snoop and No-Snoop Latency Register. - #define PCIEIP_REG_LTR_LATENCY_REG_MAX_SNOOP_LAT_K2_E5 (0x3ff<<0) // Max Snoop Latency Value. - #define PCIEIP_REG_LTR_LATENCY_REG_MAX_SNOOP_LAT_K2_E5_SHIFT 0 - #define PCIEIP_REG_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_K2_E5 (0x7<<10) // Max Snoop Latency Scale. - #define PCIEIP_REG_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_K2_E5_SHIFT 10 - #define PCIEIP_REG_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_K2_E5 (0x3ff<<16) // Max No-Snoop Latency Value. - #define PCIEIP_REG_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_K2_E5_SHIFT 16 - #define PCIEIP_REG_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_K2_E5 (0x7<<26) // Max No-Snoop Latency Scale. - #define PCIEIP_REG_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_K2_E5_SHIFT 26 -#define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_K2_E5 0x00028cUL //Access:RW DataWidth:0x20 // Vendor-Specific Extended Capability Header. - #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_K2_E5 (0xffff<<0) // PCI Express Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_CAP_VERSION_K2_E5 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_CAP_VERSION_K2_E5_SHIFT 16 - #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_K2_E5 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_K2_E5_SHIFT 20 -#define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_K2_E5 0x000290UL //Access:R DataWidth:0x20 // Vendor-Specific Header. - #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_K2_E5 (0xffff<<0) // VSEC ID. - #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_K2_E5 (0xf<<16) // VSEC Rev. - #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_K2_E5_SHIFT 16 - #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_K2_E5 (0xfff<<20) // VSEC Length. - #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_K2_E5_SHIFT 20 -#define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_K2_E5 0x000294UL //Access:RW DataWidth:0x20 // Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG viewport register. - Setting the EVENT_COUNTER_ENABLE field in this register enables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Setting the EVENT_COUNTER_CLEAR field in this register clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Reading the EVENT_COUNTER_STATUS field in this register returns the Enable status of the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_K2_E5 (0x3<<0) // Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and you can clear all event counters at once by writing the 'all clear' code. The read value is always '0'. - 00: no change - 01: per clear - 10: no change - 11: all clear - Other: reserved - #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_K2_E5_SHIFT 0 - #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_K2_E5 (0x7<<2) // Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default, all event counters are disabled. You can enable/disable a specific Event Counter by writing the 'per event off' or 'per event on' codes. You can enable/disable all event counters by writing the 'all on' or 'all off' codes. The read value is always '0'. - 000: no change - 001: per event off - 010: no change - 011: per event on - 100: no change - 101: all off - 110: no change - 111: all on - #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_K2_E5_SHIFT 2 - #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_K2_E5 (0x1<<7) // Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky. - #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_K2_E5_SHIFT 7 - #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_K2_E5 (0xf<<8) // Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky. - #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_K2_E5_SHIFT 8 - #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_K2_E5 (0xfff<<16) // Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event number(8-bit: 0..0x13) within the Group For example: - 0x000: Ebuf Overflow - 0x001: Ebuf Underrun - .. - 0x700: Tx Memory Write - 0x713: Rx Message TLP For detailed definitions of Group number and Event number, see the RAS DES chapter in the Databook. Note: This register field is sticky. - #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_K2_E5_SHIFT 16 -#define PCIEIP_REG_EVENT_COUNTER_DATA_REG_K2_E5 0x000298UL //Access:R DataWidth:0x20 // Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details, see the RAS DES section in the Core Operations chapter of the Databook. -#define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_K2_E5 0x00029cUL //Access:RW DataWidth:0x20 // Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details, see the RAS DES section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_K2_E5 (0x1<<0) // Timer Start. - 0: Start/Restart - 1: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This register field is sticky. - #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_K2_E5_SHIFT 0 - #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_K2_E5 (0xff<<8) // Time-based Duration Select. Selects the duration of time-based analysis. When "manual control" is selected and TIMER_START is set to '1', this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1: 1ms - 0x2: 10ms - 0x3: 100ms - 0x4: 1s - 0x5: 2s - 0x6: 4s - Else: Reserved Note: This register field is sticky. - #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_K2_E5_SHIFT 8 - #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_K2_E5 (0xff<<24) // Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT), and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: - Core_clk Cycles. Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when TIME_BASED_REPORT_SELECT=0x00] * TIME_BASED_ANALYSIS_DATA - Aux_clk Cycles. Total time in ps is [Period of platform specific clock] * TIME_BASED_ANALYSIS_DATA - Data Bytes. Actual amount of bytes is 16 * TIME_BASED_ANALYSIS_DATA Core_clk Cycles - 0x00: Duration of 1 cycle - 0x01: TxL0s - 0x02: RxL0s - 0x03: L0 - 0x04: L1 (Rsvd when aux_clk is supplied from the platform specific clock during L1, L1.1 or L1.2) - 0x07: Configuration/Recovery Aux_clk Cycles - 0x05: L1.1 - 0x06: L1.2 Data Bytes - 0x20: Tx TLP Bytes - 0x21: Rx TLP Bytes - Else: Rsvd Note: This register field is sticky. - #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_K2_E5_SHIFT 24 -#define PCIEIP_REG_TIME_BASED_ANALYSIS_DATA_REG_K2_E5 0x0002a0UL //Access:R DataWidth:0x20 // Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG For more details, see the RAS DES section in the Core Operations chapter of the Databook. -#define PCIEIP_REG_EINJ_ENABLE_REG_K2_E5 0x0002bcUL //Access:RW DataWidth:0x20 // Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1: Sequence Number Error: EINJ1_SEQNUM_REG - 2: DLLP Error: EINJ2_DLLP_REG - 3: Symbol DataK Mask Error or Sync Header Error: EINJ3_SYMBOL_REG - 4: FC Credit Update Error: EINJ4_FC_REG - 5: TLP Duplicate/Nullify Error: EINJ5_SP_TLP_REG - 6: Specific TLP Error: EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG After the errors have been inserted by core, it will clear each bit here. For more details, see the RAS DES section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_K2_E5 (0x1<<0) // Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details, see the EINJ0_CRC_REG register. Note: This register field is sticky. - #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_K2_E5_SHIFT 0 - #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_K2_E5 (0x1<<1) // Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details, see the EINJ1_SEQNUM_REG register. Note: This register field is sticky. - #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_K2_E5_SHIFT 1 - #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_K2_E5 (0x1<<2) // Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details, see the EINJ2_DLLP_REG register. Note: This register field is sticky. - #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_K2_E5_SHIFT 2 - #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_K2_E5 (0x1<<3) // Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details, see the EINJ3_SYMBOL_REG register. Note: This register field is sticky. - #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_K2_E5_SHIFT 3 - #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_K2_E5 (0x1<<4) // Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details, see the EINJ4_FC_REG register. Note: This register field is sticky. - #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_K2_E5_SHIFT 4 - #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_K2_E5 (0x1<<5) // Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details, see the EINJ5_SP_TLP_REG register. Note: This register field is sticky. - #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_K2_E5_SHIFT 5 - #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_K2_E5 (0x1<<6) // Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT =0. You can set this bit to '1' when you have disabled the address translation by setting ADDR_TRANSLATION_SUPPORT_EN=0. For more details, see the EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG registers. Note: This register field is sticky. - #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_K2_E5_SHIFT 6 -#define PCIEIP_REG_EINJ0_CRC_REG_K2_E5 0x0002c0UL //Access:RW DataWidth:0x20 // Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC, and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link Retry starts. - 16-bit CRC of ACK/NAK DLLPs. Bad DLLP occurs at the receiver side; Replay NUM Rollover occurs. - 16-bit CRC of UpdateFC DLLPs. Error insertion continues for the specific time; LTSSM transitions to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - ECRC. If ECRC check is enabled, ECRC error is detected at the receiver side. - FCRC. Framing error will be detected, TLP is discarded, and the LTSSM transitions to Recovery state. - Parity of TSOS. Error insertion continues for the specific time; LTSSM Recovery/Configuration timeout will occur. - Parity of SKPOS. Lane error will be detected at the receiver side. - #define PCIEIP_REG_EINJ0_CRC_REG_EINJ0_COUNT_K2_E5 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the counter value is 0x00 and ERROR_INJECTION0_ENABLE=1, the errors are inserted until ERROR_INJECTION0_ENABLE is set to '0'. Note: This register field is sticky. - #define PCIEIP_REG_EINJ0_CRC_REG_EINJ0_COUNT_K2_E5_SHIFT 0 - #define PCIEIP_REG_EINJ0_CRC_REG_EINJ0_CRC_TYPE_K2_E5 (0xf<<8) // Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC error injection - 0100b: TLP's FCRC error injection (128b/130b) - 0101b: Parity error of TSOS (128b/130b) - 0110b: Parity error of SKPOS (128b/130b) Rx Path - 1000b: LCRC error injection - 1011b: ECRC error injection - Others: Reserved Note: This register field is sticky. - #define PCIEIP_REG_EINJ0_CRC_REG_EINJ0_CRC_TYPE_K2_E5_SHIFT 8 -#define PCIEIP_REG_EINJ1_SEQNUM_REG_K2_E5 0x0002c4UL //Access:RW DataWidth:0x20 // Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: - ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048 - (AckNak_Seq_Num - ACKD_SEQ) mod 4096 >= 2048 TLP is treated as Duplicate TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ - (NEXT_RCV_SEQ - Sequence Number) mod 4096 <= 2048 TLP is treated as Bad TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ and - (NEXT_RCV_SEQ - Sequence Number) mod 4096 > 2048 - #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_COUNT_K2_E5 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION1_ENABLE=1, the errors are inserted until ERROR_INJECTION1_ENABLE is set to '0'. Note: This register field is sticky. - #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_COUNT_K2_E5_SHIFT 0 - #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_K2_E5 (0x1<<8) // Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky. - #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_K2_E5_SHIFT 8 - #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_K2_E5 (0x1fff<<16) // Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095 For example: - Set Type, SEQ# and Count -- EINJ1_SEQNUM_TYPE =0 (Insert errors into new TLPs) -- EINJ1_BAD_SEQNUM =0x1FFD (represents -3) -- EINJ1_COUNT =1 - Enable Error Injection -- ERROR_INJECTION1_ENABLE =1 - Send a TLP From the Core's Application Interface -- Assume SEQ#5 is given to the TLP. - The SEQ# is Changed to #2 by the Error Injection Function in Layer2. -- 5 + (-3) = 2 - The TLP with SEQ#2 is Transmitted to PCIe Link. Note: This register field is sticky. - #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_K2_E5_SHIFT 16 -#define PCIEIP_REG_EINJ2_DLLP_REG_K2_E5 0x0002c8UL //Access:RW DataWidth:0x20 // Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the transmitter of the TLPs and then Data Link Retry will occur. - If "Update FC DLLP's transmission block" is selected, LTSSM will transition to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - If "Always Transmission for NAK DLLP" is selected, Data Link Retry will occur at the transmitter of the TLPs. Furthermore, Replay NUM Rollover will occur when the transmitter has been requested four times to send the TLP with the same sequence number. - #define PCIEIP_REG_EINJ2_DLLP_REG_EINJ2_COUNT_K2_E5 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION2_ENABLE =1, the errors are inserted until ERROR_INJECTION2_ENABLE is set to '0'. This register is affected only when EINJ2_DLLP_TYPE =2'10b. Note: This register field is sticky. - #define PCIEIP_REG_EINJ2_DLLP_REG_EINJ2_COUNT_K2_E5_SHIFT 0 - #define PCIEIP_REG_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_K2_E5 (0x3<<8) // DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky. - #define PCIEIP_REG_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_K2_E5_SHIFT 8 -#define PCIEIP_REG_EINJ3_SYMBOL_REG_K2_E5 0x0002ccUL //Access:RW DataWidth:0x20 // Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used, this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeout of the LTSSM. - If END/EDB/STP/SDP is selected, TLP/DLLP will be discarded at the receiver side. When 128b/130b encoding is used, this register controls error insertion into the sync-header. - #define PCIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_COUNT_K2_E5 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION3_ENABLE =1, the errors are inserted until ERROR_INJECTION3_ENABLE is set to '0'. Note: This register field is sticky. - #define PCIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_COUNT_K2_E5_SHIFT 0 - #define PCIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_K2_E5 (0x7<<8) // Error Type. 8b/10b encoding - Mask K symbol. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b: COM/PAD(TS2 Order set) - 011b: COM/FTS(FTS Order set) - 100b: COM/IDL(E-Idle Order set) - 101b: END/EDB Symbol - 110b: STP/SDP Symbol - 111b: COM/SKP(SKP Order set) 128b/130b encoding - Change sync header. - 000b: Invert sync header - Others: Reserved Note: This register field is sticky. - #define PCIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_K2_E5_SHIFT 8 -#define PCIEIP_REG_EINJ4_FC_REG_K2_E5 0x0002d0UL //Access:RW DataWidth:0x20 // Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit - Completion TLP Header credit - Posted TLP Data credit - Non-Posted TLP Data credit - Completion TLP Data credit These errors are not correctable while error insertion is enabled. Receiver buffer overflow error might occur. - #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_COUNT_K2_E5 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION4_ENABLE =1, the errors are inserted until ERROR_INJECTION4_ENABLE is set to '0'. Note: This register field is sticky. - #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_COUNT_K2_E5_SHIFT 0 - #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_K2_E5 (0x7<<8) // Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit value control - 101b: Non-Posted TLP Data Credit value control - 110b: Completion TLP Data Credit value control - 111b: Reserved Note: This register field is sticky. - #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_K2_E5_SHIFT 8 - #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_VC_NUMBER_K2_E5 (0x7<<12) // VC Number. Indicates target VC Number. Note: This register field is sticky. - #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_VC_NUMBER_K2_E5_SHIFT 12 - #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_K2_E5 (0x1fff<<16) // Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095 Note: This register field is sticky. - #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_K2_E5_SHIFT 16 -#define PCIEIP_REG_EINJ5_SP_TLP_REG_K2_E5 0x0002d4UL //Access:RW DataWidth:0x20 // Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP, the core initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These TLPs will be duplicate TLPs at the receiver side. - For Nullified TLP, the TLPs that the core transmits are changed into nullified TLPs and the original TLPs are stored in the retry buffer. The receiver of these TLPs will detect the lack of seq# and send NAK DLLP at the next TLP. Then the original TLPs are sent from retry buffer and the data controls are recovered. For 128 bit core or more than 128 bit, the core inserts errors the number of times of EINJ5_COUNT but doesn't ensure that the errors are continuously inserted into TLPs. - #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_COUNT_K2_E5 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION5_ENABLE =1, the errors are inserted until ERROR_INJECTION5_ENABLE is set to '0'. Note: This register field is sticky. - #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_COUNT_K2_E5_SHIFT 0 - #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_K2_E5 (0x1<<8) // Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky. - #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_K2_E5_SHIFT 8 -#define PCIEIP_REG_EINJ6_COMPARE_POINT_H0_REG_K2_E5 0x0002d8UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register. -#define PCIEIP_REG_EINJ6_COMPARE_POINT_H1_REG_K2_E5 0x0002dcUL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register. -#define PCIEIP_REG_EINJ6_COMPARE_POINT_H2_REG_K2_E5 0x0002e0UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register. -#define PCIEIP_REG_EINJ6_COMPARE_POINT_H3_REG_K2_E5 0x0002e4UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register. -#define PCIEIP_REG_EINJ6_COMPARE_VALUE_H0_REG_K2_E5 0x0002e8UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register. -#define PCIEIP_REG_EINJ6_COMPARE_VALUE_H1_REG_K2_E5 0x0002ecUL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register. -#define PCIEIP_REG_EINJ6_COMPARE_VALUE_H2_REG_K2_E5 0x0002f0UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register. -#define PCIEIP_REG_EINJ6_COMPARE_VALUE_H3_REG_K2_E5 0x0002f4UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register. -#define PCIEIP_REG_EINJ6_CHANGE_POINT_H0_REG_K2_E5 0x0002f8UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0. -#define PCIEIP_REG_EINJ6_CHANGE_POINT_H1_REG_K2_E5 0x0002fcUL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0. -#define PCIEIP_REG_EINJ6_CHANGE_POINT_H2_REG_K2_E5 0x000300UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0. +#define PCIEIP_REG_PCIEEP_SRIOV_BAR2U_E5 0x000250UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_SRIOV_BAR4L_E5 0x000254UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_SRIOV_BAR4L_TYP_E5 (0x3<<1) // BAR type: 0x0 = 32-bit BAR. 0x2 = 64-bit BAR. + #define PCIEIP_REG_PCIEEP_SRIOV_BAR4L_TYP_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_SRIOV_BAR4L_PF_E5 (0x1<<3) // Prefetchable. + #define PCIEIP_REG_PCIEEP_SRIOV_BAR4L_PF_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_SRIOV_BAR4L_LBAB_E5 (0x7ffff<<13) // Lower bits of the VF BAR 4 base address. + #define PCIEIP_REG_PCIEEP_SRIOV_BAR4L_LBAB_E5_SHIFT 13 +#define PCIEIP_REG_PCIEEP_SRIOV_BAR4U_E5 0x000258UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_SRIOV_MS_E5 0x00025cUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_SRIOV_MS_MSBIR_E5 (0x7<<0) // VF migration state BIR. + #define PCIEIP_REG_PCIEEP_SRIOV_MS_MSBIR_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_SRIOV_MS_MSO_E5 (0x1fffffff<<3) // VF migration state offset. + #define PCIEIP_REG_PCIEEP_SRIOV_MS_MSO_E5_SHIFT 3 +#define PCIEIP_REG_PCIEEP_TPH_EXT_CAP_HDR_E5 0x000260UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_TPH_EXT_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_TPH_EXT_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_TPH_EXT_CAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_TPH_EXT_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_TPH_EXT_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_TPH_EXT_CAP_HDR_NCO_E5_SHIFT 20 +#define PCIEIP_REG_PCIEEP_TPH_REQ_CAP_E5 0x000264UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_TPH_REQ_CAP_NOST_E5 (0x1<<0) // No ST mode supported. + #define PCIEIP_REG_PCIEEP_TPH_REQ_CAP_NOST_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_TPH_REQ_CAP_INTV_E5 (0x1<<1) // Interrupt vector mode supported. + #define PCIEIP_REG_PCIEEP_TPH_REQ_CAP_INTV_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_TPH_REQ_CAP_DS_E5 (0x1<<2) // Device specific mode supported. + #define PCIEIP_REG_PCIEEP_TPH_REQ_CAP_DS_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_TPH_REQ_CAP_EXT_E5 (0x1<<8) // Extended TPH requester supported. This field is writable through PEM()_CFG_WR. However, Extended TPH requester is not supported. Therefore, the application must not write any value other than 0x0 to this field. + #define PCIEIP_REG_PCIEEP_TPH_REQ_CAP_EXT_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_TPH_REQ_CAP_STL0_E5 (0x1<<9) // Steering tag table bit 0. + #define PCIEIP_REG_PCIEEP_TPH_REQ_CAP_STL0_E5_SHIFT 9 + #define PCIEIP_REG_PCIEEP_TPH_REQ_CAP_STL1_E5 (0x1<<10) // Steering tag table bit 1. + #define PCIEIP_REG_PCIEEP_TPH_REQ_CAP_STL1_E5_SHIFT 10 + #define PCIEIP_REG_PCIEEP_TPH_REQ_CAP_STS_E5 (0x7ff<<16) // ST table size (limited by MSI-X table size). + #define PCIEIP_REG_PCIEEP_TPH_REQ_CAP_STS_E5_SHIFT 16 +#define PCIEIP_REG_PCIEEP_TPH_REQ_CTL_E5 0x000268UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_TPH_REQ_CTL_SMS_E5 (0x7<<0) // ST mode select. + #define PCIEIP_REG_PCIEEP_TPH_REQ_CTL_SMS_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_TPH_REQ_CTL_CREN_E5 (0x3<<8) // TPH requestor enable. + #define PCIEIP_REG_PCIEEP_TPH_REQ_CTL_CREN_E5_SHIFT 8 +#define PCIEIP_REG_PCIEEP_TPH_ST_TABLE_E5 0x00026cUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_TPH_ST_TABLE_STL_E5 (0xff<<0) // ST table 0 lower byte. Access can be tied to 0 by table size config. + #define PCIEIP_REG_PCIEEP_TPH_ST_TABLE_STL_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_TPH_ST_TABLE_STH_E5 (0xff<<8) // ST table 0 upper byte. Access can be tied to 0 by table size config. + #define PCIEIP_REG_PCIEEP_TPH_ST_TABLE_STH_E5_SHIFT 8 +#define PCIEIP_REG_LTR_CAP_HDR_REG_K2 0x000284UL //Access:RW DataWidth:0x20 // LTR Extended Capability Header. + #define PCIEIP_REG_LTR_CAP_HDR_REG_CAP_ID_K2 (0xffff<<0) // LTR Extended Capacity ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_LTR_CAP_HDR_REG_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_LTR_CAP_HDR_REG_CAP_VERSION_K2 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_LTR_CAP_HDR_REG_CAP_VERSION_K2_SHIFT 16 + #define PCIEIP_REG_LTR_CAP_HDR_REG_NEXT_OFFSET_K2 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_LTR_CAP_HDR_REG_NEXT_OFFSET_K2_SHIFT 20 +#define PCIEIP_REG_LTR_LATENCY_REG_K2 0x000288UL //Access:RW DataWidth:0x20 // LTR Max Snoop and No-Snoop Latency Register. + #define PCIEIP_REG_LTR_LATENCY_REG_MAX_SNOOP_LAT_K2 (0x3ff<<0) // Max Snoop Latency Value. + #define PCIEIP_REG_LTR_LATENCY_REG_MAX_SNOOP_LAT_K2_SHIFT 0 + #define PCIEIP_REG_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_K2 (0x7<<10) // Max Snoop Latency Scale. + #define PCIEIP_REG_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_K2_SHIFT 10 + #define PCIEIP_REG_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_K2 (0x3ff<<16) // Max No-Snoop Latency Value. + #define PCIEIP_REG_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_K2_SHIFT 16 + #define PCIEIP_REG_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_K2 (0x7<<26) // Max No-Snoop Latency Scale. + #define PCIEIP_REG_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_K2_SHIFT 26 +#define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_K2 0x00028cUL //Access:RW DataWidth:0x20 // Vendor-Specific Extended Capability Header. + #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_K2 (0xffff<<0) // PCI Express Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_CAP_VERSION_K2 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_CAP_VERSION_K2_SHIFT 16 + #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_K2 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_K2_SHIFT 20 +#define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_K2 0x000290UL //Access:R DataWidth:0x20 // Vendor-Specific Header. + #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_K2 (0xffff<<0) // VSEC ID. + #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_K2_SHIFT 0 + #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_K2 (0xf<<16) // VSEC Rev. + #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_K2_SHIFT 16 + #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_K2 (0xfff<<20) // VSEC Length. + #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_K2_SHIFT 20 +#define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_K2 0x000294UL //Access:RW DataWidth:0x20 // Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG viewport register. - Setting the EVENT_COUNTER_ENABLE field in this register enables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Setting the EVENT_COUNTER_CLEAR field in this register clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. - Reading the EVENT_COUNTER_STATUS field in this register returns the Enable status of the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. + #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_K2 (0x3<<0) // Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and you can clear all event counters at once by writing the 'all clear' code. The read value is always '0'. - 00: no change - 01: per clear - 10: no change - 11: all clear - Other: reserved + #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_K2_SHIFT 0 + #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_K2 (0x7<<2) // Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default, all event counters are disabled. You can enable/disable a specific Event Counter by writing the 'per event off' or 'per event on' codes. You can enable/disable all event counters by writing the 'all on' or 'all off' codes. The read value is always '0'. - 000: no change - 001: per event off - 010: no change - 011: per event on - 100: no change - 101: all off - 110: no change - 111: all on + #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_K2_SHIFT 2 + #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_K2 (0x1<<7) // Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky. + #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_K2_SHIFT 7 + #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_K2 (0xf<<8) // Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky. + #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_K2_SHIFT 8 + #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_K2 (0xfff<<16) // Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event number(8-bit: 0..0x13) within the Group For example: - 0x000: Ebuf Overflow - 0x001: Ebuf Underrun - .. - 0x700: Tx Memory Write - 0x713: Rx Message TLP For detailed definitions of Group number and Event number, see the RAS DES chapter in the Databook. Note: This register field is sticky. + #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_K2_SHIFT 16 +#define PCIEIP_REG_EVENT_COUNTER_DATA_REG_K2 0x000298UL //Access:R DataWidth:0x20 // Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details, see the RAS DES section in the Core Operations chapter of the Databook. +#define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_K2 0x00029cUL //Access:RW DataWidth:0x20 // Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details, see the RAS DES section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_K2 (0x1<<0) // Timer Start. - 0: Start/Restart - 1: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This register field is sticky. + #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_K2_SHIFT 0 + #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_K2 (0xff<<8) // Time-based Duration Select. Selects the duration of time-based analysis. When "manual control" is selected and TIMER_START is set to '1', this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1: 1ms - 0x2: 10ms - 0x3: 100ms - 0x4: 1s - 0x5: 2s - 0x6: 4s - Else: Reserved Note: This register field is sticky. + #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_K2_SHIFT 8 + #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_K2 (0xff<<24) // Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT), and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: - Core_clk Cycles. Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when TIME_BASED_REPORT_SELECT=0x00] * TIME_BASED_ANALYSIS_DATA - Aux_clk Cycles. Total time in ps is [Period of platform specific clock] * TIME_BASED_ANALYSIS_DATA - Data Bytes. Actual amount of bytes is 16 * TIME_BASED_ANALYSIS_DATA Core_clk Cycles - 0x00: Duration of 1 cycle - 0x01: TxL0s - 0x02: RxL0s - 0x03: L0 - 0x04: L1 (Rsvd when aux_clk is supplied from the platform specific clock during L1, L1.1 or L1.2) - 0x07: Configuration/Recovery Aux_clk Cycles - 0x05: L1.1 - 0x06: L1.2 Data Bytes - 0x20: Tx TLP Bytes - 0x21: Rx TLP Bytes - Else: Rsvd Note: This register field is sticky. + #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_K2_SHIFT 24 +#define PCIEIP_REG_TIME_BASED_ANALYSIS_DATA_REG_K2 0x0002a0UL //Access:R DataWidth:0x20 // Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG For more details, see the RAS DES section in the Core Operations chapter of the Databook. +#define PCIEIP_REG_EINJ_ENABLE_REG_K2 0x0002bcUL //Access:RW DataWidth:0x20 // Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1: Sequence Number Error: EINJ1_SEQNUM_REG - 2: DLLP Error: EINJ2_DLLP_REG - 3: Symbol DataK Mask Error or Sync Header Error: EINJ3_SYMBOL_REG - 4: FC Credit Update Error: EINJ4_FC_REG - 5: TLP Duplicate/Nullify Error: EINJ5_SP_TLP_REG - 6: Specific TLP Error: EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG After the errors have been inserted by core, it will clear each bit here. For more details, see the RAS DES section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_K2 (0x1<<0) // Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details, see the EINJ0_CRC_REG register. Note: This register field is sticky. + #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_K2_SHIFT 0 + #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_K2 (0x1<<1) // Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details, see the EINJ1_SEQNUM_REG register. Note: This register field is sticky. + #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_K2_SHIFT 1 + #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_K2 (0x1<<2) // Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details, see the EINJ2_DLLP_REG register. Note: This register field is sticky. + #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_K2_SHIFT 2 + #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_K2 (0x1<<3) // Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details, see the EINJ3_SYMBOL_REG register. Note: This register field is sticky. + #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_K2_SHIFT 3 + #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_K2 (0x1<<4) // Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details, see the EINJ4_FC_REG register. Note: This register field is sticky. + #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_K2_SHIFT 4 + #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_K2 (0x1<<5) // Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details, see the EINJ5_SP_TLP_REG register. Note: This register field is sticky. + #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_K2_SHIFT 5 + #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_K2 (0x1<<6) // Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT =0. You can set this bit to '1' when you have disabled the address translation by setting ADDR_TRANSLATION_SUPPORT_EN=0. For more details, see the EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG registers. Note: This register field is sticky. + #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_K2_SHIFT 6 +#define PCIEIP_REG_EINJ0_CRC_REG_K2 0x0002c0UL //Access:RW DataWidth:0x20 // Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC, and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link Retry starts. - 16-bit CRC of ACK/NAK DLLPs. Bad DLLP occurs at the receiver side; Replay NUM Rollover occurs. - 16-bit CRC of UpdateFC DLLPs. Error insertion continues for the specific time; LTSSM transitions to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - ECRC. If ECRC check is enabled, ECRC error is detected at the receiver side. - FCRC. Framing error will be detected, TLP is discarded, and the LTSSM transitions to Recovery state. - Parity of TSOS. Error insertion continues for the specific time; LTSSM Recovery/Configuration timeout will occur. - Parity of SKPOS. Lane error will be detected at the receiver side. + #define PCIEIP_REG_EINJ0_CRC_REG_EINJ0_COUNT_K2 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the counter value is 0x00 and ERROR_INJECTION0_ENABLE=1, the errors are inserted until ERROR_INJECTION0_ENABLE is set to '0'. Note: This register field is sticky. + #define PCIEIP_REG_EINJ0_CRC_REG_EINJ0_COUNT_K2_SHIFT 0 + #define PCIEIP_REG_EINJ0_CRC_REG_EINJ0_CRC_TYPE_K2 (0xf<<8) // Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC error injection - 0100b: TLP's FCRC error injection (128b/130b) - 0101b: Parity error of TSOS (128b/130b) - 0110b: Parity error of SKPOS (128b/130b) Rx Path - 1000b: LCRC error injection - 1011b: ECRC error injection - Others: Reserved Note: This register field is sticky. + #define PCIEIP_REG_EINJ0_CRC_REG_EINJ0_CRC_TYPE_K2_SHIFT 8 +#define PCIEIP_REG_EINJ1_SEQNUM_REG_K2 0x0002c4UL //Access:RW DataWidth:0x20 // Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: - ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048 - (AckNak_Seq_Num - ACKD_SEQ) mod 4096 >= 2048 TLP is treated as Duplicate TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ - (NEXT_RCV_SEQ - Sequence Number) mod 4096 <= 2048 TLP is treated as Bad TLP at the Rx side when all these conditions are true: - Sequence Number != NEXT_RCV_SEQ and - (NEXT_RCV_SEQ - Sequence Number) mod 4096 > 2048 + #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_COUNT_K2 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION1_ENABLE=1, the errors are inserted until ERROR_INJECTION1_ENABLE is set to '0'. Note: This register field is sticky. + #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_COUNT_K2_SHIFT 0 + #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_K2 (0x1<<8) // Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky. + #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_K2_SHIFT 8 + #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_K2 (0x1fff<<16) // Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095 For example: - Set Type, SEQ# and Count -- EINJ1_SEQNUM_TYPE =0 (Insert errors into new TLPs) -- EINJ1_BAD_SEQNUM =0x1FFD (represents -3) -- EINJ1_COUNT =1 - Enable Error Injection -- ERROR_INJECTION1_ENABLE =1 - Send a TLP From the Core's Application Interface -- Assume SEQ#5 is given to the TLP. - The SEQ# is Changed to #2 by the Error Injection Function in Layer2. -- 5 + (-3) = 2 - The TLP with SEQ#2 is Transmitted to PCIe Link. Note: This register field is sticky. + #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_K2_SHIFT 16 +#define PCIEIP_REG_EINJ2_DLLP_REG_K2 0x0002c8UL //Access:RW DataWidth:0x20 // Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the transmitter of the TLPs and then Data Link Retry will occur. - If "Update FC DLLP's transmission block" is selected, LTSSM will transition to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs). - If "Always Transmission for NAK DLLP" is selected, Data Link Retry will occur at the transmitter of the TLPs. Furthermore, Replay NUM Rollover will occur when the transmitter has been requested four times to send the TLP with the same sequence number. + #define PCIEIP_REG_EINJ2_DLLP_REG_EINJ2_COUNT_K2 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION2_ENABLE =1, the errors are inserted until ERROR_INJECTION2_ENABLE is set to '0'. This register is affected only when EINJ2_DLLP_TYPE =2'10b. Note: This register field is sticky. + #define PCIEIP_REG_EINJ2_DLLP_REG_EINJ2_COUNT_K2_SHIFT 0 + #define PCIEIP_REG_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_K2 (0x3<<8) // DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky. + #define PCIEIP_REG_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_K2_SHIFT 8 +#define PCIEIP_REG_EINJ3_SYMBOL_REG_K2 0x0002ccUL //Access:RW DataWidth:0x20 // Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used, this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeout of the LTSSM. - If END/EDB/STP/SDP is selected, TLP/DLLP will be discarded at the receiver side. When 128b/130b encoding is used, this register controls error insertion into the sync-header. + #define PCIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_COUNT_K2 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION3_ENABLE =1, the errors are inserted until ERROR_INJECTION3_ENABLE is set to '0'. Note: This register field is sticky. + #define PCIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_COUNT_K2_SHIFT 0 + #define PCIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_K2 (0x7<<8) // Error Type. 8b/10b encoding - Mask K symbol. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b: COM/PAD(TS2 Order set) - 011b: COM/FTS(FTS Order set) - 100b: COM/IDL(E-Idle Order set) - 101b: END/EDB Symbol - 110b: STP/SDP Symbol - 111b: COM/SKP(SKP Order set) 128b/130b encoding - Change sync header. - 000b: Invert sync header - Others: Reserved Note: This register field is sticky. + #define PCIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_K2_SHIFT 8 +#define PCIEIP_REG_EINJ4_FC_REG_K2 0x0002d0UL //Access:RW DataWidth:0x20 // Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit - Completion TLP Header credit - Posted TLP Data credit - Non-Posted TLP Data credit - Completion TLP Data credit These errors are not correctable while error insertion is enabled. Receiver buffer overflow error might occur. + #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_COUNT_K2 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION4_ENABLE =1, the errors are inserted until ERROR_INJECTION4_ENABLE is set to '0'. Note: This register field is sticky. + #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_COUNT_K2_SHIFT 0 + #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_K2 (0x7<<8) // Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit value control - 101b: Non-Posted TLP Data Credit value control - 110b: Completion TLP Data Credit value control - 111b: Reserved Note: This register field is sticky. + #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_K2_SHIFT 8 + #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_VC_NUMBER_K2 (0x7<<12) // VC Number. Indicates target VC Number. Note: This register field is sticky. + #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_VC_NUMBER_K2_SHIFT 12 + #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_K2 (0x1fff<<16) // Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. - 0x1001: -4095 Note: This register field is sticky. + #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_K2_SHIFT 16 +#define PCIEIP_REG_EINJ5_SP_TLP_REG_K2 0x0002d4UL //Access:RW DataWidth:0x20 // Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP, the core initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These TLPs will be duplicate TLPs at the receiver side. - For Nullified TLP, the TLPs that the core transmits are changed into nullified TLPs and the original TLPs are stored in the retry buffer. The receiver of these TLPs will detect the lack of seq# and send NAK DLLP at the next TLP. Then the original TLPs are sent from retry buffer and the data controls are recovered. For 128 bit core or more than 128 bit, the core inserts errors the number of times of EINJ5_COUNT but doesn't ensure that the errors are continuously inserted into TLPs. + #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_COUNT_K2 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION5_ENABLE =1, the errors are inserted until ERROR_INJECTION5_ENABLE is set to '0'. Note: This register field is sticky. + #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_COUNT_K2_SHIFT 0 + #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_K2 (0x1<<8) // Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky. + #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_K2_SHIFT 8 +#define PCIEIP_REG_EINJ6_COMPARE_POINT_H0_REG_K2 0x0002d8UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register. +#define PCIEIP_REG_EINJ6_COMPARE_POINT_H1_REG_K2 0x0002dcUL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register. +#define PCIEIP_REG_EINJ6_COMPARE_POINT_H2_REG_K2 0x0002e0UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register. +#define PCIEIP_REG_EINJ6_COMPARE_POINT_H3_REG_K2 0x0002e4UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register. +#define PCIEIP_REG_EINJ6_COMPARE_VALUE_H0_REG_K2 0x0002e8UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register. +#define PCIEIP_REG_PCIEEP_ACS_CAP_HDR_E5 0x0002ecUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_ACS_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_ACS_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_ACS_CAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_ACS_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_ACS_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_ACS_CAP_HDR_NCO_E5_SHIFT 20 +#define PCIEIP_REG_EINJ6_COMPARE_VALUE_H1_REG_K2 0x0002ecUL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register. +#define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_E5 0x0002f0UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_SV_E5 (0x1<<0) // ACS source validation. Hardwired to 0 for upstream port. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_SV_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_TB_E5 (0x1<<1) // ACS translation blocking. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_TB_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_RR_E5 (0x1<<2) // ACS P2P request redirect. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_RR_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_CR_E5 (0x1<<3) // ACS P2P completion redirect. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_CR_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_UF_E5 (0x1<<4) // ACS upstream forwarding. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_UF_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_EC_E5 (0x1<<5) // ACS P2P egress control. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_EC_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_DT_E5 (0x1<<6) // ACS direct translated P2P. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_DT_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_ECVS_E5 (0xff<<8) // Egress control vector size. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_ECVS_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_SVE_E5 (0x1<<16) // ACS source validation enable. Writable only when [SV] 1. + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_SVE_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_TBE_E5 (0x1<<17) // ACS translation blocking enable. Writable only when [TB] 1. + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_TBE_E5_SHIFT 17 + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_RRE_E5 (0x1<<18) // ACS P2P request redirect enable. Writable only when [CR] is 1. + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_RRE_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_CRE_E5 (0x1<<19) // ACS P2P completion redirect enable. Writable only when [CR] is 1. + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_CRE_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_UFE_E5 (0x1<<20) // ACS upstream forwarding enable. Writable only when [UF] is 1. + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_UFE_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_ECE_E5 (0x1<<21) // ACS P2P egress control enable. Writable only when [EC] is 1. + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_ECE_E5_SHIFT 21 + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_DTE_E5 (0x1<<22) // ACS direct translated P2P enable. Writable only when [DT] is 1. + #define PCIEIP_REG_PCIEEP_ACS_CAP_CTL_DTE_E5_SHIFT 22 +#define PCIEIP_REG_EINJ6_COMPARE_VALUE_H2_REG_K2 0x0002f0UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register. +#define PCIEIP_REG_PCIEEP_ACS_EGR_CTL_VEC_E5 0x0002f4UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_ACS_EGR_CTL_VEC_ECV_E5 (0x7<<0) // Egress control vector. + #define PCIEIP_REG_PCIEEP_ACS_EGR_CTL_VEC_ECV_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_ACS_EGR_CTL_VEC_UNUSED_E5 (0x1fffffff<<3) // Reserved. + #define PCIEIP_REG_PCIEEP_ACS_EGR_CTL_VEC_UNUSED_E5_SHIFT 3 +#define PCIEIP_REG_EINJ6_COMPARE_VALUE_H3_REG_K2 0x0002f4UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24] The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register. +#define PCIEIP_REG_PCIEEP_LTR_CAP_HDR_E5 0x0002f8UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_LTR_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_LTR_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_LTR_CAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_LTR_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_LTR_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_LTR_CAP_HDR_NCO_E5_SHIFT 20 +#define PCIEIP_REG_EINJ6_CHANGE_POINT_H0_REG_K2 0x0002f8UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0. +#define PCIEIP_REG_PCIEEP_LTR_LAT_E5 0x0002fcUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_LTR_LAT_MSL_E5 (0x3ff<<0) // Max snoop latency value. + #define PCIEIP_REG_PCIEEP_LTR_LAT_MSL_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_LTR_LAT_MSLS_E5 (0x7<<10) // Max snoop latency scale. + #define PCIEIP_REG_PCIEEP_LTR_LAT_MSLS_E5_SHIFT 10 + #define PCIEIP_REG_PCIEEP_LTR_LAT_MNSL_E5 (0x3ff<<16) // Max no-snoop latency value. + #define PCIEIP_REG_PCIEEP_LTR_LAT_MNSL_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_LTR_LAT_MNSLS_E5 (0x7<<26) // Max no-snoop latency scale. + #define PCIEIP_REG_PCIEEP_LTR_LAT_MNSLS_E5_SHIFT 26 +#define PCIEIP_REG_EINJ6_CHANGE_POINT_H1_REG_K2 0x0002fcUL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0. +#define PCIEIP_REG_PCIEEP_L1SUB_CAP_HDR_E5 0x000300UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_HDR_NCO_E5_SHIFT 20 +#define PCIEIP_REG_EINJ6_CHANGE_POINT_H2_REG_K2 0x000300UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0. #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_BB 0x000300UL //Access:R DataWidth:0x20 // The read-only value of this register is controlled by setting bit 1 of the EXT2_CAP_ENA for EP, The capability can be enabled by default by defining pcieGen3Rate in version.v and setting bit 1 of EXT2_CAP_ENA. #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_SECPCIE_EXT_CAP_ID_BB (0xffff<<0) // Secondary PCIE Extended Capability ID. #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_SECPCIE_EXT_CAP_ID_BB_SHIFT 0 @@ -2193,17 +3552,54 @@ #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_CAP_VER_BB_SHIFT 16 #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_NEXT_BB (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_NEXT_BB_SHIFT 20 -#define PCIEIP_REG_EINJ6_CHANGE_POINT_H3_REG_K2_E5 0x000304UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0. +#define PCIEIP_REG_PCIEEP_L1SUB_CAP_E5 0x000304UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_L1_2_PCIPM_SUP_E5 (0x1<<0) // PCI-PM L12 supported. + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_L1_2_PCIPM_SUP_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_L1_1_PCIPM_SUP_E5 (0x1<<1) // PCI-PM L11 supported. + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_L1_1_PCIPM_SUP_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_L1_2_ASPM_SUP_E5 (0x1<<2) // ASPM L12 supported. + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_L1_2_ASPM_SUP_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_L1_1_ASPM_SUP_E5 (0x1<<3) // ASPM L11 supported. + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_L1_1_ASPM_SUP_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_L1_PMSUB_SUP_E5 (0x1<<4) // L1 PM substates ECN supported. + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_L1_PMSUB_SUP_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_COM_MD_SUPP_E5 (0xff<<8) // Port common mode restore time. Time (in us) required for this Port to reestablish common mode. + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_COM_MD_SUPP_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_PWRON_SCALE_E5 (0x3<<16) // Port T power on scale. 0x0 = 2 us. 0x1 = 10 us. 0x2 = 100 us. 0x3 = Reserved. + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_PWRON_SCALE_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_PWRON_VAL_E5 (0x1f<<19) // Port T power on value. Along with [PWRON_SCALE] sets the time (in us) that this Port requires the port on the opposite side of the Link to wait in L.1.2.Exit after sampling PCI_CLKREQ_L asserted before actively driving the interface. + #define PCIEIP_REG_PCIEEP_L1SUB_CAP_PWRON_VAL_E5_SHIFT 19 +#define PCIEIP_REG_EINJ6_CHANGE_POINT_H3_REG_K2 0x000304UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0. #define PCIEIP_REG_LINK_CONTROL3_BB 0x000304UL //Access:R DataWidth:0x20 // The RW value of this register is controlled by setting bit 1 of the EXT2_CAP_ENA for EP. #define PCIEIP_REG_LINK_CONTROL3_PERFORM_EQ_BB (0x1<<0) // N/A to endpoints #define PCIEIP_REG_LINK_CONTROL3_PERFORM_EQ_BB_SHIFT 0 #define PCIEIP_REG_LINK_CONTROL3_LINK_EQ_REQ_INT_EN_BB (0x1<<1) // N/A to endpoints #define PCIEIP_REG_LINK_CONTROL3_LINK_EQ_REQ_INT_EN_BB_SHIFT 1 -#define PCIEIP_REG_EINJ6_CHANGE_VALUE_H0_REG_K2_E5 0x000308UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0. +#define PCIEIP_REG_PCIEEP_L1SUB_CTL1_E5 0x000308UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_L1SUB_CTL1_L1_2_PCIPM_EN_E5 (0x1<<0) // PCI-PM L12 enable. + #define PCIEIP_REG_PCIEEP_L1SUB_CTL1_L1_2_PCIPM_EN_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_L1SUB_CTL1_L1_1_PCIPM_EN_E5 (0x1<<1) // PCI-PM L11 enable. + #define PCIEIP_REG_PCIEEP_L1SUB_CTL1_L1_1_PCIPM_EN_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_L1SUB_CTL1_L1_2_ASPM_EN_E5 (0x1<<2) // ASPM L12 enable. + #define PCIEIP_REG_PCIEEP_L1SUB_CTL1_L1_2_ASPM_EN_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_L1SUB_CTL1_L1_1_ASPM_EN_E5 (0x1<<3) // ASPM L11 enable. + #define PCIEIP_REG_PCIEEP_L1SUB_CTL1_L1_1_ASPM_EN_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_L1SUB_CTL1_T_COM_MODE_E5 (0xff<<8) // Common mode restore time. Reserved for upstream port. + #define PCIEIP_REG_PCIEEP_L1SUB_CTL1_T_COM_MODE_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_L1SUB_CTL1_L1_2_TH_VAL_E5 (0x3ff<<16) // LTR L12 threshold value. Along with [L1_2_TH_SCA], this field indicates the LTR threshold use to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). + #define PCIEIP_REG_PCIEEP_L1SUB_CTL1_L1_2_TH_VAL_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_L1SUB_CTL1_L1_2_TH_SCA_E5 (0x7<<29) // LTR L12 threshold scale. 0x0 = 1 ns. 0x1 = 32 ns. 0x2 = 1024 ns. 0x3 = 32,768 ns. 0x4 = 1,048,575 ns. 0x5 = 33,554,432 ns. 0x6-7 = Reserved. + #define PCIEIP_REG_PCIEEP_L1SUB_CTL1_L1_2_TH_SCA_E5_SHIFT 29 +#define PCIEIP_REG_EINJ6_CHANGE_VALUE_H0_REG_K2 0x000308UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0. #define PCIEIP_REG_LANE_ERROR_STATUS_BB 0x000308UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_LANE_ERROR_STATUS_LANE_ERR_STATUS_BITS_BB (0xffff<<0) // Each bit indicates if corresponding PCIE lane detected a lane based error. #define PCIEIP_REG_LANE_ERROR_STATUS_LANE_ERR_STATUS_BITS_BB_SHIFT 0 -#define PCIEIP_REG_EINJ6_CHANGE_VALUE_H1_REG_K2_E5 0x00030cUL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0. +#define PCIEIP_REG_PCIEEP_L1SUB_CTL2_E5 0x00030cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_L1SUB_CTL2_T_PWR_ON_SCA_E5 (0x3<<0) // T power on scale. 0x0 = 2 us. 0x1 = 10 us. 0x2 = 100 us. 0x3 = Reserved. + #define PCIEIP_REG_PCIEEP_L1SUB_CTL2_T_PWR_ON_SCA_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_L1SUB_CTL2_T_PWR_ON_VAL_E5 (0x1f<<3) // T power on value. Along with the [T_PWR_ON_SCA], sets the minimum amount of time (in us) that the Port must wait in L.1.2.Exit after sampling PCI_CLKREQ_L asserted before actively driving the interface. + #define PCIEIP_REG_PCIEEP_L1SUB_CTL2_T_PWR_ON_VAL_E5_SHIFT 3 +#define PCIEIP_REG_EINJ6_CHANGE_VALUE_H1_REG_K2 0x00030cUL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0. #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_BB 0x00030cUL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS0_BB (0xff<<0) // Applicable only to Upstream component. #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS0_BB_SHIFT 0 @@ -2221,7 +3617,14 @@ #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS1_BB_SHIFT 28 #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_RESERVED1_BB (0x1<<31) // Reserved #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_RESERVED1_BB_SHIFT 31 -#define PCIEIP_REG_EINJ6_CHANGE_VALUE_H2_REG_K2_E5 0x000310UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0. +#define PCIEIP_REG_PCIEEP_PASID_CAP_HDR_E5 0x000310UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PASID_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PASID_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PASID_CAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PASID_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_PASID_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PASID_CAP_HDR_NCO_E5_SHIFT 20 +#define PCIEIP_REG_EINJ6_CHANGE_VALUE_H2_REG_K2 0x000310UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0. #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_BB 0x000310UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS2_BB (0xff<<0) // Applicable only to Upstream component. #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS2_BB_SHIFT 0 @@ -2239,7 +3642,20 @@ #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS3_BB_SHIFT 28 #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_RESERVED3_BB (0x1<<31) // Reserved #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_RESERVED3_BB_SHIFT 31 -#define PCIEIP_REG_EINJ6_CHANGE_VALUE_H3_REG_K2_E5 0x000314UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0. +#define PCIEIP_REG_PCIEEP_PASID_CTL_REG_E5 0x000314UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PASID_CTL_REG_EPS_E5 (0x1<<1) // Execute permission supported. + #define PCIEIP_REG_PCIEEP_PASID_CTL_REG_EPS_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_PASID_CTL_REG_PRVMS_E5 (0x1<<2) // Privileged mode supported. + #define PCIEIP_REG_PCIEEP_PASID_CTL_REG_PRVMS_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_PASID_CTL_REG_MPIDW_E5 (0x1f<<8) // Default value for the width of the PASID field supported by the endpoint. Single PASID support only. + #define PCIEIP_REG_PCIEEP_PASID_CTL_REG_MPIDW_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_PASID_CTL_REG_EN_E5 (0x1<<16) // PASID enable. + #define PCIEIP_REG_PCIEEP_PASID_CTL_REG_EN_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_PASID_CTL_REG_EPE_E5 (0x1<<17) // Execute permission enable. + #define PCIEIP_REG_PCIEEP_PASID_CTL_REG_EPE_E5_SHIFT 17 + #define PCIEIP_REG_PCIEEP_PASID_CTL_REG_PRVME_E5 (0x1<<18) // Privileged mode enable. + #define PCIEIP_REG_PCIEEP_PASID_CTL_REG_PRVME_E5_SHIFT 18 +#define PCIEIP_REG_EINJ6_CHANGE_VALUE_H3_REG_K2 0x000314UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24] The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0. #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_BB 0x000314UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS4_BB (0xff<<0) // Applicable only to Upstream component. #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS4_BB_SHIFT 0 @@ -2257,13 +3673,20 @@ #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS5_BB_SHIFT 28 #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_RESERVED5_BB (0x1<<31) // Reserved #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_RESERVED5_BB_SHIFT 31 -#define PCIEIP_REG_EINJ6_TLP_REG_K2_E5 0x000318UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the this register. The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the this register. Only applies when EINJ6_INVERTED_CONTROL in this register =0. The TLP into that errors are injected will not arrive at the transaction layer of the remote device when all of the following conditions are true. - Using 128b/130b encoding - Injecting errors into TLP Length field / TLP digest bit - #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_COUNT_K2_E5 (0xff<<0) // Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION6_ENABLE=1, errors are inserted until ERROR_INJECTION6_ENABLE is set to '0'. Note: This register field is sticky. - #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_COUNT_K2_E5_SHIFT 0 - #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_K2_E5 (0x1<<8) // Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. Note: This register field is sticky. - #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_K2_E5_SHIFT 8 - #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_K2_E5 (0x7<<9) // Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky. - #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_K2_E5_SHIFT 9 +#define PCIEIP_REG_PCIEEP_RAS_DES_CAP_HDR_E5 0x000318UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_DES_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_RAS_DES_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_DES_CAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_RAS_DES_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_RAS_DES_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Points to the Vendor Specific RAS Data Path Protection capabilities. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_RAS_DES_CAP_HDR_NCO_E5_SHIFT 20 +#define PCIEIP_REG_EINJ6_TLP_REG_K2 0x000318UL //Access:RW DataWidth:0x20 // Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the this register. The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). The type and number of errors are specified by the this register. Only applies when EINJ6_INVERTED_CONTROL in this register =0. The TLP into that errors are injected will not arrive at the transaction layer of the remote device when all of the following conditions are true. - Using 128b/130b encoding - Injecting errors into TLP Length field / TLP digest bit + #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_COUNT_K2 (0xff<<0) // Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If the counter value is 0x00 and ERROR_INJECTION6_ENABLE=1, errors are inserted until ERROR_INJECTION6_ENABLE is set to '0'. Note: This register field is sticky. + #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_COUNT_K2_SHIFT 0 + #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_K2 (0x1<<8) // Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. Note: This register field is sticky. + #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_K2_SHIFT 8 + #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_K2 (0x7<<9) // Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky. + #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_K2_SHIFT 9 #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_BB 0x000318UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS6_BB (0xff<<0) // Applicable only to Upstream component. #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS6_BB_SHIFT 0 @@ -2281,6 +3704,13 @@ #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS7_BB_SHIFT 28 #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_RESERVED7_BB (0x1<<31) // Reserved #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_RESERVED7_BB_SHIFT 31 +#define PCIEIP_REG_PCIEEP_RAS_HDR_E5 0x00031cUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_HDR_VSEC_ID_E5 (0xffff<<0) // VSEC ID. + #define PCIEIP_REG_PCIEEP_RAS_HDR_VSEC_ID_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_HDR_VSEC_REV_E5 (0xf<<16) // Capability version. + #define PCIEIP_REG_PCIEEP_RAS_HDR_VSEC_REV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_RAS_HDR_VSEC_LENGTH_E5 (0xfff<<20) // VSEC length. + #define PCIEIP_REG_PCIEEP_RAS_HDR_VSEC_LENGTH_E5_SHIFT 20 #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_BB 0x00031cUL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS8_BB (0xff<<0) // Applicable only to Upstream component. #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS8_BB_SHIFT 0 @@ -2298,6 +3728,17 @@ #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS9_BB_SHIFT 28 #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_RESERVED7_BB (0x1<<31) // Reserved #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_RESERVED7_BB_SHIFT 31 +#define PCIEIP_REG_PCIEEP_RAS_EC_CTL_E5 0x000320UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_EC_CTL_EV_CNTR_CLR_E5 (0x3<<0) // Event counter clear. Clears the event counters selected by [EV_CNTR_DATA_SEL] and [EV_CNTR_LANE_SEL]. By default, all event counters are disabled. This field always reads zeros. 0x0 = No change. 0x1 = Per clear. 0x2 = No change. 0x3 = All clear. + #define PCIEIP_REG_PCIEEP_RAS_EC_CTL_EV_CNTR_CLR_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_EC_CTL_EV_CNTR_EN_E5 (0x7<<2) // Event counter enable. Enables/disables the event counter selected by [EV_CNTR_DATA_SEL] and [EV_CNTR_LANE_SEL]. By default, all event counters are disabled. This field always reads zeros. 0x0 = No change. 0x1 = Per event off. 0x2 = No change. 0x3 = Per event on. 0x4 = No change. 0x5 = All off. 0x6 = No change. 0x7 = All on. + #define PCIEIP_REG_PCIEEP_RAS_EC_CTL_EV_CNTR_EN_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_RAS_EC_CTL_EV_CNTR_STAT_E5 (0x1<<7) // Event counter status. Returns the enable status of the event counter selected by [EV_CNTR_DATA_SEL] and [EV_CNTR_LANE_SEL]. + #define PCIEIP_REG_PCIEEP_RAS_EC_CTL_EV_CNTR_STAT_E5_SHIFT 7 + #define PCIEIP_REG_PCIEEP_RAS_EC_CTL_EV_CNTR_LANE_SEL_E5 (0xf<<8) // Event counter lane select. This field in conjunction with [EV_CNTR_DATA_SEL] indexes the event counter data returned in the PCIEEP_RAS_EC_DATA[EV_CNTR_DATA]. 0x0-0x7 = Lane number. 0x8-0xF = Reserved. + #define PCIEIP_REG_PCIEEP_RAS_EC_CTL_EV_CNTR_LANE_SEL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_RAS_EC_CTL_EV_CNTR_DATA_SEL_E5 (0xfff<<16) // Event counter data select. This field in conjunction with [EV_CNTR_LANE_SEL] selects PCIEEP_RAS_EC_DATA[EV_CNTR_DATA]. _ <27:24> = Group number (0..0x7). _ <23:16> = Event number (0..0x13). + #define PCIEIP_REG_PCIEEP_RAS_EC_CTL_EV_CNTR_DATA_SEL_E5_SHIFT 16 #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_BB 0x000320UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS10_BB (0xff<<0) // Applicable only to Upstream component. #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS10_BB_SHIFT 0 @@ -2315,6 +3756,7 @@ #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS11_BB_SHIFT 28 #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_RESERVED11_BB (0x1<<31) // Reserved #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_RESERVED11_BB_SHIFT 31 +#define PCIEIP_REG_PCIEEP_RAS_EC_DATA_E5 0x000324UL //Access:R DataWidth:0x20 // #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_BB 0x000324UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS12_BB (0xff<<0) // Applicable only to Upstream component. #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS12_BB_SHIFT 0 @@ -2332,6 +3774,13 @@ #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS13_BB_SHIFT 28 #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_RESERVED13_BB (0x1<<31) // Reserved #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_RESERVED13_BB_SHIFT 31 +#define PCIEIP_REG_PCIEEP_RAS_TBA_CTL_E5 0x000328UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_TBA_CTL_TIMER_START_E5 (0x1<<0) // Timer start. 0x0 = Start/restart. 0x1 = Stop. This bit will be cleared automatically when the measurement is finished. + #define PCIEIP_REG_PCIEEP_RAS_TBA_CTL_TIMER_START_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_TBA_CTL_TBASE_DUR_SEL_E5 (0xff<<8) // Time-based duration select. Selects the duration of time-based analysis. 0x0 = Manual control. Analysis controlled by [TIMER_START]. 0x1 = 1 ms. 0x2 = 10 ms. 0x3 = 100 ms. 0x4 = 1 s. 0x5 = 2 s. 0x6 = 4 s. 0x7 - 0xF = Reserved. + #define PCIEIP_REG_PCIEEP_RAS_TBA_CTL_TBASE_DUR_SEL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_RAS_TBA_CTL_TBASE_RPT_SEL_E5 (0xff<<24) // Time-based report select. Selects what type of data is measured for the selected duration [TBASE_DUR_SEL]. Data is returned in PCIEEP_RAS_TBA_DATA[TBASE_DATA]. Each type of data is measured using one of three types of units. Core clock cycles. 0x0 = Duration of 1 cycle. 0x1 = TxL0s. 0x2 = RxL0s. 0x3 = L0. 0x4 = L1. 0x7 = Configuration/recovery. Aux_clk cycles. 0x5 = L1.1. 0x6 = L1.2. Data bytes. Actual amount is 16x value. 0x20 = TX TLP Bytes. 0x21 = RX TLP Bytes. + #define PCIEIP_REG_PCIEEP_RAS_TBA_CTL_TBASE_RPT_SEL_E5_SHIFT 24 #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_BB 0x000328UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS14_BB (0xff<<0) // Applicable only to Upstream component. #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS14_BB_SHIFT 0 @@ -2349,348 +3798,587 @@ #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS15_BB_SHIFT 28 #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_RESERVED15_BB (0x1<<31) // Reserved #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_RESERVED15_BB_SHIFT 31 -#define PCIEIP_REG_SD_CONTROL1_REG_K2_E5 0x00032cUL //Access:RW DataWidth:0x20 // Silicon Debug Control 1. For more details, see the RAS DES section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE_K2_E5 (0xffff<<0) // Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set, the core ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This register field is sticky. - #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE_K2_E5_SHIFT 0 - #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_K2_E5 (0x1<<16) // Force Detect Lane Enable. When this bit is set, the core ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky. - #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_K2_E5_SHIFT 16 - #define PCIEIP_REG_SD_CONTROL1_REG_TX_EIOS_NUM_K2_E5 (0x3<<20) // Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The core selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s, 8.0GT/s or higher: - 0x0: 1 - 0x1: 4 - 0x2: 8 - 0x3: 16 5.0GT/s: - 0x0: 2 - 0x1: 8 - 0x2: 16 - 0x3: 32 Note: This register field is sticky. - #define PCIEIP_REG_SD_CONTROL1_REG_TX_EIOS_NUM_K2_E5_SHIFT 20 - #define PCIEIP_REG_SD_CONTROL1_REG_LOW_POWER_INTERVAL_K2_E5 (0x3<<22) // Low Power Entry Interval Time. Interval Time that the core starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to, RXELECIDLE assertion at the PHY. - 0x0: 40ns - 0x1: 160ns - 0x2: 320ns - 0x3: 640ns Note: This register field is sticky. - #define PCIEIP_REG_SD_CONTROL1_REG_LOW_POWER_INTERVAL_K2_E5_SHIFT 22 -#define PCIEIP_REG_SD_CONTROL2_REG_K2_E5 0x000330UL //Access:RW DataWidth:0x20 // Silicon Debug Control 2. For more details, see the RAS DES section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_SD_CONTROL2_REG_HOLD_LTSSM_K2_E5 (0x1<<0) // Hold and Release LTSSM. For as long as this register is '1', the core stays in the current LTSSM. Note: This register field is sticky. - #define PCIEIP_REG_SD_CONTROL2_REG_HOLD_LTSSM_K2_E5_SHIFT 0 - #define PCIEIP_REG_SD_CONTROL2_REG_RECOVERY_REQUEST_K2_E5 (0x1<<1) // Recovery Request. When this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization. - #define PCIEIP_REG_SD_CONTROL2_REG_RECOVERY_REQUEST_K2_E5_SHIFT 1 - #define PCIEIP_REG_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_K2_E5 (0x1<<2) // Force LinkDown. When this bit is set and the core detects REPLY_NUM rolling over 4 times, the LTSSM transitions to Detect State. Note: This register field is sticky. - #define PCIEIP_REG_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_K2_E5_SHIFT 2 - #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_K2_E5 (0x1<<8) // Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State, the LTSSM transitions to Configuration state. Note: This register field is sticky. - #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_K2_E5_SHIFT 8 - #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_K2_E5 (0x1<<9) // Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State, the LTSSM transitions to Detect state. Note: This register field is sticky. - #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_K2_E5_SHIFT 9 - #define PCIEIP_REG_SD_CONTROL2_REG_DETECT_LPBKSLV_TO_EXIT_K2_E5 (0x1<<10) // Detect Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State, the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky. - #define PCIEIP_REG_SD_CONTROL2_REG_DETECT_LPBKSLV_TO_EXIT_K2_E5_SHIFT 10 - #define PCIEIP_REG_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_K2_E5 (0x1<<16) // Framing Error Recovery Disable. This bit forces a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky. - #define PCIEIP_REG_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_K2_E5_SHIFT 16 -#define PCIEIP_REG_SD_STATUS_L1LANE_REG_K2_E5 0x00033cUL //Access:RW DataWidth:0x20 // Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_CONTROL1_REG For more details, see the RAS DES section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_SD_STATUS_L1LANE_REG_LANE_SELECT_K2_E5 (0xf<<0) // Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L1LANE_REG_LANE_SELECT_K2_E5_SHIFT 0 - #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_K2_E5 (0x1<<16) // PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_K2_E5_SHIFT 16 - #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_K2_E5 (0x1<<17) // PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_K2_E5_SHIFT 17 - #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXVALID_K2_E5 (0x1<<18) // PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXVALID_K2_E5_SHIFT 18 - #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_K2_E5 (0x1<<19) // PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_K2_E5_SHIFT 19 - #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_K2_E5 (0x1<<20) // PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_K2_E5_SHIFT 20 - #define PCIEIP_REG_SD_STATUS_L1LANE_REG_DESKEW_POINTER_K2_E5 (0xff<<24) // Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L1LANE_REG_DESKEW_POINTER_K2_E5_SHIFT 24 -#define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_K2_E5 0x000340UL //Access:RW DataWidth:0x20 // Silicon Debug Status(Layer1 LTSSM). For more details, see the RAS DES section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_K2_E5 (0x7f<<0) // First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception - 02h: When current token was not a valid EDB token and previous token was an EDB. (128/256 bit core only) - 03h: When SDP token was received but not expected. (128 bit & (x8 | x16) core only) - 04h: When STP token was received but not expected. (128 bit & (x8 | x16) core only) - 05h: When EDS token was expected but not received or whenever an EDS token was received but not expected. - 06h: When a framing error was detected in the deskew block while a packet has been in progress in token_finder. Received Unexpected STP Token - 11h: When Framing CRC in STP token did not match - 12h: When Framing Parity in STP token did not match. - 13h: When Framing TLP Length in STP token was smaller than 5 DWORDs. Received Unexpected Block - 21h: When Receiving an OS Block following SDS in Datastream state - 22h: When Data Block followed by OS Block different from SKP, EI, EIE in Datastream state - 23h: When Block with an undefined Block Type in Datastream state - 24h: When Data Stream without data over three cycles in Datastream state - 25h: When OS Block during Data Stream in Datastream state - 26h: When RxStatus Error was detected in Datastream state - 27h: When Not all active lanes receiving SKP OS starting at same cycle time in SKPOS state - 28h: When a 2-Block timeout occurs for SKP OS in SKPOS state - 29h: When Receiving consecutive OS Blocks within a Data Stream in SKPOS state - 2Ah: When Phy status error was detected in SKPOS state - 2Bh: When Not all active lanes receiving EIOS starting at same cycle time in EIOS state - 2Ch: When At least one Symbol from the first 4 Symbols is not EIOS Symbol in EIOS state (CX_NB=2 only) - 2Dh: When Not all active lanes receiving EIEOS starting at same cycle time in EIEOS state - 2Eh: When Not full 16 eieos symbols are received in EIEOS state All other values not listed above are Reserved. Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_K2_E5_SHIFT 0 - #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_K2_E5 (0x1<<7) // Framing Error. Indicates Framing Error detection status. - #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_K2_E5_SHIFT 7 - #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_K2_E5 (0x7<<8) // PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_K2_E5_SHIFT 8 - #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_K2_E5 (0x1<<15) // Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_K2_E5_SHIFT 15 - #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_K2_E5 (0xffff<<16) // LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express base specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if both ports advertised the UpConfigure capability in the last Config.Complete. - 4: select_deemphasis - 5: start_equalization_w_preset - 6: equalization_done_8GT_data_rate - 7: equalization_done_16GT_data_rate - 15:8: idle_to_rlock_transitioned M-PCIe Mode: - 0: idle_to_recovery - 1: recovery_to_configuration Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_K2_E5_SHIFT 16 -#define PCIEIP_REG_SD_STATUS_PM_REG_K2_E5 0x000344UL //Access:RW DataWidth:0x20 // Silicon Debug Status(PM). For more details, see the RAS DES section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_K2_E5 (0x1f<<0) // Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h: S_L1_EXIT - 8h: S_L23RDY - 9h: S_LINK_ENTR_L23 - Ah: S_L23RDY_WAIT4ALIVE - Bh: S_ACK_WAIT4IDLE Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_K2_E5_SHIFT 0 - #define PCIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_K2_E5 (0xf<<8) // Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah: L1_WAIT_LAST_TLP_ACK - 0Bh: L1_WAIT_PMDLLP_ACK - 0Ch: L1_LINK_ENTR_L1 - 0Dh: L1_EXIT - 0Fh: PREP_4L1 - 10h: L23_BLOCK_TLP - 11h: L23_WAIT_LAST_TLP_ACK - 12h: L23_WAIT_PMDLLP_ACK - 13h: L23_ENTR_L23 - 14h: L23RDY - 15h: PREP_4L23 - 16h: L23RDY_WAIT4ALIVE - 17h: L0S_BLOCK_TLP Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_K2_E5_SHIFT 8 - #define PCIEIP_REG_SD_STATUS_PM_REG_PME_RESEND_FLAG_K2_E5 (0x1<<12) // PME Re-send flag. When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%), the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent. - #define PCIEIP_REG_SD_STATUS_PM_REG_PME_RESEND_FLAG_K2_E5_SHIFT 12 - #define PCIEIP_REG_SD_STATUS_PM_REG_LATCHED_NFTS_K2_E5 (0xff<<16) // Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_PM_REG_LATCHED_NFTS_K2_E5_SHIFT 16 -#define PCIEIP_REG_SD_STATUS_L2_REG_K2_E5 0x000348UL //Access:R DataWidth:0x20 // Silicon Debug Status(Layer2). For more details, see the RAS DES section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_K2_E5 (0xfff<<0) // Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_K2_E5_SHIFT 0 - #define PCIEIP_REG_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_K2_E5 (0xfff<<12) // Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_K2_E5_SHIFT 12 - #define PCIEIP_REG_SD_STATUS_L2_REG_DLCMSM_K2_E5 (0x3<<24) // DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L2_REG_DLCMSM_K2_E5_SHIFT 24 - #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT1_K2_E5 (0x1<<26) // FC_INIT1. Indicates the core is in FC_INIT1(VC0) state. Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT1_K2_E5_SHIFT 26 - #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT2_K2_E5 (0x1<<27) // FC_INIT2. Indicates the core is in FC_INIT2(VC0) state. Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT2_K2_E5_SHIFT 27 -#define PCIEIP_REG_SD_STATUS_L3FC_REG_K2_E5 0x00034cUL //Access:RW DataWidth:0x20 // Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE - CREDIT_SEL_HD For more details, see the RAS DES section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_K2_E5 (0x7<<0) // Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 - 0x1: VC1 - 0x2: VC2 - .. - 0x7: VC7 Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_K2_E5_SHIFT 0 - #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_K2_E5 (0x1<<3) // Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Rx - 0x1: Tx Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_K2_E5_SHIFT 3 - #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_K2_E5 (0x3<<4) // Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Posted - 0x1: Non-Posted - 0x2: Completion Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_K2_E5_SHIFT 4 - #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_K2_E5 (0x1<<6) // Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Header Credit - 0x1: Data Credit Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_K2_E5_SHIFT 6 - #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA0_K2_E5 (0xfff<<8) // Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA0_K2_E5_SHIFT 8 - #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA1_K2_E5 (0xfff<<20) // Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when DLCMSM=0x3(DL_ACTIVE). Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA1_K2_E5_SHIFT 20 -#define PCIEIP_REG_SD_STATUS_L3_REG_K2_E5 0x000350UL //Access:RW DataWidth:0x20 // Silicon Debug Status(Layer3). For more details, see the RAS DES section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_POINTER_K2_E5 (0x7f<<0) // First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length miss match - 05h: Max payload size - 06h: Message TLP without TC0 - 07h: Invalid TC - 08h: Unexpected route bit in Message TLP - 09h: Unexpected CRS status in Completion TLP - 0Ah: Byte enable - 0Bh: Memory Address 4KB boundary - 0Ch: TLP prefix rules - 0Dh: Translation request rules - 0Eh: Invalid TLP type - 0Fh: Completion rules - 7Fh: Application - Else: Reserved Note: This register field is sticky. - #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_POINTER_K2_E5_SHIFT 0 - #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_STATUS_K2_E5 (0x1<<7) // Malformed TLP Status. Indicates malformed TLP has occurred. - #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_STATUS_K2_E5_SHIFT 7 -#define PCIEIP_REG_SD_EQ_CONTROL1_REG_K2_E5 0x00035cUL //Access:RW DataWidth:0x20 // Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport registers. For more details, see the RAS DES section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_K2_E5 (0xf<<0) // EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_K2_E5_SHIFT 0 - #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_K2_E5 (0x1<<4) // EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed - 0x1: 16.0GT/s Speed Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_K2_E5_SHIFT 4 - #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_K2_E5 (0x3<<16) // Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_K2_E5_SHIFT 16 - #define PCIEIP_REG_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_K2_E5 (0x1<<23) // FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_K2_E5_SHIFT 23 - #define PCIEIP_REG_SD_EQ_CONTROL1_REG_FOM_TARGET_K2_E5 (0xff<<24) // FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL1_REG_FOM_TARGET_K2_E5_SHIFT 24 -#define PCIEIP_REG_SD_EQ_CONTROL2_REG_K2_E5 0x000360UL //Access:RW DataWidth:0x20 // Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details, see the RAS DES section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_K2_E5 (0x3f<<0) // Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_K2_E5_SHIFT 0 - #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_K2_E5 (0x3f<<6) // Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_K2_E5_SHIFT 6 - #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_K2_E5 (0x3f<<12) // Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_K2_E5_SHIFT 12 - #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_K2_E5 (0x7<<18) // Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of received or set value. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_K2_E5_SHIFT 18 - #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_K2_E5 (0xf<<24) // Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_K2_E5_SHIFT 24 - #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_K2_E5 (0x1<<28) // Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_K2_E5_SHIFT 28 - #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_K2_E5 (0x1<<29) // Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_K2_E5_SHIFT 29 - #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_K2_E5 (0x1<<30) // Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_K2_E5_SHIFT 30 -#define PCIEIP_REG_SD_EQ_CONTROL3_REG_K2_E5 0x000364UL //Access:RW DataWidth:0x20 // Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details, see the RAS DES section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_K2_E5 (0x3f<<0) // Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from link partner. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_K2_E5_SHIFT 0 - #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_K2_E5 (0x3f<<6) // Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from link partner. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_K2_E5_SHIFT 6 - #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_K2_E5 (0x3f<<12) // Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from link partner. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_K2_E5_SHIFT 12 - #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_K2_E5 (0x1<<28) // Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_K2_E5_SHIFT 28 -#define PCIEIP_REG_SD_EQ_STATUS1_REG_K2_E5 0x00036cUL //Access:R DataWidth:0x20 // Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The following fields are available when Equalization finished unsuccessfully(EQ_CONVERGENCE_INFO=2). - EQ_RULEA_VIOLATION - EQ_RULEB_VIOLATION - EQ_RULEC_VIOLATION - EQ_REJECT_EVENT For more details, see the RAS DES section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_SEQUENCE_K2_E5 (0x1<<0) // EQ Sequence. Indicates that the core is starting the equalization sequence. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_SEQUENCE_K2_E5_SHIFT 0 - #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_K2_E5 (0x3<<1) // EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically cleared when the core starts EQ Master phase again. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_K2_E5_SHIFT 1 - #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_K2_E5 (0x1<<4) // EQ Rule A Violation. Indicates that coefficient rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the core starts EQ Master phase again. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_K2_E5_SHIFT 4 - #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_K2_E5 (0x1<<5) // EQ Rule B Violation. Indicates that coefficient rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the core starts EQ Master phase again. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_K2_E5_SHIFT 5 - #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_K2_E5 (0x1<<6) // EQ Rule C Violation. Indicates that coefficient rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the core starts EQ Master phase again. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_K2_E5_SHIFT 6 - #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_K2_E5 (0x1<<7) // EQ Reject Event. Indicates that the core receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the core starts EQ Master phase again. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_K2_E5_SHIFT 7 -#define PCIEIP_REG_SD_EQ_STATUS2_REG_K2_E5 0x000370UL //Access:R DataWidth:0x20 // Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1). For more details, see the RAS DES section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_K2_E5 (0x3f<<0) // EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_K2_E5_SHIFT 0 - #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_K2_E5 (0x3f<<6) // EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_K2_E5_SHIFT 6 - #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_K2_E5 (0x3f<<12) // EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_K2_E5_SHIFT 12 - #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_K2_E5 (0x7<<18) // EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_K2_E5_SHIFT 18 - #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_K2_E5 (0xff<<24) // EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_K2_E5_SHIFT 24 -#define PCIEIP_REG_SD_EQ_STATUS3_REG_K2_E5 0x000374UL //Access:R DataWidth:0x20 // Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1). For more details, see the RAS DES section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_K2_E5 (0x3f<<0) // EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_K2_E5_SHIFT 0 - #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_K2_E5 (0x3f<<6) // EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_K2_E5_SHIFT 6 - #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_K2_E5 (0x3f<<12) // EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_K2_E5_SHIFT 12 - #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_K2_E5 (0x3f<<18) // EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_K2_E5_SHIFT 18 - #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_K2_E5 (0x3f<<24) // EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky. - #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_K2_E5_SHIFT 24 -#define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_K2_E5 0x00038cUL //Access:RW DataWidth:0x20 // PCIe Extended capability ID, Capability version and Next capability offset. - #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_ID_K2_E5 (0xffff<<0) // PCI Express Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_CAP_K2_E5 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_CAP_K2_E5_SHIFT 16 - #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_K2_E5 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_K2_E5_SHIFT 20 -#define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_K2_E5 0x000390UL //Access:R DataWidth:0x20 // Vendor Specific Header. - #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_K2_E5 (0xffff<<0) // VSEC ID. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_K2_E5 (0xf<<16) // VSEC Rev. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_K2_E5_SHIFT 16 - #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_K2_E5 (0xfff<<20) // VSEC Length. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_K2_E5_SHIFT 20 -#define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_K2_E5 0x000394UL //Access:RW DataWidth:0x20 // ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native core clock (core_clk), you must not write this register while operations are in progress in the AXI master / slave interface. - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_K2_E5 (0x1<<0) // Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_K2_E5_SHIFT 0 - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_K2_E5 (0x1<<1) // Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_K2_E5_SHIFT 1 - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_K2_E5 (0x1<<2) // Error correction disable for AXI bridge outbound request path. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_K2_E5_SHIFT 2 - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_K2_E5 (0x1<<3) // Error correction disable for DMA write engine. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_K2_E5_SHIFT 3 - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_K2_E5 (0x1<<4) // Error correction disable for layer 2 Tx path. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_K2_E5_SHIFT 4 - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_K2_E5 (0x1<<5) // Error correction disable for layer 3 Tx path. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_K2_E5_SHIFT 5 - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_K2_E5 (0x1<<6) // Error correction disable for Adm Tx path. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_K2_E5_SHIFT 6 - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_K2_E5 (0x1<<16) // Global error correction disable for all Rx layers. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_K2_E5_SHIFT 16 - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_K2_E5 (0x1<<17) // Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_K2_E5_SHIFT 17 - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_K2_E5 (0x1<<18) // Error correction disable for AXI bridge inbound request path. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_K2_E5_SHIFT 18 - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_K2_E5 (0x1<<19) // Error correction disable for DMA read engine. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_K2_E5_SHIFT 19 - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_K2_E5 (0x1<<20) // Error correction disable for layer 2 Rx path. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_K2_E5_SHIFT 20 - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_K2_E5 (0x1<<21) // Error correction disable for layer 3 Rx path. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_K2_E5_SHIFT 21 - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_K2_E5 (0x1<<22) // Error correction disable for ADM Rx path. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_K2_E5_SHIFT 22 -#define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_K2_E5 0x000398UL //Access:RW DataWidth:0x20 // Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_CORR_COUNT_REPORT_OFF viewport data register. - #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_K2_E5 (0x1<<0) // Clear all correctable error counters. - #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_K2_E5_SHIFT 0 - #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_K2_E5 (0x1<<4) // Enable correctable errors counters. - 1: counters increment when the core detects a correctable error - 0: counters are frozen The counters are enabled by default. - #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_K2_E5_SHIFT 4 - #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_K2_E5 (0xf<<20) // Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved - #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_K2_E5_SHIFT 20 - #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_K2_E5 (0xff<<24) // Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf - #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_K2_E5_SHIFT 24 -#define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_K2_E5 0x00039cUL //Access:R DataWidth:0x20 // Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register. - #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_K2_E5 (0xff<<0) // Current corrected error count for the selected counter. - #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_K2_E5_SHIFT 0 - #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_K2_E5 (0xf<<20) // Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved - #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_K2_E5_SHIFT 20 - #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_K2_E5 (0xff<<24) // Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register. - #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_K2_E5_SHIFT 24 -#define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_K2_E5 0x0003a0UL //Access:RW DataWidth:0x20 // Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_UNCORR_COUNT_REPORT_OFF viewport data register. - #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_K2_E5 (0x1<<0) // Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared. - #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_K2_E5_SHIFT 0 - #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_K2_E5 (0x1<<4) // Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default. - #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_K2_E5_SHIFT 4 - #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_K2_E5 (0xf<<20) // Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved - #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_K2_E5_SHIFT 20 - #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_K2_E5 (0xff<<24) // Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf - #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_K2_E5_SHIFT 24 -#define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_K2_E5 0x0003a4UL //Access:R DataWidth:0x20 // Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF register. - #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_K2_E5 (0xff<<0) // Current uncorrected error count for the selected counter - #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_K2_E5_SHIFT 0 - #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_K2_E5 (0xf<<20) // Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved - #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_K2_E5_SHIFT 20 - #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_K2_E5 (0xff<<24) // Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register. - #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_K2_E5_SHIFT 24 -#define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_K2_E5 0x0003a8UL //Access:RW DataWidth:0x20 // Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs - #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_K2_E5 (0x1<<0) // Error injection global enable. When set enables the error insertion logic. - #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_K2_E5_SHIFT 0 - #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_K2_E5 (0x3<<4) // Error injection type: - 0: none - 1: 1-bit - 2: 2-bit - #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_K2_E5_SHIFT 4 - #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_K2_E5 (0xff<<8) // Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_K2_E5_SHIFT 8 - #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_K2_E5 (0xff<<16) // Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf - #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_K2_E5_SHIFT 16 -#define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_K2_E5 0x0003acUL //Access:R DataWidth:0x20 // Corrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_K2_E5 (0xf<<4) // Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved - #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_K2_E5_SHIFT 4 - #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_K2_E5 (0xff<<8) // Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf - #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_K2_E5_SHIFT 8 - #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_K2_E5 (0xf<<20) // Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved - #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_K2_E5_SHIFT 20 - #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_K2_E5 (0xff<<24) // Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf - #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_K2_E5_SHIFT 24 -#define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_K2_E5 0x0003b0UL //Access:R DataWidth:0x20 // Uncorrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_K2_E5 (0xf<<4) // Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved - #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_K2_E5_SHIFT 4 - #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_K2_E5 (0xff<<8) // Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf - #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_K2_E5_SHIFT 8 - #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_K2_E5 (0xf<<20) // Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved - #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_K2_E5_SHIFT 20 - #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_K2_E5 (0xff<<24) // Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf - #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_K2_E5_SHIFT 24 -#define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_K2_E5 0x0003b4UL //Access:RW DataWidth:0x20 // RASDP error mode enable. The core enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be correct; you must discard them. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_K2_E5 (0x1<<0) // Write '1' to enable the core enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_K2_E5_SHIFT 0 - #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_K2_E5 (0x1<<1) // Write '1' to enable the core to bring the link down when the core enters RASDP error mode. Note: This register field is sticky. - #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_K2_E5_SHIFT 1 -#define PCIEIP_REG_RASDP_ERROR_MODE_CLEAR_OFF_K2_E5 0x0003b8UL //Access:RW DataWidth:0x20 // Exit RASDP error mode. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_K2_E5 (0x1<<0) // Write '1' to take the core out of RASDP error mode. The core will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs. - #define PCIEIP_REG_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_K2_E5_SHIFT 0 -#define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_K2_E5 0x0003bcUL //Access:R DataWidth:0x20 // RAM Address where a corrected error (1-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_K2_E5 (0x7ffffff<<0) // RAM Address where a corrected error (1-bit ECC) has been detected. - #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_K2_E5_SHIFT 0 - #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_K2_E5 (0xf<<28) // RAM index where a corrected error (1-bit ECC) has been detected. - #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_K2_E5_SHIFT 28 -#define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_K2_E5 0x0003c0UL //Access:R DataWidth:0x20 // RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_K2_E5 (0x7ffffff<<0) // RAM Address where an uncorrected error (2-bit ECC) has been detected. - #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_K2_E5_SHIFT 0 - #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_K2_E5 (0xf<<28) // RAM index where an uncorrected error (2-bit ECC) has been detected. - #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_K2_E5_SHIFT 28 -#define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_K2_E5 0x0003c4UL //Access:RW DataWidth:0x20 // Precision Time Measurement Capability Header. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. - #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_CAP_ID_K2_E5 (0xffff<<0) // Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_CAP_VERSION_K2_E5 (0xf<<16) // Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_CAP_VERSION_K2_E5_SHIFT 16 - #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_NEXT_OFFSET_K2_E5 (0xfff<<20) // Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_NEXT_OFFSET_K2_E5_SHIFT 20 -#define PCIEIP_REG_PTM_CAP_OFF_K2_E5 0x0003c8UL //Access:RW DataWidth:0x20 // PTM Capability Register. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. - #define PCIEIP_REG_PTM_CAP_OFF_PTM_REQ_CAPABLE_K2_E5 (0x1<<0) // PTM Requester Capable. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_PTM_CAP_OFF_PTM_REQ_CAPABLE_K2_E5_SHIFT 0 - #define PCIEIP_REG_PTM_CAP_OFF_PTM_RES_CAPABLE_K2_E5 (0x1<<1) // PTM Responder Capable. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_PTM_CAP_OFF_PTM_RES_CAPABLE_K2_E5_SHIFT 1 - #define PCIEIP_REG_PTM_CAP_OFF_PTM_ROOT_CAPABLE_K2_E5 (0x1<<2) // PTM Root Capable. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_PTM_CAP_OFF_PTM_ROOT_CAPABLE_K2_E5_SHIFT 2 - #define PCIEIP_REG_PTM_CAP_OFF_PTM_CLK_GRAN_K2_E5 (0xff<<8) // PTM Local Clock Granularity. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) - #define PCIEIP_REG_PTM_CAP_OFF_PTM_CLK_GRAN_K2_E5_SHIFT 8 -#define PCIEIP_REG_PTM_CONTROL_OFF_K2_E5 0x0003ccUL //Access:RW DataWidth:0x20 // PTM Control Register. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. - #define PCIEIP_REG_PTM_CONTROL_OFF_PTM_ENABLE_K2_E5 (0x1<<0) // PTM Enable. When set, this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. - #define PCIEIP_REG_PTM_CONTROL_OFF_PTM_ENABLE_K2_E5_SHIFT 0 - #define PCIEIP_REG_PTM_CONTROL_OFF_ROOT_SELECT_K2_E5 (0x1<<1) // PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT - #define PCIEIP_REG_PTM_CONTROL_OFF_ROOT_SELECT_K2_E5_SHIFT 1 - #define PCIEIP_REG_PTM_CONTROL_OFF_EFF_GRAN_K2_E5 (0xff<<8) // PTM Effective Granularity. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT - #define PCIEIP_REG_PTM_CONTROL_OFF_EFF_GRAN_K2_E5_SHIFT 8 -#define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_K2_E5 0x0003d0UL //Access:RW DataWidth:0x20 // Precision Time Measurement Requester Capability Header (VSEC). For more details, see the PTM section in the Databook. - #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_ID_K2_E5 (0xffff<<0) // Precision Time Measurement Requester VSEC ID. For more details, see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_VER_K2_E5 (0xf<<16) // Precision Time Measurement Requester VSEC Version. For more details, see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_VER_K2_E5_SHIFT 16 - #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_NEXT_OFFS_K2_E5 (0xfff<<20) // Precision Time Measurement Requester VSEC Next Pointer. For more details, see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_NEXT_OFFS_K2_E5_SHIFT 20 -#define PCIEIP_REG_PTM_REQ_HDR_OFF_K2_E5 0x0003d4UL //Access:RW DataWidth:0x20 // Precision Time Measurement Requester Vendor Specific Header. For more details, see the PTM section in the Databook. - #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_ID_K2_E5 (0xffff<<0) // PTM Requester VSEC ID. For more details, see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_REV_K2_E5 (0xf<<16) // PTM Requester VSEC Revision. For more details, see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_REV_K2_E5_SHIFT 16 - #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_LENGTH_K2_E5 (0xfff<<20) // PTM Requester VSEC Length. For more details, see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_LENGTH_K2_E5_SHIFT 20 -#define PCIEIP_REG_PTM_REQ_CONTROL_OFF_K2_E5 0x0003d8UL //Access:RW DataWidth:0x20 // PTM Requester Vendor Specific Control Register. For more details, see the PTM section in the Databook. - #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_AUTO_UPDATE_ENABLED_K2_E5 (0x1<<0) // PTM Requester Auto Update Enabled - When enabled PTM Requester will automatically atempt to update it's context every 10ms. For more details, see the PTM section in the Databook. Note: This register field is sticky. - #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_AUTO_UPDATE_ENABLED_K2_E5_SHIFT 0 - #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_START_UPDATE_K2_E5 (0x1<<1) // PTM Requester Start Update - When set the PTM Requester will attempt a PTM Dialogue to update it's context; This bit is self clearing. For more details, see the PTM section in the Databook. - #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_START_UPDATE_K2_E5_SHIFT 1 - #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_FAST_TIMERS_K2_E5 (0x1<<2) // PTM Fast Timers - Debug mode for PTM Timers. The 100us timer output will go high at 30us and the 10ms timer output will go high at 100us (The Long Timer Value is ignored). There is no change to the 1us timer. The requester operation will otherwise remain the same. For more details, see the PTM section in the Databook. Note: This register field is sticky. - #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_FAST_TIMERS_K2_E5_SHIFT 2 - #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_LONG_TIMER_K2_E5 (0xff<<8) // PTM Requester Long Timer - Determines the period between each auto update PTM Dialogue in miliseconds. Update period is the register value +1 milisecond. For the Switch product this value must not be set larger than 0x9 for spec compliance. For more details, see the PTM section in the Databook. Note: This register field is sticky. - #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_LONG_TIMER_K2_E5_SHIFT 8 -#define PCIEIP_REG_PTM_REQ_STATUS_OFF_K2_E5 0x0003dcUL //Access:R DataWidth:0x20 // PTM Requester Vendor Specific Status Register. For more details, see the PTM section in the Databook. - #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_CONTEXT_VALID_K2_E5 (0x1<<0) // PTM Requester Context Valid - Indicate that the Timing Context is valid. For more details, see the PTM section in the Databook. - #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_CONTEXT_VALID_K2_E5_SHIFT 0 - #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_MANUAL_UPDATE_ALLOWED_K2_E5 (0x1<<1) // PTM Requester Manual Update Allowed - Indicates whether or not a Manual Update can be signalled. For more details, see the PTM section in the Databook. - #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_MANUAL_UPDATE_ALLOWED_K2_E5_SHIFT 1 -#define PCIEIP_REG_PTM_REQ_LOCAL_LSB_OFF_K2_E5 0x0003e0UL //Access:RW DataWidth:0x20 // PTM Requester Local Clock LSB For more details, see the PTM section in the Databook. -#define PCIEIP_REG_PTM_REQ_LOCAL_MSB_OFF_K2_E5 0x0003e4UL //Access:RW DataWidth:0x20 // PTM Requester Local Clock MSB. For more details, see the PTM section in the Databook. -#define PCIEIP_REG_PTM_REQ_T1_LSB_OFF_K2_E5 0x0003e8UL //Access:R DataWidth:0x20 // PTM Requester T1 Timestamp LSB. For more details, see the PTM section in the Databook. -#define PCIEIP_REG_PTM_REQ_T1_MSB_OFF_K2_E5 0x0003ecUL //Access:R DataWidth:0x20 // PTM Requester T1 Timestamp MSB. For more details, see the PTM section in the Databook. -#define PCIEIP_REG_PTM_REQ_T1P_LSB_OFF_K2_E5 0x0003f0UL //Access:R DataWidth:0x20 // PTM Requester T1 Previous Timestamp LSB. For more details, see the PTM section in the Databook. -#define PCIEIP_REG_PTM_REQ_T1P_MSB_OFF_K2_E5 0x0003f4UL //Access:R DataWidth:0x20 // PTM Requester T1 Previous Timestamp MSB. For more details, see the PTM section in the Databook. -#define PCIEIP_REG_PTM_REQ_T4_LSB_OFF_K2_E5 0x0003f8UL //Access:R DataWidth:0x20 // PTM Requester T4 Timestamp LSB. For more details, see the PTM section in the Databook. -#define PCIEIP_REG_PTM_REQ_T4_MSB_OFF_K2_E5 0x0003fcUL //Access:R DataWidth:0x20 // PTM Requester T4 Timestamp MSB. For more details, see the PTM section in the Databook. -#define PCIEIP_REG_PTM_REQ_T4P_LSB_OFF_K2_E5 0x000400UL //Access:R DataWidth:0x20 // PTM Requester T4 Previous Timestamp LSB. For more details, see the PTM section in the Databook. -#define PCIEIP_REG_PTM_REQ_T4P_MSB_OFF_K2_E5 0x000404UL //Access:R DataWidth:0x20 // PTM Requester T4 Previous Timestamp MSB. For more details, see the PTM section in the Databook. -#define PCIEIP_REG_PTM_REQ_MASTER_LSB_OFF_K2_E5 0x000408UL //Access:R DataWidth:0x20 // PTM Requester Master Time LSB. For more details, see the PTM section in the Databook. +#define PCIEIP_REG_PCIEEP_RAS_TBA_DATA_E5 0x00032cUL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_SD_CONTROL1_REG_K2 0x00032cUL //Access:RW DataWidth:0x20 // Silicon Debug Control 1. For more details, see the RAS DES section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE_K2 (0xffff<<0) // Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set, the core ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This register field is sticky. + #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE_K2_SHIFT 0 + #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_K2 (0x1<<16) // Force Detect Lane Enable. When this bit is set, the core ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky. + #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_K2_SHIFT 16 + #define PCIEIP_REG_SD_CONTROL1_REG_TX_EIOS_NUM_K2 (0x3<<20) // Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The core selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s, 8.0GT/s or higher: - 0x0: 1 - 0x1: 4 - 0x2: 8 - 0x3: 16 5.0GT/s: - 0x0: 2 - 0x1: 8 - 0x2: 16 - 0x3: 32 Note: This register field is sticky. + #define PCIEIP_REG_SD_CONTROL1_REG_TX_EIOS_NUM_K2_SHIFT 20 + #define PCIEIP_REG_SD_CONTROL1_REG_LOW_POWER_INTERVAL_K2 (0x3<<22) // Low Power Entry Interval Time. Interval Time that the core starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to, RXELECIDLE assertion at the PHY. - 0x0: 40ns - 0x1: 160ns - 0x2: 320ns - 0x3: 640ns Note: This register field is sticky. + #define PCIEIP_REG_SD_CONTROL1_REG_LOW_POWER_INTERVAL_K2_SHIFT 22 +#define PCIEIP_REG_SD_CONTROL2_REG_K2 0x000330UL //Access:RW DataWidth:0x20 // Silicon Debug Control 2. For more details, see the RAS DES section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_SD_CONTROL2_REG_HOLD_LTSSM_K2 (0x1<<0) // Hold and Release LTSSM. For as long as this register is '1', the core stays in the current LTSSM. Note: This register field is sticky. + #define PCIEIP_REG_SD_CONTROL2_REG_HOLD_LTSSM_K2_SHIFT 0 + #define PCIEIP_REG_SD_CONTROL2_REG_RECOVERY_REQUEST_K2 (0x1<<1) // Recovery Request. When this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization. + #define PCIEIP_REG_SD_CONTROL2_REG_RECOVERY_REQUEST_K2_SHIFT 1 + #define PCIEIP_REG_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_K2 (0x1<<2) // Force LinkDown. When this bit is set and the core detects REPLY_NUM rolling over 4 times, the LTSSM transitions to Detect State. Note: This register field is sticky. + #define PCIEIP_REG_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_K2_SHIFT 2 + #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_K2 (0x1<<8) // Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State, the LTSSM transitions to Configuration state. Note: This register field is sticky. + #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_K2_SHIFT 8 + #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_K2 (0x1<<9) // Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State, the LTSSM transitions to Detect state. Note: This register field is sticky. + #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_K2_SHIFT 9 + #define PCIEIP_REG_SD_CONTROL2_REG_DETECT_LPBKSLV_TO_EXIT_K2 (0x1<<10) // Detect Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State, the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky. + #define PCIEIP_REG_SD_CONTROL2_REG_DETECT_LPBKSLV_TO_EXIT_K2_SHIFT 10 + #define PCIEIP_REG_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_K2 (0x1<<16) // Framing Error Recovery Disable. This bit forces a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky. + #define PCIEIP_REG_SD_CONTROL2_REG_FRAMING_ERR_RECOVERY_DISABLE_K2_SHIFT 16 +#define PCIEIP_REG_SD_STATUS_L1LANE_REG_K2 0x00033cUL //Access:RW DataWidth:0x20 // Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_CONTROL1_REG For more details, see the RAS DES section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_SD_STATUS_L1LANE_REG_LANE_SELECT_K2 (0xf<<0) // Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L1LANE_REG_LANE_SELECT_K2_SHIFT 0 + #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_K2 (0x1<<16) // PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_K2_SHIFT 16 + #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_K2 (0x1<<17) // PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_K2_SHIFT 17 + #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXVALID_K2 (0x1<<18) // PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXVALID_K2_SHIFT 18 + #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_K2 (0x1<<19) // PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_K2_SHIFT 19 + #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_K2 (0x1<<20) // PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_K2_SHIFT 20 + #define PCIEIP_REG_SD_STATUS_L1LANE_REG_DESKEW_POINTER_K2 (0xff<<24) // Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L1LANE_REG_DESKEW_POINTER_K2_SHIFT 24 +#define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_K2 0x000340UL //Access:RW DataWidth:0x20 // Silicon Debug Status(Layer1 LTSSM). For more details, see the RAS DES section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_K2 (0x7f<<0) // First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received and it was not in TLP/DLLP reception - 02h: When current token was not a valid EDB token and previous token was an EDB. (128/256 bit core only) - 03h: When SDP token was received but not expected. (128 bit & (x8 | x16) core only) - 04h: When STP token was received but not expected. (128 bit & (x8 | x16) core only) - 05h: When EDS token was expected but not received or whenever an EDS token was received but not expected. - 06h: When a framing error was detected in the deskew block while a packet has been in progress in token_finder. Received Unexpected STP Token - 11h: When Framing CRC in STP token did not match - 12h: When Framing Parity in STP token did not match. - 13h: When Framing TLP Length in STP token was smaller than 5 DWORDs. Received Unexpected Block - 21h: When Receiving an OS Block following SDS in Datastream state - 22h: When Data Block followed by OS Block different from SKP, EI, EIE in Datastream state - 23h: When Block with an undefined Block Type in Datastream state - 24h: When Data Stream without data over three cycles in Datastream state - 25h: When OS Block during Data Stream in Datastream state - 26h: When RxStatus Error was detected in Datastream state - 27h: When Not all active lanes receiving SKP OS starting at same cycle time in SKPOS state - 28h: When a 2-Block timeout occurs for SKP OS in SKPOS state - 29h: When Receiving consecutive OS Blocks within a Data Stream in SKPOS state - 2Ah: When Phy status error was detected in SKPOS state - 2Bh: When Not all active lanes receiving EIOS starting at same cycle time in EIOS state - 2Ch: When At least one Symbol from the first 4 Symbols is not EIOS Symbol in EIOS state (CX_NB=2 only) - 2Dh: When Not all active lanes receiving EIEOS starting at same cycle time in EIEOS state - 2Eh: When Not full 16 eieos symbols are received in EIEOS state All other values not listed above are Reserved. Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_PTR_K2_SHIFT 0 + #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_K2 (0x1<<7) // Framing Error. Indicates Framing Error detection status. + #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_FRAMING_ERR_K2_SHIFT 7 + #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_K2 (0x7<<8) // PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_K2_SHIFT 8 + #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_K2 (0x1<<15) // Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_K2_SHIFT 15 + #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_K2 (0xffff<<16) // LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express base specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if both ports advertised the UpConfigure capability in the last Config.Complete. - 4: select_deemphasis - 5: start_equalization_w_preset - 6: equalization_done_8GT_data_rate - 7: equalization_done_16GT_data_rate - 15:8: idle_to_rlock_transitioned M-PCIe Mode: - 0: idle_to_recovery - 1: recovery_to_configuration Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_K2_SHIFT 16 +#define PCIEIP_REG_SD_STATUS_PM_REG_K2 0x000344UL //Access:RW DataWidth:0x20 // Silicon Debug Status(PM). For more details, see the RAS DES section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_K2 (0x1f<<0) // Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h: S_L1_EXIT - 8h: S_L23RDY - 9h: S_LINK_ENTR_L23 - Ah: S_L23RDY_WAIT4ALIVE - Bh: S_ACK_WAIT4IDLE Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_K2_SHIFT 0 + #define PCIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_K2 (0xf<<8) // Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah: L1_WAIT_LAST_TLP_ACK - 0Bh: L1_WAIT_PMDLLP_ACK - 0Ch: L1_LINK_ENTR_L1 - 0Dh: L1_EXIT - 0Fh: PREP_4L1 - 10h: L23_BLOCK_TLP - 11h: L23_WAIT_LAST_TLP_ACK - 12h: L23_WAIT_PMDLLP_ACK - 13h: L23_ENTR_L23 - 14h: L23RDY - 15h: PREP_4L23 - 16h: L23RDY_WAIT4ALIVE - 17h: L0S_BLOCK_TLP Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_K2_SHIFT 8 + #define PCIEIP_REG_SD_STATUS_PM_REG_PME_RESEND_FLAG_K2 (0x1<<12) // PME Re-send flag. When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%), the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent. + #define PCIEIP_REG_SD_STATUS_PM_REG_PME_RESEND_FLAG_K2_SHIFT 12 + #define PCIEIP_REG_SD_STATUS_PM_REG_LATCHED_NFTS_K2 (0xff<<16) // Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_PM_REG_LATCHED_NFTS_K2_SHIFT 16 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_EN_E5 0x000348UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_EINJ_EN_EINJ0_EN_E5 (0x1<<0) // CRC error injection enable. Enables insertion of errors into various CRC. See PCIEEP_RAS_EINJ_CTL0. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_EN_EINJ0_EN_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_EN_EINJ1_EN_E5 (0x1<<1) // Sequence number error injection enable. Enables insertion of errors into sequence numbers. See PCIEEP_RAS_EINJ_CTL1. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_EN_EINJ1_EN_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_EN_EINJ2_EN_E5 (0x1<<2) // DLLP error injection enable. enables insertion of DLLP errors. See PCIEEP_RAS_EINJ_CTL2. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_EN_EINJ2_EN_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_EN_EINJ3_EN_E5 (0x1<<3) // Symbol datak mask or sync header error enable. Enables data masking of special symbols or the breaking of the sync header. See PCIEEP_RAS_EINJ_CTL3. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_EN_EINJ3_EN_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_EN_EINJ4_EN_E5 (0x1<<4) // FC credit update error injection enable. Enables insertion of errors into Updated FCs. See PCIEEP_RAS_EINJ_CTL4. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_EN_EINJ4_EN_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_EN_EINJ5_EN_E5 (0x1<<5) // TLP duplicate/nullify error injection enable. Enables insertion of duplicate/nullified TLPs. For more details, refer to PCIEEP_RAS_EINJ_CTL5. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_EN_EINJ5_EN_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_EN_EINJ6_EN_E5 (0x1<<6) // Specific TLP error injection enable. Enables insertion of errors into the packet selected. For more details, refer to PCIEEP_RAS_EINJ_CTL6CMPP0. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_EN_EINJ6_EN_E5_SHIFT 6 +#define PCIEIP_REG_SD_STATUS_L2_REG_K2 0x000348UL //Access:R DataWidth:0x20 // Silicon Debug Status(Layer2). For more details, see the RAS DES section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_K2 (0xfff<<0) // Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_K2_SHIFT 0 + #define PCIEIP_REG_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_K2 (0xfff<<12) // Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_K2_SHIFT 12 + #define PCIEIP_REG_SD_STATUS_L2_REG_DLCMSM_K2 (0x3<<24) // DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L2_REG_DLCMSM_K2_SHIFT 24 + #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT1_K2 (0x1<<26) // FC_INIT1. Indicates the core is in FC_INIT1(VC0) state. Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT1_K2_SHIFT 26 + #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT2_K2 (0x1<<27) // FC_INIT2. Indicates the core is in FC_INIT2(VC0) state. Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT2_K2_SHIFT 27 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL0_E5 0x00034cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL0_EINJ0_CNT_E5 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented when errors are inserted. If the counter value is 0x1 and error is inserted, PCIEEP_RAS_EINJ_EN[EINJ0_EN] returns zero. If the counter value is 0x0 and PCIEEP_RAS_EINJ_EN[EINJ0_EN] is set, errors are inserted until PCIEEP_RAS_EINJ_EN[EINJ0_EN] is cleared. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL0_EINJ0_CNT_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL0_EINJ0_CRC_TYPE_E5 (0xf<<8) // Error injection type. Selects the type of CRC error tp in inserted. TX path: 0x0 = New TLP's LCRC error injection. 0x1 = 16bCRC error injection of ACK/NAK DLLP. 0x2 = 16bCRC error injection of Update-FC DLLP. 0x3 = New TLP's ECRC error injection. 0x4 = TLP's FCRC error injection (128b/130b). 0x5 = Parity error of TSOS (128b/130b). 0x6 = Parity error of SKPOS (128b/130b). 0x7 = Reserved. RX path: 0x8 = LCRC error injection. 0x9 = ECRC error injection. 0xA - 0xF = Reserved. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL0_EINJ0_CRC_TYPE_E5_SHIFT 8 +#define PCIEIP_REG_SD_STATUS_L3FC_REG_K2 0x00034cUL //Access:RW DataWidth:0x20 // Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE - CREDIT_SEL_HD For more details, see the RAS DES section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_K2 (0x7<<0) // Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 - 0x1: VC1 - 0x2: VC2 - .. - 0x7: VC7 Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_K2_SHIFT 0 + #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_K2 (0x1<<3) // Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Rx - 0x1: Tx Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_K2_SHIFT 3 + #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_K2 (0x3<<4) // Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Posted - 0x1: Non-Posted - 0x2: Completion Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_K2_SHIFT 4 + #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_K2 (0x1<<6) // Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: Header Credit - 0x1: Data Credit Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_K2_SHIFT 6 + #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA0_K2 (0xfff<<8) // Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA0_K2_SHIFT 8 + #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA1_K2 (0xfff<<20) // Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when DLCMSM=0x3(DL_ACTIVE). Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA1_K2_SHIFT 20 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL1_E5 0x000350UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL1_EINJ1_CNT_E5 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented when errors are inserted. If the counter value is 0x1 and error is inserted, PCIEEP_RAS_EINJ_EN[EINJ1_EN] returns zero. If the counter value is 0x0 and PCIEEP_RAS_EINJ_EN[EINJ1_EN] is set, errors are inserted until PCIEEP_RAS_EINJ_EN[EINJ1_EN] is cleared. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL1_EINJ1_CNT_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL1_EINJ1_SEQNUM_TYPE_E5 (0x1<<8) // Sequence number type. Selects the type of sequence number. 0x0 = Insertion of New TLP's SEQ error. 0x1 = Insertion of ACK/NAK DLLP's SEQ error. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL1_EINJ1_SEQNUM_TYPE_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL1_EINJ1_BAD_SEQNUM_E5 (0x1fff<<16) // Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. 0x0FFF = +4095. 0x0002 = +2. 0x0001 = +1. 0x0000 = 0. 0x1FFF = -1. 0x1FFE = -2. 0x1001 = -4095. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL1_EINJ1_BAD_SEQNUM_E5_SHIFT 16 +#define PCIEIP_REG_SD_STATUS_L3_REG_K2 0x000350UL //Access:RW DataWidth:0x20 // Silicon Debug Status(Layer3). For more details, see the RAS DES section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_POINTER_K2 (0x7f<<0) // First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length miss match - 05h: Max payload size - 06h: Message TLP without TC0 - 07h: Invalid TC - 08h: Unexpected route bit in Message TLP - 09h: Unexpected CRS status in Completion TLP - 0Ah: Byte enable - 0Bh: Memory Address 4KB boundary - 0Ch: TLP prefix rules - 0Dh: Translation request rules - 0Eh: Invalid TLP type - 0Fh: Completion rules - 7Fh: Application - Else: Reserved Note: This register field is sticky. + #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_POINTER_K2_SHIFT 0 + #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_STATUS_K2 (0x1<<7) // Malformed TLP Status. Indicates malformed TLP has occurred. + #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_STATUS_K2_SHIFT 7 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL2_E5 0x000354UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL2_EINJ2_CNT_E5 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented when errors are inserted. If the counter value is 0x1 and error is inserted, PCIEEP_RAS_EINJ_EN[EINJ2_EN] returns zero. If the counter value is 0x0 and PCIEEP_RAS_EINJ_EN[EINJ2_EN] is set, errors are inserted until PCIEEP_RAS_EINJ_EN[EINJ2_EN] is cleared. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL2_EINJ2_CNT_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL2_EINJ2_DLLP_TYPE_E5 (0x3<<8) // DLLP type. Selects the type of DLLP errors to be inserted. 0x0 = ACK/NAK DLLP transmission block. 0x1 = Update FC DLLP's transmission block. 0x2 = Always transmission for NAK DLLP. 0x3 = Reserved. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL2_EINJ2_DLLP_TYPE_E5_SHIFT 8 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL3_E5 0x000358UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL3_EINJ3_CNT_E5 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented when errors are inserted. If the counter value is 0x1 and error is inserted, PCIEEP_RAS_EINJ_EN[EINJ3_EN] returns zero. If the counter value is 0x0 and PCIEEP_RAS_EINJ_EN[EINJ3_EN] is set, errors are inserted until PCIEEP_RAS_EINJ_EN[EINJ3_EN] is cleared. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL3_EINJ3_CNT_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL3_EINJ3_SYMBOL_TYPE_E5 (0x7<<8) // Error type, 8 b/10 b encoding - Mask K symbol. 0x0 = Reserved. 0x1 = COM/PAD(TS1 Order Set). 0x2 = COM/PAD(TS2 Order Set). 0x3 = COM/FTS(FTS Order Set). 0x4 = COM/IDLE(E-Idle Order Set). 0x5 = END/EDB Symbol. 0x6 = STP/SDP Symbol. 0x7 = COM/SKP(SKP Order set). + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL3_EINJ3_SYMBOL_TYPE_E5_SHIFT 8 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL4_E5 0x00035cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL4_EINJ4_CNT_E5 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented when errors are inserted. If the counter value is 0x1 and error is inserted, PCIEEP_RAS_EINJ_EN[EINJ4_EN] returns zero. If the counter value is 0x0 and PCIEEP_RAS_EINJ_EN[EINJ4_EN] is set, errors are inserted until PCIEEP_RAS_EINJ_EN[EINJ4_EN] is cleared. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL4_EINJ4_CNT_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL4_EINJ4_VC_TYPE_E5 (0x7<<8) // Update-FC type. Selects the credit type. 0x0 = Posted TLP header credit value control. 0x1 = Non-Posted TLP header credit value control. 0x2 = Completion TLP header credit value control. 0x3 = Reserved. 0x4 = Posted TLP data credit value control. 0x5 = Non-Posted TLP data credit value control. 0x6 = Completion TLP data credit value control. 0x7 = Reserved. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL4_EINJ4_VC_TYPE_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL4_EINJ4_VC_NUM_E5 (0x7<<12) // VC number. Indicates the target VC number. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL4_EINJ4_VC_NUM_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL4_EINJ4_BAD_UPDFC_VAL_E5 (0x1fff<<16) // Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. The value is represented by two's compliment. 0x0FFF = +4095. 0x0002 = +2. 0x0001 = +1. 0x0000 = 0. 0x1FFF = -1. 0x1FFE = -2. 0x1001 = -4095. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL4_EINJ4_BAD_UPDFC_VAL_E5_SHIFT 16 +#define PCIEIP_REG_SD_EQ_CONTROL1_REG_K2 0x00035cUL //Access:RW DataWidth:0x20 // Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport registers. For more details, see the RAS DES section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_K2 (0xf<<0) // EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EQ_LANE_SEL_K2_SHIFT 0 + #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_K2 (0x1<<4) // EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed - 0x1: 16.0GT/s Speed Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EQ_RATE_SEL_K2_SHIFT 4 + #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_K2 (0x3<<16) // Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL1_REG_EVAL_INTERVAL_TIME_K2_SHIFT 16 + #define PCIEIP_REG_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_K2 (0x1<<23) // FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL1_REG_FOM_TARGET_ENABLE_K2_SHIFT 23 + #define PCIEIP_REG_SD_EQ_CONTROL1_REG_FOM_TARGET_K2 (0xff<<24) // FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL1_REG_FOM_TARGET_K2_SHIFT 24 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL5_E5 0x000360UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL5_EINJ5_CNT_E5 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented when errors are inserted. If the counter value is 0x1 and error is inserted, PCIEEP_RAS_EINJ_EN[EINJ5_EN] returns zero. If the counter value is 0x0 and PCIEEP_RAS_EINJ_EN[EINJ5_EN] is set, errors are inserted until PCIEEP_RAS_EINJ_EN[EINJ5_EN] is cleared. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL5_EINJ5_CNT_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL5_EINJ5_SP_TLP_E5 (0x1<<8) // Specified TLP. Selects the specified TLP to be inserted. 0x0 = Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. 0x1 = Generates nullified TLP (Original TLP will be stored in retry buffer). + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL5_EINJ5_SP_TLP_E5_SHIFT 8 +#define PCIEIP_REG_SD_EQ_CONTROL2_REG_K2 0x000360UL //Access:RW DataWidth:0x20 // Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details, see the RAS DES section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_K2 (0x3f<<0) // Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRE_CURSOR_K2_SHIFT 0 + #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_K2 (0x3f<<6) // Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_CURSOR_K2_SHIFT 6 + #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_K2 (0x3f<<12) // Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_POST_CURSOR_K2_SHIFT 12 + #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_K2 (0x7<<18) // Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3), instead of received or set value. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_K2_SHIFT 18 + #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_K2 (0xf<<24) // Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_K2_SHIFT 24 + #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_K2 (0x1<<28) // Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_COEF_ENABLE_K2_SHIFT 28 + #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_K2 (0x1<<29) // Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_RX_HINT_ENABLE_K2_SHIFT 29 + #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_K2 (0x1<<30) // Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL2_REG_FORCE_LOCAL_TX_PRESET_ENABLE_K2_SHIFT 30 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6CMPP0_E5 0x000364UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_SD_EQ_CONTROL3_REG_K2 0x000364UL //Access:RW DataWidth:0x20 // Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details, see the RAS DES section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_K2 (0x3f<<0) // Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from link partner. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_PRE_CURSOR_K2_SHIFT 0 + #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_K2 (0x3f<<6) // Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from link partner. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_CURSOR_K2_SHIFT 6 + #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_K2 (0x3f<<12) // Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from link partner. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_POST_CURSOR_K2_SHIFT 12 + #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_K2 (0x1<<28) // Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_CONTROL3_REG_FORCE_REMOTE_TX_COEF_ENABLE_K2_SHIFT 28 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6CMPP1_E5 0x000368UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6CMPP2_E5 0x00036cUL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_SD_EQ_STATUS1_REG_K2 0x00036cUL //Access:R DataWidth:0x20 // Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The following fields are available when Equalization finished unsuccessfully(EQ_CONVERGENCE_INFO=2). - EQ_RULEA_VIOLATION - EQ_RULEB_VIOLATION - EQ_RULEC_VIOLATION - EQ_REJECT_EVENT For more details, see the RAS DES section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_SEQUENCE_K2 (0x1<<0) // EQ Sequence. Indicates that the core is starting the equalization sequence. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_SEQUENCE_K2_SHIFT 0 + #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_K2 (0x3<<1) // EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically cleared when the core starts EQ Master phase again. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_CONVERGENCE_INFO_K2_SHIFT 1 + #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_K2 (0x1<<4) // EQ Rule A Violation. Indicates that coefficient rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the core starts EQ Master phase again. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEA_VIOLATION_K2_SHIFT 4 + #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_K2 (0x1<<5) // EQ Rule B Violation. Indicates that coefficient rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the core starts EQ Master phase again. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEB_VIOLATION_K2_SHIFT 5 + #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_K2 (0x1<<6) // EQ Rule C Violation. Indicates that coefficient rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the core starts EQ Master phase again. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_RULEC_VIOLATION_K2_SHIFT 6 + #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_K2 (0x1<<7) // EQ Reject Event. Indicates that the core receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the core starts EQ Master phase again. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_STATUS1_REG_EQ_REJECT_EVENT_K2_SHIFT 7 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6CMPP3_E5 0x000370UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_SD_EQ_STATUS2_REG_K2 0x000370UL //Access:R DataWidth:0x20 // Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1). For more details, see the RAS DES section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_K2 (0x3f<<0) // EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_PRE_CURSOR_K2_SHIFT 0 + #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_K2 (0x3f<<6) // EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_CURSOR_K2_SHIFT 6 + #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_K2 (0x3f<<12) // EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_POST_CURSOR_K2_SHIFT 12 + #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_K2 (0x7<<18) // EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_RX_HINT_K2_SHIFT 18 + #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_K2 (0xff<<24) // EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_STATUS2_REG_EQ_LOCAL_FOM_VALUE_K2_SHIFT 24 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6CMPV0_E5 0x000374UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_SD_EQ_STATUS3_REG_K2 0x000374UL //Access:R DataWidth:0x20 // Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field is available when Equalization finished successfully(EQ_CONVERGENCE_INFO=1). For more details, see the RAS DES section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_K2 (0x3f<<0) // EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_PRE_CURSOR_K2_SHIFT 0 + #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_K2 (0x3f<<6) // EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_CURSOR_K2_SHIFT 6 + #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_K2 (0x3f<<12) // EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_POST_CURSOR_K2_SHIFT 12 + #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_K2 (0x3f<<18) // EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_LF_K2_SHIFT 18 + #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_K2 (0x3f<<24) // EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky. + #define PCIEIP_REG_SD_EQ_STATUS3_REG_EQ_REMOTE_FS_K2_SHIFT 24 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6CMPV1_E5 0x000378UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6CMPV2_E5 0x00037cUL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6CMPV3_E5 0x000380UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6CHGP0_E5 0x000384UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6CHGP1_E5 0x000388UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6CHGP2_E5 0x00038cUL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_K2 0x00038cUL //Access:RW DataWidth:0x20 // PCIe Extended capability ID, Capability version and Next capability offset. + #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_ID_K2 (0xffff<<0) // PCI Express Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_ID_K2_SHIFT 0 + #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_CAP_K2 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_CAP_K2_SHIFT 16 + #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_K2 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_K2_SHIFT 20 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6CHGP3_E5 0x000390UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_K2 0x000390UL //Access:R DataWidth:0x20 // Vendor Specific Header. + #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_K2 (0xffff<<0) // VSEC ID. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_K2_SHIFT 0 + #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_K2 (0xf<<16) // VSEC Rev. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_K2_SHIFT 16 + #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_K2 (0xfff<<20) // VSEC Length. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_K2_SHIFT 20 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6CHGV0_E5 0x000394UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_K2 0x000394UL //Access:RW DataWidth:0x20 // ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native core clock (core_clk), you must not write this register while operations are in progress in the AXI master / slave interface. + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_K2 (0x1<<0) // Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_K2_SHIFT 0 + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_K2 (0x1<<1) // Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_K2_SHIFT 1 + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_K2 (0x1<<2) // Error correction disable for AXI bridge outbound request path. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_K2_SHIFT 2 + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_K2 (0x1<<3) // Error correction disable for DMA write engine. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_K2_SHIFT 3 + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_K2 (0x1<<4) // Error correction disable for layer 2 Tx path. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_K2_SHIFT 4 + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_K2 (0x1<<5) // Error correction disable for layer 3 Tx path. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_K2_SHIFT 5 + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_K2 (0x1<<6) // Error correction disable for Adm Tx path. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_K2_SHIFT 6 + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_K2 (0x1<<16) // Global error correction disable for all Rx layers. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_K2_SHIFT 16 + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_K2 (0x1<<17) // Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_K2_SHIFT 17 + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_K2 (0x1<<18) // Error correction disable for AXI bridge inbound request path. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_K2_SHIFT 18 + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_K2 (0x1<<19) // Error correction disable for DMA read engine. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_K2_SHIFT 19 + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_K2 (0x1<<20) // Error correction disable for layer 2 Rx path. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_K2_SHIFT 20 + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_K2 (0x1<<21) // Error correction disable for layer 3 Rx path. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_K2_SHIFT 21 + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_K2 (0x1<<22) // Error correction disable for ADM Rx path. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_K2_SHIFT 22 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6CHGV1_E5 0x000398UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_K2 0x000398UL //Access:RW DataWidth:0x20 // Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_CORR_COUNT_REPORT_OFF viewport data register. + #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_K2 (0x1<<0) // Clear all correctable error counters. + #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_K2_SHIFT 0 + #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_K2 (0x1<<4) // Enable correctable errors counters. - 1: counters increment when the core detects a correctable error - 0: counters are frozen The counters are enabled by default. + #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_K2_SHIFT 4 + #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_K2 (0xf<<20) // Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved + #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_K2_SHIFT 20 + #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_K2 (0xff<<24) // Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf + #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_K2_SHIFT 24 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6CHGV2_E5 0x00039cUL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_K2 0x00039cUL //Access:R DataWidth:0x20 // Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register. + #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_K2 (0xff<<0) // Current corrected error count for the selected counter. + #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_K2_SHIFT 0 + #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_K2 (0xf<<20) // Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved + #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_K2_SHIFT 20 + #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_K2 (0xff<<24) // Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register. + #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_K2_SHIFT 24 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6CHGV3_E5 0x0003a0UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_K2 0x0003a0UL //Access:RW DataWidth:0x20 // Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_UNCORR_COUNT_REPORT_OFF viewport data register. + #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_K2 (0x1<<0) // Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared. + #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_K2_SHIFT 0 + #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_K2 (0x1<<4) // Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default. + #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_K2_SHIFT 4 + #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_K2 (0xf<<20) // Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved + #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_K2_SHIFT 20 + #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_K2 (0xff<<24) // Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf + #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_K2_SHIFT 24 +#define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6PE_E5 0x0003a4UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6PE_EINJ6_CNT_E5 (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented when errors are inserted. If the counter value is 0x1 and error is inserted, PCIEEP_RAS_EINJ_EN[EINJ6_EN] returns zero. If the counter value is 0x0 and PCIEEP_RAS_EINJ_EN[EINJ6_EN] is set, errors are inserted until PCIEEP_RAS_EINJ_EN[EINJ6_EN] is cleared. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6PE_EINJ6_CNT_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6PE_EINJ6_INV_CNTRL_E5 (0x1<<8) // Inverted error injection control. 0x0 = EINJ6_CHG_VAL_H[0/1/2/3] is used to replace bits specified by EINJ6_CHG_PT_H[0/1/2/3]. 0x1 = EINJ6_CHG_VAL_H[0/1/2/3] is ignored and inverts bits specified by EINJ6_CHG_PT_H[0/1/2/3]. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6PE_EINJ6_INV_CNTRL_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6PE_EINJ6_PKT_TYP_E5 (0x7<<9) // Packet type. Selects the TLP packets to inject errors into. 0x0 = TLP header. 0x1 = TLP prefix 1st 4-DWORDs. 0x2 = TLP prefix 2nd 4-DWORDs. 0x3 - 0x7 = Reserved. + #define PCIEIP_REG_PCIEEP_RAS_EINJ_CTL6PE_EINJ6_PKT_TYP_E5_SHIFT 9 +#define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_K2 0x0003a4UL //Access:R DataWidth:0x20 // Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF register. + #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_K2 (0xff<<0) // Current uncorrected error count for the selected counter + #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_K2_SHIFT 0 + #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_K2 (0xf<<20) // Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved + #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_K2_SHIFT 20 + #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_K2 (0xff<<24) // Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register. + #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_K2_SHIFT 24 +#define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_K2 0x0003a8UL //Access:RW DataWidth:0x20 // Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs + #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_K2 (0x1<<0) // Error injection global enable. When set enables the error insertion logic. + #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_K2_SHIFT 0 + #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_K2 (0x3<<4) // Error injection type: - 0: none - 1: 1-bit - 2: 2-bit + #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_K2_SHIFT 4 + #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_K2 (0xff<<8) // Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected + #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_K2_SHIFT 8 + #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_K2 (0xff<<16) // Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf + #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_K2_SHIFT 16 +#define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_K2 0x0003acUL //Access:R DataWidth:0x20 // Corrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_K2 (0xf<<4) // Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved + #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_K2_SHIFT 4 + #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_K2 (0xff<<8) // Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf + #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_K2_SHIFT 8 + #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_K2 (0xf<<20) // Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved + #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_K2_SHIFT 20 + #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_K2 (0xff<<24) // Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf + #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_K2_SHIFT 24 +#define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_K2 0x0003b0UL //Access:R DataWidth:0x20 // Uncorrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_K2 (0xf<<4) // Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved + #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_K2_SHIFT 4 + #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_K2 (0xff<<8) // Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf + #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_K2_SHIFT 8 + #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_K2 (0xf<<20) // Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge inbound request path - 0x5: Region select for AXI bridge inbound completion composer path - 0x6: Region select for Adm Tx path - 0x7: Region select for layer 3 Tx path - 0x8: Region select for layer 2 Tx path - 0x9: Region select for DMA outbound path - 0xa: Region select for AXI bridge outbound request path - 0xb: Region select for AXI bridge outbound master completion buffer path - 0xc: Reserved - 0xf: Reserved + #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_K2_SHIFT 20 + #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_K2 (0xff<<24) // Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf + #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_K2_SHIFT 24 +#define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_K2 0x0003b4UL //Access:RW DataWidth:0x20 // RASDP error mode enable. The core enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be correct; you must discard them. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_K2 (0x1<<0) // Write '1' to enable the core enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_K2_SHIFT 0 + #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_K2 (0x1<<1) // Write '1' to enable the core to bring the link down when the core enters RASDP error mode. Note: This register field is sticky. + #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_K2_SHIFT 1 +#define PCIEIP_REG_PCIEEP_RAS_SD_CTL1_E5 0x0003b8UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL1_FORCE_DETECT_LANE_E5 (0xffff<<0) // Force detect lane. When set, the core ignores receiver detection from PHY during LTSSM detect state and uses this value instead. 0x0 = Lane0. 0x1 = Lane1. 0x2 = Lane2. 0x7 = Lane7. + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL1_FORCE_DETECT_LANE_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL1_FORCE_DETECT_LANE_EN_E5 (0x1<<16) // Force detect lane enable. When this bit is set, the core ignores receiver detection from PHY during LTSSM detect state and uses [FORCE_DETECT_LANE]. + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL1_FORCE_DETECT_LANE_EN_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL1_TX_EIOS_NUM_E5 (0x3<<20) // Number of TX EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and disable/loopback/hot-reset exit. The core selects the greater value between this register and the value defined by the PCI-SIG specification. Gen1 or Gen3 0x0 = 1. 0x1 = 4. 0x2 = 8. 0x3 - 16. Gen2 0x0 = 2. 0x1 = 8. 0x2 = 16. 0x3 - 32. + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL1_TX_EIOS_NUM_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL1_LP_INTV_E5 (0x3<<22) // Low power entry interval time. Interval time that the core starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to, RXELECIDLE assertion at the PHY 0x0 = 40ns. 0x1 = 160ns. 0x2 = 320ns. 0x3 - 640ns. + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL1_LP_INTV_E5_SHIFT 22 +#define PCIEIP_REG_RASDP_ERROR_MODE_CLEAR_OFF_K2 0x0003b8UL //Access:RW DataWidth:0x20 // Exit RASDP error mode. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_K2 (0x1<<0) // Write '1' to take the core out of RASDP error mode. The core will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs. + #define PCIEIP_REG_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_K2_SHIFT 0 +#define PCIEIP_REG_PCIEEP_RAS_SD_CTL2_E5 0x0003bcUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL2_HOLD_LTSSM_E5 (0x1<<0) // Hold and release LTSSM. For as long as this is set, the core stays in the current LTSSM. + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL2_HOLD_LTSSM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL2_RCRY_REQ_E5 (0x1<<1) // Recovery request. When this bit is set in L0 or L0s, the LTSSM starts transitioning to recovery state. This request does not cause a speed change or reequalization. This bit always reads a zero. + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL2_RCRY_REQ_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL2_NOACK_FORCE_LNKDN_E5 (0x1<<2) // Force link down. When this bit is set and the core detects REPLY_NUM rolling over 4 times, the LTSSM transitions to detect state. + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL2_NOACK_FORCE_LNKDN_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL2_DIR_RECIDLE_CONFIG_E5 (0x1<<8) // Direct Recovery.Idle to configuration. When this bit is set and the LTSSM is in recovery idle state, the LTSSM transitions to configuration state. + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL2_DIR_RECIDLE_CONFIG_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL2_DIR_POLCMP_TO_DET_E5 (0x1<<9) // Direct Polling.Compliance to detect. When this bit is set and the LTSSM is in polling compliance state, the LTSSM transitions to detect state. + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL2_DIR_POLCMP_TO_DET_E5_SHIFT 9 + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL2_DIR_LPBSLV_TO_EXIT_E5 (0x1<<10) // Direct loopback slave to exit. When set and the LTSSM is in loopback slave active state, the LTSSM transitions to the loopback slave exit state. + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL2_DIR_LPBSLV_TO_EXIT_E5_SHIFT 10 + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL2_FR_ERR_RCVY_DIS_E5 (0x1<<16) // Framing error recovery disable. This bit disables a transition to recovery state when a framing error has occurred. + #define PCIEIP_REG_PCIEEP_RAS_SD_CTL2_FR_ERR_RCVY_DIS_E5_SHIFT 16 +#define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_K2 0x0003bcUL //Access:R DataWidth:0x20 // RAM Address where a corrected error (1-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_K2 (0x7ffffff<<0) // RAM Address where a corrected error (1-bit ECC) has been detected. + #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_K2_SHIFT 0 + #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_K2 (0xf<<28) // RAM index where a corrected error (1-bit ECC) has been detected. + #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_K2_SHIFT 28 +#define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_K2 0x0003c0UL //Access:R DataWidth:0x20 // RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_K2 (0x7ffffff<<0) // RAM Address where an uncorrected error (2-bit ECC) has been detected. + #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_K2_SHIFT 0 + #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_K2 (0xf<<28) // RAM index where an uncorrected error (2-bit ECC) has been detected. + #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_K2_SHIFT 28 +#define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_K2 0x0003c4UL //Access:RW DataWidth:0x20 // Precision Time Measurement Capability Header. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. + #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_CAP_ID_K2 (0xffff<<0) // Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_CAP_VERSION_K2 (0xf<<16) // Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_CAP_VERSION_K2_SHIFT 16 + #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_NEXT_OFFSET_K2 (0xfff<<20) // Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_NEXT_OFFSET_K2_SHIFT 20 +#define PCIEIP_REG_PCIEEP_RAS_SD_L1LANE_E5 0x0003c8UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LANE_LANE_SELECT_E5 (0xf<<0) // Lane select. Lane select register for silicon debug status register of Layer1-PerLane. 0x0 = Lane0. 0x1 = Lane1. 0x2 = Lane2. 0x7 = Lane7. 0x8-0xF = Reserved. + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LANE_LANE_SELECT_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LANE_PIPE_RXPOL_E5 (0x1<<16) // PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number ([LANE_SELECT]). + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LANE_PIPE_RXPOL_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LANE_PIPE_DET_LANE_E5 (0x1<<17) // PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number ([LANE_SELECT]). + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LANE_PIPE_DET_LANE_E5_SHIFT 17 + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LANE_PIPE_RXVALID_E5 (0x1<<18) // PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number ([LANE_SELECT]). + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LANE_PIPE_RXVALID_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LANE_PIPE_RXELECIDLE_E5 (0x1<<19) // PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number ([LANE_SELECT]). + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LANE_PIPE_RXELECIDLE_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LANE_PIPE_TXELECIDLE_E5 (0x1<<20) // PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number ([LANE_SELECT]). + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LANE_PIPE_TXELECIDLE_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LANE_DESKEW_PTR_E5 (0xff<<24) // Deskew pointer. Indicates deskew pointer of internal deskew buffer of selected lane number ([LANE_SELECT]). + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LANE_DESKEW_PTR_E5_SHIFT 24 +#define PCIEIP_REG_PTM_CAP_OFF_K2 0x0003c8UL //Access:RW DataWidth:0x20 // PTM Capability Register. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. + #define PCIEIP_REG_PTM_CAP_OFF_PTM_REQ_CAPABLE_K2 (0x1<<0) // PTM Requester Capable. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_PTM_CAP_OFF_PTM_REQ_CAPABLE_K2_SHIFT 0 + #define PCIEIP_REG_PTM_CAP_OFF_PTM_RES_CAPABLE_K2 (0x1<<1) // PTM Responder Capable. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_PTM_CAP_OFF_PTM_RES_CAPABLE_K2_SHIFT 1 + #define PCIEIP_REG_PTM_CAP_OFF_PTM_ROOT_CAPABLE_K2 (0x1<<2) // PTM Root Capable. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_PTM_CAP_OFF_PTM_ROOT_CAPABLE_K2_SHIFT 2 + #define PCIEIP_REG_PTM_CAP_OFF_PTM_CLK_GRAN_K2 (0xff<<8) // PTM Local Clock Granularity. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) + #define PCIEIP_REG_PTM_CAP_OFF_PTM_CLK_GRAN_K2_SHIFT 8 +#define PCIEIP_REG_PCIEEP_RAS_SD_L1LTSSM_E5 0x0003ccUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LTSSM_FRAMING_ERR_PTR_E5 (0x7f<<0) // First framing error pointer. Identifies the first framing error using the following encoding. The field contents are only valid value when [FRAMING_ERR] = 1. Received unexpected framing token: 0x1 = When non-STP/SDP/IDL token was received and it was not in TLP/DLLP reception. 0x02 = When current token was not a valid EDB token and previous token was an EDB. (128/256 bit core only). 0x03 = When SDP token was received but not expected. 0x04 = When STP token was received but not expected. 0x05 = When EDS token was expected but not received or whenever an EDS token was received but not expected. 0x06 = When a framing error was detected in the deskew block while a packet has been in progress in token_finder. Received Unexpected STP Token 0x11 = When framing CRC in STP token did not match. 0x12 = When framing parity in STP token did not match. 0x13 = When framing TLP length in STP token was smaller than 5 DWORDs. <page> Received unexpected block: 0x21 = When receiving an OS block following SDS in datastream state.n. 0x22 = When data block followed by OS block different. from SKP, EI, EIE in datastream state. 0x23 = When block with an undefined block type in datastream state. 0x24 = When data stream without data over three cycles in datastream state. 0x25 = When OS block during data stream in datastream state. 0x26 = When RxStatus error was detected in datastream state. 0x27 = When not all active lanes receiving SKP OS starting at same cycle time in SKPOS state. 0x28 = When a two-block timeout occurs for SKP OS in SKPOS state. 0x29 = When receiving consecutive OS blocks within a data stream in SKPOS state.n. 0x2A = When Phy status error was detected in SKPOS state. 0x2B = When not all active lanes receiving EIOS starting at same cycle time in EIOS state. 0x2C = When at least one symbol from the first 4 symbols is not EIOS symbol in EIOS state (CX_NB=2 only). 0x2D = When not all active lanes receiving EIEOS starting at same cycle time in EIEOS state. 0x2E = When not full 16 eieos symbols are received in EIEOS state. All other values not listed above are reserved. + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LTSSM_FRAMING_ERR_PTR_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LTSSM_FRAMING_ERR_E5 (0x1<<7) // Framing error. Indicates framing error detection status. + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LTSSM_FRAMING_ERR_E5_SHIFT 7 + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LTSSM_PIPE_PWR_DWN_E5 (0x7<<8) // PIPE:PowerDown. Indicates PIPE PowerDown signal. + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LTSSM_PIPE_PWR_DWN_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LTSSM_LANE_REV_E5 (0x1<<15) // Lane reversal operation. Receiver detected lane reversal. + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LTSSM_LANE_REV_E5_SHIFT 15 + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LTSSM_LTSSM_VAR_E5 (0xffff<<16) // LTSSM variable. Indicates internal LTSSM variables defined in the PCI Express base specification. 0x0 = directed_speed change. 0x1 = changed_speed_recovery. 0x2 = successful_speed_negotiation. 0x3 = upconfigure_capable; Set to one if both ports advertised the UpConfigure capability in the last Config.Complete. 0x4 = select_deemphasis. 0x5 = start_equalization_w_preset. 0x6 = equalization_done_8GT_data_rate. 0x7 = equalization_done_16GT_data_rate. 0x8-0xF = idle_to_rlock_transitioned. + #define PCIEIP_REG_PCIEEP_RAS_SD_L1LTSSM_LTSSM_VAR_E5_SHIFT 16 +#define PCIEIP_REG_PTM_CONTROL_OFF_K2 0x0003ccUL //Access:RW DataWidth:0x20 // PTM Control Register. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. + #define PCIEIP_REG_PTM_CONTROL_OFF_PTM_ENABLE_K2 (0x1<<0) // PTM Enable. When set, this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. + #define PCIEIP_REG_PTM_CONTROL_OFF_PTM_ENABLE_K2_SHIFT 0 + #define PCIEIP_REG_PTM_CONTROL_OFF_ROOT_SELECT_K2 (0x1<<1) // PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT + #define PCIEIP_REG_PTM_CONTROL_OFF_ROOT_SELECT_K2_SHIFT 1 + #define PCIEIP_REG_PTM_CONTROL_OFF_EFF_GRAN_K2 (0xff<<8) // PTM Effective Granularity. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0. Note: The access attributes of this field are as follows: - Dbi: HWINIT + #define PCIEIP_REG_PTM_CONTROL_OFF_EFF_GRAN_K2_SHIFT 8 +#define PCIEIP_REG_PCIEEP_RAS_SD_STATUSPM_E5 0x0003d0UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSPM_INT_PM_MSTATE_E5 (0x1f<<0) // Internal PM state (master). Indicates internal state machine of power management master controller. 0x00 = IDLE. 0x01 = L0. 0x02 = L0S. 0x03 = ENTER_L0S. 0x04 = L0S_EXIT. 0x08 = L1. 0x09 = L1_BLOCK_TLP. 0x0A = L1_WAIT_LAST_TLP_ACK. 0x0B = L1_WAIT_PMDLLP_ACK. 0x0C = L1_LINK_ENTR_L1. 0x0D = L1_EXIT. 0x0F = PREP_4L1. 0x10 = L23_BLOCK_TLP. 0x11 = L23_WAIT_LAST_TLP_ACK. 0x12 = L23_WAIT_PMDLLP_ACK. 0x13 = L23_ENTR_L23. 0x14 = L23RDY. 0x15 = PREP_4L23. 0x16 = L23RDY_WAIT4ALIVE. 0x17 = L0S_BLOCK_TLP. 0x18 = WAIT_LAST_PMDLLP. 0x19 = WAIT_DSTATE_UPDATE. 0x20-0x1F = Reserved. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSPM_INT_PM_MSTATE_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSPM_INT_PM_SSTATE_E5 (0xf<<8) // Internal PM state (slave). Indicates internal state machine of power management slave controller. 0x00 = S_IDLE. 0x01 = S_RESPOND_NAK. 0x02 = S_BLOCK_TLP. 0x03 = S_WAIT_LAST_TLP_ACK. 0x04 = S_WAIT_EIDLE. 0x08 = S_LINK_ENTR_L1. 0x09 = S_L1. 0x0A = S_L1_EXIT. 0x0B = S_L23RDY. 0x0C = S_LINK_ENTR_L23. 0x0D = S_L23RDY_WAIT4ALIVE. 0x0F = S_L23RDY_WAIT4IDLE. 0x10 = S_WAIT_LAST_PMDLLP. 0x10-0x1F = Reserved. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSPM_INT_PM_SSTATE_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSPM_PME_RSND_FLAG_E5 (0x1<<12) // PME resend flag. When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms (+50%/-5%), the DUT resends the PM_PME message. This bit indicates that a PM_PME was resent. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSPM_PME_RSND_FLAG_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSPM_L1SUB_STATE_E5 (0x7<<13) // Indicates the internal L1Sub state machine state. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSPM_L1SUB_STATE_E5_SHIFT 13 + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSPM_LATCHED_NFTS_E5 (0xff<<16) // Latched N_FTS. Indicates the value of N_FTS in the received TS ordered sets from the link partner. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSPM_LATCHED_NFTS_E5_SHIFT 16 +#define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_K2 0x0003d0UL //Access:RW DataWidth:0x20 // Precision Time Measurement Requester Capability Header (VSEC). For more details, see the PTM section in the Databook. + #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_ID_K2 (0xffff<<0) // Precision Time Measurement Requester VSEC ID. For more details, see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_VER_K2 (0xf<<16) // Precision Time Measurement Requester VSEC Version. For more details, see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_VER_K2_SHIFT 16 + #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_NEXT_OFFS_K2 (0xfff<<20) // Precision Time Measurement Requester VSEC Next Pointer. For more details, see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_NEXT_OFFS_K2_SHIFT 20 +#define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL2_E5 0x0003d4UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL2_TX_ACK_SEQ_NO_E5 (0xfff<<0) // TX ACK sequence number. Indicates next transmit sequence number for transmit TLP. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL2_TX_ACK_SEQ_NO_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL2_RX_ACK_SEQ_NO_E5 (0xfff<<12) // RX ACK sequence number. Indicates the ack sequence number which is updated by receiving ACK/NAK DLLP. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL2_RX_ACK_SEQ_NO_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL2_DLCMSM_E5 (0x3<<24) // Indicates the current DLCMSM. 0x0 = DL_INACTIVE. 0x1 = DL_FC_INIT. 0x2 = Reserved. 0x3 = DL_ACTIVE. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL2_DLCMSM_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL2_FC_INIT1_E5 (0x1<<26) // Indicates the core is in FC_INIT1(VC0) state. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL2_FC_INIT1_E5_SHIFT 26 + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL2_FC_INIT2_E5 (0x1<<27) // Indicates the core is in FC_INIT2(VC0) state. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL2_FC_INIT2_E5_SHIFT 27 +#define PCIEIP_REG_PTM_REQ_HDR_OFF_K2 0x0003d4UL //Access:RW DataWidth:0x20 // Precision Time Measurement Requester Vendor Specific Header. For more details, see the PTM section in the Databook. + #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_ID_K2 (0xffff<<0) // PTM Requester VSEC ID. For more details, see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_ID_K2_SHIFT 0 + #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_REV_K2 (0xf<<16) // PTM Requester VSEC Revision. For more details, see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_REV_K2_SHIFT 16 + #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_LENGTH_K2 (0xfff<<20) // PTM Requester VSEC Length. For more details, see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_LENGTH_K2_SHIFT 20 +#define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3FC_E5 0x0003d8UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3FC_CREDIT_SEL_VC_E5 (0x7<<0) // Credit select (VC). This field in conjunction with the [CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields determines that data that is returned by the [CREDIT_DATA0] and [CREDIT_DATA1] data fields. 0x0 = VC0. 0x1 = VC1. 0x2 = VC2. ... 0x7 = VC7. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3FC_CREDIT_SEL_VC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3FC_CREDIT_SEL_CREDIT_TYPE_E5 (0x1<<3) // Credit select (credit type). This field in conjunction with the [CREDIT_SEL_VC], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields determines that data that is returned by the [CREDIT_DATA0] and [CREDIT_DATA1] data fields. 0x0 = RX. 0x1 = TX. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3FC_CREDIT_SEL_CREDIT_TYPE_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3FC_CREDIT_SEL_TLP_TYPE_E5 (0x3<<4) // Credit select (TLP Type). This field in conjunction with the [CREDIT_SEL_VC], [CREDIT_SEL_CREDIT_TYPE], and [CREDIT_SEL_HD] viewport-select fields determines that data that is returned by the [CREDIT_DATA0] and [CREDIT_DATA1] data fields. 0x0 = Posted. 0x1 = Non-posted. 0x2 = Completion. 0x3 = Reserved. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3FC_CREDIT_SEL_TLP_TYPE_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3FC_CREDIT_SEL_HD_E5 (0x1<<6) // Credit select (HeaderData). This field in conjunction with the [CREDIT_SEL_VC], [CREDIT_SEL_CREDIT_TYPE], and [CREDIT_SEL_TLP_TYPE] viewport-select fields determines that data that is returned by the [CREDIT_DATA0] and [CREDIT_DATA1] data fields. 0x0 = Header credit. 0x1 = Data credit. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3FC_CREDIT_SEL_HD_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3FC_CREDIT_DATA0_E5 (0xfff<<8) // Credit data 0. Current FC credit data selected by the [CREDIT_SEL_VC], [CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields. RX = Credit received value. TX = Credit consumed value. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3FC_CREDIT_DATA0_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3FC_CREDIT_DATA1_E5 (0xfff<<20) // Credit data 1. Current FC credit data selected by the [CREDIT_SEL_VC], [CREDIT_SEL_CREDIT_TYPE], [CREDIT_SEL_TLP_TYPE], and [CREDIT_SEL_HD] viewport-select fields. RX = Credit allocated value. TX = Credit limit value. This value is valid when DLCMSM=0x3(DL_ACTIVE). + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3FC_CREDIT_DATA1_E5_SHIFT 20 +#define PCIEIP_REG_PTM_REQ_CONTROL_OFF_K2 0x0003d8UL //Access:RW DataWidth:0x20 // PTM Requester Vendor Specific Control Register. For more details, see the PTM section in the Databook. + #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_AUTO_UPDATE_ENABLED_K2 (0x1<<0) // PTM Requester Auto Update Enabled - When enabled PTM Requester will automatically atempt to update it's context every 10ms. For more details, see the PTM section in the Databook. Note: This register field is sticky. + #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_AUTO_UPDATE_ENABLED_K2_SHIFT 0 + #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_START_UPDATE_K2 (0x1<<1) // PTM Requester Start Update - When set the PTM Requester will attempt a PTM Dialogue to update it's context; This bit is self clearing. For more details, see the PTM section in the Databook. + #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_START_UPDATE_K2_SHIFT 1 + #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_FAST_TIMERS_K2 (0x1<<2) // PTM Fast Timers - Debug mode for PTM Timers. The 100us timer output will go high at 30us and the 10ms timer output will go high at 100us (The Long Timer Value is ignored). There is no change to the 1us timer. The requester operation will otherwise remain the same. For more details, see the PTM section in the Databook. Note: This register field is sticky. + #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_FAST_TIMERS_K2_SHIFT 2 + #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_LONG_TIMER_K2 (0xff<<8) // PTM Requester Long Timer - Determines the period between each auto update PTM Dialogue in miliseconds. Update period is the register value +1 milisecond. For the Switch product this value must not be set larger than 0x9 for spec compliance. For more details, see the PTM section in the Databook. Note: This register field is sticky. + #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_LONG_TIMER_K2_SHIFT 8 +#define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3_E5 0x0003dcUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3_MFTLP_PTR_E5 (0x7f<<0) // First malformed TLP error pointer. Indicates the element of the received first malformed TLP. This pointer is validated by [MFTLP_STATUS]. 0x01 = AtomicOp address alignment. 0x02 = AtomicOp operand. 0x03 = AtomicOp byte enable. 0x04 = TLP length miss match. 0x05 = Max payload size. 0x06 = Message TLP without TC0. 0x07 = Invalid TC. 0x08 = Unexpected route bit in message TLP. 0x09 = Unexpected CRS status in completion TLP. 0x0A = Byte enable. 0x0B = Memory address 4KB boundary. 0x0C = TLP prefix rules. 0x0D = Translation request rules. 0x0E = Invalid TLP type. 0x0F = Completion rules. 0x10-0x7E = Reserved. 0x7F = Application. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3_MFTLP_PTR_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3_MFTLP_STATUS_E5 (0x1<<7) // Malformed TLP status. Indicates malformed TLP has occurred. + #define PCIEIP_REG_PCIEEP_RAS_SD_STATUSL3_MFTLP_STATUS_E5_SHIFT 7 +#define PCIEIP_REG_PTM_REQ_STATUS_OFF_K2 0x0003dcUL //Access:R DataWidth:0x20 // PTM Requester Vendor Specific Status Register. For more details, see the PTM section in the Databook. + #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_CONTEXT_VALID_K2 (0x1<<0) // PTM Requester Context Valid - Indicate that the Timing Context is valid. For more details, see the PTM section in the Databook. + #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_CONTEXT_VALID_K2_SHIFT 0 + #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_MANUAL_UPDATE_ALLOWED_K2 (0x1<<1) // PTM Requester Manual Update Allowed - Indicates whether or not a Manual Update can be signalled. For more details, see the PTM section in the Databook. + #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_MANUAL_UPDATE_ALLOWED_K2_SHIFT 1 +#define PCIEIP_REG_PTM_REQ_LOCAL_LSB_OFF_K2 0x0003e0UL //Access:RW DataWidth:0x20 // PTM Requester Local Clock LSB For more details, see the PTM section in the Databook. +#define PCIEIP_REG_PTM_REQ_LOCAL_MSB_OFF_K2 0x0003e4UL //Access:RW DataWidth:0x20 // PTM Requester Local Clock MSB. For more details, see the PTM section in the Databook. +#define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL1_E5 0x0003e8UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL1_EQ_LANE_SEL_E5 (0xf<<0) // EQ status lane select. Setting this field in conjunction with [EQ_RATE_SEL] determines the per-lane silicon debug EQ status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. 0x0 = Lane0. 0x1 = Lane1. 0x2 = Lane2. _ ... 0x7 = Lane7. 0x8-0xF = Reserved. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL1_EQ_LANE_SEL_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL1_EQ_RATE_SEL_E5 (0x1<<4) // EQ status rate select. Setting this field in conjunction with [EQ_LANE_SEL] determines the per-lane silicon debug EQ status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. 0x0 = 8.0 GT/s speed. 0x1 = 16.0 GT/s speed. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL1_EQ_RATE_SEL_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL1_EXT_EQ_TIMEOUT_E5 (0x3<<8) // Extends EQ Phase2/3 timeout. This field is used when the ltssm is in Recovery.EQ2/3. When this field is set, the value of the EQ2/3 timeout is extended. EQ master (DSP in EQ Phase 3/USP in EQ Phaase2) 0x0 = 24 ms (default). 0x1 = 48 ms 0x2 = 240 ms. 0x3 = No timeout. EQ slave (DSP in EQ Phase 2/USP in EQ Phaase3) 0x0 = 32 ms (default). 0x1 = 56 ms 0x2 = 248 ms. 0x3 = No timeout. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL1_EXT_EQ_TIMEOUT_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL1_EVAL_INTERVAL_TIME_E5 (0x3<<16) // Eval interval time. Indicates interval time of RxEqEval assertion. 0x0 = 500 ns. 0x1 = 1 us. 0x2 = 2 us. 0x3 = 4 us. This field is used for EQ master (DSP in EQ Phase3/USP in EQ Phase2). + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL1_EVAL_INTERVAL_TIME_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL1_FOM_TARGET_EN_E5 (0x1<<23) // FOM target enable. Enables the [FOM_TARGET] field. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL1_FOM_TARGET_EN_E5_SHIFT 23 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL1_FOM_TARGET_E5 (0xff<<24) // FOM target. Indicates figure of merit target criteria value of EQ master (DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when PCIEEP_GEN3_EQ_CTL[FM] is 0x1 (figure of merit). + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL1_FOM_TARGET_E5_SHIFT 24 +#define PCIEIP_REG_PTM_REQ_T1_LSB_OFF_K2 0x0003e8UL //Access:R DataWidth:0x20 // PTM Requester T1 Timestamp LSB. For more details, see the PTM section in the Databook. +#define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_E5 0x0003ecUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_TXPRE_CUR_E5 (0x3f<<0) // Force local transmitter precursor. Indicates the coefficient value of EQ slave (DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_TXPRE_CUR_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_TX_CUR_E5 (0x3f<<6) // Force local transmitter cursor. Indicates the coefficient value of EQ slave (DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_TX_CUR_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_TXPOST_CUR_E5 (0x3f<<12) // Force local transmitter postcursor. Indicates the coefficient value of EQ slave (DSP in EQ Phase2/USP in EQ Phase3), instead of the value instructed from link partner. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_TXPOST_CUR_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_RXHINT_E5 (0x7<<18) // Force local receiver preset hint. Indicates the RxPresetHint value of EQ slave (DSP in EQ Phase2/USP in EQ Phase3), instead of received or set value. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_RXHINT_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_TXPRE_E5 (0xf<<24) // Force local transmitter preset. Indicates initial preset value of USP in EQ slave (EQ Phase2) instead of receiving EQ TS2. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_TXPRE_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_TXCOEF_EN_E5 (0x1<<28) // Force local transmitter coefficient enable. Enables the following fields: [FORCE_LOC_TXPRE_CUR], [FORCE_LOC_TX_CUR], [FORCE_LOC_TXPOST_CUR]. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_TXCOEF_EN_E5_SHIFT 28 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_RXHINT_EN_E5 (0x1<<29) // Force local receiver preset hint enable. Enables [FORCE_LOC_RXHINT]. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_RXHINT_EN_E5_SHIFT 29 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_TXPRE_EN_E5 (0x1<<30) // Force local transmitter preset enable. Enables [FORCE_LOC_TXPRE]. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL2_FORCE_LOC_TXPRE_EN_E5_SHIFT 30 +#define PCIEIP_REG_PTM_REQ_T1_MSB_OFF_K2 0x0003ecUL //Access:R DataWidth:0x20 // PTM Requester T1 Timestamp MSB. For more details, see the PTM section in the Databook. +#define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL3_E5 0x0003f0UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL3_FORCE_REM_TXPRE_CUR_E5 (0x3f<<0) // Force remote transmitter pre-cursor as selected by PCIEEP_RAS_SD_EQ_CTL1[EQ_LANE_SEL]. Indicates the coefficient value of EQ master (DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from link partner. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL3_FORCE_REM_TXPRE_CUR_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL3_FORCE_REM_TX_CUR_E5 (0x3f<<6) // Force remote transmitter cursor as selected by PCIEEP_RAS_SD_EQ_CTL1[EQ_LANE_SEL]. Indicates the coefficient value of EQ master (DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from link partner. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL3_FORCE_REM_TX_CUR_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL3_FORCE_REM_TXPOST_CUR_E5 (0x3f<<12) // Force remote transmitter postcursor as selected by PCIEEP_RAS_SD_EQ_CTL1[EQ_LANE_SEL]. Indicates the coefficient value of EQ master (DSP in EQ Phase3/USP in EQ Phase2), instead of the value instructed from link partner. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL3_FORCE_REM_TXPOST_CUR_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL3_FORCE_REM_TXCOEF_EN_E5 (0x1<<28) // Force remote transmitter coefficient enable as selected by PCIEEP_RAS_SD_EQ_CTL1[EQ_LANE_SEL]. Enables the following fields: [FORCE_REM_TXPRE_CUR], [FORCE_REM_TX_CUR], [FORCE_REM_TXPOST_CUR]. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_CTL3_FORCE_REM_TXCOEF_EN_E5_SHIFT 28 +#define PCIEIP_REG_PTM_REQ_T1P_LSB_OFF_K2 0x0003f0UL //Access:R DataWidth:0x20 // PTM Requester T1 Previous Timestamp LSB. For more details, see the PTM section in the Databook. +#define PCIEIP_REG_PTM_REQ_T1P_MSB_OFF_K2 0x0003f4UL //Access:R DataWidth:0x20 // PTM Requester T1 Previous Timestamp MSB. For more details, see the PTM section in the Databook. +#define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_E5 0x0003f8UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_EQ_SEQUENCE_E5 (0x1<<0) // EQ sequence. Indicates that the core is starting the equalization sequence. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_EQ_SEQUENCE_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_EQ_CONV_INFO_E5 (0x3<<1) // EQ convergence info. Indicates equalization convergence information. 0x0 = Equalization is not attempted. 0x1 = Equalization finished successfully. 0x2 = Equalization finished unsuccessfully. 0x3 = Reserved. This bit is automatically cleared when the core starts EQ master phase again. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_EQ_CONV_INFO_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_EQ_RULEA_VIOL_E5 (0x1<<4) // EQ rule A violation. Indicates that coefficient rule A violation is detected in the values provided by PHY using direction change method during EQ master phase (DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to the rules a) from section "Rules for Transmitter Coefficients" in the PCI Express Base Specification. This bit is automatically cleared when the controller starts EQ master phase again. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_EQ_RULEA_VIOL_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_EQ_RULEB_VIOL_E5 (0x1<<5) // EQ rule B violation. Indicates that coefficient rule B violation is detected in the values provided by PHY using direction change method during EQ master phase (DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to the rules b) from section "Rules for Transmitter Coefficients" in the PCI Express Base Specification. This bit is automatically cleared when the controller starts EQ master phase again. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_EQ_RULEB_VIOL_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_EQ_RULEC_VIOL_E5 (0x1<<6) // EQ rule C violation. Indicates that coefficient rule C violation is detected in the values provided by PHY using direction change method during EQ master phase (DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to the rules c) from section "Rules for Transmitter Coefficients" in the PCI Express Base Specification. This bit is automatically cleared when the controller starts EQ master phase again. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_EQ_RULEC_VIOL_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_EQ_REJECT_EVENT_E5 (0x1<<7) // EQ reject event. Indicates that the core receives two consecutive TS1 OS w/Reject=1b during EQ master phase (DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the core starts EQ master phase again. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT1_EQ_REJECT_EVENT_E5_SHIFT 7 +#define PCIEIP_REG_PTM_REQ_T4_LSB_OFF_K2 0x0003f8UL //Access:R DataWidth:0x20 // PTM Requester T4 Timestamp LSB. For more details, see the PTM section in the Databook. +#define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT2_E5 0x0003fcUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT2_EQ_LOC_PRE_CUR_E5 (0x3f<<0) // EQ local precursor. Indicates local precursor coefficient value. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT2_EQ_LOC_PRE_CUR_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT2_EQ_LOC_CUR_E5 (0x3f<<6) // EQ local cursor. Indicates local cursor coefficient value. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT2_EQ_LOC_CUR_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT2_EQ_LOC_POST_CUR_E5 (0x3f<<12) // EQ local postcursor. Indicates local post cursor coefficient value. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT2_EQ_LOC_POST_CUR_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT2_EQ_LOC_RXHINT_E5 (0x7<<18) // EQ local receiver preset hint. Indicates local receiver preset hint value. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT2_EQ_LOC_RXHINT_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT2_EQ_LOC_FOM_VAL_E5 (0xff<<24) // EQ local figure of merit. Indicates local maximum figure of merit value. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT2_EQ_LOC_FOM_VAL_E5_SHIFT 24 +#define PCIEIP_REG_PTM_REQ_T4_MSB_OFF_K2 0x0003fcUL //Access:R DataWidth:0x20 // PTM Requester T4 Timestamp MSB. For more details, see the PTM section in the Databook. +#define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT3_E5 0x000400UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT3_EQ_REM_PRE_CUR_E5 (0x3f<<0) // EQ remote precursor. Indicates remote postcursor coefficient value. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT3_EQ_REM_PRE_CUR_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT3_EQ_REM_CUR_E5 (0x3f<<6) // EQ remote cursor. Indicates remote cursor coefficient value. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT3_EQ_REM_CUR_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT3_EQ_REM_POST_CUR_E5 (0x3f<<12) // EQ remote postcursor. Indicates remote postcursor coefficient value. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT3_EQ_REM_POST_CUR_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT3_EQ_REM_LF_E5 (0x3f<<18) // EQ remote LF. Indicates remote LF value. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT3_EQ_REM_LF_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT3_EQ_REM_FS_E5 (0x3f<<24) // EQ remote FS. Indicates remote FS value. + #define PCIEIP_REG_PCIEEP_RAS_SD_EQ_STAT3_EQ_REM_FS_E5_SHIFT 24 +#define PCIEIP_REG_PTM_REQ_T4P_LSB_OFF_K2 0x000400UL //Access:R DataWidth:0x20 // PTM Requester T4 Previous Timestamp LSB. For more details, see the PTM section in the Databook. +#define PCIEIP_REG_PTM_REQ_T4P_MSB_OFF_K2 0x000404UL //Access:R DataWidth:0x20 // PTM Requester T4 Previous Timestamp MSB. For more details, see the PTM section in the Databook. +#define PCIEIP_REG_PTM_REQ_MASTER_LSB_OFF_K2 0x000408UL //Access:R DataWidth:0x20 // PTM Requester Master Time LSB. For more details, see the PTM section in the Databook. #define PCIEIP_REG_CONFIG_2_BB 0x000408UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_CONFIG_2_BAR1_SIZE_BB (0xf<<0) // These bits control the size of the BAR1 area advertised in the bar_1 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. Default is 64K #define PCIEIP_REG_CONFIG_2_BAR1_SIZE_BB_SHIFT 0 @@ -2708,7 +4396,7 @@ #define PCIEIP_REG_CONFIG_2_BAR_PREFETCH_BB_SHIFT 16 #define PCIEIP_REG_CONFIG_2_RESERVED0_BB (0x7fff<<17) // #define PCIEIP_REG_CONFIG_2_RESERVED0_BB_SHIFT 17 -#define PCIEIP_REG_PTM_REQ_MASTER_MSB_OFF_K2_E5 0x00040cUL //Access:R DataWidth:0x20 // PTM Requester Master Time MSB. For more details, see the PTM section in the Databook. +#define PCIEIP_REG_PTM_REQ_MASTER_MSB_OFF_K2 0x00040cUL //Access:R DataWidth:0x20 // PTM Requester Master Time MSB. For more details, see the PTM section in the Databook. #define PCIEIP_REG_CONFIG_3_BB 0x00040cUL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_CONFIG_3_STICKY_BYTE_BB (0xff<<0) // This value is reset only reset by HARD Reset such that it can be used to detect initial power up if a non-zero value is written by the firmware after initialization. It has not hardware function other than reset type detection. This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_CONFIG_3_STICKY_BYTE_BB_SHIFT 0 @@ -2732,7 +4420,7 @@ #define PCIEIP_REG_CONFIG_3_VAUX_PRESENT_BB_SHIFT 30 #define PCIEIP_REG_CONFIG_3_PCI_POWER_BB (0x1<<31) // PCI_POWER This bit indicates the current state of power on the PCI bus. If this bit is '1', it indicates that the PCI padring has power. If this bit is '0', it indicates that the PCI padring does not have power (D3 Cold). #define PCIEIP_REG_CONFIG_3_PCI_POWER_BB_SHIFT 31 -#define PCIEIP_REG_PTM_REQ_PROP_DELAY_OFF_K2_E5 0x000410UL //Access:R DataWidth:0x20 // PTM Requester Propagation Delay. For more details, see the PTM section in the Databook. +#define PCIEIP_REG_PTM_REQ_PROP_DELAY_OFF_K2 0x000410UL //Access:R DataWidth:0x20 // PTM Requester Propagation Delay. For more details, see the PTM section in the Databook. #define PCIEIP_REG_PM_DATA_A_BB 0x000410UL //Access:RW DataWidth:0x20 // This register controls the first 4 power management PM_Data read values #define PCIEIP_REG_PM_DATA_A_PM_DATA_0_PRG_BB (0xff<<0) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 0. This is the power consumed in D0 state. This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_PM_DATA_A_PM_DATA_0_PRG_BB_SHIFT 0 @@ -2742,7 +4430,7 @@ #define PCIEIP_REG_PM_DATA_A_PM_DATA_2_PRG_BB_SHIFT 16 #define PCIEIP_REG_PM_DATA_A_PM_DATA_3_PRG_BB (0xff<<24) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 3. This is the power consumed in D3 state. This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_PM_DATA_A_PM_DATA_3_PRG_BB_SHIFT 24 -#define PCIEIP_REG_PTM_REQ_MASTERT1_LSB_OFF_K2_E5 0x000414UL //Access:R DataWidth:0x20 // PTM Requester Master Time at T1 LSB. For more details, see the PTM section in the Databook. +#define PCIEIP_REG_PTM_REQ_MASTERT1_LSB_OFF_K2 0x000414UL //Access:R DataWidth:0x20 // PTM Requester Master Time at T1 LSB. For more details, see the PTM section in the Databook. #define PCIEIP_REG_PM_DATA_B_BB 0x000414UL //Access:RW DataWidth:0x20 // This register controls the second 4 power management PM_Data read values #define PCIEIP_REG_PM_DATA_B_PM_DATA_4_PRG_BB (0xff<<0) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 4. This is the power dissipated in D0 state. This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_PM_DATA_B_PM_DATA_4_PRG_BB_SHIFT 0 @@ -2752,7 +4440,14 @@ #define PCIEIP_REG_PM_DATA_B_PM_DATA_6_PRG_BB_SHIFT 16 #define PCIEIP_REG_PM_DATA_B_PM_DATA_7_PRG_BB (0xff<<24) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 7. This is the power dissipated in D3 state. This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_PM_DATA_B_PM_DATA_7_PRG_BB_SHIFT 24 -#define PCIEIP_REG_PTM_REQ_MASTERT1_MSB_OFF_K2_E5 0x000418UL //Access:R DataWidth:0x20 // PTM Requester Master Time at T1 MSB. For more details, see the PTM section in the Databook. +#define PCIEIP_REG_PCIEEP_RASDP_CAP_HDR_E5 0x000418UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RASDP_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_RASDP_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RASDP_CAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_RASDP_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_RASDP_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_RASDP_CAP_HDR_NCO_E5_SHIFT 20 +#define PCIEIP_REG_PTM_REQ_MASTERT1_MSB_OFF_K2 0x000418UL //Access:R DataWidth:0x20 // PTM Requester Master Time at T1 MSB. For more details, see the PTM section in the Databook. #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BB 0x000418UL //Access:RW DataWidth:0x20 // This register controls the higher bar size advertizements, when a bar size greater than 1G is desired. #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR1_SIZE_HIEXT_BB (0xf<<0) // These bits control the size of the BAR1 area advertised in the bar_1 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits are programmed when a BAR size greater than 1GB is desired. When requiring a BAR size greater than 1 GB, the corresponding bar1_size bits should be programmed to 0xF. #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR1_SIZE_HIEXT_BB_SHIFT 0 @@ -2768,70 +4463,131 @@ #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR2_SIZE_LOEXT_BB_SHIFT 16 #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR3_SIZE_LOEXT_BB (0x7<<19) // These bits control the size of the BAR3 area advertised in the bar_5 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits are programmed when a BAR size lower than 64K is desired. When requiring a BAR size smaller than 64K , the corresponding bar3_size bits should be programmed to 0x0, as also the bar1_size_hiext bits. If desiring a bar size greater than 32K, then the bar1_size_loext bits need to be 0. #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR3_SIZE_LOEXT_BB_SHIFT 19 -#define PCIEIP_REG_PTM_REQ_TX_LATENCY_OFF_K2_E5 0x00041cUL //Access:RW DataWidth:0x20 // PTM Requester TX Latency. For more details, see the PTM section in the Databook. - #define PCIEIP_REG_PTM_REQ_TX_LATENCY_OFF_PTM_REQ_TX_LATENCY_K2_E5 (0xfff<<0) // PTM Requester TX Latency - Requester Transmit path latency (12 bit wide). For more details, see the PTM section in the Databook. Note: This register field is sticky. - #define PCIEIP_REG_PTM_REQ_TX_LATENCY_OFF_PTM_REQ_TX_LATENCY_K2_E5_SHIFT 0 -#define PCIEIP_REG_PTM_REQ_RX_LATENCY_OFF_K2_E5 0x000420UL //Access:RW DataWidth:0x20 // PTM Requester RX Latency. For more details, see the PTM section in the Databook. - #define PCIEIP_REG_PTM_REQ_RX_LATENCY_OFF_PTM_REQ_RX_LATENCY_K2_E5 (0xfff<<0) // PTM Requester RX Latency - Requester Receive path latency (12 bit wide). For more details, see the PTM section in the Databook. Note: This register field is sticky. - #define PCIEIP_REG_PTM_REQ_RX_LATENCY_OFF_PTM_REQ_RX_LATENCY_K2_E5_SHIFT 0 -#define PCIEIP_REG_RESBAR_CAP_HDR_REG_K2_E5 0x000424UL //Access:RW DataWidth:0x20 // Resizable BAR Capability Header. - #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_K2_E5 (0xffff<<0) // Resizable BAR Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_K2_E5 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_K2_E5_SHIFT 16 - #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_K2_E5 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_K2_E5_SHIFT 20 -#define PCIEIP_REG_RESBAR_CAP_REG_0_REG_K2_E5 0x000428UL //Access:RW DataWidth:0x20 // Resizable BAR0 Capability Register. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_K2_E5 (0x1<<4) // Up to 1MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_K2_E5_SHIFT 4 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_K2_E5 (0x1<<5) // Up to 2MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_K2_E5_SHIFT 5 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_K2_E5 (0x1<<6) // Up to 4MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_K2_E5_SHIFT 6 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_K2_E5 (0x1<<7) // Up to 8MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_K2_E5_SHIFT 7 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_K2_E5 (0x1<<8) // Up to 16MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_K2_E5_SHIFT 8 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_K2_E5 (0x1<<9) // Up to 32MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_K2_E5_SHIFT 9 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_K2_E5 (0x1<<10) // Up to 64MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_K2_E5_SHIFT 10 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_K2_E5 (0x1<<11) // Up to 128MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_K2_E5_SHIFT 11 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_K2_E5 (0x1<<12) // Up to 256MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_K2_E5_SHIFT 12 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_K2_E5 (0x1<<13) // Up to 512MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_K2_E5_SHIFT 13 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_K2_E5 (0x1<<14) // Up to 1GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_K2_E5_SHIFT 14 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_K2_E5 (0x1<<15) // Up to 2GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_K2_E5_SHIFT 15 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_K2_E5 (0x1<<16) // Up to 4GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_K2_E5_SHIFT 16 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_K2_E5 (0x1<<17) // Up to 8GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_K2_E5_SHIFT 17 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_K2_E5 (0x1<<18) // Up to 16GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_K2_E5_SHIFT 18 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_K2_E5 (0x1<<19) // Up to 32GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_K2_E5_SHIFT 19 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_K2_E5 (0x1<<20) // Up to 64GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_K2_E5_SHIFT 20 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_K2_E5 (0x1<<21) // Up to 128GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_K2_E5_SHIFT 21 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_K2_E5 (0x1<<22) // Up to 256GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_K2_E5_SHIFT 22 - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_K2_E5 (0x1<<23) // Up to 512GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_K2_E5_SHIFT 23 +#define PCIEIP_REG_PCIEEP_RASDP_HDR_E5 0x00041cUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RASDP_HDR_VSEC_ID_E5 (0xffff<<0) // VSEC ID. + #define PCIEIP_REG_PCIEEP_RASDP_HDR_VSEC_ID_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RASDP_HDR_VSEC_REV_E5 (0xf<<16) // Capability version. + #define PCIEIP_REG_PCIEEP_RASDP_HDR_VSEC_REV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_RASDP_HDR_VSEC_LENGTH_E5 (0xfff<<20) // VSEC length. + #define PCIEIP_REG_PCIEEP_RASDP_HDR_VSEC_LENGTH_E5_SHIFT 20 +#define PCIEIP_REG_PTM_REQ_TX_LATENCY_OFF_K2 0x00041cUL //Access:RW DataWidth:0x20 // PTM Requester TX Latency. For more details, see the PTM section in the Databook. + #define PCIEIP_REG_PTM_REQ_TX_LATENCY_OFF_PTM_REQ_TX_LATENCY_K2 (0xfff<<0) // PTM Requester TX Latency - Requester Transmit path latency (12 bit wide). For more details, see the PTM section in the Databook. Note: This register field is sticky. + #define PCIEIP_REG_PTM_REQ_TX_LATENCY_OFF_PTM_REQ_TX_LATENCY_K2_SHIFT 0 +#define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_E5 0x000420UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_TX_E5 (0x1<<0) // Global error correction disable for all TX layers. + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_TX_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_AXIB_MASC_E5 (0x1<<1) // Error correction disable for AXI bridge master completion buffer (not supported). + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_AXIB_MASC_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_AXIB_OUTB_E5 (0x1<<2) // Error correction disable for AXI bridge outbound request path (not supported). + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_AXIB_OUTB_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_DMA_WR_E5 (0x1<<3) // Error correction disable for DMA write (not supported). + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_DMA_WR_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_L2_TX_E5 (0x1<<4) // Error correction disable for layer 2 TX path. + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_L2_TX_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_L3_TX_E5 (0x1<<5) // Error correction disable for layer 3 TX path. + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_L3_TX_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_ADM_TX_E5 (0x1<<6) // Error correction disable for ADM TX path. + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_ADM_TX_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_RX_E5 (0x1<<16) // Global error correction disable for all RX layers. + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_RX_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_AXIB_INBC_E5 (0x1<<17) // Error correction disable for AXI bridge inbound completion composer (not supported). + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_AXIB_INBC_E5_SHIFT 17 + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_AXIB_INBR_E5 (0x1<<18) // Error correction disable for AXI bridge inbound request path (not supported). + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_AXIB_INBR_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_DMA_RD_E5 (0x1<<19) // Error correction disable for DMA read (not supported). + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_DMA_RD_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_L2_RX_E5 (0x1<<20) // Error correction disable for layer 2 RX path. + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_L2_RX_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_L3_RX_E5 (0x1<<21) // Error correction disable for layer 3 RX path. + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_L3_RX_E5_SHIFT 21 + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_ADM_RX_E5 (0x1<<22) // Error correction disable for ADM RX path. + #define PCIEIP_REG_PCIEEP_RASDP_EP_CTL_EP_DIS_ADM_RX_E5_SHIFT 22 +#define PCIEIP_REG_PTM_REQ_RX_LATENCY_OFF_K2 0x000420UL //Access:RW DataWidth:0x20 // PTM Requester RX Latency. For more details, see the PTM section in the Databook. + #define PCIEIP_REG_PTM_REQ_RX_LATENCY_OFF_PTM_REQ_RX_LATENCY_K2 (0xfff<<0) // PTM Requester RX Latency - Requester Receive path latency (12 bit wide). For more details, see the PTM section in the Databook. Note: This register field is sticky. + #define PCIEIP_REG_PTM_REQ_RX_LATENCY_OFF_PTM_REQ_RX_LATENCY_K2_SHIFT 0 +#define PCIEIP_REG_PCIEEP_RASDP_CE_CTL_E5 0x000424UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RASDP_CE_CTL_EP_DIS_L3_RX_E5 (0x1<<0) // Clears all correctable error counters. + #define PCIEIP_REG_PCIEEP_RASDP_CE_CTL_EP_DIS_L3_RX_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RASDP_CE_CTL_CORR_EN_CNTRS_E5 (0x1<<4) // Error correction disable for ADM RX path. + #define PCIEIP_REG_PCIEEP_RASDP_CE_CTL_CORR_EN_CNTRS_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_RASDP_CE_CTL_CORR_CNT_SEL_REG_E5 (0xf<<20) // Selected correctable counter region. 0x0 = ADM RX path. 0x1 = Layer 3 RX path. 0x2 = Layer 2 RX path. 0x3 = DMA read engine inbound (not supported). 0x4 = AXI bridge inbound request path (not supported). 0x5 = AXI bridge inbound completion composer (not supported). 0x6 = ADM TX path. 0x7 = Layer 3 TX path. 0x8 = Layer 2 TX path. 0x9 = DMA outbound path (not supported). 0xA = AXI bridge outbound request path (not supported). 0xB = AXI bridge outbound master completion buffer path (not supported). 0xC - 0xF = Reserved. + #define PCIEIP_REG_PCIEEP_RASDP_CE_CTL_CORR_CNT_SEL_REG_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_RASDP_CE_CTL_CORR_CNT_SEL_E5 (0xff<<24) // Counter selection. This field selects the counter ID (within the region defined by [CORR_CNT_SEL_REG]) whose contents can be read from PCIEEP_RAS_TBA_CTL. You can cycle this field value from 0 to 255 to access all counters. + #define PCIEIP_REG_PCIEEP_RASDP_CE_CTL_CORR_CNT_SEL_E5_SHIFT 24 +#define PCIEIP_REG_RESBAR_CAP_HDR_REG_K2 0x000424UL //Access:RW DataWidth:0x20 // Resizable BAR Capability Header. + #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_K2 (0xffff<<0) // Resizable BAR Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_K2_SHIFT 0 + #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_K2 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_K2_SHIFT 16 + #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_K2 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_K2_SHIFT 20 +#define PCIEIP_REG_PCIEEP_RASDP_CE_RP_E5 0x000428UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RASDP_CE_RP_CORR_COUNT_E5 (0xff<<0) // Current corrected count for the selected counter. + #define PCIEIP_REG_PCIEEP_RASDP_CE_RP_CORR_COUNT_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RASDP_CE_RP_CORR_CNT_SEL_REG_E5 (0xf<<20) // Selected correctable counter region. 0x0 = ADM RX path. 0x1 = Layer 3 RX path. 0x2 = Layer 2 RX path. 0x3 = DMA inbound path (not supported). 0x4 = AXI bridge inbound request path (not supported). 0x5 = AXI bridge inbound completion composer path (not supported). 0x6 = ADM TX path. 0x7 = Layer 3 TX path. 0x8 = Layer 2 TX path. 0x9 = DMA outbound path (not supported). 0xA = AXI bridge outbound request path (not supported). 0xB = AXI bridge outbound master completion (not supported). 0xC - 0xF = Reserved. + #define PCIEIP_REG_PCIEEP_RASDP_CE_RP_CORR_CNT_SEL_REG_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_RASDP_CE_RP_CORR_CNT_SEL_E5 (0xff<<24) // Counter selection. Returns the value set in PCIEEP_RASDP_CE_CTL[CORR_CNT_SEL]. + #define PCIEIP_REG_PCIEEP_RASDP_CE_RP_CORR_CNT_SEL_E5_SHIFT 24 +#define PCIEIP_REG_RESBAR_CAP_REG_0_REG_K2 0x000428UL //Access:RW DataWidth:0x20 // Resizable BAR0 Capability Register. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_K2 (0x1<<4) // Up to 1MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_K2_SHIFT 4 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_K2 (0x1<<5) // Up to 2MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_K2_SHIFT 5 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_K2 (0x1<<6) // Up to 4MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_K2_SHIFT 6 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_K2 (0x1<<7) // Up to 8MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_K2_SHIFT 7 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_K2 (0x1<<8) // Up to 16MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_K2_SHIFT 8 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_K2 (0x1<<9) // Up to 32MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_K2_SHIFT 9 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_K2 (0x1<<10) // Up to 64MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_K2_SHIFT 10 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_K2 (0x1<<11) // Up to 128MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_K2_SHIFT 11 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_K2 (0x1<<12) // Up to 256MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_K2_SHIFT 12 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_K2 (0x1<<13) // Up to 512MB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_K2_SHIFT 13 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_K2 (0x1<<14) // Up to 1GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_K2_SHIFT 14 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_K2 (0x1<<15) // Up to 2GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_K2_SHIFT 15 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_K2 (0x1<<16) // Up to 4GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_K2_SHIFT 16 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_K2 (0x1<<17) // Up to 8GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_K2_SHIFT 17 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_K2 (0x1<<18) // Up to 16GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_K2_SHIFT 18 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_K2 (0x1<<19) // Up to 32GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_K2_SHIFT 19 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_K2 (0x1<<20) // Up to 64GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_K2_SHIFT 20 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_K2 (0x1<<21) // Up to 128GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_K2_SHIFT 21 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_K2 (0x1<<22) // Up to 256GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_K2_SHIFT 22 + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_K2 (0x1<<23) // Up to 512GB BAR Supported. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_K2_SHIFT 23 #define PCIEIP_REG_REG_VPD_INTF_BB 0x000428UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_REG_VPD_INTF_INTF_REQ_BB (0x1<<0) // This bit will be set if there is a pending request for action by the firmware to handle a Vital Product Data interface. This bit is set when the vpd_flag_addr register in configuation space is written. This bit is cleared when the vpd_data register below is written. #define PCIEIP_REG_REG_VPD_INTF_INTF_REQ_BB_SHIFT 0 -#define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_K2_E5 0x00042cUL //Access:RW DataWidth:0x20 // Resizable BAR0 Control Register. - #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_K2_E5 (0x7<<0) // BAR Index. Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_K2_E5_SHIFT 0 - #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_K2_E5 (0x7<<5) // Number of Resizeable BARs. Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_K2_E5_SHIFT 5 - #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_K2_E5 (0x1f<<8) // BAR Size. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_K2_E5_SHIFT 8 +#define PCIEIP_REG_PCIEEP_RASDP_UCE_CTL_E5 0x00042cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RASDP_UCE_CTL_EP_DIS_L3_RX_E5 (0x1<<0) // Clears all uncorrectable error counters. + #define PCIEIP_REG_PCIEEP_RASDP_UCE_CTL_EP_DIS_L3_RX_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RASDP_UCE_CTL_UCORR_EN_CNTRS_E5 (0x1<<4) // Error correction disable for ADM RX path. + #define PCIEIP_REG_PCIEEP_RASDP_UCE_CTL_UCORR_EN_CNTRS_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_RASDP_UCE_CTL_UCORR_CNT_SEL_REG_E5 (0xf<<20) // Selected correctable counter region. 0x0 = ADM RX path. 0x1 = Layer 3 RX path. 0x2 = Layer 2 RX path. 0x3 = DMA inbound path (not supported). 0x4 = AXI bridge inbound request path (not supported). 0x5 = AXI bridge inbound completion composer path (not supported). 0x6 = ADM TX path. 0x7 = Layer 3 TX path. 0x8 = Layer 2 TX path. 0x9 = DMA outbound path (not supported). 0xA = AXI bridge outbound request path (not supported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved. + #define PCIEIP_REG_PCIEEP_RASDP_UCE_CTL_UCORR_CNT_SEL_REG_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_RASDP_UCE_CTL_UCORR_CNT_SEL_E5 (0xff<<24) // Counter selection. This field selects the counter ID (within the region defined by [UCORR_CNT_SEL_REG]) whose contents can be read from PCIEEP_RAS_TBA_CTL. You can cycle this field value from 0 to 255 to access all counters. + #define PCIEIP_REG_PCIEEP_RASDP_UCE_CTL_UCORR_CNT_SEL_E5_SHIFT 24 +#define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_K2 0x00042cUL //Access:RW DataWidth:0x20 // Resizable BAR0 Control Register. + #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_K2 (0x7<<0) // BAR Index. Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_K2_SHIFT 0 + #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_K2 (0x7<<5) // Number of Resizeable BARs. Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_K2_SHIFT 5 + #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_K2 (0x1f<<8) // BAR Size. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_K2_SHIFT 8 #define PCIEIP_REG_REG_VPD_ADDR_FLAG_BB 0x00042cUL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_REG_VPD_ADDR_FLAG_UNUSED0_BB (0x3ffff<<0) // #define PCIEIP_REG_REG_VPD_ADDR_FLAG_UNUSED0_BB_SHIFT 0 @@ -2839,22 +4595,61 @@ #define PCIEIP_REG_REG_VPD_ADDR_FLAG_ADDRESS_BB_SHIFT 18 #define PCIEIP_REG_REG_VPD_ADDR_FLAG_WR_BB (0x1<<31) // This bit indicates if the host is requesting a read or a write cycle. If this bit is set, then the host has requested the data in the vpd_data register to be passed to the NVM interface. If the value is clear, then the host has requested the data to be passed from the NVM interface to the vpd_data register. The value of this bit is only valid if the INTF_REQ bit is set. This bit is a RO copy of the flag bit in the vpd_flag_addr register in configuration space. #define PCIEIP_REG_REG_VPD_ADDR_FLAG_WR_BB_SHIFT 31 +#define PCIEIP_REG_PCIEEP_RASDP_UCE_RP_E5 0x000430UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RASDP_UCE_RP_UCORR_COUNT_E5 (0xff<<0) // Current uncorrected count for the selected counter. + #define PCIEIP_REG_PCIEEP_RASDP_UCE_RP_UCORR_COUNT_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RASDP_UCE_RP_UCORR_CNT_SEL_REG_E5 (0xf<<20) // Selected correctable counter region. 0x0 = ADM RX path. 0x1 = Layer 3 RX path. 0x2 = Layer 2 RX path. 0x3 = DMA inbound path (not supported). 0x4 = AXI bridge inbound request path (not supported). 0x5 = AXI bridge inbound completion composer path (not supported). 0x6 = ADM TX path. 0x7 = Layer 3 TX path. 0x8 = Layer 2 TX path. 0x9 = DMA outbound path (not supported). 0xA = AXI bridge outbound request path (not supported). 0xB = AXI bridge outbound master completion buffer path (not supported). 0xC - 0xF = Reserved. + #define PCIEIP_REG_PCIEEP_RASDP_UCE_RP_UCORR_CNT_SEL_REG_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_RASDP_UCE_RP_UCORR_CNT_SEL_E5 (0xff<<24) // Counter selection. Returns the value set in PCIEEP_RASDP_UCE_CTL[UCORR_CNT_SEL]. + #define PCIEIP_REG_PCIEEP_RASDP_UCE_RP_UCORR_CNT_SEL_E5_SHIFT 24 #define PCIEIP_REG_REG_VPD_DATA_BB 0x000430UL //Access:RW DataWidth:0x20 // This is the data register for passing values between the NVM interface and the vpd_data register in the configuration space. When INTF_REQ is '1' and the WR bit is clear, this word should be written with the NVM data requested in the ADDRESS value to clear the INTF_REQ bit. When INTF_REQ is '1' and the WR bit is set, this word should be read and written to the NVM interface. After the NVM interface write is complete, this value should be written with the same value to clear the INTF_REQ bit. When this value is written and the INTF_REQ bit is set, the FLAG bit in the vpd_flag_addr register in configurationspace will be complemented. +#define PCIEIP_REG_PCIEEP_RASDP_CE_ICTL_E5 0x000434UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RASDP_CE_ICTL_ERR_INJ_EN_E5 (0x1<<0) // Error injection global enable. When set, enables the error insertion logic. + #define PCIEIP_REG_PCIEEP_RASDP_CE_ICTL_ERR_INJ_EN_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RASDP_CE_ICTL_ERR_INJ_TYPE_E5 (0x3<<4) // Error injection type. 0x0 = None. 0x1 = 1-bit. 0x2 = 2-bit. 0x3 = Reserved. + #define PCIEIP_REG_PCIEEP_RASDP_CE_ICTL_ERR_INJ_TYPE_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_RASDP_CE_ICTL_ERR_INJ_CNT_E5 (0xff<<8) // Error injection count. 0x0 = errors are injected in every TLP until [ERR_INJ_EN] is cleared. 0x1 - 0xFF = number of errors injected. + #define PCIEIP_REG_PCIEEP_RASDP_CE_ICTL_ERR_INJ_CNT_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_RASDP_CE_ICTL_ERR_INJ_LOC_E5 (0xff<<16) // Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations. + #define PCIEIP_REG_PCIEEP_RASDP_CE_ICTL_ERR_INJ_LOC_E5_SHIFT 16 #define PCIEIP_REG_REG_ID_VAL1_BB 0x000434UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_REG_ID_VAL1_DEVICE_ID_BB (0xffff<<0) // This register programs the read value of the device_id register of the configuration space. The hardware default value is the Broadcom vendor ID. This value is sticky and only reset by HARD Reset. The default value reflects the value of DEVICE_ID in version.v defined by user or the strap pins user_device_id if user relies on straps. #define PCIEIP_REG_REG_ID_VAL1_DEVICE_ID_BB_SHIFT 0 #define PCIEIP_REG_REG_ID_VAL1_VENDOR_ID_BB (0xffff<<16) // This register programs the read value of the vendor_id register of the configuration space. The hardware default value is the Broadcom vendor ID. This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_REG_ID_VAL1_VENDOR_ID_BB_SHIFT 16 +#define PCIEIP_REG_PCIEEP_RASDP_CE_LOC_E5 0x000438UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RASDP_CE_LOC_REG_FIRST_CORR_ERR_E5 (0xf<<4) // Region of first corrected error 0x0 = ADM RX path. 0x1 = Layer 3 RX path. 0x2 = Layer 2 RX path. 0x3 = DMA read engine (not supported). 0x4 = AXI bridge inbound request path (not supported). 0x5 = AXI bridge inbound completion composer (not supported). 0x6 = ADM TX path. 0x7 = Layer 3 TX path. 0x8 = Layer 2 TX path. 0x9 = DMA write engine (not supported). 0xA = AXI bridge outbound request path (not supported). 0xB = AXI bridge outbound master completion (not supported). 0xC - 0xF = Reserved. + #define PCIEIP_REG_PCIEEP_RASDP_CE_LOC_REG_FIRST_CORR_ERR_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_RASDP_CE_LOC_LOC_FIRST_CORR_ERR_E5 (0xff<<8) // Location/ID of the first corrected error within the region defined by [REG_FIRST_CORR_ERR]. + #define PCIEIP_REG_PCIEEP_RASDP_CE_LOC_LOC_FIRST_CORR_ERR_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_RASDP_CE_LOC_REG_LAST_CORR_ERR_E5 (0xf<<20) // Region of last corrected error 0x0 = ADM RX path. 0x1 = Layer 3 RX path. 0x2 = Layer 2 RX path. 0x3 = DMA inbound path (not supported). 0x4 = AXI bridge inbound request path (not supported). 0x5 = AXI bridge inbound completion composer path (not supported). 0x6 = ADM TX path. 0x7 = Layer 3 TX path. 0x8 = Layer 2 TX path. 0x9 = DMA outbound path (not supported). 0xA = AXI bridge outbound request path (not supported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved. + #define PCIEIP_REG_PCIEEP_RASDP_CE_LOC_REG_LAST_CORR_ERR_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_RASDP_CE_LOC_LOC_LAST_CORR_ERR_E5 (0xff<<24) // Location/ID of the last corrected error within the region defined by [REG_LAST_CORR_ERR]. + #define PCIEIP_REG_PCIEEP_RASDP_CE_LOC_LOC_LAST_CORR_ERR_E5_SHIFT 24 #define PCIEIP_REG_REG_ID_VAL2_BB 0x000438UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_REG_ID_VAL2_SUBSYSTEM_VENDOR_ID_BB (0xffff<<0) // This value controls the read value of the subsystem_vendor_id value in the configuration space. This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_REG_ID_VAL2_SUBSYSTEM_VENDOR_ID_BB_SHIFT 0 #define PCIEIP_REG_REG_ID_VAL2_SUBSYSTEM_ID_BB (0xffff<<16) // This value controls the read value of the subsystem_id value in the configuration space. This value is sticky and only reset by HARD Reset. The default value reflects the value of DEVICE_ID in version.v defined by user or the strap pins user_device_id if user relies on straps. #define PCIEIP_REG_REG_ID_VAL2_SUBSYSTEM_ID_BB_SHIFT 16 +#define PCIEIP_REG_PCIEEP_RASDP_UCE_LOC_E5 0x00043cUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RASDP_UCE_LOC_REG_FIRST_UCORR_ERR_E5 (0xf<<4) // Region of first uncorrected error 0x0 = ADM RX path. 0x1 = Layer 3 RX path. 0x2 = Layer 2 RX path. 0x3 = DMA inbound path (not supported). 0x4 = AXI bridge inbound request path (not supported). 0x5 = AXI bridge inbound completion composer path (not supported). 0x6 = ADM TX path. 0x7 = Layer 3 TX path. 0x8 = Layer 2 TX path. 0x9 = DMA outbound path (not supported). 0xA = AXI bridge outbound request path (not supported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved. + #define PCIEIP_REG_PCIEEP_RASDP_UCE_LOC_REG_FIRST_UCORR_ERR_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_RASDP_UCE_LOC_LOC_FIRST_UCORR_ERR_E5 (0xff<<8) // Location/ID of the first uncorrected error within the region defined by [REG_FIRST_UCORR_ERR]. + #define PCIEIP_REG_PCIEEP_RASDP_UCE_LOC_LOC_FIRST_UCORR_ERR_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_RASDP_UCE_LOC_REG_LAST_UCORR_ERR_E5 (0xf<<20) // Region of last uncorrected error 0x0 = ADM RX path. 0x1 = Layer 3 RX path. 0x2 = Layer 2 RX path. 0x3 = DMA inbound path (not supported). 0x4 = AXI bridge inbound request path (not supported). 0x5 = AXI bridge inbound completion composer path (not supported). 0x6 = ADM TX path. 0x7 = Layer 3 TX path. 0x8 = Layer 2 TX path. 0x9 = DMA outbound path (not supported). 0xA = AXI bridge outbound request path (not supported). 0xB = AXI bridge outbound master completion path (not supported). 0xC - 0xF = Reserved. + #define PCIEIP_REG_PCIEEP_RASDP_UCE_LOC_REG_LAST_UCORR_ERR_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_RASDP_UCE_LOC_LOC_LAST_UCORR_ERR_E5 (0xff<<24) // Location/ID of the last uncorrected error within the region defined by [REG_LAST_UCORR_ERR]. + #define PCIEIP_REG_PCIEEP_RASDP_UCE_LOC_LOC_LAST_UCORR_ERR_E5_SHIFT 24 #define PCIEIP_REG_REG_ID_VAL3_BB 0x00043cUL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_REG_ID_VAL3_CLASS_CODE_BB (0xffffff<<0) // This register programs the read value of the class_code register of the configuration space. The 24-bit Class Code register identifies the generic function of the device. All of the legal values are specific in the PCI specification. The default value for this register is the class code for an Ethernet interface (0x020000). This value is sticky and only reset by HARD Reset. The default value reflects the value of CLASS_CODE in version.v defined by user. #define PCIEIP_REG_REG_ID_VAL3_CLASS_CODE_BB_SHIFT 0 #define PCIEIP_REG_REG_ID_VAL3_REVISION_ID_BB (0xff<<24) // This register programs the read value of the revision_id register of the configuration space. The default value is provided by user_revision_id strap pins. This field also exists in VF register space #define PCIEIP_REG_REG_ID_VAL3_REVISION_ID_BB_SHIFT 24 +#define PCIEIP_REG_PCIEEP_RASDP_DE_ME_E5 0x000440UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RASDP_DE_ME_ERR_MODE_EN_E5 (0x1<<0) // Set this bit to enable the core to enter RASDP error mode when it detects an uncorrectable error. + #define PCIEIP_REG_PCIEEP_RASDP_DE_ME_ERR_MODE_EN_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RASDP_DE_ME_AUTO_LNK_DN_EN_E5 (0x1<<1) // Set this bit to enable the core to bring the link down when RASDP error mode is entered. + #define PCIEIP_REG_PCIEEP_RASDP_DE_ME_AUTO_LNK_DN_EN_E5_SHIFT 1 #define PCIEIP_REG_REG_ID_VAL4_BB 0x000440UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_REG_ID_VAL4_CAP_ENA_BB (0xf<<0) // This value controls the read value of the next capability pointers in the PCIE configuration space and allows each extra capability to be independently disabled by manipulation of the next pointer values. The read values for each enable combination is shown below. PCIE capability is always enabled. Bit 0 enables the Power Management capability. Bit 1 enables the VPD capability, and Bit 2 enables the MSI capability and Bit3 is MSIX capability This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_REG_ID_VAL4_CAP_ENA_BB_SHIFT 0 @@ -2872,6 +4667,9 @@ #define PCIEIP_REG_REG_ID_VAL4_MSI_ENABLE_BB_SHIFT 15 #define PCIEIP_REG_REG_ID_VAL4_RESERVED3_BB (0xffff<<16) // #define PCIEIP_REG_REG_ID_VAL4_RESERVED3_BB_SHIFT 16 +#define PCIEIP_REG_PCIEEP_RASDP_DE_MC_E5 0x000444UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RASDP_DE_MC_ERR_MODE_CLR_E5 (0x1<<0) // Set this bit to take the core out of RASDP error mode. The core will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs. + #define PCIEIP_REG_PCIEEP_RASDP_DE_MC_ERR_MODE_CLR_E5_SHIFT 0 #define PCIEIP_REG_REG_ID_VAL5_BB 0x000444UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_REG_ID_VAL5_D1_SUPPORT_BB (0x1<<0) // This bit indicates whether the device supports the D1 power management state. It is reflected in the D1_SUPPORT bit in the configuration space. This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_REG_ID_VAL5_D1_SUPPORT_BB_SHIFT 0 @@ -2891,38 +4689,177 @@ #define PCIEIP_REG_REG_ID_VAL5_NO_SOFT_RESET_BB_SHIFT 9 #define PCIEIP_REG_REG_ID_VAL5_RESERVED0_BB (0x3fffff<<10) // #define PCIEIP_REG_REG_ID_VAL5_RESERVED0_BB_SHIFT 10 +#define PCIEIP_REG_PCIEEP_RASDP_RADR_CE_E5 0x000448UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RASDP_RADR_CE_RAM_ADDR_CORR_ERR_E5 (0x7ffffff<<0) // RAM address where a corrected error has been detected. + #define PCIEIP_REG_PCIEEP_RASDP_RADR_CE_RAM_ADDR_CORR_ERR_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RASDP_RADR_CE_RAM_IDX_CORR_ERR_E5 (0xf<<28) // RAM index where a corrected error has been detected. + #define PCIEIP_REG_PCIEEP_RASDP_RADR_CE_RAM_IDX_CORR_ERR_E5_SHIFT 28 +#define PCIEIP_REG_PCIEEP_RASDP_RADR_UCE_E5 0x00044cUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RASDP_RADR_UCE_RAM_ADDR_UCORR_ERR_E5 (0x7ffffff<<0) // RAM address where a uncorrected error has been detected. + #define PCIEIP_REG_PCIEEP_RASDP_RADR_UCE_RAM_ADDR_UCORR_ERR_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RASDP_RADR_UCE_RAM_IDX_UCORR_ERR_E5 (0xf<<28) // RAM index where a uncorrected error has been detected. + #define PCIEIP_REG_PCIEEP_RASDP_RADR_UCE_RAM_IDX_UCORR_ERR_E5_SHIFT 28 #define PCIEIP_REG_REG_ID_VAL6_BB 0x00044cUL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_REG_ID_VAL6_UNUSED0_BB (0xffff<<0) // #define PCIEIP_REG_REG_ID_VAL6_UNUSED0_BB_SHIFT 0 #define PCIEIP_REG_REG_ID_VAL6_BIST_BB (0xff<<16) // This register controls the read value of the bist register in the configuration space. This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_REG_ID_VAL6_BIST_BB_SHIFT 16 +#define PCIEIP_REG_PCIEEP_DL_FT_CAP_HDR_E5 0x000450UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_DL_FT_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_DL_FT_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_DL_FT_CAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_DL_FT_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_DL_FT_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_DL_FT_CAP_HDR_NCO_E5_SHIFT 20 #define PCIEIP_REG_REG_MSI_DATA_BB 0x000450UL //Access:R DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_REG_MSI_DATA_MSI_DATA_BB (0xffff<<0) // This register reflects the MSI data register value in the configuration space. This value may be used by the completion processor to determine the data value it will use for vectored MSI cycles. #define PCIEIP_REG_REG_MSI_DATA_MSI_DATA_BB_SHIFT 0 +#define PCIEIP_REG_PCIEEP_DLINK_CAP_E5 0x000454UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_DLINK_CAP_SFCS_E5 (0x1<<0) // Local scaled flow control supported, + #define PCIEIP_REG_PCIEEP_DLINK_CAP_SFCS_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_DLINK_CAP_FFS_E5 (0x3fffff<<1) // Local future data link feature supported. + #define PCIEIP_REG_PCIEEP_DLINK_CAP_FFS_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_DLINK_CAP_DFEEN_E5 (0x1<<31) // Data link feature exchange enable. + #define PCIEIP_REG_PCIEEP_DLINK_CAP_DFEEN_E5_SHIFT 31 #define PCIEIP_REG_REG_MSI_ADDR_H_BB 0x000454UL //Access:R DataWidth:0x20 // This register reflects the upper half of the MSI address register value in the configuration space. This value may be used by the completion processor to determine the address value it will use for vectored MSI cycles. +#define PCIEIP_REG_PCIEEP_DLINK_FSTAT_E5 0x000458UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_DLINK_FSTAT_RDLFS_E5 (0x7fffff<<0) // Only bit 0 is currently defined - remote scaled flow control supported. + #define PCIEIP_REG_PCIEEP_DLINK_FSTAT_RDLFS_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_DLINK_FSTAT_RDLFA_E5 (0x1<<23) // Indicates that remote port has received this port's data link feature DLLP. + #define PCIEIP_REG_PCIEEP_DLINK_FSTAT_RDLFA_E5_SHIFT 23 + #define PCIEIP_REG_PCIEEP_DLINK_FSTAT_DLFSV_E5 (0x1<<31) // Remote data link feature supported valid. + #define PCIEIP_REG_PCIEEP_DLINK_FSTAT_DLFSV_E5_SHIFT 31 #define PCIEIP_REG_REG_MSI_ADDR_L_BB 0x000458UL //Access:R DataWidth:0x20 // This register reflects the lower half of the MSI address bit[31:2] value in the configuration space. The lower two bits [1:0] are hard wired to zero. This value may be used by the completion processor to determine the address value it will use for vectored MSI cycles. +#define PCIEIP_REG_PCIEEP_PTM_CAP_HDR_E5 0x00045cUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PTM_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PTM_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PTM_CAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PTM_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_PTM_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PTM_CAP_HDR_NCO_E5_SHIFT 20 +#define PCIEIP_REG_PCIEEP_PTM_CAP_E5 0x000460UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PTM_CAP_RQC_E5 (0x1<<0) // PTM requester capable. + #define PCIEIP_REG_PCIEEP_PTM_CAP_RQC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PTM_CAP_RSC_E5 (0x1<<1) // PTM responder capable. Writable only if [RTC] is 0, otherwise always 1. + #define PCIEIP_REG_PCIEEP_PTM_CAP_RSC_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_PTM_CAP_RTC_E5 (0x1<<2) // PTM root capable. + #define PCIEIP_REG_PCIEEP_PTM_CAP_RTC_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_PTM_CAP_CLKG_E5 (0xff<<8) // PTM local clock granularity. + #define PCIEIP_REG_PCIEEP_PTM_CAP_CLKG_E5_SHIFT 8 +#define PCIEIP_REG_PCIEEP_PTM_CTL_E5 0x000464UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PTM_CTL_PEN_E5 (0x1<<0) // PTM enable. When set, this function is permitted to participate in the PTM mechanism. + #define PCIEIP_REG_PCIEEP_PTM_CTL_PEN_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PTM_CTL_RT_SEL_E5 (0x1<<1) // PTM root select. When set this time source is the PTM root. + #define PCIEIP_REG_PCIEEP_PTM_CTL_RT_SEL_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_PTM_CTL_EFF_GRAN_E5 (0xff<<8) // PTM effective granularity. + #define PCIEIP_REG_PCIEEP_PTM_CTL_EFF_GRAN_E5_SHIFT 8 #define PCIEIP_REG_REG_MSI_MASK_BB 0x000464UL //Access:R DataWidth:0x20 // This register reflects the MSI mask register value in the configuration space +#define PCIEIP_REG_PCIEEP_PTM_REQ_CAP_HDR_E5 0x000468UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PTM_REQ_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PTM_REQ_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PTM_REQ_CAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PTM_REQ_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_PTM_REQ_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_PTM_REQ_CAP_HDR_NCO_E5_SHIFT 20 #define PCIEIP_REG_REG_MSI_PEND_BB 0x000468UL //Access:RW DataWidth:0x20 // Each pending bit that is set , the function has a pending associated message. This register gets reflected in the configuration space. +#define PCIEIP_REG_PCIEEP_PTM_REQ_HDR_E5 0x00046cUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PTM_REQ_HDR_PRVID_E5 (0xffff<<0) // PTM requester VSEC ID. + #define PCIEIP_REG_PCIEEP_PTM_REQ_HDR_PRVID_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PTM_REQ_HDR_PRVR_E5 (0xf<<16) // PTM requester VSEC revision. + #define PCIEIP_REG_PCIEEP_PTM_REQ_HDR_PRVR_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_PTM_REQ_HDR_PRVL_E5 (0xfff<<20) // PTM requester VSEC length. + #define PCIEIP_REG_PCIEEP_PTM_REQ_HDR_PRVL_E5_SHIFT 20 #define PCIEIP_REG_REG_PM_DATA_C_BB 0x00046cUL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_REG_PM_DATA_C_PM_DATA_8_PRG_BB (0xff<<0) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 8. This is the power dissipated by common logic in case of multi function devices. This value is sticky and only reset by HARD Reset. #define PCIEIP_REG_REG_PM_DATA_C_PM_DATA_8_PRG_BB_SHIFT 0 #define PCIEIP_REG_REG_PM_DATA_C_RESERVED0_BB (0xffffff<<8) // #define PCIEIP_REG_REG_PM_DATA_C_RESERVED0_BB_SHIFT 8 +#define PCIEIP_REG_PCIEEP_PTM_REQ_CTL_E5 0x000470UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PTM_REQ_CTL_RAUEN_E5 (0x1<<0) // PTM requester auto update enabled. When enabled, PTM Requester will automatically attempt to update its context every 10ms. + #define PCIEIP_REG_PCIEEP_PTM_REQ_CTL_RAUEN_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PTM_REQ_CTL_RSD_E5 (0x1<<1) // PTM requester start update. When set the PTM Requester will attempt a PTM Dialogue to update it's context; This bit is self clearing. For more details, see the PTM section in the Databook. + #define PCIEIP_REG_PCIEEP_PTM_REQ_CTL_RSD_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_PTM_REQ_CTL_RFT_E5 (0x1<<2) // PTM fast timers. Debug mode for PTM timers. The 100us timer output will go high at 30us and the 10ms timer output will go high at 100us (The Long Timer Value is ignored). There is no change to the 1us timer. The requester operation will otherwise remain the same. For more details, see the PTM section in the Databook. + #define PCIEIP_REG_PCIEEP_PTM_REQ_CTL_RFT_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_PTM_REQ_CTL_RLT_E5 (0xff<<8) // PTM requester long timer. Determines the period between each auto update PTM Dialogue in miliseconds. Update period is the register value +1 milisecond. For the Switch product this value must not be set larger than 0x9 for spec compliance. For more details, see the PTM section in the Databook. + #define PCIEIP_REG_PCIEEP_PTM_REQ_CTL_RLT_E5_SHIFT 8 +#define PCIEIP_REG_PCIEEP_PTM_REQ_STAT_E5 0x000474UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PTM_REQ_STAT_RCV_E5 (0x1<<0) // PTM requester context valid. + #define PCIEIP_REG_PCIEEP_PTM_REQ_STAT_RCV_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PTM_REQ_STAT_RMUA_E5 (0x1<<1) // PTM requester manual update allowed. Indicates whether or not a manual update can be signalled. + #define PCIEIP_REG_PCIEEP_PTM_REQ_STAT_RMUA_E5_SHIFT 1 +#define PCIEIP_REG_PCIEEP_PTM_REQ_LOCALL_E5 0x000478UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_PTM_REQ_LOCALM_E5 0x00047cUL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_PTM_REQ_T1L_E5 0x000480UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_PTM_REQ_T1M_E5 0x000484UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_PTM_REQ_T1PL_E5 0x000488UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_PTM_REQ_T1PM_E5 0x00048cUL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_PTM_REQ_T4L_E5 0x000490UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_PTM_REQ_T4M_E5 0x000494UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_PTM_REQ_T4PL_E5 0x000498UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_PTM_REQ_T4PM_E5 0x00049cUL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_PTM_REQ_MASL_E5 0x0004a0UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_PTM_REQ_MASM_E5 0x0004a4UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_PTM_REQ_PDLY_E5 0x0004a8UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_PTM_REQ_MAS1L_E5 0x0004acUL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_PTM_REQ_MAS1M_E5 0x0004b0UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_PTM_REQ_TLAT_E5 0x0004b4UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PTM_REQ_TLAT_RTL_E5 (0xfff<<0) // PTM requester TX latency. + #define PCIEIP_REG_PCIEEP_PTM_REQ_TLAT_RTL_E5_SHIFT 0 +#define PCIEIP_REG_PCIEEP_PTM_REQ_RLAT_E5 0x0004b8UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PTM_REQ_RLAT_RRL_E5 (0xfff<<0) // PTM requester RX latency. + #define PCIEIP_REG_PCIEEP_PTM_REQ_RLAT_RRL_E5_SHIFT 0 +#define PCIEIP_REG_PCIEEP_RBAR_CAP_HDR_E5 0x0004bcUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RBAR_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_RBAR_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RBAR_CAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_RBAR_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_RBAR_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_RBAR_CAP_HDR_NCO_E5_SHIFT 20 +#define PCIEIP_REG_PCIEEP_RBAR_CAP_E5 0x0004c0UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RBAR_CAP_SRS_E5 (0xfffffff<<4) // Supported resource sizes. PEM advertises the maximum allowable BAR size (512 GB - 0xF_FFFF) when the fus__bar2_size_conf is intact. When the fuse is blown, the CNXXXX advertises a BAR size of 4096TB (0xFFF_FFFF and PCIEEP)_RBAR_CTL[ESRS] = 0x1F). The BAR is disabled at runtime by writing all zeros through PEM()_CFG_WR to this field. Note that when writing this field via PEM()_CFG_WR, all 28 bits must be updated at the same time, byte writes are ignored. + #define PCIEIP_REG_PCIEEP_RBAR_CAP_SRS_E5_SHIFT 4 #define PCIEIP_REG_REG_MSIX_CONTROL_BB 0x0004c0UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_REG_MSIX_CONTROL_MSIX_TBL_SIZ_BB (0x7ff<<0) // This register controls the read value of the MSIX_CONTROL[10:0] register in the configuration space. A value of "00000000011" indicates a table size of 4 Lower 6 bits of this field also exists in VF register space #define PCIEIP_REG_REG_MSIX_CONTROL_MSIX_TBL_SIZ_BB_SHIFT 0 #define PCIEIP_REG_REG_MSIX_CONTROL_RESERVED0_BB (0x1fffff<<11) // #define PCIEIP_REG_REG_MSIX_CONTROL_RESERVED0_BB_SHIFT 11 +#define PCIEIP_REG_PCIEEP_RBAR_CTL_E5 0x0004c4UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RBAR_CTL_RBARI_E5 (0x7<<0) // BAR Index. Points to BAR2. + #define PCIEIP_REG_PCIEEP_RBAR_CTL_RBARI_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RBAR_CTL_NRBAR_E5 (0x7<<5) // Number of resizable BARs + #define PCIEIP_REG_PCIEEP_RBAR_CTL_NRBAR_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_RBAR_CTL_RBARS_E5 (0x3f<<8) // BAR Size. PEM advertises the minimum allowable BAR size of 0x0 (1MB) but will accept values as large as 0x2B (8EB). + #define PCIEIP_REG_PCIEEP_RBAR_CTL_RBARS_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_RBAR_CTL_ESRS_E5 (0xffff<<16) // Extended supported resource sizes. PEM advertises the maximum allowable BAR size (512 GB) when the fus__bar2_size_conf is intact. When the fuse is blown, the CNXXXX advertises a BAR size of 4096TB (PCIEEP)_RBAR_CTL[SRS] = 0xFFF_FFFF and ESRS = 0x1F). The BAR is disabled at runtime by writing all zeros through PEM()_CFG_WR to this field. + #define PCIEIP_REG_PCIEEP_RBAR_CTL_ESRS_E5_SHIFT 16 #define PCIEIP_REG_REG_MSIX_TBL_OFF_BIR_BB 0x0004c4UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_REG_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR_BB (0x7<<0) // This register controls the read value of the MSIX_TBL_OFF_BIR[2:0] register. This indicates which one of the function's Base address registers located at 10h in configuration space is used to map the function's MSI-X table into memory space. Value is controlled by PCIE_MSIX_TBL_OFF field in version.v #define PCIEIP_REG_REG_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR_BB_SHIFT 0 #define PCIEIP_REG_REG_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF_BB (0x1fffffff<<3) // This register controls the read value of the MSIX_TBL_OFF_BIR[31:3] register. This is used as an offset from the address contained by one of the functions Base address registers to point to the base of the MSI-X table. Value is controlled by PCIE_MSIX_TBL_OFF field in version.v #define PCIEIP_REG_REG_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF_BB_SHIFT 3 +#define PCIEIP_REG_PCIEEP_VSECST_CAP_HDR_E5 0x0004c8UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_VSECST_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_VSECST_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_VSECST_CAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_VSECST_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_VSECST_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_VSECST_CAP_HDR_NCO_E5_SHIFT 20 #define PCIEIP_REG_REG_MSIX_PBA_OFF_BIR_BB 0x0004c8UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_REG_MSIX_PBA_OFF_BIR_MSIX_PBA_BIR_BB (0x7<<0) // This register controls the read value of the MSIX_PBA_OFF_BIR[2:0] register. This indicates which one of the function's Base address registers located at 10h in configuration space is used to map the function's MSI-X PBA into memory space. Value is controlled by PCIE_MSIX_PBA_OFF field in version.v #define PCIEIP_REG_REG_MSIX_PBA_OFF_BIR_MSIX_PBA_BIR_BB_SHIFT 0 #define PCIEIP_REG_REG_MSIX_PBA_OFF_BIR_MSIX_PBA_OFF_BB (0x1fffffff<<3) // This register controls the read value of the MSIX_PBA_OFF_BIR[31:3] register. This is used as an offset from the address contained by one of the functions Base address registers to point to the base of the MSI-X PBA Value is controlled by PCIE_MSIX_PBA_OFF field in version.v #define PCIEIP_REG_REG_MSIX_PBA_OFF_BIR_MSIX_PBA_OFF_BB_SHIFT 3 +#define PCIEIP_REG_PCIEEP_VSECST_HDR_E5 0x0004ccUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_VSECST_HDR_VSEC_ID_E5 (0xffff<<0) // VSEC ID. + #define PCIEIP_REG_PCIEEP_VSECST_HDR_VSEC_ID_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_VSECST_HDR_VSEC_REV_E5 (0xf<<16) // Capability version. + #define PCIEIP_REG_PCIEEP_VSECST_HDR_VSEC_REV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_VSECST_HDR_VSEC_LENGTH_E5 (0xfff<<20) // VSEC length. + #define PCIEIP_REG_PCIEEP_VSECST_HDR_VSEC_LENGTH_E5_SHIFT 20 +#define PCIEIP_REG_PCIEEP_VSECST_CTL_E5 0x0004d0UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_VSECST_CTL_STATUS_E5 (0xff<<0) // Indicates status of internal core logic to host software driver. Typically 0x0 would indicate to the host driver that CNXXXX firmware is not loaded, and non-zero values indicate some software-defined post-firmware loaded state information or failure code. This register will be reset on a core reset. This register is not RSL-writable (always reads 0x0 from host) for all PFs other than PF0. + #define PCIEIP_REG_PCIEEP_VSECST_CTL_STATUS_E5_SHIFT 0 #define PCIEIP_REG_REG_PCIE_CAPABILITY_BB 0x0004d0UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_REG_PCIE_CAPABILITY_INTERRUPT_MSG_NUM_BB (0x1f<<0) // This controls the value in configuration space #define PCIEIP_REG_REG_PCIE_CAPABILITY_INTERRUPT_MSG_NUM_BB_SHIFT 0 @@ -3305,176 +5242,422 @@ #define PCIEIP_REG_REG_VFTPH_CAP_UNUSED0_BB_SHIFT 15 #define PCIEIP_REG_REG_VFTPH_CAP_TPH_SUPP_INVF_BB (0x1<<31) // This field when set enables TPH capability in all the VF's. #define PCIEIP_REG_REG_VFTPH_CAP_TPH_SUPP_INVF_BB_SHIFT 31 -#define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_K2_E5 0x000700UL //Access:RW DataWidth:0x20 // Ack Latency Timer and Replay Timer Register. - #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_K2_E5 (0xffff<<0) // Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details, see "Ack Scheduling". You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. After reset, the core updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed. The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe 3.0 specification. The limit must reflect the round trip latency from requester to completer. If there is a change in the payload size or link width, the core will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. - #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_K2_E5_SHIFT 0 - #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_K2_E5 (0xffff<<16) // Replay Timer Limit. The replay timer expires when it reaches this limit. The core initiates a replay upon reception of a NAK or when the replay timer expires. For more details, see "Transmit Replay". You can modify the effective timer limit with the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. After reset, the core updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed. The value is determined from Tables 3-4, 3-5, and 3-6 of the PCIe 3.0 specification. If there is a change in the payload size or link speed, the core will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. - #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_K2_E5_SHIFT 16 -#define PCIEIP_REG_VENDOR_SPEC_DLLP_OFF_K2_E5 0x000704UL //Access:RW DataWidth:0x20 // Vendor Specific DLLP Register. -#define PCIEIP_REG_PORT_FORCE_OFF_K2_E5 0x000708UL //Access:RW DataWidth:0x20 // Port Force Link Register. - #define PCIEIP_REG_PORT_FORCE_OFF_LINK_NUM_K2_E5 (0xff<<0) // Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky. - #define PCIEIP_REG_PORT_FORCE_OFF_LINK_NUM_K2_E5_SHIFT 0 - #define PCIEIP_REG_PORT_FORCE_OFF_FORCED_LTSSM_K2_E5 (0xf<<8) // Forced Link Command. The link command that the core is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky. - #define PCIEIP_REG_PORT_FORCE_OFF_FORCED_LTSSM_K2_E5_SHIFT 8 - #define PCIEIP_REG_PORT_FORCE_OFF_FORCE_EN_K2_E5 (0x1<<15) // Force Link. The core supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state, and to force the core to transmit a specific Link Command. Asserting this bit triggers the following actions: - Forces the LTSSM to the state specified by the Forced LTSSM State field. - Forces the core to transmit the command specified by the Forced Link Command field. This is a self-clearing register field. Reading from this register field always returns a "0". - #define PCIEIP_REG_PORT_FORCE_OFF_FORCE_EN_K2_E5_SHIFT 15 - #define PCIEIP_REG_PORT_FORCE_OFF_LINK_STATE_K2_E5 (0x3f<<16) // Forced LTSSM State. The LTSSM state that the core is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky. - #define PCIEIP_REG_PORT_FORCE_OFF_LINK_STATE_K2_E5_SHIFT 16 - #define PCIEIP_REG_PORT_FORCE_OFF_CPL_SENT_COUNT_K2_E5 (0xff<<24) // Low Power Entrance Count. The Power Management state waits for this many clock cycles for the associated completion of a CfgWr to D-state register to go low-power. This register is intended for applications that do not let the core handle a completion for configuration request to the PMCSCR register. Not used in downstream ports. Note: This register field is sticky. - #define PCIEIP_REG_PORT_FORCE_OFF_CPL_SENT_COUNT_K2_E5_SHIFT 24 -#define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_K2_E5 0x00070cUL //Access:RW DataWidth:0x20 // Ack Frequency and L0-L1 ASPM Control Register. - #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_K2_E5 (0xff<<0) // Ack Frequency. The core accumulates the number of pending ACKs specified here (up to 255) before sending an ACK DLLP. - 0: Indicates that this Ack frequency control feature is turned off. The core schedules a low-priority ACK DLLP for every TLP that it receives. - 1-255: Indicates that the core will schedule a high-priority ACK after receiving this number of TLPs. It might schedule the ACK before receiving this number of TLPs, but never later. For a typical system, you do not have to modify the default setting. For more details, see "ACK/NAK Scheduling". Note: This register field is sticky. - #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_K2_E5_SHIFT 0 - #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_K2_E5 (0xff<<8) // N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The core does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky. - #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_K2_E5_SHIFT 8 - #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_K2_E5 (0xff<<16) // Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. This field is only writable (sticky) when all of the following configuration parameter equations are true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY The core does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_K2_E5_SHIFT 16 - #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_K2_E5 (0x7<<24) // L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky. - #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_K2_E5_SHIFT 24 - #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_K2_E5 (0x7<<27) // L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used, or all of the credits are infinite. Note: This register field is sticky. - #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_K2_E5_SHIFT 27 - #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_K2_E5 (0x1<<30) // ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has been idle. - 0: Core enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky. - #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_K2_E5_SHIFT 30 -#define PCIEIP_REG_PORT_LINK_CTRL_OFF_K2_E5 0x000710UL //Access:RW DataWidth:0x20 // Port Link Control Register. - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_K2_E5 (0x1<<0) // Vendor Specific DLLP Request. When software writes a '1' to this bit, the core transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always returns a '0'. - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_K2_E5_SHIFT 0 - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_K2_E5 (0x1<<1) // Scramble Disable. Turns off data scrambling. Note: This register field is sticky. - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_K2_E5_SHIFT 1 - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_K2_E5 (0x1<<2) // Loopback Enable. Turns on loopback. For more details, see "Loopback". For M-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during Configuration.start state(initial discovery/configuration). M-PCIe doesn't support loopback mode from L0 state - only from Configuration.start. Note: This register field is sticky. - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_K2_E5_SHIFT 2 - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_RESET_ASSERT_K2_E5 (0x1<<3) // Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky. - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_RESET_ASSERT_K2_E5_SHIFT 3 - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_DLL_LINK_EN_K2_E5 (0x1<<5) // DLL Link Enable. Enables link initialization. When DLL Link Enable =0, the core does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky. - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_DLL_LINK_EN_K2_E5_SHIFT 5 - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_DISABLE_K2_E5 (0x1<<6) // LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky. - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_DISABLE_K2_E5_SHIFT 6 - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_K2_E5 (0x1<<7) // Fast Link Mode. Sets all internal timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The scaling factor is selected in FAST_LINK_SCALING_FACTOR(default : 1024) for all internal timers. Fast Link Mode can also be activated by setting the diag_ctrl_bus[2] pin to "1". For more details, see "SII Signals: Diagnostic Control". For M-PCIe, this field also affects Remain Hibern8 Time, Minimum Activate Time, and RRAP timeout. If this bit is set to '1', tRRAPInitiatorResponse is set to 1.88 ms(60 ms/32). Note: This register field is sticky. - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_K2_E5_SHIFT 7 - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_RATE_K2_E5 (0xf<<8) // LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky. - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_RATE_K2_E5_SHIFT 8 - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_CAPABLE_K2_E5 (0x3f<<16) // Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Predetermined Number of Lanes" field of the "Link Width and Speed Change Control Register". For more information, see "How to Tie Off Unused Lanes". For information on upsizing and downsizing the link width, see "Link Establishment". - 000001: x1 - 000011: x2 - 000111: x4 - 001111: x8 - 011111: x16 - 111111: x32 (not supported) This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky. - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_CAPABLE_K2_E5_SHIFT 16 - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_BEACON_ENABLE_K2_E5 (0x1<<24) // BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky. - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_BEACON_ENABLE_K2_E5_SHIFT 24 - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_K2_E5 (0x1<<25) // CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky. - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_K2_E5_SHIFT 25 - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_K2_E5 (0x1<<26) // EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky. - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_K2_E5_SHIFT 26 - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_K2_E5 (0x1<<27) // TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky. - #define PCIEIP_REG_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_K2_E5_SHIFT 27 -#define PCIEIP_REG_LANE_SKEW_OFF_K2_E5 0x000714UL //Access:RW DataWidth:0x20 // Lane Skew Register. - #define PCIEIP_REG_LANE_SKEW_OFF_INSERT_LANE_SKEW_K2_E5 (0xffffff<<0) // Insert Lane Skew for Transmit (not supported for x16). Optional feature that causes the core to insert skew between Lanes for test purposes. There are three bits per Lane. The value is in units of one symbol time. For example, the value 010b for a Lane forces a skew of two symbol times for that Lane. The maximum skew value for any Lane is 5 symbol times. Note: This register field is sticky. - #define PCIEIP_REG_LANE_SKEW_OFF_INSERT_LANE_SKEW_K2_E5_SHIFT 0 - #define PCIEIP_REG_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_K2_E5 (0x1<<24) // Flow Control Disable. Prevents the core from sending FC DLLPs. Note: This register field is sticky. - #define PCIEIP_REG_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_K2_E5_SHIFT 24 - #define PCIEIP_REG_LANE_SKEW_OFF_ACK_NAK_DISABLE_K2_E5 (0x1<<25) // Ack/Nak Disable. Prevents the core from sending ACK and NAK DLLPs. Note: This register field is sticky. - #define PCIEIP_REG_LANE_SKEW_OFF_ACK_NAK_DISABLE_K2_E5_SHIFT 25 - #define PCIEIP_REG_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_K2_E5 (0x1<<31) // Disable Lane-to-Lane Deskew. Causes the core to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky. - #define PCIEIP_REG_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_K2_E5_SHIFT 31 -#define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_K2_E5 0x000718UL //Access:RW DataWidth:0x20 // Timer Control and Max Function Number Register. - #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_K2_E5 (0xff<<0) // Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky. - #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_K2_E5_SHIFT 0 - #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_K2_E5 (0x1f<<14) // Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock cycles at Gen3 speed. A value of "0" represents no modification to the timer limit. For more details, see the REPLAY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register. At Gen3 speed, the core automatically changes the value of this field to DEFAULT_GEN3_REPLAY_ADJ. For M-PCIe, this field increases the time-out value for the replay timer in increments of 64 clock cycles at HS-Gear1, HS-Gear2, or HS-Gear3 speed. Note: This register field is sticky. - #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_K2_E5_SHIFT 14 - #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_K2_E5 (0x1f<<19) // Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of "0" represents no modification to the timer value. For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register. Note: This register field is sticky. - #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_K2_E5_SHIFT 19 - #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_K2_E5 (0x1f<<24) // UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky. - #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_K2_E5_SHIFT 24 - #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_K2_E5 (0x3<<29) // Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE is set to 1b. - 0: Scaling Factor is 1024 (1ms is 1us) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling Factor is 64 (1ms is 16us) - 3: Scaling Factor is 16 (1ms is 64us) Not used for M-PCIe. Note: This register field is sticky. - #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_K2_E5_SHIFT 29 -#define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_K2_E5 0x00071cUL //Access:RW DataWidth:0x20 // Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule. - #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_K2_E5 (0x7ff<<0) // SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the core actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application must program this register accordingly. For example, if 1536 were programmed into this register (in a 250 MHz core), then the core actually transmits SKP ordered sets once every 1537 symbol times. The value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz core, programming the value programmed to this register should be scaled down by a factor of 2 (because one clock tick = two symbol times in this case). Note: This value is not used at Gen3 speed; the skip interval is hardcoded to 370 blocks. Note: This register field is sticky. - #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_K2_E5_SHIFT 0 - #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_K2_E5 (0xf<<11) // EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky. - #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_K2_E5_SHIFT 11 - #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_K2_E5 (0x1<<15) // Disable FC Watchdog Timer. Note: This register field is sticky. - #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_K2_E5_SHIFT 15 - #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_K2_E5 (0xffff<<16) // Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule. [31]: CX_FLT_MASK_RC_CFG_DISCARD - 0: For RADM RC filter to not allow CFG transaction being received - 1: For RADM RC filter to allow CFG transaction being received [30]: CX_FLT_MASK_RC_IO_DISCARD - 0: For RADM RC filter to not allow IO transaction being received - 1: For RADM RC filter to allow IO transaction being received [29]: CX_FLT_MASK_MSG_DROP - 0: Drop MSG TLP (except for Vendor MSG). Send decoded message on the SII. - 1: Do not Drop MSG (except for Vendor MSG). Send message TLPs to your application on TRGT1 and send decoded message on the SII. - The default for this bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG =1, then the default of this bit is "0" (drop message TLPs). This bit only controls message TLPs other than Vendor MSGs. Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0]. The core never passes ATS Invalidate messages to the SII interface regardless of this filter rule setting. The core passes all ATS Invalidate messages to TRGT1 (or AXI bridge master), as they are too big for the SII. [28]: CX_FLT_MASK_CPL_ECRC_DISCARD - Only used when completion queue is advertised with infinite credits and is in store-and-forward mode. - 0: Discard completions with ECRC errors - 1: Allow completions with ECRC errors to be passed up - Reserved field for SW. [27]: CX_FLT_MASK_ECRC_DISCARD - 0: Discard TLPs with ECRC errors - 1: Allow TLPs with ECRC errors to be passed up [26]: CX_FLT_MASK_CPL_LEN_MATCH - 0: Enforce length match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err - 1: MASK length match for completions [25]: CX_FLT_MASK_CPL_ATTR_MATCH - 0: Enforce attribute match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask attribute match for completions [24]: CX_FLT_MASK_CPL_TC_MATCH - 0: Enforce Traffic Class match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Traffic Class match for completions [23]: CX_FLT_MASK_CPL_FUNC_MATCH - 0: Enforce function match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask function match for completions [22]: CX_FLT_MASK_CPL_REQID_MATCH - 0: Enforce Req. Id match for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Req. Id match for completions [21]: CX_FLT_MASK_CPL_TAGERR_MATCH - 0: Enforce Tag Error Rules for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Tag Error Rules for completions [20]: CX_FLT_MASK_LOCKED_RD_AS_UR - 0: Treat locked Read TLPs as UR for EP; Supported for RC - 1: Treat locked Read TLPs as Supported for EP; UR for RC [19]: CX_FLT_MASK_CFG_TYPE1_RE_AS_UR - 0: Treat CFG type1 TLPs as UR for EP; Supported for RC - 1: Treat CFG type1 TLPs as Supported for EP; UR for RC - When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config requests if the EP consumes more than one bus number. [18]: CX_FLT_MASK_UR_OUTSIDE_BAR - 0: Treat out-of-bar TLPs as UR - 1: Do not treat out-of-bar TLPs as UR [17]: CX_FLT_MASK_UR_POIS - 0: Treat poisoned request TLPs as UR - 1: Do not treat poisoned request TLPs as UR - The native core always passes poisoned completions to your application except when you are using the DMA read channel. [16]: CX_FLT_MASK_UR_FUNC_MISMATCH - 0: Treat Function MisMatched TLPs as UR - 1: Do not treat Function MisMatched TLPs as UR Note: This register field is sticky. - #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_K2_E5_SHIFT 16 -#define PCIEIP_REG_FILTER_MASK_2_OFF_K2_E5 0x000720UL //Access:RW DataWidth:0x20 // Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule. -#define PCIEIP_REG_PL_DEBUG0_OFF_K2_E5 0x000728UL //Access:R DataWidth:0x20 // Debug Register 0 -#define PCIEIP_REG_PL_DEBUG1_OFF_K2_E5 0x00072cUL //Access:R DataWidth:0x20 // Debug Register 1 -#define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_K2_E5 0x000730UL //Access:R DataWidth:0x20 // Transmit Posted FC Credit Status - #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_K2_E5 (0xfff<<0) // Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]. - #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_K2_E5_SHIFT 0 - #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_K2_E5 (0xff<<12) // Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]. - #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_K2_E5_SHIFT 12 -#define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_K2_E5 0x000734UL //Access:R DataWidth:0x20 // Transmit Non-Posted FC Credit Status - #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_K2_E5 (0xfff<<0) // Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]. - #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_K2_E5_SHIFT 0 - #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_K2_E5 (0xff<<12) // Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]. - #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_K2_E5_SHIFT 12 -#define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_K2_E5 0x000738UL //Access:R DataWidth:0x20 // Transmit Completion FC Credit Status - #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_K2_E5 (0xfff<<0) // Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]. - #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_K2_E5_SHIFT 0 - #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_K2_E5 (0xff<<12) // Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]. - #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_K2_E5_SHIFT 12 -#define PCIEIP_REG_QUEUE_STATUS_OFF_K2_E5 0x00073cUL //Access:RW DataWidth:0x20 // Queue Status - #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_K2_E5 (0x1<<0) // Received TLP FC Credits Not Returned. Indicates that the core has sent a TLP but has not yet received an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the link. - #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_K2_E5_SHIFT 0 - #define PCIEIP_REG_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_K2_E5 (0x1<<1) // Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer. - #define PCIEIP_REG_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_K2_E5_SHIFT 1 - #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_K2_E5 (0x1<<2) // Received Queue Not Empty. Indicates there is data in one or more of the receive buffers. - #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_K2_E5_SHIFT 2 - #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_K2_E5 (0x1fff<<16) // FC Latency Timer Override Value. When you set the "FC Latency Timer Override Enable" in this register, the value in this field will override the FC latency timer value that the core calculates according to the PCIe specification. For more details, see "Flow Control". Note: This register field is sticky. - #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_K2_E5_SHIFT 16 - #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_K2_E5 (0x1<<31) // FC Latency Timer Override Enable. When this bit is set, the value from the "FC Latency Timer Override Value" field in this register will override the FC latency timer value that the core calculates according to the PCIe specification. Note: This register field is sticky. - #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_K2_E5_SHIFT 31 -#define PCIEIP_REG_VC_TX_ARBI_1_OFF_K2_E5 0x000740UL //Access:R DataWidth:0x20 // VC Transmit Arbitration Register 1 - #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_K2_E5 (0xff<<0) // WRR Weight for VC0. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_K2_E5_SHIFT 0 - #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_K2_E5 (0xff<<8) // WRR Weight for VC1. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_K2_E5_SHIFT 8 - #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_K2_E5 (0xff<<16) // WRR Weight for VC2. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_K2_E5_SHIFT 16 - #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_K2_E5 (0xff<<24) // WRR Weight for VC3. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_K2_E5_SHIFT 24 -#define PCIEIP_REG_VC_TX_ARBI_2_OFF_K2_E5 0x000744UL //Access:R DataWidth:0x20 // VC Transmit Arbitration Register 2 - #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_K2_E5 (0xff<<0) // WRR Weight for VC4. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_K2_E5_SHIFT 0 - #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_K2_E5 (0xff<<8) // WRR Weight for VC5. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_K2_E5_SHIFT 8 - #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_K2_E5 (0xff<<16) // WRR Weight for VC6. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_K2_E5_SHIFT 16 - #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_K2_E5 (0xff<<24) // WRR Weight for VC7. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_K2_E5_SHIFT 24 -#define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_K2_E5 0x000748UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Posted Receive Queue Control. - #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_K2_E5 (0xfff<<0) // VC0 Posted Data Credits. The number of initial posted data credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. - #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_K2_E5_SHIFT 0 - #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_K2_E5 (0xff<<12) // VC0 Posted Header Credits. The number of initial posted header credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. - #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_K2_E5_SHIFT 12 - #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED4_K2_E5 (0x1<<20) // Reserved. Note: This register field is sticky. - #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED4_K2_E5_SHIFT 20 - #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_K2_E5 (0x7<<21) // Reserved. Note: This register field is sticky. - #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_K2_E5_SHIFT 21 - #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED5_K2_E5 (0x3f<<24) // Reserved. Note: This register field is sticky. - #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED5_K2_E5_SHIFT 24 - #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_K2_E5 (0x1<<30) // TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky. - #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_K2_E5_SHIFT 30 - #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_K2_E5 (0x1<<31) // VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs have higher priority - 0: Round robin Note: This register field is sticky. - #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_K2_E5_SHIFT 31 -#define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_K2_E5 0x00074cUL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Non-Posted Receive Queue Control. - #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_K2_E5 (0xfff<<0) // VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. - #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_K2_E5_SHIFT 0 - #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_K2_E5 (0xff<<12) // VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. - #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_K2_E5_SHIFT 12 - #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_K2_E5 (0x1<<20) // Reserved. Note: This register field is sticky. - #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_K2_E5_SHIFT 20 - #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_K2_E5 (0x7<<21) // Reserved. Note: This register field is sticky. - #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_K2_E5_SHIFT 21 - #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_K2_E5 (0xff<<24) // Reserved. Note: This register field is sticky. - #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_K2_E5_SHIFT 24 -#define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_K2_E5 0x000750UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Completion Receive Queue Control. - #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_K2_E5 (0xfff<<0) // VC0 Completion Data Credits. The number of initial Completion data credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. - #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_K2_E5_SHIFT 0 - #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_K2_E5 (0xff<<12) // VC0 Completion Header Credits. The number of initial Completion header credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. - #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_K2_E5_SHIFT 12 - #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_K2_E5 (0x1<<20) // Reserved. Note: This register field is sticky. - #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_K2_E5_SHIFT 20 - #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_K2_E5 (0x7<<21) // Reserved. Note: This register field is sticky. - #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_K2_E5_SHIFT 21 - #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_K2_E5 (0xff<<24) // Reserved. Note: This register field is sticky. - #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_K2_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_ACK_TIMER_E5 0x000700UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_ACK_TIMER_RTLTL_E5 (0xffff<<0) // Round trip latency time limit. The ACK/NAK latency timer expires when it reaches this limit. This value is set correctly by the hardware out of reset or when the negotiated link width or payload size changes. If the user changes this value they should refer to the PCIe specification for the correct value. + #define PCIEIP_REG_PCIEEP_ACK_TIMER_RTLTL_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_ACK_TIMER_RTL_E5 (0xffff<<16) // Replay time limit. The replay timer expires when it reaches this limit. The PCI Express bus initiates a replay upon reception of a NAK or when the replay timer expires. This value is set correctly by the hardware out of reset or when the negotiated link width or payload size changes. If the user changes this value they should refer to the PCIe specification for the correct value. + #define PCIEIP_REG_PCIEEP_ACK_TIMER_RTL_E5_SHIFT 16 +#define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_K2 0x000700UL //Access:RW DataWidth:0x20 // Ack Latency Timer and Replay Timer Register. + #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_K2 (0xffff<<0) // Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details, see "Ack Scheduling". You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. After reset, the core updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed. The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe 3.0 specification. The limit must reflect the round trip latency from requester to completer. If there is a change in the payload size or link width, the core will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. + #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_K2_SHIFT 0 + #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_K2 (0xffff<<16) // Replay Timer Limit. The replay timer expires when it reaches this limit. The core initiates a replay upon reception of a NAK or when the replay timer expires. For more details, see "Transmit Replay". You can modify the effective timer limit with the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. After reset, the core updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed. The value is determined from Tables 3-4, 3-5, and 3-6 of the PCIe 3.0 specification. If there is a change in the payload size or link speed, the core will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. + #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_K2_SHIFT 16 +#define PCIEIP_REG_PCIEEP_OMSG_PTR_E5 0x000704UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_VENDOR_SPEC_DLLP_OFF_K2 0x000704UL //Access:RW DataWidth:0x20 // Vendor Specific DLLP Register. +#define PCIEIP_REG_PCIEEP_PORT_FLINK_E5 0x000708UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PORT_FLINK_LINK_NUM_E5 (0xff<<0) // Link number. Not used for endpoint. + #define PCIEIP_REG_PCIEEP_PORT_FLINK_LINK_NUM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PORT_FLINK_FORCED_LTSSM_E5 (0xf<<8) // Forced link command. + #define PCIEIP_REG_PCIEEP_PORT_FLINK_FORCED_LTSSM_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_PORT_FLINK_FORCE_LINK_E5 (0x1<<15) // Force link. Forces the link to the state specified by [LINK_STATE]. The force link pulse triggers link renegotiation. As the force link is a pulse, writing a 1 to it does trigger the forced link state event, even though reading it always returns a 0. + #define PCIEIP_REG_PCIEEP_PORT_FLINK_FORCE_LINK_E5_SHIFT 15 + #define PCIEIP_REG_PCIEEP_PORT_FLINK_LINK_STATE_E5 (0x3f<<16) // Link state. The link state that the PCI Express bus is forced to when bit 15 (force link) is set. State encoding: 0x0 = DETECT_QUIET. 0x1 = DETECT_ACT. 0x2 = POLL_ACTIVE. 0x3 = POLL_COMPLIANCE. 0x4 = POLL_CONFIG. 0x5 = PRE_DETECT_QUIET. 0x6 = DETECT_WAIT. 0x7 = CFG_LINKWD_START. 0x8 = CFG_LINKWD_ACEPT. 0x9 = CFG_LANENUM_WAIT. 0xA = CFG_LANENUM_ACEPT. 0xB = CFG_COMPLETE. 0xC = CFG_IDLE. 0xD = RCVRY_LOCK. 0xE = RCVRY_SPEED. 0xF = RCVRY_RCVRCFG. 0x10 = RCVRY_IDLE. 0x11 = L0. 0x12 = L0S. 0x13 = L123_SEND_EIDLE. 0x14 = L1_IDLE. 0x15 = L2_IDLE. 0x16 = L2_WAKE. 0x17 = DISABLED_ENTRY. 0x18 = DISABLED_IDLE. 0x19 = DISABLED. 0x1A = LPBK_ENTRY. 0x1B = LPBK_ACTIVE. 0x1C = LPBK_EXIT. 0x1D = LPBK_EXIT_TIMEOUT. 0x1E = HOT_RESET_ENTRY. 0x1F = HOT_RESET. + #define PCIEIP_REG_PCIEEP_PORT_FLINK_LINK_STATE_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_PORT_FLINK_DSKEW_E5 (0x1<<23) // Use the transitions from TS2 to logical idle symbol, SKP OS to logical idle symbol, and FTS sequence to SKP OS to do deskew for SRIS instead of using received SKP OS if DO_DESKEW_FOR_SRIS is set to 1. + #define PCIEIP_REG_PCIEEP_PORT_FLINK_DSKEW_E5_SHIFT 23 +#define PCIEIP_REG_PORT_FORCE_OFF_K2 0x000708UL //Access:RW DataWidth:0x20 // Port Force Link Register. + #define PCIEIP_REG_PORT_FORCE_OFF_LINK_NUM_K2 (0xff<<0) // Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky. + #define PCIEIP_REG_PORT_FORCE_OFF_LINK_NUM_K2_SHIFT 0 + #define PCIEIP_REG_PORT_FORCE_OFF_FORCED_LTSSM_K2 (0xf<<8) // Forced Link Command. The link command that the core is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky. + #define PCIEIP_REG_PORT_FORCE_OFF_FORCED_LTSSM_K2_SHIFT 8 + #define PCIEIP_REG_PORT_FORCE_OFF_FORCE_EN_K2 (0x1<<15) // Force Link. The core supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state, and to force the core to transmit a specific Link Command. Asserting this bit triggers the following actions: - Forces the LTSSM to the state specified by the Forced LTSSM State field. - Forces the core to transmit the command specified by the Forced Link Command field. This is a self-clearing register field. Reading from this register field always returns a "0". + #define PCIEIP_REG_PORT_FORCE_OFF_FORCE_EN_K2_SHIFT 15 + #define PCIEIP_REG_PORT_FORCE_OFF_LINK_STATE_K2 (0x3f<<16) // Forced LTSSM State. The LTSSM state that the core is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky. + #define PCIEIP_REG_PORT_FORCE_OFF_LINK_STATE_K2_SHIFT 16 + #define PCIEIP_REG_PORT_FORCE_OFF_CPL_SENT_COUNT_K2 (0xff<<24) // Low Power Entrance Count. The Power Management state waits for this many clock cycles for the associated completion of a CfgWr to D-state register to go low-power. This register is intended for applications that do not let the core handle a completion for configuration request to the PMCSCR register. Not used in downstream ports. Note: This register field is sticky. + #define PCIEIP_REG_PORT_FORCE_OFF_CPL_SENT_COUNT_K2_SHIFT 24 +#define PCIEIP_REG_PCIEEP_ACK_FREQ_E5 0x00070cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_ACK_FREQ_ACK_FREQ_E5 (0xff<<0) // ACK frequency. The number of pending ACKs specified here (up to 255) before sending an ACK. + #define PCIEIP_REG_PCIEEP_ACK_FREQ_ACK_FREQ_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_ACK_FREQ_N_FTS_E5 (0xff<<8) // The number of fast training sequence (FTS) ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered sets that a component can request is 255. A value of zero is not supported; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. + #define PCIEIP_REG_PCIEEP_ACK_FREQ_N_FTS_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_ACK_FREQ_N_FTS_CC_E5 (0xff<<16) // N_FTS when common clock is used. The number of fast training sequence (FTS) ordered sets to be transmitted when transitioning from L0s to L0 when common clock is used. The maximum number of FTS ordered sets that a component can request is 255. A value of zero is not supported; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. + #define PCIEIP_REG_PCIEEP_ACK_FREQ_N_FTS_CC_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_ACK_FREQ_L0EL_E5 (0x7<<24) // L0s entrance latency. Values correspond to: 0x0 = 1 ms. 0x1 = 2 ms. 0x2 = 3 ms. 0x3 = 4 ms. 0x4 = 5 ms. 0x5 = 6 ms. 0x6 or 0x7 = 7 ms. + #define PCIEIP_REG_PCIEEP_ACK_FREQ_L0EL_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_ACK_FREQ_L1EL_E5 (0x7<<27) // L1 entrance latency. Values correspond to: 0x0 = 1 ms. 0x1 = 2 ms. 0x2 = 4 ms. 0x3 = 8 ms. 0x4 = 16 ms. 0x5 = 32 ms. 0x6 or 0x7 = 64 ms. + #define PCIEIP_REG_PCIEEP_ACK_FREQ_L1EL_E5_SHIFT 27 + #define PCIEIP_REG_PCIEEP_ACK_FREQ_EASPML1_E5 (0x1<<30) // Enter ASPM L1 without receive in L0s. Allow core to enter ASPM L1 even when link partner did not go to L0s (receive is not in L0s). When not set, core goes to ASPM L1 only after idle period, during which both receive and transmit are in L0s. + #define PCIEIP_REG_PCIEEP_ACK_FREQ_EASPML1_E5_SHIFT 30 +#define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_K2 0x00070cUL //Access:RW DataWidth:0x20 // Ack Frequency and L0-L1 ASPM Control Register. + #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_K2 (0xff<<0) // Ack Frequency. The core accumulates the number of pending ACKs specified here (up to 255) before sending an ACK DLLP. - 0: Indicates that this Ack frequency control feature is turned off. The core schedules a low-priority ACK DLLP for every TLP that it receives. - 1-255: Indicates that the core will schedule a high-priority ACK after receiving this number of TLPs. It might schedule the ACK before receiving this number of TLPs, but never later. For a typical system, you do not have to modify the default setting. For more details, see "ACK/NAK Scheduling". Note: This register field is sticky. + #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_K2_SHIFT 0 + #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_K2 (0xff<<8) // N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The core does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky. + #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_K2_SHIFT 8 + #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_K2 (0xff<<16) // Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. This field is only writable (sticky) when all of the following configuration parameter equations are true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY The core does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_K2_SHIFT 16 + #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_K2 (0x7<<24) // L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky. + #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_K2_SHIFT 24 + #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_K2 (0x7<<27) // L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used, or all of the credits are infinite. Note: This register field is sticky. + #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_K2_SHIFT 27 + #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_K2 (0x1<<30) // ASPM L1 Entry Control. - 1: Core enters ASPM L1 after a period in which it has been idle. - 0: Core enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky. + #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_K2_SHIFT 30 +#define PCIEIP_REG_PCIEEP_PORT_CTL_E5 0x000710UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PORT_CTL_OMR_E5 (0x1<<0) // Other message request. When software writes a one to this bit, the PCI Express bus transmits the message contained in the other message register. + #define PCIEIP_REG_PCIEEP_PORT_CTL_OMR_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PORT_CTL_SD_E5 (0x1<<1) // Scramble disable. Setting this bit turns off data scrambling. + #define PCIEIP_REG_PCIEEP_PORT_CTL_SD_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_PORT_CTL_LE_E5 (0x1<<2) // Loopback enable. Initiate loopback mode as a master. On a 0->1 transition, the PCIe core sends TS ordered sets with the loopback bit set to cause the link partner to enter into loopback mode as a slave. Normal transmission is not possible when LE=1. To exit loopback mode, take the link through a reset sequence. + #define PCIEIP_REG_PCIEEP_PORT_CTL_LE_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_PORT_CTL_RA_E5 (0x1<<3) // Reset assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). + #define PCIEIP_REG_PCIEEP_PORT_CTL_RA_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_PORT_CTL_RESERVED4_E5 (0x1<<4) // Reserved. + #define PCIEIP_REG_PCIEEP_PORT_CTL_RESERVED4_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_PORT_CTL_DLLLE_E5 (0x1<<5) // DLL link enable. Enables link initialization. If DLL link enable = 0, the PCI Express bus does not transmit InitFC DLLPs and does not establish a link. + #define PCIEIP_REG_PCIEEP_PORT_CTL_DLLLE_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_PORT_CTL_LDIS_E5 (0x1<<6) // Link disable. Internally reserved field, do not set. + #define PCIEIP_REG_PCIEEP_PORT_CTL_LDIS_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_PORT_CTL_FLM_E5 (0x1<<7) // Fast link mode. Sets all internal timers to fast mode for simulation purposes. The scaling factor is configured by PCIEEP_TIMER_CTL[FLMSF]. If during an EEPROM load, the first word loaded is 0xFFFFFFFF, the EEPROM load is terminated and this bit is set. + #define PCIEIP_REG_PCIEEP_PORT_CTL_FLM_E5_SHIFT 7 + #define PCIEIP_REG_PCIEEP_PORT_CTL_LINK_RATE_E5 (0xf<<8) // Reserved. + #define PCIEIP_REG_PCIEEP_PORT_CTL_LINK_RATE_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_PORT_CTL_LME_E5 (0x3f<<16) // Link mode enable set as follows: 0x1 = x1. 0x3 = x2. 0x7 = x4. 0xF = x8. 0x1F = x16. 0x3F = x32 (not supported). This field indicates the maximum number of lanes supported by the PCIe port. The value can be set less than 0x1F to limit the number of lanes that the PCIe will attempt to use. If the value of 0xF set by the hardware is not desired, this field can be programmed to a smaller value (i.e. EEPROM). See also PCIEEP_LINK_CAP[MLW]. The value of this field does not indicate the number of lanes in use by the PCIe. This field sets the maximum number of lanes in the PCIe core that could be used. As per the PCIe specification, the PCIe core can negotiate a smaller link width, so all of x16, x8, x4, x2, and x1 are supported when [LME] = 0x1F, for example. + #define PCIEIP_REG_PCIEEP_PORT_CTL_LME_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_PORT_CTL_CLE_E5 (0x3<<22) // Reserved. + #define PCIEIP_REG_PCIEEP_PORT_CTL_CLE_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_PORT_CTL_BEACON_EN_E5 (0x1<<24) // Beacon enable. Internally reserved field, do not set. + #define PCIEIP_REG_PCIEEP_PORT_CTL_BEACON_EN_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_PORT_CTL_CLCRC_EN_E5 (0x1<<25) // Corrupt LCRC enable. Internally reserved field, do not set. + #define PCIEIP_REG_PCIEEP_PORT_CTL_CLCRC_EN_E5_SHIFT 25 + #define PCIEIP_REG_PCIEEP_PORT_CTL_EX_SYNCH_E5 (0x1<<26) // Extended synch. Internally reserved field, do not set. + #define PCIEIP_REG_PCIEEP_PORT_CTL_EX_SYNCH_E5_SHIFT 26 + #define PCIEIP_REG_PCIEEP_PORT_CTL_XLR_EN_E5 (0x1<<27) // Transmit lane reversible enable. Internally reserved field, do not set. + #define PCIEIP_REG_PCIEEP_PORT_CTL_XLR_EN_E5_SHIFT 27 +#define PCIEIP_REG_PORT_LINK_CTRL_OFF_K2 0x000710UL //Access:RW DataWidth:0x20 // Port Link Control Register. + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_K2 (0x1<<0) // Vendor Specific DLLP Request. When software writes a '1' to this bit, the core transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always returns a '0'. + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_K2_SHIFT 0 + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_K2 (0x1<<1) // Scramble Disable. Turns off data scrambling. Note: This register field is sticky. + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_K2_SHIFT 1 + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_K2 (0x1<<2) // Loopback Enable. Turns on loopback. For more details, see "Loopback". For M-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during Configuration.start state(initial discovery/configuration). M-PCIe doesn't support loopback mode from L0 state - only from Configuration.start. Note: This register field is sticky. + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_K2_SHIFT 2 + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_RESET_ASSERT_K2 (0x1<<3) // Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky. + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_RESET_ASSERT_K2_SHIFT 3 + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_DLL_LINK_EN_K2 (0x1<<5) // DLL Link Enable. Enables link initialization. When DLL Link Enable =0, the core does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky. + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_DLL_LINK_EN_K2_SHIFT 5 + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_DISABLE_K2 (0x1<<6) // LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky. + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_DISABLE_K2_SHIFT 6 + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_K2 (0x1<<7) // Fast Link Mode. Sets all internal timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The scaling factor is selected in FAST_LINK_SCALING_FACTOR(default : 1024) for all internal timers. Fast Link Mode can also be activated by setting the diag_ctrl_bus[2] pin to "1". For more details, see "SII Signals: Diagnostic Control". For M-PCIe, this field also affects Remain Hibern8 Time, Minimum Activate Time, and RRAP timeout. If this bit is set to '1', tRRAPInitiatorResponse is set to 1.88 ms(60 ms/32). Note: This register field is sticky. + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_K2_SHIFT 7 + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_RATE_K2 (0xf<<8) // LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky. + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_RATE_K2_SHIFT 8 + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_CAPABLE_K2 (0x3f<<16) // Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Predetermined Number of Lanes" field of the "Link Width and Speed Change Control Register". For more information, see "How to Tie Off Unused Lanes". For information on upsizing and downsizing the link width, see "Link Establishment". - 000001: x1 - 000011: x2 - 000111: x4 - 001111: x8 - 011111: x16 - 111111: x32 (not supported) This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky. + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_CAPABLE_K2_SHIFT 16 + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_BEACON_ENABLE_K2 (0x1<<24) // BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky. + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_BEACON_ENABLE_K2_SHIFT 24 + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_K2 (0x1<<25) // CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky. + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_K2_SHIFT 25 + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_K2 (0x1<<26) // EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky. + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_K2_SHIFT 26 + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_K2 (0x1<<27) // TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky. + #define PCIEIP_REG_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_K2_SHIFT 27 +#define PCIEIP_REG_PCIEEP_LANE_SKEW_E5 0x000714UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_LANE_SKEW_ILST_E5 (0xffffff<<0) // Insert lane skew for transmit (not supported for *16). Causes skew between lanes for test purposes. There are three bits per lane. The value is in units of one symbol time. For example, the value 0x2 for a lane forces a skew of two symbol times for that lane. The maximum skew value for any lane is five symbol times. + #define PCIEIP_REG_PCIEEP_LANE_SKEW_ILST_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_LANE_SKEW_FCD_E5 (0x1<<24) // Flow control disable. Prevents the PCI Express bus from sending FC DLLPs. + #define PCIEIP_REG_PCIEEP_LANE_SKEW_FCD_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_LANE_SKEW_ACK_NAK_E5 (0x1<<25) // ACK/NAK disable. Prevents the PCI Express bus from sending Ack and Nak DLLPs. + #define PCIEIP_REG_PCIEEP_LANE_SKEW_ACK_NAK_E5_SHIFT 25 + #define PCIEIP_REG_PCIEEP_LANE_SKEW_RESERVED26_E5 (0x1<<26) // Reserved. Read/Write register for future use. + #define PCIEIP_REG_PCIEEP_LANE_SKEW_RESERVED26_E5_SHIFT 26 + #define PCIEIP_REG_PCIEEP_LANE_SKEW_INUML_E5 (0xf<<27) // Set the implementation-specific number of lanes. Allowed values are: 0x0 = 1 lane. 0x1 = 2 lanes. 0x3 = 4 lanes. 0x7 = 8 lanes. 0xF = 16 lanes. + #define PCIEIP_REG_PCIEEP_LANE_SKEW_INUML_E5_SHIFT 27 + #define PCIEIP_REG_PCIEEP_LANE_SKEW_DLLD_E5 (0x1<<31) // Disable lane-to-lane deskew. Disables the internal lane-to-lane deskew logic. + #define PCIEIP_REG_PCIEEP_LANE_SKEW_DLLD_E5_SHIFT 31 +#define PCIEIP_REG_LANE_SKEW_OFF_K2 0x000714UL //Access:RW DataWidth:0x20 // Lane Skew Register. + #define PCIEIP_REG_LANE_SKEW_OFF_INSERT_LANE_SKEW_K2 (0xffffff<<0) // Insert Lane Skew for Transmit (not supported for x16). Optional feature that causes the core to insert skew between Lanes for test purposes. There are three bits per Lane. The value is in units of one symbol time. For example, the value 010b for a Lane forces a skew of two symbol times for that Lane. The maximum skew value for any Lane is 5 symbol times. Note: This register field is sticky. + #define PCIEIP_REG_LANE_SKEW_OFF_INSERT_LANE_SKEW_K2_SHIFT 0 + #define PCIEIP_REG_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_K2 (0x1<<24) // Flow Control Disable. Prevents the core from sending FC DLLPs. Note: This register field is sticky. + #define PCIEIP_REG_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_K2_SHIFT 24 + #define PCIEIP_REG_LANE_SKEW_OFF_ACK_NAK_DISABLE_K2 (0x1<<25) // Ack/Nak Disable. Prevents the core from sending ACK and NAK DLLPs. Note: This register field is sticky. + #define PCIEIP_REG_LANE_SKEW_OFF_ACK_NAK_DISABLE_K2_SHIFT 25 + #define PCIEIP_REG_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_K2 (0x1<<31) // Disable Lane-to-Lane Deskew. Causes the core to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky. + #define PCIEIP_REG_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_K2_SHIFT 31 +#define PCIEIP_REG_PCIEEP_TIMER_CTL_E5 0x000718UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_TIMER_CTL_MFUNCN_E5 (0xff<<0) // Max number of functions supported. Used for SR-IOV. + #define PCIEIP_REG_PCIEEP_TIMER_CTL_MFUNCN_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_TIMER_CTL_TMRT_E5 (0x1f<<14) // Timer modifier for replay timer. Increases the timer value for the replay timer, in increments of 64 clock cycles. + #define PCIEIP_REG_PCIEEP_TIMER_CTL_TMRT_E5_SHIFT 14 + #define PCIEIP_REG_PCIEEP_TIMER_CTL_TMANLT_E5 (0x1f<<19) // Timer modifier for ACK/NAK latency timer. Increases the timer value for the ACK/NAK latency timer, in increments of 64 clock cycles. + #define PCIEIP_REG_PCIEEP_TIMER_CTL_TMANLT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_TIMER_CTL_UPDFT_E5 (0x1f<<24) // Update frequency timer. This is an internally reserved field, do not use. + #define PCIEIP_REG_PCIEEP_TIMER_CTL_UPDFT_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_TIMER_CTL_FLMSF_E5 (0x3<<29) // Fast link timer scaling factor. Sets the scaling factor of LTSSM timer when PCIEEP_PORT_CTL[FLM] is set. 0x0 = Scaling factor is 1024 (1 ms is 1 us). 0x1 = Scaling factor is 256 (1 ms is 4 us). 0x2 = Scaling factor is 64 (1 ms is 16 us). 0x3 = Scaling factor is 16 (1 ms is 64 us). + #define PCIEIP_REG_PCIEEP_TIMER_CTL_FLMSF_E5_SHIFT 29 +#define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_K2 0x000718UL //Access:RW DataWidth:0x20 // Timer Control and Max Function Number Register. + #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_K2 (0xff<<0) // Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky. + #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_K2_SHIFT 0 + #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_K2 (0x1f<<14) // Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock cycles at Gen3 speed. A value of "0" represents no modification to the timer limit. For more details, see the REPLAY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register. At Gen3 speed, the core automatically changes the value of this field to DEFAULT_GEN3_REPLAY_ADJ. For M-PCIe, this field increases the time-out value for the replay timer in increments of 64 clock cycles at HS-Gear1, HS-Gear2, or HS-Gear3 speed. Note: This register field is sticky. + #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_K2_SHIFT 14 + #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_K2 (0x1f<<19) // Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of "0" represents no modification to the timer value. For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register. Note: This register field is sticky. + #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_K2_SHIFT 19 + #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_K2 (0x1f<<24) // UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky. + #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_K2_SHIFT 24 + #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_K2 (0x3<<29) // Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE is set to 1b. - 0: Scaling Factor is 1024 (1ms is 1us) - 1: Scaling Factor is 256 (1ms is 4us) - 2: Scaling Factor is 64 (1ms is 16us) - 3: Scaling Factor is 16 (1ms is 64us) Not used for M-PCIe. Note: This register field is sticky. + #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_K2_SHIFT 29 +#define PCIEIP_REG_PCIEEP_SYMB_TIMER_E5 0x00071cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_SKPIV_E5 (0x7ff<<0) // SKP interval value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus one between transmitting SKP ordered sets. This value is not used at Gen3 speed; the skip interval is hardcoded to 370 blocks. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_SKPIV_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_EIDLE_TIMER_E5 (0xf<<11) // an internally reserved field. Do not use. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_EIDLE_TIMER_E5_SHIFT 11 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_DFCWT_E5 (0x1<<15) // Disable FC watchdog timer. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_DFCWT_E5_SHIFT 15 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_FUN_E5 (0x1<<16) // Mask function. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_FUN_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_POIS_FILT_E5 (0x1<<17) // Mask poisoned TLP filtering. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_POIS_FILT_E5_SHIFT 17 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_BAR_MATCH_E5 (0x1<<18) // Mask BAR match filtering. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_BAR_MATCH_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CFG1_FILT_E5 (0x1<<19) // Mask type 1 configuration request filtering. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CFG1_FILT_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_LK_FILT_E5 (0x1<<20) // Mask locked request filtering. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_LK_FILT_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CPL_TAG_ERR_E5 (0x1<<21) // Mask tag error rules for received completions. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CPL_TAG_ERR_E5_SHIFT 21 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CPL_RID_ERR_E5 (0x1<<22) // Mask requester ID mismatch error for received completions. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CPL_RID_ERR_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CPL_FUN_ERR_E5 (0x1<<23) // Mask function mismatch error for received completions. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CPL_FUN_ERR_E5_SHIFT 23 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CPL_TC_ERR_E5 (0x1<<24) // Mask traffic class mismatch error for received completions. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CPL_TC_ERR_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CPL_ATTR_ERR_E5 (0x1<<25) // Mask attributes mismatch error for received completions. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CPL_ATTR_ERR_E5_SHIFT 25 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CPL_LEN_ERR_E5 (0x1<<26) // Mask length mismatch error for received completions. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CPL_LEN_ERR_E5_SHIFT 26 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_ECRC_FILT_E5 (0x1<<27) // Mask ECRC error filtering. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_ECRC_FILT_E5_SHIFT 27 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CPL_ECRC_FILT_E5 (0x1<<28) // Mask ECRC error filtering for completions. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CPL_ECRC_FILT_E5_SHIFT 28 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_MSG_CTRL_E5 (0x1<<29) // Message control. The application must not change this field. + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_MSG_CTRL_E5_SHIFT 29 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_IO_FILT_E5 (0x1<<30) // Mask filtering of received I/O requests (RC mode only). + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_IO_FILT_E5_SHIFT 30 + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CFG0_FILT_E5 (0x1<<31) // Mask filtering of received configuration requests (RC mode only). + #define PCIEIP_REG_PCIEEP_SYMB_TIMER_M_CFG0_FILT_E5_SHIFT 31 +#define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_K2 0x00071cUL //Access:RW DataWidth:0x20 // Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule. + #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_K2 (0x7ff<<0) // SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the core actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application must program this register accordingly. For example, if 1536 were programmed into this register (in a 250 MHz core), then the core actually transmits SKP ordered sets once every 1537 symbol times. The value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz core, programming the value programmed to this register should be scaled down by a factor of 2 (because one clock tick = two symbol times in this case). Note: This value is not used at Gen3 speed; the skip interval is hardcoded to 370 blocks. Note: This register field is sticky. + #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_K2_SHIFT 0 + #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_K2 (0xf<<11) // EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky. + #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_K2_SHIFT 11 + #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_K2 (0x1<<15) // Disable FC Watchdog Timer. Note: This register field is sticky. + #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_K2_SHIFT 15 + #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_K2 (0xffff<<16) // Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule. [31]: CX_FLT_MASK_RC_CFG_DISCARD - 0: For RADM RC filter to not allow CFG transaction being received - 1: For RADM RC filter to allow CFG transaction being received [30]: CX_FLT_MASK_RC_IO_DISCARD - 0: For RADM RC filter to not allow IO transaction being received - 1: For RADM RC filter to allow IO transaction being received [29]: CX_FLT_MASK_MSG_DROP - 0: Drop MSG TLP (except for Vendor MSG). Send decoded message on the SII. - 1: Do not Drop MSG (except for Vendor MSG). Send message TLPs to your application on TRGT1 and send decoded message on the SII. - The default for this bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG =1, then the default of this bit is "0" (drop message TLPs). This bit only controls message TLPs other than Vendor MSGs. Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0]. The core never passes ATS Invalidate messages to the SII interface regardless of this filter rule setting. The core passes all ATS Invalidate messages to TRGT1 (or AXI bridge master), as they are too big for the SII. [28]: CX_FLT_MASK_CPL_ECRC_DISCARD - Only used when completion queue is advertised with infinite credits and is in store-and-forward mode. - 0: Discard completions with ECRC errors - 1: Allow completions with ECRC errors to be passed up - Reserved field for SW. [27]: CX_FLT_MASK_ECRC_DISCARD - 0: Discard TLPs with ECRC errors - 1: Allow TLPs with ECRC errors to be passed up [26]: CX_FLT_MASK_CPL_LEN_MATCH - 0: Enforce length match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err - 1: MASK length match for completions [25]: CX_FLT_MASK_CPL_ATTR_MATCH - 0: Enforce attribute match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask attribute match for completions [24]: CX_FLT_MASK_CPL_TC_MATCH - 0: Enforce Traffic Class match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Traffic Class match for completions [23]: CX_FLT_MASK_CPL_FUNC_MATCH - 0: Enforce function match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask function match for completions [22]: CX_FLT_MASK_CPL_REQID_MATCH - 0: Enforce Req. Id match for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Req. Id match for completions [21]: CX_FLT_MASK_CPL_TAGERR_MATCH - 0: Enforce Tag Error Rules for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca - 1: Mask Tag Error Rules for completions [20]: CX_FLT_MASK_LOCKED_RD_AS_UR - 0: Treat locked Read TLPs as UR for EP; Supported for RC - 1: Treat locked Read TLPs as Supported for EP; UR for RC [19]: CX_FLT_MASK_CFG_TYPE1_RE_AS_UR - 0: Treat CFG type1 TLPs as UR for EP; Supported for RC - 1: Treat CFG type1 TLPs as Supported for EP; UR for RC - When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config requests if the EP consumes more than one bus number. [18]: CX_FLT_MASK_UR_OUTSIDE_BAR - 0: Treat out-of-bar TLPs as UR - 1: Do not treat out-of-bar TLPs as UR [17]: CX_FLT_MASK_UR_POIS - 0: Treat poisoned request TLPs as UR - 1: Do not treat poisoned request TLPs as UR - The native core always passes poisoned completions to your application except when you are using the DMA read channel. [16]: CX_FLT_MASK_UR_FUNC_MISMATCH - 0: Treat Function MisMatched TLPs as UR - 1: Do not treat Function MisMatched TLPs as UR Note: This register field is sticky. + #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_K2_SHIFT 16 +#define PCIEIP_REG_PCIEEP_FILT_MSK2_E5 0x000720UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_FILT_MSK2_M_VEND0_DRP_E5 (0x1<<0) // Mask vendor MSG type 0 dropped with UR error reporting. + #define PCIEIP_REG_PCIEEP_FILT_MSK2_M_VEND0_DRP_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_FILT_MSK2_M_VEND1_DRP_E5 (0x1<<1) // Mask vendor MSG type 1 dropped silently. + #define PCIEIP_REG_PCIEEP_FILT_MSK2_M_VEND1_DRP_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_FILT_MSK2_M_DABORT_4UCPL_E5 (0x1<<2) // Mask DLLP abort for unexpected CPL. + #define PCIEIP_REG_PCIEEP_FILT_MSK2_M_DABORT_4UCPL_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_FILT_MSK2_M_HANDLE_FLUSH_E5 (0x1<<3) // Mask core filter to handle flush request. + #define PCIEIP_REG_PCIEEP_FILT_MSK2_M_HANDLE_FLUSH_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_FILT_MSK2_M_LN_VEND1_DROP_E5 (0x1<<4) // Mask LN messages dropped silently. + #define PCIEIP_REG_PCIEEP_FILT_MSK2_M_LN_VEND1_DROP_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_FILT_MSK2_M_UNMASK_UR_POIS_E5 (0x1<<5) // Disable unmask UR Poison with TRGT0 destination. + #define PCIEIP_REG_PCIEEP_FILT_MSK2_M_UNMASK_UR_POIS_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_FILT_MSK2_M_UNMASK_TD_E5 (0x1<<6) // Disable unmask TD bit. + #define PCIEIP_REG_PCIEEP_FILT_MSK2_M_UNMASK_TD_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_FILT_MSK2_M_PRS_E5 (0x1<<7) // Mask PRS messages dropped silently. + #define PCIEIP_REG_PCIEEP_FILT_MSK2_M_PRS_E5_SHIFT 7 + #define PCIEIP_REG_PCIEEP_FILT_MSK2_RESERVED31_8_E5 (0xffffff<<8) // Reserved. + #define PCIEIP_REG_PCIEEP_FILT_MSK2_RESERVED31_8_E5_SHIFT 8 +#define PCIEIP_REG_FILTER_MASK_2_OFF_K2 0x000720UL //Access:RW DataWidth:0x20 // Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule. +#define PCIEIP_REG_PCIEEP_DBG0_E5 0x000728UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PL_DEBUG0_OFF_K2 0x000728UL //Access:R DataWidth:0x20 // Debug Register 0 +#define PCIEIP_REG_PCIEEP_DBG1_E5 0x00072cUL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PL_DEBUG1_OFF_K2 0x00072cUL //Access:R DataWidth:0x20 // Debug Register 1 +#define PCIEIP_REG_PCIEEP_P_XMIT_CREDIT_E5 0x000730UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_P_XMIT_CREDIT_TPDFCC_E5 (0xfff<<0) // Transmit posted data FC credits. The posted data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. + #define PCIEIP_REG_PCIEEP_P_XMIT_CREDIT_TPDFCC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_P_XMIT_CREDIT_TPHFCC_E5 (0xff<<12) // Transmit posted header FC credits. The posted header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. + #define PCIEIP_REG_PCIEEP_P_XMIT_CREDIT_TPHFCC_E5_SHIFT 12 +#define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_K2 0x000730UL //Access:R DataWidth:0x20 // Transmit Posted FC Credit Status + #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_K2 (0xfff<<0) // Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]. + #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_K2_SHIFT 0 + #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_K2 (0xff<<12) // Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]. + #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_K2_SHIFT 12 +#define PCIEIP_REG_PCIEEP_NP_XMIT_CREDIT_E5 0x000734UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_NP_XMIT_CREDIT_TCDFCC_E5 (0xfff<<0) // Transmit nonposted data FC credits. The nonposted data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. + #define PCIEIP_REG_PCIEEP_NP_XMIT_CREDIT_TCDFCC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_NP_XMIT_CREDIT_TCHFCC_E5 (0xff<<12) // Transmit nonposted header FC credits. The nonposted header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. + #define PCIEIP_REG_PCIEEP_NP_XMIT_CREDIT_TCHFCC_E5_SHIFT 12 +#define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_K2 0x000734UL //Access:R DataWidth:0x20 // Transmit Non-Posted FC Credit Status + #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_K2 (0xfff<<0) // Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]. + #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_K2_SHIFT 0 + #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_K2 (0xff<<12) // Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]. + #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_K2_SHIFT 12 +#define PCIEIP_REG_PCIEEP_C_XMIT_CREDIT_E5 0x000738UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_C_XMIT_CREDIT_TCDFCC_E5 (0xfff<<0) // Transmit completion data FC credits. The completion data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. + #define PCIEIP_REG_PCIEEP_C_XMIT_CREDIT_TCDFCC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_C_XMIT_CREDIT_TCHFCC_E5 (0xff<<12) // Transmit completion header FC credits. The completion header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. + #define PCIEIP_REG_PCIEEP_C_XMIT_CREDIT_TCHFCC_E5_SHIFT 12 +#define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_K2 0x000738UL //Access:R DataWidth:0x20 // Transmit Completion FC Credit Status + #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_K2 (0xfff<<0) // Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]. + #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_K2_SHIFT 0 + #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_K2 (0xff<<12) // Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF]. + #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_K2_SHIFT 12 +#define PCIEIP_REG_PCIEEP_QUEUE_STATUS_E5 0x00073cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_RTLPFCCNR_E5 (0x1<<0) // Received TLP FC credits not returned. Indicates that the PCI Express bus has sent a TLP but has not yet received an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the link. + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_RTLPFCCNR_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_TRBNE_E5 (0x1<<1) // Transmit retry buffer not empty. Indicates that there is data in the transmit retry buffer. + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_TRBNE_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_RQNE_E5 (0x1<<2) // Received queue not empty. Indicates there is data in one or more of the receive buffers. + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_RQNE_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_RQOF_E5 (0x1<<3) // Receive credit queue overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue. + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_RQOF_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_RSQNE_E5 (0x1<<13) // Receive serialization queue not empty. Indicates there is data in the serialization queue. + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_RSQNE_E5_SHIFT 13 + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_RSQWE_E5 (0x1<<14) // Receive serialization queue write error. Indicates insufficient buffer space available to write to the serialization queue. + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_RSQWE_E5_SHIFT 14 + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_RSQRE_E5 (0x1<<15) // Receive serialization queue read error. Indicates the serialization queue has attempted to read an incorrectly formatted TLP. + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_RSQRE_E5_SHIFT 15 + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_FCLTOV_E5 (0x1fff<<16) // FC latency timer override value. When you set PCIEEP_QUEUE_STATUS[FCLTOE], the value in this field will override the FC latency timer value that the core calculates according to the PCIe specification. + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_FCLTOV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_FCLTOE_E5 (0x1<<31) // FC latency timer override enable. When this bit is set, the value in PCIEEP_QUEUE_STATUS[FCLTOV] will override the FC latency timer value that the core calculates according to the PCIe specification. + #define PCIEIP_REG_PCIEEP_QUEUE_STATUS_FCLTOE_E5_SHIFT 31 +#define PCIEIP_REG_QUEUE_STATUS_OFF_K2 0x00073cUL //Access:RW DataWidth:0x20 // Queue Status + #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_K2 (0x1<<0) // Received TLP FC Credits Not Returned. Indicates that the core has sent a TLP but has not yet received an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the link. + #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_K2_SHIFT 0 + #define PCIEIP_REG_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_K2 (0x1<<1) // Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer. + #define PCIEIP_REG_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_K2_SHIFT 1 + #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_K2 (0x1<<2) // Received Queue Not Empty. Indicates there is data in one or more of the receive buffers. + #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_K2_SHIFT 2 + #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_K2 (0x1fff<<16) // FC Latency Timer Override Value. When you set the "FC Latency Timer Override Enable" in this register, the value in this field will override the FC latency timer value that the core calculates according to the PCIe specification. For more details, see "Flow Control". Note: This register field is sticky. + #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_K2_SHIFT 16 + #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_K2 (0x1<<31) // FC Latency Timer Override Enable. When this bit is set, the value from the "FC Latency Timer Override Value" field in this register will override the FC latency timer value that the core calculates according to the PCIe specification. Note: This register field is sticky. + #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_K2_SHIFT 31 +#define PCIEIP_REG_PCIEEP_XMIT_ARB1_E5 0x000740UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_XMIT_ARB1_WRR_VC0_E5 (0xff<<0) // WRR weight for VC0. + #define PCIEIP_REG_PCIEEP_XMIT_ARB1_WRR_VC0_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_XMIT_ARB1_WRR_VC1_E5 (0xff<<8) // WRR weight for VC1. + #define PCIEIP_REG_PCIEEP_XMIT_ARB1_WRR_VC1_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_XMIT_ARB1_WRR_VC2_E5 (0xff<<16) // WRR weight for VC2. + #define PCIEIP_REG_PCIEEP_XMIT_ARB1_WRR_VC2_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_XMIT_ARB1_WRR_VC3_E5 (0xff<<24) // WRR weight for VC3. + #define PCIEIP_REG_PCIEEP_XMIT_ARB1_WRR_VC3_E5_SHIFT 24 +#define PCIEIP_REG_VC_TX_ARBI_1_OFF_K2 0x000740UL //Access:R DataWidth:0x20 // VC Transmit Arbitration Register 1 + #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_K2 (0xff<<0) // WRR Weight for VC0. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_K2_SHIFT 0 + #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_K2 (0xff<<8) // WRR Weight for VC1. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_K2_SHIFT 8 + #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_K2 (0xff<<16) // WRR Weight for VC2. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_K2_SHIFT 16 + #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_K2 (0xff<<24) // WRR Weight for VC3. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_K2_SHIFT 24 +#define PCIEIP_REG_PCIEEP_XMIT_ARB2_E5 0x000744UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_XMIT_ARB2_WRR_VC4_E5 (0xff<<0) // WRR weight for VC4. + #define PCIEIP_REG_PCIEEP_XMIT_ARB2_WRR_VC4_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_XMIT_ARB2_WRR_VC5_E5 (0xff<<8) // WRR weight for VC5. + #define PCIEIP_REG_PCIEEP_XMIT_ARB2_WRR_VC5_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_XMIT_ARB2_WRR_VC6_E5 (0xff<<16) // WRR weight for VC6. + #define PCIEIP_REG_PCIEEP_XMIT_ARB2_WRR_VC6_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_XMIT_ARB2_WRR_VC7_E5 (0xff<<24) // WRR weight for VC7. + #define PCIEIP_REG_PCIEEP_XMIT_ARB2_WRR_VC7_E5_SHIFT 24 +#define PCIEIP_REG_VC_TX_ARBI_2_OFF_K2 0x000744UL //Access:R DataWidth:0x20 // VC Transmit Arbitration Register 2 + #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_K2 (0xff<<0) // WRR Weight for VC4. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_K2_SHIFT 0 + #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_K2 (0xff<<8) // WRR Weight for VC5. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_K2_SHIFT 8 + #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_K2 (0xff<<16) // WRR Weight for VC6. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_K2_SHIFT 16 + #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_K2 (0xff<<24) // WRR Weight for VC7. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_K2_SHIFT 24 +#define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_E5 0x000748UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_DATA_CREDITS_E5 (0xfff<<0) // VC0 posted data credits. The number of initial posted data credits for VC0, used for all receive queue buffer configurations. This field is writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_DATA_CREDITS_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_HEADER_CREDITS_E5 (0xff<<12) // VC0 posted header credits. The number of initial posted header credits for VC0, used for all receive queue buffer configurations. This field is writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_HEADER_CREDITS_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_RESERVED20_E5 (0x1<<20) // Reserved. + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_RESERVED20_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_QUEUE_MODE_E5 (0x7<<21) // VC0 posted TLP queue mode. The operating mode of the posted receive queue for VC0, used only in the segmented-buffer configuration, writable through PEM()_CFG_WR. However, the application must not change this field. Only one bit can be set at a time: _ Bit 23 = Bypass. _ Bit 22 = Cut-through. _ Bit 21 = Store-and-forward. + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_QUEUE_MODE_E5_SHIFT 21 + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_VC0_PHS_E5 (0x3<<24) // VC0 scale posted header credits. + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_VC0_PHS_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_VC0_PDS_E5 (0x3<<26) // VC0 scale posted data credits. + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_VC0_PDS_E5_SHIFT 26 + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_RESERVED29_28_E5 (0x3<<28) // Reserved. + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_RESERVED29_28_E5_SHIFT 28 + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_TYPE_ORDERING_E5 (0x1<<30) // TLP type ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration, writable through PEM()_CFG_WR: 0 = Strict ordering for received TLPs: Posted, then completion, then NonPosted. 1 = Ordering of received TLPs follows the rules in PCI Express Base Specification. The application must not change this field. + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_TYPE_ORDERING_E5_SHIFT 30 + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_RX_QUEUE_ORDER_E5 (0x1<<31) // VC ordering for receive queues. Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration, writable through PEM()_CFG_WR: 0 = Round robin. 1 = Strict ordering, higher numbered VCs have higher priority. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_P_RCV_CREDIT_RX_QUEUE_ORDER_E5_SHIFT 31 +#define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_K2 0x000748UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Posted Receive Queue Control. + #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_K2 (0xfff<<0) // VC0 Posted Data Credits. The number of initial posted data credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. + #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_K2_SHIFT 0 + #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_K2 (0xff<<12) // VC0 Posted Header Credits. The number of initial posted header credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. + #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_K2_SHIFT 12 + #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED4_K2 (0x1<<20) // Reserved. Note: This register field is sticky. + #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED4_K2_SHIFT 20 + #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_K2 (0x7<<21) // Reserved. Note: This register field is sticky. + #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_K2_SHIFT 21 + #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED5_K2 (0x3f<<24) // Reserved. Note: This register field is sticky. + #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED5_K2_SHIFT 24 + #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_K2 (0x1<<30) // TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky. + #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_K2_SHIFT 30 + #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_K2 (0x1<<31) // VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration: - 1: Strict ordering, higher numbered VCs have higher priority - 0: Round robin Note: This register field is sticky. + #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_K2_SHIFT 31 +#define PCIEIP_REG_PCIEEP_NP_RCV_CREDIT_E5 0x00074cUL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_NP_RCV_CREDIT_DATA_CREDITS_E5 (0xfff<<0) // VC0 nonposted data credits. The number of initial nonposted data credits for VC0, used for all receive queue buffer configurations. This field is writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_NP_RCV_CREDIT_DATA_CREDITS_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_NP_RCV_CREDIT_HEADER_CREDITS_E5 (0xff<<12) // VC0 nonposted header credits. The number of initial nonposted header credits for VC0, used for all receive queue buffer configurations. This field is writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_NP_RCV_CREDIT_HEADER_CREDITS_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_NP_RCV_CREDIT_RESERVED20_E5 (0x1<<20) // Reserved. + #define PCIEIP_REG_PCIEEP_NP_RCV_CREDIT_RESERVED20_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_NP_RCV_CREDIT_QUEUE_MODE_E5 (0x7<<21) // VC0 nonposted TLP queue mode. The operating mode of the nonposted receive queue for VC0, used only in the segmented-buffer configuration, writable through PEM()_CFG_WR. Only one bit can be set at a time: _ Bit 23 = Bypass. _ Bit 22 = Cut-through. _ Bit 21 = Store-and-forward. The application must not change this field. + #define PCIEIP_REG_PCIEEP_NP_RCV_CREDIT_QUEUE_MODE_E5_SHIFT 21 + #define PCIEIP_REG_PCIEEP_NP_RCV_CREDIT_VC0_NPHS_E5 (0x3<<24) // VC0 scale non-posted header credits. + #define PCIEIP_REG_PCIEEP_NP_RCV_CREDIT_VC0_NPHS_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_NP_RCV_CREDIT_VC0_NPDS_E5 (0x3<<26) // VC0 scale non-posted data credits. + #define PCIEIP_REG_PCIEEP_NP_RCV_CREDIT_VC0_NPDS_E5_SHIFT 26 + #define PCIEIP_REG_PCIEEP_NP_RCV_CREDIT_RESERVED31_28_E5 (0xf<<28) // Reserved. + #define PCIEIP_REG_PCIEEP_NP_RCV_CREDIT_RESERVED31_28_E5_SHIFT 28 +#define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_K2 0x00074cUL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Non-Posted Receive Queue Control. + #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_K2 (0xfff<<0) // VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. + #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_K2_SHIFT 0 + #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_K2 (0xff<<12) // VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. + #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_K2_SHIFT 12 + #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_K2 (0x1<<20) // Reserved. Note: This register field is sticky. + #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_K2_SHIFT 20 + #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_K2 (0x7<<21) // Reserved. Note: This register field is sticky. + #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_K2_SHIFT 21 + #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_K2 (0xff<<24) // Reserved. Note: This register field is sticky. + #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_K2_SHIFT 24 +#define PCIEIP_REG_PCIEEP_C_RCV_CREDIT_E5 0x000750UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_C_RCV_CREDIT_DATA_CREDITS_E5 (0xfff<<0) // VC0 completion data credits. The number of initial completion data credits for VC0, used for all receive queue buffer configurations. This field is writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_C_RCV_CREDIT_DATA_CREDITS_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_C_RCV_CREDIT_HEADER_CREDITS_E5 (0xff<<12) // VC0 completion header credits. The number of initial completion header credits for VC0, used for all receive queue buffer configurations. This field is writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_REG_PCIEEP_C_RCV_CREDIT_HEADER_CREDITS_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_C_RCV_CREDIT_RESERVED20_E5 (0x1<<20) // Reserved. + #define PCIEIP_REG_PCIEEP_C_RCV_CREDIT_RESERVED20_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_C_RCV_CREDIT_QUEUE_MODE_E5 (0x7<<21) // VC0 completion TLP queue mode. The operating mode of the completion receive queue for VC0, used only in the segmented-buffer configuration, writable through PEM()_CFG_WR. Only one bit can be set at a time: _ Bit 23 = Bypass. _ Bit 22 = Cut-through. _ Bit 21 = Store-and-forward. The application must not change this field. + #define PCIEIP_REG_PCIEEP_C_RCV_CREDIT_QUEUE_MODE_E5_SHIFT 21 + #define PCIEIP_REG_PCIEEP_C_RCV_CREDIT_VC0_CHS_E5 (0x3<<24) // VC0 scale completion header credits. + #define PCIEIP_REG_PCIEEP_C_RCV_CREDIT_VC0_CHS_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_C_RCV_CREDIT_VC0_CDS_E5 (0x3<<26) // VC0 scale completion data credits. + #define PCIEIP_REG_PCIEEP_C_RCV_CREDIT_VC0_CDS_E5_SHIFT 26 + #define PCIEIP_REG_PCIEEP_C_RCV_CREDIT_RESERVED31_28_E5 (0xf<<28) // Reserved. + #define PCIEIP_REG_PCIEEP_C_RCV_CREDIT_RESERVED31_28_E5_SHIFT 28 +#define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_K2 0x000750UL //Access:RW DataWidth:0x20 // Segmented-Buffer VC0 Completion Receive Queue Control. + #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_K2 (0xfff<<0) // VC0 Completion Data Credits. The number of initial Completion data credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. + #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_K2_SHIFT 0 + #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_K2 (0xff<<12) // VC0 Completion Header Credits. The number of initial Completion header credits for VC0, used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. + #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_K2_SHIFT 12 + #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_K2 (0x1<<20) // Reserved. Note: This register field is sticky. + #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_K2_SHIFT 20 + #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_K2 (0x7<<21) // Reserved. Note: This register field is sticky. + #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_K2_SHIFT 21 + #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_K2 (0xff<<24) // Reserved. Note: This register field is sticky. + #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_K2_SHIFT 24 #define PCIEIP_REG_TL_CONTROL_0_BB 0x000800UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_TL_CONTROL_0_PM_TL_IGNORE_REQS_BB (0x1<<0) // When set the TL TX does not send out pending requests if PM requests to block TLPS. By default TL will send all pending dma requests and completions when PM requests it to prepare for leaving L0 before asserting tlp blocked. When this bit is set , if min credits are available, TL indicates to PM that TLP is blocked and does not send out any pending dma requests or completions. #define PCIEIP_REG_TL_CONTROL_0_PM_TL_IGNORE_REQS_BB_SHIFT 0 @@ -3658,25 +5841,44 @@ #define PCIEIP_REG_TL_CONTROL_2_TTX_UNKNOWNTYPE_ERR_MASK_BB_SHIFT 29 #define PCIEIP_REG_TL_CONTROL_2_UNUSED_1_BB (0x3<<30) // #define PCIEIP_REG_TL_CONTROL_2_UNUSED_1_BB_SHIFT 30 -#define PCIEIP_REG_GEN2_CTRL_OFF_K2_E5 0x00080cUL //Access:RW DataWidth:0x20 // Link Width and Speed Change Control Register. - #define PCIEIP_REG_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_K2_E5 (0xff<<0) // Sets the Number of Fast Training Sequences (N_FTS) that the core advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a low power state. The number should be provided by the PHY vendor. Do not set N_FTS to zero; doing so can cause the LTSSM to go into the recovery state when exiting from L0s. This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_K2_E5_SHIFT 0 - #define PCIEIP_REG_GEN2_CTRL_OFF_NUM_OF_LANES_K2_E5 (0x1f<<8) // Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver. Indicates the number of lanes to check for exit from Electrical Idle in Polling.Active and L2.Idle. It is possible that the LTSSM might detect a receiver on a bad or broken lane during the Detect Substate. However, it is also possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being configured. This value is referred to as the "Predetermined Number of Lanes" in section 4.2.6.2.1 of the PCI Express Base 3.0 Specification, revision 1.0. Encoding is as follows: - 0x01: 1 lane - 0x02: 2 lanes - 0x03: 3 lanes - .. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Link Mode Enable" field of PORT_LINK_CTRL_OFF. The value in this register is normally the same as the encoded value in PORT_LINK_CTRL_OFF. If you find that one of your used lanes is bad then you must reduce the value in this register. For more information, see "How to Tie Off Unused Lanes." For information on upsizing and downsizing the link width, see "Link Establishment." This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_GEN2_CTRL_OFF_NUM_OF_LANES_K2_E5_SHIFT 8 - #define PCIEIP_REG_GEN2_CTRL_OFF_PRE_DET_LANE_K2_E5 (0x7<<13) // Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. Allowed values are: - 3'b000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1, depending on which lane is detected - 3'b001: Connect logical Lane0 to physical lane 1 - 3'b010: Connect logical Lane0 to physical lane 3 - 3'b011: Connect logical Lane0 to physical lane 7 - 3'b100: Connect logical Lane0 to physical lane 15 This field is used to restrict the receiver detect procedure to a particular lane when the default detect and polling procedure performed on all lanes cannot be successful. A notable example of when it is useful to program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state. Note: This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_GEN2_CTRL_OFF_PRE_DET_LANE_K2_E5_SHIFT 13 - #define PCIEIP_REG_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_K2_E5 (0x1<<16) // Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the core. For more details, see the 'Lane Reversal' appendix in the Databook. This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_K2_E5_SHIFT 16 - #define PCIEIP_REG_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_K2_E5 (0x1<<17) // Directed Speed Change. Writing "1" to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs, the core will clear the contents of this field; and a read to this field by your software will return a "0". To manually initiate the speed change: - Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this field - Assert this field If you set the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to "1", then the speed change is initiated automatically after link up, and the core clears the contents of this field. If you want to prevent this automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2 register (LINK_CONTROL2_LINK_STATUS2_OFF . PCIE_CAP_TARGET_LINK_SPEED) through the DBI before link up. This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_K2_E5_SHIFT 17 - #define PCIEIP_REG_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_K2_E5 (0x1<<18) // Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The core drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_K2_E5_SHIFT 18 - #define PCIEIP_REG_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_K2_E5 (0x1<<19) // Config Tx Compliance Receive Bit. When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to "1"). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_K2_E5_SHIFT 19 - #define PCIEIP_REG_GEN2_CTRL_OFF_SEL_DEEMPHASIS_K2_E5 (0x1<<20) // Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_GEN2_CTRL_OFF_SEL_DEEMPHASIS_K2_E5_SHIFT 20 - #define PCIEIP_REG_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_K2_E5 (0x1<<21) // Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a "1" value on RxElecIdle instead of looking for a "0" on RxValid. If the PHY fails to deassert the RxValid signal in Recovery.Speed or Loopback.Active (because of corrupted EIOS for example), then EI cannot be inferred successfully in the core by just detecting the condition RxValid=0. - 0: Use RxElecIdle signal to infer Electrical Idle - 1: Use RxValid signal to infer Electrical Idle Note: This register field is sticky. - #define PCIEIP_REG_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_K2_E5_SHIFT 21 +#define PCIEIP_REG_PCIEEP_GEN2_PORT_E5 0x00080cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_GEN2_PORT_N_FTS_E5 (0xff<<0) // Sets the number of fast training sequences (N_FTS) that the core advertises as its N_FTS during GEN2 Link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a low power state. Do not set [N_FTS] to zero; doing so can cause the LTSSM to go into the recovery state when exiting from L0s. + #define PCIEIP_REG_PCIEEP_GEN2_PORT_N_FTS_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_GEN2_PORT_NLANES_E5 (0x1f<<8) // Predetermined number of lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver. Indicates the number of lanes to check for exit from electrical idle in Polling.Active and L2.Idle. 0x1 = 1 lane. 0x2 = 2 lanes. 0x3 = 3 lanes. _ ... 0x10 = 16 lanes. 0x11-0x1F = Reserved. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change PCIEEP_PORT_CTL[LME]. + #define PCIEIP_REG_PCIEEP_GEN2_PORT_NLANES_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_GEN2_PORT_PDETLANE_E5 (0x7<<13) // Predetermined lane for auto flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in detect. 0x0 = Reserved. 0x1 = Connect logical Lane0 to physical lane 1. 0x2 = Connect logical Lane0 to physical lane 3. 0x3 = Connect logical Lane0 to physical lane 7. 0x4 = Connect logical Lane0 to physical lane 15. 0x5 - 0x7 = Reserved. + #define PCIEIP_REG_PCIEEP_GEN2_PORT_PDETLANE_E5_SHIFT 13 + #define PCIEIP_REG_PCIEEP_GEN2_PORT_ALANEFLIP_E5 (0x1<<16) // Enable auto flipping of the lanes. + #define PCIEIP_REG_PCIEEP_GEN2_PORT_ALANEFLIP_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_GEN2_PORT_DSC_E5 (0x1<<17) // Directed speed change. A write of one initiates a speed change. When the speed change occurs, the controller will clear the contents of this field. + #define PCIEIP_REG_PCIEEP_GEN2_PORT_DSC_E5_SHIFT 17 + #define PCIEIP_REG_PCIEEP_GEN2_PORT_CPYTS_E5 (0x1<<18) // Config PHY TX swing. Indicates the voltage level that the PHY should drive. When set to one, indicates low swing. When set to 0, indicates full swing. + #define PCIEIP_REG_PCIEEP_GEN2_PORT_CPYTS_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_GEN2_PORT_CTCRB_E5 (0x1<<19) // Config TX compliance receive bit. When set to one, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to one). + #define PCIEIP_REG_PCIEEP_GEN2_PORT_CTCRB_E5_SHIFT 19 + #define PCIEIP_REG_PCIEEP_GEN2_PORT_S_D_E_E5 (0x1<<20) // Set the deemphasis level for upstream ports. 0 = -6 dB. 1 = -3.5 dB. + #define PCIEIP_REG_PCIEEP_GEN2_PORT_S_D_E_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_GEN2_PORT_GEN1_EI_INF_E5 (0x1<<21) // Electrical idle inference mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a one value on RxElecIdle instead of looking for a zero on RxValid. If the PHY fails to deassert the RxValid signal in Recovery.Speed or Loopback.Active (because of corrupted EIOS for example), then EI cannot be inferred successfully in the controller by just detecting the condition RxValid=0. 0 = Use RxElecIdle signal to infer electrical idle. 1 = Use RxValid signal to infer electrical idle. + #define PCIEIP_REG_PCIEEP_GEN2_PORT_GEN1_EI_INF_E5_SHIFT 21 +#define PCIEIP_REG_GEN2_CTRL_OFF_K2 0x00080cUL //Access:RW DataWidth:0x20 // Link Width and Speed Change Control Register. + #define PCIEIP_REG_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_K2 (0xff<<0) // Sets the Number of Fast Training Sequences (N_FTS) that the core advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a low power state. The number should be provided by the PHY vendor. Do not set N_FTS to zero; doing so can cause the LTSSM to go into the recovery state when exiting from L0s. This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_GEN2_CTRL_OFF_FAST_TRAINING_SEQ_K2_SHIFT 0 + #define PCIEIP_REG_GEN2_CTRL_OFF_NUM_OF_LANES_K2 (0x1f<<8) // Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver. Indicates the number of lanes to check for exit from Electrical Idle in Polling.Active and L2.Idle. It is possible that the LTSSM might detect a receiver on a bad or broken lane during the Detect Substate. However, it is also possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being configured. This value is referred to as the "Predetermined Number of Lanes" in section 4.2.6.2.1 of the PCI Express Base 3.0 Specification, revision 1.0. Encoding is as follows: - 0x01: 1 lane - 0x02: 2 lanes - 0x03: 3 lanes - .. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Link Mode Enable" field of PORT_LINK_CTRL_OFF. The value in this register is normally the same as the encoded value in PORT_LINK_CTRL_OFF. If you find that one of your used lanes is bad then you must reduce the value in this register. For more information, see "How to Tie Off Unused Lanes." For information on upsizing and downsizing the link width, see "Link Establishment." This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_GEN2_CTRL_OFF_NUM_OF_LANES_K2_SHIFT 8 + #define PCIEIP_REG_GEN2_CTRL_OFF_PRE_DET_LANE_K2 (0x7<<13) // Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. Allowed values are: - 3'b000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1, depending on which lane is detected - 3'b001: Connect logical Lane0 to physical lane 1 - 3'b010: Connect logical Lane0 to physical lane 3 - 3'b011: Connect logical Lane0 to physical lane 7 - 3'b100: Connect logical Lane0 to physical lane 15 This field is used to restrict the receiver detect procedure to a particular lane when the default detect and polling procedure performed on all lanes cannot be successful. A notable example of when it is useful to program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state. Note: This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_GEN2_CTRL_OFF_PRE_DET_LANE_K2_SHIFT 13 + #define PCIEIP_REG_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_K2 (0x1<<16) // Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the core. For more details, see the 'Lane Reversal' appendix in the Databook. This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_K2_SHIFT 16 + #define PCIEIP_REG_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_K2 (0x1<<17) // Directed Speed Change. Writing "1" to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs, the core will clear the contents of this field; and a read to this field by your software will return a "0". To manually initiate the speed change: - Write to LINK_CONTROL2_LINK_STATUS2_REG . PCIE_CAP_TARGET_LINK_SPEED in the local device - Deassert this field - Assert this field If you set the default of this field using the DEFAULT_GEN2_SPEED_CHANGE configuration parameter to "1", then the speed change is initiated automatically after link up, and the core clears the contents of this field. If you want to prevent this automatic speed change, then write a lower speed value to the Target Link Speed field of the Link Control 2 register (LINK_CONTROL2_LINK_STATUS2_OFF . PCIE_CAP_TARGET_LINK_SPEED) through the DBI before link up. This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_GEN2_CTRL_OFF_DIRECT_SPEED_CHANGE_K2_SHIFT 17 + #define PCIEIP_REG_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_K2 (0x1<<18) // Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The core drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_GEN2_CTRL_OFF_CONFIG_PHY_TX_CHANGE_K2_SHIFT 18 + #define PCIEIP_REG_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_K2 (0x1<<19) // Config Tx Compliance Receive Bit. When set to 1, signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to "1"). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_GEN2_CTRL_OFF_CONFIG_TX_COMP_RX_K2_SHIFT 19 + #define PCIEIP_REG_GEN2_CTRL_OFF_SEL_DEEMPHASIS_K2 (0x1<<20) // Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_GEN2_CTRL_OFF_SEL_DEEMPHASIS_K2_SHIFT 20 + #define PCIEIP_REG_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_K2 (0x1<<21) // Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a "1" value on RxElecIdle instead of looking for a "0" on RxValid. If the PHY fails to deassert the RxValid signal in Recovery.Speed or Loopback.Active (because of corrupted EIOS for example), then EI cannot be inferred successfully in the core by just detecting the condition RxValid=0. - 0: Use RxElecIdle signal to infer Electrical Idle - 1: Use RxValid signal to infer Electrical Idle Note: This register field is sticky. + #define PCIEIP_REG_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_K2_SHIFT 21 #define PCIEIP_REG_TL_CONTROL_3_BB 0x00080cUL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_TL_CONTROL_3_EN_CMPL_RETRY_BB (0x1<<0) // Enable Completion retry upon completion timeout. (feature is not supported, but bit is defined for posterity.) #define PCIEIP_REG_TL_CONTROL_3_EN_CMPL_RETRY_BB_SHIFT 0 @@ -3698,13 +5900,15 @@ #define PCIEIP_REG_TL_CONTROL_3_OVERRIDE_L1_ENTRY_BB_SHIFT 16 #define PCIEIP_REG_TL_CONTROL_3_MAX_INTER_L1_GAP_BB (0x7fff<<17) // Programmable delay to prevent link from re-entering L1, when link comes out of L1 into L0 due to PM_PME. The default value corresponds to 8 us and uses pulse_1us signal to count this value #define PCIEIP_REG_TL_CONTROL_3_MAX_INTER_L1_GAP_BB_SHIFT 17 -#define PCIEIP_REG_PHY_STATUS_OFF_K2_E5 0x000810UL //Access:R DataWidth:0x20 // PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins. +#define PCIEIP_REG_PCIEEP_PHY_STATUS_E5 0x000810UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PHY_STATUS_OFF_K2 0x000810UL //Access:R DataWidth:0x20 // PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins. #define PCIEIP_REG_TL_CONTROL_4_BB 0x000810UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PCIEIP_REG_TL_CONTROL_4_RESERVED2_BB (0xffff<<0) // For ECO/CTRL bits are reset o hard_reset #define PCIEIP_REG_TL_CONTROL_4_RESERVED2_BB_SHIFT 0 #define PCIEIP_REG_TL_CONTROL_4_RESERVED1_BB (0xffff<<16) // For ECO/Control bits are reset on perst_b #define PCIEIP_REG_TL_CONTROL_4_RESERVED1_BB_SHIFT 16 -#define PCIEIP_REG_PHY_CONTROL_OFF_K2_E5 0x000814UL //Access:RW DataWidth:0x20 // PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins. +#define PCIEIP_REG_PCIEEP_PHY_CTL_E5 0x000814UL //Access:RW DataWidth:0x20 // +#define PCIEIP_REG_PHY_CONTROL_OFF_K2 0x000814UL //Access:RW DataWidth:0x20 // PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins. #define PCIEIP_REG_TL_CTRLSTAT_5_BB 0x000814UL //Access:RW DataWidth:0x20 // This register stores the status of errors to generate pcie_err_attn. #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_PSND_TLP_BB (0x1<<0) // This bit is set when h/w detects Poisoned Error Status . If set, h/w generates pcie_err_attn output . #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_PSND_TLP_BB_SHIFT 0 @@ -4435,6 +6639,9 @@ #define PCIEIP_REG_TL_FUNC11TO13_MASK_RXTABRT13_MASK_BB_SHIFT 29 #define PCIEIP_REG_TL_FUNC11TO13_MASK_UNUSED_1_BB (0x3<<30) // #define PCIEIP_REG_TL_FUNC11TO13_MASK_UNUSED_1_BB_SHIFT 30 +#define PCIEIP_REG_PCIEEP_CLK_GATING_CTL_E5 0x00088cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_CLK_GATING_CTL_RADM_CLK_GATING_EN_E5 (0x1<<0) // Enable RADM clock gating feature when there is no receive traffic, receive queues and pre/post-queue pipelines are empty, RADM completion LUT is empty, and there are no FLR actions pending. 0x0 = Disable. 0x1 = Enable. + #define PCIEIP_REG_PCIEEP_CLK_GATING_CTL_RADM_CLK_GATING_EN_E5_SHIFT 0 #define PCIEIP_REG_TL_FUNC11TO13_STAT_BB 0x00088cUL //Access:RW DataWidth:0x20 // This register stores the status of errors to generate pcie_err_attn for functions 11, 12, and 13. #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP11_BB (0x1<<0) // Poisoned Error Status detected for Function 11. If set, hw generates pcie_err_attn output. #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP11_BB_SHIFT 0 @@ -4498,29 +6705,58 @@ #define PCIEIP_REG_TL_FUNC11TO13_STAT_PRI_SIG_TARGET_ABORT13_BB_SHIFT 29 #define PCIEIP_REG_TL_FUNC11TO13_STAT_UNUSED_1_BB (0x3<<30) // #define PCIEIP_REG_TL_FUNC11TO13_STAT_UNUSED_1_BB_SHIFT 30 -#define PCIEIP_REG_GEN3_RELATED_OFF_K2_E5 0x000890UL //Access:RW DataWidth:0x20 // Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific "Directed Speed Change" field. The "Directed Speed Change" field in the "Link Width and Speed Change Control Register" is used to change to Gen2 or Gen3 speed. A speed change to Gen3 occurs if (1) the "Directed Speed Change" field is set to "1" and (2) the "Target Link Speed" field in the Link Control 2 Register is set to Gen3. Gen3 support is advertised by both sides of the link during link training. M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist. - #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_K2_E5 (0x1<<0) // Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled. - 0: The receiver complies with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. - 1: The receiver does not comply with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rates. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_K2_E5_SHIFT 0 - #define PCIEIP_REG_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_K2_E5 (0x1<<8) // Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the core needs to be disabled when the scrambling function is implemented outside of the core (for example within the PHY). Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_K2_E5_SHIFT 8 - #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_PHASE_2_3_K2_E5 (0x1<<9) // Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky. - #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_PHASE_2_3_K2_E5_SHIFT 9 - #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_EIEOS_CNT_K2_E5 (0x1<<10) // Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_EIEOS_CNT_K2_E5_SHIFT 10 - #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_REDO_K2_E5 (0x1<<11) // Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_REDO_K2_E5_SHIFT 11 - #define PCIEIP_REG_GEN3_RELATED_OFF_RXEQ_PH01_EN_K2_E5 (0x1<<12) // Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY. This bit is used during Virtex-7 Gen3 equalization. The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the following variations of the equalization procedure: - 00: Tx equalization only in phase 2/3 - 01: No Tx equalization, no Rx equalization - 10: Tx equalization in phase 2/3, Rx equalization in phase 0/1 - 11: No Tx equalization, Rx equalization in phase 0/1 Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky. - #define PCIEIP_REG_GEN3_RELATED_OFF_RXEQ_PH01_EN_K2_E5_SHIFT 12 - #define PCIEIP_REG_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_K2_E5 (0x1<<13) // When set to '1', the core as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner. - 1: mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky. - #define PCIEIP_REG_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_K2_E5_SHIFT 13 - #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_K2_E5 (0x1<<16) // Equalization Disable. Disable equalization feature. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_K2_E5_SHIFT 16 - #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_K2_E5 (0x1<<17) // DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_K2_E5_SHIFT 17 - #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_K2_E5 (0x1<<18) // DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_K2_E5_SHIFT 18 - #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_K2_E5 (0x1<<23) // Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_K2_E5_SHIFT 23 +#define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_E5 0x000890UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_GRIZDNC_E5 (0x1<<0) // Gen3 receiver impedance ZRX-DC not compliant. + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_GRIZDNC_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_DSG3_E5 (0x1<<8) // Disable scrambler for Gen3 data rate. The Gen3 scrambler/descrambler within the core needs to be disabled when the scrambling function is implemented outside of the core (within the PHY). + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_DSG3_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_EP2P3D_E5 (0x1<<9) // Equalization phase 2 and phase 3 disable. This applies to downstream ports only. + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_EP2P3D_E5_SHIFT 9 + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_ECRD_E5 (0x1<<10) // Equalization EIEOS count reset disable. Disable requesting reset of EIEOS count during equalization. + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_ECRD_E5_SHIFT 10 + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_ERD_E5 (0x1<<11) // Equalization redo disable. Disable requesting reset of EIEOS count during equalization. + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_ERD_E5_SHIFT 11 + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_RXEQ_PH01_EN_E5 (0x1<<12) // Rx equalization phase 0/phase 1 hold enable. + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_RXEQ_PH01_EN_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_RXEQ_RGRDLESS_RSTS_E5 (0x1<<13) // The controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation. 0x0 = Asserts after 1 us and 2 TS1 received from remote partner. 0x1 = Asserts after 500 ns regardless of TS's received or not. + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_RXEQ_RGRDLESS_RSTS_E5_SHIFT 13 + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_ED_E5 (0x1<<16) // Equalization disable. Disable equalization feature. + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_ED_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_DTDD_E5 (0x1<<17) // DLLP transmission delay disable. Disable delay transmission of DLLPs before equalization. + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_DTDD_E5_SHIFT 17 + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_DCBD_E5 (0x1<<18) // Disable balance disable. Disable DC balance feature. + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_DCBD_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_AED_E5 (0x1<<21) // Autonomous equalization disable. When the controller is in L0 state at Gen3 data rate and equalization was completed successfully in Autonomous EQ Mechanism, setting this bit in DSP will not direct the controller to Recovery state to perform Gen4 equalization. Link stays in Gen3 rate and DSP sends DLLPs to USP. If the bit is 0, DSP will block DLLPs and direct the link to perform Gen4 EQ in Autonomous Mechanism. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is RSVD. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_AED_E5_SHIFT 21 + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_US8ETD_E5 (0x1<<22) // Upstream port send 8GT/s EQ TS2 disable. The base spec defines that USP can optionally send 8GT EQ TS2 and it means USP can set DSP TxPreset value in Gen4 Data Rate. If this register set to 0, USP sends 8GT EQ TS2. If this register set to 1, USP does not send 8GT EQ TS2. This applies to upstream ports only. No Function for downstream ports. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is RSVD. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_US8ETD_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_EIEDD_E5 (0x1<<23) // Eq InvalidRequest and RxEqEval different time assertion disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_EIEDD_E5_SHIFT 23 + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_RSS_E5 (0x3<<24) // Data rate for shadow register. Hardwired for Gen3. + #define PCIEIP_REG_PCIEEP_PHY_GEN3_CTL_RSS_E5_SHIFT 24 +#define PCIEIP_REG_GEN3_RELATED_OFF_K2 0x000890UL //Access:RW DataWidth:0x20 // Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the "Link Width and Speed Change Control Register" is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific "Directed Speed Change" field. The "Directed Speed Change" field in the "Link Width and Speed Change Control Register" is used to change to Gen2 or Gen3 speed. A speed change to Gen3 occurs if (1) the "Directed Speed Change" field is set to "1" and (2) the "Target Link Speed" field in the Link Control 2 Register is set to Gen3. Gen3 support is advertised by both sides of the link during link training. M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist. + #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_K2 (0x1<<0) // Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the following LTSSM states: Polling, Rx_L0s, L1, L2, and Disabled. - 0: The receiver complies with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. - 1: The receiver does not comply with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rates. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL_K2_SHIFT 0 + #define PCIEIP_REG_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_K2 (0x1<<8) // Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the core needs to be disabled when the scrambling function is implemented outside of the core (for example within the PHY). Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_RELATED_OFF_DISABLE_SCRAMBLER_GEN_3_K2_SHIFT 8 + #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_PHASE_2_3_K2 (0x1<<9) // Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky. + #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_PHASE_2_3_K2_SHIFT 9 + #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_EIEOS_CNT_K2 (0x1<<10) // Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_EIEOS_CNT_K2_SHIFT 10 + #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_REDO_K2 (0x1<<11) // Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_RELATED_OFF_EQ_REDO_K2_SHIFT 11 + #define PCIEIP_REG_GEN3_RELATED_OFF_RXEQ_PH01_EN_K2 (0x1<<12) // Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be performed by the PHY. This bit is used during Virtex-7 Gen3 equalization. The programmable bits [RXEQ_PH01_EN, EQ_PHASE_2_3] can be used to obtain the following variations of the equalization procedure: - 00: Tx equalization only in phase 2/3 - 01: No Tx equalization, no Rx equalization - 10: Tx equalization in phase 2/3, Rx equalization in phase 0/1 - 11: No Tx equalization, Rx equalization in phase 0/1 Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky. + #define PCIEIP_REG_GEN3_RELATED_OFF_RXEQ_PH01_EN_K2_SHIFT 12 + #define PCIEIP_REG_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_K2 (0x1<<13) // When set to '1', the core as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from remote partner. - 1: mac_phy_rxeqeval asserts after 500ns regardless of TS's received or not. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: The access attributes of this field are as follows: - Dbi: see description Note: This register field is sticky. + #define PCIEIP_REG_GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS_K2_SHIFT 13 + #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_K2 (0x1<<16) // Equalization Disable. Disable equalization feature. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_EQUALIZATION_DISABLE_K2_SHIFT 16 + #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_K2 (0x1<<17) // DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_DLLP_XMT_DELAY_DISABLE_K2_SHIFT 17 + #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_K2 (0x1<<18) // DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_DC_BALANCE_DISABLE_K2_SHIFT 18 + #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_K2 (0x1<<23) // Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED, this register is shared for Gen3 and Gen4 data rate. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_RELATED_OFF_GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE_K2_SHIFT 23 #define PCIEIP_REG_TL_FUNC14TO15_MASK_BB 0x000890UL //Access:RW DataWidth:0x20 // This register masks specific errors from setting pcie_err_attn for functions 14 and 15. #define PCIEIP_REG_TL_FUNC14TO15_MASK_PES14_MASK_BB (0x1<<0) // Poisoned Error Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen. #define PCIEIP_REG_TL_FUNC14TO15_MASK_PES14_MASK_BB_SHIFT 0 @@ -4607,100 +6843,207 @@ #define PCIEIP_REG_TL_FUNC14TO15_STAT_PRI_SIG_TARGET_ABORT15_BB_SHIFT 19 #define PCIEIP_REG_TL_FUNC14TO15_STAT_UNUSED_1_BB (0xfff<<20) // #define PCIEIP_REG_TL_FUNC14TO15_STAT_UNUSED_1_BB_SHIFT 20 -#define PCIEIP_REG_PF_HIDE_CONTROL_K2_E5 0x0008a0UL //Access:RW DataWidth:0x20 // The core supports the hiding of implemented physical functions. To enable this feature, you must set the CX_HIDE_PF_EN hidden configuration parameter. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF0_HIDE_CONTROL_K2_E5 (0x3<<0) // 0x00: PF is Visible, 0x01:Reserved, 0x10:PF is hidden. All CFG accesses to this function will receive UR. 0x11: PF is Partially Hidden. CfgWr accesses to this funciton will receive UR. CfgRd accesses to this function will receive SC, with a data payload of 0xFFFFFFFF. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF0_HIDE_CONTROL_K2_E5_SHIFT 0 - #define PCIEIP_REG_PF_HIDE_CONTROL_PF1_HIDE_CONTROL_K2_E5 (0x3<<2) // Operates in the same way as PF0. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF1_HIDE_CONTROL_K2_E5_SHIFT 2 - #define PCIEIP_REG_PF_HIDE_CONTROL_PF2_HIDE_CONTROL_K2_E5 (0x3<<4) // Operates in the same way as PF0. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF2_HIDE_CONTROL_K2_E5_SHIFT 4 - #define PCIEIP_REG_PF_HIDE_CONTROL_PF3_HIDE_CONTROL_K2_E5 (0x3<<6) // Operates in the same way as PF0. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF3_HIDE_CONTROL_K2_E5_SHIFT 6 - #define PCIEIP_REG_PF_HIDE_CONTROL_PF4_HIDE_CONTROL_K2_E5 (0x3<<8) // Operates in the same way as PF0. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF4_HIDE_CONTROL_K2_E5_SHIFT 8 - #define PCIEIP_REG_PF_HIDE_CONTROL_PF5_HIDE_CONTROL_K2_E5 (0x3<<10) // Operates in the same way as PF0. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF5_HIDE_CONTROL_K2_E5_SHIFT 10 - #define PCIEIP_REG_PF_HIDE_CONTROL_PF6_HIDE_CONTROL_K2_E5 (0x3<<12) // Operates in the same way as PF0. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF6_HIDE_CONTROL_K2_E5_SHIFT 12 - #define PCIEIP_REG_PF_HIDE_CONTROL_PF7_HIDE_CONTROL_K2_E5 (0x3<<14) // Operates in the same way as PF0. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF7_HIDE_CONTROL_K2_E5_SHIFT 14 - #define PCIEIP_REG_PF_HIDE_CONTROL_PF8_HIDE_CONTROL_K2_E5 (0x3<<16) // Operates in the same way as PF0. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF8_HIDE_CONTROL_K2_E5_SHIFT 16 - #define PCIEIP_REG_PF_HIDE_CONTROL_PF9_HIDE_CONTROL_K2_E5 (0x3<<18) // Operates in the same way as PF0. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF9_HIDE_CONTROL_K2_E5_SHIFT 18 - #define PCIEIP_REG_PF_HIDE_CONTROL_PF10_HIDE_CONTROL_K2_E5 (0x3<<20) // Operates in the same way as PF0. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF10_HIDE_CONTROL_K2_E5_SHIFT 20 - #define PCIEIP_REG_PF_HIDE_CONTROL_PF11_HIDE_CONTROL_K2_E5 (0x3<<22) // Operates in the same way as PF0. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF11_HIDE_CONTROL_K2_E5_SHIFT 22 - #define PCIEIP_REG_PF_HIDE_CONTROL_PF12_HIDE_CONTROL_K2_E5 (0x3<<24) // Operates in the same way as PF0. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF12_HIDE_CONTROL_K2_E5_SHIFT 24 - #define PCIEIP_REG_PF_HIDE_CONTROL_PF13_HIDE_CONTROL_K2_E5 (0x3<<26) // Operates in the same way as PF0. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF13_HIDE_CONTROL_K2_E5_SHIFT 26 - #define PCIEIP_REG_PF_HIDE_CONTROL_PF14_HIDE_CONTROL_K2_E5 (0x3<<28) // Operates in the same way as PF0. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF14_HIDE_CONTROL_K2_E5_SHIFT 28 - #define PCIEIP_REG_PF_HIDE_CONTROL_PF15_HIDE_CONTROL_K2_E5 (0x3<<30) // Operates in the same way as PF0. - #define PCIEIP_REG_PF_HIDE_CONTROL_PF15_HIDE_CONTROL_K2_E5_SHIFT 30 -#define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_K2_E5 0x0008a8UL //Access:RW DataWidth:0x20 // Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist. - #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_K2_E5 (0xf<<0) // Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED, this register is a shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_K2_E5_SHIFT 0 - #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_K2_E5 (0x1<<4) // Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found then: - Equalization Phase 2 Successful status bit is not set in the "Link Status Register 2" - Equalization Phase 2 Complete status bit is set in the "Link Status Register 2" For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.RcvrLock When optimal settings are not found then: - Equalization Phase 3 Successful status bit is not set in the "Link Status Register 2" - Equalization Phase 3 Complete status bit is set in the "Link Status Register 2" Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_K2_E5_SHIFT 4 - #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_K2_E5 (0x1<<5) // Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout - 1: ignore the 2ms timeout and continue as normal. This is used to support PHYs that require more than 2ms to respond to the assertion of RxEqEval. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_K2_E5_SHIFT 5 - #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_K2_E5 (0xffff<<8) // Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase. - 0000000000000000: No preset be requested and evaluated in EQ Master Phase - 000000xxxxxxxxx1: Preset 0 is requested and evaluated in EQ Master Phase - 000000xxxxxxxx1x: Preset 1 is requested and evaluated in EQ Master Phase - 000000xxxxxxx1xx: Preset 2 is requested and evaluated in EQ Master Phase - 000000xxxxxx1xxx: Preset 3 is requested and evaluated in EQ Master Phase - 000000xxxxx1xxxx: Preset 4 is requested and evaluated in EQ Master Phase - 000000xxxx1xxxxx: Preset 5 is requested and evaluated in EQ Master Phase - 000000xxx1xxxxxx: Preset 6 is requested and evaluated in EQ Master Phase - 000000xx1xxxxxxx: Preset 7 is requested and evaluated in EQ Master Phase - 000000x1xxxxxxxx: Preset 8 is requested and evaluated in EQ Master Phase - 00000x1xxxxxxxxx: Preset 9 is requested and evaluated in EQ Master Phase - 000001xxxxxxxxxx: Preset 10 is requested and evaluated in EQ Master Phase - All other encodings: Reserved Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_K2_E5_SHIFT 8 - #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_K2_E5 (0x1<<24) // Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_K2_E5_SHIFT 24 - #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_K2_E5 (0x1<<25) // GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_K2_E5_SHIFT 25 - #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_K2_E5 (0x1<<26) // Request core to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_K2_E5_SHIFT 26 -#define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_K2_E5 0x0008acUL //Access:RW DataWidth:0x20 // Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP), when you set the Feedback Mode in "Gen3 EQ Control Register" to "Direction Change." These fields allow control over the initial starting point for the search of optimal coefficient settings, and allow control over the criteria used to determine when the optimal settings have been achieved. The values are applied to all the lanes. - #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_K2_E5 (0x1f<<0) // Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time, before starting to check for convergence of the coefficients. Allowed values 0,1,...,24. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_K2_E5_SHIFT 0 - #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_K2_E5 (0x1f<<5) // Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0,1,2,..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0, EQ Master is performed without sending any requests to the remote partner in Phase 2 for USP and Phase 3 for DSP. Therefore, the remote partner will not change its transmitter coefficients and will move to the next state. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_K2_E5_SHIFT 5 - #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_K2_E5 (0xf<<10) // Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0,1,2,..15. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_K2_E5_SHIFT 10 - #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_K2_E5 (0xf<<14) // Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0,1,2,..15. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. - #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_K2_E5_SHIFT 14 -#define PCIEIP_REG_ORDER_RULE_CTRL_OFF_K2_E5 0x0008b4UL //Access:RW DataWidth:0x20 // Order Rule Control Register. - #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_NP_PASS_P_K2_E5 (0xff<<0) // Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P - #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_NP_PASS_P_K2_E5_SHIFT 0 - #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_CPL_PASS_P_K2_E5 (0xff<<8) // Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P - #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_CPL_PASS_P_K2_E5_SHIFT 8 -#define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_K2_E5 0x0008b8UL //Access:RW DataWidth:0x20 // PIPE Loopback Control Register. - #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_K2_E5 (0xffff<<0) // LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky. - #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_K2_E5_SHIFT 0 - #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_K2_E5 (0x3f<<16) // RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky. - #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_K2_E5_SHIFT 16 - #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_K2_E5 (0x7<<24) // RXSTATUS_VALUE is an internally reserved field. Do not use. - #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_K2_E5_SHIFT 24 - #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_K2_E5 (0x1<<31) // PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky. - #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_K2_E5_SHIFT 31 -#define PCIEIP_REG_MISC_CONTROL_1_OFF_K2_E5 0x0008bcUL //Access:RW DataWidth:0x20 // DBI Read-Only Write Enable Register. - #define PCIEIP_REG_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_K2_E5 (0x1<<0) // Write to RO Registers Using DBI. When you set this field to "1", then some RO and HwInit bits are writable from the local application through the DBI. For more details, see "Writing to Read-Only Registers." Note: This register field is sticky. - #define PCIEIP_REG_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_K2_E5_SHIFT 0 -#define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_K2_E5 0x0008c0UL //Access:RW DataWidth:0x20 // UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details, see the "Link Establishment" section in the Core Operations chapter of the Databook. - #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_K2_E5 (0x3f<<0) // Target Link Width. Values correspond to: - 6'b000000: Core does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 - 6'b100000: x32 This field is reserved (fixed to '0') for M-PCIe. - #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_K2_E5_SHIFT 0 - #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_K2_E5 (0x1<<6) // Directed Link Width Change. The core always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG is '0', the core starts upconfigure or autonomous width downsizing (to the TARGET_LINK_WIDTH value) in the Configuration state. - If TARGET_LINK_WIDTH value is 0x0, the core does not start upconfigure or autonomous width downsizing in the Configuration state. The core self-clears this field when the core accepts this request. This field is reserved (fixed to '0') for M-PCIe. - #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_K2_E5_SHIFT 6 - #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_K2_E5 (0x1<<7) // Upconfigure Support. The core sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky. - #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_K2_E5_SHIFT 7 -#define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_K2_E5 0x0008c4UL //Access:RW DataWidth:0x20 // PHY Interoperability Control Register. This register is reserved for internal use. You should not write to this register and change the default unless specifically instructed by Synopsys support. - #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_K2_E5 (0x7f<<0) // Rxstandby Control. Bits 0..5 determine if the core asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. - [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]: Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP2 - [4]: RxL0s.Idle - [5]: EI Infer in L0 - [6]: Execute RxStandby/RxStandbyStatus Handshake This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky. - #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_K2_E5_SHIFT 0 - #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_K2_E5 (0x1<<9) // L1 entry control bit. - 1: Core does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Core waits for the PHY to acknowledge transition to P1 before entering L1. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. - #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_K2_E5_SHIFT 9 -#define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_K2_E5 0x0008c8UL //Access:RW DataWidth:0x20 // TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. Note:: The target completion LUT (and associated target completion timeout event) is watching for received application completions (on XALI0/1/2) corresponding to previously received non-posted requests from the PCIe wire. - #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_K2_E5 (0x7fffffff<<0) // This number selects one entry to delete of the TRGT_CPL_LUT. - #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_K2_E5_SHIFT 0 - #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_K2_E5 (0x1<<31) // This is a one shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'. - #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_K2_E5_SHIFT 31 -#define PCIEIP_REG_PL_LAST_OFF_K2_E5 0x0008fcUL //Access:R DataWidth:0x20 // PL_LAST_OFF is an internally reserved register. Do not use. - #define PCIEIP_REG_PL_LAST_OFF_PL_LAST_K2_E5 (0x1<<0) // PL_LAST is an internally reserved field. Do not use. - #define PCIEIP_REG_PL_LAST_OFF_PL_LAST_K2_E5_SHIFT 0 +#define PCIEIP_REG_PCIEEP_HIDE_PF_E5 0x0008a0UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF0_E5 (0x3<<0) // PF0 hide control. 0x0 = PF is visible. 0x1 = Reserved. 0x2 = PF is hidden. All config accesses to this function will receive UR. 0x3 = PF is partially hidden. Config write accesses to this function will receive UR. Config read accesses to this function will receive SC, with a data payload of 0xFFFFFFFF. When the MSB of a PF's HIDE_PFn is non-zero, the PF is considered hidden, and the power management state for the PF is kept in the uninitialized state. + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF0_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF1_E5 (0x3<<2) // PF1 hide control. Similar to [PF0]. + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF1_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF2_E5 (0x3<<4) // PF2 hide control. Similar to [PF0]. + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF2_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF3_E5 (0x3<<6) // PF3 hide control. Similar to [PF0]. + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF3_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF4_E5 (0x3<<8) // PF4 hide control. Similar to [PF0]. + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF4_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF5_E5 (0x3<<10) // PF5 hide control. Similar to [PF0]. + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF5_E5_SHIFT 10 + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF6_E5 (0x3<<12) // PF6 hide control. Similar to [PF0]. + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF6_E5_SHIFT 12 + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF7_E5 (0x3<<14) // PF7 hide control. Similar to [PF0]. + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF7_E5_SHIFT 14 + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF8_E5 (0x3<<16) // PF8 hide control. Similar to [PF0]. + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF8_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF9_E5 (0x3<<18) // PF9 hide control. Similar to [PF0]. + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF9_E5_SHIFT 18 + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF10_E5 (0x3<<20) // PF10 hide control. Similar to [PF0]. + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF10_E5_SHIFT 20 + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF11_E5 (0x3<<22) // PF11 hide control. Similar to [PF0]. + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF11_E5_SHIFT 22 + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF12_E5 (0x3<<24) // PF12 hide control. Similar to [PF0]. + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF12_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF13_E5 (0x3<<26) // PF13 hide control. Similar to [PF0]. + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF13_E5_SHIFT 26 + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF14_E5 (0x3<<28) // PF14 hide control. Similar to [PF0]. + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF14_E5_SHIFT 28 + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF15_E5 (0x3<<30) // PF15 hide control. Similar to [PF0]. + #define PCIEIP_REG_PCIEEP_HIDE_PF_HIDE_PF15_E5_SHIFT 30 +#define PCIEIP_REG_PF_HIDE_CONTROL_K2 0x0008a0UL //Access:RW DataWidth:0x20 // The core supports the hiding of implemented physical functions. To enable this feature, you must set the CX_HIDE_PF_EN hidden configuration parameter. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF0_HIDE_CONTROL_K2 (0x3<<0) // 0x00: PF is Visible, 0x01:Reserved, 0x10:PF is hidden. All CFG accesses to this function will receive UR. 0x11: PF is Partially Hidden. CfgWr accesses to this funciton will receive UR. CfgRd accesses to this function will receive SC, with a data payload of 0xFFFFFFFF. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF0_HIDE_CONTROL_K2_SHIFT 0 + #define PCIEIP_REG_PF_HIDE_CONTROL_PF1_HIDE_CONTROL_K2 (0x3<<2) // Operates in the same way as PF0. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF1_HIDE_CONTROL_K2_SHIFT 2 + #define PCIEIP_REG_PF_HIDE_CONTROL_PF2_HIDE_CONTROL_K2 (0x3<<4) // Operates in the same way as PF0. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF2_HIDE_CONTROL_K2_SHIFT 4 + #define PCIEIP_REG_PF_HIDE_CONTROL_PF3_HIDE_CONTROL_K2 (0x3<<6) // Operates in the same way as PF0. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF3_HIDE_CONTROL_K2_SHIFT 6 + #define PCIEIP_REG_PF_HIDE_CONTROL_PF4_HIDE_CONTROL_K2 (0x3<<8) // Operates in the same way as PF0. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF4_HIDE_CONTROL_K2_SHIFT 8 + #define PCIEIP_REG_PF_HIDE_CONTROL_PF5_HIDE_CONTROL_K2 (0x3<<10) // Operates in the same way as PF0. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF5_HIDE_CONTROL_K2_SHIFT 10 + #define PCIEIP_REG_PF_HIDE_CONTROL_PF6_HIDE_CONTROL_K2 (0x3<<12) // Operates in the same way as PF0. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF6_HIDE_CONTROL_K2_SHIFT 12 + #define PCIEIP_REG_PF_HIDE_CONTROL_PF7_HIDE_CONTROL_K2 (0x3<<14) // Operates in the same way as PF0. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF7_HIDE_CONTROL_K2_SHIFT 14 + #define PCIEIP_REG_PF_HIDE_CONTROL_PF8_HIDE_CONTROL_K2 (0x3<<16) // Operates in the same way as PF0. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF8_HIDE_CONTROL_K2_SHIFT 16 + #define PCIEIP_REG_PF_HIDE_CONTROL_PF9_HIDE_CONTROL_K2 (0x3<<18) // Operates in the same way as PF0. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF9_HIDE_CONTROL_K2_SHIFT 18 + #define PCIEIP_REG_PF_HIDE_CONTROL_PF10_HIDE_CONTROL_K2 (0x3<<20) // Operates in the same way as PF0. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF10_HIDE_CONTROL_K2_SHIFT 20 + #define PCIEIP_REG_PF_HIDE_CONTROL_PF11_HIDE_CONTROL_K2 (0x3<<22) // Operates in the same way as PF0. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF11_HIDE_CONTROL_K2_SHIFT 22 + #define PCIEIP_REG_PF_HIDE_CONTROL_PF12_HIDE_CONTROL_K2 (0x3<<24) // Operates in the same way as PF0. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF12_HIDE_CONTROL_K2_SHIFT 24 + #define PCIEIP_REG_PF_HIDE_CONTROL_PF13_HIDE_CONTROL_K2 (0x3<<26) // Operates in the same way as PF0. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF13_HIDE_CONTROL_K2_SHIFT 26 + #define PCIEIP_REG_PF_HIDE_CONTROL_PF14_HIDE_CONTROL_K2 (0x3<<28) // Operates in the same way as PF0. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF14_HIDE_CONTROL_K2_SHIFT 28 + #define PCIEIP_REG_PF_HIDE_CONTROL_PF15_HIDE_CONTROL_K2 (0x3<<30) // Operates in the same way as PF0. + #define PCIEIP_REG_PF_HIDE_CONTROL_PF15_HIDE_CONTROL_K2_SHIFT 30 +#define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_E5 0x0008a8UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_FM_E5 (0xf<<0) // Feedback mode. 0 = Direction of change. 1 = Figure of merit. 2-15 = Reserved. + #define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_FM_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_BT_E5 (0x1<<4) // Behavior after 24 ms timeout (when optimal settings are not found). For a USP: determine the next LTSSM state from Phase2: 0 = Recovery.Speed. 1 = Recovry.Equalization.Phase3. For a DSP: determine the next LTSSM state from Phase3: 0 = Recovery.Speed. 1 = Recovry.Equalization.RcrLock. When optimal settings are not found: * Equalization phase 3 successful status bit is not set in the link status register. * Equalization phase 3 complete status bit is set in the link status register. + #define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_BT_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_P23TD_E5 (0x1<<5) // Phase2_3 2 ms timeout disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2 ms to the assertion of RxEqEval: 0 = Abort the current evaluation; stop any attempt to modify the remote transmitter settings. Phase2 will be terminated by the 24 ms timeout. 1 = Ignore the 2 ms timeout and continue as normal. This is used to support PHYs that require more than 2 ms to respond to the assertion of RxEqEval. + #define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_P23TD_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_EQ_REDO_EN_E5 (0x1<<6) // Support EQ redo and lower rate change. + #define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_EQ_REDO_EN_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_PRV_E5 (0xffff<<8) // Preset request vector. Requesting of presets during the initial part of the EQ master phase. Encoding scheme as follows: Bit [15:0] = 0x0: No preset is requested and evaluated in the EQ master phase. Bit [i] = 1: Preset=i is requested and evaluated in the EQ master phase. _ 0b0000000000000000 = No preset req/evaluated in EQ master phase. _ 0b00000xxxxxxxxxx1 = Preset 0 req/evaluated in EQ master phase. _ 0b00000xxxxxxxxx1x = Preset 1 req/evaluated in EQ master phase. _ 0b00000xxxxxxxx1xx = Preset 2 req/evaluated in EQ master phase. _ 0b00000xxxxxxx1xxx = Preset 3 req/evaluated in EQ master phase. _ 0b00000xxxxxx1xxxx = Preset 4 req/evaluated in EQ master phase. _ 0b00000xxxxx1xxxxx = Preset 5 req/evaluated in EQ master phase. _ 0b00000xxxx1xxxxxx = Preset 6 req/evaluated in EQ master phase. _ 0b00000xxx1xxxxxxx = Preset 7 req/evaluated in EQ master phase. _ 0b00000xx1xxxxxxxx = Preset 8 req/evaluated in EQ master phase. _ 0b00000x1xxxxxxxxx = Preset 9 req/evaluated in EQ master phase. _ 0b000001xxxxxxxxxx = Preset 10 req/evaluated in EQ master phase. _ All other encodings = Reserved. + #define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_PRV_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_IIF_E5 (0x1<<24) // Include initial FOM. Include, or not, the FOM feedback from the initial preset evaluation performed in the EQ master, when finding the highest FOM among all preset evaluations. + #define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_IIF_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_EQ_PSET_REQ_E5 (0x1<<25) // Reserved. + #define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_EQ_PSET_REQ_E5_SHIFT 25 + #define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_SCEFPM_E5 (0x1<<26) // Request core to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficient mapping is complete. + #define PCIEIP_REG_PCIEEP_GEN3_EQ_CTL_SCEFPM_E5_SHIFT 26 +#define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_K2 0x0008a8UL //Access:RW DataWidth:0x20 // Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP), or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist. + #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_K2 (0xf<<0) // Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED, this register is a shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FB_MODE_K2_SHIFT 0 + #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_K2 (0x1<<4) // Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found then: - Equalization Phase 2 Successful status bit is not set in the "Link Status Register 2" - Equalization Phase 2 Complete status bit is set in the "Link Status Register 2" For a DSP: Determine next LTSSM state from Phase3 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.RcvrLock When optimal settings are not found then: - Equalization Phase 3 Successful status bit is not set in the "Link Status Register 2" - Equalization Phase 3 Complete status bit is set in the "Link Status Register 2" Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PHASE23_EXIT_MODE_K2_SHIFT 4 + #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_K2 (0x1<<5) // Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation, stop any attempt to modify the remote transmitter settings, Phase2 is terminated by the 24ms timeout - 1: ignore the 2ms timeout and continue as normal. This is used to support PHYs that require more than 2ms to respond to the assertion of RxEqEval. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_EVAL_2MS_DISABLE_K2_SHIFT 5 + #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_K2 (0xffff<<8) // Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: "Preset=i" is requested and evaluated in EQ Master Phase. - 0000000000000000: No preset be requested and evaluated in EQ Master Phase - 000000xxxxxxxxx1: Preset 0 is requested and evaluated in EQ Master Phase - 000000xxxxxxxx1x: Preset 1 is requested and evaluated in EQ Master Phase - 000000xxxxxxx1xx: Preset 2 is requested and evaluated in EQ Master Phase - 000000xxxxxx1xxx: Preset 3 is requested and evaluated in EQ Master Phase - 000000xxxxx1xxxx: Preset 4 is requested and evaluated in EQ Master Phase - 000000xxxx1xxxxx: Preset 5 is requested and evaluated in EQ Master Phase - 000000xxx1xxxxxx: Preset 6 is requested and evaluated in EQ Master Phase - 000000xx1xxxxxxx: Preset 7 is requested and evaluated in EQ Master Phase - 000000x1xxxxxxxx: Preset 8 is requested and evaluated in EQ Master Phase - 00000x1xxxxxxxxx: Preset 9 is requested and evaluated in EQ Master Phase - 000001xxxxxxxxxx: Preset 10 is requested and evaluated in EQ Master Phase - All other encodings: Reserved Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_VEC_K2_SHIFT 8 + #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_K2 (0x1<<24) // Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master, when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_FOM_INC_INITIAL_EVAL_K2_SHIFT 24 + #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_K2 (0x1<<25) // GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_EQ_PSET_REQ_AS_COEF_K2_SHIFT 25 + #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_K2 (0x1<<26) // Request core to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_EQ_CONTROL_OFF_GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP_K2_SHIFT 26 +#define PCIEIP_REG_PCIEEP_GEN3_FB_MODE_DIR_CHG_E5 0x0008acUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_GEN3_FB_MODE_DIR_CHG_MIN_PHASE23_E5 (0x1f<<0) // Minimum time (in ms) to remain in EQ master phase. The LTSSM stays in EQ master phase for at least this amount of time, before starting to check for convergence of the coefficients. Legal values: 0..24. + #define PCIEIP_REG_PCIEEP_GEN3_FB_MODE_DIR_CHG_MIN_PHASE23_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_GEN3_FB_MODE_DIR_CHG_N_EVALS_E5 (0x1f<<5) // Convergence window depth. Number of consecutive evaluations considered in phase 2/3 when determining if optimal coefficients have been found. When 0x0, EQ master is performed without sending any requests to the remote partner in phase 2 for USP and phase 3 for DSP. Therefore, the remote partner will not change its transmitter coefficients and will move to the next state. Legal values: 0x0, 0x1, and 0x2. + #define PCIEIP_REG_PCIEEP_GEN3_FB_MODE_DIR_CHG_N_EVALS_E5_SHIFT 5 + #define PCIEIP_REG_PCIEEP_GEN3_FB_MODE_DIR_CHG_MAX_PRE_CUR_DELTA_E5 (0xf<<10) // Convergence window aperture for C-1. Precursor coefficients maximum delta within the convergence window depth. + #define PCIEIP_REG_PCIEEP_GEN3_FB_MODE_DIR_CHG_MAX_PRE_CUR_DELTA_E5_SHIFT 10 + #define PCIEIP_REG_PCIEEP_GEN3_FB_MODE_DIR_CHG_MAX_POST_CUR_DELTA_E5 (0xf<<14) // Convergence window aperture for C+1. Postcursor coefficients maximum delta within the convergence window depth. + #define PCIEIP_REG_PCIEEP_GEN3_FB_MODE_DIR_CHG_MAX_POST_CUR_DELTA_E5_SHIFT 14 +#define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_K2 0x0008acUL //Access:RW DataWidth:0x20 // Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP), when you set the Feedback Mode in "Gen3 EQ Control Register" to "Direction Change." These fields allow control over the initial starting point for the search of optimal coefficient settings, and allow control over the criteria used to determine when the optimal settings have been achieved. The values are applied to all the lanes. + #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_K2 (0x1f<<0) // Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time, before starting to check for convergence of the coefficients. Allowed values 0,1,...,24. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_T_MIN_PHASE23_K2_SHIFT 0 + #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_K2 (0x1f<<5) // Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0,1,2,..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0, EQ Master is performed without sending any requests to the remote partner in Phase 2 for USP and Phase 3 for DSP. Therefore, the remote partner will not change its transmitter coefficients and will move to the next state. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_N_EVALS_K2_SHIFT 5 + #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_K2 (0xf<<10) // Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0,1,2,..15. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA_K2_SHIFT 10 + #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_K2 (0xf<<14) // Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0,1,2,..15. Note: When CX_GEN4_SPEED, this register is shadow register for Gen3 and Gen4 data rate. If RATE_SHADOW_SEL==00b, this register is for Gen3 data rate. If RATE_SHADOW_SEL==01b, this register is for Gen4 data rate. Note: This register field is sticky. + #define PCIEIP_REG_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF_GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA_K2_SHIFT 14 +#define PCIEIP_REG_PCIEEP_ORD_RULE_CTRL_E5 0x0008b4UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_ORD_RULE_CTRL_NP_PASS_P_E5 (0xff<<0) // Non-Posted passing posted ordering rule control. Determines if a NP can pass halted P queue. 0x0 = NP can not pass P (recommended). 0x1 = NP can pass P. 0x2-0xFF = Reserved. + #define PCIEIP_REG_PCIEEP_ORD_RULE_CTRL_NP_PASS_P_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_ORD_RULE_CTRL_CPL_PASS_P_E5 (0xff<<8) // Completion passing posted ordering rule control. Determines if a CPL can pass halted P queue. 0x0 = CPL can not pass P (recommended). 0x1 = CPL can pass P. 0x2-0xFF = Reserved. + #define PCIEIP_REG_PCIEEP_ORD_RULE_CTRL_CPL_PASS_P_E5_SHIFT 8 +#define PCIEIP_REG_ORDER_RULE_CTRL_OFF_K2 0x0008b4UL //Access:RW DataWidth:0x20 // Order Rule Control Register. + #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_NP_PASS_P_K2 (0xff<<0) // Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P + #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_NP_PASS_P_K2_SHIFT 0 + #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_CPL_PASS_P_K2 (0xff<<8) // Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P + #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_CPL_PASS_P_K2_SHIFT 8 +#define PCIEIP_REG_PCIEEP_GEN3_PIPE_LB_E5 0x0008b8UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_GEN3_PIPE_LB_LPBK_RXVALID_E5 (0xffff<<0) // Loopback rxvalid (lane enable - 1 bit per lane). + #define PCIEIP_REG_PCIEEP_GEN3_PIPE_LB_LPBK_RXVALID_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_GEN3_PIPE_LB_RESERVED_E5 (0x7fff<<16) // Reserved. + #define PCIEIP_REG_PCIEEP_GEN3_PIPE_LB_RESERVED_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_GEN3_PIPE_LB_PLE_E5 (0x1<<31) // Pipe loopback enable. + #define PCIEIP_REG_PCIEEP_GEN3_PIPE_LB_PLE_E5_SHIFT 31 +#define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_K2 0x0008b8UL //Access:RW DataWidth:0x20 // PIPE Loopback Control Register. + #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_K2 (0xffff<<0) // LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky. + #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_K2_SHIFT 0 + #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_K2 (0x3f<<16) // RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky. + #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_K2_SHIFT 16 + #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_K2 (0x7<<24) // RXSTATUS_VALUE is an internally reserved field. Do not use. + #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_K2_SHIFT 24 + #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_K2 (0x1<<31) // PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky. + #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_K2_SHIFT 31 +#define PCIEIP_REG_PCIEEP_MISC_CTL1_E5 0x0008bcUL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_MISC_CTL1_DBI_RO_WR_EN_E5 (0x1<<0) // Write to RO registers using DBI. When you set this bit, then some RO bits are writable from the DBI. + #define PCIEIP_REG_PCIEEP_MISC_CTL1_DBI_RO_WR_EN_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_MISC_CTL1_DEF_TARGET_E5 (0x1<<1) // Default target a received IO or MEM request with UR/CA/CRS is sent to be the controller. 0x0 = The controller drops all incoming I/O or Mem (after corresponding error reporting). A completion with UR status will be generated for non-posted requests. 0x1 = The controller forwards all incoming I/O or MEM requests with UR/CA/CRS status to your application. + #define PCIEIP_REG_PCIEEP_MISC_CTL1_DEF_TARGET_E5_SHIFT 1 + #define PCIEIP_REG_PCIEEP_MISC_CTL1_UR_C4_MASK_4_TRGT1_E5 (0x1<<2) // This field only applies to request TLPs (with UR filtering status) that are chosen to forward to the application (when [DEF_TARGET] is set). When set, the core suppresses error logging, error message generation, and CPL generation (for non-posted requests). + #define PCIEIP_REG_PCIEEP_MISC_CTL1_UR_C4_MASK_4_TRGT1_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_MISC_CTL1_SIMP_REPLAY_TIMER_E5 (0x1<<3) // Enables Simplified Replay Timer (Gen4). Simplified replay timer values are: A value from 24,000 to 31,000 symbol times when extended synch is 0. A value from 80,000 to 100,000 symbol times when extended synch is 1. + #define PCIEIP_REG_PCIEEP_MISC_CTL1_SIMP_REPLAY_TIMER_E5_SHIFT 3 + #define PCIEIP_REG_PCIEEP_MISC_CTL1_DIS_AUTO_LTR_CLR_E5 (0x1<<4) // Disable the autonomous generation of LTR clear message in upstream port. 0 = Allow the autonomous generation of LTR clear message. 1 = Disable the autonomous generation of LTR clear message. + #define PCIEIP_REG_PCIEEP_MISC_CTL1_DIS_AUTO_LTR_CLR_E5_SHIFT 4 + #define PCIEIP_REG_PCIEEP_MISC_CTL1_ARI_DEVN_E5 (0x1<<5) // When ARI is enabled, enables use of the device ID. + #define PCIEIP_REG_PCIEEP_MISC_CTL1_ARI_DEVN_E5_SHIFT 5 +#define PCIEIP_REG_MISC_CONTROL_1_OFF_K2 0x0008bcUL //Access:RW DataWidth:0x20 // DBI Read-Only Write Enable Register. + #define PCIEIP_REG_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_K2 (0x1<<0) // Write to RO Registers Using DBI. When you set this field to "1", then some RO and HwInit bits are writable from the local application through the DBI. For more details, see "Writing to Read-Only Registers." Note: This register field is sticky. + #define PCIEIP_REG_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_K2_SHIFT 0 +#define PCIEIP_REG_PCIEEP_UPCONFIG_E5 0x0008c0UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_UPCONFIG_TRGT_LNK_WDTH_E5 (0x3f<<0) // Target link width. 0x0 = Core does not start upconfigure or autonomous width downsizing in configuration state. 0x1 = x1. 0x2 = x2. 0x4 = x4. 0x8 = x8. 0x10 = x16. 0x20 = x32 (Not supported). + #define PCIEIP_REG_PCIEEP_UPCONFIG_TRGT_LNK_WDTH_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_UPCONFIG_DIR_LNK_WDTH_CHG_E5 (0x1<<6) // Directed link width change. The core always moves to configuration state through recovery state when this bit is set. If PCIEEP_RAS_EINJ_CTL6PE[LTSSM_VAR] is set and PCIEEP_LINK_CTL2[HASD] is zero, the core starts upconfigure or autonomous width downsizing (to the [TRGT_LNK_WDTH] value) in the configuration state. If [TRGT_LNK_WDTH] is 0x0, the core does not start upconfigure or autonomous width downsizing in the configuration state. The core self-clears this field when the core accepts this request. + #define PCIEIP_REG_PCIEEP_UPCONFIG_DIR_LNK_WDTH_CHG_E5_SHIFT 6 + #define PCIEIP_REG_PCIEEP_UPCONFIG_UPC_SUPP_E5 (0x1<<7) // Upconfigure support. The core sends this value to the link upconfigure capability in TS2 ordered sets in Configuration.Complete state. + #define PCIEIP_REG_PCIEEP_UPCONFIG_UPC_SUPP_E5_SHIFT 7 +#define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_K2 0x0008c0UL //Access:RW DataWidth:0x20 // UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details, see the "Link Establishment" section in the Core Operations chapter of the Databook. + #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_K2 (0x3f<<0) // Target Link Width. Values correspond to: - 6'b000000: Core does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 - 6'b100000: x32 This field is reserved (fixed to '0') for M-PCIe. + #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_K2_SHIFT 0 + #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_K2 (0x1<<6) // Directed Link Width Change. The core always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG is '0', the core starts upconfigure or autonomous width downsizing (to the TARGET_LINK_WIDTH value) in the Configuration state. - If TARGET_LINK_WIDTH value is 0x0, the core does not start upconfigure or autonomous width downsizing in the Configuration state. The core self-clears this field when the core accepts this request. This field is reserved (fixed to '0') for M-PCIe. + #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_K2_SHIFT 6 + #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_K2 (0x1<<7) // Upconfigure Support. The core sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky. + #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_K2_SHIFT 7 +#define PCIEIP_REG_PCIEEP_PHY_INTOP_CTL_E5 0x0008c4UL //Access:RW DataWidth:0x20 // This register is reserved for internal use. You should not write to this register and change the default unless specifically instructed by Synopsys support. + #define PCIEIP_REG_PCIEEP_PHY_INTOP_CTL_RXSTBY_CTL_E5 (0x7f<<0) // Rxstandby control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. 0x0 = Rx EIOS and subsequent T TX-IDLE-MIN. 0x1 = Rate Change. 0x2 = Inactive lane for upconfigure/downconfigure. 0x3 = PowerDown = P1orP2. 0x4 = RxL0s.Idle. 0x5 = EI Infer in L0. 0x6 = Execute RxStandby/RxStandbyStatus Handshake. + #define PCIEIP_REG_PCIEEP_PHY_INTOP_CTL_RXSTBY_CTL_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PHY_INTOP_CTL_L1SUB_EXIT_MODE_E5 (0x1<<8) // L1 exit control using phy_mac_pclkack_n. 0 = Core waits for the PHY to assert phy_mac_pclkack_n before exiting L1. 1 = Core exits L1 without waiting for the PHY to assert phy_mac_pclkack_n. + #define PCIEIP_REG_PCIEEP_PHY_INTOP_CTL_L1SUB_EXIT_MODE_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_PHY_INTOP_CTL_L1_NOWAIT_P1_E5 (0x1<<9) // L1 entry control bit. 0 = Core waits for the PHY to acknowledge transition to P1 before entering L1. 1 = Core does not wait for PHY to acknowledge transition to P1 before entering L1. + #define PCIEIP_REG_PCIEEP_PHY_INTOP_CTL_L1_NOWAIT_P1_E5_SHIFT 9 + #define PCIEIP_REG_PCIEEP_PHY_INTOP_CTL_LCS_E5 (0x1<<10) // L1 clock control bit. 0 = Controller requests aux_clk switch and core_clk gating in L1. 1 = Controller does not request aux_clk switch and core_clk gating in L1. + #define PCIEIP_REG_PCIEEP_PHY_INTOP_CTL_LCS_E5_SHIFT 10 +#define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_K2 0x0008c4UL //Access:RW DataWidth:0x20 // PHY Interoperability Control Register. This register is reserved for internal use. You should not write to this register and change the default unless specifically instructed by Synopsys support. + #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_K2 (0x7f<<0) // Rxstandby Control. Bits 0..5 determine if the core asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. - [0]: Rx EIOS and subsequent T TX-IDLE-MIN - [1]: Rate Change - [2]: Inactive lane for upconfigure/downconfigure - [3]: PowerDown=P1orP2 - [4]: RxL0s.Idle - [5]: EI Infer in L0 - [6]: Execute RxStandby/RxStandbyStatus Handshake This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky. + #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_K2_SHIFT 0 + #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_K2 (0x1<<9) // L1 entry control bit. - 1: Core does not wait for PHY to acknowledge transition to P1 before entering L1. - 0: Core waits for the PHY to acknowledge transition to P1 before entering L1. Note: The access attributes of this field are as follows: - Dbi: R/W (sticky) Note: This register field is sticky. + #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_K2_SHIFT 9 +#define PCIEIP_REG_PCIEEP_CPL_LUT_DEL_ENT_E5 0x0008c8UL //Access:RW DataWidth:0x20 // Using this register you can delete on entry in the target completion LUT. You should only use this register when you know that your application will never send the completion because of an FLR or any other reason. + #define PCIEIP_REG_PCIEEP_CPL_LUT_DEL_ENT_LUID_E5 (0x7fffffff<<0) // This number selects one entry to delete from the target completion LUT. + #define PCIEIP_REG_PCIEEP_CPL_LUT_DEL_ENT_LUID_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_CPL_LUT_DEL_ENT_DEN_E5 (0x1<<31) // This is a one-shot bit. Writing a one triggers the deletion of the target completion LUT entry that is specified in [LUID]. This is a self-clearing register field. Reading from this register field always returns a zero. + #define PCIEIP_REG_PCIEEP_CPL_LUT_DEL_ENT_DEN_E5_SHIFT 31 +#define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_K2 0x0008c8UL //Access:RW DataWidth:0x20 // TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. Note:: The target completion LUT (and associated target completion timeout event) is watching for received application completions (on XALI0/1/2) corresponding to previously received non-posted requests from the PCIe wire. + #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_K2 (0x7fffffff<<0) // This number selects one entry to delete of the TRGT_CPL_LUT. + #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_K2_SHIFT 0 + #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_K2 (0x1<<31) // This is a one shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'. + #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_K2_SHIFT 31 +#define PCIEIP_REG_PCIEEP_VER_NUM_E5 0x0008f8UL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PCIEEP_VER_TYPE_E5 0x0008fcUL //Access:R DataWidth:0x20 // +#define PCIEIP_REG_PL_LAST_OFF_K2 0x0008fcUL //Access:R DataWidth:0x20 // PL_LAST_OFF is an internally reserved register. Do not use. + #define PCIEIP_REG_PL_LAST_OFF_PL_LAST_K2 (0x1<<0) // PL_LAST is an internally reserved field. Do not use. + #define PCIEIP_REG_PL_LAST_OFF_PL_LAST_K2_SHIFT 0 #define PCIEIP_REG_TL_STATUS_0_BB 0x000900UL //Access:R DataWidth:0x20 // Split completion table entry. For Debug. #define PCIEIP_REG_TL_STATUS_0_DEVICE_NO_BB (0xf<<0) // Split table contents for tag0. this corresponds to Device_no[4:1] of PCIE header. #define PCIEIP_REG_TL_STATUS_0_DEVICE_NO_BB_SHIFT 0 @@ -4965,22 +7308,85 @@ #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_3_BB_SHIFT 24 #define PCIEIP_REG_PCIER_TL_STAT_RX_CTR_LO_BB 0x000a70UL //Access:R DataWidth:0x20 // RX TLP Statistics Low 32 bits. This register indicates the number of TLPs that have been trasmitted. It is cleared when reg_trx_tlp_stat_en goes from '0' to '1'. #define PCIEIP_REG_PCIER_TL_STAT_RX_CTR_HI_BB 0x000a74UL //Access:R DataWidth:0x20 // RX TLP Statistics High 32 bits. This register indicates the number of TLPs that have been trasmitted. It is cleared when reg_trx_tlp_stat_en goes from '0' to '1'. -#define PCIEIP_REG_PL_LTR_LATENCY_OFF_K2_E5 0x000b30UL //Access:RW DataWidth:0x20 // LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port, the register fields capture the corresponding fields in the LTR messages that are transmitted by the port. For a downstream port, the register fields capture the corresponding fields in the LTR messages that are received by the port. The full content of the register is reflected on the app_ltr_latency[31:0] output. - #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_K2_E5 (0x3ff<<0) // Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_K2_E5_SHIFT 0 - #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_K2_E5 (0x7<<10) // Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_K2_E5_SHIFT 10 - #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_K2_E5 (0x1<<15) // Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_K2_E5_SHIFT 15 - #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_K2_E5 (0x3ff<<16) // No Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_K2_E5_SHIFT 16 - #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_K2_E5 (0x7<<26) // No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_K2_E5_SHIFT 26 - #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_K2_E5 (0x1<<31) // No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_K2_E5_SHIFT 31 -#define PCIEIP_REG_AUX_CLK_FREQ_OFF_K2_E5 0x000b40UL //Access:RW DataWidth:0x20 // Auxiliary Clock Frequency Control Register. - #define PCIEIP_REG_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_K2_E5 (0x3ff<<0) // The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted. If the actual frequency (f) of aux_clk does not exactly match the programmed frequency (f_prog), then there is an error in the time counted by the core that can be expressed in percentage as: err% = (f_prog/f-1)*100. For example if f=2.5 MHz and f_prog=3 MHz, then err% =(3/2.5-1)*100 =20%, meaning that the time counted by the core on aux_clk will be 20% greater than the time in us programmed in the corresponding time register (for example T_POWER_ON). Note: This register field is sticky. - #define PCIEIP_REG_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_K2_E5_SHIFT 0 +#define PCIEIP_REG_PCIEEP_PL_LTR_LAT_E5 0x000b30UL //Access:RW DataWidth:0x20 // For an upstream port, the register fields capture the corresponding fields in the LTR messages that are transmitted by the port. For a downstream port, the register fields capture the corresponding fields in the LTR messages that are received by the port. The full content of the register is reflected on the app_ltr_latency output. + #define PCIEIP_REG_PCIEEP_PL_LTR_LAT_SLV_E5 (0x3ff<<0) // Snoop latency value. + #define PCIEIP_REG_PCIEEP_PL_LTR_LAT_SLV_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PL_LTR_LAT_SLS_E5 (0x7<<10) // Snoop latency scale. + #define PCIEIP_REG_PCIEEP_PL_LTR_LAT_SLS_E5_SHIFT 10 + #define PCIEIP_REG_PCIEEP_PL_LTR_LAT_SLR_E5 (0x1<<15) // Snoop latency requirement. + #define PCIEIP_REG_PCIEEP_PL_LTR_LAT_SLR_E5_SHIFT 15 + #define PCIEIP_REG_PCIEEP_PL_LTR_LAT_NSLV_E5 (0x3ff<<16) // No snoop latency value. + #define PCIEIP_REG_PCIEEP_PL_LTR_LAT_NSLV_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_PL_LTR_LAT_NSLS_E5 (0x7<<26) // No snoop latency scale. + #define PCIEIP_REG_PCIEEP_PL_LTR_LAT_NSLS_E5_SHIFT 26 + #define PCIEIP_REG_PCIEEP_PL_LTR_LAT_NSLR_E5 (0x1<<31) // No snoop latency requirement. + #define PCIEIP_REG_PCIEEP_PL_LTR_LAT_NSLR_E5_SHIFT 31 +#define PCIEIP_REG_PL_LTR_LATENCY_OFF_K2 0x000b30UL //Access:RW DataWidth:0x20 // LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port, the register fields capture the corresponding fields in the LTR messages that are transmitted by the port. For a downstream port, the register fields capture the corresponding fields in the LTR messages that are received by the port. The full content of the register is reflected on the app_ltr_latency[31:0] output. + #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_K2 (0x3ff<<0) // Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_K2_SHIFT 0 + #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_K2 (0x7<<10) // Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_K2_SHIFT 10 + #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_K2 (0x1<<15) // Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_K2_SHIFT 15 + #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_K2 (0x3ff<<16) // No Snoop Latency Value. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_K2_SHIFT 16 + #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_K2 (0x7<<26) // No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_K2_SHIFT 26 + #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_K2 (0x1<<31) // No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_K2_SHIFT 31 +#define PCIEIP_REG_PCIEEP_AUX_CLK_FREQ_E5 0x000b40UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_AUX_CLK_FREQ_UPC_SUPP_E5 (0x3ff<<0) // The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. + #define PCIEIP_REG_PCIEEP_AUX_CLK_FREQ_UPC_SUPP_E5_SHIFT 0 +#define PCIEIP_REG_AUX_CLK_FREQ_OFF_K2 0x000b40UL //Access:RW DataWidth:0x20 // Auxiliary Clock Frequency Control Register. + #define PCIEIP_REG_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_K2 (0x3ff<<0) // The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted. If the actual frequency (f) of aux_clk does not exactly match the programmed frequency (f_prog), then there is an error in the time counted by the core that can be expressed in percentage as: err% = (f_prog/f-1)*100. For example if f=2.5 MHz and f_prog=3 MHz, then err% =(3/2.5-1)*100 =20%, meaning that the time counted by the core on aux_clk will be 20% greater than the time in us programmed in the corresponding time register (for example T_POWER_ON). Note: This register field is sticky. + #define PCIEIP_REG_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_K2_SHIFT 0 +#define PCIEIP_REG_PCIEEP_L1_SUBSTATES_E5 0x000b44UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_L1_SUBSTATES_L1SUB_T_POWER_OFF_E5 (0x3<<0) // Duration (in us) of L1.2 entry. + #define PCIEIP_REG_PCIEEP_L1_SUBSTATES_L1SUB_T_POWER_OFF_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_L1_SUBSTATES_L1SUB_T_L1_2_E5 (0xf<<2) // Duration (in us) of L1.2. + #define PCIEIP_REG_PCIEEP_L1_SUBSTATES_L1SUB_T_L1_2_E5_SHIFT 2 + #define PCIEIP_REG_PCIEEP_L1_SUBSTATES_L1SUB_T_PCLKACK_E5 (0x3<<6) // Max delay (in 1 us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted. + #define PCIEIP_REG_PCIEEP_L1_SUBSTATES_L1SUB_T_PCLKACK_E5_SHIFT 6 +#define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_1_E5 0x000b80UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_1_NTS_E5 (0x3f<<0) // Num timing steps for lane margining at the receiver. + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_1_NTS_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_1_MTO_E5 (0x3f<<8) // Max timing offset for lane margining at the receiver. + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_1_MTO_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_1_NVS_E5 (0x7f<<16) // Num voltage steps for lane margining at the receiver. + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_1_NVS_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_1_MVO_E5 (0x3f<<24) // Max voltage offset for lane margining at the receiver. + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_1_MVO_E5_SHIFT 24 +#define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_E5 0x000b84UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_SRV_E5 (0x3f<<0) // Sample rate voltage for lane margining at the receiver. + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_SRV_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_SRT_E5 (0x3f<<8) // Sample rate timing for lane margining at the receiver. + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_SRT_E5_SHIFT 8 + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_MAX_LANES_E5 (0x1f<<16) // Max lanes for lane margining at the receiver. + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_MAX_LANES_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_VOLT_SUP_E5 (0x1<<24) // Voltage supported for lane margining at the receiver. + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_VOLT_SUP_E5_SHIFT 24 + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_IUDV_E5 (0x1<<25) // Ind up down voltage for lane margining at the receiver. + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_IUDV_E5_SHIFT 25 + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_ILRT_E5 (0x1<<26) // Ind left right timing for lane margining at the receiver. + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_ILRT_E5_SHIFT 26 + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_SRM_E5 (0x1<<27) // Sample reporting method for lane margining at the receiver. + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_SRM_E5_SHIFT 27 + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_IES_E5 (0x1<<28) // Ind error sampler for lane margining at the receiver. + #define PCIEIP_REG_PCIEEP_GEN4_LANE_MARGINING_2_IES_E5_SHIFT 28 +#define PCIEIP_REG_PCIEEP_PIPE_REL_E5 0x000b90UL //Access:R DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_PIPE_REL_RX_MSG_WBUF_DEPTH_E5 (0xf<<0) // Rx message bus write buffer depth. + #define PCIEIP_REG_PCIEEP_PIPE_REL_RX_MSG_WBUF_DEPTH_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_PIPE_REL_TX_MSG_WBUF_DEPTH_E5 (0xf<<4) // Tx message bus write buffer depth. + #define PCIEIP_REG_PCIEEP_PIPE_REL_TX_MSG_WBUF_DEPTH_E5_SHIFT 4 +#define PCIEIP_REG_PCIEEP_RX_SER_Q_CTRL_E5 0x000c00UL //Access:RW DataWidth:0x20 // + #define PCIEIP_REG_PCIEEP_RX_SER_Q_CTRL_AF_THRES_E5 (0xffff<<0) // Current almost full threshold. + #define PCIEIP_REG_PCIEEP_RX_SER_Q_CTRL_AF_THRES_E5_SHIFT 0 + #define PCIEIP_REG_PCIEEP_RX_SER_Q_CTRL_AF_THRES_VAL_E5 (0xfff<<16) // Almost full threshold adjustment value. + #define PCIEIP_REG_PCIEEP_RX_SER_Q_CTRL_AF_THRES_VAL_E5_SHIFT 16 + #define PCIEIP_REG_PCIEEP_RX_SER_Q_CTRL_AF_THRES_SIGN_E5 (0x1<<30) // Almost full threshold adjustment sign. + #define PCIEIP_REG_PCIEEP_RX_SER_Q_CTRL_AF_THRES_SIGN_E5_SHIFT 30 + #define PCIEIP_REG_PCIEEP_RX_SER_Q_CTRL_QOF_PRV_EN_E5 (0x1<<31) // Enable receive serialization queue overflow prevention. + #define PCIEIP_REG_PCIEEP_RX_SER_Q_CTRL_QOF_PRV_EN_E5_SHIFT 31 #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_BB 0x000c00UL //Access:RW DataWidth:0x20 // Main status and control register for the PL DL Debug FIFO. Trigger and status shown in this register. For the above two bits, 0b10 is ready but not triggered, 0b11 is actively collecting and triggered, and 0b01 is that the DBG FIFO has collected all needed data. #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_PRETRIG_CNT_BB (0xff<<0) // When non-zero, indicates the maximum number of entries collected and saved prior to the trigger. #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_PRETRIG_CNT_BB_SHIFT 0 @@ -6845,497 +9251,968 @@ #define PCIEIP_REG_MISC_DBG_STATUS_USER_ALLOW_GEN3_SYNC_BB_SHIFT 0 #define PCIEIP_REG_MISC_DBG_STATUS_UNUSED_BB (0x7fffffff<<1) // #define PCIEIP_REG_MISC_DBG_STATUS_UNUSED_BB_SHIFT 1 -#define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_K2_E5 0x000000UL //Access:R DataWidth:0x20 // Device ID and Vendor ID Register. - #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_K2_E5 (0xffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. - #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_K2_E5 (0xffff<<16) // Device ID. Vendor Assigned Device Identifier. - #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_K2_E5_SHIFT 16 -#define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_K2_E5 0x000004UL //Access:RW DataWidth:0x20 // Command and Status Register. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_K2_E5 (0x1<<0) // Enables IO Access Response. You cannot write to this register if your configuration has no IO bars; that is, the internal signal has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_K2_E5 (0x1<<1) // Enables Memory Access Response. You cannot write to this register if your configuration has no MEM bars; that is, the internal signal has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_K2_E5_SHIFT 1 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_K2_E5 (0x1<<2) // Bus Master Enable. Controls Issuing of Memory and I/O Requests. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_K2_E5_SHIFT 2 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_K2_E5 (0x1<<3) // Special Cycle Enable. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_K2_E5_SHIFT 3 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_K2_E5 (0x1<<4) // Memory Write and Invalidate. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_K2_E5_SHIFT 4 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_K2_E5 (0x1<<5) // VGA Palette Snoop. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_K2_E5_SHIFT 5 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_K2_E5 (0x1<<6) // Controls Logging of Poisoned TLPs. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_K2_E5_SHIFT 6 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_K2_E5 (0x1<<7) // IDSEL Stepping. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_K2_E5_SHIFT 7 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_K2_E5 (0x1<<8) // Enables Error Reporting. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_K2_E5_SHIFT 8 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_K2_E5 (0x1<<10) // Controls generation of interrupts by a function. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_K2_E5_SHIFT 10 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_RESERV_K2_E5 (0x1f<<11) // Reserved. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_RESERV_K2_E5_SHIFT 11 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_INT_STATUS_K2_E5 (0x1<<19) // Emulation interrupt pending. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_INT_STATUS_K2_E5_SHIFT 19 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_CAP_LIST_K2_E5 (0x1<<20) // Extended Capability. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_CAP_LIST_K2_E5_SHIFT 20 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_66MHZ_CAP_K2_E5 (0x1<<21) // PCI 66MHz Capability. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_66MHZ_CAP_K2_E5_SHIFT 21 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_B2B_CAP_K2_E5 (0x1<<23) // Fast Back to Back Transaction Capable and Enable. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_B2B_CAP_K2_E5_SHIFT 23 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_MASTER_DPE_K2_E5 (0x1<<24) // Controls poisoned Completion and Request error reporting. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_MASTER_DPE_K2_E5_SHIFT 24 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DEV_SEL_TIMING_K2_E5 (0x3<<25) // Device Select Timing. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DEV_SEL_TIMING_K2_E5_SHIFT 25 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_K2_E5 (0x1<<27) // Completer Abort Error. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_K2_E5_SHIFT 27 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_K2_E5 (0x1<<28) // Completer Abort received. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_K2_E5_SHIFT 28 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_K2_E5 (0x1<<29) // Unsupported request completion status received. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_K2_E5_SHIFT 29 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_K2_E5 (0x1<<30) // Fatal or Non-Fatal Error Message sent by function. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_K2_E5_SHIFT 30 - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_K2_E5 (0x1<<31) // Poisoned TLP received by function. - #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_K2_E5_SHIFT 31 -#define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_K2_E5 0x000008UL //Access:R DataWidth:0x20 // Class Code and Revision ID Register. - #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_REVISION_ID_K2_E5 (0xff<<0) // Vendor chosen Revision ID. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_REVISION_ID_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_K2_E5 (0xff<<8) // Class Code Programming Interface. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_K2_E5_SHIFT 8 - #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_K2_E5 (0xff<<16) // Subclass Code to represent Device Type. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_K2_E5_SHIFT 16 - #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_K2_E5 (0xff<<24) // Base Class Code to represent Device Type. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_K2_E5_SHIFT 24 -#define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_K2_E5 0x00000cUL //Access:R DataWidth:0x20 // BIST, Header Type, Cache Line Size, and Latency Timer Registers. - #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_K2_E5 (0xff<<0) // Cache Line Size. Has no effect on PCIe device behavior. - #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2_E5 (0xff<<8) // Does not apply to PCI Express. - #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2_E5_SHIFT 8 - #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_K2_E5 (0x7f<<16) // Specifies Header Type. - #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_K2_E5_SHIFT 16 - #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_K2_E5 (0x1<<23) // Specifies whether device is multifunction. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_K2_E5_SHIFT 23 - #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_K2_E5 (0xff<<24) // Optional for BIST support. - #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_K2_E5_SHIFT 24 -#define PCIEIP_VF_REG_VF_BAR0_REG_K2_E5 0x000010UL //Access:R DataWidth:0x20 // BAR0 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_MEM_IO_K2_E5 (0x1<<0) // BAR0 Memory Space Indicator. - #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_MEM_IO_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_TYPE_K2_E5 (0x3<<1) // BAR0 32-bit or 64-bit. - #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_PREFETCH_K2_E5 (0x1<<3) // BAR0 Prefetchable. - #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_START_K2_E5 (0xfffffff<<4) // BAR0 Base Address. - #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_START_K2_E5_SHIFT 4 -#define PCIEIP_VF_REG_VF_BAR1_REG_K2_E5 0x000014UL //Access:R DataWidth:0x20 // BAR1 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_MEM_IO_K2_E5 (0x1<<0) // BAR1 Memory Space Indicator. - #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_MEM_IO_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_TYPE_K2_E5 (0x3<<1) // BAR1 32-bit or 64-bit. - #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_PREFETCH_K2_E5 (0x1<<3) // BAR1 Prefetchable. - #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_START_K2_E5 (0xfffffff<<4) // BAR1 Base Address. - #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_START_K2_E5_SHIFT 4 -#define PCIEIP_VF_REG_VF_BAR2_REG_K2_E5 0x000018UL //Access:R DataWidth:0x20 // BAR2 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_MEM_IO_K2_E5 (0x1<<0) // BAR2 Memory Space Indicator. - #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_MEM_IO_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_TYPE_K2_E5 (0x3<<1) // BAR2 32-bit or 64-bit. - #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_PREFETCH_K2_E5 (0x1<<3) // BAR2 Prefetchable. - #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_START_K2_E5 (0xfffffff<<4) // BAR2 Base Address. - #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_START_K2_E5_SHIFT 4 -#define PCIEIP_VF_REG_VF_BAR3_REG_K2_E5 0x00001cUL //Access:R DataWidth:0x20 // BAR3 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_MEM_IO_K2_E5 (0x1<<0) // BAR3 Memory Space Indicator. - #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_MEM_IO_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_TYPE_K2_E5 (0x3<<1) // BAR3 32-bit or 64-bit. - #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_PREFETCH_K2_E5 (0x1<<3) // BAR3 Prefetchable. - #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_START_K2_E5 (0xfffffff<<4) // BAR3 Base Address. - #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_START_K2_E5_SHIFT 4 -#define PCIEIP_VF_REG_VF_BAR4_REG_K2_E5 0x000020UL //Access:R DataWidth:0x20 // BAR4 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_MEM_IO_K2_E5 (0x1<<0) // BAR4 Memory Space Indicator. - #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_MEM_IO_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_TYPE_K2_E5 (0x3<<1) // BAR4 32-bit or 64-bit. - #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_PREFETCH_K2_E5 (0x1<<3) // BAR4 Prefetchable. - #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_START_K2_E5 (0xfffffff<<4) // BAR4 Base Address. - #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_START_K2_E5_SHIFT 4 -#define PCIEIP_VF_REG_VF_BAR5_REG_K2_E5 0x000024UL //Access:R DataWidth:0x20 // BAR5 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_MEM_IO_K2_E5 (0x1<<0) // BAR5 Memory Space Indicator. - #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_MEM_IO_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_TYPE_K2_E5 (0x3<<1) // BAR5 32-bit or 64-bit. - #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_TYPE_K2_E5_SHIFT 1 - #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_PREFETCH_K2_E5 (0x1<<3) // BAR5 Prefetchable. - #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_PREFETCH_K2_E5_SHIFT 3 - #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_START_K2_E5 (0xfffffff<<4) // BAR5 Base Address. - #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_START_K2_E5_SHIFT 4 -#define PCIEIP_VF_REG_VF_CARDBUS_CIS_PTR_REG_K2_E5 0x000028UL //Access:R DataWidth:0x20 // CardBus CIS Pointer Register. -#define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_K2_E5 0x00002cUL //Access:RW DataWidth:0x20 // Subsystem ID and Subsystem Vendor ID Register. - #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_K2_E5 (0xffff<<0) // Subsystem Vendor ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_K2_E5 (0xffff<<16) // Subsystem Device ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_K2_E5_SHIFT 16 -#define PCIEIP_VF_REG_VF_PCI_CAP_PTR_REG_K2_E5 0x000034UL //Access:R DataWidth:0x20 // Capability Pointer Register. - #define PCIEIP_VF_REG_VF_PCI_CAP_PTR_REG_CAP_POINTER_K2_E5 (0xff<<0) // Pointer to first item in the PCI Capability Structure. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_PCI_CAP_PTR_REG_CAP_POINTER_K2_E5_SHIFT 0 -#define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_K2_E5 0x00003cUL //Access:R DataWidth:0x20 // Interrupt Line and Pin Register. - #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_K2_E5 (0xff<<0) // PCI Compatible Interrupt Line Routing Register Field. - #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_K2_E5 (0xff<<8) // PCI Compatible Interrupt Pin Register Field. - #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_K2_E5_SHIFT 8 -#define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_K2_E5 0x000070UL //Access:RW DataWidth:0x20 // PCI Express Capabilities, ID, Next Pointer Register. - #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_K2_E5 (0xff<<0) // PCIE Capability ID. - #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_K2_E5 (0xff<<8) // PCIE Next Capability Pointer. - #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_K2_E5_SHIFT 8 - #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_K2_E5 (0xf<<16) // PCIE Capability Version Number. - #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_K2_E5_SHIFT 16 - #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_K2_E5 (0xf<<20) // PCIE Device/PortType. - #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_K2_E5_SHIFT 20 - #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_K2_E5 (0x1<<24) // PCIe Slot Implemented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_K2_E5_SHIFT 24 - #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_K2_E5 (0x1f<<25) // PCIE Interrupt Message Number. - #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_K2_E5_SHIFT 25 - #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_K2_E5 (0x1<<30) // Reserved. - #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_K2_E5_SHIFT 30 -#define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_K2_E5 0x000074UL //Access:RW DataWidth:0x20 // Device Capabilities Register. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_K2_E5 (0x7<<0) // Max Payload Size Supported. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_K2_E5 (0x3<<3) // Phantom Functions Supported. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_K2_E5_SHIFT 3 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_K2_E5 (0x1<<5) // Extended Tag Field Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_K2_E5_SHIFT 5 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_K2_E5 (0x7<<6) // Applies to endpoints only L0s acceptable latency. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_K2_E5_SHIFT 6 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_K2_E5 (0x7<<9) // Applies to endpoints only L1 acceptable latency. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_K2_E5_SHIFT 9 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2_E5 (0x1<<15) // Role-based Error Reporting Implemented. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2_E5_SHIFT 15 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_K2_E5 (0xff<<18) // Captured Slot Power Limit Value. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_K2_E5_SHIFT 18 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_K2_E5 (0x3<<26) // Captured Slot Power Limit Scale. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_K2_E5_SHIFT 26 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_K2_E5 (0x1<<28) // Function Level Reset Capability (endpoints only). - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_K2_E5_SHIFT 28 -#define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_K2_E5 0x000078UL //Access:RW DataWidth:0x20 // Device Control and Status Register. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_K2_E5 (0x1<<0) // Correctable Error Reporting Enable. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2_E5 (0x1<<1) // Non-fatal Error Reporting Enable. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2_E5_SHIFT 1 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_K2_E5 (0x1<<2) // Fatal Error Reporting Enable. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_K2_E5_SHIFT 2 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_K2_E5 (0x1<<3) // Unsupported Request Reporting Enable. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_K2_E5_SHIFT 3 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_K2_E5 (0x1<<4) // Enable Relaxed Ordering. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_K2_E5_SHIFT 4 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_K2_E5 (0x7<<5) // Max Payload Size. Max_Payload_Size . This field sets maximum TLP payload size for the Function. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities register (DEVICE_CAPABILITIES_REG). - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_K2_E5_SHIFT 5 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_K2_E5 (0x1<<8) // Extended Tag Field Enable. The write value is gated with the PCIE_CAP_EXT_TAG_SUPP field of DEVICE_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_K2_E5_SHIFT 8 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_K2_E5 (0x1<<9) // Phantom Functions Enable. The write value is gated with the PCIE_CAP_PHANTOM_FUNC_SUPPORT field of DEVICE_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_K2_E5_SHIFT 9 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_K2_E5 (0x1<<10) // Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_K2_E5_SHIFT 10 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_K2_E5 (0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_K2_E5_SHIFT 11 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_K2_E5 (0x7<<12) // Max Read Request Size. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_K2_E5_SHIFT 12 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_K2_E5 (0x1<<15) // Initiate Function Level Reset (for endpoints). - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_K2_E5_SHIFT 15 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_K2_E5 (0x1<<16) // Correctable Error Detected Status. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_K2_E5_SHIFT 16 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2_E5 (0x1<<17) // Non-Fatal Error Detected Status. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2_E5_SHIFT 17 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_K2_E5 (0x1<<18) // Fatal Error Detected Status. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_K2_E5_SHIFT 18 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_K2_E5 (0x1<<19) // Unsupported Request Detected Status. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_K2_E5_SHIFT 19 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_K2_E5 (0x1<<20) // Aux Power Detected Status. This bit is derived by sampling the sys_aux_pwr_det input. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_K2_E5_SHIFT 20 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_K2_E5 (0x1<<21) // Transactions Pending Status. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_K2_E5_SHIFT 21 -#define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_K2_E5 0x00007cUL //Access:RW DataWidth:0x20 // Link Capabilities Register. - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_K2_E5 (0xf<<0) // Maximum Link Speed. In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_K2_E5 (0x3f<<4) // Maximum Link Width. In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_K2_E5_SHIFT 4 - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_K2_E5 (0x3<<10) // Level of ASPM (Active State Power Management) Support. - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_K2_E5_SHIFT 10 - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_K2_E5 (0x7<<12) // LOs Exit Latency. There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the core and which one is accessed by a read request. Common Clock operation is supported (possible) in the core when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the core when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location. - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_K2_E5_SHIFT 12 - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_K2_E5 (0x7<<15) // L1 Exit Latency. There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the core and which one is accessed by a read request. Common Clock operation is supported (possible) in the core when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the core when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location. - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_K2_E5_SHIFT 15 - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_K2_E5 (0x1<<18) // Clock Power Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_K2_E5_SHIFT 18 - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_K2_E5 (0x1<<19) // Surprise Down Error Reporting Capable. - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_K2_E5_SHIFT 19 - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_K2_E5 (0x1<<20) // Data Link Layer Link Active Reporting Capable. - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_K2_E5_SHIFT 20 - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_K2_E5 (0x1<<21) // Link Bandwidth Notification Capable. - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_K2_E5_SHIFT 21 - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_K2_E5 (0x1<<22) // ASPM Optionality Compliance. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_K2_E5_SHIFT 22 - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_K2_E5 (0xff<<24) // Port Number. - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_K2_E5_SHIFT 24 -#define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_K2_E5 0x000080UL //Access:RW DataWidth:0x20 // Link Control and Status Register. - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_K2_E5 (0x3<<0) // Active State Power Management (ASPM) Control. - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_K2_E5 (0x1<<3) // Read Completion Boundary (RCB). - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_K2_E5_SHIFT 3 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_K2_E5 (0x1<<4) // Initiate Link Disable. In a DSP that supports crosslink, the core gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF. Note: The access attributes of this field are as follows: - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_K2_E5_SHIFT 4 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_K2_E5 (0x1<<5) // Initiate Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_K2_E5_SHIFT 5 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_K2_E5 (0x1<<6) // Common Clock Configuration. - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_K2_E5_SHIFT 6 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_K2_E5 (0x1<<7) // Extended Synch. - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_K2_E5_SHIFT 7 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_K2_E5 (0x1<<8) // Enable Clock Power Management. The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RW : RO - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_K2_E5_SHIFT 8 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_K2_E5 (0x1<<9) // Hardware Autonomous Width Disable. - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_K2_E5_SHIFT 9 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_K2_E5 (0x1<<10) // Link Bandwidth Management Interrupt Enable. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_K2_E5_SHIFT 10 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_K2_E5 (0x1<<11) // Link Autonomous Bandwidth Management Interrupt Enable. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_K2_E5_SHIFT 11 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_K2_E5 (0x3<<14) // DRS Signaling Control. - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_K2_E5_SHIFT 14 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_K2_E5 (0xf<<16) // Current Link Speed. - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_K2_E5_SHIFT 16 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_K2_E5 (0x3f<<20) // Negotiated Link Width. - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_K2_E5_SHIFT 20 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_K2_E5 (0x1<<27) // LTSSM is in Configuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_K2_E5_SHIFT 27 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_K2_E5 (0x1<<28) // Slot Clock Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_K2_E5_SHIFT 28 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_K2_E5 (0x1<<29) // Data Link Layer Active. - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_K2_E5_SHIFT 29 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_K2_E5 (0x1<<30) // Link Bandwidth Management Status. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_K2_E5_SHIFT 30 - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_K2_E5 (0x1<<31) // Link Autonomous Bandwidth Status. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO - #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_K2_E5_SHIFT 31 -#define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_K2_E5 0x000094UL //Access:R DataWidth:0x20 // Device Capabilities 2 Register. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_K2_E5 (0xf<<0) // Completion Timeout Ranges Supported. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_K2_E5 (0x1<<4) // Completion Timeout Disable Supported. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_K2_E5_SHIFT 4 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_K2_E5 (0x1<<5) // ARI Forwarding Supported. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_K2_E5_SHIFT 5 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_K2_E5 (0x1<<6) // Atomic Operation Routing Supported. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_K2_E5_SHIFT 6 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2_E5 (0x1<<7) // 32 Bit AtomicOp Completer Supported. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2_E5_SHIFT 7 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2_E5 (0x1<<8) // 64 Bit AtomicOp Completer Supported. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2_E5_SHIFT 8 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_K2_E5 (0x1<<9) // 128 Bit CAS Completer Supported. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_K2_E5_SHIFT 9 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_K2_E5 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_K2_E5_SHIFT 10 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_K2_E5 (0x1<<11) // LTR Mechanism Supported. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_K2_E5_SHIFT 11 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_K2_E5 (0x1<<12) // TPH Completer Supported Bit 0. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_K2_E5_SHIFT 12 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_K2_E5 (0x1<<13) // TPH Completer Supported Bit 1. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_K2_E5_SHIFT 13 - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_K2_E5 (0x3<<18) // (OBFF) Optimized Buffer Flush/fill Supported. - #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_K2_E5_SHIFT 18 -#define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_K2_E5 0x000098UL //Access:R DataWidth:0x20 // Device Control 2 and Status 2 Register. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_K2_E5 (0xf<<0) // Completion Timeout Value. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_K2_E5 (0x1<<4) // Completion Timeout Disable. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_K2_E5_SHIFT 4 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_K2_E5 (0x1<<5) // ARI Forwarding Enable. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_K2_E5_SHIFT 5 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN_K2_E5 (0x1<<6) // AtomicOp Requester Enable. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN_K2_E5_SHIFT 6 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_K2_E5 (0x1<<7) // AtomicOp Egress Blocking. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_K2_E5_SHIFT 7 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_K2_E5 (0x1<<8) // IDO Request Enable. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_K2_E5_SHIFT 8 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN_K2_E5 (0x1<<9) // IDO Completion Enable. - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN_K2_E5_SHIFT 9 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_K2_E5 (0x1<<10) // LTR Mechanism Enable. The write value is gated with the PCIE_CAP_LTR_SUPP field of DEVICE_CAPABILITIES2_REG. Note: RW for function #0 and RsdvP for all other functions - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_K2_E5_SHIFT 10 - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_OBFF_EN_K2_E5 (0x3<<13) // OBFF Enable. Note: RW for function #0 and RsdvP for all other functions - #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_OBFF_EN_K2_E5_SHIFT 13 -#define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_K2_E5 0x00009cUL //Access:RW DataWidth:0x20 // Link Capabilities 2 Register. - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_K2_E5 (0x7f<<1) // Supported Link Speeds Vector. This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register. - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_K2_E5_SHIFT 1 - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_K2_E5 (0x1<<8) // Cross Link Supported. - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_K2_E5_SHIFT 8 - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_K2_E5 (0x1<<31) // DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_K2_E5_SHIFT 31 -#define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_K2_E5 0x0000a0UL //Access:RW DataWidth:0x20 // Link Control 2 and Status 2 Register. - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_K2_E5 (0xf<<0) // Target Link Speed. In M-PCIe mode, the contents of this field are derived from other registers. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_K2_E5 (0x1<<4) // Enter Compliance Mode. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_K2_E5_SHIFT 4 - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_K2_E5 (0x1<<5) // Hardware Autonomous Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_K2_E5_SHIFT 5 - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_K2_E5 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_K2_E5_SHIFT 6 - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_K2_E5 (0x7<<7) // Controls Transmit Margin for Debug or Compliance. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_K2_E5_SHIFT 7 - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_K2_E5 (0x1<<10) // Enter Modified Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_K2_E5_SHIFT 10 - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_K2_E5 (0x1<<11) // Sets Compliance Skip Ordered Sets transmission. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_K2_E5_SHIFT 11 - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_K2_E5 (0xf<<12) // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_K2_E5_SHIFT 12 - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_K2_E5 (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is always 0x0. In C-PCIe mode, its contents are derived by sampling the PIPE - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_K2_E5_SHIFT 16 - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_K2_E5 (0x1<<17) // Equalization 8.0GT/s Complete. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_K2_E5_SHIFT 17 - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_K2_E5 (0x1<<18) // Equalization 8.0GT/s Phase 1 Successful. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_K2_E5_SHIFT 18 - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_K2_E5 (0x1<<19) // Equalization 8.0GT/s Phase 2 Successful. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_K2_E5_SHIFT 19 - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_K2_E5 (0x1<<20) // Equalization 8.0GT/s Phase 3 Successful. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_K2_E5_SHIFT 20 - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_K2_E5 (0x1<<21) // Link Equalization Request 8.0GT/s. - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_K2_E5_SHIFT 21 - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_K2_E5 (0x7<<28) // Downstream Component Presence. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0. - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_K2_E5_SHIFT 28 - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_K2_E5 (0x1<<31) // DRS Message Received. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0. - #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_K2_E5_SHIFT 31 -#define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_K2_E5 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next Pointer, Control Registers. - #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2_E5 (0xff<<0) // MSI-X Capability ID. - #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2_E5 (0xff<<8) // MSI-X Next Capability Pointer. - #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2_E5_SHIFT 8 - #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_K2_E5 (0x7ff<<16) // MSI-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PCI_MSIX_TABLE_SIZE field in VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG). To write this common value, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_SIZE field in the PF PCI_MSIX_CAP_ID_NEXT_CTRL_REG register. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - Dbi2: R - #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_K2_E5_SHIFT 16 - #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_K2_E5 (0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_K2_E5_SHIFT 30 - #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_K2_E5 (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_K2_E5_SHIFT 31 -#define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_K2_E5 0x0000b4UL //Access:R DataWidth:0x20 // MSI-X Table Offset and BIR Register. - #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_K2_E5 (0x7<<0) // MSI-X Table Bar Indicator Register Field. - #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_K2_E5 (0x1fffffff<<3) // MSI-X Table Offset. - #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_K2_E5_SHIFT 3 -#define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_K2_E5 0x0000b8UL //Access:R DataWidth:0x20 // MSI-X PBA Offset and BIR Register. - #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_K2_E5 (0x7<<0) // MSI-X PBA BIR. - #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_K2_E5 (0x1fffffff<<3) // MSI-X PBA Offset. - #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_K2_E5_SHIFT 3 -#define PCIEIP_VF_REG_VF_ARI_BASE_K2_E5 0x000100UL //Access:RW DataWidth:0x20 // ARI Capability Header. - #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_PCIE_EXTENDED_CAP_ID_K2_E5 (0xffff<<0) // ARI Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_PCIE_EXTENDED_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_CAP_VERSION_K2_E5 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_CAP_VERSION_K2_E5_SHIFT 16 - #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_NEXT_OFFSET_K2_E5 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_NEXT_OFFSET_K2_E5_SHIFT 20 -#define PCIEIP_VF_REG_VF_CAP_REG_K2_E5 0x000104UL //Access:R DataWidth:0x20 // ARI Capability and Control Register. - #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_CAP_K2_E5 (0x1<<0) // Multi Functional Virtual Channel (MFVC) Function Groups Capability. - #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_CAP_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_CAP_K2_E5 (0x1<<1) // ACS Function Groups Capability. - #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_CAP_K2_E5_SHIFT 1 - #define PCIEIP_VF_REG_VF_CAP_REG_ARI_NEXT_FUN_NUM_K2_E5 (0xff<<8) // Next Function Number. - #define PCIEIP_VF_REG_VF_CAP_REG_ARI_NEXT_FUN_NUM_K2_E5_SHIFT 8 - #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_EN_K2_E5 (0x1<<16) // MFVC Function Groups Enable. - #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_EN_K2_E5_SHIFT 16 - #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_EN_K2_E5 (0x1<<17) // ACS Function Groups Enable. - #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_EN_K2_E5_SHIFT 17 - #define PCIEIP_VF_REG_VF_CAP_REG_ARI_FUN_GRP_K2_E5 (0x7<<20) // Function Group. - #define PCIEIP_VF_REG_VF_CAP_REG_ARI_FUN_GRP_K2_E5_SHIFT 20 -#define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_K2_E5 0x000110UL //Access:RW DataWidth:0x20 // TPH Extended Capability Header. - #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_K2_E5 (0xffff<<0) // TPH Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_K2_E5 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_K2_E5_SHIFT 16 - #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_K2_E5 (0xfff<<20) // Next Capability Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_K2_E5_SHIFT 20 -#define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_K2_E5 0x000114UL //Access:R DataWidth:0x20 // TPH Requestor Capability Register. SRIOV Note: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common register, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PF TPH_REQ_CAP_REG_REG register. - #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_K2_E5 (0x1<<0) // No ST Mode Supported. - #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_K2_E5 (0x1<<1) // Interrupt Vector Mode Supported. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_K2_E5_SHIFT 1 - #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_K2_E5 (0x1<<2) // Device Specific Mode Supported. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_K2_E5_SHIFT 2 - #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_K2_E5 (0x1<<8) // Extended TPH Requester Supported. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_K2_E5_SHIFT 8 - #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_K2_E5 (0x1<<9) // ST Table Location Bit 0. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_K2_E5_SHIFT 9 - #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_K2_E5 (0x1<<10) // ST Table Location Bit 1. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_K2_E5_SHIFT 10 - #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_K2_E5 (0x7ff<<16) // ST Table Size. Note: This register field is sticky. - #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_K2_E5_SHIFT 16 -#define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_K2_E5 0x000118UL //Access:RW DataWidth:0x20 // TPH Requestor Control Register. - #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_K2_E5 (0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W - #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_K2_E5 (0x3<<8) // TPH Requester Enable Bit. - #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_K2_E5_SHIFT 8 -#define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_K2_E5 0x00011cUL //Access:RW DataWidth:0x20 // TPH ST Table Register 0. - #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_K2_E5 (0xff<<0) // ST Table 0 Lower Byte. Note: The access attributes of this field are as follows: - Dbi: this field is RW or Tie to 0 by table size configure - #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_K2_E5_SHIFT 0 - #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_K2_E5 (0xff<<8) // ST Table 0 Upper Byte. Note: The access attributes of this field are as follows: - Dbi: this field is RW or Tie to 0 by table size configure - #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_K2_E5_SHIFT 8 -#define PCIEIP_SHADOW_REG_BAR0_MASK_REG_K2_E5 0x000010UL //Access:W DataWidth:0x20 // BAR0 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_K2_E5 (0x1<<0) // BAR0 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_K2_E5_SHIFT 0 - #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_K2_E5 (0x7fffffff<<1) // BAR0 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_K2_E5_SHIFT 1 -#define PCIEIP_SHADOW_REG_BAR1_MASK_REG_K2_E5 0x000014UL //Access:RW DataWidth:0x20 // BAR1 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_K2_E5 (0x1<<0) // BAR1 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_K2_E5_SHIFT 0 - #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_K2_E5 (0x7fffffff<<1) // BAR1 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_K2_E5_SHIFT 1 -#define PCIEIP_SHADOW_REG_BAR4_MASK_REG_K2_E5 0x000020UL //Access:W DataWidth:0x20 // BAR4 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_K2_E5 (0x1<<0) // BAR4 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_K2_E5_SHIFT 0 - #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_K2_E5 (0x7fffffff<<1) // BAR4 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_K2_E5_SHIFT 1 -#define PCIEIP_SHADOW_REG_BAR5_MASK_REG_K2_E5 0x000024UL //Access:W DataWidth:0x20 // BAR5 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_K2_E5 (0x1<<0) // BAR5 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_K2_E5_SHIFT 0 - #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_K2_E5 (0x7fffffff<<1) // BAR5 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_K2_E5_SHIFT 1 -#define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_K2_E5 0x000030UL //Access:R DataWidth:0x20 // Expansion ROM BAR and Mask Register. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_K2_E5 (0x1<<0) // Expansion ROM Bar Mask Register Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if ROM_BAR_ENABLED then W else R - #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_K2_E5_SHIFT 0 - #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_MASK_K2_E5 (0x7fffffff<<1) // Expansion ROM Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if ROM_BAR_ENABLED then W else R - #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_MASK_K2_E5_SHIFT 1 -#define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_K2_E5 0x0001c4UL //Access:R DataWidth:0x20 // TotalVFs InitialVFs Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two of these registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. - #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_SHADOW_SRIOV_INITIAL_VFS_K2_E5 (0xffff<<0) // InitialVFs. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two InitialVFs registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W - #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_SHADOW_SRIOV_INITIAL_VFS_K2_E5_SHIFT 0 - #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_SHADOW_SRIOV_TOTAL_VFS_K2_E5 (0xffff<<16) // Total VFs (Max Number of VFs). For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two TotalVFs registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W - #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_SHADOW_SRIOV_TOTAL_VFS_K2_E5_SHIFT 16 -#define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_K2_E5 0x0001ccUL //Access:R DataWidth:0x20 // VF Stride and Offset Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. - #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_SHADOW_SRIOV_VF_STRIDE_K2_E5 (0xffff<<0) // VF Stride. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two VF Stride registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W - #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_SHADOW_SRIOV_VF_STRIDE_K2_E5_SHIFT 0 - #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_SHADOW_SRIOV_VF_OFFSET_K2_E5 (0xffff<<16) // First VF Offset. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two First VF Offset registers at this address location; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W - #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_SHADOW_SRIOV_VF_OFFSET_K2_E5_SHIFT 16 -#define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_K2_E5 0x0001dcUL //Access:W DataWidth:0x20 // BAR0 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_ENABLED_K2_E5 (0x1<<0) // BAR0 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_ENABLED_K2_E5_SHIFT 0 - #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_MASK_K2_E5 (0x7fffffff<<1) // BAR0 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_MASK_K2_E5_SHIFT 1 -#define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_K2_E5 0x0001e0UL //Access:RW DataWidth:0x20 // BAR1 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_ENABLED_K2_E5 (0x1<<0) // BAR1 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_ENABLED_K2_E5_SHIFT 0 - #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_MASK_K2_E5 (0x7fffffff<<1) // BAR1 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_MASK_K2_E5_SHIFT 1 -#define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_K2_E5 0x0001e4UL //Access:W DataWidth:0x20 // BAR2 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_ENABLED_K2_E5 (0x1<<0) // BAR2 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_ENABLED_K2_E5_SHIFT 0 - #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_MASK_K2_E5 (0x7fffffff<<1) // BAR2 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_MASK_K2_E5_SHIFT 1 -#define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_K2_E5 0x0001e8UL //Access:RW DataWidth:0x20 // BAR3 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_ENABLED_K2_E5 (0x1<<0) // BAR3 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_ENABLED_K2_E5_SHIFT 0 - #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_MASK_K2_E5 (0x7fffffff<<1) // BAR3 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_MASK_K2_E5_SHIFT 1 -#define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_K2_E5 0x0001ecUL //Access:W DataWidth:0x20 // BAR4 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_ENABLED_K2_E5 (0x1<<0) // BAR4 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_ENABLED_K2_E5_SHIFT 0 - #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_MASK_K2_E5 (0x7fffffff<<1) // BAR4 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_MASK_K2_E5_SHIFT 1 -#define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_K2_E5 0x0001f0UL //Access:RW DataWidth:0x20 // BAR5 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". - #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_ENABLED_K2_E5 (0x1<<0) // BAR5 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_ENABLED_K2_E5_SHIFT 0 - #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_MASK_K2_E5 (0x7fffffff<<1) // BAR5 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. - #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_MASK_K2_E5_SHIFT 1 +#define PCIEIP_VF_REG_PCIEEPVF_ID_E5 0x000000UL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_ID_VENDID_E5 (0xffff<<0) // Vendor ID. For SR-IOV VFs always 0xFFFF. + #define PCIEIP_VF_REG_PCIEEPVF_ID_VENDID_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_ID_DEVID_E5 (0xffff<<16) // Device ID. For SR-IOV VFs always 0xFFFF. + #define PCIEIP_VF_REG_PCIEEPVF_ID_DEVID_E5_SHIFT 16 +#define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_K2 0x000000UL //Access:R DataWidth:0x20 // Device ID and Vendor ID Register. + #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_K2 (0xffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. + #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_K2 (0xffff<<16) // Device ID. Vendor Assigned Device Identifier. + #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_K2_SHIFT 16 +#define PCIEIP_VF_REG_PCIEEPVF_CMD_E5 0x000004UL //Access:RW DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_CMD_ISAE_E5 (0x1<<0) // VF read-only zero. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_ISAE_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_MSAE_E5 (0x1<<1) // VF read-only zero. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_MSAE_E5_SHIFT 1 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_ME_E5 (0x1<<2) // Bus master enable. If the VF tries to master the bus when this bit is not set, the request is discarded. A interrupt will be generated setting the SPEM()_PF()_DBG_INFO[P()_BMD_E bit. Transactions are dropped in the Client. Non-posted transactions returns a SWI_RSP_ERROR to SLI/DPI/NQM soon thereafter. Bus master enable mimics the behavior of SPEM()_FLR_PF()_VF()_STOPREQ. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_ME_E5_SHIFT 2 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_SCSE_E5 (0x1<<3) // Special cycle enable. Not applicable for PCI Express. Must be hardwired to 0. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_SCSE_E5_SHIFT 3 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_MWICE_E5 (0x1<<4) // Memory write and invalidate. Not applicable for PCI Express. Must be hardwired to 0. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_MWICE_E5_SHIFT 4 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_VPS_E5 (0x1<<5) // VGA palette snoop. Not applicable for PCI Express. Must be hardwired to 0. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_VPS_E5_SHIFT 5 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_PER_E5 (0x1<<6) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_PER_E5_SHIFT 6 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_IDS_WCC_E5 (0x1<<7) // IDSEL stepping/wait cycle control. Not applicable for PCI Express. Must be hardwired to 0. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_IDS_WCC_E5_SHIFT 7 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_SEE_E5 (0x1<<8) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_SEE_E5_SHIFT 8 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_FBBE_E5 (0x1<<9) // Fast back-to-back transaction enable. Not applicable for PCI Express. Must be hardwired to 0. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_FBBE_E5_SHIFT 9 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_I_DIS_E5 (0x1<<10) // VF read-only zero. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_I_DIS_E5_SHIFT 10 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_PCI_TYPE_RESERV_E5 (0x1f<<11) // Reserved. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_PCI_TYPE_RESERV_E5_SHIFT 11 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_IMM_READINESS_E5 (0x1<<16) // Immediate Readiness. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_IMM_READINESS_E5_SHIFT 16 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_I_STAT_E5 (0x1<<19) // INTx status. Not applicable for SR-IOV. Hardwired to 0. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_I_STAT_E5_SHIFT 19 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_CL_E5 (0x1<<20) // Capabilities list. Indicates presence of an extended capability item. Hardwired to 1. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_CL_E5_SHIFT 20 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_M66_E5 (0x1<<21) // 66 MHz capable. Not applicable for PCI Express. Hardwired to 0. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_M66_E5_SHIFT 21 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_FBB_E5 (0x1<<23) // Fast back-to-back capable. Not applicable for PCI Express. Hardwired to 0. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_FBB_E5_SHIFT 23 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_MDPE_E5 (0x1<<24) // Master data parity error. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_MDPE_E5_SHIFT 24 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_DEVT_E5 (0x3<<25) // DEVSEL timing. Not applicable for PCI Express. Hardwired to 0x0. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_DEVT_E5_SHIFT 25 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_STA_E5 (0x1<<27) // Signaled target abort. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_STA_E5_SHIFT 27 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_RTA_E5 (0x1<<28) // Received target abort. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_RTA_E5_SHIFT 28 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_RMA_E5 (0x1<<29) // Received master abort. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_RMA_E5_SHIFT 29 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_SSE_E5 (0x1<<30) // Signaled system error. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_SSE_E5_SHIFT 30 + #define PCIEIP_VF_REG_PCIEEPVF_CMD_DPE_E5 (0x1<<31) // Detected parity error. + #define PCIEIP_VF_REG_PCIEEPVF_CMD_DPE_E5_SHIFT 31 +#define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_K2 0x000004UL //Access:RW DataWidth:0x20 // Command and Status Register. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_K2 (0x1<<0) // Enables IO Access Response. You cannot write to this register if your configuration has no IO bars; that is, the internal signal has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_K2 (0x1<<1) // Enables Memory Access Response. You cannot write to this register if your configuration has no MEM bars; that is, the internal signal has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_K2_SHIFT 1 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_K2 (0x1<<2) // Bus Master Enable. Controls Issuing of Memory and I/O Requests. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_K2_SHIFT 2 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_K2 (0x1<<3) // Special Cycle Enable. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_K2_SHIFT 3 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_K2 (0x1<<4) // Memory Write and Invalidate. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_K2_SHIFT 4 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_K2 (0x1<<5) // VGA Palette Snoop. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_K2_SHIFT 5 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_K2 (0x1<<6) // Controls Logging of Poisoned TLPs. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_K2_SHIFT 6 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_K2 (0x1<<7) // IDSEL Stepping. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_K2_SHIFT 7 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_K2 (0x1<<8) // Enables Error Reporting. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_K2_SHIFT 8 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_K2 (0x1<<10) // Controls generation of interrupts by a function. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_K2_SHIFT 10 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_RESERV_K2 (0x1f<<11) // Reserved. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_RESERV_K2_SHIFT 11 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_INT_STATUS_K2 (0x1<<19) // Emulation interrupt pending. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_INT_STATUS_K2_SHIFT 19 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_CAP_LIST_K2 (0x1<<20) // Extended Capability. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_CAP_LIST_K2_SHIFT 20 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_66MHZ_CAP_K2 (0x1<<21) // PCI 66MHz Capability. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_66MHZ_CAP_K2_SHIFT 21 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_B2B_CAP_K2 (0x1<<23) // Fast Back to Back Transaction Capable and Enable. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_B2B_CAP_K2_SHIFT 23 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_MASTER_DPE_K2 (0x1<<24) // Controls poisoned Completion and Request error reporting. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_MASTER_DPE_K2_SHIFT 24 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DEV_SEL_TIMING_K2 (0x3<<25) // Device Select Timing. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DEV_SEL_TIMING_K2_SHIFT 25 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_K2 (0x1<<27) // Completer Abort Error. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_K2_SHIFT 27 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_K2 (0x1<<28) // Completer Abort received. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_K2_SHIFT 28 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_K2 (0x1<<29) // Unsupported request completion status received. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_K2_SHIFT 29 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_K2 (0x1<<30) // Fatal or Non-Fatal Error Message sent by function. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_K2_SHIFT 30 + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_K2 (0x1<<31) // Poisoned TLP received by function. + #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_K2_SHIFT 31 +#define PCIEIP_VF_REG_PCIEEPVF_REV_E5 0x000008UL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_REV_RID_E5 (0xff<<0) // Revision ID, writable through PEM()_CFG_WR. However, the application must not change this field. See MIO_FUS_DAT2[CHIP_ID] for more information. + #define PCIEIP_VF_REG_PCIEEPVF_REV_RID_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_REV_PI_E5 (0xff<<8) // Read-only copy of the associated PF's PCIEEP()_REV[PI]. + #define PCIEIP_VF_REG_PCIEEPVF_REV_PI_E5_SHIFT 8 + #define PCIEIP_VF_REG_PCIEEPVF_REV_SC_E5 (0xff<<16) // Read-only copy of the associated PF's PCIEEP()_REV[SC]. + #define PCIEIP_VF_REG_PCIEEPVF_REV_SC_E5_SHIFT 16 + #define PCIEIP_VF_REG_PCIEEPVF_REV_BCC_E5 (0xff<<24) // Read-only copy of the associated PF's PCIEEP()_REV[BCC]. + #define PCIEIP_VF_REG_PCIEEPVF_REV_BCC_E5_SHIFT 24 +#define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_K2 0x000008UL //Access:R DataWidth:0x20 // Class Code and Revision ID Register. + #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_REVISION_ID_K2 (0xff<<0) // Vendor chosen Revision ID. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_REVISION_ID_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_K2 (0xff<<8) // Class Code Programming Interface. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_K2_SHIFT 8 + #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_K2 (0xff<<16) // Subclass Code to represent Device Type. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_K2_SHIFT 16 + #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_K2 (0xff<<24) // Base Class Code to represent Device Type. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_K2_SHIFT 24 +#define PCIEIP_VF_REG_PCIEEPVF_CLSIZE_E5 0x00000cUL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_CLSIZE_CLS_E5 (0xff<<0) // Read-only copy of the associated PF's PCIEEP()_CLSIZE[CLS]. The cache line size register is R/W for legacy compatibility purposes and is not applicable to PCI Express device functionality. Writing to the cache line size register does not impact functionality of the PCI Express bus. + #define PCIEIP_VF_REG_PCIEEPVF_CLSIZE_CLS_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_CLSIZE_LT_E5 (0xff<<8) // Master latency timer. Not applicable for PCI Express, hardwired to 0x0. + #define PCIEIP_VF_REG_PCIEEPVF_CLSIZE_LT_E5_SHIFT 8 + #define PCIEIP_VF_REG_PCIEEPVF_CLSIZE_CHF_E5 (0x7f<<16) // Configuration header format. Hardwired to 0x0 for type 0. + #define PCIEIP_VF_REG_PCIEEPVF_CLSIZE_CHF_E5_SHIFT 16 + #define PCIEIP_VF_REG_PCIEEPVF_CLSIZE_MFD_E5 (0x1<<23) // Read-only copy of the associated PF's PCIEEP()_CLSIZE[MFD]. + #define PCIEIP_VF_REG_PCIEEPVF_CLSIZE_MFD_E5_SHIFT 23 + #define PCIEIP_VF_REG_PCIEEPVF_CLSIZE_BIST_E5 (0xff<<24) // The BIST register functions are not supported. All 8 bits of the BIST register are hardwired to 0x0. + #define PCIEIP_VF_REG_PCIEEPVF_CLSIZE_BIST_E5_SHIFT 24 +#define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_K2 0x00000cUL //Access:R DataWidth:0x20 // BIST, Header Type, Cache Line Size, and Latency Timer Registers. + #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_K2 (0xff<<0) // Cache Line Size. Has no effect on PCIe device behavior. + #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2 (0xff<<8) // Does not apply to PCI Express. + #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_K2_SHIFT 8 + #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_K2 (0x7f<<16) // Specifies Header Type. + #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_K2_SHIFT 16 + #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_K2 (0x1<<23) // Specifies whether device is multifunction. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_K2_SHIFT 23 + #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_K2 (0xff<<24) // Optional for BIST support. + #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_K2_SHIFT 24 +#define PCIEIP_VF_REG_PCIEEPVF_BAR0L_E5 0x000010UL //Access:R DataWidth:0x20 // +#define PCIEIP_VF_REG_VF_BAR0_REG_K2 0x000010UL //Access:R DataWidth:0x20 // BAR0 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_MEM_IO_K2 (0x1<<0) // BAR0 Memory Space Indicator. + #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_MEM_IO_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_TYPE_K2 (0x3<<1) // BAR0 32-bit or 64-bit. + #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_TYPE_K2_SHIFT 1 + #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_PREFETCH_K2 (0x1<<3) // BAR0 Prefetchable. + #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_PREFETCH_K2_SHIFT 3 + #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_START_K2 (0xfffffff<<4) // BAR0 Base Address. + #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_START_K2_SHIFT 4 +#define PCIEIP_VF_REG_PCIEEPVF_BAR0U_E5 0x000014UL //Access:R DataWidth:0x20 // +#define PCIEIP_VF_REG_VF_BAR1_REG_K2 0x000014UL //Access:R DataWidth:0x20 // BAR1 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_MEM_IO_K2 (0x1<<0) // BAR1 Memory Space Indicator. + #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_MEM_IO_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_TYPE_K2 (0x3<<1) // BAR1 32-bit or 64-bit. + #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_TYPE_K2_SHIFT 1 + #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_PREFETCH_K2 (0x1<<3) // BAR1 Prefetchable. + #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_PREFETCH_K2_SHIFT 3 + #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_START_K2 (0xfffffff<<4) // BAR1 Base Address. + #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_START_K2_SHIFT 4 +#define PCIEIP_VF_REG_PCIEEPVF_BAR2L_E5 0x000018UL //Access:R DataWidth:0x20 // +#define PCIEIP_VF_REG_VF_BAR2_REG_K2 0x000018UL //Access:R DataWidth:0x20 // BAR2 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_MEM_IO_K2 (0x1<<0) // BAR2 Memory Space Indicator. + #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_MEM_IO_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_TYPE_K2 (0x3<<1) // BAR2 32-bit or 64-bit. + #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_TYPE_K2_SHIFT 1 + #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_PREFETCH_K2 (0x1<<3) // BAR2 Prefetchable. + #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_PREFETCH_K2_SHIFT 3 + #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_START_K2 (0xfffffff<<4) // BAR2 Base Address. + #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_START_K2_SHIFT 4 +#define PCIEIP_VF_REG_PCIEEPVF_BAR2U_E5 0x00001cUL //Access:R DataWidth:0x20 // +#define PCIEIP_VF_REG_VF_BAR3_REG_K2 0x00001cUL //Access:R DataWidth:0x20 // BAR3 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_MEM_IO_K2 (0x1<<0) // BAR3 Memory Space Indicator. + #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_MEM_IO_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_TYPE_K2 (0x3<<1) // BAR3 32-bit or 64-bit. + #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_TYPE_K2_SHIFT 1 + #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_PREFETCH_K2 (0x1<<3) // BAR3 Prefetchable. + #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_PREFETCH_K2_SHIFT 3 + #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_START_K2 (0xfffffff<<4) // BAR3 Base Address. + #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_START_K2_SHIFT 4 +#define PCIEIP_VF_REG_PCIEEPVF_BAR4L_E5 0x000020UL //Access:R DataWidth:0x20 // +#define PCIEIP_VF_REG_VF_BAR4_REG_K2 0x000020UL //Access:R DataWidth:0x20 // BAR4 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_MEM_IO_K2 (0x1<<0) // BAR4 Memory Space Indicator. + #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_MEM_IO_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_TYPE_K2 (0x3<<1) // BAR4 32-bit or 64-bit. + #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_TYPE_K2_SHIFT 1 + #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_PREFETCH_K2 (0x1<<3) // BAR4 Prefetchable. + #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_PREFETCH_K2_SHIFT 3 + #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_START_K2 (0xfffffff<<4) // BAR4 Base Address. + #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_START_K2_SHIFT 4 +#define PCIEIP_VF_REG_PCIEEPVF_BAR4U_E5 0x000024UL //Access:R DataWidth:0x20 // +#define PCIEIP_VF_REG_VF_BAR5_REG_K2 0x000024UL //Access:R DataWidth:0x20 // BAR5 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_MEM_IO_K2 (0x1<<0) // BAR5 Memory Space Indicator. + #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_MEM_IO_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_TYPE_K2 (0x3<<1) // BAR5 32-bit or 64-bit. + #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_TYPE_K2_SHIFT 1 + #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_PREFETCH_K2 (0x1<<3) // BAR5 Prefetchable. + #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_PREFETCH_K2_SHIFT 3 + #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_START_K2 (0xfffffff<<4) // BAR5 Base Address. + #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_START_K2_SHIFT 4 +#define PCIEIP_VF_REG_PCIEEPVF_CARDBUS_E5 0x000028UL //Access:R DataWidth:0x20 // +#define PCIEIP_VF_REG_VF_CARDBUS_CIS_PTR_REG_K2 0x000028UL //Access:R DataWidth:0x20 // CardBus CIS Pointer Register. +#define PCIEIP_VF_REG_PCIEEPVF_SUBSYS_E5 0x00002cUL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_SUBSYS_SSVID_E5 (0xffff<<0) // Read-only copy of the associated PF's PCIEEP()_SUBSYS[SSVID]. + #define PCIEIP_VF_REG_PCIEEPVF_SUBSYS_SSVID_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_SUBSYS_SSID_E5 (0xffff<<16) // Read-only copy of the associated PF's PCIEEP()_SUBSYS[SSID]. + #define PCIEIP_VF_REG_PCIEEPVF_SUBSYS_SSID_E5_SHIFT 16 +#define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_K2 0x00002cUL //Access:RW DataWidth:0x20 // Subsystem ID and Subsystem Vendor ID Register. + #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_K2 (0xffff<<0) // Subsystem Vendor ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_K2 (0xffff<<16) // Subsystem Device ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_K2_SHIFT 16 +#define PCIEIP_VF_REG_PCIEEPVF_EBAR_E5 0x000030UL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_EBAR_ER_EN_E5 (0x1<<0) // Read-only copy of the associated PF's PCIEEP()_EBAR[ER_EN]. + #define PCIEIP_VF_REG_PCIEEPVF_EBAR_ER_EN_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_EBAR_ERADDR_E5 (0x1fff<<19) // Read-only copy of the associated PF's PCIEEP()_EBAR[ERADDR]. + #define PCIEIP_VF_REG_PCIEEPVF_EBAR_ERADDR_E5_SHIFT 19 +#define PCIEIP_VF_REG_PCIEEPVF_CAP_PTR_E5 0x000034UL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_CAP_PTR_CP_E5 (0xff<<0) // First capability pointer. Points to the PCI Express capability pointer structure (VF's). + #define PCIEIP_VF_REG_PCIEEPVF_CAP_PTR_CP_E5_SHIFT 0 +#define PCIEIP_VF_REG_VF_PCI_CAP_PTR_REG_K2 0x000034UL //Access:R DataWidth:0x20 // Capability Pointer Register. + #define PCIEIP_VF_REG_VF_PCI_CAP_PTR_REG_CAP_POINTER_K2 (0xff<<0) // Pointer to first item in the PCI Capability Structure. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_PCI_CAP_PTR_REG_CAP_POINTER_K2_SHIFT 0 +#define PCIEIP_VF_REG_PCIEEPVF_INT_E5 0x00003cUL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_INT_IL_E5 (0xff<<0) // VF's read-only zeros. + #define PCIEIP_VF_REG_PCIEEPVF_INT_IL_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_INT_INTA_E5 (0xff<<8) // VF's read-only zeros. + #define PCIEIP_VF_REG_PCIEEPVF_INT_INTA_E5_SHIFT 8 + #define PCIEIP_VF_REG_PCIEEPVF_INT_MG_E5 (0xff<<16) // VF's read-only zeros. + #define PCIEIP_VF_REG_PCIEEPVF_INT_MG_E5_SHIFT 16 + #define PCIEIP_VF_REG_PCIEEPVF_INT_ML_E5 (0xff<<24) // VF's read-only zeros. + #define PCIEIP_VF_REG_PCIEEPVF_INT_ML_E5_SHIFT 24 +#define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_K2 0x00003cUL //Access:R DataWidth:0x20 // Interrupt Line and Pin Register. + #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_K2 (0xff<<0) // PCI Compatible Interrupt Line Routing Register Field. + #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_K2 (0xff<<8) // PCI Compatible Interrupt Pin Register Field. + #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_K2_SHIFT 8 +#define PCIEIP_VF_REG_PCIEEPVF_E_CAP_LIST_E5 0x000070UL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_E_CAP_LIST_PCIEID_E5 (0xff<<0) // PCI Express capability ID. + #define PCIEIP_VF_REG_PCIEEPVF_E_CAP_LIST_PCIEID_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_E_CAP_LIST_NCP_E5 (0xff<<8) // Next capability pointer. Points to the MSI-X capabilities by default. + #define PCIEIP_VF_REG_PCIEEPVF_E_CAP_LIST_NCP_E5_SHIFT 8 + #define PCIEIP_VF_REG_PCIEEPVF_E_CAP_LIST_PCIECV_E5 (0xf<<16) // Read-only copy of the associated PF's PCIEEP()_E_CAP_LIST[PCIECV]. + #define PCIEIP_VF_REG_PCIEEPVF_E_CAP_LIST_PCIECV_E5_SHIFT 16 + #define PCIEIP_VF_REG_PCIEEPVF_E_CAP_LIST_DPT_E5 (0xf<<20) // Read-only copy of the associated PF's PCIEEP()_E_CAP_LIST[DPT]. + #define PCIEIP_VF_REG_PCIEEPVF_E_CAP_LIST_DPT_E5_SHIFT 20 + #define PCIEIP_VF_REG_PCIEEPVF_E_CAP_LIST_SI_E5 (0x1<<24) // Read-only copy of the associated PF's PCIEEP()_E_CAP_LIST[SI]. + #define PCIEIP_VF_REG_PCIEEPVF_E_CAP_LIST_SI_E5_SHIFT 24 + #define PCIEIP_VF_REG_PCIEEPVF_E_CAP_LIST_IMN_E5 (0x1f<<25) // Read-only copy of the associated PF's PCIEEP()_E_CAP_LIST[IMN]. + #define PCIEIP_VF_REG_PCIEEPVF_E_CAP_LIST_IMN_E5_SHIFT 25 +#define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_K2 0x000070UL //Access:RW DataWidth:0x20 // PCI Express Capabilities, ID, Next Pointer Register. + #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_K2 (0xff<<0) // PCIE Capability ID. + #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_K2 (0xff<<8) // PCIE Next Capability Pointer. + #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_K2_SHIFT 8 + #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_K2 (0xf<<16) // PCIE Capability Version Number. + #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_K2_SHIFT 16 + #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_K2 (0xf<<20) // PCIE Device/PortType. + #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_K2_SHIFT 20 + #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_K2 (0x1<<24) // PCIe Slot Implemented Valid. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_K2_SHIFT 24 + #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_K2 (0x1f<<25) // PCIE Interrupt Message Number. + #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_K2_SHIFT 25 + #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_K2 (0x1<<30) // Reserved. + #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_K2_SHIFT 30 +#define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_E5 0x000074UL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_MPSS_E5 (0x7<<0) // Read-only copy of the associated PF's PCIEEP()_DEV_CAP[MPSS]. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_MPSS_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_PFS_E5 (0x3<<3) // Read-only copy of the associated PF's PCIEEP()_DEV_CAP[PFS]. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_PFS_E5_SHIFT 3 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_ETFS_E5 (0x1<<5) // Read-only copy of the associated PF's PCIEEP()_DEV_CAP[ETFS]. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_ETFS_E5_SHIFT 5 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_EL0AL_E5 (0x7<<6) // Read-only copy of the associated PF's PCIEEP()_DEV_CAP[EL0AL]. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_EL0AL_E5_SHIFT 6 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_EL1AL_E5 (0x7<<9) // Read-only copy of the associated PF's PCIEEP()_DEV_CAP[EL1AL]. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_EL1AL_E5_SHIFT 9 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_RBER_E5 (0x1<<15) // Read-only copy of the associated PF's PCIEEP()_DEV_CAP[RBER]. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_RBER_E5_SHIFT 15 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_CSPLV_E5 (0xff<<18) // VF undefined. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_CSPLV_E5_SHIFT 18 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_CSPLS_E5 (0x3<<26) // VF undefined. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_CSPLS_E5_SHIFT 26 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_FLR_CAP_E5 (0x1<<28) // Function level reset capability. Set to 1 for SR-IOV core. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP_FLR_CAP_E5_SHIFT 28 +#define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_K2 0x000074UL //Access:RW DataWidth:0x20 // Device Capabilities Register. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_K2 (0x7<<0) // Max Payload Size Supported. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_K2 (0x3<<3) // Phantom Functions Supported. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_K2_SHIFT 3 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_K2 (0x1<<5) // Extended Tag Field Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_K2_SHIFT 5 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_K2 (0x7<<6) // Applies to endpoints only L0s acceptable latency. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_K2_SHIFT 6 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_K2 (0x7<<9) // Applies to endpoints only L1 acceptable latency. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_K2_SHIFT 9 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2 (0x1<<15) // Role-based Error Reporting Implemented. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_K2_SHIFT 15 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_K2 (0xff<<18) // Captured Slot Power Limit Value. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_K2_SHIFT 18 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_K2 (0x3<<26) // Captured Slot Power Limit Scale. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_K2_SHIFT 26 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_K2 (0x1<<28) // Function Level Reset Capability (endpoints only). + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_K2_SHIFT 28 +#define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_E5 0x000078UL //Access:RW DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_CE_EN_E5 (0x1<<0) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_CE_EN_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_NFE_EN_E5 (0x1<<1) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_NFE_EN_E5_SHIFT 1 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_FE_EN_E5 (0x1<<2) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_FE_EN_E5_SHIFT 2 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_UR_EN_E5 (0x1<<3) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_UR_EN_E5_SHIFT 3 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_RO_EN_E5 (0x1<<4) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_RO_EN_E5_SHIFT 4 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_MPS_E5 (0x7<<5) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_MPS_E5_SHIFT 5 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_ETF_EN_E5 (0x1<<8) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_ETF_EN_E5_SHIFT 8 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_PF_EN_E5 (0x1<<9) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_PF_EN_E5_SHIFT 9 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_AP_EN_E5 (0x1<<10) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_AP_EN_E5_SHIFT 10 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_NS_EN_E5 (0x1<<11) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_NS_EN_E5_SHIFT 11 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_MRRS_E5 (0x7<<12) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_MRRS_E5_SHIFT 12 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_I_FLR_E5 (0x1<<15) // Initiate function level reset when written to one. [I_FLR] must not be written to one via the indirect PEM()_CFG_WR. It should only ever be written to one via a direct PCIe access. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_I_FLR_E5_SHIFT 15 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_CE_D_E5 (0x1<<16) // Correctable error detected. Errors are logged in this register regardless of whether or not error reporting is enabled in the device control register. This field is set if we receive any of the errors in PCIEEPVF()_COR_ERR_STAT, for example a replay-timer timeout. Also, it can be set if we get any of the errors in PCIEEPVF()_UCOR_ERR_MSK that has a severity set to Nonfatal and meets the Advisory Nonfatal criteria, which most ECRC errors should. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_CE_D_E5_SHIFT 16 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_NFE_D_E5 (0x1<<17) // Nonfatal error detected. Errors are logged in this register regardless of whether or not error reporting is enabled in the device control register. This field is set if we receive any of the errors in PCIEEPVF()_UCOR_ERR_MSK that has a severity set to nonfatal and does not meet advisory nonfatal criteria, which most poisoned TLPs should. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_NFE_D_E5_SHIFT 17 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_FE_D_E5 (0x1<<18) // Fatal error detected. Errors are logged in this register regardless of whether or not error reporting is enabled in the device control register. This field is set if we receive any of the errors in PCIEEPVF()_UCOR_ERR_MSK that has a severity set to fatal. Malformed TLPs generally fit into this category. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_FE_D_E5_SHIFT 18 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_UR_D_E5 (0x1<<19) // Unsupported request detected. Errors are logged in this register regardless of whether or not error reporting is enabled in the device control register. [UR_D] occurs when we receive something unsupported. Unsupported requests are nonfatal errors, so [UR_D] should cause [NFE_D]. Receiving a vendor-defined message should cause an unsupported request. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_UR_D_E5_SHIFT 19 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_AP_D_E5 (0x1<<20) // VF's read-only zeros. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_AP_D_E5_SHIFT 20 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_TP_E5 (0x1<<21) // Transaction pending. Set to 1 when nonposted requests are not yet completed and set to 0 when they are completed. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL_TP_E5_SHIFT 21 +#define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_K2 0x000078UL //Access:RW DataWidth:0x20 // Device Control and Status Register. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_K2 (0x1<<0) // Correctable Error Reporting Enable. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2 (0x1<<1) // Non-fatal Error Reporting Enable. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_K2_SHIFT 1 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_K2 (0x1<<2) // Fatal Error Reporting Enable. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_K2_SHIFT 2 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_K2 (0x1<<3) // Unsupported Request Reporting Enable. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_K2_SHIFT 3 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_K2 (0x1<<4) // Enable Relaxed Ordering. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_K2_SHIFT 4 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_K2 (0x7<<5) // Max Payload Size. Max_Payload_Size . This field sets maximum TLP payload size for the Function. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities register (DEVICE_CAPABILITIES_REG). + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_K2_SHIFT 5 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_K2 (0x1<<8) // Extended Tag Field Enable. The write value is gated with the PCIE_CAP_EXT_TAG_SUPP field of DEVICE_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_K2_SHIFT 8 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_K2 (0x1<<9) // Phantom Functions Enable. The write value is gated with the PCIE_CAP_PHANTOM_FUNC_SUPPORT field of DEVICE_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_K2_SHIFT 9 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_K2 (0x1<<10) // Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_K2_SHIFT 10 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_K2 (0x1<<11) // Enable No Snoop. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_K2_SHIFT 11 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_K2 (0x7<<12) // Max Read Request Size. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_K2_SHIFT 12 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_K2 (0x1<<15) // Initiate Function Level Reset (for endpoints). + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_K2_SHIFT 15 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_K2 (0x1<<16) // Correctable Error Detected Status. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_K2_SHIFT 16 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2 (0x1<<17) // Non-Fatal Error Detected Status. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_K2_SHIFT 17 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_K2 (0x1<<18) // Fatal Error Detected Status. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_K2_SHIFT 18 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_K2 (0x1<<19) // Unsupported Request Detected Status. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_K2_SHIFT 19 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_K2 (0x1<<20) // Aux Power Detected Status. This bit is derived by sampling the sys_aux_pwr_det input. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_K2_SHIFT 20 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_K2 (0x1<<21) // Transactions Pending Status. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_K2_SHIFT 21 +#define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_E5 0x00007cUL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_MLS_E5 (0xf<<0) // Read-only copy of the associated PF's PCIEEP()_LINK_CAP[MLS]. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_MLS_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_MLW_E5 (0x3f<<4) // Read-only copy of the associated PF's PCIEEP()_LINK_CAP[MLW]. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_MLW_E5_SHIFT 4 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_ASLPMS_E5 (0x3<<10) // Read-only copy of the associated PF's PCIEEP()_LINK_CAP[ASLPMS]. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_ASLPMS_E5_SHIFT 10 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_L0EL_E5 (0x7<<12) // Read-only copy of the associated PF's PCIEEP()_LINK_CAP[L0EL]. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_L0EL_E5_SHIFT 12 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_L1EL_E5 (0x7<<15) // Read-only copy of the associated PF's PCIEEP()_LINK_CAP[L1EL]. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_L1EL_E5_SHIFT 15 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_CPM_E5 (0x1<<18) // Read-only copy of the associated PF's PCIEEP()_LINK_CAP[CPM]. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_CPM_E5_SHIFT 18 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_SDERC_E5 (0x1<<19) // Read-only copy of the associated PF's PCIEEP()_LINK_CAP[SDERC]. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_SDERC_E5_SHIFT 19 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_DLLARC_E5 (0x1<<20) // Read-only copy of the associated PF's PCIEEP()_LINK_CAP[DLLARC]. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_DLLARC_E5_SHIFT 20 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_LBNC_E5 (0x1<<21) // Read-only copy of the associated PF's PCIEEP()_LINK_CAP[LBNC]. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_LBNC_E5_SHIFT 21 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_ASPM_E5 (0x1<<22) // Read-only copy of the associated PF's PCIEEP()_LINK_CAP[ASPM]. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_ASPM_E5_SHIFT 22 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_PNUM_E5 (0xff<<24) // Read-only copy of the associated PF's PCIEEP()_LINK_CAP[PNUM]. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP_PNUM_E5_SHIFT 24 +#define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_K2 0x00007cUL //Access:RW DataWidth:0x20 // Link Capabilities Register. + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_K2 (0xf<<0) // Maximum Link Speed. In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_K2 (0x3f<<4) // Maximum Link Width. In M-PCIe mode, the reset and dynamic values of this field are calculated by the core. + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_K2_SHIFT 4 + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_K2 (0x3<<10) // Level of ASPM (Active State Power Management) Support. + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_K2_SHIFT 10 + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_K2 (0x7<<12) // LOs Exit Latency. There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the core and which one is accessed by a read request. Common Clock operation is supported (possible) in the core when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the core when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location. + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_K2_SHIFT 12 + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_K2 (0x7<<15) // L1 Exit Latency. There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the core and which one is accessed by a read request. Common Clock operation is supported (possible) in the core when one or more of the following expressions is true: - CX_NFTS !=CX_COMM_NFTS - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the core when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location. + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_K2_SHIFT 15 + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_K2 (0x1<<18) // Clock Power Management. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_K2_SHIFT 18 + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_K2 (0x1<<19) // Surprise Down Error Reporting Capable. + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_K2_SHIFT 19 + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_K2 (0x1<<20) // Data Link Layer Link Active Reporting Capable. + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_K2_SHIFT 20 + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_K2 (0x1<<21) // Link Bandwidth Notification Capable. + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_K2_SHIFT 21 + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_K2 (0x1<<22) // ASPM Optionality Compliance. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_K2_SHIFT 22 + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_K2 (0xff<<24) // Port Number. + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_K2_SHIFT 24 +#define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_E5 0x000080UL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_ASLPC_E5 (0x3<<0) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_ASLPC_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_RCB_E5 (0x1<<3) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_RCB_E5_SHIFT 3 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_LD_E5 (0x1<<4) // Link disable. Not applicable for an upstream port or endpoint device. Hardwired to 0. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_LD_E5_SHIFT 4 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_RL_E5 (0x1<<5) // Retrain link. Not applicable for an upstream port or endpoint device. Hardwired to 0. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_RL_E5_SHIFT 5 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_CCC_E5 (0x1<<6) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_CCC_E5_SHIFT 6 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_ES_E5 (0x1<<7) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_ES_E5_SHIFT 7 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_ECPM_E5 (0x1<<8) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_ECPM_E5_SHIFT 8 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_HAWD_E5 (0x1<<9) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_HAWD_E5_SHIFT 9 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_LBM_INT_ENB_E5 (0x1<<10) // Link bandwidth management interrupt enable. This bit is not applicable and is reserved for endpoints. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_LBM_INT_ENB_E5_SHIFT 10 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_LAB_INT_ENB_E5 (0x1<<11) // Link autonomous bandwidth interrupt enable. This bit is not applicable and is reserved for endpoints. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_LAB_INT_ENB_E5_SHIFT 11 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_DRS_SC_E5 (0x3<<14) // DRS Signaling Control. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_DRS_SC_E5_SHIFT 14 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_LS_E5 (0xf<<16) // Current link speed. The encoded value specifies a bit location in the supported link speeds vector (in the link capabilities 2 register) that corresponds to the current link speed. 0x1 = Supported link speeds vector field bit 0. 0x2 = Supported link speeds vector field bit 1. 0x3 = Supported link speeds vector field bit 2. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_LS_E5_SHIFT 16 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_NLW_E5 (0x3f<<20) // Negotiated link width. Set automatically by hardware after link initialization. Value is undefined when link is not up. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_NLW_E5_SHIFT 20 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_LT_E5 (0x1<<27) // Link training. Not applicable for an upstream port or endpoint device, hardwired to 0. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_LT_E5_SHIFT 27 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_SCC_E5 (0x1<<28) // Slot clock configuration. Indicates that the component uses the same physical reference clock that the platform provides on the connector. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_SCC_E5_SHIFT 28 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_DLLA_E5 (0x1<<29) // Data link layer active. Not applicable for an upstream port or endpoint device, hardwired to 0. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_DLLA_E5_SHIFT 29 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_LBM_E5 (0x1<<30) // Link bandwidth management status. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_LBM_E5_SHIFT 30 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_LAB_E5 (0x1<<31) // Link autonomous bandwdith status. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL_LAB_E5_SHIFT 31 +#define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_K2 0x000080UL //Access:RW DataWidth:0x20 // Link Control and Status Register. + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_K2 (0x3<<0) // Active State Power Management (ASPM) Control. + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_K2 (0x1<<3) // Read Completion Boundary (RCB). + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_K2_SHIFT 3 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_K2 (0x1<<4) // Initiate Link Disable. In a DSP that supports crosslink, the core gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF. Note: The access attributes of this field are as follows: - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_K2_SHIFT 4 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_K2 (0x1<<5) // Initiate Link Retrain. Note: The access attributes of this field are as follows: - Dbi: see description + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_K2_SHIFT 5 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_K2 (0x1<<6) // Common Clock Configuration. + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_K2_SHIFT 6 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_K2 (0x1<<7) // Extended Synch. + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_K2_SHIFT 7 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_K2 (0x1<<8) // Enable Clock Power Management. The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RW : RO + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_K2_SHIFT 8 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_K2 (0x1<<9) // Hardware Autonomous Width Disable. + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_K2_SHIFT 9 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_K2 (0x1<<10) // Link Bandwidth Management Interrupt Enable. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_K2_SHIFT 10 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_K2 (0x1<<11) // Link Autonomous Bandwidth Management Interrupt Enable. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_K2_SHIFT 11 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_K2 (0x3<<14) // DRS Signaling Control. + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_K2_SHIFT 14 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_K2 (0xf<<16) // Current Link Speed. + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_K2_SHIFT 16 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_K2 (0x3f<<20) // Negotiated Link Width. + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_K2_SHIFT 20 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_K2 (0x1<<27) // LTSSM is in Configuration or Recovery State. Note: The access attributes of this field are as follows: - Dbi: R + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_K2_SHIFT 27 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_K2 (0x1<<28) // Slot Clock Configuration. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_K2_SHIFT 28 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_K2 (0x1<<29) // Data Link Layer Active. + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_K2_SHIFT 29 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_K2 (0x1<<30) // Link Bandwidth Management Status. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_K2_SHIFT 30 + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_K2 (0x1<<31) // Link Autonomous Bandwidth Status. The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG. Note: The access attributes of this field are as follows: - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO + #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_K2_SHIFT 31 +#define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_E5 0x000094UL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_CTRS_E5 (0xf<<0) // Completion timeout ranges supported. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_CTRS_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_CTDS_E5 (0x1<<4) // Completion timeout disable supported. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_CTDS_E5_SHIFT 4 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_ARI_E5 (0x1<<5) // Alternate routing ID forwarding supported (not applicable for EP). + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_ARI_E5_SHIFT 5 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_ATOM_OPS_E5 (0x1<<6) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_ATOM_OPS_E5_SHIFT 6 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_ATOM32S_E5 (0x1<<7) // 32-bit AtomicOp supported. Note that inbound AtomicOps targeting BAR0 are not supported and are dropped as an unsupported request. Since VF's are tied to BAR0, all AtomicOp's will be dropped as unsupported requests. ATOM64S is set as an inherited attribute from the PF. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_ATOM32S_E5_SHIFT 7 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_ATOM64S_E5 (0x1<<8) // 64-bit AtomicOp supported. Note that inbound AtomicOps targeting BAR0 are not supported and are dropped as an unsupported request. Since VF's are tied to BAR0, all AtomicOp's will be dropped as unsupported requests. ATOM64S is set as an inherited attribute from the PF. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_ATOM64S_E5_SHIFT 8 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_ATOM128S_E5 (0x1<<9) // 128-bit AtomicOp supported. Note that inbound AtomicOps targeting BAR0 are not supported and are dropped as an unsupported request. Since VF's are tied to BAR0, all AtomicOp's will be dropped as unsupported requests. ATOM128S is set as an inherited attribute from the PF. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_ATOM128S_E5_SHIFT 9 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_NOROPRPR_E5 (0x1<<10) // No RO-enabled PR-PR passing. (This bit applies to RCs.) + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_NOROPRPR_E5_SHIFT 10 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_LTRS_E5 (0x1<<11) // Latency tolerance reporting (LTR) mechanism supported (not supported). + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_LTRS_E5_SHIFT 11 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_TPHS_E5 (0x3<<12) // TPH Completer Supported. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_TPHS_E5_SHIFT 12 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_LN_SYS_CLS_E5 (0x3<<14) // LN System CLS (not applicable for EP) + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_LN_SYS_CLS_E5_SHIFT 14 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_TAG10B_CPL_SUPP_E5 (0x1<<16) // 10-bit tag completer supported + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_TAG10B_CPL_SUPP_E5_SHIFT 16 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_TAG10B_REQ_SUPP_E5 (0x1<<17) // 10-bit tag requestor supported + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_TAG10B_REQ_SUPP_E5_SHIFT 17 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_OBFFS_E5 (0x3<<18) // Optimized buffer flush fill (OBFF) supported (not supported). + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_OBFFS_E5_SHIFT 18 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_EFFS_E5 (0x1<<20) // Extended fmt field supported. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_EFFS_E5_SHIFT 20 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_EETPS_E5 (0x1<<21) // End-end TLP prefix supported (not supported). + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_EETPS_E5_SHIFT 21 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_MEETP_E5 (0x3<<22) // Read-only copy of the associated PF's PCIEEP()_DEV_CAP2[MEETP]. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CAP2_MEETP_E5_SHIFT 22 +#define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_K2 0x000094UL //Access:R DataWidth:0x20 // Device Capabilities 2 Register. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_K2 (0xf<<0) // Completion Timeout Ranges Supported. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_K2 (0x1<<4) // Completion Timeout Disable Supported. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_K2_SHIFT 4 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_K2 (0x1<<5) // ARI Forwarding Supported. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_K2_SHIFT 5 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_K2 (0x1<<6) // Atomic Operation Routing Supported. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_K2_SHIFT 6 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2 (0x1<<7) // 32 Bit AtomicOp Completer Supported. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_K2_SHIFT 7 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2 (0x1<<8) // 64 Bit AtomicOp Completer Supported. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_K2_SHIFT 8 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_K2 (0x1<<9) // 128 Bit CAS Completer Supported. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_K2_SHIFT 9 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_K2 (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_K2_SHIFT 10 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_K2 (0x1<<11) // LTR Mechanism Supported. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_K2_SHIFT 11 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_K2 (0x1<<12) // TPH Completer Supported Bit 0. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_K2_SHIFT 12 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_K2 (0x1<<13) // TPH Completer Supported Bit 1. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_K2_SHIFT 13 + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_K2 (0x3<<18) // (OBFF) Optimized Buffer Flush/fill Supported. + #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_K2_SHIFT 18 +#define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_E5 0x000098UL //Access:RW DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_CTV_E5 (0xf<<0) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_CTV_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_CTD_E5 (0x1<<4) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_CTD_E5_SHIFT 4 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_ARI_E5 (0x1<<5) // Alternate routing ID forwarding supported (not supported). + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_ARI_E5_SHIFT 5 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_ATOM_OP_E5 (0x1<<6) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_ATOM_OP_E5_SHIFT 6 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_ID0_RQ_E5 (0x1<<8) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_ID0_RQ_E5_SHIFT 8 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_ID0_CP_E5 (0x1<<9) // VF RsvdP. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_ID0_CP_E5_SHIFT 9 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_LTRE_E5 (0x1<<10) // Latency tolerance reporting (LTR) mechanism enable + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_LTRE_E5_SHIFT 10 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_TAG10B_REQ_EN_E5 (0x1<<12) // 10-bit tag requestor enable. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_TAG10B_REQ_EN_E5_SHIFT 12 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_OBFFE_E5 (0x3<<13) // Optimized buffer flush fill (OBFF) enable (not supported). + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_OBFFE_E5_SHIFT 13 + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_EETPB_E5 (0x1<<15) // Unsupported end-end TLP prefix blocking. + #define PCIEIP_VF_REG_PCIEEPVF_DEV_CTL2_EETPB_E5_SHIFT 15 +#define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_K2 0x000098UL //Access:R DataWidth:0x20 // Device Control 2 and Status 2 Register. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_K2 (0xf<<0) // Completion Timeout Value. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_K2 (0x1<<4) // Completion Timeout Disable. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_K2_SHIFT 4 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_K2 (0x1<<5) // ARI Forwarding Enable. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_K2_SHIFT 5 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN_K2 (0x1<<6) // AtomicOp Requester Enable. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN_K2_SHIFT 6 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_K2 (0x1<<7) // AtomicOp Egress Blocking. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_K2_SHIFT 7 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_K2 (0x1<<8) // IDO Request Enable. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_K2_SHIFT 8 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN_K2 (0x1<<9) // IDO Completion Enable. + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN_K2_SHIFT 9 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_K2 (0x1<<10) // LTR Mechanism Enable. The write value is gated with the PCIE_CAP_LTR_SUPP field of DEVICE_CAPABILITIES2_REG. Note: RW for function #0 and RsdvP for all other functions + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_K2_SHIFT 10 + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_OBFF_EN_K2 (0x3<<13) // OBFF Enable. Note: RW for function #0 and RsdvP for all other functions + #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_OBFF_EN_K2_SHIFT 13 +#define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP2_E5 0x00009cUL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP2_SLSV_E5 (0x7f<<1) // Read-only copy of the associated PF's PCIEEP()_LINK_CAP2[SLSV]. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP2_SLSV_E5_SHIFT 1 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP2_CLS_E5 (0x1<<8) // Crosslink supported. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP2_CLS_E5_SHIFT 8 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP2_RTDS_E5 (0x1<<23) // Retimer Presence Detect Supported + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP2_RTDS_E5_SHIFT 23 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP2_TRTDS_E5 (0x1<<24) // Two Retimers Presence Detect Supported + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CAP2_TRTDS_E5_SHIFT 24 +#define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_K2 0x00009cUL //Access:RW DataWidth:0x20 // Link Capabilities 2 Register. + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_K2 (0x7f<<1) // Supported Link Speeds Vector. This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register. + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_K2_SHIFT 1 + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_K2 (0x1<<8) // Cross Link Supported. + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_K2_SHIFT 8 + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_K2 (0x1<<31) // DRS Supported. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R + #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_K2_SHIFT 31 +#define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_E5 0x0000a0UL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_TLS_E5 (0xf<<0) // VF's read-only zeros. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_TLS_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_EC_E5 (0x1<<4) // VF's read-only zeros. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_EC_E5_SHIFT 4 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_HASD_E5 (0x1<<5) // VF's read-only zeros. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_HASD_E5_SHIFT 5 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_SDE_E5 (0x1<<6) // VF's read-only zeros. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_SDE_E5_SHIFT 6 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_TM_E5 (0x7<<7) // VF's read-only zeros. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_TM_E5_SHIFT 7 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_EMC_E5 (0x1<<10) // VF's read-only zeros. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_EMC_E5_SHIFT 10 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_CSOS_E5 (0x1<<11) // VF's read-only zeros. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_CSOS_E5_SHIFT 11 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_CDE_E5 (0xf<<12) // VF's read-only zeros. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_CDE_E5_SHIFT 12 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_CDL_E5 (0x1<<16) // Read-only copy of the associated PF's PCIEEP()_LINK_CTL2[CDL]. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_CDL_E5_SHIFT 16 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_EQC_E5 (0x1<<17) // Equalization complete. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_EQC_E5_SHIFT 17 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_EP1S_E5 (0x1<<18) // Equalization phase 2 successful + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_EP1S_E5_SHIFT 18 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_EP2S_E5 (0x1<<19) // Equalization phase 2 successful + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_EP2S_E5_SHIFT 19 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_EP3S_E5 (0x1<<20) // Equalization phase 3 successful + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_EP3S_E5_SHIFT 20 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_LER_E5 (0x1<<21) // Link Equalization Request. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_LER_E5_SHIFT 21 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_RTD_E5 (0x1<<22) // Retimer presence detected. + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_RTD_E5_SHIFT 22 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_TRTD_E5 (0x1<<23) // Two Retimers Presence Detected + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_TRTD_E5_SHIFT 23 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_CLR_E5 (0x3<<24) // Crosslink Resolution (not supported). + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_CLR_E5_SHIFT 24 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_DCP_E5 (0x7<<28) // Downstream Component Presence + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_DCP_E5_SHIFT 28 + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_DRS_MR_E5 (0x1<<31) // DRS Message Received + #define PCIEIP_VF_REG_PCIEEPVF_LINK_CTL2_DRS_MR_E5_SHIFT 31 +#define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_K2 0x0000a0UL //Access:RW DataWidth:0x20 // Link Control 2 and Status 2 Register. + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_K2 (0xf<<0) // Target Link Speed. In M-PCIe mode, the contents of this field are derived from other registers. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TARGET_LINK_SPEED_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_K2 (0x1<<4) // Enter Compliance Mode. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_COMPLIANCE_K2_SHIFT 4 + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_K2 (0x1<<5) // Hardware Autonomous Speed Disable. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_HW_AUTO_SPEED_DISABLE_K2_SHIFT 5 + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_K2 (0x1<<6) // Controls Selectable De-emphasis for 5 GT/s. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_SEL_DEEMPHASIS_K2_SHIFT 6 + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_K2 (0x7<<7) // Controls Transmit Margin for Debug or Compliance. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_TX_MARGIN_K2_SHIFT 7 + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_K2 (0x1<<10) // Enter Modified Compliance. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_ENTER_MODIFIED_COMPLIANCE_K2_SHIFT 10 + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_K2 (0x1<<11) // Sets Compliance Skip Ordered Sets transmission. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_SOS_K2_SHIFT 11 + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_K2 (0xf<<12) // Sets Compliance Preset/De-emphasis for 5 GT/s and 8 GT/s. Note: The access attributes of this field are as follows: - Dbi: R (sticky) Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_COMPLIANCE_PRESET_K2_SHIFT 12 + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_K2 (0x1<<16) // Current De-emphasis Level. In M-PCIe mode this register is always 0x0. In C-PCIe mode, its contents are derived by sampling the PIPE + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_K2_SHIFT 16 + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_K2 (0x1<<17) // Equalization 8.0GT/s Complete. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_K2_SHIFT 17 + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_K2 (0x1<<18) // Equalization 8.0GT/s Phase 1 Successful. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P1_K2_SHIFT 18 + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_K2 (0x1<<19) // Equalization 8.0GT/s Phase 2 Successful. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P2_K2_SHIFT 19 + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_K2 (0x1<<20) // Equalization 8.0GT/s Phase 3 Successful. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_EQ_CPL_P3_K2_SHIFT 20 + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_K2 (0x1<<21) // Link Equalization Request 8.0GT/s. + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_LINK_EQ_REQ_K2_SHIFT 21 + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_K2 (0x7<<28) // Downstream Component Presence. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0. + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_K2_SHIFT 28 + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_K2 (0x1<<31) // DRS Message Received. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0. + #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_K2_SHIFT 31 +#define PCIEIP_VF_REG_PCIEEPVF_MSIX_CAP_CNTRL_E5 0x0000b0UL //Access:RW DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_CAP_CNTRL_MSIXCID_E5 (0xff<<0) // MSI-X capability ID. + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_CAP_CNTRL_MSIXCID_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_CAP_CNTRL_NCP_E5 (0xff<<8) // Next capability pointer. + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_CAP_CNTRL_NCP_E5_SHIFT 8 + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_CAP_CNTRL_MSIXTS_E5 (0x7ff<<16) // MSI-X table size encoded as (table size - 1). This field is writable through PEM()_CFG_WR when PEM()_CFG_WR[ADDR[31]] is set. + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_CAP_CNTRL_MSIXTS_E5_SHIFT 16 + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_CAP_CNTRL_FUNM_E5 (0x1<<30) // Function mask. 0 = Each vectors mask bit determines whether the vector is masked or not. 1 = All vectors associated with the function are masked, regardless of their respective per-vector mask bits. + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_CAP_CNTRL_FUNM_E5_SHIFT 30 + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_CAP_CNTRL_MSIXEN_E5 (0x1<<31) // MSI-X enable. + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_CAP_CNTRL_MSIXEN_E5_SHIFT 31 +#define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_K2 0x0000b0UL //Access:RW DataWidth:0x20 // MSI-X Capability ID, Next Pointer, Control Registers. + #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2 (0xff<<0) // MSI-X Capability ID. + #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2 (0xff<<8) // MSI-X Next Capability Pointer. + #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_K2_SHIFT 8 + #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_K2 (0x7ff<<16) // MSI-X Table Size. SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PCI_MSIX_TABLE_SIZE field in VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG). To write this common value, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_SIZE field in the PF PCI_MSIX_CAP_ID_NEXT_CTRL_REG register. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R - Dbi2: R + #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_K2_SHIFT 16 + #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_K2 (0x1<<30) // Function Mask. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_K2_SHIFT 30 + #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_K2 (0x1<<31) // MSI-X Enable. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_K2_SHIFT 31 +#define PCIEIP_VF_REG_PCIEEPVF_MSIX_TABLE_E5 0x0000b4UL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_TABLE_MSIXTBIR_E5 (0x7<<0) // Read-only copy of the associated PF's PCIEEP()_MSIX_TABLE[MSIXTBIR]. + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_TABLE_MSIXTBIR_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_TABLE_MSIXTOFFS_E5 (0x1fffffff<<3) // Read-only copy of the associated PF's PCIEEP()_MSIX_TABLE[MSIXTS]. + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_TABLE_MSIXTOFFS_E5_SHIFT 3 +#define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_K2 0x0000b4UL //Access:R DataWidth:0x20 // MSI-X Table Offset and BIR Register. + #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_K2 (0x7<<0) // MSI-X Table Bar Indicator Register Field. + #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_K2 (0x1fffffff<<3) // MSI-X Table Offset. + #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_K2_SHIFT 3 +#define PCIEIP_VF_REG_PCIEEPVF_MSIX_PBA_E5 0x0000b8UL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_PBA_MSIXPBIR_E5 (0x7<<0) // Read-only copy of the associated PF's PCIEEP()_MSIX_PBA[MSIXPBIR]. + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_PBA_MSIXPBIR_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_PBA_MSIXPOFFS_E5 (0x1fffffff<<3) // MSI-X table offset register. Base address of the MSI-X PBA, as an offset from the base address of the BAR indicated by the table PBA bits. + #define PCIEIP_VF_REG_PCIEEPVF_MSIX_PBA_MSIXPOFFS_E5_SHIFT 3 +#define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_K2 0x0000b8UL //Access:R DataWidth:0x20 // MSI-X PBA Offset and BIR Register. + #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_K2 (0x7<<0) // MSI-X PBA BIR. + #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_K2 (0x1fffffff<<3) // MSI-X PBA Offset. + #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_K2_SHIFT 3 +#define PCIEIP_VF_REG_PCIEEPVF_EXT_CAP_E5 0x000100UL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_EXT_CAP_ARIID_E5 (0xffff<<0) // PCIE Express extended capability + #define PCIEIP_VF_REG_PCIEEPVF_EXT_CAP_ARIID_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_EXT_CAP_CV_E5 (0xf<<16) // Capability version. + #define PCIEIP_VF_REG_PCIEEPVF_EXT_CAP_CV_E5_SHIFT 16 + #define PCIEIP_VF_REG_PCIEEPVF_EXT_CAP_NCO_E5 (0xfff<<20) // Next capability offset. + #define PCIEIP_VF_REG_PCIEEPVF_EXT_CAP_NCO_E5_SHIFT 20 +#define PCIEIP_VF_REG_VF_ARI_BASE_K2 0x000100UL //Access:RW DataWidth:0x20 // ARI Capability Header. + #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_PCIE_EXTENDED_CAP_ID_K2 (0xffff<<0) // ARI Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_PCIE_EXTENDED_CAP_ID_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_CAP_VERSION_K2 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_CAP_VERSION_K2_SHIFT 16 + #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_NEXT_OFFSET_K2 (0xfff<<20) // Next Capability Offset. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_NEXT_OFFSET_K2_SHIFT 20 +#define PCIEIP_VF_REG_PCIEEPVF_ARI_CAP_CTL_E5 0x000104UL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_ARI_CAP_CTL_MFVCFGC_E5 (0x1<<0) // MFVC function groups capability. + #define PCIEIP_VF_REG_PCIEEPVF_ARI_CAP_CTL_MFVCFGC_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_ARI_CAP_CTL_ACSFGC_E5 (0x1<<1) // ACS function groups capability. + #define PCIEIP_VF_REG_PCIEEPVF_ARI_CAP_CTL_ACSFGC_E5_SHIFT 1 + #define PCIEIP_VF_REG_PCIEEPVF_ARI_CAP_CTL_NFN_E5 (0xff<<8) // Next Function Number. + #define PCIEIP_VF_REG_PCIEEPVF_ARI_CAP_CTL_NFN_E5_SHIFT 8 + #define PCIEIP_VF_REG_PCIEEPVF_ARI_CAP_CTL_MFVCFGE_E5 (0x1<<16) // MFVC function groups enable (M). + #define PCIEIP_VF_REG_PCIEEPVF_ARI_CAP_CTL_MFVCFGE_E5_SHIFT 16 + #define PCIEIP_VF_REG_PCIEEPVF_ARI_CAP_CTL_ACSFGE_E5 (0x1<<17) // ACS function groups enable (A). + #define PCIEIP_VF_REG_PCIEEPVF_ARI_CAP_CTL_ACSFGE_E5_SHIFT 17 + #define PCIEIP_VF_REG_PCIEEPVF_ARI_CAP_CTL_FG_E5 (0x7<<20) // Function group. + #define PCIEIP_VF_REG_PCIEEPVF_ARI_CAP_CTL_FG_E5_SHIFT 20 +#define PCIEIP_VF_REG_VF_CAP_REG_K2 0x000104UL //Access:R DataWidth:0x20 // ARI Capability and Control Register. + #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_CAP_K2 (0x1<<0) // Multi Functional Virtual Channel (MFVC) Function Groups Capability. + #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_CAP_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_CAP_K2 (0x1<<1) // ACS Function Groups Capability. + #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_CAP_K2_SHIFT 1 + #define PCIEIP_VF_REG_VF_CAP_REG_ARI_NEXT_FUN_NUM_K2 (0xff<<8) // Next Function Number. + #define PCIEIP_VF_REG_VF_CAP_REG_ARI_NEXT_FUN_NUM_K2_SHIFT 8 + #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_EN_K2 (0x1<<16) // MFVC Function Groups Enable. + #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_EN_K2_SHIFT 16 + #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_EN_K2 (0x1<<17) // ACS Function Groups Enable. + #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_EN_K2_SHIFT 17 + #define PCIEIP_VF_REG_VF_CAP_REG_ARI_FUN_GRP_K2 (0x7<<20) // Function Group. + #define PCIEIP_VF_REG_VF_CAP_REG_ARI_FUN_GRP_K2_SHIFT 20 +#define PCIEIP_VF_REG_PCIEEPVF_TPH_CAP_HDR_E5 0x000110UL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_TPH_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_VF_REG_PCIEEPVF_TPH_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_TPH_CAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_VF_REG_PCIEEPVF_TPH_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_VF_REG_PCIEEPVF_TPH_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_VF_REG_PCIEEPVF_TPH_CAP_HDR_NCO_E5_SHIFT 20 +#define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_K2 0x000110UL //Access:RW DataWidth:0x20 // TPH Extended Capability Header. + #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_K2 (0xffff<<0) // TPH Extended Capability ID. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_K2 (0xf<<16) // Capability Version. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_K2_SHIFT 16 + #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_K2 (0xfff<<20) // Next Capability Pointer. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_K2_SHIFT 20 +#define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_E5 0x000114UL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_TPH_REQ_NO_ST_MODE_E5 (0x1<<0) // No ST Mode Supported. + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_TPH_REQ_NO_ST_MODE_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_INTV_E5 (0x1<<1) // Interrupt Vector Mode Supported + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_INTV_E5_SHIFT 1 + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_DS_E5 (0x1<<2) // Device Specific Mode Supported + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_DS_E5_SHIFT 2 + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_EXT_E5 (0x1<<8) // Exgtended TPH Requester Supported + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_EXT_E5_SHIFT 8 + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_STL0_E5 (0x1<<9) // Steering Tag Table Location bit 0 + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_STL0_E5_SHIFT 9 + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_STL1_E5 (0x1<<10) // Steering Tag Table Location bit 1 + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_STL1_E5_SHIFT 10 + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_STS_E5 (0x7ff<<16) // ST Table Size + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CAP_STS_E5_SHIFT 16 +#define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_K2 0x000114UL //Access:R DataWidth:0x20 // TPH Requestor Capability Register. SRIOV Note: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common register, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PF TPH_REQ_CAP_REG_REG register. + #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_K2 (0x1<<0) // No ST Mode Supported. + #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_K2 (0x1<<1) // Interrupt Vector Mode Supported. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_K2_SHIFT 1 + #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_K2 (0x1<<2) // Device Specific Mode Supported. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_K2_SHIFT 2 + #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_K2 (0x1<<8) // Extended TPH Requester Supported. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_K2_SHIFT 8 + #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_K2 (0x1<<9) // ST Table Location Bit 0. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_K2_SHIFT 9 + #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_K2 (0x1<<10) // ST Table Location Bit 1. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_K2_SHIFT 10 + #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_K2 (0x7ff<<16) // ST Table Size. Note: This register field is sticky. + #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_K2_SHIFT 16 +#define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CTL_E5 0x000118UL //Access:RW DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CTL_SMS_E5 (0x7<<0) // ST Mode Select. + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CTL_SMS_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CTL_CREN_E5 (0x3<<8) // TPH Requestor Enable bit. + #define PCIEIP_VF_REG_PCIEEPVF_TPH_REQ_CTL_CREN_E5_SHIFT 8 +#define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_K2 0x000118UL //Access:RW DataWidth:0x20 // TPH Requestor Control Register. + #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_K2 (0x7<<0) // ST Mode Select. Note: The access attributes of this field are as follows: - Dbi: R/W + #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_K2 (0x3<<8) // TPH Requester Enable Bit. + #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_K2_SHIFT 8 +#define PCIEIP_VF_REG_PCIEEPVF_TPH_ST_TABLE_E5 0x00011cUL //Access:RW DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_TPH_ST_TABLE_STL_E5 (0xff<<0) // ST Table 0 Lower Byte. Access can be tied to 0 by table size config + #define PCIEIP_VF_REG_PCIEEPVF_TPH_ST_TABLE_STL_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_TPH_ST_TABLE_STH_E5 (0xff<<8) // ST Table 0 Upper Byte. Access can be tied to 0 by table size config + #define PCIEIP_VF_REG_PCIEEPVF_TPH_ST_TABLE_STH_E5_SHIFT 8 +#define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_K2 0x00011cUL //Access:RW DataWidth:0x20 // TPH ST Table Register 0. + #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_K2 (0xff<<0) // ST Table 0 Lower Byte. Note: The access attributes of this field are as follows: - Dbi: this field is RW or Tie to 0 by table size configure + #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_K2_SHIFT 0 + #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_K2 (0xff<<8) // ST Table 0 Upper Byte. Note: The access attributes of this field are as follows: - Dbi: this field is RW or Tie to 0 by table size configure + #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_K2_SHIFT 8 +#define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_HDR_E5 0x00019cUL //Access:R DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_HDR_PCIEEC_E5 (0xffff<<0) // PCI Express extended capability. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_HDR_PCIEEC_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_HDR_CV_E5 (0xf<<16) // Capability version. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_HDR_CV_E5_SHIFT 16 + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_HDR_NCO_E5 (0xfff<<20) // Next capability offset. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_HDR_NCO_E5_SHIFT 20 +#define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_E5 0x0001a0UL //Access:RW DataWidth:0x20 // + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_SV_E5 (0x1<<0) // ACS source validation. Hardwired to 0 for upstream port. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_SV_E5_SHIFT 0 + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_TB_E5 (0x1<<1) // ACS translation blocking. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_TB_E5_SHIFT 1 + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_RR_E5 (0x1<<2) // ACS P2P request redirect. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_RR_E5_SHIFT 2 + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_CR_E5 (0x1<<3) // ACS P2P completion redirect. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_CR_E5_SHIFT 3 + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_UF_E5 (0x1<<4) // ACS upstream forwarding. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_UF_E5_SHIFT 4 + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_EC_E5 (0x1<<5) // ACS P2P egress control. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_EC_E5_SHIFT 5 + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_DT_E5 (0x1<<6) // ACS direct translated P2P. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_DT_E5_SHIFT 6 + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_ECVS_E5 (0xff<<8) // Egress control vector size. Writable through PEM()_CFG_WR. However, the application must not change this field. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_ECVS_E5_SHIFT 8 + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_SVE_E5 (0x1<<16) // ACS source validation enable. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_SVE_E5_SHIFT 16 + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_TBE_E5 (0x1<<17) // ACS translation blocking enable. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_TBE_E5_SHIFT 17 + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_RRE_E5 (0x1<<18) // ACS P2P request redirect enable. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_RRE_E5_SHIFT 18 + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_CRE_E5 (0x1<<19) // ACS P2P completion redirect enable. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_CRE_E5_SHIFT 19 + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_UFE_E5 (0x1<<20) // ACS upstream forwarding enable. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_UFE_E5_SHIFT 20 + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_ECE_E5 (0x1<<21) // ACS P2P egress control enable. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_ECE_E5_SHIFT 21 + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_DTE_E5 (0x1<<22) // ACS direct translated P2P enable. + #define PCIEIP_VF_REG_PCIEEPVF_ACS_CAP_CTL_DTE_E5_SHIFT 22 +#define PCIEIP_VF_REG_PCIEEPVF_ACS_EGR_CTL_VEC_E5 0x0001a4UL //Access:RW DataWidth:0x20 // +#define PCIEIP_SHADOW_REG_PCIEEP_BAR0_MASKL_E5 0x000010UL //Access:W DataWidth:0x20 // The BAR 0 mask register is invisible to host software and not readable from the application. The BAR 0 mask register is only writable through PEM()_CFG_WR. + #define PCIEIP_SHADOW_REG_PCIEEP_BAR0_MASKL_ENB_E5 (0x1<<0) // BAR enable. 0: BAR 0 is disabled, 1: BAR 0 is enabled. Bit 0 is interpreted as BAR enable when writing to the BAR mask register rather than as a mask bit because bit 0 of a BAR is always masked from writing by host software. Bit 0 must be written prior to writing the other mask bits. + #define PCIEIP_SHADOW_REG_PCIEEP_BAR0_MASKL_ENB_E5_SHIFT 0 + #define PCIEIP_SHADOW_REG_PCIEEP_BAR0_MASKL_LMASK_E5 (0x7fffffff<<1) // BAR mask low. + #define PCIEIP_SHADOW_REG_PCIEEP_BAR0_MASKL_LMASK_E5_SHIFT 1 +#define PCIEIP_SHADOW_REG_BAR0_MASK_REG_K2 0x000010UL //Access:W DataWidth:0x20 // BAR0 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_K2 (0x1<<0) // BAR0 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_K2_SHIFT 0 + #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_K2 (0x7fffffff<<1) // BAR0 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_K2_SHIFT 1 +#define PCIEIP_SHADOW_REG_PCIEEP_BAR0_MASKU_E5 0x000014UL //Access:W DataWidth:0x20 // The BAR 0 mask register is invisible to host software and not readable from the application. The BAR 0 mask register is only writable through PEM()_CFG_WR. +#define PCIEIP_SHADOW_REG_BAR1_MASK_REG_K2 0x000014UL //Access:RW DataWidth:0x20 // BAR1 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_K2 (0x1<<0) // BAR1 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_K2_SHIFT 0 + #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_K2 (0x7fffffff<<1) // BAR1 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_K2_SHIFT 1 +#define PCIEIP_SHADOW_REG_PCIEEP_BAR1_MASKL_E5 0x000018UL //Access:W DataWidth:0x20 // The BAR 1 mask register is invisible to host software and not readable from the application. The BAR 1 mask register is only writable through PEM()_CFG_WR. + #define PCIEIP_SHADOW_REG_PCIEEP_BAR1_MASKL_ENB_E5 (0x1<<0) // BAR enable. 0: BAR 1 is disabled, 1: BAR 1 is enabled. Bit 0 is interpreted as BAR enable when writing to the BAR mask register rather than as a mask bit because bit 0 of a BAR is always masked from writing by host software. Bit 0 must be written prior to writing the other mask bits. + #define PCIEIP_SHADOW_REG_PCIEEP_BAR1_MASKL_ENB_E5_SHIFT 0 + #define PCIEIP_SHADOW_REG_PCIEEP_BAR1_MASKL_LMASK_E5 (0x7fffffff<<1) // BAR mask low + #define PCIEIP_SHADOW_REG_PCIEEP_BAR1_MASKL_LMASK_E5_SHIFT 1 +#define PCIEIP_SHADOW_REG_PCIEEP_BAR1_MASKU_E5 0x00001cUL //Access:W DataWidth:0x20 // The BAR 1 mask register is invisible to host software and not readable from the application. The BAR 1 mask register is only writable through PEM()_CFG_WR. +#define PCIEIP_SHADOW_REG_PCIEEP_BAR2_MASKL_E5 0x000020UL //Access:W DataWidth:0x20 // The BAR 2 mask register is invisible to host software and not readable from the application. The BAR 2 mask register is only writable through PEM()_CFG_WR. + #define PCIEIP_SHADOW_REG_PCIEEP_BAR2_MASKL_ENB_E5 (0x1<<0) // BAR enable. 0: BAR 2 is disabled, 1: BAR 2 is enabled. Bit 0 is interpreted as BAR enable when writing to the BAR mask register rather than as a mask bit because bit 0 of a BAR is always masked from writing by host software. Bit 0 must be written prior to writing the other mask bits. + #define PCIEIP_SHADOW_REG_PCIEEP_BAR2_MASKL_ENB_E5_SHIFT 0 + #define PCIEIP_SHADOW_REG_PCIEEP_BAR2_MASKL_LMASK_E5 (0x7fffffff<<1) // BAR mask low. + #define PCIEIP_SHADOW_REG_PCIEEP_BAR2_MASKL_LMASK_E5_SHIFT 1 +#define PCIEIP_SHADOW_REG_BAR4_MASK_REG_K2 0x000020UL //Access:W DataWidth:0x20 // BAR4 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_K2 (0x1<<0) // BAR4 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_K2_SHIFT 0 + #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_K2 (0x7fffffff<<1) // BAR4 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_K2_SHIFT 1 +#define PCIEIP_SHADOW_REG_PCIEEP_BAR2_MASKU_E5 0x000024UL //Access:W DataWidth:0x20 // The BAR 2 mask register is invisible to host software and not readable from the application. The BAR 2 mask register is only writable through PEM()_CFG_WR. +#define PCIEIP_SHADOW_REG_BAR5_MASK_REG_K2 0x000024UL //Access:W DataWidth:0x20 // BAR5 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_K2 (0x1<<0) // BAR5 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_K2_SHIFT 0 + #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_K2 (0x7fffffff<<1) // BAR5 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_K2_SHIFT 1 +#define PCIEIP_SHADOW_REG_PCIEEP_EROM_MASK_E5 0x000030UL //Access:W DataWidth:0x20 // The ROM mask register is invisible to host software and not readable from the application. The ROM mask register is only writable through PEM()_CFG_WR. + #define PCIEIP_SHADOW_REG_PCIEEP_EROM_MASK_ENB_E5 (0x1<<0) // BAR enable. 0 = BAR ROM is disabled; 1 = BAR ROM is enabled. Bit 0 is interpreted as BAR enable when writing to the BAR mask register rather than as a mask bit because bit 0 of a BAR is always masked from writing by host software. Bit 0 must be written prior to writing the other mask bits. + #define PCIEIP_SHADOW_REG_PCIEEP_EROM_MASK_ENB_E5_SHIFT 0 + #define PCIEIP_SHADOW_REG_PCIEEP_EROM_MASK_MASK_E5 (0x7fffffff<<1) // BAR mask low + #define PCIEIP_SHADOW_REG_PCIEEP_EROM_MASK_MASK_E5_SHIFT 1 +#define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_K2 0x000030UL //Access:R DataWidth:0x20 // Expansion ROM BAR and Mask Register. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_K2 (0x1<<0) // Expansion ROM Bar Mask Register Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if ROM_BAR_ENABLED then W else R + #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_K2_SHIFT 0 + #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_MASK_K2 (0x7fffffff<<1) // Expansion ROM Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: if ROM_BAR_ENABLED then W else R + #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_MASK_K2_SHIFT 1 +#define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_K2 0x0001c4UL //Access:R DataWidth:0x20 // TotalVFs InitialVFs Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two of these registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. + #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_SHADOW_SRIOV_INITIAL_VFS_K2 (0xffff<<0) // InitialVFs. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two InitialVFs registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W + #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_SHADOW_SRIOV_INITIAL_VFS_K2_SHIFT 0 + #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_SHADOW_SRIOV_TOTAL_VFS_K2 (0xffff<<16) // Total VFs (Max Number of VFs). For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two TotalVFs registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W + #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_SHADOW_SRIOV_TOTAL_VFS_K2_SHIFT 16 +#define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_K2 0x0001ccUL //Access:R DataWidth:0x20 // VF Stride and Offset Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. + #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_SHADOW_SRIOV_VF_STRIDE_K2 (0xffff<<0) // VF Stride. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two VF Stride registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W + #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_SHADOW_SRIOV_VF_STRIDE_K2_SHIFT 0 + #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_SHADOW_SRIOV_VF_OFFSET_K2 (0xffff<<16) // First VF Offset. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two First VF Offset registers at this address location; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W + #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_SHADOW_SRIOV_VF_OFFSET_K2_SHIFT 16 +#define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_K2 0x0001dcUL //Access:W DataWidth:0x20 // BAR0 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_ENABLED_K2 (0x1<<0) // BAR0 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_ENABLED_K2_SHIFT 0 + #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_MASK_K2 (0x7fffffff<<1) // BAR0 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_MASK_K2_SHIFT 1 +#define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_K2 0x0001e0UL //Access:RW DataWidth:0x20 // BAR1 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_ENABLED_K2 (0x1<<0) // BAR1 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_ENABLED_K2_SHIFT 0 + #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_MASK_K2 (0x7fffffff<<1) // BAR1 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_MASK_K2_SHIFT 1 +#define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_K2 0x0001e4UL //Access:W DataWidth:0x20 // BAR2 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_ENABLED_K2 (0x1<<0) // BAR2 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_ENABLED_K2_SHIFT 0 + #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_MASK_K2 (0x7fffffff<<1) // BAR2 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_MASK_K2_SHIFT 1 +#define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_K2 0x0001e8UL //Access:RW DataWidth:0x20 // BAR3 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_ENABLED_K2 (0x1<<0) // BAR3 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_ENABLED_K2_SHIFT 0 + #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_MASK_K2 (0x7fffffff<<1) // BAR3 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_MASK_K2_SHIFT 1 +#define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_K2 0x0001ecUL //Access:W DataWidth:0x20 // BAR4 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_ENABLED_K2 (0x1<<0) // BAR4 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_ENABLED_K2_SHIFT 0 + #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_MASK_K2 (0x7fffffff<<1) // BAR4 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_MASK_K2_SHIFT 1 +#define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_K2 0x0001f0UL //Access:RW DataWidth:0x20 // BAR5 and BAR Mask. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers". + #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_ENABLED_K2 (0x1<<0) // BAR5 Mask Enabled. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_ENABLED_K2_SHIFT 0 + #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_MASK_K2 (0x7fffffff<<1) // BAR5 Mask. Note: The access attributes of this field are as follows: - Dbi: No access - Dbi2: W (sticky) Note: This register field is sticky. + #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_MASK_K2_SHIFT 1 #define SEM_FAST_REG_RAM_EXT_DISABLE_BB_K2 0x000004UL //Access:RW DataWidth:0x1 // Disable for SDM write to int_ram. #define SEM_FAST_REG_INT_STS 0x000040UL //Access:R DataWidth:0x1 // Multi Field Register. #define SEM_FAST_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. @@ -7352,32 +10229,36 @@ #define SEM_FAST_REG_ERROR_RST 0x000050UL //Access:W DataWidth:0x1 // Reset to error interrupt. #define SEM_FAST_REG_PARITY_RST 0x000054UL //Access:W DataWidth:0x1 // Reset to parity interrupt. #define SEM_FAST_REG_PRTY_MASK_H_0_K2_E5 0x000204UL //Access:RW DataWidth:0x8 // Multi Field Register. - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_E5 (0x1<<0) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_E5_SHIFT 0 - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_E5 (0x1<<1) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_E5_SHIFT 1 - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2 (0x1<<3) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT 3 - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5_SHIFT 2 + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5_SHIFT 0 + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5_SHIFT 1 + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY . + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_E5_SHIFT 2 + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY . + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5_SHIFT 3 + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY . + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_E5_SHIFT 4 + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_E5_SHIFT 5 + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_E5_SHIFT 6 + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5_SHIFT 7 + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2 (0x1<<0) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_SHIFT 0 + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2 (0x1<<1) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT 1 #define SEM_FAST_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2 (0x1<<2) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . #define SEM_FAST_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2_SHIFT 2 - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5_SHIFT 3 - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2 (0x1<<5) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT 5 - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5_SHIFT 4 + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2 (0x1<<3) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT 3 #define SEM_FAST_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2 (0x1<<4) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . #define SEM_FAST_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT 4 - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5_SHIFT 5 - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5_SHIFT 6 + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2 (0x1<<5) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . + #define SEM_FAST_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT 5 #define SEM_FAST_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2 (0x1<<6) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . #define SEM_FAST_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_SHIFT 6 - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . - #define SEM_FAST_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5_SHIFT 7 #define SEM_FAST_REG_MEM_ECC_EVENTS_K2_E5 0x000210UL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. #define SEM_FAST_REG_RESERVED_21C_K2 0x00021cUL //Access:R DataWidth:0x20 // Reserved #define SEM_FAST_REG_RESERVED_228_K2 0x000228UL //Access:R DataWidth:0x20 // Reserved @@ -7513,7 +10394,7 @@ #define SEM_FAST_REG_DBG_ALM_FULL 0x00084cUL //Access:RW DataWidth:0x7 // Almost full for DBG SYNC FIFO. #define SEM_FAST_REG_SYNC_DRA_WR_ALM_FULL_E5 0x000850UL //Access:RW DataWidth:0x3 // Almost full for DRA_WR SYNC FIFO. #define SEM_FAST_REG_FULL 0x000940UL //Access:R DataWidth:0x18 // Full data spelling : {mux_rbc_vfc_fifo_empty, cam_rbc_inp_msb2_empty_sel, sync_rbc_dbg_empty[STORM_B], sync_rbc_dbg_empty[STORM_A], rd_rbc_fast_fin_empty[STORM_B], rd_rbc_fast_fin_empty[STORM_A], sync_wr_fast_pop_empty[STORM_B], sync_wr_fast_pop_empty[STORM_A], sync_misc_dra_rd_push_empty[STORM_B], sync_misc_dra_rd_push_empty[STORM_A], cam_rbc_inp_lsb_empty_sel, cam_rbc_inp_msb_empty_sel, cam_mux_empty[STORM_B], cam_mux_empty[STORM_A], sync_rbc_ram_rd_empty, sync_ram_fast_ext_empty, sync_rbc_ext_empty[STORM_B], sync_rbc_ext_empty[STORM_A]}; -#define SEM_FAST_REG_EMPTY 0x000944UL //Access:R DataWidth:0x18 // Empty data spelling; {mux_rbc_vfc_fifo_empty, cam_rbc_inp_msb2_empty_sel[STORM_B], cam_rbc_inp_msb2_empty_sel[STORM_A], sync_rbc_dbg_empty[STORM_B], sync_rbc_dbg_empty[STORM_A], rd_rbc_fast_fin_empty[STORM_B], rd_rbc_fast_fin_empty[STORM_A], sync_wr_fast_pop_empty[STORM_B], sync_wr_fast_pop_empty[STORM_A], sync_misc_dra_rd_push_empty[STORM_B], sync_misc_dra_rd_push_empty[STORM_A], cam_rbc_inp_lsb_empty_sel[STORM_B], cam_rbc_inp_lsb_empty_sel[STORM_A], cam_rbc_inp_msb_empty_sel[STORM_B], cam_rbc_inp_msb_empty_sel[STORM_A], cam_mux_empty[STORM_B], cam_mux_empty[STORM_A], sync_rbc_ram_rd_empty, sync_ram_fast_ext_empty, sync_rbc_ext_empty[STORM_B], sync_rbc_ext_empty[STORM_A]}; +#define SEM_FAST_REG_EMPTY 0x000944UL //Access:R DataWidth:0x15 // Empty data spelling; {mux_rbc_vfc_fifo_empty, cam_rbc_inp_msb2_empty_sel[STORM_B], cam_rbc_inp_msb2_empty_sel[STORM_A], sync_rbc_dbg_empty[STORM_B], sync_rbc_dbg_empty[STORM_A], rd_rbc_fast_fin_empty[STORM_B], rd_rbc_fast_fin_empty[STORM_A], sync_wr_fast_pop_empty[STORM_B], sync_wr_fast_pop_empty[STORM_A], sync_misc_dra_rd_push_empty[STORM_B], sync_misc_dra_rd_push_empty[STORM_A], cam_rbc_inp_lsb_empty_sel[STORM_B], cam_rbc_inp_lsb_empty_sel[STORM_A], cam_rbc_inp_msb_empty_sel[STORM_B], cam_rbc_inp_msb_empty_sel[STORM_A], cam_mux_empty[STORM_B], cam_mux_empty[STORM_A], sync_rbc_ram_rd_empty, sync_ram_fast_ext_empty, sync_rbc_ext_empty[STORM_B], sync_rbc_ext_empty[STORM_A]}; #define SEM_FAST_REG_ALM_FULL 0x000948UL //Access:R DataWidth:0x3 // Alm_full data spelling; {ram_alm_full,ext_alm_full[STORM_B],ext_alm_full[STORM_A]}. #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE 0x000a40UL //Access:RW DataWidth:0x6 // Multi Field Register. #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_CID_EN (0x1<<0) // Used to enable CID/TID filter for Storm active statistics counter, when set. @@ -7566,7 +10447,8 @@ #define SEM_FAST_REG_LOCKS_MON_E5 0x00b200UL //Access:RW DataWidth:0x20 // Provides a RD access for all monitor block, {CNT_VAL,CNT_ID,SET}. #define SEM_FAST_REG_LOCKS_MON_SIZE 128 #define SEM_FAST_REG_INT_RAM 0x020000UL //Access:RW DataWidth:0x20 // Internal RAM (if bit lsb of addr =0 => write to bits[31:0; otherwise to [63:32). -#define SEM_FAST_REG_INT_RAM_SIZE 20480 +#define SEM_FAST_REG_INT_RAM_SIZE_BB_K2 20480 +#define SEM_FAST_REG_INT_RAM_SIZE_E5 28872 #define VFC_REG_MASK_LSB_0_LOW 0x000000UL //Access:RW DataWidth:0x20 // Bits [31:0] for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored. #define VFC_REG_MASK_LSB_0_HIGH 0x000004UL //Access:RW DataWidth:0x20 // Bits [63:32] for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored. #define VFC_REG_MASK_LSB_1_LOW 0x000008UL //Access:RW DataWidth:0x20 // Bits [31:0] for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored. @@ -7588,23 +10470,23 @@ #define VFC_REG_INTERRUPT_IND_INP_BUF_INTERRUPT_SHIFT 3 #define VFC_REG_INTERRUPT_IND_OUT_BUF_INTERRUPT (0x1<<4) // This is error interrupt. It may be asserted when it was output buffer overflow. #define VFC_REG_INTERRUPT_IND_OUT_BUF_INTERRUPT_SHIFT 4 - #define VFC_REG_INTERRUPT_IND_RSS_INFO_INTERRUPT (0x1<<5) // This is error interrupt. It may be asserted when it was address overflow of INFO part of RSS RAM. It will be de-asserted aftre write 1 to it. - #define VFC_REG_INTERRUPT_IND_RSS_INFO_INTERRUPT_SHIFT 5 - #define VFC_REG_INTERRUPT_IND_RSS_KEY_LSB_INTERRUPT (0x1<<6) // This is error interrupt. It may be asserted when it was address overflow of KEY LSB part of RSS RAM. It will be de-asserted aftre write 1 to it. - #define VFC_REG_INTERRUPT_IND_RSS_KEY_LSB_INTERRUPT_SHIFT 6 - #define VFC_REG_INTERRUPT_IND_RSS_KEY_MSB_INTERRUPT (0x1<<7) // This is error interrupt. It may be asserted when it was address overflow of KEY MSB part of RSS RAM. It will be de-asserted aftre write 1 to it. - #define VFC_REG_INTERRUPT_IND_RSS_KEY_MSB_INTERRUPT_SHIFT 7 #define VFC_REG_INTERRUPT_IND_RBC_WRITE_INTERRUPT (0x1<<8) // This is error interrupt. It may be asserted when it was RBC command with address not equal to 12 bit or data cycle not equal 64 bit or number of data cycles bigger than 6. It will be de-asserted aftre write 1 to it. #define VFC_REG_INTERRUPT_IND_RBC_WRITE_INTERRUPT_SHIFT 8 #define VFC_REG_INTERRUPT_IND_DEADLOCK_INTERRUPT (0x1<<9) // This is error interrupt. It may be asserted when waitp is asserted and output FIFO is also full. It will be de-asserted aftre write 1 to it. #define VFC_REG_INTERRUPT_IND_DEADLOCK_INTERRUPT_SHIFT 9 + #define VFC_REG_INTERRUPT_IND_RSS_INFO_INTERRUPT_BB_K2 (0x1<<5) // This is error interrupt. It may be asserted when it was address overflow of INFO part of RSS RAM. It will be de-asserted aftre write 1 to it. + #define VFC_REG_INTERRUPT_IND_RSS_INFO_INTERRUPT_BB_K2_SHIFT 5 + #define VFC_REG_INTERRUPT_IND_RSS_KEY_LSB_INTERRUPT_BB_K2 (0x1<<6) // This is error interrupt. It may be asserted when it was address overflow of KEY LSB part of RSS RAM. It will be de-asserted aftre write 1 to it. + #define VFC_REG_INTERRUPT_IND_RSS_KEY_LSB_INTERRUPT_BB_K2_SHIFT 6 + #define VFC_REG_INTERRUPT_IND_RSS_KEY_MSB_INTERRUPT_BB_K2 (0x1<<7) // This is error interrupt. It may be asserted when it was address overflow of KEY MSB part of RSS RAM. It will be de-asserted aftre write 1 to it. + #define VFC_REG_INTERRUPT_IND_RSS_KEY_MSB_INTERRUPT_BB_K2_SHIFT 7 #define VFC_REG_PARITY_IND 0x00002cUL //Access:RW DataWidth:0x3 // Multi Field Register. - #define VFC_REG_PARITY_IND_RSS_RAM_PARITY (0x1<<0) // This is parity interrupt. It may be asserted when it was RSS RAM parity error. It will be de-asserted aftre write 1 to it. - #define VFC_REG_PARITY_IND_RSS_RAM_PARITY_SHIFT 0 #define VFC_REG_PARITY_IND_CAM_PARITY (0x1<<1) // This is parity interrupt. It may be asserted when it was CAM parity error. It will be de-asserted aftre write 1 to it. #define VFC_REG_PARITY_IND_CAM_PARITY_SHIFT 1 #define VFC_REG_PARITY_IND_TT_RAM_PARITY (0x1<<2) // This is parity interrupt. It may be asserted when it was parity error inside TT RAM. It will be de-asserted aftre write 1 to it. #define VFC_REG_PARITY_IND_TT_RAM_PARITY_SHIFT 2 + #define VFC_REG_PARITY_IND_RSS_RAM_PARITY_BB_K2 (0x1<<0) // This is parity interrupt. It may be asserted when it was RSS RAM parity error. It will be de-asserted aftre write 1 to it. + #define VFC_REG_PARITY_IND_RSS_RAM_PARITY_BB_K2_SHIFT 0 #define VFC_REG_INDICATIONS1 0x000030UL //Access:R DataWidth:0x12 // Multi Field Register. #define VFC_REG_INDICATIONS1_INP_FIFO_EMPTY (0x1<<0) // Empty indication from input FIFO. #define VFC_REG_INDICATIONS1_INP_FIFO_EMPTY_SHIFT 0 @@ -7653,22 +10535,22 @@ #define VFC_REG_MEMORIES_RST 0x00003cUL //Access:RW DataWidth:0x3 // Multi Field Register. #define VFC_REG_MEMORIES_RST_CAM_RST (0x1<<0) // Write 1 to this bit will cause reset of all CAM rows including valid bit and all bits in a row. Write 0 to it will have no effect. Read 1 from this bit means that CAM reset was finished. Read 0 from this bit means that CAM reset was never done or not finished. #define VFC_REG_MEMORIES_RST_CAM_RST_SHIFT 0 - #define VFC_REG_MEMORIES_RST_RAM_RST (0x1<<1) // Write 1 to this bit will cause reset of all RSS RAM rows. Write 0 to it will have no effect. Read 1 from this bit means that RAM reset is in progress. Read 0 from this bit means that RAM reset was finished. - #define VFC_REG_MEMORIES_RST_RAM_RST_SHIFT 1 #define VFC_REG_MEMORIES_RST_TT_RST (0x1<<2) // Write 1 to this bit will cause reset of all Target tables rows. Write 0 to it will have no effect. Read 1 from this bit means that RAM reset was finished. Read 1 from this bit means that TT RAM reset is in progress. Read 0 from this bit means that TT RAM reset was finished. #define VFC_REG_MEMORIES_RST_TT_RST_SHIFT 2 + #define VFC_REG_MEMORIES_RST_RAM_RST_BB_K2 (0x1<<1) // Write 1 to this bit will cause reset of all RSS RAM rows. Write 0 to it will have no effect. Read 1 from this bit means that RAM reset is in progress. Read 0 from this bit means that RAM reset was finished. + #define VFC_REG_MEMORIES_RST_RAM_RST_BB_K2_SHIFT 1 #define VFC_REG_CAM_PARITY_EN 0x000040UL //Access:RW DataWidth:0x1 // REQUIRED -If this bit is set then background mechanism for parity check will be enabled; 0 - disabled. This bit must be disabled in palladium and FPGA. Init value of 1 must be done in a chip mode #define VFC_REG_CAM_CLK_DIVIDER 0x000044UL //Access:RW DataWidth:0x4 // Cam clock divider : may be equal to 2 only. #define VFC_REG_PARITY_MASK 0x000048UL //Access:RW DataWidth:0x3 // REQUIRED - 0 - parity is enabled;1 parity check is disabled. #define VFC_REG_INTERRUPT_MASK 0x00004cUL //Access:RW DataWidth:0xa // REQUIRED - 0 - interrupt is enabled;1- interrupt check is disabled. -#define VFC_REG_RSS_RAM_TM_0 0x000050UL //Access:RW DataWidth:0x5 // TM indication for RSS RAM instance 0. -#define VFC_REG_RSS_RAM_TM_1 0x000054UL //Access:RW DataWidth:0x5 // TM indication for RSS RAM instance 1. +#define VFC_REG_RSS_RAM_TM_0_BB_K2 0x000050UL //Access:RW DataWidth:0x5 // TM indication for RSS RAM instance 0. +#define VFC_REG_RSS_RAM_TM_1_BB_K2 0x000054UL //Access:RW DataWidth:0x5 // TM indication for RSS RAM instance 1. #define VFC_REG_INP_FIFO_TM 0x000058UL //Access:RW DataWidth:0x2 // TM indication for Input fifo. #define VFC_REG_CAM_TM 0x00005cUL //Access:RW DataWidth:0x14 // TM indication for CAM. #define VFC_REG_VFC_CAM_BIST_EN 0x000060UL //Access:RW DataWidth:0x1 // Bist enable bit for Cam. #define VFC_REG_VFC_CAM_BIST_DBG_SEL 0x000064UL //Access:RW DataWidth:0x8 // This select the type of data present on bist_status bus (slixe or status select). #define VFC_REG_VFC_CAM_BIST_STATUS 0x000068UL //Access:R DataWidth:0x20 // This returns the bist_status which can be done/go/sX_status. -#define VFC_REG_KEY_RSS_EXT5 0x00006cUL //Access:RW DataWidth:0x8 // Key extension for 5th tuple. +#define VFC_REG_KEY_RSS_EXT5_BB_K2 0x00006cUL //Access:RW DataWidth:0x8 // Key extension for 5th tuple. #define VFC_REG_INP_FIFO_ALM_FULL 0x000070UL //Access:RW DataWidth:0x5 // Almost full for input FIFO. When number of entries inside input FIFO is bigger or equal to this number then waitp to STORM will be asserted. #define VFC_REG_STORM_CMD_DISABLE 0x000074UL //Access:RW DataWidth:0x1 // When set then it disables selecting of commands from STORM. It will allow for RBC to configurate block. STORM command may be executed when this bit will be deasserted. #define VFC_REG_WAITP_STAT 0x000078UL //Access:RC DataWidth:0x20 // Statistics for number of cycles when waitp was raised to STORM as a result of full input FIFO. This vector will be reset after reading from it. It is also possible to write to it. @@ -7723,36 +10605,58 @@ #define VFC_REG_INP_FIFO_DBG_RD_EN 0x00011cUL //Access:RW DataWidth:0x1 // Input FIFO debug enable. #define VFC_REG_INP_FIFO_DBG_RD_ADD 0x000120UL //Access:RW DataWidth:0x4 // Input FIFO debug address. #define VFC_REG_CAM_BIST_SKIP_ERROR_CNT 0x000124UL //Access:RW DataWidth:0x8 // Provides a threshold for the number of CAM BIST errors that are acceptable before reporting CAM BIST failure status. -#define VFC_REG_PRTY_MASK_H_0 0x000204UL //Access:RW DataWidth:0x6 // Multi Field Register. - #define VFC_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT . - #define VFC_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_SHIFT 0 - #define VFC_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT . - #define VFC_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_SHIFT 1 - #define VFC_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_E5 (0x1<<2) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . - #define VFC_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_E5_SHIFT 2 - #define VFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY . - #define VFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT 3 - #define VFC_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . - #define VFC_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT 4 - #define VFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . - #define VFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT 5 +#define VFC_REG_PRTY_MASK_H_0 0x000204UL //Access:RW DataWidth:0x5 // Multi Field Register. + #define VFC_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT . + #define VFC_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_E5_SHIFT 0 + #define VFC_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_E5 (0x1<<1) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT . + #define VFC_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_E5_SHIFT 1 + #define VFC_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . + #define VFC_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5_SHIFT 2 + #define VFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2 (0x1<<5) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . + #define VFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT 5 + #define VFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . + #define VFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_E5_SHIFT 3 + #define VFC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . + #define VFC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5_SHIFT 4 + #define VFC_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT . + #define VFC_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_BB_K2_SHIFT 0 + #define VFC_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2 (0x1<<1) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT . + #define VFC_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_BB_K2_SHIFT 1 + #define VFC_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2 (0x1<<2) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . + #define VFC_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT 2 + #define VFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2 (0x1<<3) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY . + #define VFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT 3 + #define VFC_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2 (0x1<<4) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . + #define VFC_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT 4 #define VFC_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB (0x1<<2) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . #define VFC_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_SHIFT 2 #define VFC_REG_MEM_ECC_ENABLE_0 0x000210UL //Access:RW DataWidth:0x2 // Multi Field Register. - #define VFC_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4port - #define VFC_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_SHIFT 0 - #define VFC_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_4port - #define VFC_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_SHIFT 1 + #define VFC_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4port_e5 + #define VFC_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_E5_SHIFT 0 + #define VFC_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_E5 (0x1<<1) // Enable ECC for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_4port_e5 + #define VFC_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_E5_SHIFT 1 + #define VFC_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB_K2 (0x1<<0) // Enable ECC for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4port + #define VFC_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_BB_K2_SHIFT 0 + #define VFC_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_BB_K2 (0x1<<1) // Enable ECC for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_4port + #define VFC_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_BB_K2_SHIFT 1 #define VFC_REG_MEM_ECC_PARITY_ONLY_0 0x000214UL //Access:RW DataWidth:0x2 // Multi Field Register. - #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4port - #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_SHIFT 0 - #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_4port - #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_SHIFT 1 + #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4port_e5 + #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_E5_SHIFT 0 + #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_4port_e5 + #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_E5_SHIFT 1 + #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4port + #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_BB_K2_SHIFT 0 + #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_BB_K2 (0x1<<1) // Set parity only for memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_4port + #define VFC_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_BB_K2_SHIFT 1 #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0 0x000218UL //Access:RC DataWidth:0x2 // Multi Field Register. - #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4port - #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_SHIFT 0 - #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_4port - #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_SHIFT 1 + #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4port_e5 + #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_E5_SHIFT 0 + #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_E5 (0x1<<1) // Record if a correctable error occurred on memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_4port_e5 + #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_E5_SHIFT 1 + #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB_K2 (0x1<<0) // Record if a correctable error occurred on memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_ecc in module vfc_mem_tt1_4port + #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_BB_K2_SHIFT 0 + #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_BB_K2 (0x1<<1) // Record if a correctable error occurred on memory ecc instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_ecc in module vfc_mem_mtt2_4port + #define VFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_BB_K2_SHIFT 1 #define VFC_REG_MEM_ECC_EVENTS 0x00021cUL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. #define PB_REG_INT_STS 0x000040UL //Access:R DataWidth:0x9 // Multi Field Register. #define PB_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. @@ -33800,7 +36704,7 @@ #define MISC_REG_SW_TIMER_VAL_SIZE 8 #define MISCS_REG_RESET_CONFIG 0x009040UL //Access:RW DataWidth:0x20 // Reset configuration register. inside order of the bits is: [0] rst_ncsi_on_core_rst (0- no auto deassertion; 1 - auto deassertion); [1] rst_umac_on_core_rst (0- no auto deassertion; 1 - auto deassertion); [2] rst_mstat_on_core_rst (0- no auto deassertion; 1 - auto deassertion); [3] rst_cpmu_auto_mode (0- no auto deassertion; 1 - auto deassertion); [4] rst_pxpv_auto_mode (0- no auto deassertion; 1 - auto deassertion); [5] rst_nwm_mac_core_assert_on_core_rst (0 - no; 1 - yes); [6] rst_rbcb_auto_mode (0- no auto deassertion; 1 - auto deassertion); [7] rst_mcp_n_reset_reg_hard_core_auto_mode (0- no auto deassertion; 1 - auto deassertion); [8] rst_mcp_n_hard_core_rst_b_auto_mode (0- no autodeassertion; 1 - auto deassertion); [9] rst_mcp_n_reset_cmn_cpu_auto_mode (0- no auto deassertion;1 - auto deassertion); [10] rst_mcp_n_reset_cmn_core_auto_mode (0- no auto deassertion; 1 - auto deassertion); [11-13] reserved; [14] rst_misc_core_auto_mode (0- no auto deassertion; 1 - auto deassertion); [15] rst_dbue_auto_mode (0- no auto deassertion; 1 - auto deassertion); [16] grc_reset_assert_on_core_rst (0 - no; 1 - yes); [17] rst_mcp_n_reset_cmn_cpu_assert_on_core_rst (0 - no; 1 -yes); [18] rst_mcp_n_reset_cmn_core_assert_on_core_rst (0 - no; 1 - yes); [19] rst_rbc{n|h}_assert_on_core_rst (0 - no; 1 - yes); [20] rst_nwm_core_assert_on_core_rst (0 - no; 1 - yes); [21] rst_misc_core_assert_on_core_rst (0 - no; 1 - yes); [22] rst_dbue_assert_on_core_rst (0 - no; 1 - yes); [23] wrappers_iddq_and_rst_signals_assert_on_core_rst (0 - no; 1 - yes); [24] rst_rbcw_core_assert_on_core_rst (0 - no; 1 - yes); [25] rst_pglc_auto_mode (0- no auto deassertion; 1 - auto deassertion); [26] rst_bmb_on_core_rst (0- no reset on core reset; 1 - reset on core reset); [27] rst_opte_on_core_rst (0- no reset on core reset; 1 - reset on core reset); [28] rst_opcs_core_assert_on_core_rst (0 - no; 1 - yes); [29] rst_nws_core_assert_on_core_rst (0 - no; 1 - yes); [30] rst_ms_core_assert_on_core_rst (0 - no; 1 - yes); [31] rst_led_core_assert_on_core_rst (0 - no; 1 - yes) Reset on hard reset. #define MISCS_REG_RESET_CONFIG_POR 0x009044UL //Access:RW DataWidth:0x4 // Reset configuration register. inside order of the bits is: [0] rst_n_reg_hard_misc_rbc_pcie (0 - is not reset on hard reset; 1 - is reset on hard reset); [1] rst_n_hard_misc_rbc_pcie (0 - is not reset on hard reset; 1 - is reset on hard reset); [2] rst_n_hard_misc_erstclk_pcie (0 - is not reset on hard reset; 1 - is reset on hard reset); [3] reserved; Reset on POR reset. -#define MISCS_REG_RESET_PL_UA 0x009050UL //Access:RW DataWidth:0x20 // Reset_reg: Shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_cgrc; [1] rst_mcp_n_reset_reg_hard_core; [2] rst_mcp_n_hard_core_rst_b; [3] rst_mcp_n_reset_cmn_cpu; [4] rst_mcp_n_reset_cmn_core; [5] rst_misc_core; [6] rst_dbue (UART); [7] rst_bmb; [8] rst_ipc; [9]rst_crbcn; [10] reserved; [11] rst_avs; [31-10] reserved; Global register. +#define MISCS_REG_RESET_PL_UA 0x009050UL //Access:RW DataWidth:0x20 // Reset_reg: Shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_cgrc; [1] rst_mcp_n_reset_reg_hard_core; [2] rst_mcp_n_hard_core_rst_b; [3] rst_mcp_n_reset_cmn_cpu; [4] rst_mcp_n_reset_cmn_core; [5] rst_misc_core; [6] rst_dbue (UART); [7] rst_bmb; [8] rst_ipc; [9]rst_crbcn; [10] reserved; [31-11] reserved; Global register. #define MISCS_REG_RESET_PL_UA_SIZE 3 #define MISCS_REG_RESET_PL_HV 0x009060UL //Access:RW DataWidth:0x20 // Reset_reg: Shared blocks with protection level (PL=HV); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_cnig; [1] rst_pglc; [2] rst_pxpv; [3] rst_crbch; [4] rst_opte; [5] rst_ncsi; [6] rst_umac; [7] rst_mstat; [8] rst_cpmu; [9] rst_rbcb; [10] rst_rbcw; [11] rst_opcs; [12] rst_nws; [13] rst_ms; [14] rst_led; [31:15] reserved; Global register. #define MISCS_REG_RESET_PL_HV_SIZE 3 @@ -34159,7 +37063,7 @@ #define MISCS_REG_GEN_PURP_PORG 0x0096e4UL //Access:RW DataWidth:0x20 // Debug only: [31:11] - spare RW register reset by por reset; [10:8] : PCIe Device Type: 3'b000 - Endpoint mode; 3'b010 - RC mode; 3'b011 - RC mode, with Refclk provided by Serdes. [7:5] - spare RW register reset by por reset; [4] - SW control to the serdes uController reset. When =1 the serdes uController is reset; [3] - when 1 reset the Vmain Switching Regulator Controller PMU registers; [2] - when 1 disable the Vmain Switching Regulator Controller; [1] - when 1 reset the Vmgmt Switching Regulator Controller PMU registers; [0] - when 1 disable the Vmgmt Switching Regulator Controller. Global register. #define MISCS_REG_ISOLATION_LOGIC 0x0096e8UL //Access:R DataWidth:0x1 // The isolation between Vaux and Vmain read value. #define MISCS_REG_VMAIN_POR 0x0096ecUL //Access:RW DataWidth:0x2 // 0-bypass the Vmain PORBG. for Vmain POR; if sel=1 the output wil be MISC_REGISTERS_VMAIN_POR.VMAIN_POR [1]; 1- bypass the Vmain PORBG. If MISC_REGISTERS_VMAIN_POR.VMAIN_POR [0] is '1' the output of Vmain POR will be this field. -#define MISCS_REG_FUNCTION_HIDE_BB_K2 0x0096f0UL //Access:RW DataWidth:0x10 // Reserved. +#define MISCS_REG_FUNCTION_HIDE 0x0096f0UL //Access:RW DataWidth:0x10 // Bypass to the FUNC_HIDE pin. Bit 0 - bypass select; Bits[15:1] - bypass value per function (1 - function 1; 2 -function 2; etc.). When bypass select is 0, the value is selected depending on FUNC_HIDE pin and 4 port/2 port mode; when bypass select = 1; bypass value is selected. Reset on hard reset. #define MISCS_REG_PWR_ATTN 0x0096f4UL //Access:RW DataWidth:0x1 // This bit indicates that a Vmain powerdown event occurred. Write 0 to clear the event. Reset on hard reset. #define MISCS_REG_SMBIO_ENABLE_GLITCH_FILTER 0x0096f8UL //Access:RW DataWidth:0x1 // When set enables the deglitching circuit for the SMBus inputs per I2C requirement. #define MISCS_REG_PCIE_HOT_RESET 0x0096fcUL //Access:RC DataWidth:0x1 // If set indicate that the pcie_rst_b was asserted without perst assertion. @@ -34187,7 +37091,7 @@ #define MISCS_REG_UNPREPARED 0x009754UL //Access:RW DataWidth:0x1 // Set by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset on hard reset. #define MISCS_REG_UNPREPARED_FW 0x009758UL //Access:RW DataWidth:0x1 // Set by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset on hard reset. #define MISCS_REG_UNPREPARED_DR 0x00975cUL //Access:RW DataWidth:0x1 // Set by the Driver to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset on hard reset. -#define MISCS_REG_VAUX_PRESENT 0x009760UL //Access:R DataWidth:0x1 // 0 - VAUX is not present; 1 - VAUX is present. +#define MISCS_REG_VAUX_PRESENT 0x009760UL //Access:R DataWidth:0x1 // 0 - VAUX is not present (external pin is 0); 1 - VAUX is present (external pin is 1). #define MISCS_REG_VAUX_EN_DIS 0x009764UL //Access:RW DataWidth:0x8 // VAUX ENABLE Chip IO: when pulsed low enables supply from VAUX. VAUX DISABLE Chip IO: when pulsed low disables supply form VAUX. [7-6] RESERVED (FLOAT: these IOs are outputs only). [5-4] CLR: When any of these bits is written as a '1', the corresponding vaux_enable [bit 4]/ vaux_disable [bit 5] chip IOs will drive low. The read value of these bits will be '1' if the last command ( SET ; CLR ; or FLOAT ) for this bit was a CLR . (Reset value 0). [3-2] SET: When any of these bits is written as a '1', the corresponding vaux_enable [bit 2] / vaux_disable [bit 3] chip IOs will drive high. The read value of these bits will be '1' if the last command ( SET ; CLR ; or FLOAT ) for this bit was a SET . (Reset value 0). [1-0] RESERVED (VALUE RO). Global register. #define MISCS_REG_VAUX_EN_DIS_INT 0x009768UL //Access:RW DataWidth:0x8 // RESERVED. #define MISCS_REG_CHIP_NUM 0x00976cUL //Access:R DataWidth:0x10 // These bits indicate the part number for the chip. @@ -34436,9 +37340,10 @@ #define DBG_REG_CPU_TIMEOUT 0x010450UL //Access:RW DataWidth:0x1 // Debug only: Timeout operation initiated by the CPU; prior to initiating a timeout event all inputs must be disabled; Timeout signal must stay high until all data was fully sent to nig or pci and the internal buffer is empty. #define DBG_REG_DBG_BLOCK_ON 0x010454UL //Access:RW DataWidth:0x1 // Debug only: This bit enables the operation of the debug block; This bit should be set upon completion of all required configuration for the dbg block and shouldn't be reset during all operational phase of the block;. #define DBG_REG_NO_GRANT_ON_FULL 0x010458UL //Access:RW DataWidth:0x1 // Debug only: This bit indicate whether grant will be issued by the dbg block towards the storms in case the internal buffer is almost full as follows: (a) 1 - no grants will be made to the storms when the internal buffer is almost full. When the buffer will be partialy freed (enough for a complete data chunk) then grant is resumed; b) 0 - grant is supplied every time the matching storms's slot is chosen disregarding the volume status of the internal buffer. -#define DBG_REG_FULL_BUFFER_THR 0x01045cUL //Access:RW DataWidth:0x9 // Debug only: These bits indicate the value of the internal buffer almost full threshold used for deciding when dbg_sem_buffer_full output should go high/low; holds the number of 512 bit free lines in the internal buffer under which the full would go high; not applicable when DBG_REGISTERS_DEBUG_TARGET =0 (internal buffer) and DBG_REGISTERS_FULL_MODE =1 (wrap). NOTE: When filter_enable > 0 then this register should be >= 12. +#define DBG_REG_FULL_BUFFER_THR 0x01045cUL //Access:RW DataWidth:0x9 // Debug only: These bits indicate the value of the internal buffer almost full threshold used for deciding when dbg_sem_buffer_full output should go high/low; holds the number of 512 bit free lines in the internal buffer under which the full would go high; not applicable when DBG_REGISTERS_DEBUG_TARGET =0 (internal buffer) and DBG_REGISTERS_FULL_MODE =1 (wrap). NOTE: When filter_enable > 0 then this register should be >= 12. Together with DBG_REG_BUFFER_THR_HIGH provides histerezis-like mechanism to set SEMI grant. #define DBG_REG_PCI_LOGIC_ADDR 0x010460UL //Access:RW DataWidth:0x1 // Debug only: This bit indicates logical/physical address in PCI request as follows: (a) 1 - logical address; (b) 0 - physical address;. #define DBG_REG_IFMUX_SELECT_K2_E5 0x010464UL //Access:RW DataWidth:0x3 // Debug only: Selects 32b of data, valid and frame from the input stream to internal buffer to be output to IFMUX interface. 0 - bits[31:0] 1 - bits[63:32] 2:6 - etc. 7 - bits[255:224] +#define DBG_REG_FULL_BUFFER_THR_HIGH_E5 0x010468UL //Access:RW DataWidth:0x9 // Debug only: together with DBG_REG_BUFFER_THR provides histerezis-like mechanism to set SEMI grant. When the number of empty lines of 512b in internal buffer is less than DBG_REG_BUFFER_THR the SEMI grant is stopped. When the number of empty lines of 512b in internal buffer is more than DBG_REG_BUFFER_THR_HIGH SEMI grant is resumed. Not applicable when DBG_REGISTERS_DEBUG_TARGET =0 (internal buffer) and DBG_REGISTERS_FULL_MODE =1 (wrap). NOTE: When filter_enable > 0 then this register should be >= 13. #define DBG_REG_CALENDAR_OUT_DATA 0x010480UL //Access:WB_R DataWidth:0x132 // Debug only: These bits indicate the value of the sop; data; frame and valid output of the calendar; The concatenation is done as follows: bits 255:0 - data; bits 263:256 - frame; bits 271:264 - valid; bits 303:272 - ID; bits 305:304 - SOP. #define DBG_REG_CALENDAR_OUT_DATA_SIZE 16 #define DBG_REG_EXPECTED_PATTERN 0x0104c0UL //Access:WB DataWidth:0x132 // Debug only: For pattern recognition usage: These bits represent the pattern to be compared with the vector {sop[1:0]; id[31:0]; valid[7:0];frame[7:0]; data[255:0]}; This vector represent the debug data it's slot number and it's frame signals that are going to stored in the internal buffer; to allow recognize sop the following should be applied: trigger_enable=1 and filter_enable>0.NOTE: In order to take into consideration the SOP value set trigger_enable=1 and filter_enable>0 @@ -34949,7 +37854,7 @@ #define DBG_REG_TRIGGER_STATUS_STATE_TRANSITIONS_0 0x010b7cUL //Access:R DataWidth:0x10 // Debug only: Number of transitions per state. #define DBG_REG_TRIGGER_STATUS_STATE_TRANSITIONS_1 0x010b80UL //Access:R DataWidth:0x10 // Debug only: Number of transitions per state. #define DBG_REG_TRIGGER_STATUS_STATE_TRANSITIONS_2 0x010b84UL //Access:R DataWidth:0x10 // Debug only: Number of transitions per state. -#define DBG_REG_TRAILER_STATUS_CUR_STATE 0x010b88UL //Access:R DataWidth:0x2 // Debug only: Current state status in trailer block : 0 - WAIT_FOR_NEW_LINE; 1- END_OF_CHUNK; 2 - SEND_ADDITIONAL_CHUNK; 3 - SEND_ADDITIONAL_LINE. +#define DBG_REG_TRAILER_STATUS_CUR_STATE 0x010b88UL //Access:R DataWidth:0x3 // Debug only: Current state status in trailer block : 0 - WAIT_FOR_NEW_LINE; 1- END_OF_CHUNK; 2 - SEND_ADDITIONAL_CHUNK; 3 - SEND_ADDITIONAL_LINE; 4 - FIRST_LINE_OF_NEW_CHUNK. #define DBG_REG_TRAILER_STATUS_VALID_DWORDS 0x010b8cUL //Access:R DataWidth:0x6 // Debug only: number of valid dwords in trailer block. #define DBG_REG_FILTER_STATUS_MATCH_CNSTR 0x010b90UL //Access:R DataWidth:0x4 // Statistics. Match constraint status. B0 - constraint 0; B1 - constraint 1; B2 - constraint 2 ; B3 - constraint 3. #define DBG_REG_MEMCTRL_WR_RD_N_BB 0x010b94UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST @@ -34961,47 +37866,70 @@ #define DBG_REG_TRIGGER_SEMI_CORE_E5 0x010bacUL //Access:RW DataWidth:0x1 // When 0 - SEMI core A is selected for all trigger/filter related activities; when 1 - SEMI core B. #define DBG_REG_INTR_BUFFER 0x014000UL //Access:WB DataWidth:0x200 // Debug only: Internal buffer of 12KByte buffer. #define DBG_REG_INTR_BUFFER_SIZE 3072 -#define IPC_REG_PLL_MAIN_DIVR_K2_E5 0x020200UL //Access:RW DataWidth:0x6 // PLLLOUT = REF / DIVR_Value * DIVF_Value * 2 / DIVQ_Value Reference divider value +#define IPC_REG_PLL_MAIN_BYPASS_K2 0x020210UL //Access:RW DataWidth:0x1 // pll bypass signal +#define IPC_REG_PLL_MAIN_BYPASS_E5 0x020200UL //Access:RW DataWidth:0x1 // 0: output clock comes from core_pll (default) 1: output clock is buffered bypass clock; overrides pll_ref_sel +#define IPC_REG_PLL_MAIN_DIVR_K2 0x020200UL //Access:RW DataWidth:0x6 // PLLLOUT = REF / DIVR_Value * DIVF_Value * 2 / DIVQ_Value Reference divider value #define IPC_REG_MDIO_VOLTAGE_SEL_BB 0x020200UL //Access:RW DataWidth:0x1 // Select line for MDIO Voltage Select 0 : MDIO VDDIO is 1.8V or below. 1 : MDIO VDDIO is 1.8+V or above. -#define IPC_REG_PLL_MAIN_DIVF_K2_E5 0x020204UL //Access:RW DataWidth:0x9 // Feedback divider value +#define IPC_REG_PLL_MAIN_BYPASS_PDB_E5 0x020204UL //Access:RW DataWidth:0x1 // 0: bypass clock level converter power down (default) 1: bypass clock level converter power on +#define IPC_REG_PLL_MAIN_DIVF_K2 0x020204UL //Access:RW DataWidth:0x9 // Feedback divider value #define IPC_REG_CPU_OTP_CTRL1_BB 0x020204UL //Access:RW DataWidth:0x20 // [0]: cpu_cmd_wr_en: A rising edge of this bit will execute the OTP "command" in the next field. This bit should be set to Low and high again for the next command execution to start; [5:1]: Command: 0: Read; 1: OTP_ProgEnable (OTP must be put in ProgEnable mode by writing 0xF; 0x4; 0x8; 0xD in sequence with OTP_ProgEnable command before you do any actual write to OTP. Sequence Data is taken from bitsel bus and therefore word_address and wdata do not play any role during this authentication process; 2: OTP_ProgDisable (Disable OTP with this command once you are done with programming); 3: Verify( vsel and tm are used from control bits); 4: Init (vsel and tm are used from strap module); 5: lock_cmd. used to program the lock bits that can not be programmed by using regular program bit and program Word cmd. OTP word address 6 and 7 are allocated for lock bits and to program these bits lock command must be used; 6: stby (Not used in this IP); 7: wakeup (Not used in this IP); 9: Prescreen test. Upon getting a prescrn_cmd; word_addr; and bit_sel; otp_controller keeps reading(simple read) the OTP MEMORY SPACE until it reaches the max word_addr or it finds any programmed bit; 10: Program Bit; 11: Program Word; 12: burnin. Upon getting a burnin_cmd; word_addr; and bit_sel; otp_controller keeps reading(simple read) the OTP MEMORY SPACE. It keeps looping until the cmd is changed from burnin to something else; 13: auto_reload; 14: ovst_read; 15: ovst_prog; [17:6]: Address; [18]: cpu_mode: When set, enables command execution through this cpu interface; [19]: cpu_disable_otp_access: When set, disables any command execution through this cpu interface. [31:20]: RESERVED; -#define IPC_REG_PLL_MAIN_DIVQ_K2_E5 0x020208UL //Access:RW DataWidth:0x3 // output divider value, 2^binary value +#define IPC_REG_PLL_MAIN_CPB_E5 0x020208UL //Access:RW DataWidth:0x4 // charge pump current setting for Cb (default 0000) +#define IPC_REG_PLL_MAIN_DIVQ_K2 0x020208UL //Access:RW DataWidth:0x3 // output divider value, 2^binary value #define IPC_REG_CPU_OTP_STATUS_BB 0x020208UL //Access:R DataWidth:0x20 // [0]: data_valid: This bit is used to sample READ data in burst mode; [1]: cmd_done: Command Done, This signal indicates the completion of the command; [2]: progok: Program OK, This signal is set when PROG ENABLE sequence is issued correctly; [3]: fdone: This signal is set when fout bits are loaded; [4]: cmd_fail: Command Failure, This bit is set when locked address is accessed using program related commands; [5]: refok: OTP RefOK signal; [6]: debug_mode_set: This bit is set when ctrl_wr_cmd is issued; [7]: mst_fsm_error: An illegal state has executed. This bit is set to '0' in idle state, otherwise '1' in all other states; [8]: debug_mode: This bit is set using ctrl_wr command and indicates the debug mode option; [9]: invalid_addr: This bit is set when Locked address is accessed by program related commands or when address is out of range; [10]: prog_word_fail: This bit is set when Programming fails for a bit during word program; [11]: prog_screen_fail: This bit is set when screening fails for word programming. [12]: prog_block_cmd: Invalid for CPU mode; [13]: prog_en: By default this is set to enable PROG command; [14]: prgm_wd_rp_fail: TBD; [15]: max_rw: TBD; [16]: max_rwp: TBD; [17]: auto_rw_max_set: TBD; [18]: max_sw: TBD; [19]: addr_in_illegal_range: TBD; [31:20]: Reserved; -#define IPC_REG_PLL_MAIN_RANGE_K2_E5 0x02020cUL //Access:RW DataWidth:0x3 // PLL Filter Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 011 = 18-30MHz 111 = 130-200MHz +#define IPC_REG_PLL_MAIN_CPS_E5 0x02020cUL //Access:RW DataWidth:0x4 // charge pump current setting for Cs (default 0000) +#define IPC_REG_PLL_MAIN_RANGE_K2 0x02020cUL //Access:RW DataWidth:0x3 // PLL Filter Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 011 = 18-30MHz 111 = 130-200MHz #define IPC_REG_CPU_OTP_WRITE_DATA_BB 0x02020cUL //Access:RW DataWidth:0x20 // Used to provide write data with burst write command from CPU side. -#define IPC_REG_PLL_MAIN_BYPASS_K2_E5 0x020210UL //Access:RW DataWidth:0x1 // pll bypass signal +#define IPC_REG_PLL_MAIN_DIFFAMP_E5 0x020210UL //Access:RW DataWidth:0x4 // diffamp bias current setting (default 0000) #define IPC_REG_CPU_OTP_READ_DATA_BB 0x020210UL //Access:R DataWidth:0x20 // Data output from the OTP read data command. -#define IPC_REG_PLL_MAIN_LOCK_K2_E5 0x020214UL //Access:R DataWidth:0x1 // pll lock signal +#define IPC_REG_PLL_MAIN_BG_CLK_EN_E5 0x020214UL //Access:RW DataWidth:0x1 // 0: bandgap gap chopping disabled (default) 1: bandgap gap chopping enabled +#define IPC_REG_PLL_MAIN_LOCK_K2 0x020214UL //Access:R DataWidth:0x1 // pll lock signal #define IPC_REG_OSC_E28_XCORE_BIAS_BB 0x020214UL //Access:RW DataWidth:0x4 // XTAL core current control 4'b0010: 27Mhz 4'b0100: 50Mhz Device will be using 50Mhz crytal, so defaults to a value of 4. Global Register, Reset on POR -#define IPC_REG_PLL_MAIN_LOCK_DETECT_FILTER_STATUS_K2_E5 0x020218UL //Access:R DataWidth:0x1 // pll lock detected filter status +#define IPC_REG_PLL_MAIN_BG_DIV16_EN_E5 0x020218UL //Access:RW DataWidth:0x1 // 0: bandgap clock freq = ref clock freq/4 (default) 1: bandgap clock freq = ref clock freq/16 +#define IPC_REG_PLL_MAIN_LOCK_DETECT_FILTER_STATUS_K2 0x020218UL //Access:R DataWidth:0x1 // pll lock detected filter status #define IPC_REG_OSC_E28_XCORE_BIAS_OVERRIDE_BB 0x020218UL //Access:RW DataWidth:0x1 // XCORE_BIAS in normal operation is controlled by straps on the board. This bit allows it SW to override the setting based on register osc_e28_xcore_bias Global Register, Reset on POR -#define IPC_REG_PLL_MAIN_NEWDIV_K2_E5 0x02021cUL //Access:RW DataWidth:0x1 // Divider input control +#define IPC_REG_PLL_MAIN_CLKF_E5 0x02021cUL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf setting table for division settings +#define IPC_REG_PLL_MAIN_NEWDIV_K2 0x02021cUL //Access:RW DataWidth:0x1 // Divider input control #define IPC_REG_OSC_E28_HIPASS_BB 0x02021cUL //Access:RW DataWidth:0x1 // XTAL core Highpass Filter Corner Frequency control 0: 27Mhz 1: 50Mhz Device will be using 50Mhz crytal, so defaults to a value of 1. Global Register, Reset on POR -#define IPC_REG_PLL_MAIN_DIVACK_K2_E5 0x020220UL //Access:R DataWidth:0x1 // Divider handshake signal +#define IPC_REG_PLL_MAIN_CPAMP_E5 0x020220UL //Access:RW DataWidth:0x1 // charge pump internal opamp setting (default 0) +#define IPC_REG_PLL_MAIN_DIVACK_K2 0x020220UL //Access:R DataWidth:0x1 // Divider handshake signal #define IPC_REG_OSC_E28_HIPASS_OVERRIDE_BB 0x020220UL //Access:RW DataWidth:0x1 // HIPASS in normal operation is controlled by straps on the board. This bit allows it SW to override the setting based on register osc_e28_hipass Global Register, Reset on POR -#define IPC_REG_PLL_MAIN_RESET_K2_E5 0x020224UL //Access:RW DataWidth:0x5 // Multi Field Register. - #define IPC_REG_PLL_MAIN_RESET_PLL_MAIN_RESET_K2_E5 (0x1<<0) // 1 : Reset the PLL. The reset is active high. - #define IPC_REG_PLL_MAIN_RESET_PLL_MAIN_RESET_K2_E5_SHIFT 0 - #define IPC_REG_PLL_MAIN_RESET_OVERRIDE_K2_E5 (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register. - #define IPC_REG_PLL_MAIN_RESET_OVERRIDE_K2_E5_SHIFT 4 +#define IPC_REG_PLL_MAIN_DIV1_E5 0x020224UL //Access:RW DataWidth:0x1 // 0: divide core_pll clock by 2/4/8/16 according to postdiv setting (default) 1: no division on the core_pll clock (no 50% duty cycle) #define IPC_REG_OSC_E28_D2C_BIAS_BB 0x020224UL //Access:RW DataWidth:0x3 // D2C Bias Current Control Global Register, Reset on POR -#define IPC_REG_PLL_MAIN_LOCK_DETECT_FILTER_STATUS_WAS_CLEARED_K2_E5 0x020228UL //Access:RW DataWidth:0x1 // Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases. +#define IPC_REG_PLL_MAIN_REF_BYPASS_E5 0x020228UL //Access:RW DataWidth:0x1 // 0: ref clock not from the bypass path (default) 1: ref clock from the bypass path +#define IPC_REG_PLL_MAIN_LOCK_DETECT_FILTER_STATUS_WAS_CLEARED_K2 0x020228UL //Access:RW DataWidth:0x1 // Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases. #define IPC_REG_OSC_E28_CML_CUR_BB 0x020228UL //Access:RW DataWidth:0x1 // CML Current Control Global Register, Reset on POR -#define IPC_REG_PLL_NWM_DIVR_K2_E5 0x02022cUL //Access:RW DataWidth:0x6 // PLLLOUT = REF / DIVR_Value * DIVF_Value * 2 / DIVQ_Value Reference divider value +#define IPC_REG_PLL_MAIN_REF_HCSL_E5 0x02022cUL //Access:RW DataWidth:0x1 // 0: disable HCSL ref clock termination (default) 1: enable HCSL ref clock termination when pll_ref_oct is set to 1 +#define IPC_REG_PLL_NWM_DIVR_K2 0x02022cUL //Access:RW DataWidth:0x6 // PLLLOUT = REF / DIVR_Value * DIVF_Value * 2 / DIVQ_Value Reference divider value #define IPC_REG_OSC_E28_DRV_CUR_BB 0x02022cUL //Access:RW DataWidth:0x2 // 50ohm Driver Current Control 00 = 5mA 01 = 10mA 10 = 15mA 11 = 20mA Global Register, Reset on POR -#define IPC_REG_PLL_NWM_DIVF_K2_E5 0x020230UL //Access:RW DataWidth:0x9 // Feedback divider value +#define IPC_REG_PLL_MAIN_REF_OCT_E5 0x020230UL //Access:RW DataWidth:0x1 // 0: disable 50 Ohm on chip termination (default) 1: enable 50 Ohm on chip termination +#define IPC_REG_PLL_NWM_DIVF_K2 0x020230UL //Access:RW DataWidth:0x9 // Feedback divider value #define IPC_REG_OSC_E28_DIV2_SEL_BB 0x020230UL //Access:RW DataWidth:0x1 // Divide by 2 Selection for pad_op/n_cml output 0=XTAL Freq. 1=XTAL Freq. / 2 Global Register, Reset on POR -#define IPC_REG_PLL_NWM_DIVQ_K2_E5 0x020234UL //Access:RW DataWidth:0x3 // output divider value, 2^binary value +#define IPC_REG_PLL_MAIN_PLL_PWDN_E5 0x020234UL //Access:RW DataWidth:0x1 // 0: power down disabled (default) 1: power down enabled +#define IPC_REG_PLL_NWM_DIVQ_K2 0x020234UL //Access:RW DataWidth:0x3 // output divider value, 2^binary value #define IPC_REG_OSC_E28_LDO_CTRL_BB 0x020234UL //Access:RW DataWidth:0x4 // [3:2] LDO Output Stage Bias Control [1:0] LDO Output Voltage Level Control 00 = 1.05V 01 = 1.00V 10 = 0.95V 11 = 0.90V Global Register, Reset on POR -#define IPC_REG_PLL_NWM_RANGE_K2_E5 0x020238UL //Access:RW DataWidth:0x3 // PLL Filter Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 011 = 18-30MHz 111 = 130-200MHz +#define IPC_REG_PLL_MAIN_POSTDIV_E5 0x020238UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): refer to postdiv setting table for division settings +#define IPC_REG_PLL_NWM_RANGE_K2 0x020238UL //Access:RW DataWidth:0x3 // PLL Filter Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 011 = 18-30MHz 111 = 130-200MHz #define IPC_REG_OSC_E28_CMOS_EN_ALL_BB 0x020238UL //Access:RW DataWidth:0x1 // ENABLE All CMOS Outputs 0=o_xtal_ck[5:0] depends on i_resetb and i_cmos_en_ch[5:0] 1=o_xtal_ck[5:0] ALL ON Global Register, Reset on POR -#define IPC_REG_PLL_NWM_RESET_K2_E5 0x02023cUL //Access:RW DataWidth:0x1 // pll reset signal +#define IPC_REG_PLL_MAIN_PREDIV_E5 0x02023cUL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3): refer to prediv setting table for division settings +#define IPC_REG_PLL_NWM_RESET_K2 0x02023cUL //Access:RW DataWidth:0x1 // pll reset signal #define IPC_REG_OSC_E28_CMOS_EN_CH_BB 0x02023cUL //Access:RW DataWidth:0x6 // Enable for CMOS outputs 0=CMOS output DISABLED 1=CMOS output ENABLED Bit[0] = o_xtal_ck0 Bit[1] = o_xtal_ck1 Bit[2] = o_xtal_ck2 Bit[3] = o_xtal_ck3 Bit[4] = o_xtal_ck4 Bit[5] = o_xtal_ck5 Global Register, Reset on POR -#define IPC_REG_PLL_NWM_BYPASS_K2_E5 0x020240UL //Access:RW DataWidth:0x1 // pll bypass signal +#define IPC_REG_PLL_MAIN_REP_E5 0x020240UL //Access:RW DataWidth:0x1 // regamp internal setting (default 0) +#define IPC_REG_PLL_NWM_BYPASS_K2 0x020240UL //Access:RW DataWidth:0x1 // pll bypass signal #define IPC_REG_OSC_E28_CML_EN_CH_BB 0x020240UL //Access:RW DataWidth:0x4 // CML Output Channel Power Down 0=CML output ON 1=CML output OFF Bit[0] = o_cml_p/n 0 Bit[1] = o_cml_p/n 1 Bit[2] = o_cml_p/n 2 Bit[3] = o_cml_p/n 3 Global Register, Reset on POR -#define IPC_REG_PLL_NWM_LOCK_K2_E5 0x020244UL //Access:R DataWidth:0x1 // pll lock signal +#define IPC_REG_PLL_MAIN_RESET_K2 0x020224UL //Access:RW DataWidth:0x5 // Multi Field Register. +#define IPC_REG_PLL_MAIN_RESET_E5 0x020244UL //Access:RW DataWidth:0x5 // Multi Field Register. + #define IPC_REG_PLL_MAIN_RESET_PLL_MAIN_RESET_K2_E5 (0x1<<0) // 0: pll reset disabled 1: pll reset enabled + #define IPC_REG_PLL_MAIN_RESET_PLL_MAIN_RESET_K2_E5_SHIFT 0 + #define IPC_REG_PLL_MAIN_RESET_OVERRIDE_K2_E5 (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register. + #define IPC_REG_PLL_MAIN_RESET_OVERRIDE_K2_E5_SHIFT 4 +#define IPC_REG_PLL_NWM_LOCK_K2 0x020244UL //Access:R DataWidth:0x1 // pll lock signal #define IPC_REG_OSC_E28_PD_DRV_BB 0x020244UL //Access:RW DataWidth:0x1 // 50ohm Driver Power Down 0=Driver ENABLED 1=Driver DISABLED Global Register, Reset on POR -#define IPC_REG_PLL_NWM_LOCK_DETECT_FILTER_STATUS_K2_E5 0x020248UL //Access:R DataWidth:0x1 // pll lock detected filter status +#define IPC_REG_PLL_MAIN_LOGIC_RESET_E5 0x020248UL //Access:RW DataWidth:0x5 // Multi Field Register. + #define IPC_REG_PLL_MAIN_LOGIC_RESET_PLL_MAIN_LOGIC_RESET_E5 (0x1<<0) // 0: post scaler reset disabled 1: post scaler reset enabled + #define IPC_REG_PLL_MAIN_LOGIC_RESET_PLL_MAIN_LOGIC_RESET_E5_SHIFT 0 + #define IPC_REG_PLL_MAIN_LOGIC_RESET_OVERRIDE_E5 (0x1<<4) // 1 : Override the init state machine and control the PLL logic reset using bit[0] of the register. + #define IPC_REG_PLL_MAIN_LOGIC_RESET_OVERRIDE_E5_SHIFT 4 +#define IPC_REG_PLL_NWM_LOCK_DETECT_FILTER_STATUS_K2 0x020248UL //Access:R DataWidth:0x1 // pll lock detected filter status #define IPC_REG_OSC_E28_MISC_BB 0x020248UL //Access:RW DataWidth:0x5 // Multi Field Register. #define IPC_REG_OSC_E28_MISC_OSC_E28_POWER_SAVE_BB (0x1<<0) // Future Use #define IPC_REG_OSC_E28_MISC_OSC_E28_POWER_SAVE_BB_SHIFT 0 @@ -35009,123 +37937,216 @@ #define IPC_REG_OSC_E28_MISC_OSC_E28_BIAS_BB_SHIFT 1 #define IPC_REG_OSC_E28_MISC_OSC_E28_XCORE_CM_SEL_BB (0x1<<4) // Future Use #define IPC_REG_OSC_E28_MISC_OSC_E28_XCORE_CM_SEL_BB_SHIFT 4 -#define IPC_REG_PLL_NWM_NEWDIV_K2_E5 0x02024cUL //Access:RW DataWidth:0x1 // Divider input control +#define IPC_REG_PLL_MISC_BYPASS_E5 0x02024cUL //Access:RW DataWidth:0x1 // 0: output clock comes from core_pll (default) 1: output clock is buffered bypass clock; overrides pll_ref_sel +#define IPC_REG_PLL_NWM_NEWDIV_K2 0x02024cUL //Access:RW DataWidth:0x1 // Divider input control #define IPC_REG_PLL_MAIN_E28_PWRDN_BB 0x02024cUL //Access:RW DataWidth:0x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR -#define IPC_REG_PLL_NWM_DIVACK_K2_E5 0x020250UL //Access:R DataWidth:0x1 // Divider handshake signal +#define IPC_REG_PLL_MISC_BYPASS_PDB_E5 0x020250UL //Access:RW DataWidth:0x1 // 0: bypass clock level converter power down (default) 1: bypass clock level converter power on +#define IPC_REG_PLL_NWM_DIVACK_K2 0x020250UL //Access:R DataWidth:0x1 // Divider handshake signal #define IPC_REG_PLL_MAIN_E28_RESET_VCO_BB 0x020250UL //Access:RW DataWidth:0x5 // Multi Field Register. #define IPC_REG_PLL_MAIN_E28_RESET_VCO_PLL_MAIN_RESET_VCO_BB (0x1<<0) // 1 : Reset the VCO of the PLL. The reset is active high. Global Register, Reset on POR #define IPC_REG_PLL_MAIN_E28_RESET_VCO_PLL_MAIN_RESET_VCO_BB_SHIFT 0 #define IPC_REG_PLL_MAIN_E28_RESET_VCO_PLL_MAIN_RESET_VCO_OVERRIDE_BB (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register. #define IPC_REG_PLL_MAIN_E28_RESET_VCO_PLL_MAIN_RESET_VCO_OVERRIDE_BB_SHIFT 4 -#define IPC_REG_PLL_NWM_LOCK_DETECT_FILTER_STATUS_WAS_CLEARED_K2_E5 0x020254UL //Access:RW DataWidth:0x1 // Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases. +#define IPC_REG_PLL_MISC_CPB_E5 0x020254UL //Access:RW DataWidth:0x4 // charge pump current setting for Cb (default 0000) +#define IPC_REG_PLL_NWM_LOCK_DETECT_FILTER_STATUS_WAS_CLEARED_K2 0x020254UL //Access:RW DataWidth:0x1 // Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases. #define IPC_REG_PLL_MAIN_E28_RESET_POST_BB 0x020254UL //Access:RW DataWidth:0x5 // Multi Field Register. #define IPC_REG_PLL_MAIN_E28_RESET_POST_PLL_MAIN_RESET_POST_BB (0x1<<0) // 1 : Reset the Post Divider of the PLL. The reset is active high. Global Register, Reset on POR #define IPC_REG_PLL_MAIN_E28_RESET_POST_PLL_MAIN_RESET_POST_BB_SHIFT 0 #define IPC_REG_PLL_MAIN_E28_RESET_POST_PLL_MAIN_RESET_POST_OVERRIDE_BB (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register. #define IPC_REG_PLL_MAIN_E28_RESET_POST_PLL_MAIN_RESET_POST_OVERRIDE_BB_SHIFT 4 -#define IPC_REG_PLL_STORM_DIVR_K2_E5 0x020258UL //Access:RW DataWidth:0x6 // PLLLOUT = REF / DIVR_Value * DIVF_Value * 2 / DIVQ_Value Reference divider value +#define IPC_REG_PLL_MISC_CPS_E5 0x020258UL //Access:RW DataWidth:0x4 // charge pump current setting for Cs (default 0000) +#define IPC_REG_PLL_STORM_DIVR_K2 0x020258UL //Access:RW DataWidth:0x6 // PLLLOUT = REF / DIVR_Value * DIVF_Value * 2 / DIVQ_Value Reference divider value #define IPC_REG_PLL_MAIN_E28_PDIV_BB 0x020258UL //Access:RW DataWidth:0x4 // Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset. -#define IPC_REG_PLL_STORM_DIVF_K2_E5 0x02025cUL //Access:RW DataWidth:0x9 // Feedback divider value +#define IPC_REG_PLL_MISC_DIFFAMP_E5 0x02025cUL //Access:RW DataWidth:0x4 // diffamp bias current setting (default 0000) +#define IPC_REG_PLL_STORM_DIVF_K2 0x02025cUL //Access:RW DataWidth:0x9 // Feedback divider value #define IPC_REG_PLL_MAIN_E28_NDIV_INT_BB 0x02025cUL //Access:RW DataWidth:0xa // Feedback divider control 0000000000= divide-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= divide-by-13 0000001110= divide-by-14 : 1111111110= divide-by-1022 1111111111= divide-by-1023 Global register. Reset on POR reset. -#define IPC_REG_PLL_STORM_DIVQ_K2_E5 0x020260UL //Access:RW DataWidth:0x3 // output divider value, 2^binary value +#define IPC_REG_PLL_MISC_BG_CLK_EN_E5 0x020260UL //Access:RW DataWidth:0x1 // 0: bandgap gap chopping disabled (default) 1: bandgap gap chopping enabled +#define IPC_REG_PLL_STORM_DIVQ_K2 0x020260UL //Access:RW DataWidth:0x3 // output divider value, 2^binary value #define IPC_REG_PLL_MAIN_E28_NDIV_FRAC_BB 0x020260UL //Access:RW DataWidth:0x14 // Fractional feedback divider control. Resolution= 1/(2^20). Global register. Reset on POR reset. -#define IPC_REG_PLL_STORM_RANGE_K2_E5 0x020264UL //Access:RW DataWidth:0x3 // PLL Filter Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 011 = 18-30MHz 111 = 130-200MHz +#define IPC_REG_PLL_MISC_BG_DIV16_EN_E5 0x020264UL //Access:RW DataWidth:0x1 // 0: bandgap clock freq = ref clock freq/4 (default) 1: bandgap clock freq = ref clock freq/16 +#define IPC_REG_PLL_STORM_RANGE_K2 0x020264UL //Access:RW DataWidth:0x3 // PLL Filter Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 011 = 18-30MHz 111 = 130-200MHz #define IPC_REG_PLL_MAIN_E28_CH0_MDIV_BB 0x020264UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset. -#define IPC_REG_PLL_STORM_RESET_K2_E5 0x020268UL //Access:RW DataWidth:0x1 // pll reset signal +#define IPC_REG_PLL_MISC_CLKF_E5 0x020268UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf setting table for division settings #define IPC_REG_PLL_MAIN_E28_CH1_MDIV_BB 0x020268UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset. -#define IPC_REG_PLL_STORM_BYPASS_K2_E5 0x02026cUL //Access:RW DataWidth:0x1 // pll bypass signal +#define IPC_REG_PLL_MISC_CPAMP_E5 0x02026cUL //Access:RW DataWidth:0x1 // charge pump internal opamp setting (default 0) #define IPC_REG_PLL_MAIN_E28_CH2_MDIV_BB 0x02026cUL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-2 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset. -#define IPC_REG_PLL_STORM_LOCK_K2_E5 0x020270UL //Access:R DataWidth:0x1 // pll lock signal +#define IPC_REG_PLL_MISC_DIV1_E5 0x020270UL //Access:RW DataWidth:0x1 // 0: divide core_pll clock by 2/4/8/16 according to postdiv setting (default) 1: no division on the core_pll clock (no 50% duty cycle) +#define IPC_REG_PLL_STORM_LOCK_K2 0x020270UL //Access:R DataWidth:0x1 // pll lock signal #define IPC_REG_PLL_MAIN_E28_CH3_MDIV_BB 0x020270UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-3 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset. -#define IPC_REG_PLL_STORM_LOCK_DETECT_FILTER_STATUS_K2_E5 0x020274UL //Access:R DataWidth:0x1 // pll lock detected filter status +#define IPC_REG_PLL_MISC_REF_BYPASS_E5 0x020274UL //Access:RW DataWidth:0x1 // 0: ref clock not from the bypass path (default) 1: ref clock from the bypass path +#define IPC_REG_PLL_STORM_LOCK_DETECT_FILTER_STATUS_K2 0x020274UL //Access:R DataWidth:0x1 // pll lock detected filter status #define IPC_REG_PLL_MAIN_E28_CH4_MDIV_BB 0x020274UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-4 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset. -#define IPC_REG_PLL_STORM_NEWDIV_K2_E5 0x020278UL //Access:RW DataWidth:0x1 // Divider input control +#define IPC_REG_PLL_MISC_REF_HCSL_E5 0x020278UL //Access:RW DataWidth:0x1 // 0: disable HCSL ref clock termination (default) 1: enable HCSL ref clock termination when pll_ref_oct is set to 1 +#define IPC_REG_PLL_STORM_NEWDIV_K2 0x020278UL //Access:RW DataWidth:0x1 // Divider input control #define IPC_REG_PLL_MAIN_E28_CH5_MDIV_BB 0x020278UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-5 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset. -#define IPC_REG_PLL_STORM_DIVACK_K2_E5 0x02027cUL //Access:R DataWidth:0x1 // Divider handshake signal +#define IPC_REG_PLL_MISC_REF_OCT_E5 0x02027cUL //Access:RW DataWidth:0x1 // 0: disable 50 Ohm on chip termination (default) 1: enable 50 Ohm on chip termination +#define IPC_REG_PLL_STORM_DIVACK_K2 0x02027cUL //Access:R DataWidth:0x1 // Divider handshake signal #define IPC_REG_PLL_MAIN_E28_CH2_MDEL_BB 0x02027cUL //Access:RW DataWidth:0x10 // Number to VCO clock to delay Channel 2 Global register. Reset on POR reset. -#define IPC_REG_PLL_STORM_LOCK_DETECT_FILTER_STATUS_WAS_CLEARED_K2_E5 0x020280UL //Access:RW DataWidth:0x1 // Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases. +#define IPC_REG_PLL_MISC_PLL_PWDN_E5 0x020280UL //Access:RW DataWidth:0x1 // 0: power down disabled (default) 1: power down enabled +#define IPC_REG_PLL_STORM_LOCK_DETECT_FILTER_STATUS_WAS_CLEARED_K2 0x020280UL //Access:RW DataWidth:0x1 // Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases. #define IPC_REG_PLL_MAIN_E28_CH3_MDEL_BB 0x020280UL //Access:RW DataWidth:0x10 // Number to VCO clock to delay Channel 3 Global register. Reset on POR reset. -#define IPC_REG_MDIO_MODE_BB 0x020494UL //Access:RW DataWidth:0x16 // [21:12] -> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency equal to CORE_CLK/(2*(CLOCK_CNT+1)). A value of 0 is invalid for this register. [11] -> MDC Setting this bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low will cause the MDC pin to drive low if the BIT_BANG bit is set. [10] -> MDIO_OE Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if the BIT_BANG bit is set. Setting this bit to zero will make the MDIO pin an input. [9] -> MDIO The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set. The read value of this bit always reflects the state of the MDIO pin. [8] -> BIT_BANG If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bits in this register. When this bit is '0', the commands in the mdio_cmd register will be executed. [0] -> FREE_DIS 1 -> Diable Free running MDIO clock All other field in the register are reserved -#define IPC_REG_MDIO_MODE_K2_E5 0x020284UL //Access:RW DataWidth:0x16 // [21:12] -> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency equal to CORE_CLK/(2*(CLOCK_CNT+1)). A value of 0 is invalid for this register. [11] -> MDC Setting this bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low will cause the MDC pin to drive low if the BIT_BANG bit is set. [10] -> MDIO_OE Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if the BIT_BANG bit is set. Setting this bit to zero will make the MDIO pin an input. [9] -> MDIO The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set. The read value of this bit always reflects the state of the MDIO pin. [8] -> BIT_BANG If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bits in this register. When this bit is '0', the commands in the mdio_cmd register will be executed. [7:4] RESERVED [3] -> CLAUSE_45/CLAUSE_22 1 -> clause 45 mode 0 -> clause 22 mode [2] -> AUTO_POLL(not verified feature) Setting this bit to 1 will enable the auto poll mode which will constantly read from a specified register address 1. clause 22 the register address is always 1 and the phy addr is programable. Clause 45 the register address is always 1 and the deivce type and phy_addr are configurable [1] -> SHORT_PREAMBLE(not verified feature) setting this bit will cancell the preamble frame of 32 consecutive 1s [0] -> FREE_DIS(not verified feature) 1 -> Disable Free running MDIO clock +#define IPC_REG_PLL_MISC_POSTDIV_E5 0x020284UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): refer to postdiv setting table for division settings #define IPC_REG_PLL_MAIN_E28_CH4_MDEL_BB 0x020284UL //Access:RW DataWidth:0x10 // Number to VCO clock to delay Channel 4 Global register. Reset on POR reset. -#define IPC_REG_MDIO_COMM_BB 0x02048cUL //Access:RW DataWidth:0x1e // [29] -> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activate. When the operation is complete, this bit will clear and the MI_COMPLETE bit will be set in the status register. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting to prevent un-predictable results. [28] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. [27:26] -> COMMAND 1 -> Write 2 -> Read [25:21] -> PHY_ADDR This value is used to define the PHY address portion of the MDIO transaction 1 -> SWREG VMGMT 2 -> SWREG VMAIN 3 -> SWREG VANALOG 4 -> SWREG V1p8 [20:16] -> REG_ADDR This value is used to define the register address portion of the MDIO transaction [15:0] -> DATA When this register is read, it returns the results of the last MDIO transaction that was performed. When this register value is written, it updates the value that will be used on the next MDIO write transaction that will be performed. -#define IPC_REG_MDIO_COMM_K2_E5 0x020288UL //Access:RW DataWidth:0x1e // [29] -> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activate. When the operation is complete, this bit will clear and the MI_COMPLETE bit will be set in the status register. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting to prevent un-predictable results. [28] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. [27:26] -> COMMAND 00 -> clause 45 address 01 -> Write 10 -> clause 22 Read, clause 45 read_inc 11 -> clause 45 Read [25:21] -> PHY_ADDR This value is used to define the PHY address portion of the MDIO transaction. [20:16] -> REG_ADDR clause 22 - This value is used to define the register address portion of the MDIO transaction. clause 45 - This value is used to define the device type portion of the MDIO transaction. [15:0] -> DATA Clause 22: When this register is read, it returns the results of the last MDIO transaction that was performed. When this register value is written, it updates the value that will be used on the next MDIO write transaction that will be performed. Clause 45: for the first frame, this register contain the adsress of the command. for the second frame, it returns the results of the last MDIO transaction that was performed for read operation or the data to be written for write operation. +#define IPC_REG_PLL_MISC_PREDIV_E5 0x020288UL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3): refer to prediv setting table for division settings #define IPC_REG_PLL_MAIN_E28_CH5_MDEL_BB 0x020288UL //Access:RW DataWidth:0x10 // Number to VCO clock to delay Channel 5 Global register. Reset on POR reset. -#define IPC_REG_MDIO_STATUS_BB 0x020490UL //Access:R DataWidth:0x2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the next transaction starts. [1] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. -#define IPC_REG_MDIO_STATUS_K2_E5 0x02028cUL //Access:R DataWidth:0x2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the next transaction starts. [1] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. +#define IPC_REG_PLL_MISC_REP_E5 0x02028cUL //Access:RW DataWidth:0x1 // regamp internal setting (default 0) #define IPC_REG_PLL_MAIN_E28_CH_DELAY_DONE_BB 0x02028cUL //Access:R DataWidth:0x4 // Delay for each channel 2-5 is completed. -#define IPC_REG_SGMII_MDIO_ADDR_K2_E5 0x020290UL //Access:RW DataWidth:0x5 // PHY Address for MDIO Transaction +#define IPC_REG_PLL_MISC_RESET_E5 0x020290UL //Access:RW DataWidth:0x5 // Multi Field Register. + #define IPC_REG_PLL_MISC_RESET_PLL_MISC_RESET_E5 (0x1<<0) // 0: pll reset disabled 1: pll reset enabled + #define IPC_REG_PLL_MISC_RESET_PLL_MISC_RESET_E5_SHIFT 0 + #define IPC_REG_PLL_MISC_RESET_OVERRIDE_E5 (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register. + #define IPC_REG_PLL_MISC_RESET_OVERRIDE_E5_SHIFT 4 #define IPC_REG_PLL_MAIN_E28_CH_ENABLEB_BB 0x020290UL //Access:RW DataWidth:0x6 // Active Low Channel Enable. Global register. Reset on POR reset. -#define IPC_REG_SGMII_RSTB_MDIOREGS_K2_E5 0x020294UL //Access:RW DataWidth:0x1 // reset of sgmii mdio registers. This is an active high reset. The name "rstb" is mistakenly suggest an active low reset. +#define IPC_REG_PLL_MISC_LOGIC_RESET_E5 0x020294UL //Access:RW DataWidth:0x5 // Multi Field Register. + #define IPC_REG_PLL_MISC_LOGIC_RESET_PLL_MISC_LOGIC_RESET_E5 (0x1<<0) // 0: post scaler reset disabled 1: post scaler reset enabled + #define IPC_REG_PLL_MISC_LOGIC_RESET_PLL_MISC_LOGIC_RESET_E5_SHIFT 0 + #define IPC_REG_PLL_MISC_LOGIC_RESET_OVERRIDE_E5 (0x1<<4) // 1 : Override the init state machine and control the PLL logic reset using bit[0] of the register. + #define IPC_REG_PLL_MISC_LOGIC_RESET_OVERRIDE_E5_SHIFT 4 #define IPC_REG_PLL_MAIN_E28_CTRL_0_BB 0x020294UL //Access:RW DataWidth:0x20 // PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved -#define IPC_REG_FREQ_CAPTURE_BB 0x0204a4UL //Access:W DataWidth:0x1 // Setting this bit high will result in the HW to capture the frequency of Main, STORM and NW clocks. This is a self clearing bit. -#define IPC_REG_FREQ_CAPTURE_K2_E5 0x020298UL //Access:W DataWidth:0x1 // Setting this bit high will result in the HW to capture the frequency of Main, STORM and NWM clocks. This is a self clearing bit. +#define IPC_REG_PLL_STORM_BYPASS_K2 0x02026cUL //Access:RW DataWidth:0x1 // pll bypass signal +#define IPC_REG_PLL_STORM_BYPASS_E5 0x020298UL //Access:RW DataWidth:0x1 // 0: output clock comes from core_pll (default) 1: output clock is buffered bypass clock; overrides pll_ref_sel #define IPC_REG_PLL_MAIN_E28_CTRL_1_BB 0x020298UL //Access:RW DataWidth:0x20 // PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved +#define IPC_REG_PLL_STORM_BYPASS_PDB_E5 0x02029cUL //Access:RW DataWidth:0x1 // 0: bypass clock level converter power down (default) 1: bypass clock level converter power on +#define IPC_REG_PLL_MAIN_E28_KA_BB 0x02029cUL //Access:RW DataWidth:0x3 // Loop gain in frequency acquisition mode Global register. Reset on POR reset. +#define IPC_REG_PLL_STORM_CPB_E5 0x0202a0UL //Access:RW DataWidth:0x4 // charge pump current setting for Cb (default 0000) +#define IPC_REG_PLL_MAIN_E28_KI_BB 0x0202a0UL //Access:RW DataWidth:0x3 // Gain of P/I loop filter integrator path during fine phase acquisition mode Global register. Reset on POR reset. +#define IPC_REG_PLL_STORM_CPS_E5 0x0202a4UL //Access:RW DataWidth:0x4 // charge pump current setting for Cs (default 0000) +#define IPC_REG_PLL_MAIN_E28_KP_BB 0x0202a4UL //Access:RW DataWidth:0x4 // Gain of P/I loop filter proportional path during fine phase acquisition mode. SW needs to use the following transformation to program this register. For 0, Write 0 For 1, Write 1 For 2, Write 4 For 3, Write 5 For 4, Write 2 For 5, Write 3 For 6, Write 6 For 7, Write 7 For 8, Write 8 For 9, Write 9 For 10, Write 12 For 11, Write 13 For 12, Write 10 For 13, Write 11 For 14, Write 14 For 15, Write 15 A default of 5 implies that the PLL sees a value of 3. Global register. Reset on POR reset. +#define IPC_REG_PLL_STORM_DIFFAMP_E5 0x0202a8UL //Access:RW DataWidth:0x4 // diffamp bias current setting (default 0000) +#define IPC_REG_PLL_MAIN_E28_LOCK_BB 0x0202a8UL //Access:R DataWidth:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset. +#define IPC_REG_PLL_STORM_BG_CLK_EN_E5 0x0202acUL //Access:RW DataWidth:0x1 // 0: bandgap gap chopping disabled (default) 1: bandgap gap chopping enabled +#define IPC_REG_PLL_MAIN_E28_STATUS_BB 0x0202acUL //Access:R DataWidth:0xc // Status Bits from the PLL Global register. Reset on POR reset. +#define IPC_REG_PLL_STORM_BG_DIV16_EN_E5 0x0202b0UL //Access:RW DataWidth:0x1 // 0: bandgap clock freq = ref clock freq/4 (default) 1: bandgap clock freq = ref clock freq/16 +#define IPC_REG_PLL_NW_E28_PWRDN_BB 0x0202b0UL //Access:RW DataWidth:0x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR +#define IPC_REG_PLL_STORM_CLKF_E5 0x0202b4UL //Access:RW DataWidth:0x9 // pll feedback divider (8-511): refer to clkf setting table for division settings +#define IPC_REG_PLL_NW_E28_RESET_VCO_BB 0x0202b4UL //Access:RW DataWidth:0x1 // Resets the VCO logic in the PLL. The reset is Active High +#define IPC_REG_PLL_STORM_CPAMP_E5 0x0202b8UL //Access:RW DataWidth:0x1 // charge pump internal opamp setting (default 0) +#define IPC_REG_PLL_NW_E28_RESET_POST_BB 0x0202b8UL //Access:RW DataWidth:0x1 // Resets the Post Divider logic in the PLL. The reset is Active High +#define IPC_REG_PLL_STORM_DIV1_E5 0x0202bcUL //Access:RW DataWidth:0x1 // 0: divide core_pll clock by 2/4/8/16 according to postdiv setting (default) 1: no division on the core_pll clock (no 50% duty cycle) +#define IPC_REG_PLL_NW_E28_PDIV_BB 0x0202bcUL //Access:RW DataWidth:0x4 // Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset. +#define IPC_REG_PLL_STORM_REF_BYPASS_E5 0x0202c0UL //Access:RW DataWidth:0x1 // 0: ref clock not from the bypass path (default) 1: ref clock from the bypass path +#define IPC_REG_PLL_NW_E28_NDIV_INT_BB 0x0202c0UL //Access:RW DataWidth:0xa // Feedback divider control 0000000000= divide-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= divide-by-13 0000001110= divide-by-14 : 1111111110= divide-by-1022 1111111111= divide-by-1023 Global register. Reset on POR reset. +#define IPC_REG_PLL_STORM_REF_HCSL_E5 0x0202c4UL //Access:RW DataWidth:0x1 // 0: disable HCSL ref clock termination (default) 1: enable HCSL ref clock termination when pll_ref_oct is set to 1 +#define IPC_REG_PLL_NW_E28_NDIV_FRAC_BB 0x0202c4UL //Access:RW DataWidth:0x14 // Fractional feedback divider control. Resolution= 1/(2^20). Global register. Reset on POR reset. +#define IPC_REG_PLL_STORM_REF_OCT_E5 0x0202c8UL //Access:RW DataWidth:0x1 // 0: disable 50 Ohm on chip termination (default) 1: enable 50 Ohm on chip termination +#define IPC_REG_PLL_NW_E28_CH0_MDIV_BB 0x0202c8UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset. +#define IPC_REG_PLL_STORM_PLL_PWDN_E5 0x0202ccUL //Access:RW DataWidth:0x1 // 0: power down disabled (default) 1: power down enabled +#define IPC_REG_PLL_NW_E28_CH1_MDIV_BB 0x0202ccUL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset. +#define IPC_REG_PLL_STORM_POSTDIV_E5 0x0202d0UL //Access:RW DataWidth:0x2 // post-scaler(2/4/8/16): refer to postdiv setting table for division settings +#define IPC_REG_PLL_NW_E28_CH_ENABLEB_BB 0x0202d0UL //Access:RW DataWidth:0x6 // Active Low Channel Enable. Global register. Reset on POR reset. +#define IPC_REG_PLL_STORM_PREDIV_E5 0x0202d4UL //Access:RW DataWidth:0x2 // ref-clock divider (1/2/3): refer to prediv setting table for division settings +#define IPC_REG_PLL_NW_E28_CTRL_0_BB 0x0202d4UL //Access:RW DataWidth:0x20 // PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved +#define IPC_REG_PLL_STORM_REP_E5 0x0202d8UL //Access:RW DataWidth:0x1 // regamp internal setting (default 0) +#define IPC_REG_PLL_NW_E28_CTRL_1_BB 0x0202d8UL //Access:RW DataWidth:0x20 // PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved +#define IPC_REG_PLL_STORM_RESET_K2 0x020268UL //Access:RW DataWidth:0x1 // pll reset signal +#define IPC_REG_PLL_STORM_RESET_E5 0x0202dcUL //Access:RW DataWidth:0x1 // 0: pll reset disabled 1: pll reset enabled +#define IPC_REG_PLL_NW_E28_KA_BB 0x0202dcUL //Access:RW DataWidth:0x3 // Loop gain in frequency acquisition mode Global register. Reset on POR reset. +#define IPC_REG_PLL_STORM_LOGIC_RESET_E5 0x0202e0UL //Access:RW DataWidth:0x1 // 0: post scaler reset disabled 1: post scaler reset enabled +#define IPC_REG_PLL_NW_E28_KI_BB 0x0202e0UL //Access:RW DataWidth:0x3 // Gain of P/I loop filter integrator path during fine phase acquisition mode Global register. Reset on POR reset. +#define IPC_REG_MDIO_MODE_BB 0x020494UL //Access:RW DataWidth:0x16 // [21:12] -> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency equal to CORE_CLK/(2*(CLOCK_CNT+1)). A value of 0 is invalid for this register. [11] -> MDC Setting this bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low will cause the MDC pin to drive low if the BIT_BANG bit is set. [10] -> MDIO_OE Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if the BIT_BANG bit is set. Setting this bit to zero will make the MDIO pin an input. [9] -> MDIO The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set. The read value of this bit always reflects the state of the MDIO pin. [8] -> BIT_BANG If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bits in this register. When this bit is '0', the commands in the mdio_cmd register will be executed. [0] -> FREE_DIS 1 -> Diable Free running MDIO clock All other field in the register are reserved +#define IPC_REG_MDIO_MODE_K2 0x020284UL //Access:RW DataWidth:0x16 // [21:12] -> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency equal to CORE_CLK/(2*(CLOCK_CNT+1)). A value of 0 is invalid for this register. [11] -> MDC Setting this bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low will cause the MDC pin to drive low if the BIT_BANG bit is set. [10] -> MDIO_OE Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if the BIT_BANG bit is set. Setting this bit to zero will make the MDIO pin an input. [9] -> MDIO The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set. The read value of this bit always reflects the state of the MDIO pin. [8] -> BIT_BANG If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bits in this register. When this bit is '0', the commands in the mdio_cmd register will be executed. [7:4] RESERVED [3] -> CLAUSE_45/CLAUSE_22 1 -> clause 45 mode 0 -> clause 22 mode [2] -> AUTO_POLL(not verified feature) Setting this bit to 1 will enable the auto poll mode which will constantly read from a specified register address 1. clause 22 the register address is always 1 and the phy addr is programable. Clause 45 the register address is always 1 and the deivce type and phy_addr are configurable [1] -> SHORT_PREAMBLE(not verified feature) setting this bit will cancell the preamble frame of 32 consecutive 1s [0] -> FREE_DIS(not verified feature) 1 -> Disable Free running MDIO clock +#define IPC_REG_MDIO_MODE_E5 0x0202e4UL //Access:RW DataWidth:0x16 // [21:12] -> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency equal to CORE_CLK/(2*(CLOCK_CNT+1)). A value of 0 is invalid for this register. [11] -> MDC Setting this bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low will cause the MDC pin to drive low if the BIT_BANG bit is set. [10] -> MDIO_OE Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if the BIT_BANG bit is set. Setting this bit to zero will make the MDIO pin an input. [9] -> MDIO The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set. The read value of this bit always reflects the state of the MDIO pin. [8] -> BIT_BANG If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bits in this register. When this bit is '0', the commands in the mdio_cmd register will be executed. [7:4] RESERVED [3] -> CLAUSE_45/CLAUSE_22 1 -> clause 45 mode 0 -> clause 22 mode [2] -> AUTO_POLL(not verified feature) Setting this bit to 1 will enable the auto poll mode which will constantly read from a specified register address 1. clause 22 the register address is always 1 and the phy addr is programable. Clause 45 the register address is always 1 and the deivce type and phy_addr are configurable [1] -> SHORT_PREAMBLE(not verified feature) setting this bit will cancell the preamble frame of 32 consecutive 1s [0] -> FREE_DIS(not verified feature) 1 -> Disable Free running MDIO clock +#define IPC_REG_PLL_NW_E28_KP_BB 0x0202e4UL //Access:RW DataWidth:0x4 // Gain of P/I loop filter proportional path during fine phase acquisition mode. SW needs to use the following transformation to program this register. For 0, Write 0 For 1, Write 1 For 2, Write 4 For 3, Write 5 For 4, Write 2 For 5, Write 3 For 6, Write 6 For 7, Write 7 For 8, Write 8 For 9, Write 9 For 10, Write 12 For 11, Write 13 For 12, Write 10 For 13, Write 11 For 14, Write 14 For 15, Write 15 A default of 5 implies that the PLL sees a value of 3. Global register. Reset on POR reset. +#define IPC_REG_MDIO_COMM_BB 0x02048cUL //Access:RW DataWidth:0x1e // [29] -> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activate. When the operation is complete, this bit will clear and the MI_COMPLETE bit will be set in the status register. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting to prevent un-predictable results. [28] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. [27:26] -> COMMAND 1 -> Write 2 -> Read [25:21] -> PHY_ADDR This value is used to define the PHY address portion of the MDIO transaction 1 -> SWREG VMGMT 2 -> SWREG VMAIN 3 -> SWREG VANALOG 4 -> SWREG V1p8 [20:16] -> REG_ADDR This value is used to define the register address portion of the MDIO transaction [15:0] -> DATA When this register is read, it returns the results of the last MDIO transaction that was performed. When this register value is written, it updates the value that will be used on the next MDIO write transaction that will be performed. +#define IPC_REG_MDIO_COMM_K2 0x020288UL //Access:RW DataWidth:0x1e // [29] -> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activate. When the operation is complete, this bit will clear and the MI_COMPLETE bit will be set in the status register. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting to prevent un-predictable results. [28] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. [27:26] -> COMMAND 00 -> clause 45 address 01 -> Write 10 -> clause 22 Read, clause 45 read_inc 11 -> clause 45 Read [25:21] -> PHY_ADDR This value is used to define the PHY address portion of the MDIO transaction. [20:16] -> REG_ADDR clause 22 - This value is used to define the register address portion of the MDIO transaction. clause 45 - This value is used to define the device type portion of the MDIO transaction. [15:0] -> DATA Clause 22: When this register is read, it returns the results of the last MDIO transaction that was performed. When this register value is written, it updates the value that will be used on the next MDIO write transaction that will be performed. Clause 45: for the first frame, this register contain the adsress of the command. for the second frame, it returns the results of the last MDIO transaction that was performed for read operation or the data to be written for write operation. +#define IPC_REG_MDIO_COMM_E5 0x0202e8UL //Access:RW DataWidth:0x1e // [29] -> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activate. When the operation is complete, this bit will clear and the MI_COMPLETE bit will be set in the status register. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting to prevent un-predictable results. [28] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. [27:26] -> COMMAND 00 -> clause 45 address 01 -> Write 10 -> clause 22 Read, clause 45 read_inc 11 -> clause 45 Read [25:21] -> PHY_ADDR This value is used to define the PHY address portion of the MDIO transaction. [20:16] -> REG_ADDR clause 22 - This value is used to define the register address portion of the MDIO transaction. clause 45 - This value is used to define the device type portion of the MDIO transaction. [15:0] -> DATA Clause 22: When this register is read, it returns the results of the last MDIO transaction that was performed. When this register value is written, it updates the value that will be used on the next MDIO write transaction that will be performed. Clause 45: for the first frame, this register contain the adsress of the command. for the second frame, it returns the results of the last MDIO transaction that was performed for read operation or the data to be written for write operation. +#define IPC_REG_PLL_NW_E28_LOCK_BB 0x0202e8UL //Access:R DataWidth:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset. +#define IPC_REG_MDIO_STATUS_BB 0x020490UL //Access:R DataWidth:0x2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the next transaction starts. [1] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. +#define IPC_REG_MDIO_STATUS_K2 0x02028cUL //Access:R DataWidth:0x2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the next transaction starts. [1] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. +#define IPC_REG_MDIO_STATUS_E5 0x0202ecUL //Access:R DataWidth:0x2 // [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the next transaction starts. [1] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. +#define IPC_REG_PLL_NW_E28_STATUS_BB 0x0202ecUL //Access:R DataWidth:0xc // Status Bits from the PLL Global register. Reset on POR reset. +#define IPC_REG_SGMII_MDIO_ADDR_K2 0x020290UL //Access:RW DataWidth:0x5 // PHY Address for MDIO Transaction +#define IPC_REG_SGMII_MDIO_ADDR_E5 0x0202f0UL //Access:RW DataWidth:0x5 // PHY Address for MDIO Transaction +#define IPC_REG_PLL_STORM_E28_PWRDN_BB 0x0202f0UL //Access:RW DataWidth:0x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR +#define IPC_REG_SGMII_RSTB_MDIOREGS_K2 0x020294UL //Access:RW DataWidth:0x1 // reset of sgmii mdio registers. This is an active high reset. The name "rstb" is mistakenly suggest an active low reset. +#define IPC_REG_SGMII_RSTB_MDIOREGS_E5 0x0202f4UL //Access:RW DataWidth:0x1 // reset of sgmii mdio registers. This is an active high reset. The name "rstb" is mistakenly suggest an active low reset. +#define IPC_REG_PLL_STORM_E28_RESET_VCO_BB 0x0202f4UL //Access:RW DataWidth:0x1 // Resets the VCO logic in the PLL. The reset is Active High +#define IPC_REG_FREQ_CAPTURE_BB 0x0204a4UL //Access:W DataWidth:0x1 // Setting this bit high will result in the HW to capture the frequency of Main, STORM and NW clocks. This is a self clearing bit. +#define IPC_REG_FREQ_CAPTURE_K2 0x020298UL //Access:W DataWidth:0x1 // Setting this bit high will result in the HW to capture the frequency of Main, STORM and NWM clocks. This is a self clearing bit. +#define IPC_REG_FREQ_CAPTURE_E5 0x0202f8UL //Access:W DataWidth:0x1 // Setting this bit high will result in the HW to capture the frequency of Main, STORM and NWM clocks. This is a self clearing bit. +#define IPC_REG_PLL_STORM_E28_RESET_POST_BB 0x0202f8UL //Access:RW DataWidth:0x1 // Resets the Post Divider logic in the PLL. The reset is Active High #define IPC_REG_FREQ_MAIN_BB 0x0204a8UL //Access:R DataWidth:0x11 // Multi Field Register. -#define IPC_REG_FREQ_MAIN_K2_E5 0x02029cUL //Access:R DataWidth:0x11 // Multi Field Register. +#define IPC_REG_FREQ_MAIN_K2 0x02029cUL //Access:R DataWidth:0x11 // Multi Field Register. +#define IPC_REG_FREQ_MAIN_E5 0x0202fcUL //Access:R DataWidth:0x11 // Multi Field Register. #define IPC_REG_FREQ_MAIN_CNT (0xffff<<0) // This field shows the frequency counter for main clock over a 10uS interval. Main Clock Frequency = ~(FreqCnt / 10)MHz. This field is not reset between measurements. For example, it shows X MHz in first measurement, 2*X in second measurement, 3*X MHz in third measurement. #define IPC_REG_FREQ_MAIN_CNT_SHIFT 0 #define IPC_REG_FREQ_MAIN_CNT_VALID (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt field is valid #define IPC_REG_FREQ_MAIN_CNT_VALID_SHIFT 16 -#define IPC_REG_PLL_MAIN_E28_KA_BB 0x02029cUL //Access:RW DataWidth:0x3 // Loop gain in frequency acquisition mode Global register. Reset on POR reset. +#define IPC_REG_PLL_STORM_E28_PDIV_BB 0x0202fcUL //Access:RW DataWidth:0x4 // Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset. #define IPC_REG_FREQ_STORM_BB 0x0204acUL //Access:R DataWidth:0x11 // Multi Field Register. -#define IPC_REG_FREQ_STORM_K2_E5 0x0202a0UL //Access:R DataWidth:0x11 // Multi Field Register. +#define IPC_REG_FREQ_STORM_K2 0x0202a0UL //Access:R DataWidth:0x11 // Multi Field Register. +#define IPC_REG_FREQ_STORM_E5 0x020300UL //Access:R DataWidth:0x11 // Multi Field Register. #define IPC_REG_FREQ_STORM_CNT (0xffff<<0) // This field shows the frequency counter for main clock over a 10uS interval. Storm Clock Frequency = ~(FreqCnt / 10)MHz. This field is not reset between measurements. For example, it shows X MHz in first measurement, 2*X in second measurement, 3*X MHz in third measurement. #define IPC_REG_FREQ_STORM_CNT_SHIFT 0 #define IPC_REG_FREQ_STORM_CNT_VALID (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt field is valid #define IPC_REG_FREQ_STORM_CNT_VALID_SHIFT 16 -#define IPC_REG_PLL_MAIN_E28_KI_BB 0x0202a0UL //Access:RW DataWidth:0x3 // Gain of P/I loop filter integrator path during fine phase acquisition mode Global register. Reset on POR reset. -#define IPC_REG_FREQ_NWM_K2_E5 0x0202a4UL //Access:R DataWidth:0x11 // Multi Field Register. +#define IPC_REG_PLL_STORM_E28_NDIV_INT_BB 0x020300UL //Access:RW DataWidth:0xa // Feedback divider control 0000000000 = not usable 0000000001 = not usable ... 0000001111 = not usable 0000010000 = 16 ... 1111111111 = 1023 Global register. Reset on POR reset. +#define IPC_REG_FREQ_NWM_K2 0x0202a4UL //Access:R DataWidth:0x11 // Multi Field Register. +#define IPC_REG_FREQ_NWM_E5 0x020304UL //Access:R DataWidth:0x11 // Multi Field Register. #define IPC_REG_FREQ_NWM_CNT_K2_E5 (0xffff<<0) // This field shows the frequency counter for main clock over a 10uS interval. NW Clock Frequency = ~(FreqCnt / 10)MHz. This field is not reset between measurements. For example, it shows X MHz in first measurement, 2*X in second measurement, 3*X MHz in third measurement. #define IPC_REG_FREQ_NWM_CNT_K2_E5_SHIFT 0 #define IPC_REG_FREQ_NWM_CNT_VALID_K2_E5 (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt field is valid #define IPC_REG_FREQ_NWM_CNT_VALID_K2_E5_SHIFT 16 -#define IPC_REG_PLL_MAIN_E28_KP_BB 0x0202a4UL //Access:RW DataWidth:0x4 // Gain of P/I loop filter proportional path during fine phase acquisition mode. SW needs to use the following transformation to program this register. For 0, Write 0 For 1, Write 1 For 2, Write 4 For 3, Write 5 For 4, Write 2 For 5, Write 3 For 6, Write 6 For 7, Write 7 For 8, Write 8 For 9, Write 9 For 10, Write 12 For 11, Write 13 For 12, Write 10 For 13, Write 11 For 14, Write 14 For 15, Write 15 A default of 5 implies that the PLL sees a value of 3. Global register. Reset on POR reset. +#define IPC_REG_PLL_STORM_E28_CH0_MDIV_BB 0x020304UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset. #define IPC_REG_FREE_RUNNING_CNTR_0_BB 0x0204b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 1us resolution. -#define IPC_REG_FREE_RUNNING_CNTR_0_K2_E5 0x0202a8UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 1us resolution. -#define IPC_REG_PLL_MAIN_E28_LOCK_BB 0x0202a8UL //Access:R DataWidth:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset. +#define IPC_REG_FREE_RUNNING_CNTR_0_K2 0x0202a8UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 1us resolution. +#define IPC_REG_FREE_RUNNING_CNTR_0_E5 0x020308UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 1us resolution. +#define IPC_REG_PLL_STORM_E28_CH1_MDIV_BB 0x020308UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset. #define IPC_REG_FREE_RUNNING_CNTR_1_BB 0x0204b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 16us resolution. -#define IPC_REG_FREE_RUNNING_CNTR_1_K2_E5 0x0202acUL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 16us resolution. -#define IPC_REG_PLL_MAIN_E28_STATUS_BB 0x0202acUL //Access:R DataWidth:0xc // Status Bits from the PLL Global register. Reset on POR reset. +#define IPC_REG_FREE_RUNNING_CNTR_1_K2 0x0202acUL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 16us resolution. +#define IPC_REG_FREE_RUNNING_CNTR_1_E5 0x02030cUL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 16us resolution. +#define IPC_REG_PLL_STORM_E28_CH_ENABLEB_BB 0x02030cUL //Access:RW DataWidth:0x6 // Active Low Channel Enable. Global register. Reset on POR reset. #define IPC_REG_FREE_RUNNING_CNTR_2_BB 0x0204bcUL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 256us resolution. -#define IPC_REG_FREE_RUNNING_CNTR_2_K2_E5 0x0202b0UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 256us resolution. -#define IPC_REG_PLL_NW_E28_PWRDN_BB 0x0202b0UL //Access:RW DataWidth:0x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR +#define IPC_REG_FREE_RUNNING_CNTR_2_K2 0x0202b0UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 256us resolution. +#define IPC_REG_FREE_RUNNING_CNTR_2_E5 0x020310UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 256us resolution. +#define IPC_REG_PLL_STORM_E28_CTRL_0_BB 0x020310UL //Access:RW DataWidth:0x20 // PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset. #define IPC_REG_FREE_RUNNING_CNTR_3_BB 0x0204c0UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 4096us resolution. -#define IPC_REG_FREE_RUNNING_CNTR_3_K2_E5 0x0202b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 4096us resolution. -#define IPC_REG_PLL_NW_E28_RESET_VCO_BB 0x0202b4UL //Access:RW DataWidth:0x1 // Resets the VCO logic in the PLL. The reset is Active High +#define IPC_REG_FREE_RUNNING_CNTR_3_K2 0x0202b4UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 4096us resolution. +#define IPC_REG_FREE_RUNNING_CNTR_3_E5 0x020314UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 4096us resolution. +#define IPC_REG_PLL_STORM_E28_CTRL_1_BB 0x020314UL //Access:RW DataWidth:0x20 // PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset. #define IPC_REG_FREE_RUNNING_CNTR_4_BB 0x0204c4UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 65536us resolution. -#define IPC_REG_FREE_RUNNING_CNTR_4_K2_E5 0x0202b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 65536us resolution. -#define IPC_REG_PLL_NW_E28_RESET_POST_BB 0x0202b8UL //Access:RW DataWidth:0x1 // Resets the Post Divider logic in the PLL. The reset is Active High +#define IPC_REG_FREE_RUNNING_CNTR_4_K2 0x0202b8UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 65536us resolution. +#define IPC_REG_FREE_RUNNING_CNTR_4_E5 0x020318UL //Access:R DataWidth:0x20 // This is a 32-bit free running counter that has 65536us resolution. +#define IPC_REG_PLL_STORM_E28_CTRL_2_BB 0x020318UL //Access:RW DataWidth:0x2 // PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset. #define IPC_REG_VMAIN_POR_STATUS_BB 0x0204c8UL //Access:R DataWidth:0x1 // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up -#define IPC_REG_VMAIN_POR_STATUS_K2_E5 0x0202bcUL //Access:R DataWidth:0x1 // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up -#define IPC_REG_PLL_NW_E28_PDIV_BB 0x0202bcUL //Access:RW DataWidth:0x4 // Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset. +#define IPC_REG_VMAIN_POR_STATUS_K2 0x0202bcUL //Access:R DataWidth:0x1 // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up +#define IPC_REG_VMAIN_POR_STATUS_E5 0x02031cUL //Access:R DataWidth:0x1 // This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up +#define IPC_REG_PLL_STORM_E28_KI_BB 0x02031cUL //Access:RW DataWidth:0x3 // Integrator gain control of the PLL digital filter. Global register. Reset on POR reset. #define IPC_REG_STAT_VMAIN_POR_ASSERTION_BB 0x0204ccUL //Access:RC DataWidth:0x8 // This register provides the number of times VMAIN POR was asserted. This would be the count of number of times VMAIN went down. -#define IPC_REG_STAT_VMAIN_POR_ASSERTION_K2_E5 0x0202c0UL //Access:RC DataWidth:0x8 // This register provides the number of times VMAIN POR was asserted. This would be the count of number of times VMAIN went down. -#define IPC_REG_PLL_NW_E28_NDIV_INT_BB 0x0202c0UL //Access:RW DataWidth:0xa // Feedback divider control 0000000000= divide-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= divide-by-13 0000001110= divide-by-14 : 1111111110= divide-by-1022 1111111111= divide-by-1023 Global register. Reset on POR reset. +#define IPC_REG_STAT_VMAIN_POR_ASSERTION_K2 0x0202c0UL //Access:RC DataWidth:0x8 // This register provides the number of times VMAIN POR was asserted. This would be the count of number of times VMAIN went down. +#define IPC_REG_STAT_VMAIN_POR_ASSERTION_E5 0x020320UL //Access:RC DataWidth:0x8 // This register provides the number of times VMAIN POR was asserted. This would be the count of number of times VMAIN went down. +#define IPC_REG_PLL_STORM_E28_KP_BB 0x020320UL //Access:RW DataWidth:0x4 // Gain of P/I loop filter proportional path during fine phase acquisition mode. Global register. Reset on POR reset. #define IPC_REG_STAT_VMAIN_POR_DEASSERTION_BB 0x0204d0UL //Access:RC DataWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would be the count of number of times VMAIN came up. -#define IPC_REG_STAT_VMAIN_POR_DEASSERTION_K2_E5 0x0202c4UL //Access:RC DataWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would be the count of number of times VMAIN came up. -#define IPC_REG_PLL_NW_E28_NDIV_FRAC_BB 0x0202c4UL //Access:RW DataWidth:0x14 // Fractional feedback divider control. Resolution= 1/(2^20). Global register. Reset on POR reset. +#define IPC_REG_STAT_VMAIN_POR_DEASSERTION_K2 0x0202c4UL //Access:RC DataWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would be the count of number of times VMAIN came up. +#define IPC_REG_STAT_VMAIN_POR_DEASSERTION_E5 0x020324UL //Access:RC DataWidth:0x8 // This register provides the number of times VMAIN POR was de-asserted. This would be the count of number of times VMAIN came up. +#define IPC_REG_PLL_STORM_E28_KPP_BB 0x020324UL //Access:RW DataWidth:0x4 // Control of the non-zero pole in the PLL digital filter. Global register. Reset on POR reset. #define IPC_REG_PERST_POR_STATUS_BB 0x0204d4UL //Access:R DataWidth:0x1 // This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-asserted -#define IPC_REG_PERST_POR_STATUS_K2_E5 0x0202c8UL //Access:R DataWidth:0x1 // This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-asserted -#define IPC_REG_PLL_NW_E28_CH0_MDIV_BB 0x0202c8UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset. +#define IPC_REG_PERST_POR_STATUS_K2 0x0202c8UL //Access:R DataWidth:0x1 // This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-asserted +#define IPC_REG_PERST_POR_STATUS_E5 0x020328UL //Access:R DataWidth:0x1 // This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-asserted +#define IPC_REG_PLL_STORM_E28_LOCK_BB 0x020328UL //Access:R DataWidth:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset. #define IPC_REG_STAT_PERST_ASSERTION_BB 0x0204d8UL //Access:RC DataWidth:0x8 // This register provides the number of times PERST# was asserted -#define IPC_REG_STAT_PERST_ASSERTION_K2_E5 0x0202ccUL //Access:RC DataWidth:0x8 // This register provides the number of times PERST# was asserted -#define IPC_REG_PLL_NW_E28_CH1_MDIV_BB 0x0202ccUL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset. +#define IPC_REG_STAT_PERST_ASSERTION_K2 0x0202ccUL //Access:RC DataWidth:0x8 // This register provides the number of times PERST# was asserted +#define IPC_REG_STAT_PERST_ASSERTION_E5 0x02032cUL //Access:RC DataWidth:0x8 // This register provides the number of times PERST# was asserted +#define IPC_REG_PLL_STORM_E28_STATUS_BB 0x02032cUL //Access:R DataWidth:0xc // Internal Status Bits of the PLL Global register. Reset on POR reset. #define IPC_REG_STAT_PERST_DEASSERTION_BB 0x0204dcUL //Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted -#define IPC_REG_STAT_PERST_DEASSERTION_K2_E5 0x0202d0UL //Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted -#define IPC_REG_PLL_NW_E28_CH_ENABLEB_BB 0x0202d0UL //Access:RW DataWidth:0x6 // Active Low Channel Enable. Global register. Reset on POR reset. +#define IPC_REG_STAT_PERST_DEASSERTION_K2 0x0202d0UL //Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted +#define IPC_REG_STAT_PERST_DEASSERTION_E5 0x020330UL //Access:RC DataWidth:0x8 // This register provides the number of times PERST# was de-asserted +#define IPC_REG_LCPLL_E28_PWRDN_BB 0x020330UL //Access:RW DataWidth:0x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR #define IPC_REG_CHIP_MODE_BB 0x0204e0UL //Access:R DataWidth:0x6 // This register shows the current status of the Mode Pins of the chip. 6'bXX0000 -> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone mode 6'bXX0100 -> MAC SERDES Standalone mode 6'bXX0101 -> IDDQ Mode 6'bXX0110 -> OVSTB Mode 6'bX1XXXX -> Run all the modes in Fast Reset (useful in Simulation/ATE) 6'b1XXXXX -> Run all the modes in POR Bypass mode -#define IPC_REG_CHIP_MODE_K2_E5 0x0202d4UL //Access:R DataWidth:0x6 // This register shows the current status of the Mode Pins of the chip. 6'bXX0000 -> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone mode 6'bXX0100 -> MAC SERDES Standalone mode 6'bXX0101 -> IDDQ Mode 6'bXX0110 -> OVSTB Mode 6'bX1XXXX -> Run all the modes in Fast Reset (useful in Simulation/ATE) 6'b1XXXXX -> Run all the modes in POR Bypass mode -#define IPC_REG_PLL_NW_E28_CTRL_0_BB 0x0202d4UL //Access:RW DataWidth:0x20 // PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved +#define IPC_REG_CHIP_MODE_K2 0x0202d4UL //Access:R DataWidth:0x6 // This register shows the current status of the Mode Pins of the chip. 6'bXX0000 -> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone mode 6'bXX0100 -> MAC SERDES Standalone mode 6'bXX0101 -> IDDQ Mode 6'bXX0110 -> OVSTB Mode 6'bX1XXXX -> Run all the modes in Fast Reset (useful in Simulation/ATE) 6'b1XXXXX -> Run all the modes in POR Bypass mode +#define IPC_REG_CHIP_MODE_E5 0x020334UL //Access:R DataWidth:0x6 // This register shows the current status of the Mode Pins of the chip. 6'bXX0000 -> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone mode 6'bXX0100 -> MAC SERDES Standalone mode 6'bXX0101 -> IDDQ Mode 6'bXX0110 -> OVSTB Mode 6'bX1XXXX -> Run all the modes in Fast Reset (useful in Simulation/ATE) 6'b1XXXXX -> Run all the modes in POR Bypass mode +#define IPC_REG_LCPLL_E28_RESET_VCO_BB 0x020334UL //Access:RW DataWidth:0x1 // Resets the VCO logic in the PLL. The reset is Active High #define IPC_REG_HW_STRAPS_BB 0x0204e4UL //Access:R DataWidth:0xc // Multi Field Register. -#define IPC_REG_HW_STRAPS_K2_E5 0x0202d8UL //Access:R DataWidth:0xc // Multi Field Register. +#define IPC_REG_HW_STRAPS_K2 0x0202d8UL //Access:R DataWidth:0xc // Multi Field Register. +#define IPC_REG_HW_STRAPS_E5 0x020338UL //Access:R DataWidth:0xc // Multi Field Register. #define IPC_REG_HW_STRAPS_TESTIN_STRAPS (0xff<<0) // Strap value on TEST IN pins #define IPC_REG_HW_STRAPS_TESTIN_STRAPS_SHIFT 0 #define IPC_REG_HW_STRAPS_FLASH_STRAPS (0xf<<8) // Strap value on FLASH pins #define IPC_REG_HW_STRAPS_FLASH_STRAPS_SHIFT 8 -#define IPC_REG_PLL_NW_E28_CTRL_1_BB 0x0202d8UL //Access:RW DataWidth:0x20 // PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved +#define IPC_REG_LCPLL_E28_RESET_POST_BB 0x020338UL //Access:RW DataWidth:0x1 // Resets the Post Divider logic in the PLL. The reset is Active High #define IPC_REG_INT_STS_0_BB 0x02050cUL //Access:R DataWidth:0x10 // Multi Field Register. -#define IPC_REG_INT_STS_0_K2_E5 0x0202dcUL //Access:R DataWidth:0x8 // Multi Field Register. +#define IPC_REG_INT_STS_0_K2 0x0202dcUL //Access:R DataWidth:0x8 // Multi Field Register. +#define IPC_REG_INT_STS_0_E5 0x02033cUL //Access:R DataWidth:0x8 // Multi Field Register. #define IPC_REG_INT_STS_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define IPC_REG_INT_STS_0_ADDRESS_ERROR_SHIFT 0 #define IPC_REG_INT_STS_0_VMAIN_POR_ASSERT (0x1<<4) // This bit generates an interrupt when VMAIN POR is asserted, ie VMAIN goes from high to low @@ -35152,9 +38173,10 @@ #define IPC_REG_INT_STS_0_OTP_ECC_DED_6_BB_SHIFT 14 #define IPC_REG_INT_STS_0_OTP_ECC_DED_7_BB (0x1<<15) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 0 is asserted. #define IPC_REG_INT_STS_0_OTP_ECC_DED_7_BB_SHIFT 15 -#define IPC_REG_PLL_NW_E28_KA_BB 0x0202dcUL //Access:RW DataWidth:0x3 // Loop gain in frequency acquisition mode Global register. Reset on POR reset. +#define IPC_REG_LCPLL_E28_PDIV_BB 0x02033cUL //Access:RW DataWidth:0x4 // Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset. #define IPC_REG_INT_MASK_0_BB 0x020510UL //Access:RW DataWidth:0x10 // Multi Field Register. -#define IPC_REG_INT_MASK_0_K2_E5 0x0202e0UL //Access:RW DataWidth:0x8 // Multi Field Register. +#define IPC_REG_INT_MASK_0_K2 0x0202e0UL //Access:RW DataWidth:0x8 // Multi Field Register. +#define IPC_REG_INT_MASK_0_E5 0x020340UL //Access:RW DataWidth:0x8 // Multi Field Register. #define IPC_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.ADDRESS_ERROR . #define IPC_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT 0 #define IPC_REG_INT_MASK_0_VMAIN_POR_ASSERT (0x1<<4) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.VMAIN_POR_ASSERT . @@ -35181,9 +38203,10 @@ #define IPC_REG_INT_MASK_0_OTP_ECC_DED_6_BB_SHIFT 14 #define IPC_REG_INT_MASK_0_OTP_ECC_DED_7_BB (0x1<<15) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_7 . #define IPC_REG_INT_MASK_0_OTP_ECC_DED_7_BB_SHIFT 15 -#define IPC_REG_PLL_NW_E28_KI_BB 0x0202e0UL //Access:RW DataWidth:0x3 // Gain of P/I loop filter integrator path during fine phase acquisition mode Global register. Reset on POR reset. +#define IPC_REG_LCPLL_E28_NDIV_INT_BB 0x020340UL //Access:RW DataWidth:0xa // Feedback divider control 0000000000 = not usable 0000000001 = not usable ... 0000001111 = not usable 0000010000 = 16 ... 1111111111 = 1023 Global register. Reset on POR reset. #define IPC_REG_INT_STS_WR_0_BB 0x020514UL //Access:WR DataWidth:0x10 // Multi Field Register. -#define IPC_REG_INT_STS_WR_0_K2_E5 0x0202e4UL //Access:WR DataWidth:0x8 // Multi Field Register. +#define IPC_REG_INT_STS_WR_0_K2 0x0202e4UL //Access:WR DataWidth:0x8 // Multi Field Register. +#define IPC_REG_INT_STS_WR_0_E5 0x020344UL //Access:WR DataWidth:0x8 // Multi Field Register. #define IPC_REG_INT_STS_WR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define IPC_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT 0 #define IPC_REG_INT_STS_WR_0_VMAIN_POR_ASSERT (0x1<<4) // This bit generates an interrupt when VMAIN POR is asserted, ie VMAIN goes from high to low @@ -35210,9 +38233,10 @@ #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_6_BB_SHIFT 14 #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_7_BB (0x1<<15) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 0 is asserted. #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_7_BB_SHIFT 15 -#define IPC_REG_PLL_NW_E28_KP_BB 0x0202e4UL //Access:RW DataWidth:0x4 // Gain of P/I loop filter proportional path during fine phase acquisition mode. SW needs to use the following transformation to program this register. For 0, Write 0 For 1, Write 1 For 2, Write 4 For 3, Write 5 For 4, Write 2 For 5, Write 3 For 6, Write 6 For 7, Write 7 For 8, Write 8 For 9, Write 9 For 10, Write 12 For 11, Write 13 For 12, Write 10 For 13, Write 11 For 14, Write 14 For 15, Write 15 A default of 5 implies that the PLL sees a value of 3. Global register. Reset on POR reset. +#define IPC_REG_LCPLL_E28_CH0_MDIV_BB 0x020344UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset. #define IPC_REG_INT_STS_CLR_0_BB 0x020518UL //Access:RC DataWidth:0x10 // Multi Field Register. -#define IPC_REG_INT_STS_CLR_0_K2_E5 0x0202e8UL //Access:RC DataWidth:0x8 // Multi Field Register. +#define IPC_REG_INT_STS_CLR_0_K2 0x0202e8UL //Access:RC DataWidth:0x8 // Multi Field Register. +#define IPC_REG_INT_STS_CLR_0_E5 0x020348UL //Access:RC DataWidth:0x8 // Multi Field Register. #define IPC_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define IPC_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT 0 #define IPC_REG_INT_STS_CLR_0_VMAIN_POR_ASSERT (0x1<<4) // This bit generates an interrupt when VMAIN POR is asserted, ie VMAIN goes from high to low @@ -35239,105 +38263,116 @@ #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_6_BB_SHIFT 14 #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_7_BB (0x1<<15) // This bit generates an interrupt when Fdone Double Error Detection status flag for AUTOLOAD word 0 is asserted. #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_7_BB_SHIFT 15 -#define IPC_REG_PLL_NW_E28_LOCK_BB 0x0202e8UL //Access:R DataWidth:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset. +#define IPC_REG_LCPLL_E28_CH1_MDIV_BB 0x020348UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset. #define IPC_REG_JTAG_COMPLIANCE_BB 0x020508UL //Access:RW DataWidth:0x5 // Multi Field Register. -#define IPC_REG_JTAG_COMPLIANCE_K2_E5 0x0202ecUL //Access:RW DataWidth:0x5 // Multi Field Register. +#define IPC_REG_JTAG_COMPLIANCE_K2 0x0202ecUL //Access:RW DataWidth:0x5 // Multi Field Register. +#define IPC_REG_JTAG_COMPLIANCE_E5 0x02034cUL //Access:RW DataWidth:0x5 // Multi Field Register. #define IPC_REG_JTAG_COMPLIANCE_EN (0x3<<0) // These bits set the compliance enable for JTAG pins. the JTAG interface is shared by four masters and there is a dedicated 2-bit compliance enable pins on the ballout. These bits are used to override the pins if needed. 2'b00 --> LV JTAG is selected 2'b01 --> AVS JTAG is selected 2'b10 --> MCP EJTAG is selected 2'b11 --> AVS EJTAG is selected #define IPC_REG_JTAG_COMPLIANCE_EN_SHIFT 0 #define IPC_REG_JTAG_COMPLIANCE_OVERRIDE (0x1<<4) // Set this bit to override the pins on the chip with bits[1:0] #define IPC_REG_JTAG_COMPLIANCE_OVERRIDE_SHIFT 4 -#define IPC_REG_PLL_NW_E28_STATUS_BB 0x0202ecUL //Access:R DataWidth:0xc // Status Bits from the PLL Global register. Reset on POR reset. -#define IPC_REG_TCAM_BIST_REGISTER_OR_EXTERNAL_SELECT_K2_E5 0x0202f0UL //Access:RW DataWidth:0x1 // 0 - control of the tcam bist is from the IPC register tcam_bist_control and tcam_bist_num. 1 - control of the tcam bist is from the external pins. by default these pins are gurenteed to be zero so tcam bist will not start running. -#define IPC_REG_PLL_STORM_E28_PWRDN_BB 0x0202f0UL //Access:RW DataWidth:0x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR -#define IPC_REG_TCAM_BIST_NUM_K2_E5 0x0202f4UL //Access:RW DataWidth:0x5 // select the cam instance when reading the status of the cam in tcam_bist_status 0 ccfc_ccam 1 ccfc_scam 2 igu 3 msem 4 prs_gft 5 prs_h 6 prs_l 7 psem 8 psem_vfc 9 qm 10 tcfc_ccam 11 tsem 12 tsem_vfc 13 usem 14 xsem 15 ysem -#define IPC_REG_PLL_STORM_E28_RESET_VCO_BB 0x0202f4UL //Access:RW DataWidth:0x1 // Resets the VCO logic in the PLL. The reset is Active High -#define IPC_REG_TCAM_BIST_STATUS_K2_E5 0x0202f8UL //Access:R DataWidth:0x6 // tcam bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(bist_sho) bit 4 - reserved bit 5 - reserved -#define IPC_REG_PLL_STORM_E28_RESET_POST_BB 0x0202f8UL //Access:RW DataWidth:0x1 // Resets the Post Divider logic in the PLL. The reset is Active High -#define IPC_REG_TCAM_BIST_CONTROL_CCFC_CCAM_K2_E5 0x0202fcUL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved -#define IPC_REG_PLL_STORM_E28_PDIV_BB 0x0202fcUL //Access:RW DataWidth:0x4 // Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset. -#define IPC_REG_TCAM_BIST_CONTROL_CCFC_SCAM_K2_E5 0x020300UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved -#define IPC_REG_PLL_STORM_E28_NDIV_INT_BB 0x020300UL //Access:RW DataWidth:0xa // Feedback divider control 0000000000 = not usable 0000000001 = not usable ... 0000001111 = not usable 0000010000 = 16 ... 1111111111 = 1023 Global register. Reset on POR reset. -#define IPC_REG_TCAM_BIST_CONTROL_TCFC_CCAM_K2_E5 0x020304UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved -#define IPC_REG_PLL_STORM_E28_CH0_MDIV_BB 0x020304UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset. -#define IPC_REG_TCAM_BIST_CONTROL_QM_K2_E5 0x020308UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved -#define IPC_REG_PLL_STORM_E28_CH1_MDIV_BB 0x020308UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset. -#define IPC_REG_TCAM_BIST_CONTROL_XSEM_K2_E5 0x02030cUL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved -#define IPC_REG_PLL_STORM_E28_CH_ENABLEB_BB 0x02030cUL //Access:RW DataWidth:0x6 // Active Low Channel Enable. Global register. Reset on POR reset. -#define IPC_REG_TCAM_BIST_CONTROL_YSEM_K2_E5 0x020310UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved -#define IPC_REG_PLL_STORM_E28_CTRL_0_BB 0x020310UL //Access:RW DataWidth:0x20 // PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset. -#define IPC_REG_TCAM_BIST_CONTROL_PSEM_K2_E5 0x020314UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved -#define IPC_REG_PLL_STORM_E28_CTRL_1_BB 0x020314UL //Access:RW DataWidth:0x20 // PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset. -#define IPC_REG_TCAM_BIST_CONTROL_PSEM_VFC_K2_E5 0x020318UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved -#define IPC_REG_PLL_STORM_E28_CTRL_2_BB 0x020318UL //Access:RW DataWidth:0x2 // PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset. -#define IPC_REG_TCAM_BIST_CONTROL_USEM_K2_E5 0x02031cUL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved -#define IPC_REG_PLL_STORM_E28_KI_BB 0x02031cUL //Access:RW DataWidth:0x3 // Integrator gain control of the PLL digital filter. Global register. Reset on POR reset. -#define IPC_REG_TCAM_BIST_CONTROL_TSEM_K2_E5 0x020320UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved -#define IPC_REG_PLL_STORM_E28_KP_BB 0x020320UL //Access:RW DataWidth:0x4 // Gain of P/I loop filter proportional path during fine phase acquisition mode. Global register. Reset on POR reset. -#define IPC_REG_TCAM_BIST_CONTROL_TSEM_VFC_K2_E5 0x020324UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved -#define IPC_REG_PLL_STORM_E28_KPP_BB 0x020324UL //Access:RW DataWidth:0x4 // Control of the non-zero pole in the PLL digital filter. Global register. Reset on POR reset. -#define IPC_REG_TCAM_BIST_CONTROL_MSEM_K2_E5 0x020328UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved -#define IPC_REG_PLL_STORM_E28_LOCK_BB 0x020328UL //Access:R DataWidth:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset. -#define IPC_REG_TCAM_BIST_CONTROL_PRS_GFT_K2_E5 0x02032cUL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved -#define IPC_REG_PLL_STORM_E28_STATUS_BB 0x02032cUL //Access:R DataWidth:0xc // Internal Status Bits of the PLL Global register. Reset on POR reset. -#define IPC_REG_TCAM_BIST_CONTROL_PRS_L_K2_E5 0x020330UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved -#define IPC_REG_LCPLL_E28_PWRDN_BB 0x020330UL //Access:RW DataWidth:0x1 // PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR -#define IPC_REG_TCAM_BIST_CONTROL_PRS_H_K2_E5 0x020334UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved -#define IPC_REG_LCPLL_E28_RESET_VCO_BB 0x020334UL //Access:RW DataWidth:0x1 // Resets the VCO logic in the PLL. The reset is Active High -#define IPC_REG_TCAM_BIST_CONTROL_IGU_K2_E5 0x020338UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved -#define IPC_REG_LCPLL_E28_RESET_POST_BB 0x020338UL //Access:RW DataWidth:0x1 // Resets the Post Divider logic in the PLL. The reset is Active High -#define IPC_REG_CLK_DFT_MS_125M_DIV_K2_E5 0x02033cUL //Access:RW DataWidth:0x8 // divider value for clk_dft_ms_125, the division is 2*value. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divide by 4 -#define IPC_REG_LCPLL_E28_PDIV_BB 0x02033cUL //Access:RW DataWidth:0x4 // Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset. -#define IPC_REG_CLK_DFT_MS_150M_DIV_K2_E5 0x020340UL //Access:RW DataWidth:0x8 // -#define IPC_REG_LCPLL_E28_NDIV_INT_BB 0x020340UL //Access:RW DataWidth:0xa // Feedback divider control 0000000000 = not usable 0000000001 = not usable ... 0000001111 = not usable 0000010000 = 16 ... 1111111111 = 1023 Global register. Reset on POR reset. -#define IPC_REG_CLK_DFT_MS_60M_DIV_K2_E5 0x020344UL //Access:RW DataWidth:0x8 // -#define IPC_REG_LCPLL_E28_CH0_MDIV_BB 0x020344UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-0 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset. -#define IPC_REG_CLK_DFT_MS_70M_DIV_K2_E5 0x020348UL //Access:RW DataWidth:0x8 // -#define IPC_REG_LCPLL_E28_CH1_MDIV_BB 0x020348UL //Access:RW DataWidth:0x8 // Post-divider ratio for channel-1 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset. -#define IPC_REG_CLK_DFT_MS_412M_DIV_K2_E5 0x02034cUL //Access:RW DataWidth:0x8 // #define IPC_REG_LCPLL_E28_CH_ENABLEB_BB 0x02034cUL //Access:RW DataWidth:0x6 // Active Low Channel Enable. Global register. Reset on POR reset. -#define IPC_REG_CLK_DFT_NWS_644M_DIV_K2_E5 0x020350UL //Access:RW DataWidth:0x8 // +#define IPC_REG_TCAM_BIST_REGISTER_OR_EXTERNAL_SELECT_K2 0x0202f0UL //Access:RW DataWidth:0x1 // 0 - control of the tcam bist is from the IPC register tcam_bist_control and tcam_bist_num. 1 - control of the tcam bist is from the external pins. by default these pins are gurenteed to be zero so tcam bist will not start running. +#define IPC_REG_TCAM_BIST_REGISTER_OR_EXTERNAL_SELECT_E5 0x020350UL //Access:RW DataWidth:0x1 // 0 - control of the tcam bist is from the IPC register tcam_bist_control and tcam_bist_num. 1 - control of the tcam bist is from the external pins. by default these pins are gurenteed to be zero so tcam bist will not start running. #define IPC_REG_LCPLL_E28_CTRL_0_BB 0x020350UL //Access:RW DataWidth:0x20 // PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset. -#define IPC_REG_CLK_DFT_NWS_300M_DIV_K2_E5 0x020354UL //Access:RW DataWidth:0x8 // +#define IPC_REG_TCAM_BIST_NUM_K2 0x0202f4UL //Access:RW DataWidth:0x5 // select the cam instance when reading the status of the cam in tcam_bist_status 0 ccfc_ccam 1 ccfc_scam 2 igu 3 msem 4 prs_gft 5 prs_h 6 prs_l 7 psem 8 psem_vfc 9 qm 10 tcfc_ccam 11 tsem 12 tsem_vfc 13 usem 14 xsem 15 ysem +#define IPC_REG_TCAM_BIST_NUM_E5 0x020354UL //Access:RW DataWidth:0x5 // select the cam instance when reading the status of the cam in tcam_bist_status 0 ccfc_ccam 1 ccfc_scam 2 igu 3 msem 4 prs_gft 5 prs_h 6 prs_l 7 psem 8 psem_vfc 9 qm 10 tcfc_ccam 11 tsem 12 tsem_vfc 13 usem 14 xsem 15 ysem #define IPC_REG_LCPLL_E28_CTRL_1_BB 0x020354UL //Access:RW DataWidth:0x20 // PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset. -#define IPC_REG_CLK_DFT_NWS_100M_DIV_K2_E5 0x020358UL //Access:RW DataWidth:0x8 // +#define IPC_REG_TCAM_BIST_STATUS_K2 0x0202f8UL //Access:R DataWidth:0x6 // tcam bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(bist_sho) bit 4 - reserved bit 5 - reserved +#define IPC_REG_TCAM_BIST_STATUS_E5 0x020358UL //Access:R DataWidth:0x6 // tcam bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(bist_sho) bit 4 - reserved bit 5 - reserved #define IPC_REG_LCPLL_E28_CTRL_2_BB 0x020358UL //Access:RW DataWidth:0x2 // PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset. -#define IPC_REG_CLK_DFT_PCIES_500M_DIV_K2_E5 0x02035cUL //Access:RW DataWidth:0x8 // +#define IPC_REG_TCAM_BIST_CONTROL_CCFC_CCAM_K2 0x0202fcUL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved +#define IPC_REG_TCAM_BIST_CONTROL_CCFC_CCAM_E5 0x02035cUL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved #define IPC_REG_LCPLL_E28_KI_BB 0x02035cUL //Access:RW DataWidth:0x3 // Integrator gain control of the PLL digital filter. Global register. Reset on POR reset. -#define IPC_REG_CLK_DFT_PCIES_100M_DIV_K2_E5 0x020360UL //Access:RW DataWidth:0x8 // +#define IPC_REG_TCAM_BIST_CONTROL_CCFC_SCAM_K2 0x020300UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved +#define IPC_REG_TCAM_BIST_CONTROL_CCFC_SCAM_E5 0x020360UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved #define IPC_REG_LCPLL_E28_KP_BB 0x020360UL //Access:RW DataWidth:0x4 // Gain of P/I loop filter proportional path during fine phase acquisition mode. Global register. Reset on POR reset. -#define IPC_REG_CLK_DFT_PCIES_50M_DIV_K2_E5 0x020364UL //Access:RW DataWidth:0x8 // +#define IPC_REG_TCAM_BIST_CONTROL_TCFC_CCAM_K2 0x020304UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved +#define IPC_REG_TCAM_BIST_CONTROL_TCFC_CCAM_E5 0x020364UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved #define IPC_REG_LCPLL_E28_KPP_BB 0x020364UL //Access:RW DataWidth:0x4 // Control of the non-zero pole in the PLL digital filter. Global register. Reset on POR reset. -#define IPC_REG_STRENGTH_IO_CONTROL_K2_E5 0x020368UL //Access:RW DataWidth:0x6 // Sets the CTL# (# in [0..5]) I/Os of the PADS in non - scan/mbist modes +#define IPC_REG_TCAM_BIST_CONTROL_QM_K2 0x020308UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved +#define IPC_REG_TCAM_BIST_CONTROL_QM_E5 0x020368UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved #define IPC_REG_LCPLL_E28_LOCK_BB 0x020368UL //Access:R DataWidth:0x1 // LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset. -#define IPC_REG_SLEW_IO_CONTROL_K2_E5 0x02036cUL //Access:RW DataWidth:0x2 // Sets the SL# (# in [0..1]) I/Os of the PADS in non - scan/mbist modes +#define IPC_REG_TCAM_BIST_CONTROL_XSEM_K2 0x02030cUL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved +#define IPC_REG_TCAM_BIST_CONTROL_XSEM_E5 0x02036cUL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved #define IPC_REG_LCPLL_E28_STATUS_BB 0x02036cUL //Access:R DataWidth:0xc // Internal Status Bits of the PLL Global register. Reset on POR reset. -#define IPC_REG_BISR_DEBUG_K2_E5 0x020370UL //Access:R DataWidth:0x14 // debug from bisr +#define IPC_REG_TCAM_BIST_CONTROL_YSEM_K2 0x020310UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved +#define IPC_REG_TCAM_BIST_CONTROL_YSEM_E5 0x020370UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved #define IPC_REG_PMFC_DVT_EN_BB 0x020370UL //Access:RW DataWidth:0x1 // Enable the MAC SERDES -#define IPC_REG_ECO_RESERVED_K2_E5 0x020374UL //Access:RW DataWidth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc. +#define IPC_REG_TCAM_BIST_CONTROL_PSEM_K2 0x020314UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved +#define IPC_REG_TCAM_BIST_CONTROL_PSEM_E5 0x020374UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved #define IPC_REG_PMFC_DVT_IDDQ_BB 0x020374UL //Access:RW DataWidth:0x1 // MAC SERDES IDDQ +#define IPC_REG_TCAM_BIST_CONTROL_PSEM_VFC_K2 0x020318UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved +#define IPC_REG_TCAM_BIST_CONTROL_PSEM_VFC_E5 0x020378UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved #define IPC_REG_PMFC_DVT_PWRDWN_BB 0x020378UL //Access:RW DataWidth:0x1 // MAC SERDES Power Down +#define IPC_REG_TCAM_BIST_CONTROL_USEM_K2 0x02031cUL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved +#define IPC_REG_TCAM_BIST_CONTROL_USEM_E5 0x02037cUL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved #define IPC_REG_PMFC_DVT_REFIN_EN_BB 0x02037cUL //Access:RW DataWidth:0x1 // +#define IPC_REG_TCAM_BIST_CONTROL_TSEM_K2 0x020320UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved +#define IPC_REG_TCAM_BIST_CONTROL_TSEM_E5 0x020380UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved #define IPC_REG_PMFC_DVT_REFOUT_EN_BB 0x020380UL //Access:RW DataWidth:0x1 // +#define IPC_REG_TCAM_BIST_CONTROL_TSEM_VFC_K2 0x020324UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved +#define IPC_REG_TCAM_BIST_CONTROL_TSEM_VFC_E5 0x020384UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved #define IPC_REG_PMFC_DVT_TSC_RESET_BB 0x020384UL //Access:RW DataWidth:0x1 // +#define IPC_REG_TCAM_BIST_CONTROL_MSEM_K2 0x020328UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved +#define IPC_REG_TCAM_BIST_CONTROL_MSEM_E5 0x020388UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved #define IPC_REG_PMFC_DVT_MDIO_FAST_MODE_BB 0x020388UL //Access:RW DataWidth:0x1 // +#define IPC_REG_TCAM_BIST_CONTROL_PRS_GFT_K2 0x02032cUL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved +#define IPC_REG_TCAM_BIST_CONTROL_PRS_GFT_E5 0x02038cUL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved #define IPC_REG_PMFC_PHY_ADDR_BB 0x02038cUL //Access:RW DataWidth:0x5 // MDIO PHY Address. The SERDES uses this address to determine whether or not it is the recipient of the message on the MDIO interface. +#define IPC_REG_TCAM_BIST_CONTROL_PRS_L_K2 0x020330UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved +#define IPC_REG_TCAM_BIST_CONTROL_PRS_L_E5 0x020390UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved #define IPC_REG_PMFC_TX_DRV_HV_DISABLE_BB 0x020390UL //Access:RW DataWidth:0x1 // 1 : Disable high voltage for Tx Driver +#define IPC_REG_TCAM_BIST_CONTROL_PRS_H_K2 0x020334UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved +#define IPC_REG_TCAM_BIST_CONTROL_PRS_H_E5 0x020394UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved #define IPC_REG_PMFC_BOND_OPTION_BB 0x020394UL //Access:RW DataWidth:0x9 // Bonding option for PM Falcon +#define IPC_REG_TCAM_BIST_CONTROL_IGU_K2 0x020338UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved +#define IPC_REG_TCAM_BIST_CONTROL_IGU_E5 0x020398UL //Access:RW DataWidth:0x6 // tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved #define IPC_REG_PMFC_PLL_LOCK_BB 0x020398UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global register. +#define IPC_REG_CLK_DFT_MS_125M_DIV_K2 0x02033cUL //Access:RW DataWidth:0x8 // divider value for clk_dft_ms_125, the division is 2*value. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divide by 4 +#define IPC_REG_CLK_DFT_MS_125M_DIV_E5 0x02039cUL //Access:RW DataWidth:0x8 // divider value for clk_dft_ms_125, the division is 2*value. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divide by 4 #define IPC_REG_PMFC_RECOVER_CLOCK_LOCK_BB 0x02039cUL //Access:R DataWidth:0x4 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global register. +#define IPC_REG_CLK_DFT_MS_150M_DIV_K2 0x020340UL //Access:RW DataWidth:0x8 // +#define IPC_REG_CLK_DFT_MS_150M_DIV_E5 0x0203a0UL //Access:RW DataWidth:0x8 // #define IPC_REG_PMEG_DVT_EN_BB 0x0203a0UL //Access:RW DataWidth:0x1 // Enable the MAC SERDES +#define IPC_REG_CLK_DFT_MS_60M_DIV_K2 0x020344UL //Access:RW DataWidth:0x8 // +#define IPC_REG_CLK_DFT_MS_60M_DIV_E5 0x0203a4UL //Access:RW DataWidth:0x8 // #define IPC_REG_PMEG_DVT_IDDQ_BB 0x0203a4UL //Access:RW DataWidth:0x1 // MAC SERDES IDDQ +#define IPC_REG_CLK_DFT_MS_70M_DIV_K2 0x020348UL //Access:RW DataWidth:0x8 // +#define IPC_REG_CLK_DFT_MS_70M_DIV_E5 0x0203a8UL //Access:RW DataWidth:0x8 // #define IPC_REG_PMEG_DVT_PWRDWN_BB 0x0203a8UL //Access:RW DataWidth:0x1 // MAC SERDES Power Down +#define IPC_REG_CLK_DFT_MS_412M_DIV_K2 0x02034cUL //Access:RW DataWidth:0x8 // +#define IPC_REG_CLK_DFT_MS_412M_DIV_E5 0x0203acUL //Access:RW DataWidth:0x8 // #define IPC_REG_PMEG_DVT_REFIN_EN_BB 0x0203acUL //Access:RW DataWidth:0x1 // +#define IPC_REG_CLK_DFT_NWS_644M_DIV_K2 0x020350UL //Access:RW DataWidth:0x8 // +#define IPC_REG_CLK_DFT_NWS_644M_DIV_E5 0x0203b0UL //Access:RW DataWidth:0x8 // #define IPC_REG_PMEG_DVT_REFOUT_EN_BB 0x0203b0UL //Access:RW DataWidth:0x1 // +#define IPC_REG_CLK_DFT_NWS_300M_DIV_K2 0x020354UL //Access:RW DataWidth:0x8 // +#define IPC_REG_CLK_DFT_NWS_300M_DIV_E5 0x0203b4UL //Access:RW DataWidth:0x8 // #define IPC_REG_PMEG_DVT_TSC_RESET_BB 0x0203b4UL //Access:RW DataWidth:0x1 // +#define IPC_REG_CLK_DFT_NWS_100M_DIV_K2 0x020358UL //Access:RW DataWidth:0x8 // +#define IPC_REG_CLK_DFT_NWS_100M_DIV_E5 0x0203b8UL //Access:RW DataWidth:0x8 // #define IPC_REG_PMEG_DVT_MDIO_FAST_MODE_BB 0x0203b8UL //Access:RW DataWidth:0x1 // +#define IPC_REG_CLK_DFT_PCIES_500M_DIV_K2 0x02035cUL //Access:RW DataWidth:0x8 // +#define IPC_REG_CLK_DFT_PCIES_500M_DIV_E5 0x0203bcUL //Access:RW DataWidth:0x8 // #define IPC_REG_PMEG_PHY_ADDR_BB 0x0203bcUL //Access:RW DataWidth:0x5 // MDIO PHY Address. The SERDES uses this address to determine whether or not it is the recipient of the message on the MDIO interface. +#define IPC_REG_CLK_DFT_PCIES_100M_DIV_K2 0x020360UL //Access:RW DataWidth:0x8 // +#define IPC_REG_CLK_DFT_PCIES_100M_DIV_E5 0x0203c0UL //Access:RW DataWidth:0x8 // #define IPC_REG_PMEG_BOND_OPTION_BB 0x0203c0UL //Access:RW DataWidth:0xd // Bonding option for PM Eagle +#define IPC_REG_CLK_DFT_PCIES_50M_DIV_K2 0x020364UL //Access:RW DataWidth:0x8 // +#define IPC_REG_CLK_DFT_PCIES_50M_DIV_E5 0x0203c4UL //Access:RW DataWidth:0x8 // #define IPC_REG_PMEG_PLL_LOCK_BB 0x0203c4UL //Access:R DataWidth:0x1 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global register. +#define IPC_REG_STRENGTH_IO_CONTROL_K2 0x020368UL //Access:RW DataWidth:0x6 // Sets the CTL# (# in [0..5]) I/Os of the PADS in non - scan/mbist modes +#define IPC_REG_STRENGTH_IO_CONTROL_E5 0x0203c8UL //Access:RW DataWidth:0x2 // TBD #define IPC_REG_PMEG_RECOVER_CLOCK_LOCK_BB 0x0203c8UL //Access:R DataWidth:0x4 // MAC SERDES PLL lock. 0-unlocked; 1-locked. Global register. +#define IPC_REG_SLEW_IO_CONTROL_K2 0x02036cUL //Access:RW DataWidth:0x2 // Sets the SL# (# in [0..1]) I/Os of the PADS in non - scan/mbist modes +#define IPC_REG_SLEW_IO_CONTROL_E5 0x0203ccUL //Access:RW DataWidth:0x1 // TBD #define IPC_REG_PCIE_PIPE_PLL_LOCK_BB 0x0203ccUL //Access:R DataWidth:0x8 // PCIe lock signals. 0-unlocked; 1-locked. Global register. +#define IPC_REG_BISR_DEBUG_K2 0x020370UL //Access:R DataWidth:0x14 // debug from bisr +#define IPC_REG_BISR_DEBUG_E5 0x0203d0UL //Access:R DataWidth:0x14 // debug from bisr #define IPC_REG_PCIES_PIPE_IDDQ_BB 0x0203d0UL //Access:RW DataWidth:0x1 // +#define IPC_REG_ECO_RESERVED_K2 0x020374UL //Access:RW DataWidth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc. +#define IPC_REG_ECO_RESERVED_E5 0x0203d4UL //Access:RW DataWidth:0x20 // This register is reserved for future ECO fixes. It may be used for chicken-bits, etc. #define IPC_REG_PCIES_RESETMDIO_N_BB 0x0203d4UL //Access:RW DataWidth:0x1 // #define IPC_REG_PCIES_ALT_CLK_SELECT_BB 0x0203d8UL //Access:RW DataWidth:0x1 // #define IPC_REG_SGMII_RESETS_BB 0x0203dcUL //Access:RW DataWidth:0x3 // Multi Field Register. @@ -36813,75 +39848,179 @@ #define MCP2_REG_PRTY_MASK_ROM_PARITY (0x1<<0) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS.ROM_PARITY . #define MCP2_REG_PRTY_MASK_ROM_PARITY_SHIFT 0 #define MCP2_REG_ECO_RESERVED 0x052200UL //Access:RW DataWidth:0x8 // Debug only: Reserved bits for ECO. -#define MCP2_REG_PRTY_MASK_H_0 0x052208UL //Access:RW DataWidth:0xc // Multi Field Register. - #define MCP2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT . - #define MCP2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_SHIFT 0 - #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_0_RF_INT . - #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_SHIFT 1 - #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_1_RF_INT . - #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_SHIFT 2 - #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_2_RF_INT (0x1<<3) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_2_RF_INT . - #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_2_RF_INT_SHIFT 3 - #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_3_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_3_RF_INT . - #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_3_RF_INT_SHIFT 4 - #define MCP2_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT (0x1<<5) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT . - #define MCP2_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_SHIFT 5 - #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . - #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT 6 - #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY (0x1<<7) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . - #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT 7 - #define MCP2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY (0x1<<8) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . - #define MCP2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT 8 - #define MCP2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . - #define MCP2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT 9 +#define MCP2_REG_PRTY_MASK_H_0 0x052208UL //Access:RW DataWidth:0x11 // Multi Field Register. + #define MCP2_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT . + #define MCP2_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_E5_SHIFT 0 + #define MCP2_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_E5 (0x1<<1) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT . + #define MCP2_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_E5_SHIFT 1 + #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_E5 (0x1<<2) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT . + #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_E5_SHIFT 2 + #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_E5 (0x1<<3) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT . + #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_E5_SHIFT 3 + #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_ECC_2_RF_INT_E5 (0x1<<4) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM003_I_ECC_2_RF_INT . + #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_ECC_2_RF_INT_E5_SHIFT 4 + #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_ECC_3_RF_INT_E5 (0x1<<5) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM003_I_ECC_3_RF_INT . + #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_ECC_3_RF_INT_E5_SHIFT 5 + #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_ECC_0_RF_INT_E5 (0x1<<6) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM004_I_ECC_0_RF_INT . + #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_ECC_0_RF_INT_E5_SHIFT 6 + #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_ECC_1_RF_INT_E5 (0x1<<7) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM004_I_ECC_1_RF_INT . + #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_ECC_1_RF_INT_E5_SHIFT 7 + #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_ECC_2_RF_INT_E5 (0x1<<8) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM004_I_ECC_2_RF_INT . + #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_ECC_2_RF_INT_E5_SHIFT 8 + #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_ECC_3_RF_INT_E5 (0x1<<9) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM004_I_ECC_3_RF_INT . + #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_ECC_3_RF_INT_E5_SHIFT 9 #define MCP2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY . #define MCP2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT 10 - #define MCP2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . - #define MCP2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT 11 -#define MCP2_REG_MEM006_RF_ECC_ERROR_CONNECT_0 0x052214UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next write to memory: mcp.i_mcp_scratchpad_mem_0.rf_ecc_error_connect_0 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define MCP2_REG_MEM006_RF_ECC_ERROR_CONNECT_1 0x052218UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next write to memory: mcp.i_mcp_scratchpad_mem_0.rf_ecc_error_connect_1 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define MCP2_REG_MEM006_RF_ECC_ERROR_CONNECT_2 0x05221cUL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next write to memory: mcp.i_mcp_scratchpad_mem_0.rf_ecc_error_connect_2 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define MCP2_REG_MEM006_RF_ECC_ERROR_CONNECT_3 0x052220UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next write to memory: mcp.i_mcp_scratchpad_mem_0.rf_ecc_error_connect_3 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define MCP2_REG_MEM_ECC_ENABLE_0 0x052224UL //Access:RW DataWidth:0x6 // Multi Field Register. - #define MCP2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer - #define MCP2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_SHIFT 0 - #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN (0x1<<1) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem - #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN_SHIFT 1 - #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN (0x1<<2) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem - #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_SHIFT 2 - #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_2_EN (0x1<<3) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem - #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_2_EN_SHIFT 3 - #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_3_EN (0x1<<4) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem - #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_3_EN_SHIFT 4 - #define MCP2_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN (0x1<<5) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpad_nobe_mem - #define MCP2_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN_SHIFT 5 -#define MCP2_REG_MEM_ECC_PARITY_ONLY_0 0x052228UL //Access:RW DataWidth:0x6 // Multi Field Register. - #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer - #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_SHIFT 0 - #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY (0x1<<1) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem - #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY_SHIFT 1 - #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY (0x1<<2) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem - #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_SHIFT 2 - #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_2_PRTY (0x1<<3) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem - #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_2_PRTY_SHIFT 3 - #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_3_PRTY (0x1<<4) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem - #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_3_PRTY_SHIFT 4 - #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY (0x1<<5) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpad_nobe_mem - #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY_SHIFT 5 -#define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0 0x05222cUL //Access:RC DataWidth:0x6 // Multi Field Register. - #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer - #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_SHIFT 0 - #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem - #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT_SHIFT 1 - #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem - #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_SHIFT 2 - #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_2_CORRECT (0x1<<3) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem - #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_2_CORRECT_SHIFT 3 - #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_3_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem - #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_3_CORRECT_SHIFT 4 - #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT (0x1<<5) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpad_nobe_mem - #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT_SHIFT 5 -#define MCP2_REG_MEM_ECC_EVENTS 0x052230UL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. + #define MCP2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . + #define MCP2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5_SHIFT 11 + #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . + #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_E5_SHIFT 12 + #define MCP2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY . + #define MCP2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5_SHIFT 13 + #define MCP2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY . + #define MCP2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_E5_SHIFT 14 + #define MCP2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY . + #define MCP2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5_SHIFT 15 + #define MCP2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . + #define MCP2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT 8 + #define MCP2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . + #define MCP2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5_SHIFT 16 + #define MCP2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT . + #define MCP2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2_SHIFT 0 + #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_BB_K2 (0x1<<1) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_0_RF_INT . + #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_BB_K2_SHIFT 1 + #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_BB_K2 (0x1<<2) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_1_RF_INT . + #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_BB_K2_SHIFT 2 + #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_2_RF_INT_BB_K2 (0x1<<3) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_2_RF_INT . + #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_2_RF_INT_BB_K2_SHIFT 3 + #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_3_RF_INT_BB_K2 (0x1<<4) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_3_RF_INT . + #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_3_RF_INT_BB_K2_SHIFT 4 + #define MCP2_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_BB_K2 (0x1<<5) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT . + #define MCP2_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_BB_K2_SHIFT 5 + #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2 (0x1<<6) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . + #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT 6 + #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2 (0x1<<7) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . + #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT 7 + #define MCP2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2 (0x1<<9) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . + #define MCP2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT 9 + #define MCP2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2 (0x1<<11) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . + #define MCP2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_K2_SHIFT 11 +#define MCP2_REG_MEM003_RF_ECC_ERROR_CONNECT_0_E5 0x052214UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next write to memory: mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.rf_ecc_error_connect_0 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define MCP2_REG_MEM006_RF_ECC_ERROR_CONNECT_0_BB_K2 0x052214UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next write to memory: mcp.i_mcp_scratchpad_mem_0.rf_ecc_error_connect_0 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define MCP2_REG_MEM003_RF_ECC_ERROR_CONNECT_1_E5 0x052218UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next write to memory: mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.rf_ecc_error_connect_1 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define MCP2_REG_MEM006_RF_ECC_ERROR_CONNECT_1_BB_K2 0x052218UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next write to memory: mcp.i_mcp_scratchpad_mem_0.rf_ecc_error_connect_1 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define MCP2_REG_MEM003_RF_ECC_ERROR_CONNECT_2_E5 0x05221cUL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next write to memory: mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.rf_ecc_error_connect_2 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define MCP2_REG_MEM006_RF_ECC_ERROR_CONNECT_2_BB_K2 0x05221cUL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next write to memory: mcp.i_mcp_scratchpad_mem_0.rf_ecc_error_connect_2 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define MCP2_REG_MEM003_RF_ECC_ERROR_CONNECT_3_E5 0x052220UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next write to memory: mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.rf_ecc_error_connect_3 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define MCP2_REG_MEM006_RF_ECC_ERROR_CONNECT_3_BB_K2 0x052220UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next write to memory: mcp.i_mcp_scratchpad_mem_0.rf_ecc_error_connect_3 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define MCP2_REG_MEM004_RF_ECC_ERROR_CONNECT_0_E5 0x052224UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next write to memory: mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.rf_ecc_error_connect_0 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define MCP2_REG_MEM004_RF_ECC_ERROR_CONNECT_1_E5 0x052228UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next write to memory: mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.rf_ecc_error_connect_1 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define MCP2_REG_MEM004_RF_ECC_ERROR_CONNECT_2_E5 0x05222cUL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next write to memory: mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.rf_ecc_error_connect_2 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define MCP2_REG_MEM004_RF_ECC_ERROR_CONNECT_3_E5 0x052230UL //Access:W DataWidth:0xa // Register to generate up to two ECC errors on the next write to memory: mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.rf_ecc_error_connect_3 Includes 2 words of 5 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 8. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define MCP2_REG_MEM_ECC_ENABLE_0_BB_K2 0x052224UL //Access:RW DataWidth:0x6 // Multi Field Register. +#define MCP2_REG_MEM_ECC_ENABLE_0_E5 0x052234UL //Access:RW DataWidth:0xa // Multi Field Register. + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_E5_SHIFT 0 + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_E5 (0x1<<1) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpad_nobe_mem + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_EN_E5_SHIFT 1 + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN_E5 (0x1<<2) // Enable ECC for memory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN_E5_SHIFT 2 + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN_E5 (0x1<<3) // Enable ECC for memory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN_E5_SHIFT 3 + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_2_EN_E5 (0x1<<4) // Enable ECC for memory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_2_EN_E5_SHIFT 4 + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_3_EN_E5 (0x1<<5) // Enable ECC for memory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_3_EN_E5_SHIFT 5 + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_0_EN_E5 (0x1<<6) // Enable ECC for memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_0_EN_E5_SHIFT 6 + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_1_EN_E5 (0x1<<7) // Enable ECC for memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_1_EN_E5_SHIFT 7 + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_2_EN_E5 (0x1<<8) // Enable ECC for memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_2_EN_E5_SHIFT 8 + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_3_EN_E5 (0x1<<9) // Enable ECC for memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_3_EN_E5_SHIFT 9 + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_K2 (0x1<<0) // Enable ECC for memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_K2_SHIFT 0 + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN_BB_K2 (0x1<<1) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN_BB_K2_SHIFT 1 + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_BB_K2 (0x1<<2) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_BB_K2_SHIFT 2 + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_2_EN_BB_K2 (0x1<<3) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_2_EN_BB_K2_SHIFT 3 + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_3_EN_BB_K2 (0x1<<4) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_3_EN_BB_K2_SHIFT 4 + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN_BB_K2 (0x1<<5) // Enable ECC for memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpad_nobe_mem + #define MCP2_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_EN_BB_K2_SHIFT 5 +#define MCP2_REG_MEM_ECC_PARITY_ONLY_0_BB_K2 0x052228UL //Access:RW DataWidth:0x6 // Multi Field Register. +#define MCP2_REG_MEM_ECC_PARITY_ONLY_0_E5 0x052238UL //Access:RW DataWidth:0xa // Multi Field Register. + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_E5_SHIFT 0 + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpad_nobe_mem + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_PRTY_E5_SHIFT 1 + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY_E5 (0x1<<2) // Set parity only for memory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY_E5_SHIFT 2 + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY_E5 (0x1<<3) // Set parity only for memory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY_E5_SHIFT 3 + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_2_PRTY_E5 (0x1<<4) // Set parity only for memory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_2_PRTY_E5_SHIFT 4 + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_3_PRTY_E5 (0x1<<5) // Set parity only for memory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_3_PRTY_E5_SHIFT 5 + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_0_PRTY_E5 (0x1<<6) // Set parity only for memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_0_PRTY_E5_SHIFT 6 + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_1_PRTY_E5 (0x1<<7) // Set parity only for memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_1_PRTY_E5_SHIFT 7 + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_2_PRTY_E5 (0x1<<8) // Set parity only for memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_2_PRTY_E5_SHIFT 8 + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_3_PRTY_E5 (0x1<<9) // Set parity only for memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_3_PRTY_E5_SHIFT 9 + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_K2_SHIFT 0 + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY_BB_K2 (0x1<<1) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY_BB_K2_SHIFT 1 + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_BB_K2 (0x1<<2) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_BB_K2_SHIFT 2 + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_2_PRTY_BB_K2 (0x1<<3) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_2_PRTY_BB_K2_SHIFT 3 + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_3_PRTY_BB_K2 (0x1<<4) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_3_PRTY_BB_K2_SHIFT 4 + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY_BB_K2 (0x1<<5) // Set parity only for memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpad_nobe_mem + #define MCP2_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_PRTY_BB_K2_SHIFT 5 +#define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2 0x05222cUL //Access:RC DataWidth:0x6 // Multi Field Register. +#define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_E5 0x05223cUL //Access:RC DataWidth:0xa // Multi Field Register. + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_E5_SHIFT 0 + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_E5 (0x1<<1) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpad_nobe_mem + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_CORRECT_E5_SHIFT 1 + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT_E5 (0x1<<2) // Record if a correctable error occurred on memory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT_E5_SHIFT 2 + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT_E5 (0x1<<3) // Record if a correctable error occurred on memory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT_E5_SHIFT 3 + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_2_CORRECT_E5 (0x1<<4) // Record if a correctable error occurred on memory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_2_CORRECT_E5_SHIFT 4 + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_3_CORRECT_E5 (0x1<<5) // Record if a correctable error occurred on memory ecc instance mcp.gen_scratchpad_mem[0].i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_3_CORRECT_E5_SHIFT 5 + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_0_CORRECT_E5 (0x1<<6) // Record if a correctable error occurred on memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_0_CORRECT_E5_SHIFT 6 + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_1_CORRECT_E5 (0x1<<7) // Record if a correctable error occurred on memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_1_CORRECT_E5_SHIFT 7 + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_2_CORRECT_E5 (0x1<<8) // Record if a correctable error occurred on memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_2_CORRECT_E5_SHIFT 8 + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_3_CORRECT_E5 (0x1<<9) // Record if a correctable error occurred on memory ecc instance mcp.gen_scratchpad_mem[1].i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_3_CORRECT_E5_SHIFT 9 + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_K2 (0x1<<0) // Record if a correctable error occurred on memory ecc instance mcp.i_flsh.i_flsh_buffer.i_ecc in module flsh_buffer + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_K2_SHIFT 0 + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT_BB_K2 (0x1<<1) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_0 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT_BB_K2_SHIFT 1 + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_BB_K2 (0x1<<2) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_1 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_BB_K2_SHIFT 2 + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_2_CORRECT_BB_K2 (0x1<<3) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_2 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_2_CORRECT_BB_K2_SHIFT 3 + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_3_CORRECT_BB_K2 (0x1<<4) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_0.i_ecc_3 in module mcp_scratchpad_mem + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_3_CORRECT_BB_K2_SHIFT 4 + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT_BB_K2 (0x1<<5) // Record if a correctable error occurred on memory ecc instance mcp.i_mcp_scratchpad_mem_1.i_ecc in module mcp_scratchpad_nobe_mem + #define MCP2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_CORRECT_BB_K2_SHIFT 5 +#define MCP2_REG_MEM_ECC_EVENTS_BB_K2 0x052230UL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. +#define MCP2_REG_MEM_ECC_EVENTS_E5 0x052240UL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. #define MCP2_REG_DBG_SELECT 0x052400UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output #define MCP2_REG_DBG_DWORD_ENABLE 0x052404UL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line) in the selected line (before shift).for selecting a line to output #define MCP2_REG_DBG_SHIFT 0x052408UL //Access:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) right shifting of the selected line (after the masking). @@ -37517,6 +40656,67 @@ #define PCIE_REG_RESET_STATUS_2_SOFT_PIPE_RST_2_K2_E5 (0x1<<23) // Soft PIPE reset occurred. #define PCIE_REG_RESET_STATUS_2_SOFT_PIPE_RST_2_K2_E5_SHIFT 23 #define PCIE_REG_RESET_STATUS_3_K2_E5 0x054804UL //Access:RW DataWidth:0x18 // Corresponding bits of Reset Status Register 2 will be cleared for bits written with a 1. +#define PXPREQBUS_REG_PRTY_MASK_H_0_K2_E5 0x056004UL //Access:RW DataWidth:0x16 // Multi Field Register. + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2 (0x1<<3) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_SHIFT 3 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5_SHIFT 0 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_E5 (0x1<<1) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_E5_SHIFT 1 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2 (0x1<<13) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT 13 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5_SHIFT 2 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2 (0x1<<4) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT 4 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5_SHIFT 3 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5_SHIFT 4 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_E5 (0x1<<5) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_E5_SHIFT 5 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_E5 (0x1<<6) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_E5_SHIFT 6 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_E5 (0x1<<7) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_E5_SHIFT 7 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2 (0x1<<2) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT 2 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5_SHIFT 8 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2 (0x1<<8) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT 8 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5_SHIFT 9 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_E5 (0x1<<10) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_E5_SHIFT 10 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_E5 (0x1<<11) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_E5_SHIFT 11 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_E5 (0x1<<12) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_E5_SHIFT 12 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5_SHIFT 13 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2_E5 (0x1<<14) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2_E5_SHIFT 14 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_E5 (0x1<<15) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_E5_SHIFT 15 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_E5 (0x1<<16) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_E5_SHIFT 16 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_E5 (0x1<<17) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_E5_SHIFT 17 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_E5 (0x1<<18) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_E5_SHIFT 18 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_E5 (0x1<<19) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_E5_SHIFT 19 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2 (0x1<<0) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT 0 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5_SHIFT 20 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2 (0x1<<9) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT 9 + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: PXPREQBUS_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . + #define PXPREQBUS_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5_SHIFT 21 +#define PXPREQBUS_REG_MEM_ECC_EVENTS_K2_E5 0x056010UL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. +#define PXPREQBUS_REG_ECO_RESERVED_K2_E5 0x056200UL //Access:RW DataWidth:0x1 // Reserved bits for ECO. #define DORQ_REG_INIT 0x100000UL //Access:RW DataWidth:0x1 // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0. #define DORQ_REG_IFEN 0x100040UL //Access:RW DataWidth:0x1 // Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity. #define DORQ_REG_INT_STS 0x100180UL //Access:R DataWidth:0xc // Multi Field Register. @@ -38184,9 +41384,9 @@ #define DORQ_REG_IEDPM_ABORT_DETAILS_CID_E5 0x102bc4UL //Access:R DataWidth:0x20 // Stores the details of the first aborted IEDPM doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: CID. #define DORQ_REG_IEDPM_ABORT_DETAILS_DPM_SIZE_E5 0x102bc8UL //Access:R DataWidth:0x6 // Stores the details of the first aborted IEDPM doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: Doorbell DPM size. #define DORQ_REG_IEDPM_ABORT_DETAILS_SRC_CLN_ID_E5 0x102bccUL //Access:R DataWidth:0x4 // Stores the details of the first aborted IEDPM doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: Source client ID. -#define DORQ_REG_IEDPM_ABORT_DETAILS_REASON_E5 0x102bd0UL //Access:R DataWidth:0x5 // Stores the details of the first aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: 0 - First DPM doorbell does not match DPM global start conditions at CFC load response for Internal EDPM doorbell; 1 - First DPM doorbell does not match DPM global start conditions at WAIT_CFC state for Internal EDPM doorbell; 2 - IEDPM context check fail; 3 - IEDPM DbTimer expiration; 4 - CFC load response with error; +#define DORQ_REG_IEDPM_ABORT_DETAILS_REASON_E5 0x102bd0UL //Access:R DataWidth:0x6 // Stores the details of the first aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: 0 - First DPM doorbell does not match DPM global start conditions at CFC load response for Internal EDPM doorbell; 1 - First DPM doorbell does not match DPM global start conditions at WAIT_CFC state for Internal EDPM doorbell; 2 - IEDPM context check fail; 3 - IEDPM DbTimer expiration; 4 - CFC load response with error; 5 - Force abort; #define DORQ_REG_IEDPM_ABORT_DETAILS_REL_E5 0x102bd4UL //Access:W DataWidth:0x1 // Clears iedpm_abort_details and makes it ready for the next details capture. Write only. -#define DORQ_REG_IEDPM_ABORT_REASON_E5 0x102bd8UL //Access:R DataWidth:0x5 // Sticky status of abort reason (a bit per reason). It is reset on write to db_abort_details_rel. 0 - First DPM doorbell does not match DPM global start conditions at CFC load response for Internal EDPM doorbell; 1 - First DPM doorbell does not match DPM global start conditions at WAIT_CFC state for Internal EDPM doorbell; 2 - IEDPM context check fail; 3 - IEDPM DbTimer expiration; 4 - CFC load response with error; +#define DORQ_REG_IEDPM_ABORT_REASON_E5 0x102bd8UL //Access:R DataWidth:0x6 // Sticky status of abort reason (a bit per reason). It is reset on write to db_abort_details_rel. 0 - First DPM doorbell does not match DPM global start conditions at CFC load response for Internal EDPM doorbell; 1 - First DPM doorbell does not match DPM global start conditions at WAIT_CFC state for Internal EDPM doorbell; 2 - IEDPM context check fail; 3 - IEDPM DbTimer expiration; 4 - CFC load response with error; 5 - Force abort; #define DORQ_REG_IEDPM_DROP_DETAILS_REASON_E5 0x102bdcUL //Access:R DataWidth:0x5 // Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_details_rel. The following details of the transaction will be recorded: IEDPM doorbell drop reason: 4 - First QWord (offset 0) arives on IEDPM buffer which is not free; 3 - Non-first QWord (offset other than 0) arives on IEDPM buffer which is not free and non-contigious offset; 2 - Non-first QWord (offset other than 0) arives on IEDPM buffer which is free; 1 - Drop prior to being exposed to IEDPM buffer due to first drop doesn't include 2 QWords 0 - Drop prior to being exposed to IEDPM buffer due to ICID is greater or equal to PrvMaxIcid[DbPfid][DbFtype][5]; #define DORQ_REG_IEDPM_DROP_DETAILS_SRC_CLN_E5 0x102be0UL //Access:R DataWidth:0x4 // Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_details_rel. The following details of the transaction will be recorded: Source client ID. #define DORQ_REG_IEDPM_DROP_DETAILS_DB_ADDR_E5 0x102be4UL //Access:R DataWidth:0x8 // Stores the details of the first dropped IEDPM doorbell after logging was re-armed by iedpm_drop_details_rel. The following details of the transaction will be recorded: Address. @@ -38371,9 +41571,9 @@ #define IGU_REG_PRTY_MASK 0x180194UL //Access:RW DataWidth:0x1 // Multi Field Register. #define IGU_REG_PRTY_MASK_CAM_PARITY (0x1<<0) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS.CAM_PARITY . #define IGU_REG_PRTY_MASK_CAM_PARITY_SHIFT 0 -#define IGU_REG_PRTY_MASK_H_0 0x180204UL //Access:RW DataWidth:0x1c // Multi Field Register. - #define IGU_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT . - #define IGU_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_E5_SHIFT 0 +#define IGU_REG_PRTY_MASK_H_0 0x180204UL //Access:RW DataWidth:0x1f // Multi Field Register. + #define IGU_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT . + #define IGU_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_E5_SHIFT 0 #define IGU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2 (0x1<<6) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY . #define IGU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT 6 #define IGU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY . @@ -38444,34 +41644,38 @@ #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT 26 #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5_SHIFT 19 - #define IGU_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_0_E5 (0x1<<20) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY_0 . - #define IGU_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_0_E5_SHIFT 20 - #define IGU_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_1_E5 (0x1<<21) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY_1 . - #define IGU_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_1_E5_SHIFT 21 - #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_0_E5 (0x1<<22) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_0 . - #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_0_E5_SHIFT 22 - #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_1_E5 (0x1<<23) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_1 . - #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_1_E5_SHIFT 23 - #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_2_E5 (0x1<<24) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_2 . - #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_2_E5_SHIFT 24 - #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB (0x1<<2) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . - #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_SHIFT 2 - #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2 (0x1<<3) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . - #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT 3 - #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . - #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5_SHIFT 25 + #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_0_E5 (0x1<<20) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_0 . + #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_0_E5_SHIFT 20 + #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_1_E5 (0x1<<21) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_1 . + #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_1_E5_SHIFT 21 + #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_0_E5 (0x1<<22) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY_0 . + #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_0_E5_SHIFT 22 + #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_1_E5 (0x1<<23) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY_1 . + #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_1_E5_SHIFT 23 + #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_2_E5 (0x1<<24) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY_2 . + #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_2_E5_SHIFT 24 #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB (0x1<<3) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_SHIFT 3 #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2 (0x1<<4) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_SHIFT 4 - #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . - #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5_SHIFT 26 + #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . + #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5_SHIFT 25 #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB (0x1<<4) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_SHIFT 4 #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2 (0x1<<5) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT 5 - #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . - #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5_SHIFT 27 + #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . + #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5_SHIFT 26 + #define IGU_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB (0x1<<5) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . + #define IGU_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_SHIFT 5 + #define IGU_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . + #define IGU_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5_SHIFT 27 + #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_0_E5 (0x1<<28) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_0 . + #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_0_E5_SHIFT 28 + #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_1_E5 (0x1<<29) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_1 . + #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_1_E5_SHIFT 29 + #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_2_E5 (0x1<<30) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_2 . + #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_2_E5_SHIFT 30 #define IGU_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT . #define IGU_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_BB_K2_SHIFT 0 #define IGU_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2 (0x1<<1) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . @@ -38480,6 +41684,10 @@ #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_SHIFT 1 #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2 (0x1<<2) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT 2 + #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB (0x1<<2) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . + #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_SHIFT 2 + #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2 (0x1<<3) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . + #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT 3 #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_BB (0x1<<7) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_0 . #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_BB_SHIFT 7 #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_K2 (0x1<<9) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_0 . @@ -38518,8 +41726,6 @@ #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_SHIFT 30 #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2 (0x1<<27) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT 27 - #define IGU_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB (0x1<<5) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . - #define IGU_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_SHIFT 5 #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB (0x1<<12) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_SHIFT 12 #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB (0x1<<16) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 . @@ -38536,17 +41742,24 @@ #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_0_BB_SHIFT 24 #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_1_BB (0x1<<25) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY_1 . #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_1_BB_SHIFT 25 -#define IGU_REG_MEM_ECC_ENABLE_0_BB 0x180220UL //Access:RW DataWidth:0x1 // Enable ECC for memory ecc instance igu.IGU_MSIX_288_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_288_sb_mem -#define IGU_REG_MEM_ECC_ENABLE_0_K2_E5 0x180210UL //Access:RW DataWidth:0x1 // Enable ECC for memory ecc instance igu.i_igu_msix_mem.i_ecc in module igu_msix_512_sb_mem -#define IGU_REG_MEM_ECC_PARITY_ONLY_0_BB 0x180224UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc instance igu.IGU_MSIX_288_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_288_sb_mem -#define IGU_REG_MEM_ECC_PARITY_ONLY_0_K2_E5 0x180214UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc instance igu.i_igu_msix_mem.i_ecc in module igu_msix_512_sb_mem #define IGU_REG_PRTY_MASK_H_1_BB 0x180214UL //Access:RW DataWidth:0x1 // Multi Field Register. +#define IGU_REG_PRTY_MASK_H_1_E5 0x180214UL //Access:RW DataWidth:0x1 // Multi Field Register. + #define IGU_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_3_E5 (0x1<<0) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY_3 . + #define IGU_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_3_E5_SHIFT 0 #define IGU_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB (0x1<<0) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY . #define IGU_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_SHIFT 0 +#define IGU_REG_MEM_ECC_ENABLE_0_BB 0x180220UL //Access:RW DataWidth:0x1 // Enable ECC for memory ecc instance igu.IGU_MSIX_288_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_288_sb_mem +#define IGU_REG_MEM_ECC_ENABLE_0_K2 0x180210UL //Access:RW DataWidth:0x1 // Enable ECC for memory ecc instance igu.IGU_MSIX_368_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_368_sb_mem +#define IGU_REG_MEM_ECC_ENABLE_0_E5 0x180220UL //Access:RW DataWidth:0x1 // Enable ECC for memory ecc instance igu.i_igu_msix_mem.i_ecc in module igu_msix_512_sb_mem +#define IGU_REG_MEM_ECC_PARITY_ONLY_0_BB 0x180224UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc instance igu.IGU_MSIX_288_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_288_sb_mem +#define IGU_REG_MEM_ECC_PARITY_ONLY_0_K2 0x180214UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc instance igu.IGU_MSIX_368_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_368_sb_mem +#define IGU_REG_MEM_ECC_PARITY_ONLY_0_E5 0x180224UL //Access:RW DataWidth:0x1 // Set parity only for memory ecc instance igu.i_igu_msix_mem.i_ecc in module igu_msix_512_sb_mem #define IGU_REG_MEM_ECC_ERROR_CORRECTED_0_BB 0x180228UL //Access:RC DataWidth:0x1 // Record if a correctable error occurred on memory ecc instance igu.IGU_MSIX_288_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_288_sb_mem -#define IGU_REG_MEM_ECC_ERROR_CORRECTED_0_K2_E5 0x180218UL //Access:RC DataWidth:0x1 // Record if a correctable error occurred on memory ecc instance igu.i_igu_msix_mem.i_ecc in module igu_msix_512_sb_mem +#define IGU_REG_MEM_ECC_ERROR_CORRECTED_0_K2 0x180218UL //Access:RC DataWidth:0x1 // Record if a correctable error occurred on memory ecc instance igu.IGU_MSIX_368_SB_IF.i_igu_msix_mem.i_ecc in module igu_msix_368_sb_mem +#define IGU_REG_MEM_ECC_ERROR_CORRECTED_0_E5 0x180228UL //Access:RC DataWidth:0x1 // Record if a correctable error occurred on memory ecc instance igu.i_igu_msix_mem.i_ecc in module igu_msix_512_sb_mem #define IGU_REG_MEM_ECC_EVENTS_BB 0x18022cUL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. -#define IGU_REG_MEM_ECC_EVENTS_K2_E5 0x18021cUL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. +#define IGU_REG_MEM_ECC_EVENTS_K2 0x18021cUL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. +#define IGU_REG_MEM_ECC_EVENTS_E5 0x18022cUL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. #define IGU_REG_STATISTIC_NUM_PF_MSG_SENT 0x180400UL //Access:RW DataWidth:0x14 // Debug: Number of MSI/MSIX/ATTN messages sent for the PF: address 0 - number of MSI/MSIX messages; address 1 - number of ATTN messages. #define IGU_REG_STATISTIC_NUM_PF_MSG_SENT_SIZE 2 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT 0x180408UL //Access:RW DataWidth:0x14 // Debug: Number of MSI/MSIX messages sent for VF. @@ -39187,7 +42400,7 @@ #define CAU_REG_SB_TIMERS_MEMORY_SIZE_K2 368 #define CAU_REG_SB_TIMERS_MEMORY_SIZE_E5 512 #define PRS_REG_SOFT_RST 0x1f0000UL //Access:RW DataWidth:0x1 // Soft reset - reset all FSM. -#define PRS_REG_MAC_VLAN_CACHE_INIT 0x1f0004UL //Access:W DataWidth:0x1 // Any write to this register triggers MAC-VLAN Cache initialization. +#define PRS_REG_MAC_VLAN_CACHE_INIT 0x1f0004UL //Access:W DataWidth:0x1 // Any write to this register triggers MAC-VLAN Cache initialization. Initialization during traffic is not verified. #define PRS_REG_MAC_VLAN_CACHE_INIT_DONE 0x1f0008UL //Access:R DataWidth:0x1 // Set when the cache initialization is complete. #define PRS_REG_CAM_SCRUB_HIT_EN 0x1f000cUL //Access:RW DataWidth:0x1 // When set to 1 the cam hit parity scrubbing feature is enabled in the MAC/VLAN cache CAM. #define PRS_REG_CAM_SCRUB_MISS_EN 0x1f0010UL //Access:RW DataWidth:0x1 // When set to 1 the cam miss parity scrubbing feature is enabled in the MAC/VLAN cache CAM. @@ -39960,7 +43173,7 @@ #define PRS_REG_SRC_MAC_SELECT 0x1f0974UL //Access:RW DataWidth:0x3 // Selects whether to use the source MAC address of the first (0) or encapsulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN 2 - NGE #define PRS_REG_VLAN_TAG_SELECT 0x1f0978UL //Access:RW DataWidth:0x3 // Selects whether to use the 8021q tag of the first (0) or encapsulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN, 2 - NGE #define PRS_REG_MAC_VLAN_CACHE_USE_TENANT_ID 0x1f09bcUL //Access:RW DataWidth:0x6 // Per-PF: Indicates whether to include Tenant ID (if it exists) in the MAC VLAN Cache entry for each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 NGE, 5 - IP NGE -#define PRS_REG_MAC_VLAN_FLEX_UPPER 0x1f09c0UL //Access:RW DataWidth:0xe // Building block information used to build the MAC-VLAN Cache Flexible Field. If two blocks are used, this block is used for the upper bytes. 13:11 - number of bytes, 10:4 - byte offset, 3:0 - block id. +#define PRS_REG_MAC_VLAN_FLEX_UPPER 0x1f09c0UL //Access:RW DataWidth:0xf // Building block information used to build the MAC-VLAN Cache Flexible Field. If two blocks are used, this block is used for the upper bytes. 14:11 - number of bytes, 0 to 8. 10:4 - byte offset, 3:0 - block id. #define PRS_REG_MAC_VLAN_FLEX_LOWER 0x1f09c4UL //Access:RW DataWidth:0xb // Building block information used to build the MAC-VLAN Cache Flexible Field. This block is only used if the number of bytes in mac_vlan_flex_upper is less than 8. 10:4 - byte offset 3:0 - block id. #define PRS_REG_MAC_VLAN_FLEX_BITMASK_0 0x1f09c8UL //Access:RW DataWidth:0x20 // Used to bitmask the flexible field formed from the building block information in mac_vlan_flex_upper and/or mac_vlan_flex_lower. A zero in this register will mask the corresponding bit in the flexible field to 0. #define PRS_REG_MAC_VLAN_FLEX_BITMASK_1 0x1f09ccUL //Access:RW DataWidth:0x20 // Used to bitmask the flexible field formed from the building block information in mac_vlan_flex_upper and/or mac_vlan_flex_lower. A zero in this register will mask the corresponding bit in the flexible field to 0. @@ -40073,12 +43286,12 @@ #define PRS_REG_TCFC_SEARCH_CURRENT_CREDIT 0x1f0f14UL //Access:R DataWidth:0x8 // Debug only: TCFC search request current credit. Transaction based. This is a count of the requests that have not received an ACK. #define PRS_REG_CCFC_LOAD_CURRENT_CREDIT 0x1f0f18UL //Access:R DataWidth:0x1 // Debug only: CCFC load request current credit. Transaction based. Since the credit limit on this interface is 1, if this bit is high there is a request that has not received an ACK. #define PRS_REG_TCFC_LOAD_CURRENT_CREDIT 0x1f0f1cUL //Access:R DataWidth:0x1 // Debug only: TCFC load request current credit. Transaction based. Since the credit limit on this interface is 1, if this bit is high there is a request that has not received an ACK. -#define PRS_REG_CCFC_SEARCH_REQ_CT 0x1f0f20UL //Access:R DataWidth:0x5 // Debug only: The number of outstanding CCFC search requests. This is a count of the requests that have not received a response. -#define PRS_REG_TCFC_SEARCH_REQ_CT 0x1f0f24UL //Access:R DataWidth:0x5 // Debug only: The number of outstanding TCFC search requests This is a count of the requests that have not received a response. -#define PRS_REG_CCFC_LOAD_REQ_CT 0x1f0f28UL //Access:R DataWidth:0x5 // Debug only: The number of outstanding CCFC load requests -#define PRS_REG_TCFC_LOAD_REQ_CT 0x1f0f2cUL //Access:R DataWidth:0x5 // Debug only: The number of outstanding TCFC load requests +#define PRS_REG_CCFC_SEARCH_REQ_CT 0x1f0f20UL //Access:R DataWidth:0x8 // Debug only: The number of outstanding CCFC search requests. This is a count of the requests that have not received a response. +#define PRS_REG_TCFC_SEARCH_REQ_CT 0x1f0f24UL //Access:R DataWidth:0x8 // Debug only: The number of outstanding TCFC search requests This is a count of the requests that have not received a response. +#define PRS_REG_CCFC_LOAD_REQ_CT 0x1f0f28UL //Access:R DataWidth:0x8 // Debug only: The number of outstanding CCFC load requests +#define PRS_REG_TCFC_LOAD_REQ_CT 0x1f0f2cUL //Access:R DataWidth:0x8 // Debug only: The number of outstanding TCFC load requests #define PRS_REG_SOP_REQ_CT 0x1f0f30UL //Access:R DataWidth:0x3 // Debug only: Outstanding SOP request count. The value of the counter in the BRB Interface Unit that keeps track of the number of SOP requests sent to the BRB. -#define PRS_REG_EOP_REQ_CT 0x1f0f34UL //Access:R DataWidth:0x3 // Debug only (per-port): Outstanding EOP request count. The value of the counter in the BRB Interface Unit that keeps track of the number of EOP requests sent to the BRB. +#define PRS_REG_EOP_REQ_CT 0x1f0f34UL //Access:R DataWidth:0x3 // Debug only: Outstanding EOP request count. The value of the counter in the BRB Interface Unit that keeps track of the number of EOP requests sent to the BRB. #define PRS_REG_RGFS_INITIAL_CREDIT_E5 0x1f0f38UL //Access:RW DataWidth:0x8 // The initial credit in the packet start message to the RGFS interface. Credit is cycle based. #define PRS_REG_RGFS_CURRENT_CREDIT_E5 0x1f0f3cUL //Access:R DataWidth:0x8 // Debug only: RGFS current credit. Transaction based. This is a count of the requests that have not received an ACK. #define PRS_REG_FCE_FC_FIFO_INPUT_FIFO_ALMOST_FULL_TH_E5 0x1f0f40UL //Access:RW DataWidth:0x4 // @@ -41265,7 +44478,7 @@ #define PRM_REG_PRTY_MASK 0x230054UL //Access:RW DataWidth:0x1 // Multi Field Register. #define PRM_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS.DATAPATH_REGISTERS . #define PRM_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT 0 -#define PRM_REG_PRTY_MASK_H_0 0x230204UL //Access:RW DataWidth:0x18 // Multi Field Register. +#define PRM_REG_PRTY_MASK_H_0 0x230204UL //Access:RW DataWidth:0x1a // Multi Field Register. #define PRM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_K2_E5 (0x1<<0) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT . #define PRM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_K2_E5_SHIFT 0 #define PRM_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_BB (0x1<<0) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT . @@ -41276,18 +44489,14 @@ #define PRM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_BB_SHIFT 1 #define PRM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_K2_E5 (0x1<<2) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT . #define PRM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_K2_E5_SHIFT 2 - #define PRM_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_BB (0x1<<3) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM021_I_ECC_RF_INT . - #define PRM_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_BB_SHIFT 3 - #define PRM_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_E5 (0x1<<3) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM021_I_ECC_RF_INT . - #define PRM_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_E5_SHIFT 3 + #define PRM_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT_E5 (0x1<<3) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM024_I_ECC_RF_INT . + #define PRM_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT_E5_SHIFT 3 #define PRM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB (0x1<<13) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . #define PRM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_SHIFT 13 #define PRM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_E5 (0x1<<4) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . #define PRM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_E5_SHIFT 4 - #define PRM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB (0x1<<5) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . - #define PRM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_SHIFT 5 - #define PRM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . - #define PRM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5_SHIFT 5 + #define PRM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . + #define PRM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_E5_SHIFT 5 #define PRM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB (0x1<<7) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . #define PRM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_SHIFT 7 #define PRM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . @@ -41340,12 +44549,8 @@ #define PRM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_SHIFT 15 #define PRM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . #define PRM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5_SHIFT 16 - #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB (0x1<<16) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . - #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_SHIFT 16 - #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2 (0x1<<5) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . - #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_SHIFT 5 - #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . - #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5_SHIFT 17 + #define PRM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . + #define PRM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5_SHIFT 17 #define PRM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB (0x1<<15) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . #define PRM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT 15 #define PRM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2 (0x1<<17) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . @@ -41362,30 +44567,40 @@ #define PRM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT 19 #define PRM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY . #define PRM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5_SHIFT 20 - #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB (0x1<<21) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . - #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_SHIFT 21 - #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2 (0x1<<16) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . - #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT 16 - #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . - #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5_SHIFT 21 - #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB (0x1<<22) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . - #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_SHIFT 22 - #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2 (0x1<<20) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . - #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2_SHIFT 20 - #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . - #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5_SHIFT 22 + #define PRM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB (0x1<<5) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . + #define PRM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_SHIFT 5 + #define PRM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . + #define PRM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5_SHIFT 21 + #define PRM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_E5 (0x1<<22) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . + #define PRM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_E5_SHIFT 22 #define PRM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB (0x1<<23) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . #define PRM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_SHIFT 23 #define PRM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . #define PRM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5_SHIFT 23 - #define PRM_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_K2 (0x1<<3) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM020_I_ECC_RF_INT . - #define PRM_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_K2_SHIFT 3 #define PRM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2 (0x1<<21) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . #define PRM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT 21 - #define PRM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2 (0x1<<22) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . - #define PRM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT 22 + #define PRM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . + #define PRM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5_SHIFT 24 + #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB (0x1<<22) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . + #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_SHIFT 22 + #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2 (0x1<<20) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . + #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2_SHIFT 20 + #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . + #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5_SHIFT 25 + #define PRM_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_K2 (0x1<<3) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM020_I_ECC_RF_INT . + #define PRM_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_K2_SHIFT 3 + #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB (0x1<<16) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . + #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_SHIFT 16 + #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2 (0x1<<5) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . + #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_SHIFT 5 + #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB (0x1<<21) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . + #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_SHIFT 21 + #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2 (0x1<<16) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . + #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT 16 #define PRM_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_BB (0x1<<2) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT . #define PRM_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_BB_SHIFT 2 + #define PRM_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_BB (0x1<<3) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM021_I_ECC_RF_INT . + #define PRM_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_BB_SHIFT 3 #define PRM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB (0x1<<12) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . #define PRM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_SHIFT 12 #define PRM_REG_MEM012_RF_ECC_ERROR_CONNECT_K2_E5 0x230210UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. @@ -41405,14 +44620,14 @@ #define PRM_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_BB_SHIFT 1 #define PRM_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_K2_E5 (0x1<<2) // Enable ECC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_sector2_mem #define PRM_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_K2_E5_SHIFT 2 - #define PRM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_BB (0x1<<3) // Enable ECC for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram - #define PRM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_BB_SHIFT 3 - #define PRM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_E5 (0x1<<3) // Enable ECC for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram - #define PRM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_E5_SHIFT 3 + #define PRM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_EN_E5 (0x1<<3) // Enable ECC for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram + #define PRM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_EN_E5_SHIFT 3 #define PRM_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN_K2 (0x1<<3) // Enable ECC for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram #define PRM_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN_K2_SHIFT 3 #define PRM_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_BB (0x1<<2) // Enable ECC for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_sector2_mem #define PRM_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_BB_SHIFT 2 + #define PRM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_BB (0x1<<3) // Enable ECC for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram + #define PRM_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_BB_SHIFT 3 #define PRM_REG_MEM_ECC_PARITY_ONLY_0 0x230220UL //Access:RW DataWidth:0x4 // Multi Field Register. #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_K2_E5 (0x1<<0) // Set parity only for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_sector0_mem #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_K2_E5_SHIFT 0 @@ -41424,14 +44639,14 @@ #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_BB_SHIFT 1 #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_K2_E5 (0x1<<2) // Set parity only for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_sector2_mem #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_K2_E5_SHIFT 2 - #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_BB (0x1<<3) // Set parity only for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram - #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_BB_SHIFT 3 - #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram - #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_E5_SHIFT 3 + #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram + #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_PRTY_E5_SHIFT 3 #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY_K2 (0x1<<3) // Set parity only for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY_K2_SHIFT 3 #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_BB (0x1<<2) // Set parity only for memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_sector2_mem #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_BB_SHIFT 2 + #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_BB (0x1<<3) // Set parity only for memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram + #define PRM_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_BB_SHIFT 3 #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0 0x230224UL //Access:RC DataWidth:0x4 // Multi Field Register. #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_K2_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_ecc in module rdif_l1_sector0_mem #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_K2_E5_SHIFT 0 @@ -41443,14 +44658,14 @@ #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_BB_SHIFT 1 #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_K2_E5 (0x1<<2) // Record if a correctable error occurred on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_sector2_mem #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_K2_E5_SHIFT 2 - #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_BB (0x1<<3) // Record if a correctable error occurred on memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram - #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_BB_SHIFT 3 - #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_E5 (0x1<<3) // Record if a correctable error occurred on memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram - #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_E5_SHIFT 3 + #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_CORRECT_E5 (0x1<<3) // Record if a correctable error occurred on memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram + #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_CORRECT_E5_SHIFT 3 #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT_K2 (0x1<<3) // Record if a correctable error occurred on memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT_K2_SHIFT 3 #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_BB (0x1<<2) // Record if a correctable error occurred on memory ecc instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_ecc in module rdif_l1_sector2_mem #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_BB_SHIFT 2 + #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_BB (0x1<<3) // Record if a correctable error occurred on memory ecc instance prm.i_prm_rpb_l1_ram.i_ecc in module prm_rpb_l1_ram + #define PRM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_BB_SHIFT 3 #define PRM_REG_MEM_ECC_EVENTS 0x230228UL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. #define PRM_REG_TAG_SZ 0x230400UL //Access:RW DataWidth:0x4 // Array of registers provides a size (in units of two bytes) for each of the possible seven configurable L2 tags to remove, where the direct register index corresponds with the tag ID. The actual value to remove in bytes will be defined by the following: size (bytes) = (tag_sz+1)*2. Note: there is no tag_sz register for tag ID = 0x7 because this is the LLC/Snap tag ID and is not configurable. #define PRM_REG_TAG_SZ_SIZE 7 @@ -42112,7 +45327,7 @@ #define RPB_REG_DB_FIFO_SIZE 512 #define RPB_REG_L1 0x23f000UL //Access:WB DataWidth:0x40 // L1 CRC memory access. #define RPB_REG_L1_SIZE 640 -#define PSWRQ2_REG_RBC_DONE 0x240000UL //Access:RW DataWidth:0x1 // Driver should write 1 to this register in order to signal the PSWRQ block to start initializing internal memories. +#define PSWRQ2_REG_RBC_DONE 0x240000UL //Access:RW DataWidth:0x1 // Driver should write 1 to this register in order to signal the PSWRQ block to issue soft reset. #define PSWRQ2_REG_CFG_DONE 0x240004UL //Access:R DataWidth:0x1 // PSWRQ internal memories initialization is done. Driver should check this register is 1 some time after writing 1 to rbc_done register. #define PSWRQ2_REG_RESET_STT 0x240008UL //Access:RW DataWidth:0x1 // MCP writes '1' to this bit to indicate PSWRQ to initialize Steering Tag Table with zeros. PSWRQ clears this bit when the initialization is done. MCP can use this register the same as it uses IGU reset_memories register. #define PSWRQ2_REG_CDUT_P_SIZE 0x24000cUL //Access:RW DataWidth:0x4 // Page size in L2P table for CDU-Task module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M. @@ -42166,40 +45381,46 @@ #define PSWRQ2_REG_DBG_SHIFT 0x240108UL //Access:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) right shifting of the selected line (after the masking). #define PSWRQ2_REG_DBG_FORCE_VALID 0x24010cUL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line) / qword (256bit line) (before shift). #define PSWRQ2_REG_DBG_FORCE_FRAME 0x240110UL //Access:RW DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift). -#define PSWRQ2_REG_DBG_OUT_VALID 0x240114UL //Access:R DataWidth:0x4 // Dbgmux output valid -#define PSWRQ2_REG_DBG_OUT_FRAME 0x240118UL //Access:R DataWidth:0x4 // Dbgmux output frame -#define PSWRQ2_REG_INT_STS 0x240180UL //Access:R DataWidth:0xf // Multi Field Register. +#define PSWRQ2_REG_DBG_OUT_VALID 0x240114UL //Access:R DataWidth:0x8 // Dbgmux output valid per Dword +#define PSWRQ2_REG_DBG_OUT_FRAME 0x240118UL //Access:R DataWidth:0x8 // Dbgmux output frame per Dword +#define PSWRQ2_REG_INT_STS 0x240180UL //Access:R DataWidth:0x12 // Multi Field Register. #define PSWRQ2_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define PSWRQ2_REG_INT_STS_ADDRESS_ERROR_SHIFT 0 - #define PSWRQ2_REG_INT_STS_L2P_FIFO_OVERFLOW (0x1<<1) // Overflow in l2p input fifo - hard wired to 0 in E4. + #define PSWRQ2_REG_INT_STS_L2P_FIFO_OVERFLOW (0x1<<1) // Overflow in l2p input fifo - removed in E4. #define PSWRQ2_REG_INT_STS_L2P_FIFO_OVERFLOW_SHIFT 1 #define PSWRQ2_REG_INT_STS_WDFIFO_OVERFLOW (0x1<<2) // Overflow in src write done fifo. #define PSWRQ2_REG_INT_STS_WDFIFO_OVERFLOW_SHIFT 2 #define PSWRQ2_REG_INT_STS_PHYADDR_FIFO_OF (0x1<<3) // Overflow of phy addr fifo - removed in E4. #define PSWRQ2_REG_INT_STS_PHYADDR_FIFO_OF_SHIFT 3 - #define PSWRQ2_REG_INT_STS_L2P_VIOLATION_1 (0x1<<4) // Translation page pointer is bigger than 15 - hard wired to 0 in E4. + #define PSWRQ2_REG_INT_STS_L2P_VIOLATION_1 (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4. #define PSWRQ2_REG_INT_STS_L2P_VIOLATION_1_SHIFT 4 - #define PSWRQ2_REG_INT_STS_L2P_VIOLATION_2 (0x1<<5) // Vah+elt_first_index is bigger than page size - hard wired to 0 in E4. + #define PSWRQ2_REG_INT_STS_L2P_VIOLATION_2 (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4. #define PSWRQ2_REG_INT_STS_L2P_VIOLATION_2_SHIFT 5 - #define PSWRQ2_REG_INT_STS_FREE_LIST_EMPTY (0x1<<6) // If this interrupt occurs then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset. + #define PSWRQ2_REG_INT_STS_FREE_LIST_EMPTY (0x1<<6) // If this interrupt occurs then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5. #define PSWRQ2_REG_INT_STS_FREE_LIST_EMPTY_SHIFT 6 #define PSWRQ2_REG_INT_STS_ELT_ADDR (0x1<<7) // Indicates that onchip translation did not succeed in ILT mode (in ILT mode all onchip translation MUST succeed). #define PSWRQ2_REG_INT_STS_ELT_ADDR_SHIFT 7 #define PSWRQ2_REG_INT_STS_L2P_VF_ERR (0x1<<8) // E4: Indicates a request with: 1. Logical address. 2. Function is a VF. 3. Client is NOT (TM;CDU). #define PSWRQ2_REG_INT_STS_L2P_VF_ERR_SHIFT 8 - #define PSWRQ2_REG_INT_STS_CORE_WDONE_OVERFLOW (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue. + #define PSWRQ2_REG_INT_STS_CORE_WDONE_OVERFLOW (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5. #define PSWRQ2_REG_INT_STS_CORE_WDONE_OVERFLOW_SHIFT 9 - #define PSWRQ2_REG_INT_STS_TREQ_FIFO_UNDERFLOW (0x1<<10) // Underflwoing the treq fifo. + #define PSWRQ2_REG_INT_STS_TREQ_FIFO_UNDERFLOW (0x1<<10) // Underflwoing the treq fifo - removed in E5. #define PSWRQ2_REG_INT_STS_TREQ_FIFO_UNDERFLOW_SHIFT 10 - #define PSWRQ2_REG_INT_STS_TREQ_FIFO_OVERFLOW (0x1<<11) // Overflwoing the treq fifo. + #define PSWRQ2_REG_INT_STS_TREQ_FIFO_OVERFLOW (0x1<<11) // Overflwoing the treq fifo - removed in E5. #define PSWRQ2_REG_INT_STS_TREQ_FIFO_OVERFLOW_SHIFT 11 - #define PSWRQ2_REG_INT_STS_ICPL_FIFO_UNDERFLOW (0x1<<12) // Underflwoing the icpl fifo. + #define PSWRQ2_REG_INT_STS_ICPL_FIFO_UNDERFLOW (0x1<<12) // Underflwoing the icpl fifo - removed in E5. #define PSWRQ2_REG_INT_STS_ICPL_FIFO_UNDERFLOW_SHIFT 12 - #define PSWRQ2_REG_INT_STS_ICPL_FIFO_OVERFLOW (0x1<<13) // Overflwoing the icpl fifo. + #define PSWRQ2_REG_INT_STS_ICPL_FIFO_OVERFLOW (0x1<<13) // Overflwoing the icpl fifo - removed in E5. #define PSWRQ2_REG_INT_STS_ICPL_FIFO_OVERFLOW_SHIFT 13 - #define PSWRQ2_REG_INT_STS_BACK2BACK_ATC_RESPONSE (0x1<<14) // 2 consecutive atc responses are not allowed. + #define PSWRQ2_REG_INT_STS_BACK2BACK_ATC_RESPONSE (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5. #define PSWRQ2_REG_INT_STS_BACK2BACK_ATC_RESPONSE_SHIFT 14 -#define PSWRQ2_REG_INT_MASK 0x240184UL //Access:RW DataWidth:0xf // Multi Field Register. + #define PSWRQ2_REG_INT_STS_SHORT_WDONE_OVERFLOW_E5 (0x1<<15) // Overflow in the short wdone fifo. + #define PSWRQ2_REG_INT_STS_SHORT_WDONE_OVERFLOW_E5_SHIFT 15 + #define PSWRQ2_REG_INT_STS_SRSBMT_FIFO_OVERFLOW_E5 (0x1<<16) // Overflow in the SR submit fifo. + #define PSWRQ2_REG_INT_STS_SRSBMT_FIFO_OVERFLOW_E5_SHIFT 16 + #define PSWRQ2_REG_INT_STS_FORBIDDEN_VQID_E5 (0x1<<17) // Client issue request to a VQID which is not mapped to it + #define PSWRQ2_REG_INT_STS_FORBIDDEN_VQID_E5_SHIFT 17 +#define PSWRQ2_REG_INT_MASK 0x240184UL //Access:RW DataWidth:0x12 // Multi Field Register. #define PSWRQ2_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.ADDRESS_ERROR . #define PSWRQ2_REG_INT_MASK_ADDRESS_ERROR_SHIFT 0 #define PSWRQ2_REG_INT_MASK_L2P_FIFO_OVERFLOW (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.L2P_FIFO_OVERFLOW . @@ -42230,227 +45451,278 @@ #define PSWRQ2_REG_INT_MASK_ICPL_FIFO_OVERFLOW_SHIFT 13 #define PSWRQ2_REG_INT_MASK_BACK2BACK_ATC_RESPONSE (0x1<<14) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.BACK2BACK_ATC_RESPONSE . #define PSWRQ2_REG_INT_MASK_BACK2BACK_ATC_RESPONSE_SHIFT 14 -#define PSWRQ2_REG_INT_STS_WR 0x240188UL //Access:WR DataWidth:0xf // Multi Field Register. + #define PSWRQ2_REG_INT_MASK_SHORT_WDONE_OVERFLOW_E5 (0x1<<15) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.SHORT_WDONE_OVERFLOW . + #define PSWRQ2_REG_INT_MASK_SHORT_WDONE_OVERFLOW_E5_SHIFT 15 + #define PSWRQ2_REG_INT_MASK_SRSBMT_FIFO_OVERFLOW_E5 (0x1<<16) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.SRSBMT_FIFO_OVERFLOW . + #define PSWRQ2_REG_INT_MASK_SRSBMT_FIFO_OVERFLOW_E5_SHIFT 16 + #define PSWRQ2_REG_INT_MASK_FORBIDDEN_VQID_E5 (0x1<<17) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.FORBIDDEN_VQID . + #define PSWRQ2_REG_INT_MASK_FORBIDDEN_VQID_E5_SHIFT 17 +#define PSWRQ2_REG_INT_STS_WR 0x240188UL //Access:WR DataWidth:0x12 // Multi Field Register. #define PSWRQ2_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define PSWRQ2_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT 0 - #define PSWRQ2_REG_INT_STS_WR_L2P_FIFO_OVERFLOW (0x1<<1) // Overflow in l2p input fifo - hard wired to 0 in E4. + #define PSWRQ2_REG_INT_STS_WR_L2P_FIFO_OVERFLOW (0x1<<1) // Overflow in l2p input fifo - removed in E4. #define PSWRQ2_REG_INT_STS_WR_L2P_FIFO_OVERFLOW_SHIFT 1 #define PSWRQ2_REG_INT_STS_WR_WDFIFO_OVERFLOW (0x1<<2) // Overflow in src write done fifo. #define PSWRQ2_REG_INT_STS_WR_WDFIFO_OVERFLOW_SHIFT 2 #define PSWRQ2_REG_INT_STS_WR_PHYADDR_FIFO_OF (0x1<<3) // Overflow of phy addr fifo - removed in E4. #define PSWRQ2_REG_INT_STS_WR_PHYADDR_FIFO_OF_SHIFT 3 - #define PSWRQ2_REG_INT_STS_WR_L2P_VIOLATION_1 (0x1<<4) // Translation page pointer is bigger than 15 - hard wired to 0 in E4. + #define PSWRQ2_REG_INT_STS_WR_L2P_VIOLATION_1 (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4. #define PSWRQ2_REG_INT_STS_WR_L2P_VIOLATION_1_SHIFT 4 - #define PSWRQ2_REG_INT_STS_WR_L2P_VIOLATION_2 (0x1<<5) // Vah+elt_first_index is bigger than page size - hard wired to 0 in E4. + #define PSWRQ2_REG_INT_STS_WR_L2P_VIOLATION_2 (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4. #define PSWRQ2_REG_INT_STS_WR_L2P_VIOLATION_2_SHIFT 5 - #define PSWRQ2_REG_INT_STS_WR_FREE_LIST_EMPTY (0x1<<6) // If this interrupt occurs then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset. + #define PSWRQ2_REG_INT_STS_WR_FREE_LIST_EMPTY (0x1<<6) // If this interrupt occurs then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5. #define PSWRQ2_REG_INT_STS_WR_FREE_LIST_EMPTY_SHIFT 6 #define PSWRQ2_REG_INT_STS_WR_ELT_ADDR (0x1<<7) // Indicates that onchip translation did not succeed in ILT mode (in ILT mode all onchip translation MUST succeed). #define PSWRQ2_REG_INT_STS_WR_ELT_ADDR_SHIFT 7 #define PSWRQ2_REG_INT_STS_WR_L2P_VF_ERR (0x1<<8) // E4: Indicates a request with: 1. Logical address. 2. Function is a VF. 3. Client is NOT (TM;CDU). #define PSWRQ2_REG_INT_STS_WR_L2P_VF_ERR_SHIFT 8 - #define PSWRQ2_REG_INT_STS_WR_CORE_WDONE_OVERFLOW (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue. + #define PSWRQ2_REG_INT_STS_WR_CORE_WDONE_OVERFLOW (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5. #define PSWRQ2_REG_INT_STS_WR_CORE_WDONE_OVERFLOW_SHIFT 9 - #define PSWRQ2_REG_INT_STS_WR_TREQ_FIFO_UNDERFLOW (0x1<<10) // Underflwoing the treq fifo. + #define PSWRQ2_REG_INT_STS_WR_TREQ_FIFO_UNDERFLOW (0x1<<10) // Underflwoing the treq fifo - removed in E5. #define PSWRQ2_REG_INT_STS_WR_TREQ_FIFO_UNDERFLOW_SHIFT 10 - #define PSWRQ2_REG_INT_STS_WR_TREQ_FIFO_OVERFLOW (0x1<<11) // Overflwoing the treq fifo. + #define PSWRQ2_REG_INT_STS_WR_TREQ_FIFO_OVERFLOW (0x1<<11) // Overflwoing the treq fifo - removed in E5. #define PSWRQ2_REG_INT_STS_WR_TREQ_FIFO_OVERFLOW_SHIFT 11 - #define PSWRQ2_REG_INT_STS_WR_ICPL_FIFO_UNDERFLOW (0x1<<12) // Underflwoing the icpl fifo. + #define PSWRQ2_REG_INT_STS_WR_ICPL_FIFO_UNDERFLOW (0x1<<12) // Underflwoing the icpl fifo - removed in E5. #define PSWRQ2_REG_INT_STS_WR_ICPL_FIFO_UNDERFLOW_SHIFT 12 - #define PSWRQ2_REG_INT_STS_WR_ICPL_FIFO_OVERFLOW (0x1<<13) // Overflwoing the icpl fifo. + #define PSWRQ2_REG_INT_STS_WR_ICPL_FIFO_OVERFLOW (0x1<<13) // Overflwoing the icpl fifo - removed in E5. #define PSWRQ2_REG_INT_STS_WR_ICPL_FIFO_OVERFLOW_SHIFT 13 - #define PSWRQ2_REG_INT_STS_WR_BACK2BACK_ATC_RESPONSE (0x1<<14) // 2 consecutive atc responses are not allowed. + #define PSWRQ2_REG_INT_STS_WR_BACK2BACK_ATC_RESPONSE (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5. #define PSWRQ2_REG_INT_STS_WR_BACK2BACK_ATC_RESPONSE_SHIFT 14 -#define PSWRQ2_REG_INT_STS_CLR 0x24018cUL //Access:RC DataWidth:0xf // Multi Field Register. + #define PSWRQ2_REG_INT_STS_WR_SHORT_WDONE_OVERFLOW_E5 (0x1<<15) // Overflow in the short wdone fifo. + #define PSWRQ2_REG_INT_STS_WR_SHORT_WDONE_OVERFLOW_E5_SHIFT 15 + #define PSWRQ2_REG_INT_STS_WR_SRSBMT_FIFO_OVERFLOW_E5 (0x1<<16) // Overflow in the SR submit fifo. + #define PSWRQ2_REG_INT_STS_WR_SRSBMT_FIFO_OVERFLOW_E5_SHIFT 16 + #define PSWRQ2_REG_INT_STS_WR_FORBIDDEN_VQID_E5 (0x1<<17) // Client issue request to a VQID which is not mapped to it + #define PSWRQ2_REG_INT_STS_WR_FORBIDDEN_VQID_E5_SHIFT 17 +#define PSWRQ2_REG_INT_STS_CLR 0x24018cUL //Access:RC DataWidth:0x12 // Multi Field Register. #define PSWRQ2_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define PSWRQ2_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT 0 - #define PSWRQ2_REG_INT_STS_CLR_L2P_FIFO_OVERFLOW (0x1<<1) // Overflow in l2p input fifo - hard wired to 0 in E4. + #define PSWRQ2_REG_INT_STS_CLR_L2P_FIFO_OVERFLOW (0x1<<1) // Overflow in l2p input fifo - removed in E4. #define PSWRQ2_REG_INT_STS_CLR_L2P_FIFO_OVERFLOW_SHIFT 1 #define PSWRQ2_REG_INT_STS_CLR_WDFIFO_OVERFLOW (0x1<<2) // Overflow in src write done fifo. #define PSWRQ2_REG_INT_STS_CLR_WDFIFO_OVERFLOW_SHIFT 2 #define PSWRQ2_REG_INT_STS_CLR_PHYADDR_FIFO_OF (0x1<<3) // Overflow of phy addr fifo - removed in E4. #define PSWRQ2_REG_INT_STS_CLR_PHYADDR_FIFO_OF_SHIFT 3 - #define PSWRQ2_REG_INT_STS_CLR_L2P_VIOLATION_1 (0x1<<4) // Translation page pointer is bigger than 15 - hard wired to 0 in E4. + #define PSWRQ2_REG_INT_STS_CLR_L2P_VIOLATION_1 (0x1<<4) // Translation page pointer is bigger than 15 - removed in E4. #define PSWRQ2_REG_INT_STS_CLR_L2P_VIOLATION_1_SHIFT 4 - #define PSWRQ2_REG_INT_STS_CLR_L2P_VIOLATION_2 (0x1<<5) // Vah+elt_first_index is bigger than page size - hard wired to 0 in E4. + #define PSWRQ2_REG_INT_STS_CLR_L2P_VIOLATION_2 (0x1<<5) // Vah+elt_first_index is bigger than page size - removed in E4. #define PSWRQ2_REG_INT_STS_CLR_L2P_VIOLATION_2_SHIFT 5 - #define PSWRQ2_REG_INT_STS_CLR_FREE_LIST_EMPTY (0x1<<6) // If this interrupt occurs then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset. + #define PSWRQ2_REG_INT_STS_CLR_FREE_LIST_EMPTY (0x1<<6) // If this interrupt occurs then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset - removed in E5. #define PSWRQ2_REG_INT_STS_CLR_FREE_LIST_EMPTY_SHIFT 6 #define PSWRQ2_REG_INT_STS_CLR_ELT_ADDR (0x1<<7) // Indicates that onchip translation did not succeed in ILT mode (in ILT mode all onchip translation MUST succeed). #define PSWRQ2_REG_INT_STS_CLR_ELT_ADDR_SHIFT 7 #define PSWRQ2_REG_INT_STS_CLR_L2P_VF_ERR (0x1<<8) // E4: Indicates a request with: 1. Logical address. 2. Function is a VF. 3. Client is NOT (TM;CDU). #define PSWRQ2_REG_INT_STS_CLR_L2P_VF_ERR_SHIFT 8 - #define PSWRQ2_REG_INT_STS_CLR_CORE_WDONE_OVERFLOW (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue. + #define PSWRQ2_REG_INT_STS_CLR_CORE_WDONE_OVERFLOW (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue - removed in E5. #define PSWRQ2_REG_INT_STS_CLR_CORE_WDONE_OVERFLOW_SHIFT 9 - #define PSWRQ2_REG_INT_STS_CLR_TREQ_FIFO_UNDERFLOW (0x1<<10) // Underflwoing the treq fifo. + #define PSWRQ2_REG_INT_STS_CLR_TREQ_FIFO_UNDERFLOW (0x1<<10) // Underflwoing the treq fifo - removed in E5. #define PSWRQ2_REG_INT_STS_CLR_TREQ_FIFO_UNDERFLOW_SHIFT 10 - #define PSWRQ2_REG_INT_STS_CLR_TREQ_FIFO_OVERFLOW (0x1<<11) // Overflwoing the treq fifo. + #define PSWRQ2_REG_INT_STS_CLR_TREQ_FIFO_OVERFLOW (0x1<<11) // Overflwoing the treq fifo - removed in E5. #define PSWRQ2_REG_INT_STS_CLR_TREQ_FIFO_OVERFLOW_SHIFT 11 - #define PSWRQ2_REG_INT_STS_CLR_ICPL_FIFO_UNDERFLOW (0x1<<12) // Underflwoing the icpl fifo. + #define PSWRQ2_REG_INT_STS_CLR_ICPL_FIFO_UNDERFLOW (0x1<<12) // Underflwoing the icpl fifo - removed in E5. #define PSWRQ2_REG_INT_STS_CLR_ICPL_FIFO_UNDERFLOW_SHIFT 12 - #define PSWRQ2_REG_INT_STS_CLR_ICPL_FIFO_OVERFLOW (0x1<<13) // Overflwoing the icpl fifo. + #define PSWRQ2_REG_INT_STS_CLR_ICPL_FIFO_OVERFLOW (0x1<<13) // Overflwoing the icpl fifo - removed in E5. #define PSWRQ2_REG_INT_STS_CLR_ICPL_FIFO_OVERFLOW_SHIFT 13 - #define PSWRQ2_REG_INT_STS_CLR_BACK2BACK_ATC_RESPONSE (0x1<<14) // 2 consecutive atc responses are not allowed. + #define PSWRQ2_REG_INT_STS_CLR_BACK2BACK_ATC_RESPONSE (0x1<<14) // 2 consecutive atc responses are not allowed - removed in E5. #define PSWRQ2_REG_INT_STS_CLR_BACK2BACK_ATC_RESPONSE_SHIFT 14 -#define PSWRQ2_REG_PRTY_MASK_H_0 0x240204UL //Access:RW DataWidth:0xa // Multi Field Register. - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT . - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_SHIFT 0 - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_K2_E5 (0x1<<1) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT . - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_K2_E5_SHIFT 1 + #define PSWRQ2_REG_INT_STS_CLR_SHORT_WDONE_OVERFLOW_E5 (0x1<<15) // Overflow in the short wdone fifo. + #define PSWRQ2_REG_INT_STS_CLR_SHORT_WDONE_OVERFLOW_E5_SHIFT 15 + #define PSWRQ2_REG_INT_STS_CLR_SRSBMT_FIFO_OVERFLOW_E5 (0x1<<16) // Overflow in the SR submit fifo. + #define PSWRQ2_REG_INT_STS_CLR_SRSBMT_FIFO_OVERFLOW_E5_SHIFT 16 + #define PSWRQ2_REG_INT_STS_CLR_FORBIDDEN_VQID_E5 (0x1<<17) // Client issue request to a VQID which is not mapped to it + #define PSWRQ2_REG_INT_STS_CLR_FORBIDDEN_VQID_E5_SHIFT 17 +#define PSWRQ2_REG_PRTY_MASK_H_0 0x240204UL //Access:RW DataWidth:0x5 // Multi Field Register. #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB (0x1<<1) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT . #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_SHIFT 1 - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_K2_E5 (0x1<<2) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT . - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_K2_E5_SHIFT 2 + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_K2 (0x1<<2) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT . + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_K2_SHIFT 2 + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT . + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_E5_SHIFT 0 + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_E5 (0x1<<1) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT . + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_E5_SHIFT 1 + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_E5 (0x1<<2) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT . + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_E5_SHIFT 2 + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5_SHIFT 3 + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB (0x1<<2) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_SHIFT 2 + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5_SHIFT 4 + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT . + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_BB_K2_SHIFT 0 + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_K2 (0x1<<1) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT . + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_K2_SHIFT 1 #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB (0x1<<8) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT 8 - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_E5 (0x1<<3) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_E5_SHIFT 3 - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY . - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT 4 + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2 (0x1<<3) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT 3 + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2 (0x1<<4) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY . + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT 4 #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB (0x1<<7) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_SHIFT 7 - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_E5 (0x1<<5) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_E5_SHIFT 5 + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2 (0x1<<5) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_SHIFT 5 #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB (0x1<<5) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_SHIFT 5 - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_E5 (0x1<<6) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_E5_SHIFT 6 + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2 (0x1<<6) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_SHIFT 6 #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB (0x1<<6) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_SHIFT 6 - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_E5 (0x1<<7) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_E5_SHIFT 7 - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_E5 (0x1<<8) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY . - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_E5_SHIFT 8 + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2 (0x1<<7) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_SHIFT 7 + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2 (0x1<<8) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY . + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_SHIFT 8 #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB (0x1<<3) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_SHIFT 3 - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_E5 (0x1<<9) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_E5_SHIFT 9 - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB (0x1<<2) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . - #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_SHIFT 2 -#define PSWRQ2_REG_MEM004_RF_ECC_ERROR_CONNECT 0x240210UL //Access:W DataWidth:0xe // Register to generate up to two ECC errors on the next write to memory: pswrq.i_l2p_table.rf_ecc_error_connect Includes 2 words of 7 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 53. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define PSWRQ2_REG_MEM005_RF_ECC_ERROR_CONNECT_K2_E5 0x240214UL //Access:W DataWidth:0xe // Register to generate up to two ECC errors on the next write to memory: pswrq.i_l2p_table_high.rf_ecc_error_connect Includes 2 words of 7 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 53. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2 (0x1<<9) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . + #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_SHIFT 9 +#define PSWRQ2_REG_MEM001_RF_ECC_ERROR_CONNECT_E5 0x240210UL //Access:W DataWidth:0xe // Register to generate up to two ECC errors on the next write to memory: pswrq.i_l2p_table.rf_ecc_error_connect Includes 2 words of 7 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 53. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PSWRQ2_REG_MEM004_RF_ECC_ERROR_CONNECT_BB_K2 0x240210UL //Access:W DataWidth:0xe // Register to generate up to two ECC errors on the next write to memory: pswrq.i_l2p_table.rf_ecc_error_connect Includes 2 words of 7 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 53. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define PSWRQ2_REG_MEM_ECC_ENABLE_0_BB 0x240214UL //Access:RW DataWidth:0x2 // Multi Field Register. -#define PSWRQ2_REG_MEM_ECC_ENABLE_0_K2_E5 0x240218UL //Access:RW DataWidth:0x3 // Multi Field Register. - #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p_table - #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_SHIFT 0 - #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_K2_E5 (0x1<<1) // Enable ECC for memory ecc instance pswrq.i_l2p_table_high.i_ecc in module pswrq_mem_l2p_table - #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_K2_E5_SHIFT 1 +#define PSWRQ2_REG_MEM_ECC_ENABLE_0_K2 0x240218UL //Access:RW DataWidth:0x3 // Multi Field Register. +#define PSWRQ2_REG_MEM_ECC_ENABLE_0_E5 0x240214UL //Access:RW DataWidth:0x3 // Multi Field Register. #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB (0x1<<1) // Enable ECC for memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1 #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_BB_SHIFT 1 - #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_K2_E5 (0x1<<2) // Enable ECC for memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1 - #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_K2_E5_SHIFT 2 + #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_K2 (0x1<<2) // Enable ECC for memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1 + #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_K2_SHIFT 2 + #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p_table + #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_E5_SHIFT 0 + #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_E5 (0x1<<1) // Enable ECC for memory ecc instance pswrq.i_pswrq_mem_vqmem1.i_ecc in module pswrq_mem_vqmem1 + #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM002_I_ECC_EN_E5_SHIFT 1 + #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_E5 (0x1<<2) // Enable ECC for memory ecc instance pswrq.i_pswrq_mem_vqmem2.i_ecc in module pswrq_mem_vqmem2 + #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_E5_SHIFT 2 + #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_BB_K2 (0x1<<0) // Enable ECC for memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p_table + #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_BB_K2_SHIFT 0 + #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_K2 (0x1<<1) // Enable ECC for memory ecc instance pswrq.i_l2p_table_high.i_ecc in module pswrq_mem_l2p_table + #define PSWRQ2_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_EN_K2_SHIFT 1 +#define PSWRQ2_REG_MEM005_RF_ECC_ERROR_CONNECT_K2 0x240214UL //Access:W DataWidth:0xe // Register to generate up to two ECC errors on the next write to memory: pswrq.i_l2p_table_high.rf_ecc_error_connect Includes 2 words of 7 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 53. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_BB 0x240218UL //Access:RW DataWidth:0x2 // Multi Field Register. -#define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_K2_E5 0x24021cUL //Access:RW DataWidth:0x3 // Multi Field Register. - #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p_table - #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_SHIFT 0 - #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_K2_E5 (0x1<<1) // Set parity only for memory ecc instance pswrq.i_l2p_table_high.i_ecc in module pswrq_mem_l2p_table - #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_K2_E5_SHIFT 1 +#define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_K2 0x24021cUL //Access:RW DataWidth:0x3 // Multi Field Register. +#define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_E5 0x240218UL //Access:RW DataWidth:0x3 // Multi Field Register. #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB (0x1<<1) // Set parity only for memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1 #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_BB_SHIFT 1 - #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_K2_E5 (0x1<<2) // Set parity only for memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1 - #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_K2_E5_SHIFT 2 + #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_K2 (0x1<<2) // Set parity only for memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1 + #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_K2_SHIFT 2 + #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p_table + #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_E5_SHIFT 0 + #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for memory ecc instance pswrq.i_pswrq_mem_vqmem1.i_ecc in module pswrq_mem_vqmem1 + #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM002_I_ECC_PRTY_E5_SHIFT 1 + #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_E5 (0x1<<2) // Set parity only for memory ecc instance pswrq.i_pswrq_mem_vqmem2.i_ecc in module pswrq_mem_vqmem2 + #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_E5_SHIFT 2 + #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p_table + #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_BB_K2_SHIFT 0 + #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_K2 (0x1<<1) // Set parity only for memory ecc instance pswrq.i_l2p_table_high.i_ecc in module pswrq_mem_l2p_table + #define PSWRQ2_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_PRTY_K2_SHIFT 1 #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_BB 0x24021cUL //Access:RC DataWidth:0x2 // Multi Field Register. -#define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_K2_E5 0x240220UL //Access:RC DataWidth:0x3 // Multi Field Register. - #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p_table - #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_SHIFT 0 - #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_K2_E5 (0x1<<1) // Record if a correctable error occurred on memory ecc instance pswrq.i_l2p_table_high.i_ecc in module pswrq_mem_l2p_table - #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_K2_E5_SHIFT 1 +#define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_K2 0x240220UL //Access:RC DataWidth:0x3 // Multi Field Register. +#define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_E5 0x24021cUL //Access:RC DataWidth:0x3 // Multi Field Register. #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB (0x1<<1) // Record if a correctable error occurred on memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1 #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_BB_SHIFT 1 - #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_K2_E5 (0x1<<2) // Record if a correctable error occurred on memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1 - #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_K2_E5_SHIFT 2 + #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_K2 (0x1<<2) // Record if a correctable error occurred on memory ecc instance pswrq.i_cxr_ram1.i_ecc in module pswrq_mem_cxr_ram1 + #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_K2_SHIFT 2 + #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p_table + #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_E5_SHIFT 0 + #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_E5 (0x1<<1) // Record if a correctable error occurred on memory ecc instance pswrq.i_pswrq_mem_vqmem1.i_ecc in module pswrq_mem_vqmem1 + #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM002_I_ECC_CORRECT_E5_SHIFT 1 + #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_E5 (0x1<<2) // Record if a correctable error occurred on memory ecc instance pswrq.i_pswrq_mem_vqmem2.i_ecc in module pswrq_mem_vqmem2 + #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_E5_SHIFT 2 + #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_BB_K2 (0x1<<0) // Record if a correctable error occurred on memory ecc instance pswrq.i_l2p_table.i_ecc in module pswrq_mem_l2p_table + #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_BB_K2_SHIFT 0 + #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_K2 (0x1<<1) // Record if a correctable error occurred on memory ecc instance pswrq.i_l2p_table_high.i_ecc in module pswrq_mem_l2p_table + #define PSWRQ2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_CORRECT_K2_SHIFT 1 #define PSWRQ2_REG_MEM_ECC_EVENTS_BB 0x240220UL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. -#define PSWRQ2_REG_MEM_ECC_EVENTS_K2_E5 0x240224UL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. +#define PSWRQ2_REG_MEM_ECC_EVENTS_K2 0x240224UL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. +#define PSWRQ2_REG_MEM_ECC_EVENTS_E5 0x240220UL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. #define PSWRQ2_REG_WR_MBS0 0x240400UL //Access:RW DataWidth:0x3 // Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010: 512B;. #define PSWRQ2_REG_RD_MBS0 0x240404UL //Access:RW DataWidth:0x3 // Max burst size filed for read requests port 0; 000 - 128B; 001:256B; 010: 512B;011:1K:100:2K;101:4K. #define PSWRQ2_REG_CDU_ENDIAN_M 0x240408UL //Access:RW DataWidth:0x2 // Endian mode for cdu. #define PSWRQ2_REG_DISABLE_INPUTS 0x24040cUL //Access:RW DataWidth:0x1 // When '1'; requests will enter input buffers but wont get out towards the glue. #define PSWRQ2_REG_DRAM_ALIGN_WR 0x240410UL //Access:RW DataWidth:0x4 // Determines alignment of write SRs when a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B aligned. 4 - 512B aligned. #define PSWRQ2_REG_DRAM_ALIGN_RD 0x240414UL //Access:RW DataWidth:0x4 // Determines alignment of read SRs when a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B aligned. 4 - 512B aligned. -#define PSWRQ2_REG_USDM_ENTRY_TH 0x240418UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to usdm in the queues. -#define PSWRQ2_REG_PRM_ENTRY_TH 0x24041cUL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to prm in the queues. -#define PSWRQ2_REG_TSDM_ENTRY_TH 0x240420UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to tsdm in the queues. -#define PSWRQ2_REG_XSDM_ENTRY_TH 0x240424UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to xsdm in the queues. -#define PSWRQ2_REG_DMAE_ENTRY_TH 0x240428UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to rwh in the queues. -#define PSWRQ2_REG_CDUWR_ENTRY_TH 0x24042cUL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to cduwr in the queues. -#define PSWRQ2_REG_CDURD_ENTRY_TH 0x240430UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to cdurd in the queues. -#define PSWRQ2_REG_PBF_ENTRY_TH 0x240434UL //Access:RW DataWidth:0x7 // This number indicates how many entries are guaranteed to pbf in the queues. -#define PSWRQ2_REG_QM_ENTRY_TH 0x240438UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to qm in the queues. -#define PSWRQ2_REG_TM_ENTRY_TH 0x24043cUL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to tm in the queues. -#define PSWRQ2_REG_SRC_ENTRY_TH 0x240440UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to src in the queues. -#define PSWRQ2_REG_DBG_ENTRY_TH 0x240444UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to debug in the queues. -#define PSWRQ2_REG_HC_ENTRY_TH 0x240448UL //Access:RW DataWidth:0x2 // This number indicates how many entries are guaranteed to hc in the queues. -#define PSWRQ2_REG_GC_INIT_VAL 0x24044cUL //Access:RW DataWidth:0x8 // Initial value of global counter; This value MUST be 256 - sum of all clients thresholds. -#define PSWRQ2_REG_UFIFO 0x240450UL //Access:RW DataWidth:0x8 // Multi Field Register. - #define PSWRQ2_REG_UFIFO_UFIFO_LOW_TH (0xf<<0) // Low threshold of update fifo; not used. - #define PSWRQ2_REG_UFIFO_UFIFO_LOW_TH_SHIFT 0 - #define PSWRQ2_REG_UFIFO_UFIFO_HIGH_TH (0xf<<4) // High threshold of update fifo; not used. - #define PSWRQ2_REG_UFIFO_UFIFO_HIGH_TH_SHIFT 4 -#define PSWRQ2_REG_VQ0_ENTRY_CNT 0x240454UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 0 in pswrq memory. -#define PSWRQ2_REG_VQ1_ENTRY_CNT 0x240458UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 1 in pswrq memory. -#define PSWRQ2_REG_VQ2_ENTRY_CNT 0x24045cUL //Access:R DataWidth:0x8 // Number of entries occupied by vq 2 in pswrq memory. -#define PSWRQ2_REG_VQ3_ENTRY_CNT 0x240460UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 3 in pswrq memory. -#define PSWRQ2_REG_VQ4_ENTRY_CNT 0x240464UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 4 in pswrq memory. -#define PSWRQ2_REG_VQ5_ENTRY_CNT 0x240468UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 5 in pswrq memory. -#define PSWRQ2_REG_VQ6_ENTRY_CNT 0x24046cUL //Access:R DataWidth:0x8 // Number of entries occupied by vq 6 in pswrq memory. -#define PSWRQ2_REG_VQ7_ENTRY_CNT 0x240470UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 7 in pswrq memory. -#define PSWRQ2_REG_VQ8_ENTRY_CNT 0x240474UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 8 in pswrq memory. -#define PSWRQ2_REG_VQ9_ENTRY_CNT 0x240478UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 9 in pswrq memory. -#define PSWRQ2_REG_VQ10_ENTRY_CNT 0x24047cUL //Access:R DataWidth:0x8 // Number of entries occupied by vq 10 in pswrq memory. -#define PSWRQ2_REG_VQ11_ENTRY_CNT 0x240480UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 11 in pswrq memory. -#define PSWRQ2_REG_VQ12_ENTRY_CNT 0x240484UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 12 in pswrq memory. -#define PSWRQ2_REG_VQ13_ENTRY_CNT 0x240488UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 13 in pswrq memory. -#define PSWRQ2_REG_VQ14_ENTRY_CNT 0x24048cUL //Access:R DataWidth:0x8 // Number of entries occupied by vq 14 in pswrq memory. -#define PSWRQ2_REG_VQ15_ENTRY_CNT 0x240490UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 15 in pswrq memory. -#define PSWRQ2_REG_VQ16_ENTRY_CNT 0x240494UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 16 in pswrq memory. -#define PSWRQ2_REG_VQ17_ENTRY_CNT 0x240498UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 17 in pswrq memory. -#define PSWRQ2_REG_VQ18_ENTRY_CNT 0x24049cUL //Access:R DataWidth:0x8 // Number of entries occupied by vq 18 in pswrq memory. -#define PSWRQ2_REG_VQ19_ENTRY_CNT 0x2404a0UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 19 in pswrq memory. -#define PSWRQ2_REG_VQ20_ENTRY_CNT 0x2404a4UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 20 in pswrq memory. -#define PSWRQ2_REG_VQ21_ENTRY_CNT 0x2404a8UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 21 in pswrq memory. -#define PSWRQ2_REG_VQ22_ENTRY_CNT 0x2404acUL //Access:R DataWidth:0x8 // Number of entries occupied by vq 22 in pswrq memory. -#define PSWRQ2_REG_VQ23_ENTRY_CNT 0x2404b0UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 23 in pswrq memory. -#define PSWRQ2_REG_VQ24_ENTRY_CNT 0x2404b4UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 24 in pswrq memory. -#define PSWRQ2_REG_VQ25_ENTRY_CNT 0x2404b8UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 25 in pswrq memory. -#define PSWRQ2_REG_VQ26_ENTRY_CNT 0x2404bcUL //Access:R DataWidth:0x8 // Number of entries occupied by vq 26 in pswrq memory. -#define PSWRQ2_REG_VQ27_ENTRY_CNT 0x2404c0UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 27 in pswrq memory. -#define PSWRQ2_REG_VQ28_ENTRY_CNT 0x2404c4UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 28 in pswrq memory. -#define PSWRQ2_REG_VQ29_ENTRY_CNT 0x2404c8UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 29 in pswrq memory. -#define PSWRQ2_REG_VQ30_ENTRY_CNT 0x2404ccUL //Access:R DataWidth:0x8 // Number of entries occupied by vq 30 in pswrq memory. -#define PSWRQ2_REG_VQ31_ENTRY_CNT 0x2404d0UL //Access:R DataWidth:0x8 // Number of entries occupied by vq 31 in pswrq memory. -#define PSWRQ2_REG_VQ0_MAX_ENTRY_CNT 0x2404d4UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 0. -#define PSWRQ2_REG_VQ1_MAX_ENTRY_CNT 0x2404d8UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 1. -#define PSWRQ2_REG_VQ2_MAX_ENTRY_CNT 0x2404dcUL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 2. -#define PSWRQ2_REG_VQ3_MAX_ENTRY_CNT 0x2404e0UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 3. -#define PSWRQ2_REG_VQ4_MAX_ENTRY_CNT 0x2404e4UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 4. -#define PSWRQ2_REG_VQ5_MAX_ENTRY_CNT 0x2404e8UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 5. -#define PSWRQ2_REG_VQ6_MAX_ENTRY_CNT 0x2404ecUL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 6. -#define PSWRQ2_REG_VQ7_MAX_ENTRY_CNT 0x2404f0UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 7. -#define PSWRQ2_REG_VQ8_MAX_ENTRY_CNT 0x2404f4UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 8. -#define PSWRQ2_REG_VQ9_MAX_ENTRY_CNT 0x2404f8UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 9. -#define PSWRQ2_REG_VQ10_MAX_ENTRY_CNT 0x2404fcUL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 10. -#define PSWRQ2_REG_VQ11_MAX_ENTRY_CNT 0x240500UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 11. -#define PSWRQ2_REG_VQ12_MAX_ENTRY_CNT 0x240504UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 12. -#define PSWRQ2_REG_VQ13_MAX_ENTRY_CNT 0x240508UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 13. -#define PSWRQ2_REG_VQ14_MAX_ENTRY_CNT 0x24050cUL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 14. -#define PSWRQ2_REG_VQ15_MAX_ENTRY_CNT 0x240510UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 15. -#define PSWRQ2_REG_VQ16_MAX_ENTRY_CNT 0x240514UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 16. -#define PSWRQ2_REG_VQ17_MAX_ENTRY_CNT 0x240518UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 17. -#define PSWRQ2_REG_VQ18_MAX_ENTRY_CNT 0x24051cUL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 18. -#define PSWRQ2_REG_VQ19_MAX_ENTRY_CNT 0x240520UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 19. -#define PSWRQ2_REG_VQ20_MAX_ENTRY_CNT 0x240524UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 20. -#define PSWRQ2_REG_VQ21_MAX_ENTRY_CNT 0x240528UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 21. -#define PSWRQ2_REG_VQ22_MAX_ENTRY_CNT 0x24052cUL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 22. -#define PSWRQ2_REG_VQ23_MAX_ENTRY_CNT 0x240530UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 23. -#define PSWRQ2_REG_VQ24_MAX_ENTRY_CNT 0x240534UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 24. -#define PSWRQ2_REG_VQ25_MAX_ENTRY_CNT 0x240538UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 25. -#define PSWRQ2_REG_VQ26_MAX_ENTRY_CNT 0x24053cUL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 26. -#define PSWRQ2_REG_VQ27_MAX_ENTRY_CNT 0x240540UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 27. -#define PSWRQ2_REG_VQ28_MAX_ENTRY_CNT 0x240544UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 28. -#define PSWRQ2_REG_VQ29_MAX_ENTRY_CNT 0x240548UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 29. -#define PSWRQ2_REG_VQ30_MAX_ENTRY_CNT 0x24054cUL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 30. -#define PSWRQ2_REG_VQ31_MAX_ENTRY_CNT 0x240550UL //Access:R DataWidth:0x8 // Maximum Number of entries occupied by vq 31. -#define PSWRQ2_REG_UFIFO_NUM_OF_ENTRY 0x240554UL //Access:R DataWidth:0x5 // Number of entries in the ufifo;This fifo has l2p completions. +#define PSWRQ2_REG_USDM_ENTRY_TH_BB_K2 0x240418UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to usdm in the queues. +#define PSWRQ2_REG_PRM_ENTRY_TH_BB_K2 0x24041cUL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to prm in the queues. +#define PSWRQ2_REG_TSDM_ENTRY_TH_BB_K2 0x240420UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to tsdm in the queues. +#define PSWRQ2_REG_XSDM_ENTRY_TH_BB_K2 0x240424UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to xsdm in the queues. +#define PSWRQ2_REG_DMAE_ENTRY_TH_BB_K2 0x240428UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to rwh in the queues. +#define PSWRQ2_REG_CDUWR_ENTRY_TH_BB_K2 0x24042cUL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to cduwr in the queues. +#define PSWRQ2_REG_CDURD_ENTRY_TH_BB_K2 0x240430UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to cdurd in the queues. +#define PSWRQ2_REG_PBF_ENTRY_TH_BB_K2 0x240434UL //Access:RW DataWidth:0x7 // This number indicates how many entries are guaranteed to pbf in the queues. +#define PSWRQ2_REG_QM_ENTRY_TH_BB_K2 0x240438UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to qm in the queues. +#define PSWRQ2_REG_TM_ENTRY_TH_BB_K2 0x24043cUL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to tm in the queues. +#define PSWRQ2_REG_SRC_ENTRY_TH_BB_K2 0x240440UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to src in the queues. +#define PSWRQ2_REG_DBG_ENTRY_TH_BB_K2 0x240444UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to debug in the queues. +#define PSWRQ2_REG_HC_ENTRY_TH_BB_K2 0x240448UL //Access:RW DataWidth:0x2 // This number indicates how many entries are guaranteed to hc in the queues. +#define PSWRQ2_REG_GC_INIT_VAL_BB_K2 0x24044cUL //Access:RW DataWidth:0x8 // Initial value of global counter; This value MUST be 256 - sum of all clients thresholds. +#define PSWRQ2_REG_UFIFO_BB_K2 0x240450UL //Access:RW DataWidth:0x8 // Multi Field Register. + #define PSWRQ2_REG_UFIFO_UFIFO_LOW_TH_BB_K2 (0xf<<0) // Low threshold of update fifo; not used. + #define PSWRQ2_REG_UFIFO_UFIFO_LOW_TH_BB_K2_SHIFT 0 + #define PSWRQ2_REG_UFIFO_UFIFO_HIGH_TH_BB_K2 (0xf<<4) // High threshold of update fifo; not used. + #define PSWRQ2_REG_UFIFO_UFIFO_HIGH_TH_BB_K2_SHIFT 4 +#define PSWRQ2_REG_VQ0_ENTRY_CNT 0x240454UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 0 in pswrq memory. +#define PSWRQ2_REG_VQ1_ENTRY_CNT 0x240458UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 1 in pswrq memory. +#define PSWRQ2_REG_VQ2_ENTRY_CNT 0x24045cUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 2 in pswrq memory. +#define PSWRQ2_REG_VQ3_ENTRY_CNT 0x240460UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 3 in pswrq memory. +#define PSWRQ2_REG_VQ4_ENTRY_CNT 0x240464UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 4 in pswrq memory. +#define PSWRQ2_REG_VQ5_ENTRY_CNT 0x240468UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 5 in pswrq memory. +#define PSWRQ2_REG_VQ6_ENTRY_CNT 0x24046cUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 6 in pswrq memory. +#define PSWRQ2_REG_VQ7_ENTRY_CNT 0x240470UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 7 in pswrq memory. +#define PSWRQ2_REG_VQ8_ENTRY_CNT 0x240474UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 8 in pswrq memory. +#define PSWRQ2_REG_VQ9_ENTRY_CNT 0x240478UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 9 in pswrq memory. +#define PSWRQ2_REG_VQ10_ENTRY_CNT 0x24047cUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 10 in pswrq memory. +#define PSWRQ2_REG_VQ11_ENTRY_CNT 0x240480UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 11 in pswrq memory. +#define PSWRQ2_REG_VQ12_ENTRY_CNT 0x240484UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 12 in pswrq memory. +#define PSWRQ2_REG_VQ13_ENTRY_CNT 0x240488UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 13 in pswrq memory. +#define PSWRQ2_REG_VQ14_ENTRY_CNT 0x24048cUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 14 in pswrq memory. +#define PSWRQ2_REG_VQ15_ENTRY_CNT 0x240490UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 15 in pswrq memory. +#define PSWRQ2_REG_VQ16_ENTRY_CNT 0x240494UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 16 in pswrq memory. +#define PSWRQ2_REG_VQ17_ENTRY_CNT 0x240498UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 17 in pswrq memory. +#define PSWRQ2_REG_VQ18_ENTRY_CNT 0x24049cUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 18 in pswrq memory. +#define PSWRQ2_REG_VQ19_ENTRY_CNT 0x2404a0UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 19 in pswrq memory. +#define PSWRQ2_REG_VQ20_ENTRY_CNT 0x2404a4UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 20 in pswrq memory. +#define PSWRQ2_REG_VQ21_ENTRY_CNT 0x2404a8UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 21 in pswrq memory. +#define PSWRQ2_REG_VQ22_ENTRY_CNT 0x2404acUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 22 in pswrq memory. +#define PSWRQ2_REG_VQ23_ENTRY_CNT 0x2404b0UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 23 in pswrq memory. +#define PSWRQ2_REG_VQ24_ENTRY_CNT 0x2404b4UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 24 in pswrq memory. +#define PSWRQ2_REG_VQ25_ENTRY_CNT 0x2404b8UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 25 in pswrq memory. +#define PSWRQ2_REG_VQ26_ENTRY_CNT 0x2404bcUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 26 in pswrq memory. +#define PSWRQ2_REG_VQ27_ENTRY_CNT 0x2404c0UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 27 in pswrq memory. +#define PSWRQ2_REG_VQ28_ENTRY_CNT 0x2404c4UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 28 in pswrq memory. +#define PSWRQ2_REG_VQ29_ENTRY_CNT 0x2404c8UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 29 in pswrq memory. +#define PSWRQ2_REG_VQ30_ENTRY_CNT 0x2404ccUL //Access:R DataWidth:0x9 // Number of entries occupied by vq 30 in pswrq memory. +#define PSWRQ2_REG_VQ31_ENTRY_CNT 0x2404d0UL //Access:R DataWidth:0x9 // Number of entries occupied by vq 31 in pswrq memory. +#define PSWRQ2_REG_VQ0_MAX_ENTRY_CNT 0x2404d4UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 0. +#define PSWRQ2_REG_VQ1_MAX_ENTRY_CNT 0x2404d8UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 1. +#define PSWRQ2_REG_VQ2_MAX_ENTRY_CNT 0x2404dcUL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 2. +#define PSWRQ2_REG_VQ3_MAX_ENTRY_CNT 0x2404e0UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 3. +#define PSWRQ2_REG_VQ4_MAX_ENTRY_CNT 0x2404e4UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 4. +#define PSWRQ2_REG_VQ5_MAX_ENTRY_CNT 0x2404e8UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 5. +#define PSWRQ2_REG_VQ6_MAX_ENTRY_CNT 0x2404ecUL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 6. +#define PSWRQ2_REG_VQ7_MAX_ENTRY_CNT 0x2404f0UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 7. +#define PSWRQ2_REG_VQ8_MAX_ENTRY_CNT 0x2404f4UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 8. +#define PSWRQ2_REG_VQ9_MAX_ENTRY_CNT 0x2404f8UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 9. +#define PSWRQ2_REG_VQ10_MAX_ENTRY_CNT 0x2404fcUL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 10. +#define PSWRQ2_REG_VQ11_MAX_ENTRY_CNT 0x240500UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 11. +#define PSWRQ2_REG_VQ12_MAX_ENTRY_CNT 0x240504UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 12. +#define PSWRQ2_REG_VQ13_MAX_ENTRY_CNT 0x240508UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 13. +#define PSWRQ2_REG_VQ14_MAX_ENTRY_CNT 0x24050cUL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 14. +#define PSWRQ2_REG_VQ15_MAX_ENTRY_CNT 0x240510UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 15. +#define PSWRQ2_REG_VQ16_MAX_ENTRY_CNT 0x240514UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 16. +#define PSWRQ2_REG_VQ17_MAX_ENTRY_CNT 0x240518UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 17. +#define PSWRQ2_REG_VQ18_MAX_ENTRY_CNT 0x24051cUL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 18. +#define PSWRQ2_REG_VQ19_MAX_ENTRY_CNT 0x240520UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 19. +#define PSWRQ2_REG_VQ20_MAX_ENTRY_CNT 0x240524UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 20. +#define PSWRQ2_REG_VQ21_MAX_ENTRY_CNT 0x240528UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 21. +#define PSWRQ2_REG_VQ22_MAX_ENTRY_CNT 0x24052cUL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 22. +#define PSWRQ2_REG_VQ23_MAX_ENTRY_CNT 0x240530UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 23. +#define PSWRQ2_REG_VQ24_MAX_ENTRY_CNT 0x240534UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 24. +#define PSWRQ2_REG_VQ25_MAX_ENTRY_CNT 0x240538UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 25. +#define PSWRQ2_REG_VQ26_MAX_ENTRY_CNT 0x24053cUL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 26. +#define PSWRQ2_REG_VQ27_MAX_ENTRY_CNT 0x240540UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 27. +#define PSWRQ2_REG_VQ28_MAX_ENTRY_CNT 0x240544UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 28. +#define PSWRQ2_REG_VQ29_MAX_ENTRY_CNT 0x240548UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 29. +#define PSWRQ2_REG_VQ30_MAX_ENTRY_CNT 0x24054cUL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 30. +#define PSWRQ2_REG_VQ31_MAX_ENTRY_CNT 0x240550UL //Access:R DataWidth:0x9 // Maximum Number of entries occupied by vq 31. +#define PSWRQ2_REG_UFIFO_NUM_OF_ENTRY_BB_K2 0x240554UL //Access:R DataWidth:0x5 // Number of entries in the ufifo;This fifo has l2p completions. #define PSWRQ2_REG_QM_PCI_ATTR 0x240558UL //Access:RW DataWidth:0x2 // Multi Field Register. #define PSWRQ2_REG_QM_PCI_ATTR_QM_RELAXED (0x1<<0) // Relaxed oredering attribute for qm. #define PSWRQ2_REG_QM_PCI_ATTR_QM_RELAXED_SHIFT 0 @@ -42492,7 +45764,8 @@ #define PSWRQ2_REG_DBG_ENDIAN_M 0x240580UL //Access:RW DataWidth:0x2 // Endian mode for debug. #define PSWRQ2_REG_PBF_ENDIAN_M 0x240584UL //Access:RW DataWidth:0x2 // Endian mode for pbf. #define PSWRQ2_REG_DONE_FIFO_TH 0x240588UL //Access:RW DataWidth:0x5 // Write Done fifo threshold; this fifo has write done indications;this threshold would not be reached unless there is a bug. -#define PSWRQ2_REG_BW_RD_ADD0 0x24058cUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ0 write requests. +#define PSWRQ2_REG_BW_ADD0_E5 0x24058cUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ0 read requests. +#define PSWRQ2_REG_BW_RD_ADD0_BB_K2 0x24058cUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ0 write requests. #define PSWRQ2_REG_BW_ADD1 0x240590UL //Access:RW DataWidth:0x14 // Multi Field Register. #define PSWRQ2_REG_BW_ADD1_BW_RD_ADD1 (0x3ff<<0) // Bandwidth addition to VQ1 read requests. #define PSWRQ2_REG_BW_ADD1_BW_RD_ADD1_SHIFT 0 @@ -42508,8 +45781,10 @@ #define PSWRQ2_REG_BW_ADD3_BW_RD_ADD3_SHIFT 0 #define PSWRQ2_REG_BW_ADD3_BW_WR_ADD3 (0x3ff<<10) // Bandwidth addition to VQ3 write requests. #define PSWRQ2_REG_BW_ADD3_BW_WR_ADD3_SHIFT 10 -#define PSWRQ2_REG_BW_RD_ADD4 0x24059cUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ4 read requests. -#define PSWRQ2_REG_BW_RD_ADD5 0x2405a0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ5 read requests. +#define PSWRQ2_REG_BW_ADD4_E5 0x24059cUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ4 read requests. +#define PSWRQ2_REG_BW_RD_ADD4_BB_K2 0x24059cUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ4 read requests. +#define PSWRQ2_REG_BW_ADD5_E5 0x2405a0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ5 read requests. +#define PSWRQ2_REG_BW_RD_ADD5_BB_K2 0x2405a0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ5 read requests. #define PSWRQ2_REG_BW_ADD6 0x2405a4UL //Access:RW DataWidth:0x14 // Multi Field Register. #define PSWRQ2_REG_BW_ADD6_BW_RD_ADD6 (0x3ff<<0) // Bandwidth addition to VQ6 read requests. #define PSWRQ2_REG_BW_ADD6_BW_RD_ADD6_SHIFT 0 @@ -42540,39 +45815,65 @@ #define PSWRQ2_REG_BW_ADD11_BW_RD_ADD11_SHIFT 0 #define PSWRQ2_REG_BW_ADD11_BW_WR_ADD11 (0x3ff<<10) // Bandwidth addition to VQ11 write requests. #define PSWRQ2_REG_BW_ADD11_BW_WR_ADD11_SHIFT 10 -#define PSWRQ2_REG_BW_RD_ADD12 0x2405bcUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ12 read requests. -#define PSWRQ2_REG_BW_RD_ADD13 0x2405c0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ13 read requests. +#define PSWRQ2_REG_BW_ADD12_E5 0x2405bcUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ12 read requests. +#define PSWRQ2_REG_BW_RD_ADD12_BB_K2 0x2405bcUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ12 read requests. +#define PSWRQ2_REG_BW_ADD13_E5 0x2405c0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ13 read requests. +#define PSWRQ2_REG_BW_RD_ADD13_BB_K2 0x2405c0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ13 read requests. #define PSWRQ2_REG_BW_ADD14 0x2405c4UL //Access:RW DataWidth:0x14 // Multi Field Register. #define PSWRQ2_REG_BW_ADD14_BW_RD_ADD14 (0x3ff<<0) // Bandwidth addition to VQ14 read requests. #define PSWRQ2_REG_BW_ADD14_BW_RD_ADD14_SHIFT 0 #define PSWRQ2_REG_BW_ADD14_BW_WR_ADD14 (0x3ff<<10) // Bandwidth addition to VQ14 write requests. #define PSWRQ2_REG_BW_ADD14_BW_WR_ADD14_SHIFT 10 -#define PSWRQ2_REG_BW_RD_ADD15 0x2405c8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ15 read requests. -#define PSWRQ2_REG_BW_RD_ADD16 0x2405ccUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ16 read requests. -#define PSWRQ2_REG_BW_RD_ADD17 0x2405d0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ17 read requests. -#define PSWRQ2_REG_BW_RD_ADD18 0x2405d4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ18 read requests. -#define PSWRQ2_REG_BW_RD_ADD19 0x2405d8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ19 read requests. -#define PSWRQ2_REG_BW_RD_ADD20 0x2405dcUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ20 read requests. -#define PSWRQ2_REG_BW_WR_ADD21 0x2405e0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ21 write requests. -#define PSWRQ2_REG_BW_RD_ADD22 0x2405e4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ22 read requests. -#define PSWRQ2_REG_BW_RD_ADD23 0x2405e8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ23 read requests. -#define PSWRQ2_REG_BW_RD_ADD24 0x2405ecUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ24 read requests. -#define PSWRQ2_REG_BW_RD_ADD25 0x2405f0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ25 read requests. -#define PSWRQ2_REG_BW_RD_ADD26 0x2405f4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ26 read requests. -#define PSWRQ2_REG_BW_RD_ADD27 0x2405f8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ27 read requests. +#define PSWRQ2_REG_BW_ADD15_E5 0x2405c8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ15 read requests. +#define PSWRQ2_REG_BW_RD_ADD15_BB_K2 0x2405c8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ15 read requests. +#define PSWRQ2_REG_BW_ADD16_E5 0x2405ccUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ16 read requests. +#define PSWRQ2_REG_BW_RD_ADD16_BB_K2 0x2405ccUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ16 read requests. +#define PSWRQ2_REG_BW_ADD17_E5 0x2405d0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ17 read requests. +#define PSWRQ2_REG_BW_RD_ADD17_BB_K2 0x2405d0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ17 read requests. +#define PSWRQ2_REG_BW_ADD18_E5 0x2405d4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ18 read requests. +#define PSWRQ2_REG_BW_RD_ADD18_BB_K2 0x2405d4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ18 read requests. +#define PSWRQ2_REG_BW_ADD19_E5 0x2405d8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ19 read requests. +#define PSWRQ2_REG_BW_RD_ADD19_BB_K2 0x2405d8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ19 read requests. +#define PSWRQ2_REG_BW_ADD20_E5 0x2405dcUL //Access:RW DataWidth:0x14 // Multi Field Register. + #define PSWRQ2_REG_BW_ADD20_BW_RD_ADD20_E5 (0x3ff<<0) // Bandwidth addition to VQ20 read requests. + #define PSWRQ2_REG_BW_ADD20_BW_RD_ADD20_E5_SHIFT 0 + #define PSWRQ2_REG_BW_ADD20_BW_WR_ADD20_E5 (0x3ff<<10) // Bandwidth addition to VQ20 write requests. + #define PSWRQ2_REG_BW_ADD20_BW_WR_ADD20_E5_SHIFT 10 +#define PSWRQ2_REG_BW_RD_ADD20_BB_K2 0x2405dcUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ20 read requests. +#define PSWRQ2_REG_BW_ADD21_E5 0x2405e0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ21 write requests. +#define PSWRQ2_REG_BW_WR_ADD21_BB_K2 0x2405e0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ21 write requests. +#define PSWRQ2_REG_BW_ADD22_E5 0x2405e4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ22 read requests. +#define PSWRQ2_REG_BW_RD_ADD22_BB_K2 0x2405e4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ22 read requests. +#define PSWRQ2_REG_BW_ADD23_E5 0x2405e8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ23 read requests. +#define PSWRQ2_REG_BW_RD_ADD23_BB_K2 0x2405e8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ23 read requests. +#define PSWRQ2_REG_BW_ADD24_E5 0x2405ecUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ24 read requests. +#define PSWRQ2_REG_BW_RD_ADD24_BB_K2 0x2405ecUL //Access:RW DataWidth:0xa // Bandwidth addition to VQ24 read requests. +#define PSWRQ2_REG_BW_ADD25_E5 0x2405f0UL //Access:RW DataWidth:0x14 // Multi Field Register. + #define PSWRQ2_REG_BW_ADD25_BW_RD_ADD25_E5 (0x3ff<<0) // Bandwidth addition to VQ25 read requests. + #define PSWRQ2_REG_BW_ADD25_BW_RD_ADD25_E5_SHIFT 0 + #define PSWRQ2_REG_BW_ADD25_BW_WR_ADD25_E5 (0x3ff<<10) // Bandwidth addition to VQ25 write requests. + #define PSWRQ2_REG_BW_ADD25_BW_WR_ADD25_E5_SHIFT 10 +#define PSWRQ2_REG_BW_RD_ADD25_BB_K2 0x2405f0UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ25 read requests. +#define PSWRQ2_REG_BW_ADD26_E5 0x2405f4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ26 read requests. +#define PSWRQ2_REG_BW_RD_ADD26_BB_K2 0x2405f4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ26 read requests. +#define PSWRQ2_REG_BW_ADD27_E5 0x2405f8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ27 read requests. +#define PSWRQ2_REG_BW_RD_ADD27_BB_K2 0x2405f8UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ27 read requests. #define PSWRQ2_REG_BW_ADD28 0x2405fcUL //Access:RW DataWidth:0x14 // Multi Field Register. #define PSWRQ2_REG_BW_ADD28_BW_RD_ADD28 (0x3ff<<0) // Bandwidth addition to VQ28 read requests. #define PSWRQ2_REG_BW_ADD28_BW_RD_ADD28_SHIFT 0 #define PSWRQ2_REG_BW_ADD28_BW_WR_ADD28 (0x3ff<<10) // Bandwidth addition to VQ28 write requests. #define PSWRQ2_REG_BW_ADD28_BW_WR_ADD28_SHIFT 10 -#define PSWRQ2_REG_BW_WR_ADD29 0x240600UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ29 write requests. -#define PSWRQ2_REG_BW_WR_ADD30 0x240604UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ30 write requests. +#define PSWRQ2_REG_BW_ADD29_E5 0x240600UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ29 write requests. +#define PSWRQ2_REG_BW_WR_ADD29_BB_K2 0x240600UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ29 write requests. +#define PSWRQ2_REG_BW_ADD30_E5 0x240604UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ30 write requests. +#define PSWRQ2_REG_BW_WR_ADD30_BB_K2 0x240604UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ30 write requests. #define PSWRQ2_REG_BW_ADD31 0x240608UL //Access:RW DataWidth:0x14 // Multi Field Register. #define PSWRQ2_REG_BW_ADD31_BW_RD_ADD31 (0x3ff<<0) // Bandwidth addition to VQ31 read requests. #define PSWRQ2_REG_BW_ADD31_BW_RD_ADD31_SHIFT 0 #define PSWRQ2_REG_BW_ADD31_BW_WR_ADD31 (0x3ff<<10) // Bandwidth addition to VQ31 write requests. #define PSWRQ2_REG_BW_ADD31_BW_WR_ADD31_SHIFT 10 -#define PSWRQ2_REG_BW_RD_UBOUND0 0x24060cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ0 read requests. +#define PSWRQ2_REG_BW_UB0_E5 0x24060cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ0 read requests. +#define PSWRQ2_REG_BW_RD_UBOUND0_BB_K2 0x24060cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ0 read requests. #define PSWRQ2_REG_BW_UB1 0x240610UL //Access:RW DataWidth:0x12 // Multi Field Register. #define PSWRQ2_REG_BW_UB1_BW_RD_UBOUND1 (0x1ff<<0) // Bandwidth upper bound for VQ1 read requests. #define PSWRQ2_REG_BW_UB1_BW_RD_UBOUND1_SHIFT 0 @@ -42588,8 +45889,10 @@ #define PSWRQ2_REG_BW_UB3_BW_RD_UBOUND3_SHIFT 0 #define PSWRQ2_REG_BW_UB3_BW_WR_UBOUND3 (0x1ff<<9) // Bandwidth upper bound for VQ3 write requests. #define PSWRQ2_REG_BW_UB3_BW_WR_UBOUND3_SHIFT 9 -#define PSWRQ2_REG_BW_RD_UBOUND4 0x24061cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ4 read requests. -#define PSWRQ2_REG_BW_RD_UBOUND5 0x240620UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ5 read requests. +#define PSWRQ2_REG_BW_UB4_E5 0x24061cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ4 read requests. +#define PSWRQ2_REG_BW_RD_UBOUND4_BB_K2 0x24061cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ4 read requests. +#define PSWRQ2_REG_BW_UB5_E5 0x240620UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ5 read requests. +#define PSWRQ2_REG_BW_RD_UBOUND5_BB_K2 0x240620UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ5 read requests. #define PSWRQ2_REG_BW_UB6 0x240624UL //Access:RW DataWidth:0x12 // Multi Field Register. #define PSWRQ2_REG_BW_UB6_BW_RD_UBOUND6 (0x1ff<<0) // Bandwidth upper bound for VQ6 read requests. #define PSWRQ2_REG_BW_UB6_BW_RD_UBOUND6_SHIFT 0 @@ -42620,39 +45923,65 @@ #define PSWRQ2_REG_BW_UB11_BW_RD_UBOUND11_SHIFT 0 #define PSWRQ2_REG_BW_UB11_BW_WR_UBOUND11 (0x1ff<<9) // Bandwidth upper bound for VQ11 write requests. #define PSWRQ2_REG_BW_UB11_BW_WR_UBOUND11_SHIFT 9 -#define PSWRQ2_REG_BW_RD_UBOUND12 0x24063cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ12 read requests. -#define PSWRQ2_REG_BW_RD_UBOUND13 0x240640UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ13 read requests. +#define PSWRQ2_REG_BW_UB12_E5 0x24063cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ12 read requests. +#define PSWRQ2_REG_BW_RD_UBOUND12_BB_K2 0x24063cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ12 read requests. +#define PSWRQ2_REG_BW_UB13_E5 0x240640UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ13 read requests. +#define PSWRQ2_REG_BW_RD_UBOUND13_BB_K2 0x240640UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ13 read requests. #define PSWRQ2_REG_BW_UB14 0x240644UL //Access:RW DataWidth:0x12 // Multi Field Register. #define PSWRQ2_REG_BW_UB14_BW_RD_UBOUND14 (0x1ff<<0) // Bandwidth upper bound for VQ14 read requests. #define PSWRQ2_REG_BW_UB14_BW_RD_UBOUND14_SHIFT 0 #define PSWRQ2_REG_BW_UB14_BW_WR_UBOUND14 (0x1ff<<9) // Bandwidth upper bound for VQ14 write requests. #define PSWRQ2_REG_BW_UB14_BW_WR_UBOUND14_SHIFT 9 -#define PSWRQ2_REG_BW_RD_UBOUND15 0x240648UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ15 read requests. -#define PSWRQ2_REG_BW_RD_UBOUND16 0x24064cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ16 read requests. -#define PSWRQ2_REG_BW_RD_UBOUND17 0x240650UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ17 read requests. -#define PSWRQ2_REG_BW_RD_UBOUND18 0x240654UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ18 read requests. -#define PSWRQ2_REG_BW_RD_UBOUND19 0x240658UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ19 read requests. -#define PSWRQ2_REG_BW_RD_UBOUND20 0x24065cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ20 read requests. -#define PSWRQ2_REG_BW_WR_UBOUND21 0x240660UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ21 write requests. -#define PSWRQ2_REG_BW_RD_UBOUND22 0x240664UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ22 read requests. -#define PSWRQ2_REG_BW_RD_UBOUND23 0x240668UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ23 read requests. -#define PSWRQ2_REG_BW_RD_UBOUND24 0x24066cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ24 read requests. -#define PSWRQ2_REG_BW_RD_UBOUND25 0x240670UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ25 read requests. -#define PSWRQ2_REG_BW_RD_UBOUND26 0x240674UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ26 read requests. -#define PSWRQ2_REG_BW_RD_UBOUND27 0x240678UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ27 read requests. +#define PSWRQ2_REG_BW_UB15_E5 0x240648UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ15 read requests. +#define PSWRQ2_REG_BW_RD_UBOUND15_BB_K2 0x240648UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ15 read requests. +#define PSWRQ2_REG_BW_UB16_E5 0x24064cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ16 read requests. +#define PSWRQ2_REG_BW_RD_UBOUND16_BB_K2 0x24064cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ16 read requests. +#define PSWRQ2_REG_BW_UB17_E5 0x240650UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ17 read requests. +#define PSWRQ2_REG_BW_RD_UBOUND17_BB_K2 0x240650UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ17 read requests. +#define PSWRQ2_REG_BW_UB18_E5 0x240654UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ18 read requests. +#define PSWRQ2_REG_BW_RD_UBOUND18_BB_K2 0x240654UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ18 read requests. +#define PSWRQ2_REG_BW_UB19_E5 0x240658UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ19 read requests. +#define PSWRQ2_REG_BW_RD_UBOUND19_BB_K2 0x240658UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ19 read requests. +#define PSWRQ2_REG_BW_UB20_E5 0x24065cUL //Access:RW DataWidth:0x12 // Multi Field Register. + #define PSWRQ2_REG_BW_UB20_BW_RD_UBOUND20_E5 (0x1ff<<0) // Bandwidth upper bound for VQ20 read requests. + #define PSWRQ2_REG_BW_UB20_BW_RD_UBOUND20_E5_SHIFT 0 + #define PSWRQ2_REG_BW_UB20_BW_WR_UBOUND20_E5 (0x1ff<<9) // Bandwidth upper bound for VQ20 write requests. + #define PSWRQ2_REG_BW_UB20_BW_WR_UBOUND20_E5_SHIFT 9 +#define PSWRQ2_REG_BW_RD_UBOUND20_BB_K2 0x24065cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ20 read requests. +#define PSWRQ2_REG_BW_UB21_E5 0x240660UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ21 write requests. +#define PSWRQ2_REG_BW_WR_UBOUND21_BB_K2 0x240660UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ21 write requests. +#define PSWRQ2_REG_BW_UB22_E5 0x240664UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ22 read requests. +#define PSWRQ2_REG_BW_RD_UBOUND22_BB_K2 0x240664UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ22 read requests. +#define PSWRQ2_REG_BW_UB23_E5 0x240668UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ23 read requests. +#define PSWRQ2_REG_BW_RD_UBOUND23_BB_K2 0x240668UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ23 read requests. +#define PSWRQ2_REG_BW_UB24_E5 0x24066cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ24 read requests. +#define PSWRQ2_REG_BW_RD_UBOUND24_BB_K2 0x24066cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ24 read requests. +#define PSWRQ2_REG_BW_UB25_E5 0x240670UL //Access:RW DataWidth:0x12 // Multi Field Register. + #define PSWRQ2_REG_BW_UB25_BW_RD_UBOUND25_E5 (0x1ff<<0) // Bandwidth upper bound for VQ25 read requests. + #define PSWRQ2_REG_BW_UB25_BW_RD_UBOUND25_E5_SHIFT 0 + #define PSWRQ2_REG_BW_UB25_BW_WR_UBOUND25_E5 (0x1ff<<9) // Bandwidth upper bound for VQ25 write requests. + #define PSWRQ2_REG_BW_UB25_BW_WR_UBOUND25_E5_SHIFT 9 +#define PSWRQ2_REG_BW_RD_UBOUND25_BB_K2 0x240670UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ25 read requests. +#define PSWRQ2_REG_BW_UB26_E5 0x240674UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ26 read requests. +#define PSWRQ2_REG_BW_RD_UBOUND26_BB_K2 0x240674UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ26 read requests. +#define PSWRQ2_REG_BW_UB27_E5 0x240678UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ27 read requests. +#define PSWRQ2_REG_BW_RD_UBOUND27_BB_K2 0x240678UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ27 read requests. #define PSWRQ2_REG_BW_UB28 0x24067cUL //Access:RW DataWidth:0x12 // Multi Field Register. #define PSWRQ2_REG_BW_UB28_BW_RD_UBOUND28 (0x1ff<<0) // Bandwidth upper bound for VQ28 read requests. #define PSWRQ2_REG_BW_UB28_BW_RD_UBOUND28_SHIFT 0 #define PSWRQ2_REG_BW_UB28_BW_WR_UBOUND28 (0x1ff<<9) // Bandwidth upper bound for VQ28. #define PSWRQ2_REG_BW_UB28_BW_WR_UBOUND28_SHIFT 9 -#define PSWRQ2_REG_BW_WR_UBOUND29 0x240680UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ29. -#define PSWRQ2_REG_BW_WR_UBOUND30 0x240684UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ30. +#define PSWRQ2_REG_BW_UB29_E5 0x240680UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ29 write requests. +#define PSWRQ2_REG_BW_WR_UBOUND29_BB_K2 0x240680UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ29. +#define PSWRQ2_REG_BW_UB30_E5 0x240684UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ30 write requests. +#define PSWRQ2_REG_BW_WR_UBOUND30_BB_K2 0x240684UL //Access:RW DataWidth:0x9 // Bandwidth upper bound for VQ30. #define PSWRQ2_REG_BW_UB31 0x240688UL //Access:RW DataWidth:0x12 // Multi Field Register. #define PSWRQ2_REG_BW_UB31_BW_RD_UBOUND31 (0x1ff<<0) // Bandwidth upper bound for VQ31 read requests. #define PSWRQ2_REG_BW_UB31_BW_RD_UBOUND31_SHIFT 0 #define PSWRQ2_REG_BW_UB31_BW_WR_UBOUND31 (0x1ff<<9) // Bandwidth upper bound for VQ31 write requests. #define PSWRQ2_REG_BW_UB31_BW_WR_UBOUND31_SHIFT 9 -#define PSWRQ2_REG_BW_RD_L0 0x24068cUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ0 Read requests. +#define PSWRQ2_REG_BW_L0_E5 0x24068cUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ0 requests. +#define PSWRQ2_REG_BW_RD_L0_BB_K2 0x24068cUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ0 Read requests. #define PSWRQ2_REG_BW_L1 0x240690UL //Access:RW DataWidth:0x12 // Multi Field Register. #define PSWRQ2_REG_BW_L1_BW_WR_L1 (0x1ff<<0) // Bandwidth Typical L for VQ1 Write requests. #define PSWRQ2_REG_BW_L1_BW_WR_L1_SHIFT 0 @@ -42668,8 +45997,10 @@ #define PSWRQ2_REG_BW_L3_BW_WR_L3_SHIFT 0 #define PSWRQ2_REG_BW_L3_BW_RD_L3 (0x1ff<<9) // Bandwidth Typical L for VQ3 Read requests. #define PSWRQ2_REG_BW_L3_BW_RD_L3_SHIFT 9 -#define PSWRQ2_REG_BW_RD_L4 0x24069cUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ4 Read requests. -#define PSWRQ2_REG_BW_RD_L5 0x2406a0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ5 Read- currently not used. +#define PSWRQ2_REG_BW_L4_E5 0x24069cUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ4 requests. +#define PSWRQ2_REG_BW_RD_L4_BB_K2 0x24069cUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ4 Read requests. +#define PSWRQ2_REG_BW_L5_E5 0x2406a0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ5 requests. +#define PSWRQ2_REG_BW_RD_L5_BB_K2 0x2406a0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ5 Read- currently not used. #define PSWRQ2_REG_BW_L6 0x2406a4UL //Access:RW DataWidth:0x12 // Multi Field Register. #define PSWRQ2_REG_BW_L6_BW_RD_L6 (0x1ff<<0) // Bandwidth Typical L for VQ6 Read requests. #define PSWRQ2_REG_BW_L6_BW_RD_L6_SHIFT 0 @@ -42700,33 +46031,58 @@ #define PSWRQ2_REG_BW_L11_BW_RD_L11_SHIFT 0 #define PSWRQ2_REG_BW_L11_BW_WR_L11 (0x1ff<<9) // Bandwidth Typical L for VQ11 Write requests. #define PSWRQ2_REG_BW_L11_BW_WR_L11_SHIFT 9 -#define PSWRQ2_REG_BW_RD_L12 0x2406bcUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ12 Read requests. -#define PSWRQ2_REG_BW_RD_L13 0x2406c0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ13 Read requests. +#define PSWRQ2_REG_BW_L12_E5 0x2406bcUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ12 requests. +#define PSWRQ2_REG_BW_RD_L12_BB_K2 0x2406bcUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ12 Read requests. +#define PSWRQ2_REG_BW_L13_E5 0x2406c0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ13 requests. +#define PSWRQ2_REG_BW_RD_L13_BB_K2 0x2406c0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ13 Read requests. #define PSWRQ2_REG_BW_L14 0x2406c4UL //Access:RW DataWidth:0x12 // Multi Field Register. #define PSWRQ2_REG_BW_L14_BW_RD_L14 (0x1ff<<0) // Bandwidth Typical L for VQ14 Read requests. #define PSWRQ2_REG_BW_L14_BW_RD_L14_SHIFT 0 #define PSWRQ2_REG_BW_L14_BW_WR_L14 (0x1ff<<9) // Bandwidth Typical L for VQ14 Write requests. #define PSWRQ2_REG_BW_L14_BW_WR_L14_SHIFT 9 -#define PSWRQ2_REG_BW_RD_L15 0x2406c8UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ15 Read requests. -#define PSWRQ2_REG_BW_RD_L16 0x2406ccUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ16 Read requests. -#define PSWRQ2_REG_BW_RD_L17 0x2406d0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ17 Read requests. -#define PSWRQ2_REG_BW_RD_L18 0x2406d4UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ18 Read requests. -#define PSWRQ2_REG_BW_RD_L19 0x2406d8UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ19 Read requests. -#define PSWRQ2_REG_BW_RD_L20 0x2406dcUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ20 Read requests. -#define PSWRQ2_REG_BW_WR_L21 0x2406e0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ21 Write requests. -#define PSWRQ2_REG_BW_RD_L22 0x2406e4UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ22 Read requests. -#define PSWRQ2_REG_BW_RD_L23 0x2406e8UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ23 Read requests. -#define PSWRQ2_REG_BW_RD_L24 0x2406ecUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ24 Read requests. -#define PSWRQ2_REG_BW_RD_L25 0x2406f0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ25 Read requests. -#define PSWRQ2_REG_BW_RD_L26 0x2406f4UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ26 Read requests. -#define PSWRQ2_REG_BW_RD_L27 0x2406f8UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ27 Read requests. +#define PSWRQ2_REG_BW_L15_E5 0x2406c8UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ15 requests. +#define PSWRQ2_REG_BW_RD_L15_BB_K2 0x2406c8UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ15 Read requests. +#define PSWRQ2_REG_BW_L16_E5 0x2406ccUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ16 requests. +#define PSWRQ2_REG_BW_RD_L16_BB_K2 0x2406ccUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ16 Read requests. +#define PSWRQ2_REG_BW_L17_E5 0x2406d0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ17 requests. +#define PSWRQ2_REG_BW_RD_L17_BB_K2 0x2406d0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ17 Read requests. +#define PSWRQ2_REG_BW_L18_E5 0x2406d4UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ18 requests. +#define PSWRQ2_REG_BW_RD_L18_BB_K2 0x2406d4UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ18 Read requests. +#define PSWRQ2_REG_BW_L19_E5 0x2406d8UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ19 requests. +#define PSWRQ2_REG_BW_RD_L19_BB_K2 0x2406d8UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ19 Read requests. +#define PSWRQ2_REG_BW_L20_E5 0x2406dcUL //Access:RW DataWidth:0x12 // Multi Field Register. + #define PSWRQ2_REG_BW_L20_BW_RD_L20_E5 (0x1ff<<0) // Bandwidth Typical L for VQ20 Read requests. + #define PSWRQ2_REG_BW_L20_BW_RD_L20_E5_SHIFT 0 + #define PSWRQ2_REG_BW_L20_BW_WR_L20_E5 (0x1ff<<9) // Bandwidth Typical L for VQ20 Write requests. + #define PSWRQ2_REG_BW_L20_BW_WR_L20_E5_SHIFT 9 +#define PSWRQ2_REG_BW_RD_L20_BB_K2 0x2406dcUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ20 Read requests. +#define PSWRQ2_REG_BW_L21_E5 0x2406e0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ21 write requests. +#define PSWRQ2_REG_BW_WR_L21_BB_K2 0x2406e0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ21 Write requests. +#define PSWRQ2_REG_BW_L22_E5 0x2406e4UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ22 Read requests. +#define PSWRQ2_REG_BW_RD_L22_BB_K2 0x2406e4UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ22 Read requests. +#define PSWRQ2_REG_BW_L23_E5 0x2406e8UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ23 Read requests. +#define PSWRQ2_REG_BW_RD_L23_BB_K2 0x2406e8UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ23 Read requests. +#define PSWRQ2_REG_BW_L24_E5 0x2406ecUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ24 Read requests. +#define PSWRQ2_REG_BW_RD_L24_BB_K2 0x2406ecUL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ24 Read requests. +#define PSWRQ2_REG_BW_L25_E5 0x2406f0UL //Access:RW DataWidth:0x12 // Multi Field Register. + #define PSWRQ2_REG_BW_L25_BW_RD_L25_E5 (0x1ff<<0) // Bandwidth Typical L for VQ25 Read requests. + #define PSWRQ2_REG_BW_L25_BW_RD_L25_E5_SHIFT 0 + #define PSWRQ2_REG_BW_L25_BW_WR_L25_E5 (0x1ff<<9) // Bandwidth Typical L for VQ25 Write requests. + #define PSWRQ2_REG_BW_L25_BW_WR_L25_E5_SHIFT 9 +#define PSWRQ2_REG_BW_RD_L25_BB_K2 0x2406f0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ25 Read requests. +#define PSWRQ2_REG_BW_L26_E5 0x2406f4UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ26 Read requests. +#define PSWRQ2_REG_BW_RD_L26_BB_K2 0x2406f4UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ26 Read requests. +#define PSWRQ2_REG_BW_L27_E5 0x2406f8UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ27 Read requests. +#define PSWRQ2_REG_BW_RD_L27_BB_K2 0x2406f8UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ27 Read requests. #define PSWRQ2_REG_BW_L28 0x2406fcUL //Access:RW DataWidth:0x12 // Multi Field Register. #define PSWRQ2_REG_BW_L28_BW_RD_L28 (0x1ff<<0) // Bandwidth Typical L for VQ28 Read requests. #define PSWRQ2_REG_BW_L28_BW_RD_L28_SHIFT 0 #define PSWRQ2_REG_BW_L28_BW_WR_L28 (0x1ff<<9) // Bandwidth Typical L for VQ28 Write requests. #define PSWRQ2_REG_BW_L28_BW_WR_L28_SHIFT 9 -#define PSWRQ2_REG_BW_WR_L29 0x240700UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ29 Write requests. -#define PSWRQ2_REG_BW_WR_L30 0x240704UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ30 Write requests. +#define PSWRQ2_REG_BW_L29_E5 0x240700UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ29 write requests. +#define PSWRQ2_REG_BW_WR_L29_BB_K2 0x240700UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ29 Write requests. +#define PSWRQ2_REG_BW_L30_E5 0x240704UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ30 write requests. +#define PSWRQ2_REG_BW_WR_L30_BB_K2 0x240704UL //Access:RW DataWidth:0x9 // Bandwidth Typical L for VQ30 Write requests. #define PSWRQ2_REG_BW_L31 0x240708UL //Access:RW DataWidth:0x12 // Multi Field Register. #define PSWRQ2_REG_BW_L31_BW_RD_L31 (0x1ff<<0) // Bandwidth Typical L for VQ31 Read requests. #define PSWRQ2_REG_BW_L31_BW_RD_L31_SHIFT 0 @@ -42746,92 +46102,92 @@ #define PSWRQ2_REG_BW_WR_WR_BW_UBOUND_SHIFT 10 #define PSWRQ2_REG_BW_WR_WR_BW_L (0x1ff<<19) // Bandwidth Typical L for write requests in the read write arbiter. #define PSWRQ2_REG_BW_WR_WR_BW_L_SHIFT 19 -#define PSWRQ2_REG_BW_CREDIT 0x240714UL //Access:RW DataWidth:0x8 // Multi Field Register. +#define PSWRQ2_REG_BW_CREDIT 0x240714UL //Access:RW DataWidth:0x9 // Multi Field Register. #define PSWRQ2_REG_BW_CREDIT_READ_CREDIT (0xf<<0) // Indicates the number of credits for read sub-requests in th requester glue interface. #define PSWRQ2_REG_BW_CREDIT_READ_CREDIT_SHIFT 0 - #define PSWRQ2_REG_BW_CREDIT_WRITE_CREDIT (0xf<<4) // Indicates the number of credits for write sub-requests in th requester glue interface. + #define PSWRQ2_REG_BW_CREDIT_WRITE_CREDIT (0x1f<<4) // Indicates the number of credits for write sub-requests in th requester glue interface. #define PSWRQ2_REG_BW_CREDIT_WRITE_CREDIT_SHIFT 4 #define PSWRQ2_REG_L2P_TM 0x240718UL //Access:RW DataWidth:0x5 // Tm input for l2p memory. -#define PSWRQ2_REG_SLOW_TH 0x24071cUL //Access:RW DataWidth:0x8 // When number of free entries in the context ram will be lower than this;the input clients arbiter will work in a slower pace. +#define PSWRQ2_REG_SLOW_TH_BB_K2 0x24071cUL //Access:RW DataWidth:0x8 // When number of free entries in the context ram will be lower than this;the input clients arbiter will work in a slower pace. #define PSWRQ2_REG_PDR_LIMIT 0x240720UL //Access:RW DataWidth:0xe // Pending read limiter threshold; in Dwords. -#define PSWRQ2_REG_DBG_HEAD_MUX_SEL 0x240724UL //Access:RW DataWidth:0x5 // Sets which vq head pointer to see out of queues 0-31. -#define PSWRQ2_REG_DBG_TAIL_MUX_SEL 0x240728UL //Access:RW DataWidth:0x5 // Sets which vq tail pointer to see out of queues 0-31. +#define PSWRQ2_REG_DBG_HEAD_MUX_SEL_BB_K2 0x240724UL //Access:RW DataWidth:0x5 // Sets which vq head pointer to see out of queues 0-31. +#define PSWRQ2_REG_DBG_TAIL_MUX_SEL_BB_K2 0x240728UL //Access:RW DataWidth:0x5 // Sets which vq tail pointer to see out of queues 0-31. #define PSWRQ2_REG_L2P_MODE 0x24072cUL //Access:RW DataWidth:0x1 // Will determine how the logical address is calculated; 0: as in E1; 1:with new algorithm. #define PSWRQ2_REG_DRAM_ALIGN_SEL 0x240730UL //Access:RW DataWidth:0x1 // When set the new alignment method (E2) will be applied; when reset the original alignment method (E1 E1H) will be applied. -#define PSWRQ2_REG_CXR_RAM0_TM 0x240734UL //Access:RW DataWidth:0x8 // TM bits for cxr ram0. -#define PSWRQ2_REG_CXR_RAM1_TM 0x240738UL //Access:RW DataWidth:0x8 // TM bits for cxr ram1. -#define PSWRQ2_REG_VQ_RD_DISABLE 0x24073cUL //Access:R DataWidth:0xc // Vq read disable as wdone was not received yet for the wr request that was sent {vq1 ; vq2 ; vq3 ; vq6 ; vq7 ; vq8 ; vq9 ; vq10 ; vq11 ; vq14; vq28; vq31}. -#define PSWRQ2_REG_QC_REG1 0x240740UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_REG2 0x240744UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_1ENTRY 0x240748UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_HOQ_IS_LOGICAL 0x24074cUL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_TAIL_V 0x240750UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_HEAD_V 0x240754UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_31_28_TAIL 0x240758UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_27_24_TAIL 0x24075cUL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_23_20_TAIL 0x240760UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_19_16_TAIL 0x240764UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_15_12_TAIL 0x240768UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_11_8_TAIL 0x24076cUL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_7_4_TAIL 0x240770UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_3_0_TAIL 0x240774UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_31_28_HEAD 0x240778UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_27_24_HEAD 0x24077cUL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_23_20_HEAD 0x240780UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_19_16_HEAD 0x240784UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_15_12_HEAD 0x240788UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_11_8_HEAD 0x24078cUL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_7_4_HEAD 0x240790UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_QC_VIQ_3_0_HEAD 0x240794UL //Access:R DataWidth:0x20 // -#define PSWRQ2_REG_BW_RD_ADD_TREQ 0x240798UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ TREQ read requests. -#define PSWRQ2_REG_BW_RD_UBOUND_TREQ 0x24079cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound to VQ TREQ read requests. -#define PSWRQ2_REG_BW_RD_L_TREQ 0x2407a0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L to VQ TREQ read requests. -#define PSWRQ2_REG_BW_WR_ADD_ICPL 0x2407a4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ ICPL write requests. -#define PSWRQ2_REG_BW_WR_UBOUND_ICPL 0x2407a8UL //Access:RW DataWidth:0x9 // Bandwidth upper bound to VQ ICPL write requests. -#define PSWRQ2_REG_BW_WR_L_ICPL 0x2407acUL //Access:RW DataWidth:0x9 // Bandwidth Typical L to VQ ICPL write requests. -#define PSWRQ2_REG_ATC_USDM_FLAGS 0x2407b0UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_USDMDP_FLAGS 0x2407b4UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_TSDM_FLAGS 0x2407b8UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_XSDM_FLAGS 0x2407bcUL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_DMAE_FLAGS 0x2407c0UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_CDUWR_FLAGS 0x2407c4UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_CDURD_FLAGS 0x2407c8UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_PBF_FLAGS 0x2407ccUL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_QM_FLAGS 0x2407d0UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_TM_FLAGS 0x2407d4UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_SRC_FLAGS 0x2407d8UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_DBG_FLAGS 0x2407dcUL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_M2P_FLAGS 0x2407e0UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_PTU_FLAGS 0x2407e4UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_HC_FLAGS 0x2407e8UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_VQ_ENABLE 0x2407ecUL //Access:RW DataWidth:0x20 // ATC VQ enable bits. When set - SR from the VQ can send ATC lookup request to the ATC (assuming all other conditions are met). When reset - all SR-s from the VQ will NOT go through the ATC. b0 - VQ0; b1 - VQ1; b30 - VQ30; b31 - reserved (should be filled with zeroes). -#define PSWRQ2_REG_ATC_INTERNAL_ATS_ENABLE 0x2407f0UL //Access:RW DataWidth:0x2 // ATC enable values per PF as follows: b0 - PF enable; b1 - VF enable; PF enable bit is relevant when VF_Valid (in the request) bit is 0; VF enable bit is relevant when VF_Valid bit is 1. -#define PSWRQ2_REG_ATC_INTERNAL_ATS_ENABLE_ALL 0x2407f4UL //Access:R DataWidth:0x20 // Concatenated values of rq_atc_internal_ats_enable as follows: b0 - PF0; b1 - VF0; b2 - PF1; b3 - VF1; b30 - PF15 ; b31 - VF15;. -#define PSWRQ2_REG_ATC_VQ_GO_TRANSLATED 0x2407f8UL //Access:RW DataWidth:0x20 // DEBUG ONLY. bit per VQ. go translated set means that SR of the matched VQ will be always sent to the GLUE with the at_valid=1 indication (see atc_code in PSWRQ-PGLUE interface for more details). In that case the address will be delivered by the chip (and not by the ATC). This mode will be used mainly for debug and the other configurations must make sure that ATC will never be used for that VQ while the go_translated bit for that VQ is set. when reset means that the at_valid indication will be determined according to the ATC. -#define PSWRQ2_REG_ATC_GLOBAL_ENABLE 0x2407fcUL //Access:RW DataWidth:0x1 // Global ATC enable bit. when reset all ATC logic is disabled within the PSWRQ. The value of this register must be the same as RD_ATC_GLOBAL_ENABLE. This value must be '1' when ATC capability is enabled in PCIe core. -#define PSWRQ2_REG_CLOSE_GATE_VQ_LSB_EN 0x240800UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i.e. can be chosen by the GARB) in close the gates scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow IGU TREQ & ICPL requests to be chosen in such scenario. -#define PSWRQ2_REG_CLOSE_GATE_VQ_MSB_EN 0x240804UL //Access:RW DataWidth:0x2 // VQ-s that are enabled (i.e. can be chosen by the GARB) in close the gates scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow IGU TREQ & ICPL requests to be chosen in such scenario. -#define PSWRQ2_REG_STALL_MEM_VQ_LSB_EN 0x240808UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall mem scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow IGU requests to be chosen in such scenario. -#define PSWRQ2_REG_STALL_MEM_VQ_MSB_EN 0x24080cUL //Access:RW DataWidth:0x2 // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall mem scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow IGU requests to be chosen in such scenario. -#define PSWRQ2_REG_STALL_INT_VQ_LSB_EN 0x240810UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall int scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow non-IGU requests to be chosen in such scenario. -#define PSWRQ2_REG_STALL_INT_VQ_MSB_EN 0x240814UL //Access:RW DataWidth:0x2 // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall int scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow non-IGU requests to be chosen in such scenario. -#define PSWRQ2_REG_TREQ_FIFO_FILL_LVL 0x240818UL //Access:R DataWidth:0x6 // The fill level of the TREQ fifo. -#define PSWRQ2_REG_ICPL_FIFO_FILL_LVL 0x24081cUL //Access:R DataWidth:0x3 // The fill level of the ICPL fifo. -#define PSWRQ2_REG_ATC_TREQ_FIFO_TM 0x240820UL //Access:RW DataWidth:0x2 // NOT USED. +#define PSWRQ2_REG_CXR_RAM0_TM_BB_K2 0x240734UL //Access:RW DataWidth:0x8 // TM bits for cxr ram0. +#define PSWRQ2_REG_CXR_RAM1_TM_BB_K2 0x240738UL //Access:RW DataWidth:0x8 // TM bits for cxr ram1. +#define PSWRQ2_REG_VQ_RD_DISABLE 0x24073cUL //Access:R DataWidth:0xe // Vq read disable as wdone was not received yet for the wr request that was sent {vq1 ; vq2 ; vq3 ; vq6 ; vq7 ; vq8 ; vq9 ; vq10 ; vq11 ; vq14; vq20; vq25; vq28; vq31}. +#define PSWRQ2_REG_QC_REG1_BB_K2 0x240740UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_REG2_BB_K2 0x240744UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_1ENTRY_BB_K2 0x240748UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_HOQ_IS_LOGICAL_BB_K2 0x24074cUL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_TAIL_V_BB_K2 0x240750UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_HEAD_V_BB_K2 0x240754UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_31_28_TAIL_BB_K2 0x240758UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_27_24_TAIL_BB_K2 0x24075cUL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_23_20_TAIL_BB_K2 0x240760UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_19_16_TAIL_BB_K2 0x240764UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_15_12_TAIL_BB_K2 0x240768UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_11_8_TAIL_BB_K2 0x24076cUL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_7_4_TAIL_BB_K2 0x240770UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_3_0_TAIL_BB_K2 0x240774UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_31_28_HEAD_BB_K2 0x240778UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_27_24_HEAD_BB_K2 0x24077cUL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_23_20_HEAD_BB_K2 0x240780UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_19_16_HEAD_BB_K2 0x240784UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_15_12_HEAD_BB_K2 0x240788UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_11_8_HEAD_BB_K2 0x24078cUL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_7_4_HEAD_BB_K2 0x240790UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_QC_VIQ_3_0_HEAD_BB_K2 0x240794UL //Access:R DataWidth:0x20 // +#define PSWRQ2_REG_BW_RD_ADD_TREQ_BB_K2 0x240798UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ TREQ read requests. +#define PSWRQ2_REG_BW_RD_UBOUND_TREQ_BB_K2 0x24079cUL //Access:RW DataWidth:0x9 // Bandwidth upper bound to VQ TREQ read requests. +#define PSWRQ2_REG_BW_RD_L_TREQ_BB_K2 0x2407a0UL //Access:RW DataWidth:0x9 // Bandwidth Typical L to VQ TREQ read requests. +#define PSWRQ2_REG_BW_WR_ADD_ICPL_BB_K2 0x2407a4UL //Access:RW DataWidth:0xa // Bandwidth addition to VQ ICPL write requests. +#define PSWRQ2_REG_BW_WR_UBOUND_ICPL_BB_K2 0x2407a8UL //Access:RW DataWidth:0x9 // Bandwidth upper bound to VQ ICPL write requests. +#define PSWRQ2_REG_BW_WR_L_ICPL_BB_K2 0x2407acUL //Access:RW DataWidth:0x9 // Bandwidth Typical L to VQ ICPL write requests. +#define PSWRQ2_REG_ATC_USDM_FLAGS_BB_K2 0x2407b0UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_USDMDP_FLAGS_BB_K2 0x2407b4UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_TSDM_FLAGS_BB_K2 0x2407b8UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_XSDM_FLAGS_BB_K2 0x2407bcUL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_DMAE_FLAGS_BB_K2 0x2407c0UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_CDUWR_FLAGS_BB_K2 0x2407c4UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_CDURD_FLAGS_BB_K2 0x2407c8UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_PBF_FLAGS_BB_K2 0x2407ccUL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_QM_FLAGS_BB_K2 0x2407d0UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_TM_FLAGS_BB_K2 0x2407d4UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_SRC_FLAGS_BB_K2 0x2407d8UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_DBG_FLAGS_BB_K2 0x2407dcUL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_M2P_FLAGS_BB_K2 0x2407e0UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_PTU_FLAGS_BB_K2 0x2407e4UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_HC_FLAGS_BB_K2 0x2407e8UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_VQ_ENABLE_BB_K2 0x2407ecUL //Access:RW DataWidth:0x20 // ATC VQ enable bits. When set - SR from the VQ can send ATC lookup request to the ATC (assuming all other conditions are met). When reset - all SR-s from the VQ will NOT go through the ATC. b0 - VQ0; b1 - VQ1; b30 - VQ30; b31 - reserved (should be filled with zeroes). +#define PSWRQ2_REG_ATC_INTERNAL_ATS_ENABLE_BB_K2 0x2407f0UL //Access:RW DataWidth:0x2 // ATC enable values per PF as follows: b0 - PF enable; b1 - VF enable; PF enable bit is relevant when VF_Valid (in the request) bit is 0; VF enable bit is relevant when VF_Valid bit is 1. +#define PSWRQ2_REG_ATC_INTERNAL_ATS_ENABLE_ALL_BB_K2 0x2407f4UL //Access:R DataWidth:0x20 // Concatenated values of rq_atc_internal_ats_enable as follows: b0 - PF0; b1 - VF0; b2 - PF1; b3 - VF1; b30 - PF15 ; b31 - VF15;. +#define PSWRQ2_REG_ATC_VQ_GO_TRANSLATED_BB_K2 0x2407f8UL //Access:RW DataWidth:0x20 // DEBUG ONLY. bit per VQ. go translated set means that SR of the matched VQ will be always sent to the GLUE with the at_valid=1 indication (see atc_code in PSWRQ-PGLUE interface for more details). In that case the address will be delivered by the chip (and not by the ATC). This mode will be used mainly for debug and the other configurations must make sure that ATC will never be used for that VQ while the go_translated bit for that VQ is set. when reset means that the at_valid indication will be determined according to the ATC. +#define PSWRQ2_REG_ATC_GLOBAL_ENABLE_BB_K2 0x2407fcUL //Access:RW DataWidth:0x1 // Global ATC enable bit. when reset all ATC logic is disabled within the PSWRQ. The value of this register must be the same as RD_ATC_GLOBAL_ENABLE. This value must be '1' when ATC capability is enabled in PCIe core. +#define PSWRQ2_REG_CLOSE_GATE_VQ_LSB_EN 0x240800UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i.e. can be chosen by the GARB) in close the gates scenario +#define PSWRQ2_REG_CLOSE_GATE_VQ_MSB_EN_BB_K2 0x240804UL //Access:RW DataWidth:0x2 // VQ-s that are enabled (i.e. can be chosen by the GARB) in close the gates scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow IGU TREQ & ICPL requests to be chosen in such scenario. +#define PSWRQ2_REG_STALL_MEM_VQ_LSB_EN 0x240808UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall mem scenario. +#define PSWRQ2_REG_STALL_MEM_VQ_MSB_EN_BB_K2 0x24080cUL //Access:RW DataWidth:0x2 // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall mem scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow IGU requests to be chosen in such scenario. +#define PSWRQ2_REG_STALL_INT_VQ_LSB_EN 0x240810UL //Access:RW DataWidth:0x20 // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall int scenario. +#define PSWRQ2_REG_STALL_INT_VQ_MSB_EN_BB_K2 0x240814UL //Access:RW DataWidth:0x2 // VQ-s that are enabled (i.e. can be chosen by the GARB) in stall int scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow non-IGU requests to be chosen in such scenario. +#define PSWRQ2_REG_TREQ_FIFO_FILL_LVL_BB_K2 0x240818UL //Access:R DataWidth:0x6 // The fill level of the TREQ fifo. +#define PSWRQ2_REG_ICPL_FIFO_FILL_LVL_BB_K2 0x24081cUL //Access:R DataWidth:0x3 // The fill level of the ICPL fifo. +#define PSWRQ2_REG_ATC_TREQ_FIFO_TM_BB_K2 0x240820UL //Access:RW DataWidth:0x2 // NOT USED. #define PSWRQ2_REG_ASSERT_IF_ILT_FAIL 0x240824UL //Access:RW DataWidth:0x1 // When set - assert ilt fail interrupt (rq_elt_addr) in case working in ilt mode and onchip translation fail due to overflow on vah_plus_1st signal (Cont00041628). If reset - interrupt will not assert. -#define PSWRQ2_REG_HOQ_RAM_RD_REQ 0x240828UL //Access:RW DataWidth:0x5 // FOR DBG: read request from the hoq ram; the write data represents the address which is the vqid; in order to read from the hoq ram the read enable register should be set as well (rq_hoq_ram_rd_en); upon read completion (rq_hoq_ram_rd_status =1) data_rd_0 data_rd_1 data_rd_2 and data_rd_3 are ready with the valid values. -#define PSWRQ2_REG_HOQ_RAM_RD_EN 0x24082cUL //Access:RW DataWidth:0x1 // FOR DBG: enable reading from the hoq ram; when set hoq rbc read is enabled; when reset hoq rbc read is disabled (i.e. rq_hoq_ram_rd_req will not have any affect). -#define PSWRQ2_REG_HOQ_RAM_RD_STATUS 0x240830UL //Access:R DataWidth:0x1 // FOR DBG: when set - data rd from hoq ram is completed (i.e. data is ready in data_rd_0 data_rd_1 data_rd2 and data_rd_3); when reset - still waiting for hoq ram read request to be completed). -#define PSWRQ2_REG_HOQ_RAM_DATA_RD_0 0x240834UL //Access:R DataWidth:0x20 // FOR DBG: bits 15:0 length; bits 31:16 request id. -#define PSWRQ2_REG_HOQ_RAM_DATA_RD_1 0x240838UL //Access:R DataWidth:0x20 // FOR DBG: address (32 lsb). -#define PSWRQ2_REG_HOQ_RAM_DATA_RD_2 0x24083cUL //Access:R DataWidth:0x20 // FOR DBG: address (32 msb). -#define PSWRQ2_REG_HOQ_RAM_DATA_RD_3 0x240840UL //Access:R DataWidth:0x20 // FOR DBG: bit 0 relaxed ordering; bit 1 no-snoop; bits 5:2 client id; bit 6 done type; bit 7 resevred; bit 10:8 pfid; bit 11 vf_valid; bit 17:12 vfid; bits 20:18 atc flags; bits 31:21 reserved. +#define PSWRQ2_REG_HOQ_RAM_RD_REQ_BB_K2 0x240828UL //Access:RW DataWidth:0x5 // FOR DBG: read request from the hoq ram; the write data represents the address which is the vqid; in order to read from the hoq ram the read enable register should be set as well (rq_hoq_ram_rd_en); upon read completion (rq_hoq_ram_rd_status =1) data_rd_0 data_rd_1 data_rd_2 and data_rd_3 are ready with the valid values. +#define PSWRQ2_REG_HOQ_RAM_RD_EN_BB_K2 0x24082cUL //Access:RW DataWidth:0x1 // FOR DBG: enable reading from the hoq ram; when set hoq rbc read is enabled; when reset hoq rbc read is disabled (i.e. rq_hoq_ram_rd_req will not have any affect). +#define PSWRQ2_REG_HOQ_RAM_RD_STATUS_BB_K2 0x240830UL //Access:R DataWidth:0x1 // FOR DBG: when set - data rd from hoq ram is completed (i.e. data is ready in data_rd_0 data_rd_1 data_rd2 and data_rd_3); when reset - still waiting for hoq ram read request to be completed). +#define PSWRQ2_REG_HOQ_RAM_DATA_RD_0_BB_K2 0x240834UL //Access:R DataWidth:0x20 // FOR DBG: bits 15:0 length; bits 31:16 request id. +#define PSWRQ2_REG_HOQ_RAM_DATA_RD_1_BB_K2 0x240838UL //Access:R DataWidth:0x20 // FOR DBG: address (32 lsb). +#define PSWRQ2_REG_HOQ_RAM_DATA_RD_2_BB_K2 0x24083cUL //Access:R DataWidth:0x20 // FOR DBG: address (32 msb). +#define PSWRQ2_REG_HOQ_RAM_DATA_RD_3_BB_K2 0x240840UL //Access:R DataWidth:0x20 // FOR DBG: bit 0 relaxed ordering; bit 1 no-snoop; bits 5:2 client id; bit 6 done type; bit 7 resevred; bit 10:8 pfid; bit 11 vf_valid; bit 17:12 vfid; bits 20:18 atc flags; bits 31:21 reserved. #define PSWRQ2_REG_SR_CNT_WR_CNT 0x240844UL //Access:R DataWidth:0x20 // The total number of WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done. #define PSWRQ2_REG_SR_CNT_RD_CNT 0x240848UL //Access:R DataWidth:0x20 // The total number of RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done. #define PSWRQ2_REG_SR_CNT_PBF_CNT 0x24084cUL //Access:R DataWidth:0x20 // The number of PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done. #define PSWRQ2_REG_SR_CNT_USDMDP_CNT 0x240850UL //Access:R DataWidth:0x20 // The number of USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done. -#define PSWRQ2_REG_SR_CNT_TREQ_CNT 0x240854UL //Access:R DataWidth:0x20 // The number of TREQ SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done. -#define PSWRQ2_REG_SR_CNT_ICPL_CNT 0x240858UL //Access:R DataWidth:0x20 // The number of ICPL SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done. +#define PSWRQ2_REG_SR_CNT_TREQ_CNT_BB_K2 0x240854UL //Access:R DataWidth:0x20 // The number of TREQ SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done. +#define PSWRQ2_REG_SR_CNT_ICPL_CNT_BB_K2 0x240858UL //Access:R DataWidth:0x20 // The number of ICPL SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done. #define PSWRQ2_REG_SR_CNT_WR_BYTE_LSB 0x24085cUL //Access:R DataWidth:0x20 // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - lsb value. #define PSWRQ2_REG_SR_CNT_WR_BYTE_MSB 0x240860UL //Access:R DataWidth:0x9 // The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - msb value. #define PSWRQ2_REG_SR_CNT_RD_BYTE_LSB 0x240864UL //Access:R DataWidth:0x20 // The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - lsb value. @@ -42852,24 +46208,24 @@ #define PSWRQ2_REG_LAST_RD_SR_LOG_0 0x2408a0UL //Access:R DataWidth:0x20 // SR address - 32 lsb. #define PSWRQ2_REG_LAST_RD_SR_LOG_1 0x2408a4UL //Access:R DataWidth:0x20 // SR address - 32 msb. #define PSWRQ2_REG_LAST_RD_SR_LOG_2 0x2408a8UL //Access:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b31-30: attributes. -#define PSWRQ2_REG_LAST_RD_SR_LOG_3 0x2408acUL //Access:R DataWidth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15: client id; b24-20: vq; b31-25: srid. -#define PSWRQ2_REG_LAST_RD_SR_LOG_4 0x2408b0UL //Access:R DataWidth:0x9 // b1-0: atc code; b3-2: endianity. b8-4: Treq otb entry. +#define PSWRQ2_REG_LAST_RD_SR_LOG_3 0x2408acUL //Access:R DataWidth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15: client id; b24-20: vq; b26-25: endianity; b27-31: reserved; +#define PSWRQ2_REG_LAST_RD_SR_LOG_4 0x2408b0UL //Access:R DataWidth:0x9 // bit 8-0: srid. #define PSWRQ2_REG_LAST_WR_SR_LOG_0 0x2408b4UL //Access:R DataWidth:0x20 // SR address - 32 lsb. #define PSWRQ2_REG_LAST_WR_SR_LOG_1 0x2408b8UL //Access:R DataWidth:0x20 // SR address - 32 msb. #define PSWRQ2_REG_LAST_WR_SR_LOG_2 0x2408bcUL //Access:R DataWidth:0x20 // B15-0: reqid; b28-16: SR length; b29 - reserved; b31-30: attributes. #define PSWRQ2_REG_LAST_WR_SR_LOG_3 0x2408c0UL //Access:R DataWidth:0x20 // B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15: client id; b24-20: vq; b30-25: start offset; b31: usdm err. #define PSWRQ2_REG_LAST_WR_SR_LOG_4 0x2408c4UL //Access:R DataWidth:0xa // b1-0: atc code; b2: wdone type; b4-3: endianity; b9-5: Icpl itag index. -#define PSWRQ2_REG_MSDM_ENTRY_TH 0x2408c8UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to msdm in the queues. -#define PSWRQ2_REG_YSDM_ENTRY_TH 0x2408ccUL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to ysdm in the queues. -#define PSWRQ2_REG_PSDM_ENTRY_TH 0x2408d0UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to psdm in the queues. -#define PSWRQ2_REG_MULD_ENTRY_TH 0x2408d4UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to muld in the queues. -#define PSWRQ2_REG_PTU_ENTRY_TH 0x2408d8UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to ptu in the queues. +#define PSWRQ2_REG_MSDM_ENTRY_TH_BB_K2 0x2408c8UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to msdm in the queues. +#define PSWRQ2_REG_YSDM_ENTRY_TH_BB_K2 0x2408ccUL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to ysdm in the queues. +#define PSWRQ2_REG_PSDM_ENTRY_TH_BB_K2 0x2408d0UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to psdm in the queues. +#define PSWRQ2_REG_MULD_ENTRY_TH_BB_K2 0x2408d4UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to muld in the queues. +#define PSWRQ2_REG_PTU_ENTRY_TH_BB_K2 0x2408d8UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to ptu in the queues. #define PSWRQ2_REG_PTU_PCI_ATTR 0x2408dcUL //Access:RW DataWidth:0x2 // Multi Field Register. #define PSWRQ2_REG_PTU_PCI_ATTR_PTU_RELAXED (0x1<<0) // Relaxed oredering attribute for ptu. #define PSWRQ2_REG_PTU_PCI_ATTR_PTU_RELAXED_SHIFT 0 #define PSWRQ2_REG_PTU_PCI_ATTR_PTU_NOSNOOP (0x1<<1) // Nosnoop attribute for ptu. #define PSWRQ2_REG_PTU_PCI_ATTR_PTU_NOSNOOP_SHIFT 1 -#define PSWRQ2_REG_M2P_ENTRY_TH 0x2408e0UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to m2p in the queues. +#define PSWRQ2_REG_M2P_ENTRY_TH_BB_K2 0x2408e0UL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to m2p in the queues. #define PSWRQ2_REG_M2P_PCI_ATTR 0x2408e4UL //Access:RW DataWidth:0x2 // Multi Field Register. #define PSWRQ2_REG_M2P_PCI_ATTR_M2P_RELAXED (0x1<<0) // Relaxed oredering attribute for m2p. #define PSWRQ2_REG_M2P_PCI_ATTR_M2P_RELAXED_SHIFT 0 @@ -42880,17 +46236,17 @@ #define PSWRQ2_REG_MULD_PCI_ATTR_MULD_RELAXED_SHIFT 0 #define PSWRQ2_REG_MULD_PCI_ATTR_MULD_NOSNOOP (0x1<<1) // Nosnoop attribute for muld. #define PSWRQ2_REG_MULD_PCI_ATTR_MULD_NOSNOOP_SHIFT 1 -#define PSWRQ2_REG_XYLD_ENTRY_TH 0x2408ecUL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to xyld in the queues. +#define PSWRQ2_REG_XYLD_ENTRY_TH_BB_K2 0x2408ecUL //Access:RW DataWidth:0x3 // This number indicates how many entries are guaranteed to xyld in the queues. #define PSWRQ2_REG_XYLD_PCI_ATTR 0x2408f0UL //Access:RW DataWidth:0x2 // Multi Field Register. #define PSWRQ2_REG_XYLD_PCI_ATTR_XYLD_RELAXED (0x1<<0) // Relaxed oredering attribute for xyld. #define PSWRQ2_REG_XYLD_PCI_ATTR_XYLD_RELAXED_SHIFT 0 #define PSWRQ2_REG_XYLD_PCI_ATTR_XYLD_NOSNOOP (0x1<<1) // Nosnoop attribute for xyld. #define PSWRQ2_REG_XYLD_PCI_ATTR_XYLD_NOSNOOP_SHIFT 1 -#define PSWRQ2_REG_ATC_MSDM_FLAGS 0x2408f4UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_YSDM_FLAGS 0x2408f8UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_PSDM_FLAGS 0x2408fcUL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_MULD_FLAGS 0x240900UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. -#define PSWRQ2_REG_ATC_XYLD_FLAGS 0x240904UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_MSDM_FLAGS_BB_K2 0x2408f4UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_YSDM_FLAGS_BB_K2 0x2408f8UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_PSDM_FLAGS_BB_K2 0x2408fcUL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_MULD_FLAGS_BB_K2 0x240900UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. +#define PSWRQ2_REG_ATC_XYLD_FLAGS_BB_K2 0x240904UL //Access:RW DataWidth:0x4 // ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request. #define PSWRQ2_REG_RMM_ENABLE 0x240908UL //Access:RW DataWidth:0x1 // Debug only. Writing this register from 0 to 1 enables the roundtrip measurement mechanism and resets the registers latest_rtt ,max_hold_rtt, min_hold_rtt, num_of_measurements. #define PSWRQ2_REG_LATEST_RTT 0x24090cUL //Access:R DataWidth:0x20 // Debug only. Round trip measurement of latest request that was measured. Measured in clk_pci cycles (375 MHz). #define PSWRQ2_REG_MAX_HOLD_RTT 0x240910UL //Access:R DataWidth:0x20 // Debug only. Maximal round trip measurement value from the time rmm_enable register was written with '1'. Measured in clk_pci cycles (375 MHz). @@ -42904,210 +46260,301 @@ #define PSWRQ2_REG_L2P_ERR_DETAILS 0x240930UL //Access:R DataWidth:0x1a // Details of first request that triggered rq_l2p_vf_err or rq_elt_addr interrupt. [12:0] - Length in bytes. [16:13] - PFID. [17] - VF_VALID. [25:18] - VFID. #define PSWRQ2_REG_L2P_ERR_DETAILS2 0x240934UL //Access:R DataWidth:0x1d // Details of first request that triggered rq_l2p_vf_err or rq_elt_addr interrupt. [15:0] Request ID. [20:16] client ID. [21] - Error type - 0 - rq_l2p_vf_err; 1 - rq_elt_addr. [22] - w_nr - 0 - read; 1 - write.[27:23]VQID. [28] valid - indicates if there was a request not submitted due to error since the last time this register was cleared. #define PSWRQ2_REG_L2P_ERR_DETAILS_CLR 0x240938UL //Access:W DataWidth:0x1 // Writing to this register clears rq_l2p_err registers and enables logging new error details. -#define PSWRQ2_REG_SR_NUM_CFG 0x24093cUL //Access:RW DataWidth:0x7 // Debug only: Total number of available PCI read sub-requests. Must be bigger than 1. Normally should not be changed. -#define PSWRQ2_REG_BLK_NUM_CFG 0x240940UL //Access:RW DataWidth:0x9 // Debug only: Total number of available blocks in Tetris Buffer. Must be bigger than 6. Normally should not be changed. -#define PSWRQ2_REG_MAX_BLKS_VQ0 0x240944UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ1 0x240948UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ2 0x24094cUL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ3 0x240950UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ4 0x240954UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ5 0x240958UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ6 0x24095cUL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ7 0x240960UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ8 0x240964UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ9 0x240968UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ10 0x24096cUL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ11 0x240970UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ12 0x240974UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ13 0x240978UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ14 0x24097cUL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ15 0x240980UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ16 0x240984UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ17 0x240988UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ18 0x24098cUL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ19 0x240990UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ20 0x240994UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ21 0x240998UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ22 0x24099cUL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ23 0x2409a0UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ24 0x2409a4UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ25 0x2409a8UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ26 0x2409acUL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ27 0x2409b0UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ28 0x2409b4UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_MAX_BLKS_VQ29 0x2409b8UL //Access:RW DataWidth:0x9 // Not used. VQ29 is not used for read. -#define PSWRQ2_REG_MAX_BLKS_VQ30 0x2409bcUL //Access:RW DataWidth:0x9 // Not used. VQ30 is not used for read. -#define PSWRQ2_REG_MAX_BLKS_VQ31 0x2409c0UL //Access:RW DataWidth:0x9 // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. -#define PSWRQ2_REG_SR_CNT 0x2409c4UL //Access:R DataWidth:0x7 // Debug only: The SR counter - number of unused sub request ids. Field and register name used to be rd. -#define PSWRQ2_REG_SR_CNT_PER_VQ_0 0x2409c8UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_1 0x2409ccUL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_2 0x2409d0UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_3 0x2409d4UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_4 0x2409d8UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_5 0x2409dcUL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_6 0x2409e0UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_7 0x2409e4UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_8 0x2409e8UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_9 0x2409ecUL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_10 0x2409f0UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_11 0x2409f4UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_12 0x2409f8UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_13 0x2409fcUL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_14 0x240a00UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_15 0x240a04UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_16 0x240a08UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_17 0x240a0cUL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_18 0x240a10UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_19 0x240a14UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_20 0x240a18UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_21 0x240a1cUL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_22 0x240a20UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_23 0x240a24UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_24 0x240a28UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_25 0x240a2cUL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_26 0x240a30UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_27 0x240a34UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_28 0x240a38UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_29 0x240a3cUL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_30 0x240a40UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_SR_CNT_PER_VQ_31 0x240a44UL //Access:R DataWidth:0x7 // Debug only: The SR counter per vq. -#define PSWRQ2_REG_BLK_CNT 0x240a48UL //Access:R DataWidth:0x9 // Debug only: The blocks counter - number of unused block ids. Field and register name used to be rd. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_0 0x240a4cUL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_1 0x240a50UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_2 0x240a54UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_3 0x240a58UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_4 0x240a5cUL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_5 0x240a60UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_6 0x240a64UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_7 0x240a68UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_8 0x240a6cUL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_9 0x240a70UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_10 0x240a74UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_11 0x240a78UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_12 0x240a7cUL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_13 0x240a80UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_14 0x240a84UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_15 0x240a88UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_16 0x240a8cUL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_17 0x240a90UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_18 0x240a94UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_19 0x240a98UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_20 0x240a9cUL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_21 0x240aa0UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_22 0x240aa4UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_23 0x240aa8UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_24 0x240aacUL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_25 0x240ab0UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_26 0x240ab4UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_27 0x240ab8UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_28 0x240abcUL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_29 0x240ac0UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_30 0x240ac4UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_BLK_CNT_PER_VQ_31 0x240ac8UL //Access:R DataWidth:0x9 // Debug only: The blocks counter per vq. -#define PSWRQ2_REG_CNT_BYTE_0 0x240accUL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_BYTE_1 0x240ad0UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_BYTE_2 0x240ad4UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_BYTE_3 0x240ad8UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_BYTE_4 0x240adcUL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_BYTE_5 0x240ae0UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_BYTE_6 0x240ae4UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_BYTE_7 0x240ae8UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_BYTE_8 0x240aecUL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_BYTE_9 0x240af0UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_BYTE_10 0x240af4UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_BYTE_11 0x240af8UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_BYTE_12 0x240afcUL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_BYTE_13 0x240b00UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_BYTE_14 0x240b04UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_EOP_0 0x240b08UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_EOP_1 0x240b0cUL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_EOP_2 0x240b10UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_EOP_3 0x240b14UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_EOP_4 0x240b18UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_EOP_5 0x240b1cUL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_EOP_6 0x240b20UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_EOP_7 0x240b24UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_EOP_8 0x240b28UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_EOP_9 0x240b2cUL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_EOP_10 0x240b30UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_EOP_11 0x240b34UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_EOP_12 0x240b38UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_EOP_13 0x240b3cUL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_CNT_EOP_14 0x240b40UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14. -#define PSWRQ2_REG_MAX_SRS_VQ0 0x240b44UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ1 0x240b48UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ2 0x240b4cUL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ3 0x240b50UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ4 0x240b54UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ5 0x240b58UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ6 0x240b5cUL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ7 0x240b60UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ8 0x240b64UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ9 0x240b68UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ10 0x240b6cUL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ11 0x240b70UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ12 0x240b74UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ13 0x240b78UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ14 0x240b7cUL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ15 0x240b80UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ16 0x240b84UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ17 0x240b88UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ18 0x240b8cUL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ19 0x240b90UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ20 0x240b94UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ21 0x240b98UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ22 0x240b9cUL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ23 0x240ba0UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ24 0x240ba4UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ25 0x240ba8UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ26 0x240bacUL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ27 0x240bb0UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ28 0x240bb4UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ29 0x240bb8UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ30 0x240bbcUL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_MAX_SRS_VQ31 0x240bc0UL //Access:RW DataWidth:0x7 // The maximum number of sub-requests that can be allocated for this vq. -#define PSWRQ2_REG_REQIF_DEL_DELAY 0x240bc4UL //Access:RW DataWidth:0x3 // Number of delay cycles on the reqif del indication. +#define PSWRQ2_REG_SR_NUM_CFG 0x24093cUL //Access:RW DataWidth:0x9 // Debug only: Total number of available PCI read sub-requests. Must be bigger than 1. Normally should not be changed. +#define PSWRQ2_REG_BLK_NUM_CFG 0x240940UL //Access:RW DataWidth:0xa // Debug only: Total number of available blocks in Tetris Buffer. Must be bigger than 6. Normally should not be changed. +#define PSWRQ2_REG_MAX_BLKS_VQ0 0x240944UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ1 0x240948UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ2 0x24094cUL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ3 0x240950UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ4 0x240954UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ5 0x240958UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ6 0x24095cUL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ7 0x240960UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ8 0x240964UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ9 0x240968UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ10 0x24096cUL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ11 0x240970UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ12 0x240974UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ13 0x240978UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ14 0x24097cUL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ15 0x240980UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ16 0x240984UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ17 0x240988UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ18 0x24098cUL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ19 0x240990UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ20 0x240994UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ21 0x240998UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ22 0x24099cUL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ23 0x2409a0UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ24 0x2409a4UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ25 0x2409a8UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ26 0x2409acUL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ27 0x2409b0UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ28 0x2409b4UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_MAX_BLKS_VQ29 0x2409b8UL //Access:RW DataWidth:0xa // Not used. VQ29 is not used for read. +#define PSWRQ2_REG_MAX_BLKS_VQ30 0x2409bcUL //Access:RW DataWidth:0xa // Not used. VQ30 is not used for read. +#define PSWRQ2_REG_MAX_BLKS_VQ31 0x2409c0UL //Access:RW DataWidth:0xa // The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD. +#define PSWRQ2_REG_SR_CNT 0x2409c4UL //Access:R DataWidth:0x9 // Debug only: The SR counter - number of unused sub request ids. Field and register name used to be rd. +#define PSWRQ2_REG_SR_CNT_PER_VQ_0 0x2409c8UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_1 0x2409ccUL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_2 0x2409d0UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_3 0x2409d4UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_4 0x2409d8UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_5 0x2409dcUL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_6 0x2409e0UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_7 0x2409e4UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_8 0x2409e8UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_9 0x2409ecUL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_10 0x2409f0UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_11 0x2409f4UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_12 0x2409f8UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_13 0x2409fcUL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_14 0x240a00UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_15 0x240a04UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_16 0x240a08UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_17 0x240a0cUL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_18 0x240a10UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_19 0x240a14UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_20 0x240a18UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_21 0x240a1cUL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_22 0x240a20UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_23 0x240a24UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_24 0x240a28UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_25 0x240a2cUL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_26 0x240a30UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_27 0x240a34UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_28 0x240a38UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_29 0x240a3cUL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_30 0x240a40UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_SR_CNT_PER_VQ_31 0x240a44UL //Access:R DataWidth:0x9 // Debug only: The SR counter per vq. +#define PSWRQ2_REG_BLK_CNT 0x240a48UL //Access:R DataWidth:0xa // Debug only: The blocks counter - number of unused block ids. Field and register name used to be rd. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_0 0x240a4cUL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_1 0x240a50UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_2 0x240a54UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_3 0x240a58UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_4 0x240a5cUL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_5 0x240a60UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_6 0x240a64UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_7 0x240a68UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_8 0x240a6cUL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_9 0x240a70UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_10 0x240a74UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_11 0x240a78UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_12 0x240a7cUL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_13 0x240a80UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_14 0x240a84UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_15 0x240a88UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_16 0x240a8cUL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_17 0x240a90UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_18 0x240a94UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_19 0x240a98UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_20 0x240a9cUL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_21 0x240aa0UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_22 0x240aa4UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_23 0x240aa8UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_24 0x240aacUL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_25 0x240ab0UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_26 0x240ab4UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_27 0x240ab8UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_28 0x240abcUL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_29 0x240ac0UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_30 0x240ac4UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_BLK_CNT_PER_VQ_31 0x240ac8UL //Access:R DataWidth:0xa // Debug only: The blocks counter per vq. +#define PSWRQ2_REG_CNT_BYTE_0 0x240accUL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of TSDM +#define PSWRQ2_REG_CNT_BYTE_1 0x240ad0UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of MSDM +#define PSWRQ2_REG_CNT_BYTE_2 0x240ad4UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of USDM +#define PSWRQ2_REG_CNT_BYTE_3 0x240ad8UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of XSDM +#define PSWRQ2_REG_CNT_BYTE_4 0x240adcUL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of YSDM +#define PSWRQ2_REG_CNT_BYTE_5 0x240ae0UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of PSDM +#define PSWRQ2_REG_CNT_BYTE_6 0x240ae4UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of QM 6 +#define PSWRQ2_REG_CNT_BYTE_7 0x240ae8UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of TM +#define PSWRQ2_REG_CNT_BYTE_8 0x240aecUL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of SRC +#define PSWRQ2_REG_CNT_BYTE_9 0x240af0UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of DMAE +#define PSWRQ2_REG_CNT_BYTE_10 0x240af4UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of PRM +#define PSWRQ2_REG_CNT_BYTE_11 0x240af8UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of HC +#define PSWRQ2_REG_CNT_BYTE_12 0x240afcUL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of CDUWR +#define PSWRQ2_REG_CNT_BYTE_13 0x240b00UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of DBG +#define PSWRQ2_REG_CNT_BYTE_14 0x240b04UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of M2P +#define PSWRQ2_REG_CNT_EOP_0 0x240b08UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of TSDM +#define PSWRQ2_REG_CNT_EOP_1 0x240b0cUL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of MSDM +#define PSWRQ2_REG_CNT_EOP_2 0x240b10UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of USDM +#define PSWRQ2_REG_CNT_EOP_3 0x240b14UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of XSDM +#define PSWRQ2_REG_CNT_EOP_4 0x240b18UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of YSDM +#define PSWRQ2_REG_CNT_EOP_5 0x240b1cUL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of PSDM +#define PSWRQ2_REG_CNT_EOP_6 0x240b20UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of QM +#define PSWRQ2_REG_CNT_EOP_7 0x240b24UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of TM +#define PSWRQ2_REG_CNT_EOP_8 0x240b28UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of SRC +#define PSWRQ2_REG_CNT_EOP_9 0x240b2cUL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of DMAE +#define PSWRQ2_REG_CNT_EOP_10 0x240b30UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of PRM +#define PSWRQ2_REG_CNT_EOP_11 0x240b34UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of HC +#define PSWRQ2_REG_CNT_EOP_12 0x240b38UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of CDUWR +#define PSWRQ2_REG_CNT_EOP_13 0x240b3cUL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of DBG +#define PSWRQ2_REG_CNT_EOP_14 0x240b40UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of M2P +#define PSWRQ2_REG_MAX_SRS_VQ0 0x240b44UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ1 0x240b48UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ2 0x240b4cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ3 0x240b50UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ4 0x240b54UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ5 0x240b58UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ6 0x240b5cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ7 0x240b60UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ8 0x240b64UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ9 0x240b68UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ10 0x240b6cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ11 0x240b70UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ12 0x240b74UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ13 0x240b78UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ14 0x240b7cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ15 0x240b80UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ16 0x240b84UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ17 0x240b88UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ18 0x240b8cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ19 0x240b90UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ20 0x240b94UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ21 0x240b98UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ22 0x240b9cUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ23 0x240ba0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ24 0x240ba4UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ25 0x240ba8UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ26 0x240bacUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ27 0x240bb0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ28 0x240bb4UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ29 0x240bb8UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ30 0x240bbcUL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_MAX_SRS_VQ31 0x240bc0UL //Access:RW DataWidth:0x9 // The maximum number of sub-requests that can be allocated for this vq. +#define PSWRQ2_REG_REQIF_DEL_DELAY_BB_K2 0x240bc4UL //Access:RW DataWidth:0x3 // Number of delay cycles on the reqif del indication. #define PSWRQ2_REG_L2P_CLOSE_GATE_STS 0x240bc8UL //Access:RW DataWidth:0x1 // L2P error close the gate status register. #define PSWRQ2_REG_MISC_CLOSE_GATE_STS 0x240bccUL //Access:R DataWidth:0x1 // MISC close the gate status register. 1 indicates the gates are closed. #define PSWRQ2_REG_MISC_STALL_MEM_STS 0x240bd0UL //Access:R DataWidth:0x1 // MISC stall mem status register. 1 indicates stall mem is active. #define PSWRQ2_REG_GARB_STRICT_PRIORITY_FOR_READS 0x240bd4UL //Access:RW DataWidth:0x1 // GARB config: 1 indicates read SRs have strict priority over write SRs in RW arbiter. #define PSWRQ2_REG_GARB_NEGATIVE_BWC_MODE 0x240bd8UL //Access:RW DataWidth:0x1 // GARB config: 1 indicates BWCs can become negative. Clients with negative BWCs are not chosen. Default value: 1. #define PSWRQ2_REG_GARB_GNT_ABOVE_LIMIT_ONLY_MODE 0x240bdcUL //Access:RW DataWidth:0x1 // GARB config: 1 indicates that only clients with BWC greater or equal to Li are chosen. 0 indicates that clients with BWC greater or equal to 0 can be chosen if no BWC is greater or equal to Li. Default value: 0. This is a chicken bit in case there are problems/bugs when choosing clients with BWC less than Li. -#define PSWRQ2_REG_GARB_VQ_2_STRICT_LSB 0x240be0UL //Access:RW DataWidth:0x20 // GARB config: mapping of VQ to strict priority: 0 - the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW counters); 1 - the VQ has strict priority; VQ32 = TREQ; VQ33 = ICPL; NOTE: the VQ-s associated with strict priority slot should match the configuration in garb_strict0_2_vq or garb_strict1_2_vq;. -#define PSWRQ2_REG_GARB_VQ_2_STRICT_MSB 0x240be4UL //Access:RW DataWidth:0x2 // GARB config: mapping of VQ to strict priority: 0 - the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW counters); 1 - the VQ has strict priority; VQ32 = TREQ; VQ33 = ICPL; NOTE: the VQ-s associated with strict priority slot should match the configuration in garb_strict0_2_vq or garb_strict1_2_vq;. -#define PSWRQ2_REG_GARB_STRICT0_2_VQ_0 0x240be8UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). -#define PSWRQ2_REG_GARB_STRICT0_2_VQ_1 0x240becUL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). -#define PSWRQ2_REG_GARB_STRICT0_2_VQ_2 0x240bf0UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). -#define PSWRQ2_REG_GARB_STRICT0_2_VQ_3 0x240bf4UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). -#define PSWRQ2_REG_GARB_STRICT0_2_VQ_4 0x240bf8UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). -#define PSWRQ2_REG_GARB_STRICT0_2_VQ_5 0x240bfcUL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). -#define PSWRQ2_REG_GARB_STRICT0_2_VQ_6 0x240c00UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). -#define PSWRQ2_REG_GARB_STRICT0_2_VQ_7 0x240c04UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). -#define PSWRQ2_REG_GARB_STRICT1_2_VQ_0 0x240c08UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). -#define PSWRQ2_REG_GARB_STRICT1_2_VQ_1 0x240c0cUL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). -#define PSWRQ2_REG_GARB_STRICT1_2_VQ_2 0x240c10UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). -#define PSWRQ2_REG_GARB_STRICT1_2_VQ_3 0x240c14UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). -#define PSWRQ2_REG_GARB_STRICT1_2_VQ_4 0x240c18UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). -#define PSWRQ2_REG_GARB_STRICT1_2_VQ_5 0x240c1cUL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). -#define PSWRQ2_REG_GARB_STRICT1_2_VQ_6 0x240c20UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). -#define PSWRQ2_REG_GARB_STRICT1_2_VQ_7 0x240c24UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). +#define PSWRQ2_REG_GARB_VQ_2_STRICT_LSB 0x240be0UL //Access:RW DataWidth:0x20 // GARB config: mapping of VQ to strict priority: 0 - the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW counters); 1 - the VQ has strict priority; NOTE: the VQ-s associated with strict priority slot should match the configuration in garb_strict0_2_vq or garb_strict1_2_vq;. +#define PSWRQ2_REG_GARB_VQ_2_STRICT_MSB_BB_K2 0x240be4UL //Access:RW DataWidth:0x2 // GARB config: mapping of VQ to strict priority: 0 - the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW counters); 1 - the VQ has strict priority; VQ32 = TREQ; VQ33 = ICPL; NOTE: the VQ-s associated with strict priority slot should match the configuration in garb_strict0_2_vq or garb_strict1_2_vq;. +#define PSWRQ2_REG_GARB_STRICT0_2_VQ_0 0x240be8UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). +#define PSWRQ2_REG_GARB_STRICT0_2_VQ_1 0x240becUL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). +#define PSWRQ2_REG_GARB_STRICT0_2_VQ_2 0x240bf0UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). +#define PSWRQ2_REG_GARB_STRICT0_2_VQ_3 0x240bf4UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). +#define PSWRQ2_REG_GARB_STRICT0_2_VQ_4 0x240bf8UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). +#define PSWRQ2_REG_GARB_STRICT0_2_VQ_5 0x240bfcUL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). +#define PSWRQ2_REG_GARB_STRICT0_2_VQ_6 0x240c00UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). +#define PSWRQ2_REG_GARB_STRICT0_2_VQ_7 0x240c04UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 0 (high priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). +#define PSWRQ2_REG_GARB_STRICT1_2_VQ_0 0x240c08UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). +#define PSWRQ2_REG_GARB_STRICT1_2_VQ_1 0x240c0cUL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). +#define PSWRQ2_REG_GARB_STRICT1_2_VQ_2 0x240c10UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). +#define PSWRQ2_REG_GARB_STRICT1_2_VQ_3 0x240c14UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). +#define PSWRQ2_REG_GARB_STRICT1_2_VQ_4 0x240c18UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). +#define PSWRQ2_REG_GARB_STRICT1_2_VQ_5 0x240c1cUL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). +#define PSWRQ2_REG_GARB_STRICT1_2_VQ_6 0x240c20UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). +#define PSWRQ2_REG_GARB_STRICT1_2_VQ_7 0x240c24UL //Access:RW DataWidth:0x7 // GARB config: mapping of strict priority 1 (low priority) to VQ: bits 4:0 - the VQ id; bit6 - validates the VQ association; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1). #define PSWRQ2_REG_CREDIT_WR_STS 0x240c28UL //Access:R DataWidth:0x1 // The status of the PSWRQ-PGLUE request interface write credit; 0 - no more credit for wr SR-s (i.e. write SR-s cannot be sent to the PGLUE); 1 - credit is greater than 0 for wr SR-s (i.e. more write SR-s can be sent to the PGLUE). #define PSWRQ2_REG_CREDIT_RD_STS 0x240c2cUL //Access:R DataWidth:0x1 // The status of the PSWRQ-PGLUE request interface read credit; 0 - no more credit for rd SR-s (i.e. read SR-s cannot be sent to the PGLUE); 1 - credit is greater than 0 for rd SR-s (i.e. more read SR-s can be sent to the PGLUE). -#define PSWRQ2_REG_WAIT_FOR_EOP 0x240c30UL //Access:RW DataWidth:0xf // Per client store_and_forward configuration. When set it will only enable to submit a write request when eop arrived. This can be a workaround for possible bugs in the byte counters. Id-s are based on wr client id-s (taken from pswrq_funcs.v). -#define PSWRQ2_REG_ADD2Q_2_DELHOQ0_DELAY 0x240c34UL //Access:RW DataWidth:0x3 // LSI purpose: the number of [cycles-1] between qc_cmg_add_2_q (indication that new request is written into hoq0) and cmg_qc_del_head (delete request sent by the cmg towards hoq0). This register should be touched unless there is non-expected HW limitation within the QC. value of N means that there are N dead cycles between qc_cmg_add_2_q and cmg_qc_del_head. -#define PSWRQ2_REG_DELHOQ0_2_DELHOQ0_DELAY_0 0x240c38UL //Access:RW DataWidth:0x4 // LSI purpose: the minimum allowed number of [cycles-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_head for the same VQ. This register should be touched unless there is non-expected HW limitation within the QC. value of N means that there are N dead cycles between 2 adjacent requests. -#define PSWRQ2_REG_DELHOQ0_2_DELHOQ0_DELAY_1 0x240c3cUL //Access:RW DataWidth:0x4 // LSI purpose: the minimum allowed number of [cycles-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_head for different VQ. This register should be touched unless there is non-expected HW limitation within the QC. value of N means that there are N dead cycles between 2 adjacent requests. +#define PSWRQ2_REG_WAIT_FOR_EOP 0x240c30UL //Access:RW DataWidth:0x12 // Per client store_and_forward configuration. When set it will only enable to submit a write request when eop arrived. This can be a workaround for possible bugs in the byte counters. Id-s are based on wr client id-s (taken from pswrq_funcs.v). +#define PSWRQ2_REG_ADD2Q_2_DELHOQ0_DELAY_BB_K2 0x240c34UL //Access:RW DataWidth:0x3 // LSI purpose: the number of [cycles-1] between qc_cmg_add_2_q (indication that new request is written into hoq0) and cmg_qc_del_head (delete request sent by the cmg towards hoq0). This register should be touched unless there is non-expected HW limitation within the QC. value of N means that there are N dead cycles between qc_cmg_add_2_q and cmg_qc_del_head. +#define PSWRQ2_REG_DELHOQ0_2_DELHOQ0_DELAY_0_BB_K2 0x240c38UL //Access:RW DataWidth:0x4 // LSI purpose: the minimum allowed number of [cycles-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_head for the same VQ. This register should be touched unless there is non-expected HW limitation within the QC. value of N means that there are N dead cycles between 2 adjacent requests. +#define PSWRQ2_REG_DELHOQ0_2_DELHOQ0_DELAY_1_BB_K2 0x240c3cUL //Access:RW DataWidth:0x4 // LSI purpose: the minimum allowed number of [cycles-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_head for different VQ. This register should be touched unless there is non-expected HW limitation within the QC. value of N means that there are N dead cycles between 2 adjacent requests. #define PSWRQ2_REG_PDR_CNT 0x240c40UL //Access:R DataWidth:0xe // For debug and Idle-check use. The value of the PDR counter. #define PSWRQ2_REG_CHECK_RESOURCES_FOR_THE_ENTIRE_REQ 0x240c44UL //Access:RW DataWidth:0x6 // Will be used for OOO clients deadlock prevention. indicating if to submit the first SR of a request only when there are enough SRIDs and blocks for the entire request. bit0: TSDM; bit1: MSDM; bit2: USDM; bit3: XSDM; bit4: YSDM; bit5: PSDM. #define PSWRQ2_REG_RW_ORDERING_DISABLE_WR_THR 0x240c48UL //Access:RW DataWidth:0x6 // LSI purpose: the threshold for the max number of pending wr requests sent to the PGLUE (i.e. sent to the PGLUE and did not receive write done for them from the PGLUE). Upon reaching the threshold no more wr SR-s will be sent by the PSWRQ to the PGLUE until receiving write done for the previous requests. #define PSWRQ2_REG_ECO_RESERVED 0x240c4cUL //Access:RW DataWidth:0x6 // Debug only: Reserved bits for ECO. #define PSWRQ2_REG_L2P_VALIDATE_VFID 0x240c50UL //Access:RW DataWidth:0x1 // Enables VFID validate check +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ0_E5 0x240c54UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 0 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ1_E5 0x240c58UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 1 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ2_E5 0x240c5cUL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 2 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ3_E5 0x240c60UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 3 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ4_E5 0x240c64UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 4 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ5_E5 0x240c68UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 5 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ6_E5 0x240c6cUL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 6 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ7_E5 0x240c70UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 7 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ8_E5 0x240c74UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 8 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ9_E5 0x240c78UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 9 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ10_E5 0x240c7cUL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 10 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ11_E5 0x240c80UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 11 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ12_E5 0x240c84UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 12 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ13_E5 0x240c88UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 13 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ14_E5 0x240c8cUL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 14 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ15_E5 0x240c90UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 15 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ16_E5 0x240c94UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 16 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ17_E5 0x240c98UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 17 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ18_E5 0x240c9cUL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 18 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ19_E5 0x240ca0UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 19 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ20_E5 0x240ca4UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 20 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ21_E5 0x240ca8UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 21 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ22_E5 0x240cacUL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 22 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ23_E5 0x240cb0UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 23 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ24_E5 0x240cb4UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 24 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ25_E5 0x240cb8UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 25 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ26_E5 0x240cbcUL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 26 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ27_E5 0x240cc0UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 27 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ28_E5 0x240cc4UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 28 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ29_E5 0x240cc8UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 29 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ30_E5 0x240cccUL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 30 +#define PSWRQ2_REG_MEM_BASE_ADDR_VQ31_E5 0x240cd0UL //Access:RW DataWidth:0x9 // Memory base address for VQ FIFO 31 +#define PSWRQ2_REG_TSDM_TO_VQ_MAP_E5 0x240cd4UL //Access:RW DataWidth:0x9 // If bit is set, client can push request to this VQ. Map TSDM to VQs: bit 0 is mapped to VQID 6. bit 1 is mapped to VQID 7. bit 2 is mapped to VQID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is mapped to VQID 11. bit 6 is mapped to VQID 14. bit 7 is mapped to VQID 19. bit 8 is mapped to VQID 31. +#define PSWRQ2_REG_MSDM_TO_VQ_MAP_E5 0x240cd8UL //Access:RW DataWidth:0x9 // If bit is set, client can push request to this VQ. Map MSDM to VQs: bit 0 is mapped to VQID 6. bit 1 is mapped to VQID 7. bit 2 is mapped to VQID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is mapped to VQID 11. bit 6 is mapped to VQID 14. bit 7 is mapped to VQID 19. bit 8 is mapped to VQID 31. +#define PSWRQ2_REG_USDM_TO_VQ_MAP_E5 0x240cdcUL //Access:RW DataWidth:0x9 // If bit is set, client can push request to this VQ. Map USDM to VQs: bit 0 is mapped to VQID 6. bit 1 is mapped to VQID 7. bit 2 is mapped to VQID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is mapped to VQID 11. bit 6 is mapped to VQID 14. bit 7 is mapped to VQID 19. bit 8 is mapped to VQID 31. +#define PSWRQ2_REG_XSDM_TO_VQ_MAP_E5 0x240ce0UL //Access:RW DataWidth:0x9 // If bit is set, client can push request to this VQ. Map XSDM to VQs: bit 0 is mapped to VQID 6. bit 1 is mapped to VQID 7. bit 2 is mapped to VQID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is mapped to VQID 11. bit 6 is mapped to VQID 14. bit 7 is mapped to VQID 19. bit 8 is mapped to VQID 31. +#define PSWRQ2_REG_YSDM_TO_VQ_MAP_E5 0x240ce4UL //Access:RW DataWidth:0x9 // If bit is set, client can push request to this VQ. Map YSDM to VQs: bit 0 is mapped to VQID 6. bit 1 is mapped to VQID 7. bit 2 is mapped to VQID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is mapped to VQID 11. bit 6 is mapped to VQID 14. bit 7 is mapped to VQID 19. bit 8 is mapped to VQID 31. +#define PSWRQ2_REG_PSDM_TO_VQ_MAP_E5 0x240ce8UL //Access:RW DataWidth:0x9 // If bit is set, client can push request to this VQ. Map PSDM to VQs: bit 0 is mapped to VQID 6. bit 1 is mapped to VQID 7. bit 2 is mapped to VQID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 10. bit 5 is mapped to VQID 11. bit 6 is mapped to VQID 14. bit 7 is mapped to VQID 19. bit 8 is mapped to VQID 31. +#define PSWRQ2_REG_M2P_TO_VQ_MAP_E5 0x240cecUL //Access:RW DataWidth:0x7 // If bit is set, client can push request to this VQ. Map M2P to VQs: bit 0 is mapped to VQID 6. bit 1 is mapped to VQID 7. bit 2 is mapped to VQID 8. bit 3 is mapped to VQID 9. bit 4 is mapped to VQID 14. bit 5 is mapped to VQID 28. bit 6 is mapped to VQID 31. +#define PSWRQ2_REG_TGSRC_PCI_ATTR_E5 0x240cf0UL //Access:RW DataWidth:0x2 // Multi Field Register. + #define PSWRQ2_REG_TGSRC_PCI_ATTR_TGSRC_RELAXED_E5 (0x1<<0) // Relaxed oredering attribute for tgsrc. + #define PSWRQ2_REG_TGSRC_PCI_ATTR_TGSRC_RELAXED_E5_SHIFT 0 + #define PSWRQ2_REG_TGSRC_PCI_ATTR_TGSRC_NOSNOOP_E5 (0x1<<1) // Nosnoop attribute for tgsrc. + #define PSWRQ2_REG_TGSRC_PCI_ATTR_TGSRC_NOSNOOP_E5_SHIFT 1 +#define PSWRQ2_REG_RGSRC_PCI_ATTR_E5 0x240cf4UL //Access:RW DataWidth:0x2 // Multi Field Register. + #define PSWRQ2_REG_RGSRC_PCI_ATTR_RGSRC_RELAXED_E5 (0x1<<0) // Relaxed oredering attribute for rgsrc. + #define PSWRQ2_REG_RGSRC_PCI_ATTR_RGSRC_RELAXED_E5_SHIFT 0 + #define PSWRQ2_REG_RGSRC_PCI_ATTR_RGSRC_NOSNOOP_E5 (0x1<<1) // Nosnoop attribute for rgsrc. + #define PSWRQ2_REG_RGSRC_PCI_ATTR_RGSRC_NOSNOOP_E5_SHIFT 1 +#define PSWRQ2_REG_PRMS_PCI_ATTR_E5 0x240cf8UL //Access:RW DataWidth:0x2 // Multi Field Register. + #define PSWRQ2_REG_PRMS_PCI_ATTR_PRMS_RELAXED_E5 (0x1<<0) // Relaxed oredering attribute for prm secondary. + #define PSWRQ2_REG_PRMS_PCI_ATTR_PRMS_RELAXED_E5_SHIFT 0 + #define PSWRQ2_REG_PRMS_PCI_ATTR_PRMS_NOSNOOP_E5 (0x1<<1) // Nosnoop attribute for prm secondary. + #define PSWRQ2_REG_PRMS_PCI_ATTR_PRMS_NOSNOOP_E5_SHIFT 1 +#define PSWRQ2_REG_TGSRC_P_SIZE_E5 0x240cfcUL //Access:RW DataWidth:0x4 // Page size in L2P table for tgsrc module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M. +#define PSWRQ2_REG_RGSRC_P_SIZE_E5 0x240d00UL //Access:RW DataWidth:0x4 // Page size in L2P table for RGSRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M. +#define PSWRQ2_REG_TGSRC_FIRST_ILT_E5 0x240d04UL //Access:RW DataWidth:0xe // First memory address base for tgsrc in ILT. +#define PSWRQ2_REG_RGSRC_FIRST_ILT_E5 0x240d08UL //Access:RW DataWidth:0xe // First memory address base for rgsrc in ILT. +#define PSWRQ2_REG_TGSRC_LAST_ILT_E5 0x240d0cUL //Access:RW DataWidth:0xe // Last memory address base for tgsrc in ILT. +#define PSWRQ2_REG_RGSRC_LAST_ILT_E5 0x240d10UL //Access:RW DataWidth:0xe // Last memory address base for rgsrc in ILT. +#define PSWRQ2_REG_CNT_EOP_15_E5 0x240d14UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of TGSRC +#define PSWRQ2_REG_CNT_EOP_16_E5 0x240d18UL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of RGSRC +#define PSWRQ2_REG_CNT_EOP_17_E5 0x240d1cUL //Access:R DataWidth:0x8 // Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of PRM Seconadaty +#define PSWRQ2_REG_CNT_BYTE_15_E5 0x240d20UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of TGSRC +#define PSWRQ2_REG_CNT_BYTE_16_E5 0x240d24UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of RGSRC +#define PSWRQ2_REG_CNT_BYTE_17_E5 0x240d28UL //Access:R DataWidth:0xe // Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of PRM Seconadaty +#define PSWRQ2_REG_FILL_LEVEL_CDURD_E5 0x240d2cUL //Access:R DataWidth:0x3 // fill level of cdurd client. +#define PSWRQ2_REG_FILL_LEVEL_CDUWR_E5 0x240d30UL //Access:R DataWidth:0x3 // fill level of cduwr client. +#define PSWRQ2_REG_FILL_LEVEL_DBG_E5 0x240d34UL //Access:R DataWidth:0x2 // fill level of dbg client. +#define PSWRQ2_REG_FILL_LEVEL_DMAE_E5 0x240d38UL //Access:R DataWidth:0x2 // fill level of dmae client. +#define PSWRQ2_REG_FILL_LEVEL_HC_E5 0x240d3cUL //Access:R DataWidth:0x2 // fill level of hc client. +#define PSWRQ2_REG_FILL_LEVEL_MSDM_E5 0x240d40UL //Access:R DataWidth:0x2 // fill level of msdm client. +#define PSWRQ2_REG_FILL_LEVEL_MULD_E5 0x240d44UL //Access:R DataWidth:0x3 // fill level of muld client. +#define PSWRQ2_REG_FILL_LEVEL_PBF_E5 0x240d48UL //Access:R DataWidth:0x3 // fill level of pbf client. +#define PSWRQ2_REG_FILL_LEVEL_PRM_E5 0x240d4cUL //Access:R DataWidth:0x3 // fill level of prm client. +#define PSWRQ2_REG_FILL_LEVEL_PSDM_E5 0x240d50UL //Access:R DataWidth:0x2 // fill level of psdm client. +#define PSWRQ2_REG_FILL_LEVEL_QM_E5 0x240d54UL //Access:R DataWidth:0x2 // fill level of qm client. +#define PSWRQ2_REG_FILL_LEVEL_SRC_E5 0x240d58UL //Access:R DataWidth:0x2 // fill level of src client. +#define PSWRQ2_REG_FILL_LEVEL_TM_E5 0x240d5cUL //Access:R DataWidth:0x2 // fill level of tm client. +#define PSWRQ2_REG_FILL_LEVEL_TSDM_E5 0x240d60UL //Access:R DataWidth:0x2 // fill level of tsdm client. +#define PSWRQ2_REG_FILL_LEVEL_USDM_E5 0x240d64UL //Access:R DataWidth:0x2 // fill level of usdm client. +#define PSWRQ2_REG_FILL_LEVEL_XSDM_E5 0x240d68UL //Access:R DataWidth:0x2 // fill level of xsdm client. +#define PSWRQ2_REG_FILL_LEVEL_XYLD_E5 0x240d6cUL //Access:R DataWidth:0x2 // fill level of xyld client. +#define PSWRQ2_REG_FILL_LEVEL_PTU_E5 0x240d70UL //Access:R DataWidth:0x3 // fill level of ptu client. +#define PSWRQ2_REG_FILL_LEVEL_M2P_E5 0x240d74UL //Access:R DataWidth:0x2 // fill level of m2p client. +#define PSWRQ2_REG_FILL_LEVEL_YSDM_E5 0x240d78UL //Access:R DataWidth:0x2 // fill level of ysdm client. +#define PSWRQ2_REG_FILL_LEVEL_TGSRC_E5 0x240d7cUL //Access:R DataWidth:0x2 // fill level of tgsrc client. +#define PSWRQ2_REG_FILL_LEVEL_RGSRC_E5 0x240d80UL //Access:R DataWidth:0x2 // fill level of rgsrc client. +#define PSWRQ2_REG_RGSRC_ENDIAN_M_E5 0x240d84UL //Access:RW DataWidth:0x2 // Endian mode for rgsrc. +#define PSWRQ2_REG_TGSRC_ENDIAN_M_E5 0x240d88UL //Access:RW DataWidth:0x2 // Endian mode for tgsrc. #define PSWRQ2_REG_STEERING_TAG_TABLE 0x241000UL //Access:RW DataWidth:0x8 // Steering Tag Table. Used for TPH. #define PSWRQ2_REG_STEERING_TAG_TABLE_SIZE_BB 288 #define PSWRQ2_REG_STEERING_TAG_TABLE_SIZE_K2_E5 368 #define PSWRQ2_REG_ILT_MEMORY 0x260000UL //Access:WB DataWidth:0x35 // Internal lookup table for logical to physical address translation. Re-instantiated in E4 due to size increase. #define PSWRQ2_REG_ILT_MEMORY_SIZE_BB 15200 -#define PSWRQ2_REG_ILT_MEMORY_SIZE_K2_E5 22000 +#define PSWRQ2_REG_ILT_MEMORY_SIZE_K2 22000 +#define PSWRQ2_REG_ILT_MEMORY_SIZE_E5 26414 #define PSWRQ_REG_DBG_OUT_DATA 0x280000UL //Access:WB_R DataWidth:0x100 // Dbgmux output data #define PSWRQ_REG_DBG_OUT_DATA_SIZE 8 #define PSWRQ_REG_DBG_SELECT 0x280020UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output @@ -44236,8 +47683,8 @@ #define PSWRD_REG_DBG_OUT_VALID 0x29c080UL //Access:R DataWidth:0x8 // Dbgmux output valid per Dword #define PSWRD_REG_DBG_OUT_FRAME 0x29c084UL //Access:R DataWidth:0x8 // Dbgmux output frame per Dword #define PSWRD_REG_ECO_RESERVED 0x29c0a0UL //Access:RW DataWidth:0xa // Debug only: Reserved bits for ECO. -#define PSWRD_REG_FIFO_FULL_STATUS 0x29c0a4UL //Access:R DataWidth:0x10 // Each bit indicates if full is asserted by the client. The clients order is according to the incrementing client IDs of read clients. -#define PSWRD_REG_FIFO_FULL_STICKY 0x29c0a8UL //Access:R DataWidth:0x10 // Each bit indicates if full was asserted since reset by the client. The clients order is according to the incrementing client IDs of read clients:. +#define PSWRD_REG_FIFO_FULL_STATUS 0x29c0a4UL //Access:R DataWidth:0x12 // Each bit indicates if full is asserted by the client. The clients order is according to the incrementing client IDs of read clients. +#define PSWRD_REG_FIFO_FULL_STICKY 0x29c0a8UL //Access:R DataWidth:0x12 // Each bit indicates if full was asserted since reset by the client. The clients order is according to the incrementing client IDs of read clients:. #define PSWRD_REG_INT_STS 0x29c180UL //Access:R DataWidth:0x3 // Multi Field Register. #define PSWRD_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define PSWRD_REG_INT_STS_ADDRESS_ERROR_SHIFT 0 @@ -44271,9 +47718,9 @@ #define PSWRD_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT 0 #define PSWRD2_REG_START_INIT 0x29d000UL //Access:RW DataWidth:0x1 // Driver should write 1 to this register in order to signal the PSWRD block to start initializing internal memories. #define PSWRD2_REG_INIT_DONE 0x29d004UL //Access:R DataWidth:0x1 // PSWRD internal memories initialization is done. Driver should check this register is 1 some time after writing 1 to start_init register. -#define PSWRD2_REG_FIRST_SR_NODES 0x29d040UL //Access:R DataWidth:0x1c // Debug only and read only: Each entry provides the first sub request ID in 4 VQs. SR ID of 0x7f is NULL and means there is no sub request in this VQ in PSWRD. The reset value is the one expected in idle check except for the Timers VQ (VQ3). +#define PSWRD2_REG_FIRST_SR_NODES 0x29d040UL //Access:R DataWidth:0x1b // Debug only and read only: Each entry provides the first sub request ID in 3 VQs. SR ID of 0x1ff is NULL and means there is no sub request in this VQ in PSWRD. The reset value is the one expected in idle check except for the Timers VQ (VQ3). This register is for VQs 0-23. #define PSWRD2_REG_FIRST_SR_NODES_SIZE 8 -#define PSWRD2_REG_MASK_ERROR_TO_CLIENTS 0x29d060UL //Access:RW DataWidth:0x10 // Debug only: '1' indicates that error indication is masked towards the corresponding client. +#define PSWRD2_REG_MASK_ERROR_TO_CLIENTS 0x29d060UL //Access:RW DataWidth:0x12 // Debug only: '1' indicates that error indication is masked towards the corresponding client. #define PSWRD2_REG_CONF11 0x29d064UL //Access:RW DataWidth:0x12 // Multi Field Register. #define PSWRD2_REG_CONF11_ERROR_PATTERN (0xffff<<0) // Data pattern that should override the data in case of an error. Duplicated 4 times to create 64 bit data. Can be deaddeaddeaddead for example. #define PSWRD2_REG_CONF11_ERROR_PATTERN_SHIFT 0 @@ -44289,12 +47736,16 @@ #define PSWRD2_REG_PORT_IS_IDLE_0 0x29d07cUL //Access:R DataWidth:0x1 // Debug only: Indication if delivery ports are idle. #define PSWRD2_REG_PORT_IS_IDLE_1 0x29d080UL //Access:R DataWidth:0x1 // Debug only: Indication if delivery ports are idle. #define PSWRD2_REG_ECO_RESERVED 0x29d084UL //Access:RW DataWidth:0x14 // Debug only: Reserved bits for ECO. +#define PSWRD2_REG_FIRST_SR_NODES_2_E5 0x29d090UL //Access:R DataWidth:0x1b // Debug only and read only: Each entry provides the first sub request ID in 3 VQs. SR ID of 0x1ff is NULL and means there is no sub request in this VQ in PSWRD. The reset value is the one expected in idle check except for the Timers VQ (VQ3). This register is for VQs 24-31. +#define PSWRD2_REG_FIRST_SR_NODES_2_SIZE 3 #define PSWRD2_REG_PBF_SWAP_MODE 0x29d0c0UL //Access:RW DataWidth:0x2 // PBF byte swapping mode configuration for master read requests. #define PSWRD2_REG_QM_SWAP_MODE 0x29d0c4UL //Access:RW DataWidth:0x2 // QM byte swapping mode configuration for master read requests. #define PSWRD2_REG_TM_SWAP_MODE 0x29d0c8UL //Access:RW DataWidth:0x2 // TM byte swapping mode configuration for master read requests. #define PSWRD2_REG_SRC_SWAP_MODE 0x29d0ccUL //Access:RW DataWidth:0x2 // SRC byte swapping mode configuration for master read requests. #define PSWRD2_REG_CDURD_SWAP_MODE 0x29d0d0UL //Access:RW DataWidth:0x2 // CDU byte swapping mode configuration for master read requests. #define PSWRD2_REG_PTU_SWAP_MODE 0x29d0d4UL //Access:RW DataWidth:0x2 // PTU byte swapping mode configuration for master read requests. +#define PSWRD2_REG_RGSRC_SWAP_MODE_E5 0x29d0d8UL //Access:RW DataWidth:0x2 // RGSRC byte swapping mode configuration for master read requests. +#define PSWRD2_REG_TGSRC_SWAP_MODE_E5 0x29d0dcUL //Access:RW DataWidth:0x2 // TGSRC byte swapping mode configuration for master read requests. #define PSWRD2_REG_ALMOST_FULL_0 0x29d0e0UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure). #define PSWRD2_REG_ALMOST_FULL_1 0x29d0e4UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure). #define PSWRD2_REG_ALMOST_FULL_2 0x29d0e8UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure). @@ -44319,12 +47770,15 @@ #define PSWRD2_REG_ALMOST_FULL_THR_LOW_PBF 0x29d134UL //Access:RW DataWidth:0x7 // Debug only: If less or equal than this Number of entries are used in the PBF clock synchronization FIFO; it de-asserts the 'almost full' bit. This is the almost full low configuration for PBF It should be equal or smaller to the almost full high consiguration. #define PSWRD2_REG_ALMOST_FULL_THR_HIGH_PRM 0x29d138UL //Access:RW DataWidth:0x3 // Debug only: If more than this Number of entries are used in the PRM clock synchronization FIFO; it asserts the 'almost full' bit. This is the almost full high configuration for PRM. #define PSWRD2_REG_ALMOST_FULL_THR_LOW_PRM 0x29d13cUL //Access:RW DataWidth:0x3 // Debug only: If less or equal than this Number of entries are used in the clock synchronization FIFO; it de-asserts the 'almost full' bit. This is the almost full low configuration for PRM. It should be equal or smaller to the almost full high consiguration. -#define PSWRD2_REG_FIFO_ALMOST_FULL_STICKY 0x29d140UL //Access:R DataWidth:0x10 // Each bit indicates if 'almost full' was asserted since reset from the FIFO towards the delivery module. The clients order is according to the incrementing client IDs of read clients: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 PBF (TDIF); 7 QM; 8 TM; 9 SRC; 10 CDURD; 11 DMAE; 12 MULD (Rfetcher); 13 XYLD; 14 PTU; 15 PRM. +#define PSWRD2_REG_FIFO_ALMOST_FULL_STICKY 0x29d140UL //Access:R DataWidth:0x12 // Each bit indicates if 'almost full' was asserted since reset from the FIFO towards the delivery module. The clients order is according to the incrementing client IDs of read clients: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 PBF (TDIF); 7 QM; 8 TM; 9 SRC; 10 CDURD; 11 DMAE; 12 MULD (Rfetcher); 13 XYLD; 14 PTU; 15 TGSRC; 16 RGSRC; 17 PRM. #define PSWRD2_REG_MAX_FILL_LEVEL1 0x29d144UL //Access:R DataWidth:0x20 // Per-client maximum sync FIFO fill level since reset in 16B lines. 7:0 TSDM; 15:8 MSDM; 23:16 USDM; 31:24 XSDM. #define PSWRD2_REG_MAX_FILL_LEVEL2 0x29d148UL //Access:R DataWidth:0x20 // Per-client maximum sync FIFO fill level since reset in 16B lines. 7:0 YSDM; 15:8 PSDM; 23:16 QM; 31:24 TM. #define PSWRD2_REG_MAX_FILL_LEVEL3 0x29d14cUL //Access:R DataWidth:0x20 // Per-client maximum sync FIFO fill level since reset in 16B lines. 7:0 SRC; 15:8 CDU; 23:16 DMAE; 31:24 MULD. -#define PSWRD2_REG_MAX_FILL_LEVEL4 0x29d150UL //Access:R DataWidth:0x18 // Per-client maximum sync FIFO fill level since reset in 16B lines. 7:0 XYLD. 15:8 PTU. 23:16 PRM. +#define PSWRD2_REG_MAX_FILL_LEVEL4 0x29d150UL //Access:R DataWidth:0x20 // Per-client maximum sync FIFO fill level since reset in 16B lines. 7:0 XYLD. 15:8 PTU. 23:16 TGSRC; 31:24 RGSRC. #define PSWRD2_REG_MAX_FILL_LEVEL_PBF 0x29d154UL //Access:R DataWidth:0x8 // PBF maximum sync FIFO fill level since reset in 16B lines. +#define PSWRD2_REG_ALMOST_FULL_16_E5 0x29d158UL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure). +#define PSWRD2_REG_ALMOST_FULL_17_E5 0x29d15cUL //Access:R DataWidth:0x1 // Debug only: The 'almost full' indication from each fifo (gives indication about backpressure). +#define PSWRD2_REG_MAX_FILL_LEVEL5_E5 0x29d160UL //Access:R DataWidth:0x8 // Per-client maximum sync FIFO fill level since reset in 16B lines. 7:0 PRM. #define PSWRD2_REG_INT_STS 0x29d180UL //Access:R DataWidth:0x5 // Multi Field Register. #define PSWRD2_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define PSWRD2_REG_INT_STS_ADDRESS_ERROR_SHIFT 0 @@ -44373,110 +47827,98 @@ #define PSWRD2_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS.DATAPATH_REGISTERS . #define PSWRD2_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT 0 #define PSWRD2_REG_PRTY_MASK_H_0 0x29d204UL //Access:RW DataWidth:0x1f // Multi Field Register. - #define PSWRD2_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT_BB_K2 (0x1<<1) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM018_I_ECC_RF_INT . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT_BB_K2_SHIFT 1 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM018_I_ECC_RF_INT . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT_E5_SHIFT 0 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM019_I_ECC_RF_INT_BB_K2 (0x1<<2) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM019_I_ECC_RF_INT . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM019_I_ECC_RF_INT_BB_K2_SHIFT 2 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM019_I_ECC_RF_INT_E5 (0x1<<1) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM019_I_ECC_RF_INT . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM019_I_ECC_RF_INT_E5_SHIFT 1 #define PSWRD2_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_BB_K2 (0x1<<3) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM020_I_ECC_RF_INT . #define PSWRD2_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_BB_K2_SHIFT 3 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_E5 (0x1<<2) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM020_I_ECC_RF_INT . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_E5_SHIFT 2 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM020_I_ECC_RF_INT . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_E5_SHIFT 0 #define PSWRD2_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_BB_K2 (0x1<<4) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM021_I_ECC_RF_INT . #define PSWRD2_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_BB_K2_SHIFT 4 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_E5 (0x1<<3) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM021_I_ECC_RF_INT . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_E5_SHIFT 3 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_E5 (0x1<<1) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM021_I_ECC_RF_INT . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_E5_SHIFT 1 #define PSWRD2_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_BB_K2 (0x1<<5) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM022_I_ECC_RF_INT . #define PSWRD2_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_BB_K2_SHIFT 5 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_E5 (0x1<<4) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM022_I_ECC_RF_INT . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_E5_SHIFT 4 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_E5 (0x1<<2) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM022_I_ECC_RF_INT . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_E5_SHIFT 2 #define PSWRD2_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT_BB_K2 (0x1<<6) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM023_I_ECC_RF_INT . #define PSWRD2_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT_BB_K2_SHIFT 6 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT_E5 (0x1<<5) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM023_I_ECC_RF_INT . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT_E5_SHIFT 5 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT_E5 (0x1<<3) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM023_I_ECC_RF_INT . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT_E5_SHIFT 3 #define PSWRD2_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT_BB_K2 (0x1<<7) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM024_I_ECC_RF_INT . #define PSWRD2_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT_BB_K2_SHIFT 7 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT_E5 (0x1<<6) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM024_I_ECC_RF_INT . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT_E5_SHIFT 6 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT_E5 (0x1<<4) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM024_I_ECC_RF_INT . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT_E5_SHIFT 4 #define PSWRD2_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT_BB_K2 (0x1<<8) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM025_I_ECC_RF_INT . #define PSWRD2_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT_BB_K2_SHIFT 8 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT_E5 (0x1<<7) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM025_I_ECC_RF_INT . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT_E5_SHIFT 7 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_E5 (0x1<<8) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_E5_SHIFT 8 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT_E5 (0x1<<9) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM016_I_ECC_RF_INT . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT_E5_SHIFT 9 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT_E5 (0x1<<5) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM025_I_ECC_RF_INT . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT_E5_SHIFT 5 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_E5 (0x1<<6) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_E5_SHIFT 6 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_ECC_RF_INT_E5 (0x1<<7) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM027_I_ECC_RF_INT . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_ECC_RF_INT_E5_SHIFT 7 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_E5 (0x1<<8) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM028_I_ECC_RF_INT . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_E5_SHIFT 8 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT_BB_K2 (0x1<<1) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM018_I_ECC_RF_INT . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT_BB_K2_SHIFT 1 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT_E5 (0x1<<9) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM018_I_ECC_RF_INT . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT_E5_SHIFT 9 #define PSWRD2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_E5 (0x1<<10) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT . #define PSWRD2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_E5_SHIFT 10 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_E5_SHIFT 11 #define PSWRD2_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_K2 (0x1<<10) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_K2_SHIFT 10 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5_SHIFT 11 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5_SHIFT 12 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2 (0x1<<14) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2_SHIFT 14 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_E5_SHIFT 13 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_E5_SHIFT 14 #define PSWRD2_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_K2 (0x1<<11) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_K2_SHIFT 11 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_E5_SHIFT 12 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_K2 (0x1<<12) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_K2_SHIFT 12 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_E5_SHIFT 13 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_E5_SHIFT 15 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY (0x1<<16) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_SHIFT 16 #define PSWRD2_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_K2 (0x1<<13) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_K2_SHIFT 13 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_E5_SHIFT 14 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2 (0x1<<14) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2_SHIFT 14 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_E5_SHIFT 15 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_E5_SHIFT 17 #define PSWRD2_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_K2 (0x1<<15) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_K2_SHIFT 15 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_E5_SHIFT 16 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2 (0x1<<16) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2_SHIFT 16 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_E5_SHIFT 17 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_K2 (0x1<<17) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_K2_SHIFT 17 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_E5_SHIFT 18 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_E5_SHIFT 18 #define PSWRD2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2 (0x1<<28) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_K2_SHIFT 28 #define PSWRD2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5_SHIFT 19 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2 (0x1<<21) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT 21 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_E5_SHIFT 20 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2 (0x1<<22) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT 22 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_E5_SHIFT 21 #define PSWRD2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2 (0x1<<23) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2_SHIFT 23 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_E5_SHIFT 22 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_E5_SHIFT 20 #define PSWRD2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_K2 (0x1<<24) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_K2_SHIFT 24 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5_SHIFT 23 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5_SHIFT 21 #define PSWRD2_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_K2 (0x1<<25) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_K2_SHIFT 25 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5_SHIFT 24 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5_SHIFT 22 #define PSWRD2_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2 (0x1<<26) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2_SHIFT 26 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5_SHIFT 25 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5_SHIFT 23 #define PSWRD2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_K2 (0x1<<27) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_K2_SHIFT 27 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5_SHIFT 26 - #define PSWRD2_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5_SHIFT 27 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5_SHIFT 24 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5_SHIFT 25 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5_SHIFT 26 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5_SHIFT 27 #define PSWRD2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2 (0x1<<29) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT 29 #define PSWRD2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . @@ -44489,168 +47931,182 @@ #define PSWRD2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5_SHIFT 30 #define PSWRD2_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM017_I_ECC_RF_INT . #define PSWRD2_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT_BB_K2_SHIFT 0 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM019_I_ECC_RF_INT_BB_K2 (0x1<<2) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM019_I_ECC_RF_INT . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM019_I_ECC_RF_INT_BB_K2_SHIFT 2 #define PSWRD2_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_BB_K2 (0x1<<9) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT . #define PSWRD2_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_BB_K2_SHIFT 9 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_K2 (0x1<<12) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_K2_SHIFT 12 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_K2 (0x1<<17) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_K2_SHIFT 17 #define PSWRD2_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_K2 (0x1<<18) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_K2_SHIFT 18 #define PSWRD2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2 (0x1<<19) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_K2_SHIFT 19 #define PSWRD2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2 (0x1<<20) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_K2_SHIFT 20 -#define PSWRD2_REG_PRTY_MASK_H_1 0x29d214UL //Access:RW DataWidth:0x3 // Multi Field Register. + #define PSWRD2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2 (0x1<<21) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT 21 + #define PSWRD2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2 (0x1<<22) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT 22 +#define PSWRD2_REG_PRTY_MASK_H_1 0x29d214UL //Access:RW DataWidth:0x5 // Multi Field Register. #define PSWRD2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_BB_K2 (0x1<<1) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_BB_K2_SHIFT 1 #define PSWRD2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_E5_SHIFT 0 #define PSWRD2_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_E5_SHIFT 1 - #define PSWRD2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY . - #define PSWRD2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_E5_SHIFT 2 + #define PSWRD2_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_E5_SHIFT 2 + #define PSWRD2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5_SHIFT 3 + #define PSWRD2_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY . + #define PSWRD2_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_E5_SHIFT 4 #define PSWRD2_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM005_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_BB_K2_SHIFT 0 #define PSWRD2_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_BB_K2 (0x1<<2) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY . #define PSWRD2_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_BB_K2_SHIFT 2 -#define PSWRD2_REG_MEM020_RF_ECC_ERROR_CONNECT_BB_K2 0x29d224UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define PSWRD2_REG_MEM020_RF_ECC_ERROR_CONNECT_E5 0x29d220UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define PSWRD2_REG_MEM019_RF_ECC_ERROR_CONNECT_BB_K2 0x29d220UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define PSWRD2_REG_MEM021_RF_ECC_ERROR_CONNECT_BB_K2 0x29d228UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define PSWRD2_REG_MEM021_RF_ECC_ERROR_CONNECT_E5 0x29d224UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define PSWRD2_REG_MEM022_RF_ECC_ERROR_CONNECT_BB_K2 0x29d22cUL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define PSWRD2_REG_MEM022_RF_ECC_ERROR_CONNECT_E5 0x29d228UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PSWRD2_REG_MEM022_RF_ECC_ERROR_CONNECT_E5 0x29d220UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PSWRD2_REG_MEM019_RF_ECC_ERROR_CONNECT_BB_K2 0x29d220UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define PSWRD2_REG_MEM023_RF_ECC_ERROR_CONNECT_BB_K2 0x29d230UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define PSWRD2_REG_MEM023_RF_ECC_ERROR_CONNECT_E5 0x29d22cUL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PSWRD2_REG_MEM023_RF_ECC_ERROR_CONNECT_E5 0x29d224UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PSWRD2_REG_MEM020_RF_ECC_ERROR_CONNECT_BB_K2 0x29d224UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define PSWRD2_REG_MEM024_RF_ECC_ERROR_CONNECT_BB_K2 0x29d234UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define PSWRD2_REG_MEM024_RF_ECC_ERROR_CONNECT_E5 0x29d230UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PSWRD2_REG_MEM024_RF_ECC_ERROR_CONNECT_E5 0x29d228UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PSWRD2_REG_MEM021_RF_ECC_ERROR_CONNECT_BB_K2 0x29d228UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define PSWRD2_REG_MEM025_RF_ECC_ERROR_CONNECT_BB_K2 0x29d238UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define PSWRD2_REG_MEM025_RF_ECC_ERROR_CONNECT_E5 0x29d234UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define PSWRD2_REG_MEM026_RF_ECC_ERROR_CONNECT_E5 0x29d238UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PSWRD2_REG_MEM025_RF_ECC_ERROR_CONNECT_E5 0x29d22cUL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PSWRD2_REG_MEM026_RF_ECC_ERROR_CONNECT_E5 0x29d230UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PSWRD2_REG_MEM027_RF_ECC_ERROR_CONNECT_E5 0x29d234UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PSWRD2_REG_MEM028_RF_ECC_ERROR_CONNECT_E5 0x29d238UL //Access:W DataWidth:0x10 // Register to generate up to two ECC errors on the next write to memory: pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.rf_ecc_error_connect Includes 2 words of 8 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 64. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define PSWRD2_REG_MEM_ECC_ENABLE_0 0x29d23cUL //Access:RW DataWidth:0xb // Multi Field Register. - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN_BB_K2 (0x1<<1) // Enable ECC for memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN_BB_K2_SHIFT 1 - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN_E5_SHIFT 0 - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM019_I_ECC_EN_BB_K2 (0x1<<2) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM019_I_ECC_EN_BB_K2_SHIFT 2 - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM019_I_ECC_EN_E5 (0x1<<1) // Enable ECC for memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM019_I_ECC_EN_E5_SHIFT 1 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN_BB_K2 (0x1<<3) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN_BB_K2_SHIFT 3 - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN_E5 (0x1<<2) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN_E5_SHIFT 2 + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM020_I_ECC_EN_E5_SHIFT 0 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_BB_K2 (0x1<<4) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_BB_K2_SHIFT 4 - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_E5 (0x1<<3) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_E5_SHIFT 3 + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_E5 (0x1<<1) // Enable ECC for memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM021_I_ECC_EN_E5_SHIFT 1 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN_BB_K2 (0x1<<5) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN_BB_K2_SHIFT 5 - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN_E5 (0x1<<4) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN_E5_SHIFT 4 + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN_E5 (0x1<<2) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN_E5_SHIFT 2 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_EN_BB_K2 (0x1<<6) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_EN_BB_K2_SHIFT 6 - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_EN_E5 (0x1<<5) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_EN_E5_SHIFT 5 + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_EN_E5 (0x1<<3) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_EN_E5_SHIFT 3 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_EN_BB_K2 (0x1<<7) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_EN_BB_K2_SHIFT 7 - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_EN_E5 (0x1<<6) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_EN_E5_SHIFT 6 + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_EN_E5 (0x1<<4) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_EN_E5_SHIFT 4 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_EN_BB_K2 (0x1<<8) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_EN_BB_K2_SHIFT 8 - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_EN_E5 (0x1<<7) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_EN_E5_SHIFT 7 - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_E5 (0x1<<8) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_E5_SHIFT 8 - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_EN_E5 (0x1<<9) // Enable ECC for memory ecc instance pswrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_pbf_mem_wrap - #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_EN_E5_SHIFT 9 + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_EN_E5 (0x1<<5) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_EN_E5_SHIFT 5 + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_E5 (0x1<<6) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_E5_SHIFT 6 + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_EN_E5 (0x1<<7) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_EN_E5_SHIFT 7 + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_EN_E5 (0x1<<8) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_EN_E5_SHIFT 8 + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN_BB_K2 (0x1<<1) // Enable ECC for memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN_BB_K2_SHIFT 1 + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN_E5 (0x1<<9) // Enable ECC for memory ecc instance pswrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_pbf_mem_wrap + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN_E5_SHIFT 9 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_E5 (0x1<<10) // Enable ECC for memory ecc instance pswrd.SYNC_FIFO_GEN_CDU_FOR[6].SYNC_FIFO_GEN_CDU_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_cdu_mem_wrap #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_E5_SHIFT 10 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM017_I_ECC_EN_BB_K2 (0x1<<0) // Enable ECC for memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM017_I_ECC_EN_BB_K2_SHIFT 0 + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM019_I_ECC_EN_BB_K2 (0x1<<2) // Enable ECC for memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM019_I_ECC_EN_BB_K2_SHIFT 2 #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_BB_K2 (0x1<<9) // Enable ECC for memory ecc instance pswrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_pbf_mem_wrap #define PSWRD2_REG_MEM_ECC_ENABLE_0_MEM015_I_ECC_EN_BB_K2_SHIFT 9 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0 0x29d240UL //Access:RW DataWidth:0xb // Multi Field Register. - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY_BB_K2 (0x1<<1) // Set parity only for memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY_BB_K2_SHIFT 1 - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY_E5_SHIFT 0 - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM019_I_ECC_PRTY_BB_K2 (0x1<<2) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM019_I_ECC_PRTY_BB_K2_SHIFT 2 - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM019_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM019_I_ECC_PRTY_E5_SHIFT 1 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY_BB_K2 (0x1<<3) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY_BB_K2_SHIFT 3 - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY_E5 (0x1<<2) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY_E5_SHIFT 2 + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM020_I_ECC_PRTY_E5_SHIFT 0 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_BB_K2 (0x1<<4) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_BB_K2_SHIFT 4 - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_E5_SHIFT 3 + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM021_I_ECC_PRTY_E5_SHIFT 1 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY_BB_K2 (0x1<<5) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY_BB_K2_SHIFT 5 - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY_E5 (0x1<<4) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY_E5_SHIFT 4 + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY_E5 (0x1<<2) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY_E5_SHIFT 2 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_PRTY_BB_K2 (0x1<<6) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_PRTY_BB_K2_SHIFT 6 - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_PRTY_E5 (0x1<<5) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_PRTY_E5_SHIFT 5 + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_PRTY_E5_SHIFT 3 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_PRTY_BB_K2 (0x1<<7) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_PRTY_BB_K2_SHIFT 7 - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_PRTY_E5 (0x1<<6) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_PRTY_E5_SHIFT 6 + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_PRTY_E5 (0x1<<4) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_PRTY_E5_SHIFT 4 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_PRTY_BB_K2 (0x1<<8) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_PRTY_BB_K2_SHIFT 8 - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_PRTY_E5 (0x1<<7) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_PRTY_E5_SHIFT 7 - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_E5 (0x1<<8) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_E5_SHIFT 8 - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_PRTY_E5 (0x1<<9) // Set parity only for memory ecc instance pswrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_pbf_mem_wrap - #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_PRTY_E5_SHIFT 9 + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_PRTY_E5 (0x1<<5) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_PRTY_E5_SHIFT 5 + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_E5 (0x1<<6) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_E5_SHIFT 6 + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_PRTY_E5 (0x1<<7) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_PRTY_E5_SHIFT 7 + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_PRTY_E5 (0x1<<8) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_PRTY_E5_SHIFT 8 + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY_BB_K2 (0x1<<1) // Set parity only for memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY_BB_K2_SHIFT 1 + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY_E5 (0x1<<9) // Set parity only for memory ecc instance pswrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_pbf_mem_wrap + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY_E5_SHIFT 9 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_E5 (0x1<<10) // Set parity only for memory ecc instance pswrd.SYNC_FIFO_GEN_CDU_FOR[6].SYNC_FIFO_GEN_CDU_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_cdu_mem_wrap #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_E5_SHIFT 10 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM017_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM017_I_ECC_PRTY_BB_K2_SHIFT 0 + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM019_I_ECC_PRTY_BB_K2 (0x1<<2) // Set parity only for memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM019_I_ECC_PRTY_BB_K2_SHIFT 2 #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_BB_K2 (0x1<<9) // Set parity only for memory ecc instance pswrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_pbf_mem_wrap #define PSWRD2_REG_MEM_ECC_PARITY_ONLY_0_MEM015_I_ECC_PRTY_BB_K2_SHIFT 9 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0 0x29d244UL //Access:RC DataWidth:0xb // Multi Field Register. - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT_BB_K2 (0x1<<1) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT_BB_K2_SHIFT 1 - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT_E5_SHIFT 0 - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM019_I_ECC_CORRECT_BB_K2 (0x1<<2) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM019_I_ECC_CORRECT_BB_K2_SHIFT 2 - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM019_I_ECC_CORRECT_E5 (0x1<<1) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM019_I_ECC_CORRECT_E5_SHIFT 1 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT_BB_K2 (0x1<<3) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT_BB_K2_SHIFT 3 - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT_E5 (0x1<<2) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT_E5_SHIFT 2 + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM020_I_ECC_CORRECT_E5_SHIFT 0 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_BB_K2 (0x1<<4) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_BB_K2_SHIFT 4 - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_E5 (0x1<<3) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_E5_SHIFT 3 + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_E5 (0x1<<1) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM021_I_ECC_CORRECT_E5_SHIFT 1 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT_BB_K2 (0x1<<5) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT_BB_K2_SHIFT 5 - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT_E5 (0x1<<4) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT_E5_SHIFT 4 + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT_E5 (0x1<<2) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT_E5_SHIFT 2 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_CORRECT_BB_K2 (0x1<<6) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_CORRECT_BB_K2_SHIFT 6 - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_CORRECT_E5 (0x1<<5) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_CORRECT_E5_SHIFT 5 + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_CORRECT_E5 (0x1<<3) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_CORRECT_E5_SHIFT 3 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_CORRECT_BB_K2 (0x1<<7) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_CORRECT_BB_K2_SHIFT 7 - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_CORRECT_E5 (0x1<<6) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_CORRECT_E5_SHIFT 6 + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_CORRECT_E5 (0x1<<4) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_CORRECT_E5_SHIFT 4 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_CORRECT_BB_K2 (0x1<<8) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_CORRECT_BB_K2_SHIFT 8 - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_CORRECT_E5 (0x1<<7) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_CORRECT_E5_SHIFT 7 - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT_E5 (0x1<<8) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT_E5_SHIFT 8 - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_CORRECT_E5 (0x1<<9) // Record if a correctable error occurred on memory ecc instance pswrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_pbf_mem_wrap - #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_CORRECT_E5_SHIFT 9 + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_CORRECT_E5 (0x1<<5) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_CORRECT_E5_SHIFT 5 + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT_E5 (0x1<<6) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT_E5_SHIFT 6 + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_CORRECT_E5 (0x1<<7) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_CORRECT_E5_SHIFT 7 + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_CORRECT_E5 (0x1<<8) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_CORRECT_E5_SHIFT 8 + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT_BB_K2 (0x1<<1) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT_BB_K2_SHIFT 1 + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT_E5 (0x1<<9) // Record if a correctable error occurred on memory ecc instance pswrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_pbf_mem_wrap + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT_E5_SHIFT 9 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_E5 (0x1<<10) // Record if a correctable error occurred on memory ecc instance pswrd.SYNC_FIFO_GEN_CDU_FOR[6].SYNC_FIFO_GEN_CDU_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_cdu_mem_wrap #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_E5_SHIFT 10 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM017_I_ECC_CORRECT_BB_K2 (0x1<<0) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_ecc in module pswrd_tetris_buffer_first_qw #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM017_I_ECC_CORRECT_BB_K2_SHIFT 0 + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM019_I_ECC_CORRECT_BB_K2 (0x1<<2) // Record if a correctable error occurred on memory ecc instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_ecc in module pswrd_tetris_buffer_mem_wrap + #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM019_I_ECC_CORRECT_BB_K2_SHIFT 2 #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_BB_K2 (0x1<<9) // Record if a correctable error occurred on memory ecc instance pswrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_ecc in module pswrd_sync_fifo_pbf_mem_wrap #define PSWRD2_REG_MEM_ECC_ERROR_CORRECTED_0_MEM015_I_ECC_CORRECT_BB_K2_SHIFT 9 #define PSWRD2_REG_MEM_ECC_EVENTS 0x29d248UL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. @@ -44664,9 +48120,9 @@ #define PSWRD2_REG_DBG_OUT_VALID 0x29d440UL //Access:R DataWidth:0x8 // Dbgmux output valid per Dword #define PSWRD2_REG_DBG_OUT_FRAME 0x29d444UL //Access:R DataWidth:0x8 // Dbgmux output frame per Dword #define PSWRD2_REG_DISABLE_INPUTS 0x29d460UL //Access:RW DataWidth:0x1 // When '1'; inputs to the PSWRD block are ignored. -#define PSWRD2_REG_SR_NUM_CFG 0x29d464UL //Access:RW DataWidth:0x7 // Debug only: Total number of available PCI read sub-requests. Must be bigger than 1. Normally should not be changed. Should have identical value to rq_sr_num_cfg. -#define PSWRD2_REG_BLK_NUM_CFG 0x29d468UL //Access:RW DataWidth:0x9 // Debug only: Total number of available blocks in Tetris Buffer. Must be bigger than 6. Normally should not be changed. Should have identical value to rq_blk_num_cfg. -#define PSWRD2_REG_ATC_GLOBAL_ENABLE 0x29d46cUL //Access:RW DataWidth:0x1 // Global ATC enable bit. When reset all ATC logic is disabled within the PSWRD. 'ATC entry ID' interface from PSWRQ is ignored and 'ATC RCPL Done' interface to ATC is not generated. The value of this register must be the same as PSWRQ_ATC_GLOBAL_ENABLE. This value must be '1' when ATC capability is enabled in PCIe core. +#define PSWRD2_REG_SR_NUM_CFG 0x29d464UL //Access:RW DataWidth:0x9 // Debug only: Total number of available PCI read sub-requests. Must be bigger than 1. Normally should not be changed. Should have identical value to rq_sr_num_cfg. +#define PSWRD2_REG_BLK_NUM_CFG 0x29d468UL //Access:RW DataWidth:0xa // Debug only: Total number of available blocks in Tetris Buffer. Must be bigger than 6. Normally should not be changed. Should have identical value to rq_blk_num_cfg. +#define PSWRD2_REG_ATC_GLOBAL_ENABLE_BB_K2 0x29d46cUL //Access:RW DataWidth:0x1 // Global ATC enable bit. When reset all ATC logic is disabled within the PSWRD. 'ATC entry ID' interface from PSWRQ is ignored and 'ATC RCPL Done' interface to ATC is not generated. The value of this register must be the same as PSWRQ_ATC_GLOBAL_ENABLE. This value must be '1' when ATC capability is enabled in PCIe core. #define PSWRD2_REG_CONTINUE_SERVING_PBF 0x29d470UL //Access:RW DataWidth:0x1 // This register defines the delivery port behavior when finishing delivering a request to the PBF and the data for the next request is already in the Tetris buffer. 0 - The delivery port continues delivering the next PBF request only if the second delivery port is idle. This is the behavior in E1 E1H and E2. 1 - The delivery port always continues delivering the next PBF request. This is more efficient since about 11 arbitration cycles are not wasted. #define PSWRD2_REG_USDM_ADDITIONAL_REQUESTS 0x29d474UL //Access:RW DataWidth:0x2 // When finishing delivering a request to this client; this register determines the number of additional requests to deliver to the client without doing arbitration again. This configuration is for all clients except PBF (for PBF the number of additional requests to deliver is unlimited). This feature can save arbitration overhead. #define PSWRD2_REG_XSDM_ADDITIONAL_REQUESTS 0x29d478UL //Access:RW DataWidth:0x2 // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead. @@ -44683,6 +48139,8 @@ #define PSWRD2_REG_XYLD_ADDITIONAL_REQUESTS 0x29d4a4UL //Access:RW DataWidth:0x2 // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead. #define PSWRD2_REG_PTU_ADDITIONAL_REQUESTS 0x29d4a8UL //Access:RW DataWidth:0x2 // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead. #define PSWRD2_REG_PRM_ADDITIONAL_REQUESTS 0x29d4acUL //Access:RW DataWidth:0x2 // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead. +#define PSWRD2_REG_TGSRC_ADDITIONAL_REQUESTS_E5 0x29d4b0UL //Access:RW DataWidth:0x2 // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead. +#define PSWRD2_REG_RGSRC_ADDITIONAL_REQUESTS_E5 0x29d4b4UL //Access:RW DataWidth:0x2 // When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead. #define PSWHST2_REG_HEADER_FIFO_STATUS 0x29e040UL //Access:R DataWidth:0x7 // Debug only: Number of used entries in the header FIFO. #define PSWHST2_REG_DATA_FIFO_STATUS 0x29e044UL //Access:R DataWidth:0x7 // Debug only: Number of used entries in the data FIFO. #define PSWHST2_REG_HEADER_FIFO_MAX_ENTRIES 0x29e048UL //Access:R DataWidth:0x7 // Debug only: Maximum number of entries that were used in the header FIFO. @@ -44772,7 +48230,7 @@ #define PSWHST_REG_DEST_SDM_CREDITS 0x2a0098UL //Access:RW DataWidth:0x2 // Number of credits for destination SDM in target write interface (common to all SDMs). #define PSWHST_REG_DEST_IGU_CREDITS 0x2a009cUL //Access:RW DataWidth:0x2 // Number of credits for destination IGU in target write interface. #define PSWHST_REG_DEST_CAU_CREDITS 0x2a00a0UL //Access:RW DataWidth:0x2 // Number of credits for destination CAU in target write interface. -#define PSWHST_REG_DEST_CREDITS_AVAIL 0x2a00a4UL //Access:R DataWidth:0x10 // Number of available credits for destination in internal write interface. [1:0] usdm; [3:2] xsdm; [5:4] msdm; [7:6] ysdm; [9:8] psdm; [11:10] tsdm; [13:12] igu; [15:14] cau. +#define PSWHST_REG_DEST_CREDITS_AVAIL 0x2a00a4UL //Access:R DataWidth:0x12 // Number of available credits for destination in internal write interface. [1:0] usdm; [3:2] xsdm; [5:4] msdm; [7:6] ysdm; [9:8] psdm; [11:10] tsdm; [13:12] igu; [15:14] cau; [17:16] dorq #define PSWHST_REG_TIMEOUT 0x2a00a8UL //Access:RW DataWidth:0x1e // Number of cycles to wait before entering drain mode. #define PSWHST_REG_IS_IN_DRAIN_MODE 0x2a00acUL //Access:R DataWidth:0x1 // 1 - PSWHST is in drain mode. #define PSWHST_REG_EXIT_DRAIN_MODE 0x2a00b0UL //Access:W DataWidth:0x1 // Writing 1 to this register indicates PSWHST to exit drain mode. @@ -44996,7 +48454,8 @@ #define PSWHST_REG_INBOUND_INT_SIZE 72 #define PSWHST_REG_ZONE_PERMISSION_TABLE 0x2a0800UL //Access:RW DataWidth:0x9 // Indirect access to the permission table. The fields are : {Valid; VFID[7:0]}. #define PSWHST_REG_ZONE_PERMISSION_TABLE_SIZE_BB 256 -#define PSWHST_REG_ZONE_PERMISSION_TABLE_SIZE_K2_E5 320 +#define PSWHST_REG_ZONE_PERMISSION_TABLE_SIZE_K2 320 +#define PSWHST_REG_ZONE_PERMISSION_TABLE_SIZE_E5 512 #define PGLUE_B_REG_START_INIT_INB_INT_MEM 0x2a8000UL //Access:W DataWidth:0x1 // Writing 1 to this register signals the PGLUE block to start initializing inbound interrupt memories for PF zone B. Memories are initialized such that all interrupts are disabled: start_address = 1; end_address = 0. #define PGLUE_B_REG_INIT_DONE_INB_INT_MEM 0x2a8004UL //Access:R DataWidth:0x2 // Initializing inbound interrupt memories for PF zone B is done. Driver should make sure the corresponding bit is 1 some time after writing to start_init_inb_int_mem. Bit 0 is for path 0 and bit 1 is for path 1. #define PGLUE_B_REG_START_INIT_PTT_GTT 0x2a8008UL //Access:W DataWidth:0x1 // Writing 1 to this register signals the PGLUE block to start initializing PTT and GTT. Offsets should map to reserved space, pretend should map to the same PF. This register should be initialized by MCP. @@ -46440,8 +49899,9 @@ #define TM_REG_PRE_SCAN_MEM_BB_K2 0x2c4000UL //Access:RW DataWidth:0x20 // Pre scan memory which contains the scan rate fields for each group. Each row contains scan rate field (2 bits) per group, for 16 groups. The first 512 rows contain the scan rate fields for connections, the last 512 rows contain the scan rate fields for tasks. TBD - describe the fields. #define TM_REG_PRE_SCAN_MEM_SIZE_BB 1024 #define TM_REG_PRE_SCAN_MEM_SIZE_K2 2048 -#define TM_REG_CONTEXT_MEM 0x2c8000UL //Access:WB DataWidth:0x73 // Context memory for connections and tasks. 320 LCIDs for connections and 320 LTIDs for tasks. The addresses are interleaved between connections and tasks. If address [0] = 0, it is LCID (connections), if address [0] = 1, it is LTID (tasks). Previous name: context_ram0. -#define TM_REG_CONTEXT_MEM_SIZE 2560 +#define TM_REG_CONTEXT_MEM 0x2c8000UL //Access:WB DataWidth:0x73 // Context memory for connections and tasks. It holds 320 LCIDs for connections and 384 LTIDs for tasks. Logically the memory is divided to two sections: the first section is for the LCIDs, the second section is for the LTIDs. Ie addresses 0 to 319 are for CIDs, and addresses 320 to 703 are for LTIDs. +#define TM_REG_CONTEXT_MEM_SIZE_BB_K2 2560 +#define TM_REG_CONTEXT_MEM_SIZE_E5 2816 #define TCFC_REG_INIT_REG 0x2d0000UL //Access:RW DataWidth:0xd // Multi Field Register. #define TCFC_REG_INIT_REG_AC_INIT (0x1<<0) // When set activity counter ram will be initialized to zeros. when this operation is completed CFC_REGISTERS_AC_INITDONE.AC_INIT_DONE will be set. #define TCFC_REG_INIT_REG_AC_INIT_SHIFT 0 @@ -46649,7 +50109,7 @@ #define TCFC_REG_LCREQ_CREDIT_SIZE_BB_K2 14 #define TCFC_REG_LCREQ_CREDIT_SIZE_E5 13 #define TCFC_REG_PRSRESP_CREDIT 0x2d0780UL //Access:RW DataWidth:0x5 // Set the initial credit for the parser response interface if less than the max is desired. -#define TCFC_REG_SEARCH_CREDIT 0x2d0784UL //Access:RW DataWidth:0x5 // Set the initial credit for the searcher interface if less than the max is desired. +#define TCFC_REG_SEARCH_CREDIT 0x2d0784UL //Access:RW DataWidth:0x7 // Set the initial credit for the searcher interface if less than the max is desired. #define TCFC_REG_CDULD_CREDIT 0x2d0788UL //Access:RW DataWidth:0x7 // Set the initial credit for the CDU load interface if less than the max is desired. #define TCFC_REG_CDUWB_CREDIT 0x2d078cUL //Access:RW DataWidth:0x7 // Set the initial credit for the CDU write-back interface if less than the max is desired. #define TCFC_REG_FLOAD_RGN_MSK 0x2d07a0UL //Access:RW DataWidth:0x8 // Array of indirect registers defines the forced load regions per type. Applicable only in the TCFC. @@ -46793,44 +50253,60 @@ #define CCFC_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT 0 #define CCFC_REG_INT_STS_CLR_0_EXE_ERROR (0x1<<1) // Interrupt indicating that an execution error has occurred. #define CCFC_REG_INT_STS_CLR_0_EXE_ERROR_SHIFT 1 -#define CCFC_REG_PRTY_MASK_H_0 0x2e0204UL //Access:RW DataWidth:0x4 // Multi Field Register. - #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_ECC1_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM003_I_ECC1_RF_INT . - #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_ECC1_RF_INT_E5_SHIFT 0 - #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_ECC2_RF_INT_E5 (0x1<<1) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM003_I_ECC2_RF_INT . - #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_ECC2_RF_INT_E5_SHIFT 1 +#define CCFC_REG_PRTY_MASK_H_0 0x2e0204UL //Access:RW DataWidth:0x6 // Multi Field Register. + #define CCFC_REG_PRTY_MASK_H_0_MEM005_I_ECC1_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM005_I_ECC1_RF_INT . + #define CCFC_REG_PRTY_MASK_H_0_MEM005_I_ECC1_RF_INT_E5_SHIFT 0 + #define CCFC_REG_PRTY_MASK_H_0_MEM005_I_ECC2_RF_INT_E5 (0x1<<1) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM005_I_ECC2_RF_INT . + #define CCFC_REG_PRTY_MASK_H_0_MEM005_I_ECC2_RF_INT_E5_SHIFT 1 #define CCFC_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT . #define CCFC_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_K2_SHIFT 0 #define CCFC_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_E5 (0x1<<2) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT . #define CCFC_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_E5_SHIFT 2 - #define CCFC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . - #define CCFC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5_SHIFT 3 + #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_E5 (0x1<<3) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT . + #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_E5_SHIFT 3 + #define CCFC_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_E5 (0x1<<4) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT . + #define CCFC_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_E5_SHIFT 4 + #define CCFC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . + #define CCFC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5_SHIFT 5 #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2 (0x1<<1) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_K2_SHIFT 1 -#define CCFC_REG_MEM_ECC_ENABLE_0 0x2e0210UL //Access:RW DataWidth:0x3 // Multi Field Register. - #define CCFC_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC1_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc1 in module cfc_lc_que_ram - #define CCFC_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC1_EN_E5_SHIFT 0 - #define CCFC_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC2_EN_E5 (0x1<<1) // Enable ECC for memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc2 in module cfc_lc_que_ram - #define CCFC_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC2_EN_E5_SHIFT 1 +#define CCFC_REG_MEM_ECC_ENABLE_0 0x2e0210UL //Access:RW DataWidth:0x5 // Multi Field Register. + #define CCFC_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC1_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc1 in module cfc_lc_que_ram + #define CCFC_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC1_EN_E5_SHIFT 0 + #define CCFC_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC2_EN_E5 (0x1<<1) // Enable ECC for memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc2 in module cfc_lc_que_ram + #define CCFC_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC2_EN_E5_SHIFT 1 #define CCFC_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_E5 (0x1<<2) // Enable ECC for memory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram #define CCFC_REG_MEM_ECC_ENABLE_0_MEM001_I_ECC_EN_E5_SHIFT 2 + #define CCFC_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_E5 (0x1<<3) // Enable ECC for memory ecc instance ccfc.i_cfc_core.CFC_RFE_QUE_GEN.i_rfe_que_ctrl_ram.i_ecc in module cfc_rfe_que_ram + #define CCFC_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_E5_SHIFT 3 + #define CCFC_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_E5 (0x1<<4) // Enable ECC for memory ecc instance ccfc.i_cfc_core.CFC_RFE_QUE_GEN.i_rfe_que_upd_ram.i_ecc in module cfc_rfe_que_ram + #define CCFC_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_E5_SHIFT 4 #define CCFC_REG_MEM_ECC_ENABLE_0_MEM_ECC_ENABLE_0_BB_K2 (0x1<<0) // Enable ECC for memory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram #define CCFC_REG_MEM_ECC_ENABLE_0_MEM_ECC_ENABLE_0_BB_K2_SHIFT 0 -#define CCFC_REG_MEM_ECC_PARITY_ONLY_0 0x2e0214UL //Access:RW DataWidth:0x3 // Multi Field Register. - #define CCFC_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC1_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc1 in module cfc_lc_que_ram - #define CCFC_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC1_PRTY_E5_SHIFT 0 - #define CCFC_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC2_PRTY_E5 (0x1<<1) // Set parity only for memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc2 in module cfc_lc_que_ram - #define CCFC_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC2_PRTY_E5_SHIFT 1 +#define CCFC_REG_MEM_ECC_PARITY_ONLY_0 0x2e0214UL //Access:RW DataWidth:0x5 // Multi Field Register. + #define CCFC_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC1_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc1 in module cfc_lc_que_ram + #define CCFC_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC1_PRTY_E5_SHIFT 0 + #define CCFC_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC2_PRTY_E5 (0x1<<1) // Set parity only for memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc2 in module cfc_lc_que_ram + #define CCFC_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC2_PRTY_E5_SHIFT 1 #define CCFC_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_E5 (0x1<<2) // Set parity only for memory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram #define CCFC_REG_MEM_ECC_PARITY_ONLY_0_MEM001_I_ECC_PRTY_E5_SHIFT 2 + #define CCFC_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for memory ecc instance ccfc.i_cfc_core.CFC_RFE_QUE_GEN.i_rfe_que_ctrl_ram.i_ecc in module cfc_rfe_que_ram + #define CCFC_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_E5_SHIFT 3 + #define CCFC_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_E5 (0x1<<4) // Set parity only for memory ecc instance ccfc.i_cfc_core.CFC_RFE_QUE_GEN.i_rfe_que_upd_ram.i_ecc in module cfc_rfe_que_ram + #define CCFC_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_E5_SHIFT 4 #define CCFC_REG_MEM_ECC_PARITY_ONLY_0_MEM_ECC_PARITY_ONLY_0_BB_K2 (0x1<<0) // Set parity only for memory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram #define CCFC_REG_MEM_ECC_PARITY_ONLY_0_MEM_ECC_PARITY_ONLY_0_BB_K2_SHIFT 0 -#define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0 0x2e0218UL //Access:RC DataWidth:0x3 // Multi Field Register. - #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC1_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc1 in module cfc_lc_que_ram - #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC1_CORRECT_E5_SHIFT 0 - #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC2_CORRECT_E5 (0x1<<1) // Record if a correctable error occurred on memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc2 in module cfc_lc_que_ram - #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC2_CORRECT_E5_SHIFT 1 +#define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0 0x2e0218UL //Access:RC DataWidth:0x5 // Multi Field Register. + #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC1_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc1 in module cfc_lc_que_ram + #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC1_CORRECT_E5_SHIFT 0 + #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC2_CORRECT_E5 (0x1<<1) // Record if a correctable error occurred on memory ecc instance ccfc.i_cfc_core.i_lc_que_ram.i_ecc2 in module cfc_lc_que_ram + #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC2_CORRECT_E5_SHIFT 1 #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_E5 (0x1<<2) // Record if a correctable error occurred on memory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM001_I_ECC_CORRECT_E5_SHIFT 2 + #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_E5 (0x1<<3) // Record if a correctable error occurred on memory ecc instance ccfc.i_cfc_core.CFC_RFE_QUE_GEN.i_rfe_que_ctrl_ram.i_ecc in module cfc_rfe_que_ram + #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_E5_SHIFT 3 + #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_E5 (0x1<<4) // Record if a correctable error occurred on memory ecc instance ccfc.i_cfc_core.CFC_RFE_QUE_GEN.i_rfe_que_upd_ram.i_ecc in module cfc_rfe_que_ram + #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_E5_SHIFT 4 #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM_ECC_ERROR_CORRECTED_0_BB_K2 (0x1<<0) // Record if a correctable error occurred on memory ecc instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_ecc in module cfc_sinfo_ram #define CCFC_REG_MEM_ECC_ERROR_CORRECTED_0_MEM_ECC_ERROR_CORRECTED_0_BB_K2_SHIFT 0 #define CCFC_REG_MEM_ECC_EVENTS 0x2e021cUL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. @@ -46975,8 +50451,8 @@ #define CCFC_REG_LCREQ_CREDIT 0x2e0740UL //Access:RW DataWidth:0x6 // Set the initial credit for each of the load clients if less than the max is desired. #define CCFC_REG_LCREQ_CREDIT_SIZE_BB_K2 14 #define CCFC_REG_LCREQ_CREDIT_SIZE_E5 13 -#define CCFC_REG_PRSRESP_CREDIT 0x2e0780UL //Access:RW DataWidth:0x5 // Set the initial credit for the parser response interface if less than the max is desired. -#define CCFC_REG_SEARCH_CREDIT 0x2e0784UL //Access:RW DataWidth:0x5 // Set the initial credit for the searcher interface if less than the max is desired. +#define CCFC_REG_PRSRESP_CREDIT 0x2e0780UL //Access:RW DataWidth:0x7 // Set the initial credit for the parser response interface if less than the max is desired. +#define CCFC_REG_SEARCH_CREDIT 0x2e0784UL //Access:RW DataWidth:0x7 // Set the initial credit for the searcher interface if less than the max is desired. #define CCFC_REG_CDULD_CREDIT 0x2e0788UL //Access:RW DataWidth:0x7 // Set the initial credit for the CDU load interface if less than the max is desired. #define CCFC_REG_CDUWB_CREDIT 0x2e078cUL //Access:RW DataWidth:0x7 // Set the initial credit for the CDU write-back interface if less than the max is desired. #define CCFC_REG_FLOAD_RGN_MSK 0x2e07a0UL //Access:RW DataWidth:0x8 // Array of indirect registers defines the forced load regions per type. Applicable only in the TCFC. @@ -47300,84 +50776,82 @@ #define QM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_E5_SHIFT 3 #define QM_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_E5 (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT . #define QM_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_E5_SHIFT 4 - #define QM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5_SHIFT 5 - #define QM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5_SHIFT 6 - #define QM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5_SHIFT 7 - #define QM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5_SHIFT 8 - #define QM_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_SHIFT 9 + #define QM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5_SHIFT 5 + #define QM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5_SHIFT 6 + #define QM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5_SHIFT 7 + #define QM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5_SHIFT 8 #define QM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_K2 (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_K2_SHIFT 7 - #define QM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_E5_SHIFT 10 - #define QM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5_SHIFT 11 - #define QM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_E5_SHIFT 12 - #define QM_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM044_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_E5_SHIFT 13 - #define QM_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_BB_K2 (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_BB_K2_SHIFT 10 - #define QM_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_E5_SHIFT 14 + #define QM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_E5_SHIFT 9 + #define QM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_K2_SHIFT 8 + #define QM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_E5_SHIFT 10 + #define QM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5_SHIFT 11 + #define QM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_E5_SHIFT 12 + #define QM_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM043_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY_E5_SHIFT 13 #define QM_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_BB_K2 (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_BB_K2_SHIFT 11 - #define QM_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_E5_SHIFT 15 - #define QM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_E5_SHIFT 16 - #define QM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2 (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2_SHIFT 26 - #define QM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_E5_SHIFT 17 - #define QM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5_SHIFT 18 - #define QM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_E5_SHIFT 19 - #define QM_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM046_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY_E5_SHIFT 20 - #define QM_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM045_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY_E5_SHIFT 21 - #define QM_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_BB_K2 (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM056_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_BB_K2_SHIFT 12 - #define QM_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM056_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_E5_SHIFT 22 + #define QM_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_E5_SHIFT 14 + #define QM_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB_K2 (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB_K2_SHIFT 9 + #define QM_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_E5_SHIFT 15 + #define QM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5_SHIFT 16 + #define QM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_E5_SHIFT 17 + #define QM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5_SHIFT 18 + #define QM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_E5_SHIFT 19 + #define QM_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM045_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY_E5_SHIFT 20 + #define QM_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM044_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_E5_SHIFT 21 #define QM_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_BB_K2 (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM055_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_BB_K2_SHIFT 13 - #define QM_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM055_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_E5_SHIFT 23 - #define QM_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_BB_K2 (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM053_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_BB_K2_SHIFT 14 - #define QM_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM053_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_E5_SHIFT 24 + #define QM_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM055_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_E5_SHIFT 22 #define QM_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_BB_K2 (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM054_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_BB_K2_SHIFT 15 - #define QM_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM054_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_E5_SHIFT 25 + #define QM_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM054_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_E5_SHIFT 23 + #define QM_REG_PRTY_MASK_H_0_MEM052_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM052_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM052_I_MEM_PRTY_E5_SHIFT 24 + #define QM_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_BB_K2 (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM053_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_BB_K2_SHIFT 14 + #define QM_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM053_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_E5_SHIFT 25 + #define QM_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_BB_K2 (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM056_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_BB_K2_SHIFT 12 + #define QM_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM056_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_E5_SHIFT 26 #define QM_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY_BB_K2 (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM057_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY_BB_K2_SHIFT 16 - #define QM_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM057_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY_E5_SHIFT 26 - #define QM_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_BB_K2 (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_BB_K2_SHIFT 17 - #define QM_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_E5_SHIFT 27 - #define QM_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_BB_K2 (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM062_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_BB_K2_SHIFT 18 - #define QM_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM062_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_E5_SHIFT 28 + #define QM_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM057_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY_E5_SHIFT 27 #define QM_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_BB_K2 (0x1<<19) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_BB_K2_SHIFT 19 - #define QM_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_E5_SHIFT 29 - #define QM_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_BB_K2 (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_BB_K2_SHIFT 20 - #define QM_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_E5_SHIFT 30 + #define QM_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_E5_SHIFT 28 + #define QM_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_BB_K2 (0x1<<21) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_BB_K2_SHIFT 21 + #define QM_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_E5_SHIFT 29 + #define QM_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_BB_K2 (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_BB_K2_SHIFT 17 + #define QM_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_E5_SHIFT 30 #define QM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM006_I_ECC_0_RF_INT . #define QM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_BB_K2_SHIFT 0 #define QM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_BB_K2 (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM006_I_ECC_1_RF_INT . @@ -47392,10 +50866,12 @@ #define QM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB_K2_SHIFT 5 #define QM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB_K2 (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB_K2_SHIFT 6 - #define QM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_K2_SHIFT 8 - #define QM_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_BB_K2 (0x1<<21) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_BB_K2_SHIFT 21 + #define QM_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_BB_K2 (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_BB_K2_SHIFT 10 + #define QM_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_BB_K2 (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM062_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_BB_K2_SHIFT 18 + #define QM_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_BB_K2 (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_BB_K2_SHIFT 20 #define QM_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_BB_K2 (0x1<<22) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM063_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_BB_K2_SHIFT 22 #define QM_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_BB_K2 (0x1<<23) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM064_I_MEM_PRTY . @@ -47404,6 +50880,8 @@ #define QM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_K2_SHIFT 24 #define QM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_K2 (0x1<<25) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_K2_SHIFT 25 + #define QM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2 (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2_SHIFT 26 #define QM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2 (0x1<<27) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2_SHIFT 27 #define QM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_K2 (0x1<<28) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY . @@ -47413,102 +50891,100 @@ #define QM_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY_BB_K2 (0x1<<30) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM051_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY_BB_K2_SHIFT 30 #define QM_REG_PRTY_MASK_H_1 0x2f0214UL //Access:RW DataWidth:0x1f // Multi Field Register. - #define QM_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM060_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_E5_SHIFT 0 - #define QM_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM063_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY_E5_SHIFT 1 - #define QM_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM064_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY_E5_SHIFT 2 - #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_BB_K2 (0x1<<19) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_BB_K2_SHIFT 19 - #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_E5_SHIFT 3 + #define QM_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM059_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_E5_SHIFT 0 + #define QM_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM062_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_E5_SHIFT 1 + #define QM_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM063_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY_E5_SHIFT 2 #define QM_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_K2 (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_K2_SHIFT 13 - #define QM_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_E5_SHIFT 4 - #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_K2 (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_K2_SHIFT 20 - #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_E5_SHIFT 5 + #define QM_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_E5_SHIFT 3 #define QM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_BB_K2 (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_BB_K2_SHIFT 14 - #define QM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_E5_SHIFT 6 + #define QM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_E5_SHIFT 4 + #define QM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_K2 (0x1<<21) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_K2_SHIFT 21 + #define QM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_E5_SHIFT 5 + #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_K2 (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_K2_SHIFT 20 + #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_E5_SHIFT 6 + #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_BB_K2 (0x1<<19) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_BB_K2_SHIFT 19 + #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_E5_SHIFT 7 #define QM_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_K2 (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_K2_SHIFT 18 - #define QM_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_E5_SHIFT 7 - #define QM_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_K2 (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_K2_SHIFT 26 - #define QM_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_E5_SHIFT 8 - #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_BB_K2 (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM043_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_BB_K2_SHIFT 7 - #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM043_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_E5_SHIFT 9 - #define QM_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_E5_SHIFT 10 + #define QM_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_E5_SHIFT 8 + #define QM_REG_PRTY_MASK_H_1_MEM042_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM042_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM042_I_MEM_PRTY_E5_SHIFT 9 + #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_BB_K2 (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_BB_K2_SHIFT 4 + #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_E5_SHIFT 10 + #define QM_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_BB_K2 (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_BB_K2_SHIFT 6 + #define QM_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_E5_SHIFT 11 + #define QM_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_BB_K2 (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_BB_K2_SHIFT 2 + #define QM_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_E5_SHIFT 12 #define QM_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_BB_K2_SHIFT 0 - #define QM_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_E5_SHIFT 11 + #define QM_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_E5_SHIFT 13 + #define QM_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_E5_SHIFT 14 #define QM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_BB_K2 (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_BB_K2_SHIFT 1 - #define QM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_E5_SHIFT 12 - #define QM_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_BB_K2 (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_BB_K2_SHIFT 2 - #define QM_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_E5_SHIFT 13 - #define QM_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_BB_K2 (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_BB_K2_SHIFT 3 - #define QM_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_E5_SHIFT 14 - #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_BB_K2 (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_BB_K2_SHIFT 4 - #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_E5_SHIFT 15 - #define QM_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_E5_SHIFT 16 - #define QM_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM034_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_E5_SHIFT 17 - #define QM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_E5_SHIFT 18 - #define QM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_E5_SHIFT 19 - #define QM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_K2 (0x1<<21) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_K2_SHIFT 21 - #define QM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_E5_SHIFT 20 - #define QM_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_E5_SHIFT 21 - #define QM_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_E5_SHIFT 22 - #define QM_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM038_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_E5_SHIFT 23 - #define QM_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_E5_SHIFT 24 - #define QM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5_SHIFT 25 - #define QM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5_SHIFT 26 - #define QM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5_SHIFT 27 + #define QM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_E5_SHIFT 15 + #define QM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_E5_SHIFT 16 + #define QM_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_E5_SHIFT 17 + #define QM_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM030_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_E5_SHIFT 18 + #define QM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_E5_SHIFT 19 + #define QM_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_E5_SHIFT 20 + #define QM_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM034_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_E5_SHIFT 21 + #define QM_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_E5_SHIFT 22 + #define QM_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_E5_SHIFT 23 + #define QM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5_SHIFT 24 + #define QM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5_SHIFT 25 + #define QM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5_SHIFT 26 #define QM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_K2 (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_K2_SHIFT 12 - #define QM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_E5_SHIFT 28 + #define QM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_E5_SHIFT 27 #define QM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_K2 (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_K2_SHIFT 15 - #define QM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_E5_SHIFT 29 - #define QM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_E5_SHIFT 30 + #define QM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_E5_SHIFT 28 + #define QM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_E5_SHIFT 29 + #define QM_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_E5_SHIFT 30 + #define QM_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_BB_K2 (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_BB_K2_SHIFT 3 #define QM_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_BB_K2 (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM045_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_BB_K2_SHIFT 5 - #define QM_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_BB_K2 (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_BB_K2_SHIFT 6 + #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_BB_K2 (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM043_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_BB_K2_SHIFT 7 #define QM_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_BB_K2_SHIFT 8 #define QM_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_BB_K2 (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY . @@ -47529,6 +51005,8 @@ #define QM_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_K2_SHIFT 24 #define QM_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_BB_K2 (0x1<<25) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_BB_K2_SHIFT 25 + #define QM_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_K2 (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_K2_SHIFT 26 #define QM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB_K2 (0x1<<27) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY . #define QM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB_K2_SHIFT 27 #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_0_BB_K2 (0x1<<28) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY_0 . @@ -47537,45 +51015,43 @@ #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_1_BB_K2_SHIFT 29 #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_2_BB_K2 (0x1<<30) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY_2 . #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_2_BB_K2_SHIFT 30 -#define QM_REG_PRTY_MASK_H_2 0x2f0224UL //Access:RW DataWidth:0x13 // Multi Field Register. - #define QM_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM006_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_E5_SHIFT 0 - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_0_E5 (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_0 . - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_0_E5_SHIFT 1 - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_1_E5 (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_1 . - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_1_E5_SHIFT 2 - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_2_E5 (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_2 . - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_2_E5_SHIFT 3 - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_3_E5 (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_3 . - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_3_E5_SHIFT 4 - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_4_E5 (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_4 . - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_4_E5_SHIFT 5 - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_5_E5 (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_5 . - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_5_E5_SHIFT 6 - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_6_E5 (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_6 . - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_6_E5_SHIFT 7 - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_7_E5 (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_7 . - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_7_E5_SHIFT 8 - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_8_E5 (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_8 . - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_8_E5_SHIFT 9 - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_9_E5 (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_9 . - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_9_E5_SHIFT 10 - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_10_E5 (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_10 . - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_10_E5_SHIFT 11 - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_11_E5 (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_11 . - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_11_E5_SHIFT 12 - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_12_E5 (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_12 . - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_12_E5_SHIFT 13 - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_13_E5 (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_13 . - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_13_E5_SHIFT 14 - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_14_E5 (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_14 . - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_14_E5_SHIFT 15 - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_15_E5 (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_15 . - #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_15_E5_SHIFT 16 - #define QM_REG_PRTY_MASK_H_2_MEM008_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM008_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_2_MEM008_I_MEM_PRTY_E5_SHIFT 17 - #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY . - #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_E5_SHIFT 18 +#define QM_REG_PRTY_MASK_H_2 0x2f0224UL //Access:RW DataWidth:0x12 // Multi Field Register. + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_0_E5 (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_0 . + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_0_E5_SHIFT 0 + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_1_E5 (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_1 . + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_1_E5_SHIFT 1 + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_2_E5 (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_2 . + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_2_E5_SHIFT 2 + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_3_E5 (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_3 . + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_3_E5_SHIFT 3 + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_4_E5 (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_4 . + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_4_E5_SHIFT 4 + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_5_E5 (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_5 . + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_5_E5_SHIFT 5 + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_6_E5 (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_6 . + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_6_E5_SHIFT 6 + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_7_E5 (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_7 . + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_7_E5_SHIFT 7 + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_8_E5 (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_8 . + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_8_E5_SHIFT 8 + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_9_E5 (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_9 . + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_9_E5_SHIFT 9 + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_10_E5 (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_10 . + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_10_E5_SHIFT 10 + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_11_E5 (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_11 . + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_11_E5_SHIFT 11 + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_12_E5 (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_12 . + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_12_E5_SHIFT 12 + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_13_E5 (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_13 . + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_13_E5_SHIFT 13 + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_14_E5 (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_14 . + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_14_E5_SHIFT 14 + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_15_E5 (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM005_I_MEM_PRTY_15 . + #define QM_REG_PRTY_MASK_H_2_MEM005_I_MEM_PRTY_15_E5_SHIFT 15 + #define QM_REG_PRTY_MASK_H_2_MEM008_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM008_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_2_MEM008_I_MEM_PRTY_E5_SHIFT 16 + #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY . + #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_E5_SHIFT 17 #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_3_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_3 . #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_3_BB_K2_SHIFT 0 #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_4_BB_K2 (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_4 . @@ -47808,86 +51284,86 @@ #define QM_REG_QSTATUSOTHER_1 0x2f10c4UL //Access:R DataWidth:0x20 // Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Queues 96-127 in n=3. #define QM_REG_QSTATUSOTHER_2_K2_E5 0x2f10c8UL //Access:R DataWidth:0x20 // Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Queues 96-127 in n=3. #define QM_REG_QSTATUSOTHER_3_K2_E5 0x2f10ccUL //Access:R DataWidth:0x20 // Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Queues 96-127 in n=3. -#define QM_REG_CTXREGTCFC_0 0x2f1220UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_1 0x2f1224UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_2 0x2f1228UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_3 0x2f122cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_4 0x2f1230UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_5 0x2f1234UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_6 0x2f1238UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_7 0x2f123cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_8 0x2f1240UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_9 0x2f1244UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_10 0x2f1248UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_11 0x2f124cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_12 0x2f1250UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_13 0x2f1254UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_14 0x2f1258UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_15 0x2f125cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_16 0x2f1260UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_17 0x2f1264UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_18 0x2f1268UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_19 0x2f126cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_20 0x2f1270UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_21 0x2f1274UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_22 0x2f1278UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_23 0x2f127cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_24 0x2f1280UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_25 0x2f1284UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_26 0x2f1288UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_27 0x2f128cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_28 0x2f1290UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_29 0x2f1294UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_30 0x2f1298UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_31 0x2f129cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_32 0x2f12a0UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_33 0x2f12a4UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_34 0x2f12a8UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_35 0x2f12acUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_36 0x2f12b0UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_37 0x2f12b4UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_38 0x2f12b8UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGTCFC_39 0x2f12bcUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_0 0x2f1420UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_1 0x2f1424UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_2 0x2f1428UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_3 0x2f142cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_4 0x2f1430UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_5 0x2f1434UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_6 0x2f1438UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_7 0x2f143cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_8 0x2f1440UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_9 0x2f1444UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_10 0x2f1448UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_11 0x2f144cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_12 0x2f1450UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_13 0x2f1454UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_14 0x2f1458UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_15 0x2f145cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_16 0x2f1460UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_17 0x2f1464UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_18 0x2f1468UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_19 0x2f146cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_20 0x2f1470UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_21 0x2f1474UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_22 0x2f1478UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_23 0x2f147cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_24 0x2f1480UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_25 0x2f1484UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_26 0x2f1488UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_27 0x2f148cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_28 0x2f1490UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_29 0x2f1494UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_30 0x2f1498UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_31 0x2f149cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_32 0x2f14a0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_33 0x2f14a4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_34 0x2f14a8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_35 0x2f14acUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_36 0x2f14b0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_37 0x2f14b4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_38 0x2f14b8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALTCFC_39 0x2f14bcUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID) +#define QM_REG_CTXREGTCFC_0 0x2f1220UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_1 0x2f1224UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_2 0x2f1228UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_3 0x2f122cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_4 0x2f1230UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_5 0x2f1234UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_6 0x2f1238UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_7 0x2f123cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_8 0x2f1240UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_9 0x2f1244UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_10 0x2f1248UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_11 0x2f124cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_12 0x2f1250UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_13 0x2f1254UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_14 0x2f1258UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_15 0x2f125cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_16 0x2f1260UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_17 0x2f1264UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_18 0x2f1268UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_19 0x2f126cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_20 0x2f1270UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_21 0x2f1274UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_22 0x2f1278UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_23 0x2f127cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_24 0x2f1280UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_25 0x2f1284UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_26 0x2f1288UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_27 0x2f128cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_28 0x2f1290UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_29 0x2f1294UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_30 0x2f1298UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_31 0x2f129cUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_32 0x2f12a0UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_33 0x2f12a4UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_34 0x2f12a8UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_35 0x2f12acUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_36 0x2f12b0UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_37 0x2f12b4UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_38 0x2f12b8UL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGTCFC_39 0x2f12bcUL //Access:RW DataWidth:0x8 // The context regions sent in the TCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_0 0x2f1420UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_1 0x2f1424UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_2 0x2f1428UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_3 0x2f142cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_4 0x2f1430UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_5 0x2f1434UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_6 0x2f1438UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_7 0x2f143cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_8 0x2f1440UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_9 0x2f1444UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_10 0x2f1448UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_11 0x2f144cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_12 0x2f1450UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_13 0x2f1454UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_14 0x2f1458UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_15 0x2f145cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_16 0x2f1460UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_17 0x2f1464UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_18 0x2f1468UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_19 0x2f146cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_20 0x2f1470UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_21 0x2f1474UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_22 0x2f1478UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_23 0x2f147cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_24 0x2f1480UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_25 0x2f1484UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_26 0x2f1488UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_27 0x2f148cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_28 0x2f1490UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_29 0x2f1494UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_30 0x2f1498UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_31 0x2f149cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_32 0x2f14a0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_33 0x2f14a4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_34 0x2f14a8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_35 0x2f14acUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_36 0x2f14b0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_37 0x2f14b4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_38 0x2f14b8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALTCFC_39 0x2f14bcUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID (only values [0:4])) #define QM_REG_PCIREQQID 0x2f1520UL //Access:RW DataWidth:0x5 // The virtual Queue ID used in the PCI request. #define QM_REG_PCIREQAT 0x2f1524UL //Access:RW DataWidth:0x2 // The PCI attributes field used in the PCI request. #define QM_REG_PCIREQATC 0x2f1528UL //Access:RW DataWidth:0x18 // The PCI ATC flags used in the PCI request. b2-b0: rd first bank in page; b3: reserved (zero); b6-b4: wr first bank in page; b7: reserved (zero); b10-b8: rd middle bank in page; b11: reserved (zero); b14-b12: wr middle bank in page; b15: reserved (zero); b18-b16: rd last bank in page; b19: reserved (zero); b22-b20: wr last bank in page; b23: reserved (zero);. @@ -47896,11 +51372,11 @@ #define QM_REG_PCIREQPADTOCACHELINE 0x2f1534UL //Access:RW DataWidth:0x1 // pad to cache line field as part of PXP write request #define QM_REG_OVFQNUMTX 0x2f1538UL //Access:RC DataWidth:0x9 // The Q were the qverflow occurs. #define QM_REG_OVFERRORTX 0x2f153cUL //Access:RC DataWidth:0x1 // A flag to indicate that overflow error occurred in one of the queues. -#define QM_REG_OVFQNUMOTHER 0x2f1540UL //Access:RC DataWidth:0x6 // The Q were the qverflow occurs. +#define QM_REG_OVFQNUMOTHER 0x2f1540UL //Access:RC DataWidth:0x7 // The Q were the qverflow occurs. #define QM_REG_OVFERROROTHER 0x2f1544UL //Access:RC DataWidth:0x1 // A flag to indicate that overflow error occurred in one of the queues. -#define QM_REG_VOQCRDLINEFULL 0x2f1600UL //Access:R DataWidth:0x20 // VoqCrdLineFull (This one) - VOQs [0..31] VoqCrdLineFull_msb - VOQs [32..35] Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [8..31] are "not used". port_mode == 1 (2 port device) : VOQs [16..31] are "not used". port_mode == 2 (4 port device) : VOQs [6,7,14,15,22,23,30,31] are "not used" When set, inidicates that the VOQ line credit counter is equal to the VOQ line init value. There is a bit per VOQ. +#define QM_REG_VOQCRDLINEFULL 0x2f1600UL //Access:R DataWidth:0x20 // VoqCrdLineFull (This one) - VOQs [0..31] VoqCrdLineFull_msb - VOQs [32..35] Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [8..31] are "not used". port_mode == 1 (2 port device) : VOQs [16..31] are "not used". port_mode == 2 (4 port device) : VOQs [6,7,14,15,22,23,30,31] are "not used" The non-used value will be 1 always. When set, inidicates that the VOQ line credit counter is equal to the VOQ line init value. There is a bit per VOQ. #define QM_REG_TASKLINECRDCOST 0x2f1700UL //Access:RW DataWidth:0x8 // The lineVOQ credit cost per every task in the QM. must be smaller or equal to the matched Voq line credit (relevant only for VOQs that are being used - or in other words VOQs that have at least single PQ that is associated with the VOQ). Granularity of 16B. -#define QM_REG_VOQCRDBYTEFULL 0x2f1800UL //Access:R DataWidth:0x20 // VoqCrdByteFull (This one) - VOQs [0..31]. VoqCrdByteFull_msb - VOQs [32..35]. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [8..31] are "not used". port_mode == 1 (2 port device) : VOQs [16..31] are "not used". port_mode == 2 (4 port device) : VOQs [6,7,14,15,22,23,30,31] are "not used". When set, inidicates that the VOQ byte credit counter is equal to the VOQ byte init value. There is a bit per VOQ. +#define QM_REG_VOQCRDBYTEFULL 0x2f1800UL //Access:R DataWidth:0x20 // VoqCrdByteFull (This one) - VOQs [0..31]. VoqCrdByteFull_msb - VOQs [32..35]. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [8..31] are "not used". port_mode == 1 (2 port device) : VOQs [16..31] are "not used". port_mode == 2 (4 port device) : VOQs [6,7,14,15,22,23,30,31] are "not used". The non-used value will be 1 always. When set, inidicates that the VOQ byte credit counter is equal to the VOQ byte init value. There is a bit per VOQ. #define QM_REG_TASKBYTECRDCOST_0 0x2f1900UL //Access:RW DataWidth:0x10 // The byte credit cost per every task in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functional mode all byte credits will have the same value. must be smaller or equal to the matched Voq byte redit (relevant only for VOQs that are being used - or in other words VOQs that have at least single PQ that is associated with the VOQ). #define QM_REG_TASKBYTECRDCOST_1 0x2f1904UL //Access:RW DataWidth:0x10 // The byte credit cost per every task in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functional mode all byte credits will have the same value. must be smaller or equal to the matched Voq byte redit (relevant only for VOQs that are being used - or in other words VOQs that have at least single PQ that is associated with the VOQ). #define QM_REG_TASKBYTECRDCOST_2 0x2f1908UL //Access:RW DataWidth:0x10 // The byte credit cost per every task in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functional mode all byte credits will have the same value. must be smaller or equal to the matched Voq byte redit (relevant only for VOQs that are being used - or in other words VOQs that have at least single PQ that is associated with the VOQ). @@ -48217,245 +51693,245 @@ #define QM_REG_BASEADDRTXPQ_SIZE_BB 448 #define QM_REG_BASEADDRTXPQ_SIZE_K2_E5 512 #define QM_REG_CTXREGCCFC_0_BB_K2 0x2f1120UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_0_E5 0x2f6800UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_0_E5 0x2f6800UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_1_BB_K2 0x2f1124UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_1_E5 0x2f6804UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_1_E5 0x2f6804UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_2_BB_K2 0x2f1128UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_2_E5 0x2f6808UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_2_E5 0x2f6808UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_3_BB_K2 0x2f112cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_3_E5 0x2f680cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_3_E5 0x2f680cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_4_BB_K2 0x2f1130UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_4_E5 0x2f6810UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_4_E5 0x2f6810UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_5_BB_K2 0x2f1134UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_5_E5 0x2f6814UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_5_E5 0x2f6814UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_6_BB_K2 0x2f1138UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_6_E5 0x2f6818UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_6_E5 0x2f6818UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_7_BB_K2 0x2f113cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_7_E5 0x2f681cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_7_E5 0x2f681cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_8_BB_K2 0x2f1140UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_8_E5 0x2f6820UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_8_E5 0x2f6820UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_9_BB_K2 0x2f1144UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_9_E5 0x2f6824UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_9_E5 0x2f6824UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_10_BB_K2 0x2f1148UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_10_E5 0x2f6828UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_10_E5 0x2f6828UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_11_BB_K2 0x2f114cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_11_E5 0x2f682cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_11_E5 0x2f682cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_12_BB_K2 0x2f1150UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_12_E5 0x2f6830UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_12_E5 0x2f6830UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_13_BB_K2 0x2f1154UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_13_E5 0x2f6834UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_13_E5 0x2f6834UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_14_BB_K2 0x2f1158UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_14_E5 0x2f6838UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_14_E5 0x2f6838UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_15_BB_K2 0x2f115cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_15_E5 0x2f683cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_15_E5 0x2f683cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_16_BB_K2 0x2f1160UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_16_E5 0x2f6840UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_16_E5 0x2f6840UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_17_BB_K2 0x2f1164UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_17_E5 0x2f6844UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_17_E5 0x2f6844UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_18_BB_K2 0x2f1168UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_18_E5 0x2f6848UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_18_E5 0x2f6848UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_19_BB_K2 0x2f116cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_19_E5 0x2f684cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_19_E5 0x2f684cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_20_BB_K2 0x2f1170UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_20_E5 0x2f6850UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_20_E5 0x2f6850UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_21_BB_K2 0x2f1174UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_21_E5 0x2f6854UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_21_E5 0x2f6854UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_22_BB_K2 0x2f1178UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_22_E5 0x2f6858UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_22_E5 0x2f6858UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_23_BB_K2 0x2f117cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_23_E5 0x2f685cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_23_E5 0x2f685cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_24_BB_K2 0x2f1180UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_24_E5 0x2f6860UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_24_E5 0x2f6860UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_25_BB_K2 0x2f1184UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_25_E5 0x2f6864UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_25_E5 0x2f6864UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_26_BB_K2 0x2f1188UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_26_E5 0x2f6868UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_26_E5 0x2f6868UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_27_BB_K2 0x2f118cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_27_E5 0x2f686cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_27_E5 0x2f686cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_28_BB_K2 0x2f1190UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_28_E5 0x2f6870UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_28_E5 0x2f6870UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_29_BB_K2 0x2f1194UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_29_E5 0x2f6874UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_29_E5 0x2f6874UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_30_BB_K2 0x2f1198UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_30_E5 0x2f6878UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_30_E5 0x2f6878UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_31_BB_K2 0x2f119cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_31_E5 0x2f687cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_31_E5 0x2f687cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_32_BB_K2 0x2f11a0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_32_E5 0x2f6880UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_32_E5 0x2f6880UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_33_BB_K2 0x2f11a4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_33_E5 0x2f6884UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_33_E5 0x2f6884UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_34_BB_K2 0x2f11a8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_34_E5 0x2f6888UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_34_E5 0x2f6888UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_35_BB_K2 0x2f11acUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_35_E5 0x2f688cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_35_E5 0x2f688cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_36_BB_K2 0x2f11b0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_36_E5 0x2f6890UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_36_E5 0x2f6890UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_37_BB_K2 0x2f11b4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_37_E5 0x2f6894UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_37_E5 0x2f6894UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_38_BB_K2 0x2f11b8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_38_E5 0x2f6898UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_38_E5 0x2f6898UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_CTXREGCCFC_39_BB_K2 0x2f11bcUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_CTXREGCCFC_39_E5 0x2f689cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_40_E5 0x2f68a0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_41_E5 0x2f68a4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_42_E5 0x2f68a8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_43_E5 0x2f68acUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_44_E5 0x2f68b0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_45_E5 0x2f68b4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_46_E5 0x2f68b8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_47_E5 0x2f68bcUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_48_E5 0x2f68c0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_49_E5 0x2f68c4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_50_E5 0x2f68c8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_51_E5 0x2f68ccUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_52_E5 0x2f68d0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_53_E5 0x2f68d4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_54_E5 0x2f68d8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_55_E5 0x2f68dcUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_56_E5 0x2f68e0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_57_E5 0x2f68e4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_58_E5 0x2f68e8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_59_E5 0x2f68ecUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_60_E5 0x2f68f0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_61_E5 0x2f68f4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_62_E5 0x2f68f8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_63_E5 0x2f68fcUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_64_E5 0x2f6900UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_65_E5 0x2f6904UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_66_E5 0x2f6908UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_67_E5 0x2f690cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_68_E5 0x2f6910UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_69_E5 0x2f6914UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_70_E5 0x2f6918UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_71_E5 0x2f691cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_72_E5 0x2f6920UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_73_E5 0x2f6924UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_74_E5 0x2f6928UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_75_E5 0x2f692cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_76_E5 0x2f6930UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_77_E5 0x2f6934UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_78_E5 0x2f6938UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_CTXREGCCFC_79_E5 0x2f693cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_CTXREGCCFC_39_E5 0x2f689cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_40_E5 0x2f68a0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_41_E5 0x2f68a4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_42_E5 0x2f68a8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_43_E5 0x2f68acUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_44_E5 0x2f68b0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_45_E5 0x2f68b4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_46_E5 0x2f68b8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_47_E5 0x2f68bcUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_48_E5 0x2f68c0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_49_E5 0x2f68c4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_50_E5 0x2f68c8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_51_E5 0x2f68ccUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_52_E5 0x2f68d0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_53_E5 0x2f68d4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_54_E5 0x2f68d8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_55_E5 0x2f68dcUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_56_E5 0x2f68e0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_57_E5 0x2f68e4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_58_E5 0x2f68e8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_59_E5 0x2f68ecUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_60_E5 0x2f68f0UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_61_E5 0x2f68f4UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_62_E5 0x2f68f8UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_63_E5 0x2f68fcUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_64_E5 0x2f6900UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_65_E5 0x2f6904UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_66_E5 0x2f6908UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_67_E5 0x2f690cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_68_E5 0x2f6910UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_69_E5 0x2f6914UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_70_E5 0x2f6918UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_71_E5 0x2f691cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_72_E5 0x2f6920UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_73_E5 0x2f6924UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_74_E5 0x2f6928UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_75_E5 0x2f692cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_76_E5 0x2f6930UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_77_E5 0x2f6934UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_78_E5 0x2f6938UL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_CTXREGCCFC_79_E5 0x2f693cUL //Access:RW DataWidth:0x8 // The context regions sent in the CCFC load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_0_BB_K2 0x2f1320UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_0_E5 0x2f6940UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_0_E5 0x2f6940UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_1_BB_K2 0x2f1324UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_1_E5 0x2f6944UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_1_E5 0x2f6944UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_2_BB_K2 0x2f1328UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_2_E5 0x2f6948UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_2_E5 0x2f6948UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_3_BB_K2 0x2f132cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_3_E5 0x2f694cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_3_E5 0x2f694cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_4_BB_K2 0x2f1330UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_4_E5 0x2f6950UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_4_E5 0x2f6950UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_5_BB_K2 0x2f1334UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_5_E5 0x2f6954UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_5_E5 0x2f6954UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_6_BB_K2 0x2f1338UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_6_E5 0x2f6958UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_6_E5 0x2f6958UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_7_BB_K2 0x2f133cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_7_E5 0x2f695cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_7_E5 0x2f695cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_8_BB_K2 0x2f1340UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_8_E5 0x2f6960UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_8_E5 0x2f6960UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_9_BB_K2 0x2f1344UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_9_E5 0x2f6964UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_9_E5 0x2f6964UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_10_BB_K2 0x2f1348UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_10_E5 0x2f6968UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_10_E5 0x2f6968UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_11_BB_K2 0x2f134cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_11_E5 0x2f696cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_11_E5 0x2f696cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_12_BB_K2 0x2f1350UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_12_E5 0x2f6970UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_12_E5 0x2f6970UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_13_BB_K2 0x2f1354UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_13_E5 0x2f6974UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_13_E5 0x2f6974UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_14_BB_K2 0x2f1358UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_14_E5 0x2f6978UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_14_E5 0x2f6978UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_15_BB_K2 0x2f135cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_15_E5 0x2f697cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_15_E5 0x2f697cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_16_BB_K2 0x2f1360UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_16_E5 0x2f6980UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_16_E5 0x2f6980UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_17_BB_K2 0x2f1364UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_17_E5 0x2f6984UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_17_E5 0x2f6984UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_18_BB_K2 0x2f1368UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_18_E5 0x2f6988UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_18_E5 0x2f6988UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_19_BB_K2 0x2f136cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_19_E5 0x2f698cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_19_E5 0x2f698cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_20_BB_K2 0x2f1370UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_20_E5 0x2f6990UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_20_E5 0x2f6990UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_21_BB_K2 0x2f1374UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_21_E5 0x2f6994UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_21_E5 0x2f6994UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_22_BB_K2 0x2f1378UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_22_E5 0x2f6998UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_22_E5 0x2f6998UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_23_BB_K2 0x2f137cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_23_E5 0x2f699cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_23_E5 0x2f699cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_24_BB_K2 0x2f1380UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_24_E5 0x2f69a0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_24_E5 0x2f69a0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_25_BB_K2 0x2f1384UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_25_E5 0x2f69a4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_25_E5 0x2f69a4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_26_BB_K2 0x2f1388UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_26_E5 0x2f69a8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_26_E5 0x2f69a8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_27_BB_K2 0x2f138cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_27_E5 0x2f69acUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_27_E5 0x2f69acUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_28_BB_K2 0x2f1390UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_28_E5 0x2f69b0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_28_E5 0x2f69b0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_29_BB_K2 0x2f1394UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_29_E5 0x2f69b4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_29_E5 0x2f69b4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_30_BB_K2 0x2f1398UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_30_E5 0x2f69b8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_30_E5 0x2f69b8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_31_BB_K2 0x2f139cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_31_E5 0x2f69bcUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_31_E5 0x2f69bcUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_32_BB_K2 0x2f13a0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_32_E5 0x2f69c0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_32_E5 0x2f69c0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_33_BB_K2 0x2f13a4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_33_E5 0x2f69c4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_33_E5 0x2f69c4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_34_BB_K2 0x2f13a8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_34_E5 0x2f69c8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_34_E5 0x2f69c8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_35_BB_K2 0x2f13acUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_35_E5 0x2f69ccUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_35_E5 0x2f69ccUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_36_BB_K2 0x2f13b0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_36_E5 0x2f69d0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_36_E5 0x2f69d0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_37_BB_K2 0x2f13b4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_37_E5 0x2f69d4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_37_E5 0x2f69d4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_38_BB_K2 0x2f13b8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_38_E5 0x2f69d8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_38_E5 0x2f69d8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_ACTCTRINITVALCCFC_39_BB_K2 0x2f13bcUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_39_E5 0x2f69dcUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_40_E5 0x2f69e0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_41_E5 0x2f69e4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_42_E5 0x2f69e8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_43_E5 0x2f69ecUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_44_E5 0x2f69f0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_45_E5 0x2f69f4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_46_E5 0x2f69f8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_47_E5 0x2f69fcUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_48_E5 0x2f6a00UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_49_E5 0x2f6a04UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_50_E5 0x2f6a08UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_51_E5 0x2f6a0cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_52_E5 0x2f6a10UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_53_E5 0x2f6a14UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_54_E5 0x2f6a18UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_55_E5 0x2f6a1cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_56_E5 0x2f6a20UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_57_E5 0x2f6a24UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_58_E5 0x2f6a28UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_59_E5 0x2f6a2cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_60_E5 0x2f6a30UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_61_E5 0x2f6a34UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_62_E5 0x2f6a38UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_63_E5 0x2f6a3cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_64_E5 0x2f6a40UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_65_E5 0x2f6a44UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_66_E5 0x2f6a48UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_67_E5 0x2f6a4cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_68_E5 0x2f6a50UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_69_E5 0x2f6a54UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_70_E5 0x2f6a58UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_71_E5 0x2f6a5cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_72_E5 0x2f6a60UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_73_E5 0x2f6a64UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_74_E5 0x2f6a68UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_75_E5 0x2f6a6cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_76_E5 0x2f6a70UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_77_E5 0x2f6a74UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_78_E5 0x2f6a78UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) -#define QM_REG_ACTCTRINITVALCCFC_79_E5 0x2f6a7cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID) +#define QM_REG_ACTCTRINITVALCCFC_39_E5 0x2f69dcUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_40_E5 0x2f69e0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_41_E5 0x2f69e4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_42_E5 0x2f69e8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_43_E5 0x2f69ecUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_44_E5 0x2f69f0UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_45_E5 0x2f69f4UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_46_E5 0x2f69f8UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_47_E5 0x2f69fcUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_48_E5 0x2f6a00UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_49_E5 0x2f6a04UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_50_E5 0x2f6a08UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_51_E5 0x2f6a0cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_52_E5 0x2f6a10UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_53_E5 0x2f6a14UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_54_E5 0x2f6a18UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_55_E5 0x2f6a1cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_56_E5 0x2f6a20UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_57_E5 0x2f6a24UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_58_E5 0x2f6a28UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_59_E5 0x2f6a2cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_60_E5 0x2f6a30UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_61_E5 0x2f6a34UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_62_E5 0x2f6a38UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_63_E5 0x2f6a3cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_64_E5 0x2f6a40UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_65_E5 0x2f6a44UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_66_E5 0x2f6a48UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_67_E5 0x2f6a4cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_68_E5 0x2f6a50UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_69_E5 0x2f6a54UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_70_E5 0x2f6a58UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_71_E5 0x2f6a5cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_72_E5 0x2f6a60UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_73_E5 0x2f6a64UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_74_E5 0x2f6a68UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_75_E5 0x2f6a6cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_76_E5 0x2f6a70UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_77_E5 0x2f6a74UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_78_E5 0x2f6a78UL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) +#define QM_REG_ACTCTRINITVALCCFC_79_E5 0x2f6a7cUL //Access:RW DataWidth:0x8 // The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 3:0 = ConnType, bits 6:4 = CM_ID (only values [0:4])) #define QM_REG_PQFILLLVLTX 0x2f7000UL //Access:RW DataWidth:0x18 // The number of tasks queued for each TX queue. Should be read only access. #define QM_REG_PQFILLLVLTX_SIZE_BB 448 #define QM_REG_PQFILLLVLTX_SIZE_K2_E5 512 @@ -48488,29 +51964,29 @@ #define QM_REG_CMINTQMASK_MSB_E5 0x2ff800UL //Access:RW DataWidth:0x8 // An MSB bit vector per CM interface which indicates which one of the Other queues are tied to the matched CM interface. address: 7-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM sec; 63-56 YCM pri; 71-64 XCM sec; for addr[2:0]=0 Other queues 7-0; for addr[2:0]=1 Other queues 15-8; for addr[2:0]=7 Other queues 63-56. #define QM_REG_CMINTQMASK_MSB_SIZE 72 #define QM_REG_VOQCRDLINE_BB_K2 0x2f1580UL //Access:RW DataWidth:0x10 // The actual line credit for each VOQ. Should be read only access in non-init mode. In init mode should be written with the same value of voqinitcrdline. Granularity of 16B. -#define QM_REG_VOQCRDLINE_E5 0x2ffa00UL //Access:RW DataWidth:0x10 // The actual line credit for each VOQ. Should be read only access in non-init mode. In init mode should be written with the same value of voqinitcrdline. Granularity of 16B. +#define QM_REG_VOQCRDLINE_E5 0x2ffa00UL //Access:RW DataWidth:0x10 // The actual line credit for each VOQ. Should be read only access in non-init mode. In init mode should be written with the same value of voqinitcrdline. Granularity of 16B. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [16..31,33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [16..31,34,35] are "not used". port_mode == 2 (4 port device) : VOQs [22,23,30,31] are "not used" NOTE : WR/RD to a "not used" address will not return an ack!!! #define QM_REG_VOQCRDLINE_SIZE_BB 18 #define QM_REG_VOQCRDLINE_SIZE_K2 20 #define QM_REG_VOQCRDLINE_SIZE_E5 36 #define QM_REG_VOQINITCRDLINE_BB_K2 0x2f1680UL //Access:RW DataWidth:0x10 // The init and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of 16B. -#define QM_REG_VOQINITCRDLINE_E5 0x2ffb00UL //Access:RW DataWidth:0x10 // The init and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of 16B. +#define QM_REG_VOQINITCRDLINE_E5 0x2ffb00UL //Access:RW DataWidth:0x10 // The init and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of 16B. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [16..31,33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [16..31,34,35] are "not used". port_mode == 2 (4 port device) : VOQs [22,23,30,31] are "not used" NOTE : WR/RD to a "not used" address will not return an ack!!! #define QM_REG_VOQINITCRDLINE_SIZE_BB 18 #define QM_REG_VOQINITCRDLINE_SIZE_K2 20 #define QM_REG_VOQINITCRDLINE_SIZE_E5 36 #define QM_REG_VOQCRDBYTE_BB_K2 0x2f1780UL //Access:RW DataWidth:0x18 // The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mode should be written with the same value of voqinitcrdbyte. -#define QM_REG_VOQCRDBYTE_E5 0x2ffc00UL //Access:RW DataWidth:0x18 // The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mode should be written with the same value of voqinitcrdbyte. +#define QM_REG_VOQCRDBYTE_E5 0x2ffc00UL //Access:RW DataWidth:0x18 // The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mode should be written with the same value of voqinitcrdbyte. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [16..31,33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [16..31,34,35] are "not used". port_mode == 2 (4 port device) : VOQs [22,23,30,31] are "not used" NOTE : WR/RD to a "not used" address will not return an ack!!! #define QM_REG_VOQCRDBYTE_SIZE_BB 18 #define QM_REG_VOQCRDBYTE_SIZE_K2 20 #define QM_REG_VOQCRDBYTE_SIZE_E5 36 #define QM_REG_VOQINITCRDBYTE_BB_K2 0x2f1880UL //Access:RW DataWidth:0x18 // The init and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16. -#define QM_REG_VOQINITCRDBYTE_E5 0x2ffd00UL //Access:RW DataWidth:0x18 // The init and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16. +#define QM_REG_VOQINITCRDBYTE_E5 0x2ffd00UL //Access:RW DataWidth:0x18 // The init and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [16..31,33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [16..31,34,35] are "not used". port_mode == 2 (4 port device) : VOQs [22,23,30,31] are "not used" NOTE : WR/RD to a "not used" address will not return an ack!!! #define QM_REG_VOQINITCRDBYTE_SIZE_BB 18 #define QM_REG_VOQINITCRDBYTE_SIZE_K2 20 #define QM_REG_VOQINITCRDBYTE_SIZE_E5 36 #define QM_REG_AFULLQMBYPTHRLINEVOQMASK_MSB_E5 0x2ffe00UL //Access:RW DataWidth:0x4 // VOQ line credit almost full threshold mask for the QM bypass feature (per VOQ id bit). AFullQmBypThrLineVoqMask - VOQs [0..31]. AFullQmBypThrLineVoqMask_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [34,35] are "not used". When 1 the VOQ line credit counter should be equal to the VOQ line init value to enable bypass. When 0 - the VOQ line credit counter is don't care, and bypass can be implemented regardless of the VOQ line counter value. #define QM_REG_RLPFVOQENABLE_MSB_E5 0x2ffe04UL //Access:RW DataWidth:0x4 // Enabling the PF RL mechanism per VOQ. RlPfVoqEnable - VOQs [0..31]. RlPfVoqEnable_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [34,35] are "not used". -#define QM_REG_VOQCRDLINEFULL_MSB_E5 0x2ffe08UL //Access:R DataWidth:0x4 // VoqCrdLineFull - VOQs [0..31]. VoqCrdLineFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [34,35] are "not used". When set, inidicates that the VOQ line credit counter is equal to the VOQ line init value. There is a bit per VOQ. -#define QM_REG_VOQCRDBYTEFULL_MSB_E5 0x2ffe0cUL //Access:R DataWidth:0x4 // VoqCrdByteFull - VOQs [0..31]. VoqCrdByteFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [34,35] are "not used". When set, inidicates that the VOQ byte credit counter is equal to the VOQ byte init value. There is a bit per VOQ. +#define QM_REG_VOQCRDLINEFULL_MSB_E5 0x2ffe08UL //Access:R DataWidth:0x4 // VoqCrdLineFull - VOQs [0..31]. VoqCrdLineFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [34,35] are "not used". The non-used value will be 1 always. When set, inidicates that the VOQ line credit counter is equal to the VOQ line init value. There is a bit per VOQ. +#define QM_REG_VOQCRDBYTEFULL_MSB_E5 0x2ffe0cUL //Access:R DataWidth:0x4 // VoqCrdByteFull - VOQs [0..31]. VoqCrdByteFull_msb (This one) - VOQs [32..35]. Some VOQs are "not used" depending on the port_mode. Namely : port_mode == 0 (1 port device) : VOQs [33,34,35] are "not used". port_mode == 1 (2 port device) : VOQs [34,35] are "not used". The non-used value will be 1 always. When set, inidicates that the VOQ byte credit counter is equal to the VOQ byte init value. There is a bit per VOQ. #define RDIF_REG_RESET_MEMORIES 0x300000UL //Access:W DataWidth:0x1 // Write one to this register will write zero to all L1 entries. When the command is complete zero will be indicated in this register. #define RDIF_REG_STOP_ON_ERROR 0x300040UL //Access:RW DataWidth:0x1 // If set and DIF block found error; the DIF block will be stuck - hard reset is needed. #define RDIF_REG_BYPASS_MODE_EN 0x300044UL //Access:RW DataWidth:0x1 // If set allow bypass the pipline on pass through commands and in an empty system. @@ -48896,9 +52372,9 @@ #define RGSRC_REG_MAX_HOPS_EN_E5 0x320408UL //Access:RW DataWidth:0x1 // Stop searching when MAX HOPs is reached #define RGSRC_REG_MAX_HOPS_E5 0x32040cUL //Access:RW DataWidth:0x8 // Number of HOPs, when reached, stop the searching #define RGSRC_REG_HASH_BIN_BIT_W_E5 0x320410UL //Access:RW DataWidth:0x5 // Number of MSB hash bits to be used for bin -#define RGSRC_REG_TABLE_T1_ENTRY_SIZE_E5 0x320448UL //Access:RW DataWidth:0x20 // Size of T1 table entry in 16-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_granularity(16 + N*HASH/8 + N*16*RF_GSRC_CTX_SIZE) if HASH is not aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_granularity(16 + N*8*round_up(HASH/64)); (N - integer number) (HASH is written in bits) -#define RGSRC_REG_TABLE_T2_ENTRY_SIZE_E5 0x32044cUL //Access:RW DataWidth:0x20 // Size of T2 table entry in 16-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_granularity(16 + N*HASH/8 + N*16*RF_GSRC_CTX_SIZE) if HASH is not aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_granularity(16 + N*8*round_up(HASH/64)); (N - integer number) (HASH is written in bits) -#define RGSRC_REG_PXP_CTRL_E5 0x320450UL //Access:RW DataWidth:0x12 // Multi Field Register. +#define RGSRC_REG_TABLE_T1_ENTRY_SIZE_E5 0x320444UL //Access:RW DataWidth:0x20 // Size of T1 table entry in 16-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_granularity(16 + N*HASH/8 + N*16*RF_GSRC_CTX_SIZE) if HASH is not aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_granularity(16 + N*8*round_up(HASH/64)); (N - integer number) (HASH is written in bits) +#define RGSRC_REG_TABLE_T2_ENTRY_SIZE_E5 0x320448UL //Access:RW DataWidth:0x20 // Size of T2 table entry in 16-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_granularity(16 + N*HASH/8 + N*16*RF_GSRC_CTX_SIZE) if HASH is not aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_granularity(16 + N*8*round_up(HASH/64)); (N - integer number) (HASH is written in bits) +#define RGSRC_REG_PXP_CTRL_E5 0x32044cUL //Access:RW DataWidth:0x12 // Multi Field Register. #define RGSRC_REG_PXP_CTRL_VQID_E5 (0x1f<<0) // Controls PXP Request VQID Field #define RGSRC_REG_PXP_CTRL_VQID_E5_SHIFT 0 #define RGSRC_REG_PXP_CTRL_TPH_VALID_E5 (0x1<<5) // Controls PXP Request TPH valid Field @@ -48909,19 +52385,19 @@ #define RGSRC_REG_PXP_CTRL_TPH_INDEX_E5_SHIFT 8 #define RGSRC_REG_PXP_CTRL_DONE_TYPE_E5 (0x1<<17) // Controls PXP Request done type Field #define RGSRC_REG_PXP_CTRL_DONE_TYPE_E5_SHIFT 17 -#define RGSRC_REG_PXP_REQ_CREDIT_E5 0x320454UL //Access:RW DataWidth:0x2 // PXP request intial credits. -#define RGSRC_REG_CFC_REQ_CREDIT_E5 0x320458UL //Access:RW DataWidth:0x4 // CFC request intial credits. -#define RGSRC_REG_NUM_INHOUSE_CMD_E5 0x32045cUL //Access:R DataWidth:0x7 // Number of commands which are currently occupy GSRC FIFO -#define RGSRC_REG_WAS_ERROR_E5 0x320460UL //Access:RW DataWidth:0x8 // Command was found with error. [0] - SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; [3] - ADD cmd result in no match; [4] - ADD cmd already exist; [5] - MAX hops reached; [6] - Magic number error; [7] - PCIe error -#define RGSRC_REG_NUM_SRC_CMD_E5 0x320464UL //Access:RC DataWidth:0x20 // Number of src commands which were recieved by GSRC -#define RGSRC_REG_NUM_NON_SRC_CMD_E5 0x320468UL //Access:RC DataWidth:0x20 // Number of ADD/DEL/CHG commands which were recieved by GSRC -#define RGSRC_REG_NUM_PXP_RD_REQ_E5 0x32046cUL //Access:RC DataWidth:0x20 // Number of PXP read requests which were sent -#define RGSRC_REG_NUM_PXP_RD_DONE_E5 0x320470UL //Access:RC DataWidth:0x20 // Number of PXP read done which were recieved -#define RGSRC_REG_NUM_PXP_WR_REQ_E5 0x320474UL //Access:RC DataWidth:0x20 // Number of PXP write requests which were sent -#define RGSRC_REG_NUM_PXP_WR_DONE_E5 0x320478UL //Access:RC DataWidth:0x20 // Number of PXP write done which were recieved -#define RGSRC_REG_NUM_SRC_CMD_HIT_HOP_1_E5 0x32047cUL //Access:RC DataWidth:0x20 // Number of SRC commands which hit with HOP=1 -#define RGSRC_REG_NUM_SRC_CMD_HIT_HOP_2_E5 0x320480UL //Access:RC DataWidth:0x20 // Number of SRC commands which hit with HOP=2 -#define RGSRC_REG_NUM_SRC_CMD_HIT_HOP_3_OR_MORE_E5 0x320484UL //Access:RC DataWidth:0x20 // Number of SRC commands which hit with HOP=3 or more +#define RGSRC_REG_PXP_REQ_CREDIT_E5 0x320450UL //Access:RW DataWidth:0x2 // PXP request intial credits. +#define RGSRC_REG_CFC_REQ_CREDIT_E5 0x320454UL //Access:RW DataWidth:0x4 // CFC request intial credits. +#define RGSRC_REG_NUM_INHOUSE_CMD_E5 0x320458UL //Access:R DataWidth:0x7 // Number of commands which are currently occupy GSRC FIFO +#define RGSRC_REG_WAS_ERROR_E5 0x32045cUL //Access:RW DataWidth:0x8 // Command was found with error. [0] - SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; [3] - ADD cmd result in no match; [4] - ADD cmd already exist; [5] - MAX hops reached; [6] - Magic number error; [7] - PCIe error +#define RGSRC_REG_NUM_SRC_CMD_E5 0x320460UL //Access:RC DataWidth:0x20 // Number of src commands which were recieved by GSRC +#define RGSRC_REG_NUM_NON_SRC_CMD_E5 0x320464UL //Access:RC DataWidth:0x20 // Number of ADD/DEL/CHG commands which were recieved by GSRC +#define RGSRC_REG_NUM_PXP_RD_REQ_E5 0x320468UL //Access:RC DataWidth:0x20 // Number of PXP read requests which were sent +#define RGSRC_REG_NUM_PXP_RD_DONE_E5 0x32046cUL //Access:RC DataWidth:0x20 // Number of PXP read done which were recieved +#define RGSRC_REG_NUM_PXP_WR_REQ_E5 0x320470UL //Access:RC DataWidth:0x20 // Number of PXP write requests which were sent +#define RGSRC_REG_NUM_PXP_WR_DONE_E5 0x320474UL //Access:RC DataWidth:0x20 // Number of PXP write done which were recieved +#define RGSRC_REG_NUM_SRC_CMD_HIT_HOP_1_E5 0x320478UL //Access:RC DataWidth:0x20 // Number of SRC commands which hit with HOP=1 +#define RGSRC_REG_NUM_SRC_CMD_HIT_HOP_2_E5 0x32047cUL //Access:RC DataWidth:0x20 // Number of SRC commands which hit with HOP=2 +#define RGSRC_REG_NUM_SRC_CMD_HIT_HOP_3_OR_MORE_E5 0x320480UL //Access:RC DataWidth:0x20 // Number of SRC commands which hit with HOP=3 or more #define TGSRC_REG_DBG_SELECT_E5 0x322040UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output #define TGSRC_REG_DBG_DWORD_ENABLE_E5 0x322044UL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line) in the selected line (before shift).for selecting a line to output #define TGSRC_REG_DBG_SHIFT_E5 0x322048UL //Access:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) right shifting of the selected line (after the masking). @@ -48970,9 +52446,9 @@ #define TGSRC_REG_MAX_HOPS_EN_E5 0x322408UL //Access:RW DataWidth:0x1 // Stop searching when MAX HOPs is reached #define TGSRC_REG_MAX_HOPS_E5 0x32240cUL //Access:RW DataWidth:0x8 // Number of HOPs, when reached, stop the searching #define TGSRC_REG_HASH_BIN_BIT_W_E5 0x322410UL //Access:RW DataWidth:0x5 // Number of MSB hash bits to be used for bin -#define TGSRC_REG_TABLE_T1_ENTRY_SIZE_E5 0x322448UL //Access:RW DataWidth:0x20 // Size of T1 table entry in 16-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_granularity(16 + N*HASH/8 + N*16*RF_GSRC_CTX_SIZE) if HASH is not aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_granularity(16 + N*8*round_up(HASH/64)); (N - integer number) (HASH is written in bits) -#define TGSRC_REG_TABLE_T2_ENTRY_SIZE_E5 0x32244cUL //Access:RW DataWidth:0x20 // Size of T2 table entry in 16-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_granularity(16 + N*HASH/8 + N*16*RF_GSRC_CTX_SIZE) if HASH is not aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_granularity(16 + N*8*round_up(HASH/64)); (N - integer number) (HASH is written in bits) -#define TGSRC_REG_PXP_CTRL_E5 0x322450UL //Access:RW DataWidth:0x12 // Multi Field Register. +#define TGSRC_REG_TABLE_T1_ENTRY_SIZE_E5 0x322444UL //Access:RW DataWidth:0x20 // Size of T1 table entry in 16-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_granularity(16 + N*HASH/8 + N*16*RF_GSRC_CTX_SIZE) if HASH is not aligned to 64, set RF_GSRC_TABLE_T1_ENTRY_SIZE = round_up_qreg_granularity(16 + N*8*round_up(HASH/64)); (N - integer number) (HASH is written in bits) +#define TGSRC_REG_TABLE_T2_ENTRY_SIZE_E5 0x322448UL //Access:RW DataWidth:0x20 // Size of T2 table entry in 16-Bytes granularity (QREG). if HASH aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_granularity(16 + N*HASH/8 + N*16*RF_GSRC_CTX_SIZE) if HASH is not aligned to 64, set RF_GSRC_TABLE_T2_ENTRY_SIZE = round_up_qreg_granularity(16 + N*8*round_up(HASH/64)); (N - integer number) (HASH is written in bits) +#define TGSRC_REG_PXP_CTRL_E5 0x32244cUL //Access:RW DataWidth:0x12 // Multi Field Register. #define TGSRC_REG_PXP_CTRL_VQID_E5 (0x1f<<0) // Controls PXP Request VQID Field #define TGSRC_REG_PXP_CTRL_VQID_E5_SHIFT 0 #define TGSRC_REG_PXP_CTRL_TPH_VALID_E5 (0x1<<5) // Controls PXP Request TPH valid Field @@ -48983,19 +52459,19 @@ #define TGSRC_REG_PXP_CTRL_TPH_INDEX_E5_SHIFT 8 #define TGSRC_REG_PXP_CTRL_DONE_TYPE_E5 (0x1<<17) // Controls PXP Request done type Field #define TGSRC_REG_PXP_CTRL_DONE_TYPE_E5_SHIFT 17 -#define TGSRC_REG_PXP_REQ_CREDIT_E5 0x322454UL //Access:RW DataWidth:0x2 // PXP request intial credits. -#define TGSRC_REG_CFC_REQ_CREDIT_E5 0x322458UL //Access:RW DataWidth:0x4 // CFC request intial credits. -#define TGSRC_REG_NUM_INHOUSE_CMD_E5 0x32245cUL //Access:R DataWidth:0x7 // Number of commands which are currently occupy GSRC FIFO -#define TGSRC_REG_WAS_ERROR_E5 0x322460UL //Access:RW DataWidth:0x8 // Command was found with error. [0] - SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; [3] - ADD cmd result in no match; [4] - ADD cmd already exist; [5] - MAX hops reached; [6] - Magic number error; [7] - PCIe error -#define TGSRC_REG_NUM_SRC_CMD_E5 0x322464UL //Access:RC DataWidth:0x20 // Number of src commands which were recieved by GSRC -#define TGSRC_REG_NUM_NON_SRC_CMD_E5 0x322468UL //Access:RC DataWidth:0x20 // Number of ADD/DEL/CHG commands which were recieved by GSRC -#define TGSRC_REG_NUM_PXP_RD_REQ_E5 0x32246cUL //Access:RC DataWidth:0x20 // Number of PXP read requests which were sent -#define TGSRC_REG_NUM_PXP_RD_DONE_E5 0x322470UL //Access:RC DataWidth:0x20 // Number of PXP read done which were recieved -#define TGSRC_REG_NUM_PXP_WR_REQ_E5 0x322474UL //Access:RC DataWidth:0x20 // Number of PXP write requests which were sent -#define TGSRC_REG_NUM_PXP_WR_DONE_E5 0x322478UL //Access:RC DataWidth:0x20 // Number of PXP write done which were recieved -#define TGSRC_REG_NUM_SRC_CMD_HIT_HOP_1_E5 0x32247cUL //Access:RC DataWidth:0x20 // Number of SRC commands which hit with HOP=1 -#define TGSRC_REG_NUM_SRC_CMD_HIT_HOP_2_E5 0x322480UL //Access:RC DataWidth:0x20 // Number of SRC commands which hit with HOP=2 -#define TGSRC_REG_NUM_SRC_CMD_HIT_HOP_3_OR_MORE_E5 0x322484UL //Access:RC DataWidth:0x20 // Number of SRC commands which hit with HOP=3 or more +#define TGSRC_REG_PXP_REQ_CREDIT_E5 0x322450UL //Access:RW DataWidth:0x2 // PXP request intial credits. +#define TGSRC_REG_CFC_REQ_CREDIT_E5 0x322454UL //Access:RW DataWidth:0x4 // CFC request intial credits. +#define TGSRC_REG_NUM_INHOUSE_CMD_E5 0x322458UL //Access:R DataWidth:0x7 // Number of commands which are currently occupy GSRC FIFO +#define TGSRC_REG_WAS_ERROR_E5 0x32245cUL //Access:RW DataWidth:0x8 // Command was found with error. [0] - SRC cmd result in no match; [1] - DEL cmd result in no match; [2] - CHG cmd result in no match; [3] - ADD cmd result in no match; [4] - ADD cmd already exist; [5] - MAX hops reached; [6] - Magic number error; [7] - PCIe error +#define TGSRC_REG_NUM_SRC_CMD_E5 0x322460UL //Access:RC DataWidth:0x20 // Number of src commands which were recieved by GSRC +#define TGSRC_REG_NUM_NON_SRC_CMD_E5 0x322464UL //Access:RC DataWidth:0x20 // Number of ADD/DEL/CHG commands which were recieved by GSRC +#define TGSRC_REG_NUM_PXP_RD_REQ_E5 0x322468UL //Access:RC DataWidth:0x20 // Number of PXP read requests which were sent +#define TGSRC_REG_NUM_PXP_RD_DONE_E5 0x32246cUL //Access:RC DataWidth:0x20 // Number of PXP read done which were recieved +#define TGSRC_REG_NUM_PXP_WR_REQ_E5 0x322470UL //Access:RC DataWidth:0x20 // Number of PXP write requests which were sent +#define TGSRC_REG_NUM_PXP_WR_DONE_E5 0x322474UL //Access:RC DataWidth:0x20 // Number of PXP write done which were recieved +#define TGSRC_REG_NUM_SRC_CMD_HIT_HOP_1_E5 0x322478UL //Access:RC DataWidth:0x20 // Number of SRC commands which hit with HOP=1 +#define TGSRC_REG_NUM_SRC_CMD_HIT_HOP_2_E5 0x32247cUL //Access:RC DataWidth:0x20 // Number of SRC commands which hit with HOP=2 +#define TGSRC_REG_NUM_SRC_CMD_HIT_HOP_3_OR_MORE_E5 0x322480UL //Access:RC DataWidth:0x20 // Number of SRC commands which hit with HOP=3 or more #define BRB_REG_HW_INIT_EN 0x340004UL //Access:RW DataWidth:0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers will be done by HW. Bit 1 - if this bit is set then initialization of BIG RAM will be done by HW. Both bits will be reset by HW when initialization is finished. #define BRB_REG_INIT_DONE 0x340008UL //Access:R DataWidth:0x2 // Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers are finished by HW. Bit 1 - if this bit is set then initialization of BIG RAM is finished by HW. #define BRB_REG_START_EN 0x34000cUL //Access:RW DataWidth:0x1 // This bit should be set when initialization of all BRTB registers and memories is finished. BRTB will fill all prefetch FIFO with free pointers. BRTB will not be able to get packets from write clients when this bit is reset. If link list was configured by HW then this bit will be set by HW. @@ -49062,7 +52538,7 @@ #define BRB_REG_INT_STS_0_PACKET_COUNTER_ERROR_SHIFT 29 #define BRB_REG_INT_STS_0_BYTE_COUNTER_ERROR (0x1<<30) // Byte counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments. #define BRB_REG_INT_STS_0_BYTE_COUNTER_ERROR_SHIFT 30 - #define BRB_REG_INT_STS_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. + #define BRB_REG_INT_STS_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. When unified_shared_area is 1, then the error applies to the common area for all MAC ports. #define BRB_REG_INT_STS_0_MAC0_FC_CNT_ERROR_SHIFT 31 #define BRB_REG_INT_MASK_0 0x3400c4UL //Access:RW DataWidth:0x20 // Multi Field Register. #define BRB_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.ADDRESS_ERROR . @@ -49192,7 +52668,7 @@ #define BRB_REG_INT_STS_WR_0_PACKET_COUNTER_ERROR_SHIFT 29 #define BRB_REG_INT_STS_WR_0_BYTE_COUNTER_ERROR (0x1<<30) // Byte counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments. #define BRB_REG_INT_STS_WR_0_BYTE_COUNTER_ERROR_SHIFT 30 - #define BRB_REG_INT_STS_WR_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. + #define BRB_REG_INT_STS_WR_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. When unified_shared_area is 1, then the error applies to the common area for all MAC ports. #define BRB_REG_INT_STS_WR_0_MAC0_FC_CNT_ERROR_SHIFT 31 #define BRB_REG_INT_STS_CLR_0 0x3400ccUL //Access:RC DataWidth:0x20 // Multi Field Register. #define BRB_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. @@ -49257,10 +52733,10 @@ #define BRB_REG_INT_STS_CLR_0_PACKET_COUNTER_ERROR_SHIFT 29 #define BRB_REG_INT_STS_CLR_0_BYTE_COUNTER_ERROR (0x1<<30) // Byte counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments. #define BRB_REG_INT_STS_CLR_0_BYTE_COUNTER_ERROR_SHIFT 30 - #define BRB_REG_INT_STS_CLR_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. + #define BRB_REG_INT_STS_CLR_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. When unified_shared_area is 1, then the error applies to the common area for all MAC ports. #define BRB_REG_INT_STS_CLR_0_MAC0_FC_CNT_ERROR_SHIFT 31 #define BRB_REG_INT_STS_1 0x3400d8UL //Access:R DataWidth:0x20 // Multi Field Register. - #define BRB_REG_INT_STS_1_MAC1_FC_CNT_ERROR (0x1<<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments. + #define BRB_REG_INT_STS_1_MAC1_FC_CNT_ERROR (0x1<<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments. When unified_shared_area is 1 this error can be ignored. #define BRB_REG_INT_STS_1_MAC1_FC_CNT_ERROR_SHIFT 0 #define BRB_REG_INT_STS_1_LL_ARB_CALC_ERROR (0x1<<1) // Calculations error in LL arbiter block. #define BRB_REG_INT_STS_1_LL_ARB_CALC_ERROR_SHIFT 1 @@ -49382,7 +52858,7 @@ #define BRB_REG_INT_MASK_1_WC1_BB_PA_CNT_ERROR (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_BB_PA_CNT_ERROR . #define BRB_REG_INT_MASK_1_WC1_BB_PA_CNT_ERROR_SHIFT 31 #define BRB_REG_INT_STS_WR_1 0x3400e0UL //Access:WR DataWidth:0x20 // Multi Field Register. - #define BRB_REG_INT_STS_WR_1_MAC1_FC_CNT_ERROR (0x1<<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments. + #define BRB_REG_INT_STS_WR_1_MAC1_FC_CNT_ERROR (0x1<<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments. When unified_shared_area is 1 this error can be ignored. #define BRB_REG_INT_STS_WR_1_MAC1_FC_CNT_ERROR_SHIFT 0 #define BRB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR (0x1<<1) // Calculations error in LL arbiter block. #define BRB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR_SHIFT 1 @@ -49443,7 +52919,7 @@ #define BRB_REG_INT_STS_WR_1_WC1_BB_PA_CNT_ERROR (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments. #define BRB_REG_INT_STS_WR_1_WC1_BB_PA_CNT_ERROR_SHIFT 31 #define BRB_REG_INT_STS_CLR_1 0x3400e4UL //Access:RC DataWidth:0x20 // Multi Field Register. - #define BRB_REG_INT_STS_CLR_1_MAC1_FC_CNT_ERROR (0x1<<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments. + #define BRB_REG_INT_STS_CLR_1_MAC1_FC_CNT_ERROR (0x1<<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments. When unified_shared_area is 1 this error can be ignored. #define BRB_REG_INT_STS_CLR_1_MAC1_FC_CNT_ERROR_SHIFT 0 #define BRB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR (0x1<<1) // Calculations error in LL arbiter block. #define BRB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR_SHIFT 1 @@ -50848,9 +54324,9 @@ #define BRB_REG_INT_STS_11_RC2_EOP_ERROR_SHIFT 10 #define BRB_REG_INT_STS_11_RC3_EOP_ERROR (0x1<<11) // Read EOP client 2 request FIFO error #define BRB_REG_INT_STS_11_RC3_EOP_ERROR_SHIFT 11 - #define BRB_REG_INT_STS_11_MAC2_FC_CNT_ERROR (0x1<<12) // Free shared area calculation error for MAC port 2 + #define BRB_REG_INT_STS_11_MAC2_FC_CNT_ERROR (0x1<<12) // Free shared area calculation error for MAC port 2 When unified_shared_area is 1 this error can be ignored. #define BRB_REG_INT_STS_11_MAC2_FC_CNT_ERROR_SHIFT 12 - #define BRB_REG_INT_STS_11_MAC3_FC_CNT_ERROR (0x1<<13) // Free shared area calculation error for MAC port 3 + #define BRB_REG_INT_STS_11_MAC3_FC_CNT_ERROR (0x1<<13) // Free shared area calculation error for MAC port 3 When unified_shared_area is 1 this error can be ignored. #define BRB_REG_INT_STS_11_MAC3_FC_CNT_ERROR_SHIFT 13 #define BRB_REG_INT_STS_11_WC4_EOP_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 4 #define BRB_REG_INT_STS_11_WC4_EOP_FIFO_ERROR_SHIFT 14 @@ -50882,9 +54358,9 @@ #define BRB_REG_INT_STS_WR_11_RC2_EOP_ERROR_SHIFT 10 #define BRB_REG_INT_STS_WR_11_RC3_EOP_ERROR (0x1<<11) // Read EOP client 2 request FIFO error #define BRB_REG_INT_STS_WR_11_RC3_EOP_ERROR_SHIFT 11 - #define BRB_REG_INT_STS_WR_11_MAC2_FC_CNT_ERROR (0x1<<12) // Free shared area calculation error for MAC port 2 + #define BRB_REG_INT_STS_WR_11_MAC2_FC_CNT_ERROR (0x1<<12) // Free shared area calculation error for MAC port 2 When unified_shared_area is 1 this error can be ignored. #define BRB_REG_INT_STS_WR_11_MAC2_FC_CNT_ERROR_SHIFT 12 - #define BRB_REG_INT_STS_WR_11_MAC3_FC_CNT_ERROR (0x1<<13) // Free shared area calculation error for MAC port 3 + #define BRB_REG_INT_STS_WR_11_MAC3_FC_CNT_ERROR (0x1<<13) // Free shared area calculation error for MAC port 3 When unified_shared_area is 1 this error can be ignored. #define BRB_REG_INT_STS_WR_11_MAC3_FC_CNT_ERROR_SHIFT 13 #define BRB_REG_INT_STS_WR_11_WC4_EOP_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 4 #define BRB_REG_INT_STS_WR_11_WC4_EOP_FIFO_ERROR_SHIFT 14 @@ -50899,9 +54375,9 @@ #define BRB_REG_INT_STS_CLR_11_RC2_EOP_ERROR_SHIFT 10 #define BRB_REG_INT_STS_CLR_11_RC3_EOP_ERROR (0x1<<11) // Read EOP client 2 request FIFO error #define BRB_REG_INT_STS_CLR_11_RC3_EOP_ERROR_SHIFT 11 - #define BRB_REG_INT_STS_CLR_11_MAC2_FC_CNT_ERROR (0x1<<12) // Free shared area calculation error for MAC port 2 + #define BRB_REG_INT_STS_CLR_11_MAC2_FC_CNT_ERROR (0x1<<12) // Free shared area calculation error for MAC port 2 When unified_shared_area is 1 this error can be ignored. #define BRB_REG_INT_STS_CLR_11_MAC2_FC_CNT_ERROR_SHIFT 12 - #define BRB_REG_INT_STS_CLR_11_MAC3_FC_CNT_ERROR (0x1<<13) // Free shared area calculation error for MAC port 3 + #define BRB_REG_INT_STS_CLR_11_MAC3_FC_CNT_ERROR (0x1<<13) // Free shared area calculation error for MAC port 3 When unified_shared_area is 1 this error can be ignored. #define BRB_REG_INT_STS_CLR_11_MAC3_FC_CNT_ERROR_SHIFT 13 #define BRB_REG_INT_STS_CLR_11_WC4_EOP_FIFO_ERROR (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 4 #define BRB_REG_INT_STS_CLR_11_WC4_EOP_FIFO_ERROR_SHIFT 14 @@ -51381,10 +54857,10 @@ #define BRB_REG_FREE_LIST_SIZE_SIZE 4 #define BRB_REG_MAX_RELEASES 0x340840UL //Access:RW DataWidth:0xa // Number of packet copies that should be released before whole packet is released::s/MAX_RLS_WDTH/10/g in Data Width::s/MAX_RLS_RST/512/g in Reset Value::s/MAX_RLS_REQ/required/g in Required::s/MAX_RLS_REQ/required/g in Software init. #define BRB_REG_STOP_ON_LEN_ERR 0x340844UL //Access:RW DataWidth:0x5 // There is bit for each PACKET read client. When bit is set then read client will not execute more requests till reset in a case of length error other way it will continue to work as usual.::s/STOP_LEN_ERR_RST/7/g in Reset Value::s/PKT_RC_NUM/5/g in Data Width. -#define BRB_REG_SHARED_HR_AREA 0x340880UL //Access:RW DataWidth:0xe // The total number available blocks for each MAC port that includes shared and headroom areas. This register should be equal to total_mac_size - SUM(tc_guarantied) Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance. +#define BRB_REG_SHARED_HR_AREA 0x340880UL //Access:RW DataWidth:0xe // The total number available blocks for each MAC port that includes shared and headroom areas. This register should be equal to total_mac_size - SUM(tc_guarantied) Reset value is right for 128B block size only. It should be twice smaller for 256B block size. When unified_shared_area is 1, then the value applies to the common area for all MAC ports. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance. #define BRB_REG_SHARED_HR_AREA_SIZE_BB 2 #define BRB_REG_SHARED_HR_AREA_SIZE_K2_E5 4 -#define BRB_REG_TOTAL_MAC_SIZE 0x3408c0UL //Access:RW DataWidth:0xe // The total number available blocks for each MAC port that includes guaranteed and shared and headroom areas. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance. +#define BRB_REG_TOTAL_MAC_SIZE 0x3408c0UL //Access:RW DataWidth:0xe // The total number available blocks for each MAC port that includes guaranteed and shared and headroom areas. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. When unified_shared_area is 1, then the threshold applies to the common area for all MAC ports. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance. #define BRB_REG_TOTAL_MAC_SIZE_SIZE_BB 2 #define BRB_REG_TOTAL_MAC_SIZE_SIZE_K2_E5 4 #define BRB_REG_TC_GUARANTIED_0 0x340900UL //Access:RW DataWidth:0xe // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance. @@ -51589,8 +55065,8 @@ #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_19_K2_E5 0x340d84UL //Access:RW DataWidth:0xe // The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance. #define BRB_REG_LOSSLESS_THRESHOLD 0x340db0UL //Access:RW DataWidth:0xe // The number of allocated blocks in each TC after asserting pause upper whih full to that TC or interrupt will be asserted depending on lossless_int_en::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance. #define BRB_REG_LOSSLESS_INT_EN 0x340db4UL //Access:RW DataWidth:0x1 // If 1 then interrupt will be asserted when number of allocated blocks in TC bigger lossless_threshold, if 0 - then full to that TC will be asserted.::/PAUSE_EN/d in Existance. -#define BRB_REG_BRTB_EMPTY_FOR_DUP 0x340db8UL //Access:RW DataWidth:0xe // The number of blocks used by the MAC port below which EMPTY[0] is asserted for this MAC port::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Existance. -#define BRB_REG_BRTB_EMPTY_FOR_RDMA 0x340dbcUL //Access:RW DataWidth:0xe // The number of blocks used by the MAC port below which EMPTY[1] is asserted for this MAC port::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Existance. +#define BRB_REG_BRTB_EMPTY_FOR_DUP 0x340db8UL //Access:RW DataWidth:0xe // The number of blocks used by the MAC port below which EMPTY[0] is asserted for this MAC port::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Existance. When unified_shared_area is 1, then the threshold applies to the common area for all MAC ports. +#define BRB_REG_BRTB_EMPTY_FOR_RDMA 0x340dbcUL //Access:RW DataWidth:0xe // The number of blocks used by the MAC port below which EMPTY[1] is asserted for this MAC port::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Existance. When unified_shared_area is 1, then the threshold applies to the common area for all MAC ports. #define BRB_REG_PKT_CNT_THRESHOLD 0x340dc0UL //Access:RW DataWidth:0xe // The number of packets that were read by EOP read client interface but not released by BRTB above which stop parsing interface is asserted::s/BLK_NUM/4800/g in Reset Value::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance. #define BRB_REG_BYTE_CNT_THRESHOLD 0x340dc4UL //Access:RW DataWidth:0x15 // The number of bytes that were read by EOP read client interface but not released by BRTB above which stop parsing interface is asserted::s/BLK_WDTH_PLUS_7/20/g in Data Width::s/BYTE_CNT_RST/614400/g in Reset Value::/PAUSE_EN/d in Existance. #define BRB_REG_NO_DEAD_CYCLES_EN 0x340dc8UL //Access:RW DataWidth:0x5 // There is bit for each PACKET read client. Bit 0 suits to client 0 and so on. If bit is set then packet will be read without dead cycles.B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser ::s/NO_DEAD_CYCLE_RST/1/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments::s/PKT_RC_NUM/5/g in Data Width. @@ -51621,7 +55097,7 @@ #define BRB_REG_QUEUE_FIFO_ALM_FULL 0x340e34UL //Access:RW DataWidth:0x5 // Number of entries inside queue FIFO of each write client upper which full outputs to this write client interface.::s/QUEUE_FIFO_RST/8/g in Reset Value. #define BRB_REG_DSCR_FIFO_HIGH_THRESHOLD 0x340e38UL //Access:RW DataWidth:0x5 // Number of entries inside descriptors FIFO of each write client upper which all arbiters selects this client with high priority. #define BRB_REG_PM_TOTAL_PKT_THRESHOLD 0x340e3cUL //Access:RW DataWidth:0xe // Number of packets above which BRB_above_threshold_mac_n is asserted to power management block::s/BLK_NUM/4800/g in Reset Value::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Existance. -#define BRB_REG_PM_FREE_THRESHOLD 0x340e40UL //Access:RW DataWidth:0xe // Number of free blocks below which BRB_above_threshold_mac_n is asserted to power management block::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Existance. +#define BRB_REG_PM_FREE_THRESHOLD 0x340e40UL //Access:RW DataWidth:0xe // Number of free blocks below which BRB_above_threshold_mac_n is asserted to power management block::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Existance. When unified_shared_area is 1, then the free blocks value is the common free blocks value for all MAC ports. #define BRB_REG_PM_TC_LATENCY_SENSITIVE_0 0x340e44UL //Access:RW DataWidth:0x9 // Per TC enable for output BRB_above_threshold_mac_n to power management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance. #define BRB_REG_PM_TC_LATENCY_SENSITIVE_1 0x340e48UL //Access:RW DataWidth:0x9 // Per TC enable for output BRB_above_threshold_mac_n to power management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance. #define BRB_REG_PM_TC_LATENCY_SENSITIVE_2_K2_E5 0x340e4cUL //Access:RW DataWidth:0x9 // Per TC enable for output BRB_above_threshold_mac_n to power management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance. @@ -51706,10 +55182,10 @@ #define BRB_REG_LL_ARB_EMPTY 0x341084UL //Access:R DataWidth:0x3 // Debug register. Empty status of link list arbiter: {rls_fifo; prefetch_fifo}. #define BRB_REG_LL_ARB_FULL 0x341088UL //Access:R DataWidth:0x3 // Debug register. Full status of link list arbiter: {rls_fifo; prefetch_fifos}. #define BRB_REG_LL_ARB_STATUS 0x34108cUL //Access:R DataWidth:0xe // Debug register. FIFO counters status of link list arbiter: {rls_fifo[7:4]; prefetch_fifo_1[4:0], prefetch_fifo_0[4:0]}. -#define BRB_REG_EMPTY_IF_0 0x341090UL //Access:R DataWidth:0x2 // Debug register. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance. -#define BRB_REG_EMPTY_IF_1 0x341094UL //Access:R DataWidth:0x2 // Debug register. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance. -#define BRB_REG_EMPTY_IF_2_K2_E5 0x341098UL //Access:R DataWidth:0x2 // Debug register. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance. -#define BRB_REG_EMPTY_IF_3_K2_E5 0x34109cUL //Access:R DataWidth:0x2 // Debug register. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance. +#define BRB_REG_EMPTY_IF_0 0x341090UL //Access:R DataWidth:0x2 // Debug register. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance. When unified_shared_area is 1 this only the first index is valid and applies to the global shared area being empty. +#define BRB_REG_EMPTY_IF_1 0x341094UL //Access:R DataWidth:0x2 // Debug register. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance. When unified_shared_area is 1 this only the first index is valid and applies to the global shared area being empty. +#define BRB_REG_EMPTY_IF_2_K2_E5 0x341098UL //Access:R DataWidth:0x2 // Debug register. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance. When unified_shared_area is 1 this only the first index is valid and applies to the global shared area being empty. +#define BRB_REG_EMPTY_IF_3_K2_E5 0x34109cUL //Access:R DataWidth:0x2 // Debug register. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance. When unified_shared_area is 1 this only the first index is valid and applies to the global shared area being empty. #define BRB_REG_RC_SOP_INP_SYNC_FIFO_PUSH_STATUS 0x3410a8UL //Access:R DataWidth:0x3 // Debug register. This is full status of SOP SYNC FIFO for PRS client #define BRB_REG_RC_INP_SYNC_FIFO_PUSH_STATUS_0 0x3410acUL //Access:R DataWidth:0x5 // Debug register. This is full status of packet RC input SYNC FIFO #define BRB_REG_RC_INP_SYNC_FIFO_PUSH_STATUS_1 0x3410b0UL //Access:R DataWidth:0x5 // Debug register. This is full status of packet RC input SYNC FIFO @@ -51764,10 +55240,10 @@ #define BRB_REG_MAC3_TC_OCCUPANCY_2_K2_E5 0x341298UL //Access:R DataWidth:0xe // Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance. #define BRB_REG_MAC3_TC_OCCUPANCY_3_K2_E5 0x34129cUL //Access:R DataWidth:0xe // Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance. #define BRB_REG_MAC3_TC_OCCUPANCY_4_K2_E5 0x3412a0UL //Access:R DataWidth:0xe // Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance. -#define BRB_REG_AVAILABLE_MAC_SIZE_0 0x3412d0UL //Access:R DataWidth:0xe // Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance. -#define BRB_REG_AVAILABLE_MAC_SIZE_1 0x3412d4UL //Access:R DataWidth:0xe // Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance. -#define BRB_REG_AVAILABLE_MAC_SIZE_2_K2_E5 0x3412d8UL //Access:R DataWidth:0xe // Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance. -#define BRB_REG_AVAILABLE_MAC_SIZE_3_K2_E5 0x3412dcUL //Access:R DataWidth:0xe // Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance. +#define BRB_REG_AVAILABLE_MAC_SIZE_0 0x3412d0UL //Access:R DataWidth:0xe // Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas. When unified_shared_area is 1, then the value applies to the common area for all MAC ports, and only the first index of this field is valid. ::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance. +#define BRB_REG_AVAILABLE_MAC_SIZE_1 0x3412d4UL //Access:R DataWidth:0xe // Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas. When unified_shared_area is 1, then the value applies to the common area for all MAC ports, and only the first index of this field is valid. ::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance. +#define BRB_REG_AVAILABLE_MAC_SIZE_2_K2_E5 0x3412d8UL //Access:R DataWidth:0xe // Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas. When unified_shared_area is 1, then the value applies to the common area for all MAC ports, and only the first index of this field is valid. ::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance. +#define BRB_REG_AVAILABLE_MAC_SIZE_3_K2_E5 0x3412dcUL //Access:R DataWidth:0xe // Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas. When unified_shared_area is 1, then the value applies to the common area for all MAC ports, and only the first index of this field is valid. ::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance. #define BRB_REG_MAIN_TC_PAUSE_0 0x3412e8UL //Access:R DataWidth:0x8 // Debug register. Output pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance. #define BRB_REG_MAIN_TC_PAUSE_1 0x3412ecUL //Access:R DataWidth:0x8 // Debug register. Output pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance. #define BRB_REG_MAIN_TC_PAUSE_2_K2_E5 0x3412f0UL //Access:R DataWidth:0x8 // Debug register. Output pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance. @@ -51869,7 +55345,7 @@ #define XYLD_REG_LD_VQID 0x4c0028UL //Access:RW DataWidth:0x5 // VQID value for PXP read requests issued from all sources (PCI read BD fetches and SGE fetches). #define XYLD_REG_CID_REQ_CREDITS 0x4c002cUL //Access:RW DataWidth:0x6 // Max credits value for the load cid request interface. #define XYLD_REG_TID_REQ_CREDITS 0x4c0030UL //Access:RW DataWidth:0x6 // Max credits value for the load tid request interface. -#define XYLD_REG_LD_SEG_MSG_Q 0x4c0034UL //Access:RW DataWidth:0x2 // The QID to which the segment messages can be mapped::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD. +#define XYLD_REG_LD_SEG_MSG_Q_BB_K2 0x4c0034UL //Access:RW DataWidth:0x2 // The QID to which the segment messages can be mapped::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD. #define XYLD_REG_TID_REMAIN_CREDITS 0x4c0038UL //Access:R DataWidth:0x6 // Remaining credits for the tid interface #define XYLD_REG_TID_MSG_STAT 0x4c003cUL //Access:RC DataWidth:0x20 // Statistics counter of TID requests #define XYLD_REG_CID_REMAIN_CREDITS 0x4c0040UL //Access:R DataWidth:0x6 // Remaining credits for the cid interface @@ -51906,12 +55382,12 @@ #define XYLD_REG_CM_HDR_95_64 0x4c00bcUL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_err is raised. #define XYLD_REG_CM_HDR_127_96 0x4c00c0UL //Access:R DataWidth:0x20 // Logging of the cm header cycle - for the case ld_hdr_err is raised. #define XYLD_REG_LD_HDR_CLR 0x4c00c4UL //Access:W DataWidth:0x1 // Writing to this register clears hdr registers and enables logging new error details. -#define XYLD_REG_SEG_MSG_LOG 0x4c00c8UL //Access:R DataWidth:0x8 // Logging register for segment message error: bits 3:0 - header len; bits 7:4 - number of iteration::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD. -#define XYLD_REG_SEG_MSG_LOG_LEN_ARR_31_0 0x4c00ccUL //Access:R DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 31:0 of the segment message length array::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD. -#define XYLD_REG_SEG_MSG_LOG_LEN_ARR_63_32 0x4c00d0UL //Access:R DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 63:32 of the segment message length array::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD. -#define XYLD_REG_SEG_MSG_LOG_LEN_ARR_95_64 0x4c00d4UL //Access:R DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 95:64 of the segment message length array::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD. -#define XYLD_REG_SEG_MSG_LOG_CLR 0x4c00d8UL //Access:W DataWidth:0x1 // Writing to this register clears seg msg logging registers and enables logging new error details::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD. -#define XYLD_REG_SEG_MSG_LOG_V 0x4c00dcUL //Access:R DataWidth:0x1 // Indicates that the data at the seg_msg logging registers is valid::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD. +#define XYLD_REG_SEG_MSG_LOG_BB_K2 0x4c00c8UL //Access:R DataWidth:0x8 // Logging register for segment message error: bits 3:0 - header len; bits 7:4 - number of iteration::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD. +#define XYLD_REG_SEG_MSG_LOG_LEN_ARR_31_0_BB_K2 0x4c00ccUL //Access:R DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 31:0 of the segment message length array::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD. +#define XYLD_REG_SEG_MSG_LOG_LEN_ARR_63_32_BB_K2 0x4c00d0UL //Access:R DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 63:32 of the segment message length array::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD. +#define XYLD_REG_SEG_MSG_LOG_LEN_ARR_95_64_BB_K2 0x4c00d4UL //Access:R DataWidth:0x20 // Logging register for segment message error: bits 31:0 - bits 95:64 of the segment message length array::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD. +#define XYLD_REG_SEG_MSG_LOG_CLR_BB_K2 0x4c00d8UL //Access:W DataWidth:0x1 // Writing to this register clears seg msg logging registers and enables logging new error details::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD. +#define XYLD_REG_SEG_MSG_LOG_V_BB_K2 0x4c00dcUL //Access:R DataWidth:0x1 // Indicates that the data at the seg_msg logging registers is valid::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD. #define XYLD_REG_STAT_FIC_MSG 0x4c00e0UL //Access:RC DataWidth:0x20 // Number of FIC messages sent to the loader #define XYLD_REG_DBG_PENDING_CCFC_REQ 0x4c00e4UL //Access:R DataWidth:0x6 // number of CCFC requests wating for responses #define XYLD_REG_DBG_PENDING_TCFC_REQ 0x4c00e8UL //Access:R DataWidth:0x6 // number of TCFC requests wating for responses @@ -55177,114 +58653,114 @@ #define NIG_REG_INT_STS_CLR_10_LB_SOPQ23_ERROR_E5 (0x1<<15) // Error in the LB SOPQ. #define NIG_REG_INT_STS_CLR_10_LB_SOPQ23_ERROR_E5_SHIFT 15 #define NIG_REG_PRTY_MASK_H_0 0x500204UL //Access:RW DataWidth:0x1f // Multi Field Register. - #define NIG_REG_PRTY_MASK_H_0_MEM118_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM118_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM118_I_MEM_PRTY_E5_SHIFT 0 - #define NIG_REG_PRTY_MASK_H_0_MEM117_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM117_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM117_I_MEM_PRTY_E5_SHIFT 1 - #define NIG_REG_PRTY_MASK_H_0_MEM086_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM086_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM086_I_MEM_PRTY_E5_SHIFT 2 - #define NIG_REG_PRTY_MASK_H_0_MEM085_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM085_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM085_I_MEM_PRTY_E5_SHIFT 3 - #define NIG_REG_PRTY_MASK_H_0_MEM088_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM088_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM088_I_MEM_PRTY_E5_SHIFT 4 - #define NIG_REG_PRTY_MASK_H_0_MEM087_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM087_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM087_I_MEM_PRTY_E5_SHIFT 5 + #define NIG_REG_PRTY_MASK_H_0_MEM116_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM116_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM116_I_MEM_PRTY_E5_SHIFT 0 + #define NIG_REG_PRTY_MASK_H_0_MEM115_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM115_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM115_I_MEM_PRTY_E5_SHIFT 1 + #define NIG_REG_PRTY_MASK_H_0_MEM084_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM084_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM084_I_MEM_PRTY_E5_SHIFT 2 + #define NIG_REG_PRTY_MASK_H_0_MEM083_I_MEM_PRTY_BB (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM083_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM083_I_MEM_PRTY_BB_SHIFT 30 + #define NIG_REG_PRTY_MASK_H_0_MEM083_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM083_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM083_I_MEM_PRTY_E5_SHIFT 3 + #define NIG_REG_PRTY_MASK_H_0_MEM086_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM086_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM086_I_MEM_PRTY_E5_SHIFT 4 + #define NIG_REG_PRTY_MASK_H_0_MEM085_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM085_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM085_I_MEM_PRTY_E5_SHIFT 5 + #define NIG_REG_PRTY_MASK_H_0_MEM088_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM088_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM088_I_MEM_PRTY_E5_SHIFT 6 + #define NIG_REG_PRTY_MASK_H_0_MEM087_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM087_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM087_I_MEM_PRTY_E5_SHIFT 7 #define NIG_REG_PRTY_MASK_H_0_MEM090_I_MEM_PRTY_BB (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM090_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM090_I_MEM_PRTY_BB_SHIFT 4 - #define NIG_REG_PRTY_MASK_H_0_MEM090_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM090_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM090_I_MEM_PRTY_E5_SHIFT 6 + #define NIG_REG_PRTY_MASK_H_0_MEM090_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM090_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM090_I_MEM_PRTY_E5_SHIFT 8 #define NIG_REG_PRTY_MASK_H_0_MEM089_I_MEM_PRTY_BB (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM089_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM089_I_MEM_PRTY_BB_SHIFT 5 - #define NIG_REG_PRTY_MASK_H_0_MEM089_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM089_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM089_I_MEM_PRTY_E5_SHIFT 7 - #define NIG_REG_PRTY_MASK_H_0_MEM092_I_MEM_PRTY_BB (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM092_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM092_I_MEM_PRTY_BB_SHIFT 6 - #define NIG_REG_PRTY_MASK_H_0_MEM092_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM092_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM092_I_MEM_PRTY_E5_SHIFT 8 - #define NIG_REG_PRTY_MASK_H_0_MEM091_I_MEM_PRTY_BB (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM091_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM091_I_MEM_PRTY_BB_SHIFT 7 - #define NIG_REG_PRTY_MASK_H_0_MEM091_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM091_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM091_I_MEM_PRTY_E5_SHIFT 9 - #define NIG_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_K2 (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_K2_SHIFT 28 - #define NIG_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_E5_SHIFT 10 - #define NIG_REG_PRTY_MASK_H_0_MEM072_I_MEM_PRTY_K2 (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM072_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM072_I_MEM_PRTY_K2_SHIFT 5 - #define NIG_REG_PRTY_MASK_H_0_MEM072_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM072_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM072_I_MEM_PRTY_E5_SHIFT 11 - #define NIG_REG_PRTY_MASK_H_0_MEM077_I_MEM_PRTY_K2_E5 (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM077_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM077_I_MEM_PRTY_K2_E5_SHIFT 12 + #define NIG_REG_PRTY_MASK_H_0_MEM089_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM089_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM089_I_MEM_PRTY_E5_SHIFT 9 + #define NIG_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_K2 (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_K2_SHIFT 26 + #define NIG_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_E5_SHIFT 10 + #define NIG_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_K2 (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM070_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_K2_SHIFT 22 + #define NIG_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM070_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_E5_SHIFT 11 + #define NIG_REG_PRTY_MASK_H_0_MEM075_I_MEM_PRTY_K2 (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM075_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM075_I_MEM_PRTY_K2_SHIFT 10 + #define NIG_REG_PRTY_MASK_H_0_MEM075_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM075_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM075_I_MEM_PRTY_E5_SHIFT 12 + #define NIG_REG_PRTY_MASK_H_0_MEM076_I_MEM_PRTY_K2 (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM076_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM076_I_MEM_PRTY_K2_SHIFT 9 + #define NIG_REG_PRTY_MASK_H_0_MEM076_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM076_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM076_I_MEM_PRTY_E5_SHIFT 13 + #define NIG_REG_PRTY_MASK_H_0_MEM077_I_MEM_PRTY_K2 (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM077_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM077_I_MEM_PRTY_K2_SHIFT 12 + #define NIG_REG_PRTY_MASK_H_0_MEM077_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM077_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM077_I_MEM_PRTY_E5_SHIFT 14 #define NIG_REG_PRTY_MASK_H_0_MEM078_I_MEM_PRTY_K2 (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM078_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM078_I_MEM_PRTY_K2_SHIFT 11 - #define NIG_REG_PRTY_MASK_H_0_MEM078_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM078_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM078_I_MEM_PRTY_E5_SHIFT 13 - #define NIG_REG_PRTY_MASK_H_0_MEM079_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM079_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM079_I_MEM_PRTY_E5_SHIFT 14 + #define NIG_REG_PRTY_MASK_H_0_MEM078_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM078_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM078_I_MEM_PRTY_E5_SHIFT 15 + #define NIG_REG_PRTY_MASK_H_0_MEM079_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM079_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM079_I_MEM_PRTY_E5_SHIFT 16 #define NIG_REG_PRTY_MASK_H_0_MEM080_I_MEM_PRTY_BB (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM080_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM080_I_MEM_PRTY_BB_SHIFT 27 - #define NIG_REG_PRTY_MASK_H_0_MEM080_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM080_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM080_I_MEM_PRTY_E5_SHIFT 15 + #define NIG_REG_PRTY_MASK_H_0_MEM080_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM080_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM080_I_MEM_PRTY_E5_SHIFT 17 #define NIG_REG_PRTY_MASK_H_0_MEM081_I_MEM_PRTY_BB (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM081_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM081_I_MEM_PRTY_BB_SHIFT 28 - #define NIG_REG_PRTY_MASK_H_0_MEM081_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM081_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM081_I_MEM_PRTY_E5_SHIFT 16 + #define NIG_REG_PRTY_MASK_H_0_MEM081_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM081_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM081_I_MEM_PRTY_E5_SHIFT 18 #define NIG_REG_PRTY_MASK_H_0_MEM082_I_MEM_PRTY_BB (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM082_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM082_I_MEM_PRTY_BB_SHIFT 29 - #define NIG_REG_PRTY_MASK_H_0_MEM082_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM082_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM082_I_MEM_PRTY_E5_SHIFT 17 - #define NIG_REG_PRTY_MASK_H_0_MEM083_I_MEM_PRTY_BB (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM083_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM083_I_MEM_PRTY_BB_SHIFT 30 - #define NIG_REG_PRTY_MASK_H_0_MEM083_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM083_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM083_I_MEM_PRTY_E5_SHIFT 18 - #define NIG_REG_PRTY_MASK_H_0_MEM084_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM084_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM084_I_MEM_PRTY_E5_SHIFT 19 + #define NIG_REG_PRTY_MASK_H_0_MEM082_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM082_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM082_I_MEM_PRTY_E5_SHIFT 19 + #define NIG_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_K2 (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_K2_SHIFT 27 + #define NIG_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_E5_SHIFT 20 + #define NIG_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_K2 (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_K2_SHIFT 28 + #define NIG_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_E5_SHIFT 21 #define NIG_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_K2 (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM062_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_K2_SHIFT 14 - #define NIG_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM062_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_E5_SHIFT 20 + #define NIG_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM062_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_E5_SHIFT 22 #define NIG_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_K2 (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM063_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_K2_SHIFT 15 - #define NIG_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM063_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_E5_SHIFT 21 + #define NIG_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM063_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_E5_SHIFT 23 #define NIG_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_K2 (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM064_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_K2_SHIFT 16 - #define NIG_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM064_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_E5_SHIFT 22 + #define NIG_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM064_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_E5_SHIFT 24 #define NIG_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY_K2 (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM065_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY_K2_SHIFT 17 - #define NIG_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM065_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY_E5_SHIFT 23 + #define NIG_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM065_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY_E5_SHIFT 25 #define NIG_REG_PRTY_MASK_H_0_MEM066_I_MEM_PRTY_K2 (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM066_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM066_I_MEM_PRTY_K2_SHIFT 18 - #define NIG_REG_PRTY_MASK_H_0_MEM066_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM066_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM066_I_MEM_PRTY_E5_SHIFT 24 + #define NIG_REG_PRTY_MASK_H_0_MEM066_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM066_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM066_I_MEM_PRTY_E5_SHIFT 26 #define NIG_REG_PRTY_MASK_H_0_MEM067_I_MEM_PRTY_K2 (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM067_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM067_I_MEM_PRTY_K2_SHIFT 19 - #define NIG_REG_PRTY_MASK_H_0_MEM067_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM067_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM067_I_MEM_PRTY_E5_SHIFT 25 + #define NIG_REG_PRTY_MASK_H_0_MEM067_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM067_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM067_I_MEM_PRTY_E5_SHIFT 27 #define NIG_REG_PRTY_MASK_H_0_MEM068_I_MEM_PRTY_K2 (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM068_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM068_I_MEM_PRTY_K2_SHIFT 20 - #define NIG_REG_PRTY_MASK_H_0_MEM068_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM068_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM068_I_MEM_PRTY_E5_SHIFT 26 + #define NIG_REG_PRTY_MASK_H_0_MEM068_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM068_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM068_I_MEM_PRTY_E5_SHIFT 28 #define NIG_REG_PRTY_MASK_H_0_MEM069_I_MEM_PRTY_K2 (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM069_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM069_I_MEM_PRTY_K2_SHIFT 21 - #define NIG_REG_PRTY_MASK_H_0_MEM069_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM069_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM069_I_MEM_PRTY_E5_SHIFT 27 - #define NIG_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_K2 (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM070_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_K2_SHIFT 22 - #define NIG_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM070_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_E5_SHIFT 28 + #define NIG_REG_PRTY_MASK_H_0_MEM069_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM069_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM069_I_MEM_PRTY_E5_SHIFT 29 #define NIG_REG_PRTY_MASK_H_0_MEM071_I_MEM_PRTY_K2 (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM071_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM071_I_MEM_PRTY_K2_SHIFT 6 - #define NIG_REG_PRTY_MASK_H_0_MEM071_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM071_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM071_I_MEM_PRTY_E5_SHIFT 29 - #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_BB (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM073_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_BB_SHIFT 26 - #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_K2 (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM073_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_K2_SHIFT 8 - #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM073_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_E5_SHIFT 30 + #define NIG_REG_PRTY_MASK_H_0_MEM071_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM071_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM071_I_MEM_PRTY_E5_SHIFT 30 #define NIG_REG_PRTY_MASK_H_0_MEM107_I_MEM_PRTY_K2 (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM107_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM107_I_MEM_PRTY_K2_SHIFT 0 #define NIG_REG_PRTY_MASK_H_0_MEM103_I_MEM_PRTY_K2 (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM103_I_MEM_PRTY . @@ -55299,12 +58775,14 @@ #define NIG_REG_PRTY_MASK_H_0_MEM106_I_MEM_PRTY_BB_SHIFT 3 #define NIG_REG_PRTY_MASK_H_0_MEM106_I_MEM_PRTY_K2 (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM106_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM106_I_MEM_PRTY_K2_SHIFT 4 + #define NIG_REG_PRTY_MASK_H_0_MEM072_I_MEM_PRTY_K2 (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM072_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM072_I_MEM_PRTY_K2_SHIFT 5 #define NIG_REG_PRTY_MASK_H_0_MEM074_I_MEM_PRTY_K2 (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM074_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM074_I_MEM_PRTY_K2_SHIFT 7 - #define NIG_REG_PRTY_MASK_H_0_MEM076_I_MEM_PRTY_K2 (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM076_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM076_I_MEM_PRTY_K2_SHIFT 9 - #define NIG_REG_PRTY_MASK_H_0_MEM075_I_MEM_PRTY_K2 (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM075_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM075_I_MEM_PRTY_K2_SHIFT 10 + #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_BB (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM073_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_BB_SHIFT 26 + #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_K2 (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM073_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_K2_SHIFT 8 #define NIG_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_K2 (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM055_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_K2_SHIFT 13 #define NIG_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_K2 (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM056_I_MEM_PRTY . @@ -55313,10 +58791,6 @@ #define NIG_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY_K2_SHIFT 24 #define NIG_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_K2 (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_K2_SHIFT 25 - #define NIG_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_K2 (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_K2_SHIFT 26 - #define NIG_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_K2 (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_K2_SHIFT 27 #define NIG_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2 (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2_SHIFT 29 #define NIG_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY_K2 (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM046_I_MEM_PRTY . @@ -55325,6 +58799,10 @@ #define NIG_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY_BB_SHIFT 0 #define NIG_REG_PRTY_MASK_H_0_MEM052_I_MEM_PRTY_BB (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM052_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM052_I_MEM_PRTY_BB_SHIFT 1 + #define NIG_REG_PRTY_MASK_H_0_MEM092_I_MEM_PRTY_BB (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM092_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM092_I_MEM_PRTY_BB_SHIFT 6 + #define NIG_REG_PRTY_MASK_H_0_MEM091_I_MEM_PRTY_BB (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM091_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_0_MEM091_I_MEM_PRTY_BB_SHIFT 7 #define NIG_REG_PRTY_MASK_H_0_MEM109_I_MEM_PRTY_BB (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM109_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM109_I_MEM_PRTY_BB_SHIFT 8 #define NIG_REG_PRTY_MASK_H_0_MEM110_I_MEM_PRTY_BB (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM110_I_MEM_PRTY . @@ -55362,122 +58840,116 @@ #define NIG_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_SHIFT 25 #define NIG_REG_PRTY_MASK_H_1 0x500214UL //Access:RW DataWidth:0x1f // Multi Field Register. + #define NIG_REG_PRTY_MASK_H_1_MEM072_I_MEM_PRTY_BB (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM072_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM072_I_MEM_PRTY_BB_SHIFT 20 + #define NIG_REG_PRTY_MASK_H_1_MEM072_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM072_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM072_I_MEM_PRTY_E5_SHIFT 0 + #define NIG_REG_PRTY_MASK_H_1_MEM073_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM073_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM073_I_MEM_PRTY_E5_SHIFT 1 #define NIG_REG_PRTY_MASK_H_1_MEM074_I_MEM_PRTY_BB (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM074_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM074_I_MEM_PRTY_BB_SHIFT 5 - #define NIG_REG_PRTY_MASK_H_1_MEM074_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM074_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM074_I_MEM_PRTY_E5_SHIFT 0 - #define NIG_REG_PRTY_MASK_H_1_MEM075_I_MEM_PRTY_BB (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM075_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM075_I_MEM_PRTY_BB_SHIFT 6 - #define NIG_REG_PRTY_MASK_H_1_MEM075_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM075_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM075_I_MEM_PRTY_E5_SHIFT 1 - #define NIG_REG_PRTY_MASK_H_1_MEM076_I_MEM_PRTY_BB (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM076_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM076_I_MEM_PRTY_BB_SHIFT 7 - #define NIG_REG_PRTY_MASK_H_1_MEM076_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM076_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM076_I_MEM_PRTY_E5_SHIFT 2 - #define NIG_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_E5_SHIFT 3 - #define NIG_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_K2 (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_K2_SHIFT 16 - #define NIG_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_E5_SHIFT 4 + #define NIG_REG_PRTY_MASK_H_1_MEM074_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM074_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM074_I_MEM_PRTY_E5_SHIFT 2 + #define NIG_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_E5_SHIFT 3 + #define NIG_REG_PRTY_MASK_H_1_MEM042_I_MEM_PRTY_K2 (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM042_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM042_I_MEM_PRTY_K2_SHIFT 14 + #define NIG_REG_PRTY_MASK_H_1_MEM042_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM042_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM042_I_MEM_PRTY_E5_SHIFT 4 + #define NIG_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_K2 (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_K2_SHIFT 4 + #define NIG_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_E5_SHIFT 5 + #define NIG_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_K2 (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_K2_SHIFT 5 + #define NIG_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_E5_SHIFT 6 #define NIG_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_K2 (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_K2_SHIFT 6 - #define NIG_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_E5_SHIFT 5 + #define NIG_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_E5_SHIFT 7 #define NIG_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_K2 (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_K2_SHIFT 7 - #define NIG_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_E5_SHIFT 6 + #define NIG_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_E5_SHIFT 8 #define NIG_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_BB (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_BB_SHIFT 11 - #define NIG_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_E5_SHIFT 7 + #define NIG_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_E5_SHIFT 9 #define NIG_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_BB (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM056_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_BB_SHIFT 21 - #define NIG_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM056_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_E5_SHIFT 8 + #define NIG_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM056_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_E5_SHIFT 10 #define NIG_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_BB (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_BB_SHIFT 22 - #define NIG_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_E5_SHIFT 9 + #define NIG_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_E5_SHIFT 11 #define NIG_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_BB (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_BB_SHIFT 23 - #define NIG_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_E5_SHIFT 10 - #define NIG_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_BB (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM059_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_BB_SHIFT 24 - #define NIG_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM059_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_E5_SHIFT 11 - #define NIG_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_BB (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM060_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_BB_SHIFT 25 - #define NIG_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM060_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_E5_SHIFT 12 - #define NIG_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM034_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_E5_SHIFT 13 - #define NIG_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_E5_SHIFT 14 + #define NIG_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_E5_SHIFT 12 + #define NIG_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_E5_SHIFT 13 + #define NIG_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_E5_SHIFT 14 + #define NIG_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM034_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_E5_SHIFT 15 + #define NIG_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_E5_SHIFT 16 #define NIG_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_K2 (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_K2_SHIFT 8 - #define NIG_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_E5_SHIFT 15 + #define NIG_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_E5_SHIFT 17 #define NIG_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_K2 (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_K2_SHIFT 9 - #define NIG_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_E5_SHIFT 16 + #define NIG_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_E5_SHIFT 18 #define NIG_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_K2 (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM038_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_K2_SHIFT 10 - #define NIG_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM038_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_E5_SHIFT 17 + #define NIG_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM038_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_E5_SHIFT 19 #define NIG_REG_PRTY_MASK_H_1_MEM039_I_MEM_PRTY_K2 (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM039_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM039_I_MEM_PRTY_K2_SHIFT 11 - #define NIG_REG_PRTY_MASK_H_1_MEM039_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM039_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM039_I_MEM_PRTY_E5_SHIFT 18 + #define NIG_REG_PRTY_MASK_H_1_MEM039_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM039_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM039_I_MEM_PRTY_E5_SHIFT 20 #define NIG_REG_PRTY_MASK_H_1_MEM040_I_MEM_PRTY_K2 (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM040_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM040_I_MEM_PRTY_K2_SHIFT 12 - #define NIG_REG_PRTY_MASK_H_1_MEM040_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM040_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM040_I_MEM_PRTY_E5_SHIFT 19 + #define NIG_REG_PRTY_MASK_H_1_MEM040_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM040_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM040_I_MEM_PRTY_E5_SHIFT 21 #define NIG_REG_PRTY_MASK_H_1_MEM041_I_MEM_PRTY_K2 (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM041_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM041_I_MEM_PRTY_K2_SHIFT 13 - #define NIG_REG_PRTY_MASK_H_1_MEM041_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM041_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM041_I_MEM_PRTY_E5_SHIFT 20 - #define NIG_REG_PRTY_MASK_H_1_MEM042_I_MEM_PRTY_K2 (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM042_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM042_I_MEM_PRTY_K2_SHIFT 14 - #define NIG_REG_PRTY_MASK_H_1_MEM042_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM042_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM042_I_MEM_PRTY_E5_SHIFT 21 + #define NIG_REG_PRTY_MASK_H_1_MEM041_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM041_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM041_I_MEM_PRTY_E5_SHIFT 22 #define NIG_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_K2 (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM043_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_K2_SHIFT 15 - #define NIG_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM043_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_E5_SHIFT 22 + #define NIG_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM043_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_E5_SHIFT 23 + #define NIG_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_K2 (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_K2_SHIFT 16 + #define NIG_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_E5_SHIFT 24 #define NIG_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_K2 (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM045_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_K2_SHIFT 17 - #define NIG_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM045_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_E5_SHIFT 23 - #define NIG_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_E5_SHIFT 24 + #define NIG_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM045_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_E5_SHIFT 25 + #define NIG_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_E5_SHIFT 26 #define NIG_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_K2 (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_K2_SHIFT 0 - #define NIG_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_E5_SHIFT 25 + #define NIG_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_E5_SHIFT 27 #define NIG_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_K2 (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_K2_SHIFT 1 - #define NIG_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_E5_SHIFT 26 + #define NIG_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_E5_SHIFT 28 #define NIG_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_K2 (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_K2_SHIFT 2 - #define NIG_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_E5_SHIFT 27 + #define NIG_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_E5_SHIFT 29 #define NIG_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_K2 (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_K2_SHIFT 3 - #define NIG_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_E5_SHIFT 28 - #define NIG_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_K2 (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_K2_SHIFT 4 - #define NIG_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_E5_SHIFT 29 - #define NIG_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_K2 (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_K2_SHIFT 5 - #define NIG_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_E5_SHIFT 30 + #define NIG_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_E5_SHIFT 30 #define NIG_REG_PRTY_MASK_H_1_MEM091_I_MEM_PRTY_K2 (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM091_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM091_I_MEM_PRTY_K2_SHIFT 18 #define NIG_REG_PRTY_MASK_H_1_MEM092_I_MEM_PRTY_K2 (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM092_I_MEM_PRTY . @@ -55514,6 +58986,10 @@ #define NIG_REG_PRTY_MASK_H_1_MEM087_I_MEM_PRTY_BB_SHIFT 3 #define NIG_REG_PRTY_MASK_H_1_MEM088_I_MEM_PRTY_BB (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM088_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM088_I_MEM_PRTY_BB_SHIFT 4 + #define NIG_REG_PRTY_MASK_H_1_MEM075_I_MEM_PRTY_BB (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM075_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM075_I_MEM_PRTY_BB_SHIFT 6 + #define NIG_REG_PRTY_MASK_H_1_MEM076_I_MEM_PRTY_BB (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM076_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM076_I_MEM_PRTY_BB_SHIFT 7 #define NIG_REG_PRTY_MASK_H_1_MEM077_I_MEM_PRTY_BB (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM077_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM077_I_MEM_PRTY_BB_SHIFT 8 #define NIG_REG_PRTY_MASK_H_1_MEM078_I_MEM_PRTY_BB (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM078_I_MEM_PRTY . @@ -55536,8 +59012,10 @@ #define NIG_REG_PRTY_MASK_H_1_MEM070_I_MEM_PRTY_BB_SHIFT 18 #define NIG_REG_PRTY_MASK_H_1_MEM071_I_MEM_PRTY_BB (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM071_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM071_I_MEM_PRTY_BB_SHIFT 19 - #define NIG_REG_PRTY_MASK_H_1_MEM072_I_MEM_PRTY_BB (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM072_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_1_MEM072_I_MEM_PRTY_BB_SHIFT 20 + #define NIG_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_BB (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM059_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_BB_SHIFT 24 + #define NIG_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_BB (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM060_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_BB_SHIFT 25 #define NIG_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY_BB (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM061_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY_BB_SHIFT 26 #define NIG_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_BB (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM062_I_MEM_PRTY . @@ -55549,38 +59027,38 @@ #define NIG_REG_PRTY_MASK_H_1_MEM100_I_MEM_PRTY_BB (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM100_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_1_MEM100_I_MEM_PRTY_BB_SHIFT 30 #define NIG_REG_PRTY_MASK_H_2 0x500224UL //Access:RW DataWidth:0x1f // Multi Field Register. - #define NIG_REG_PRTY_MASK_H_2_MEM105_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM105_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM105_I_MEM_PRTY_E5_SHIFT 0 - #define NIG_REG_PRTY_MASK_H_2_MEM106_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM106_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM106_I_MEM_PRTY_E5_SHIFT 1 - #define NIG_REG_PRTY_MASK_H_2_MEM107_I_MEM_PRTY_BB (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM107_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM107_I_MEM_PRTY_BB_SHIFT 6 - #define NIG_REG_PRTY_MASK_H_2_MEM107_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM107_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM107_I_MEM_PRTY_E5_SHIFT 2 - #define NIG_REG_PRTY_MASK_H_2_MEM108_I_MEM_PRTY_BB (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM108_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM108_I_MEM_PRTY_BB_SHIFT 15 - #define NIG_REG_PRTY_MASK_H_2_MEM108_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM108_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM108_I_MEM_PRTY_E5_SHIFT 3 + #define NIG_REG_PRTY_MASK_H_2_MEM103_I_MEM_PRTY_BB (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM103_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM103_I_MEM_PRTY_BB_SHIFT 13 + #define NIG_REG_PRTY_MASK_H_2_MEM103_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM103_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM103_I_MEM_PRTY_E5_SHIFT 0 + #define NIG_REG_PRTY_MASK_H_2_MEM104_I_MEM_PRTY_BB (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM104_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM104_I_MEM_PRTY_BB_SHIFT 14 + #define NIG_REG_PRTY_MASK_H_2_MEM104_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM104_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM104_I_MEM_PRTY_E5_SHIFT 1 + #define NIG_REG_PRTY_MASK_H_2_MEM105_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM105_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM105_I_MEM_PRTY_E5_SHIFT 2 + #define NIG_REG_PRTY_MASK_H_2_MEM106_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM106_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM106_I_MEM_PRTY_E5_SHIFT 3 + #define NIG_REG_PRTY_MASK_H_2_MEM023_I_MEM_PRTY_K2 (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM023_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM023_I_MEM_PRTY_K2_SHIFT 15 + #define NIG_REG_PRTY_MASK_H_2_MEM023_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM023_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM023_I_MEM_PRTY_E5_SHIFT 4 + #define NIG_REG_PRTY_MASK_H_2_MEM024_I_MEM_PRTY_K2 (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM024_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM024_I_MEM_PRTY_K2_SHIFT 16 + #define NIG_REG_PRTY_MASK_H_2_MEM024_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM024_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM024_I_MEM_PRTY_E5_SHIFT 5 #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_BB (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM025_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_BB_SHIFT 2 #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_K2 (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM025_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_K2_SHIFT 17 - #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM025_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_E5_SHIFT 4 + #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM025_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_E5_SHIFT 6 #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_BB (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM026_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_BB_SHIFT 3 #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_K2 (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM026_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_K2_SHIFT 18 - #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM026_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_E5_SHIFT 5 - #define NIG_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_BB (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM027_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_BB_SHIFT 10 - #define NIG_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM027_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_E5_SHIFT 6 - #define NIG_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_BB (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM028_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_BB_SHIFT 11 - #define NIG_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM028_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_E5_SHIFT 7 + #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM026_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_E5_SHIFT 7 #define NIG_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_E5_SHIFT 8 #define NIG_REG_PRTY_MASK_H_2_MEM012_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM012_I_MEM_PRTY . @@ -55589,32 +59067,34 @@ #define NIG_REG_PRTY_MASK_H_2_MEM013_I_MEM_PRTY_E5_SHIFT 10 #define NIG_REG_PRTY_MASK_H_2_MEM014_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM014_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM014_I_MEM_PRTY_E5_SHIFT 11 - #define NIG_REG_PRTY_MASK_H_2_MEM109_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM109_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM109_I_MEM_PRTY_E5_SHIFT 12 - #define NIG_REG_PRTY_MASK_H_2_MEM110_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM110_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM110_I_MEM_PRTY_E5_SHIFT 13 - #define NIG_REG_PRTY_MASK_H_2_MEM111_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM111_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM111_I_MEM_PRTY_E5_SHIFT 14 - #define NIG_REG_PRTY_MASK_H_2_MEM112_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM112_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM112_I_MEM_PRTY_E5_SHIFT 15 + #define NIG_REG_PRTY_MASK_H_2_MEM107_I_MEM_PRTY_BB (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM107_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM107_I_MEM_PRTY_BB_SHIFT 6 + #define NIG_REG_PRTY_MASK_H_2_MEM107_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM107_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM107_I_MEM_PRTY_E5_SHIFT 12 + #define NIG_REG_PRTY_MASK_H_2_MEM108_I_MEM_PRTY_BB (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM108_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM108_I_MEM_PRTY_BB_SHIFT 15 + #define NIG_REG_PRTY_MASK_H_2_MEM108_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM108_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM108_I_MEM_PRTY_E5_SHIFT 13 + #define NIG_REG_PRTY_MASK_H_2_MEM109_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM109_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM109_I_MEM_PRTY_E5_SHIFT 14 + #define NIG_REG_PRTY_MASK_H_2_MEM110_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM110_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM110_I_MEM_PRTY_E5_SHIFT 15 + #define NIG_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_BB (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM027_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_BB_SHIFT 10 + #define NIG_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM027_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_E5_SHIFT 16 + #define NIG_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_BB (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM028_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_BB_SHIFT 11 + #define NIG_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM028_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_E5_SHIFT 17 #define NIG_REG_PRTY_MASK_H_2_MEM029_I_MEM_PRTY_BB (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM029_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM029_I_MEM_PRTY_BB_SHIFT 19 - #define NIG_REG_PRTY_MASK_H_2_MEM029_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM029_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM029_I_MEM_PRTY_E5_SHIFT 16 + #define NIG_REG_PRTY_MASK_H_2_MEM029_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM029_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM029_I_MEM_PRTY_E5_SHIFT 18 #define NIG_REG_PRTY_MASK_H_2_MEM030_I_MEM_PRTY_BB (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM030_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM030_I_MEM_PRTY_BB_SHIFT 20 - #define NIG_REG_PRTY_MASK_H_2_MEM030_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM030_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM030_I_MEM_PRTY_E5_SHIFT 17 - #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_BB (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM031_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_BB_SHIFT 21 - #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_K2 (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM031_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_K2_SHIFT 3 - #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM031_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_E5_SHIFT 18 - #define NIG_REG_PRTY_MASK_H_2_MEM032_I_MEM_PRTY_K2 (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM032_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM032_I_MEM_PRTY_K2_SHIFT 4 - #define NIG_REG_PRTY_MASK_H_2_MEM032_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM032_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM032_I_MEM_PRTY_E5_SHIFT 19 + #define NIG_REG_PRTY_MASK_H_2_MEM030_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM030_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM030_I_MEM_PRTY_E5_SHIFT 19 #define NIG_REG_PRTY_MASK_H_2_MEM015_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM015_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM015_I_MEM_PRTY_E5_SHIFT 20 #define NIG_REG_PRTY_MASK_H_2_MEM016_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM016_I_MEM_PRTY . @@ -55623,14 +59103,14 @@ #define NIG_REG_PRTY_MASK_H_2_MEM017_I_MEM_PRTY_E5_SHIFT 22 #define NIG_REG_PRTY_MASK_H_2_MEM018_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM018_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM018_I_MEM_PRTY_E5_SHIFT 23 - #define NIG_REG_PRTY_MASK_H_2_MEM113_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM113_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM113_I_MEM_PRTY_E5_SHIFT 24 - #define NIG_REG_PRTY_MASK_H_2_MEM114_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM114_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM114_I_MEM_PRTY_E5_SHIFT 25 - #define NIG_REG_PRTY_MASK_H_2_MEM115_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM115_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM115_I_MEM_PRTY_E5_SHIFT 26 - #define NIG_REG_PRTY_MASK_H_2_MEM116_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM116_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM116_I_MEM_PRTY_E5_SHIFT 27 + #define NIG_REG_PRTY_MASK_H_2_MEM111_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM111_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM111_I_MEM_PRTY_E5_SHIFT 24 + #define NIG_REG_PRTY_MASK_H_2_MEM112_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM112_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM112_I_MEM_PRTY_E5_SHIFT 25 + #define NIG_REG_PRTY_MASK_H_2_MEM113_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM113_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM113_I_MEM_PRTY_E5_SHIFT 26 + #define NIG_REG_PRTY_MASK_H_2_MEM114_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM114_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM114_I_MEM_PRTY_E5_SHIFT 27 #define NIG_REG_PRTY_MASK_H_2_MEM019_I_MEM_PRTY_K2 (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM019_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM019_I_MEM_PRTY_K2_SHIFT 7 #define NIG_REG_PRTY_MASK_H_2_MEM019_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM019_I_MEM_PRTY . @@ -55657,6 +59137,12 @@ #define NIG_REG_PRTY_MASK_H_2_MEM098_I_MEM_PRTY_BB_SHIFT 30 #define NIG_REG_PRTY_MASK_H_2_MEM098_I_MEM_PRTY_K2 (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM098_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM098_I_MEM_PRTY_K2_SHIFT 2 + #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_BB (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM031_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_BB_SHIFT 21 + #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_K2 (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM031_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_K2_SHIFT 3 + #define NIG_REG_PRTY_MASK_H_2_MEM032_I_MEM_PRTY_K2 (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM032_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_2_MEM032_I_MEM_PRTY_K2_SHIFT 4 #define NIG_REG_PRTY_MASK_H_2_MEM033_I_MEM_PRTY_BB (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM033_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM033_I_MEM_PRTY_BB_SHIFT 12 #define NIG_REG_PRTY_MASK_H_2_MEM033_I_MEM_PRTY_K2 (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM033_I_MEM_PRTY . @@ -55681,10 +59167,6 @@ #define NIG_REG_PRTY_MASK_H_2_MEM102_I_MEM_PRTY_BB_SHIFT 5 #define NIG_REG_PRTY_MASK_H_2_MEM102_I_MEM_PRTY_K2 (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM102_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM102_I_MEM_PRTY_K2_SHIFT 14 - #define NIG_REG_PRTY_MASK_H_2_MEM023_I_MEM_PRTY_K2 (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM023_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM023_I_MEM_PRTY_K2_SHIFT 15 - #define NIG_REG_PRTY_MASK_H_2_MEM024_I_MEM_PRTY_K2 (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM024_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM024_I_MEM_PRTY_K2_SHIFT 16 #define NIG_REG_PRTY_MASK_H_2_MEM083_I_MEM_PRTY_K2 (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM083_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM083_I_MEM_PRTY_K2_SHIFT 19 #define NIG_REG_PRTY_MASK_H_2_MEM084_I_MEM_PRTY_K2 (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM084_I_MEM_PRTY . @@ -55719,10 +59201,6 @@ #define NIG_REG_PRTY_MASK_H_2_MEM048_I_MEM_PRTY_BB_SHIFT 8 #define NIG_REG_PRTY_MASK_H_2_MEM053_I_MEM_PRTY_BB (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM053_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM053_I_MEM_PRTY_BB_SHIFT 9 - #define NIG_REG_PRTY_MASK_H_2_MEM103_I_MEM_PRTY_BB (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM103_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM103_I_MEM_PRTY_BB_SHIFT 13 - #define NIG_REG_PRTY_MASK_H_2_MEM104_I_MEM_PRTY_BB (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM104_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_2_MEM104_I_MEM_PRTY_BB_SHIFT 14 #define NIG_REG_PRTY_MASK_H_2_MEM049_I_MEM_PRTY_BB (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM049_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM049_I_MEM_PRTY_BB_SHIFT 16 #define NIG_REG_PRTY_MASK_H_2_MEM050_I_MEM_PRTY_BB (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM050_I_MEM_PRTY . @@ -55735,17 +59213,17 @@ #define NIG_REG_PRTY_MASK_H_2_MEM034_EXT_I_MEM_PRTY_BB_SHIFT 24 #define NIG_REG_PRTY_MASK_H_2_MEM095_I_MEM_PRTY_BB (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM095_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_2_MEM095_I_MEM_PRTY_BB_SHIFT 25 -#define NIG_REG_PRTY_MASK_H_3 0x500234UL //Access:RW DataWidth:0x19 // Multi Field Register. +#define NIG_REG_PRTY_MASK_H_3 0x500234UL //Access:RW DataWidth:0x17 // Multi Field Register. #define NIG_REG_PRTY_MASK_H_3_MEM022_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM022_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_3_MEM022_I_MEM_PRTY_E5_SHIFT 0 - #define NIG_REG_PRTY_MASK_H_3_MEM097_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM097_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_3_MEM097_I_MEM_PRTY_E5_SHIFT 1 - #define NIG_REG_PRTY_MASK_H_3_MEM098_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM098_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_3_MEM098_I_MEM_PRTY_E5_SHIFT 2 - #define NIG_REG_PRTY_MASK_H_3_MEM099_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM099_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_3_MEM099_I_MEM_PRTY_E5_SHIFT 3 - #define NIG_REG_PRTY_MASK_H_3_MEM100_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM100_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_3_MEM100_I_MEM_PRTY_E5_SHIFT 4 + #define NIG_REG_PRTY_MASK_H_3_MEM095_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM095_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_3_MEM095_I_MEM_PRTY_E5_SHIFT 1 + #define NIG_REG_PRTY_MASK_H_3_MEM096_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM096_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_3_MEM096_I_MEM_PRTY_E5_SHIFT 2 + #define NIG_REG_PRTY_MASK_H_3_MEM097_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM097_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_3_MEM097_I_MEM_PRTY_E5_SHIFT 3 + #define NIG_REG_PRTY_MASK_H_3_MEM098_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM098_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_3_MEM098_I_MEM_PRTY_E5_SHIFT 4 #define NIG_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_K2 (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM003_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_K2_SHIFT 10 #define NIG_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM003_I_MEM_PRTY . @@ -55762,14 +59240,14 @@ #define NIG_REG_PRTY_MASK_H_3_MEM006_I_MEM_PRTY_K2_SHIFT 13 #define NIG_REG_PRTY_MASK_H_3_MEM006_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM006_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_3_MEM006_I_MEM_PRTY_E5_SHIFT 8 - #define NIG_REG_PRTY_MASK_H_3_MEM101_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM101_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_3_MEM101_I_MEM_PRTY_E5_SHIFT 9 - #define NIG_REG_PRTY_MASK_H_3_MEM102_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM102_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_3_MEM102_I_MEM_PRTY_E5_SHIFT 10 - #define NIG_REG_PRTY_MASK_H_3_MEM103_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM103_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_3_MEM103_I_MEM_PRTY_E5_SHIFT 11 - #define NIG_REG_PRTY_MASK_H_3_MEM104_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM104_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_3_MEM104_I_MEM_PRTY_E5_SHIFT 12 + #define NIG_REG_PRTY_MASK_H_3_MEM099_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM099_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_3_MEM099_I_MEM_PRTY_E5_SHIFT 9 + #define NIG_REG_PRTY_MASK_H_3_MEM100_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM100_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_3_MEM100_I_MEM_PRTY_E5_SHIFT 10 + #define NIG_REG_PRTY_MASK_H_3_MEM101_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM101_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_3_MEM101_I_MEM_PRTY_E5_SHIFT 11 + #define NIG_REG_PRTY_MASK_H_3_MEM102_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM102_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_3_MEM102_I_MEM_PRTY_E5_SHIFT 12 #define NIG_REG_PRTY_MASK_H_3_MEM007_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM007_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_3_MEM007_I_MEM_PRTY_E5_SHIFT 13 #define NIG_REG_PRTY_MASK_H_3_MEM008_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM008_I_MEM_PRTY . @@ -55786,26 +59264,18 @@ #define NIG_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_K2_SHIFT 5 #define NIG_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_E5_SHIFT 18 + #define NIG_REG_PRTY_MASK_H_3_MEM091_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM091_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_3_MEM091_I_MEM_PRTY_E5_SHIFT 19 + #define NIG_REG_PRTY_MASK_H_3_MEM092_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM092_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_3_MEM092_I_MEM_PRTY_E5_SHIFT 20 #define NIG_REG_PRTY_MASK_H_3_MEM093_I_MEM_PRTY_BB (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM093_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_3_MEM093_I_MEM_PRTY_BB_SHIFT 4 - #define NIG_REG_PRTY_MASK_H_3_MEM093_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM093_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_3_MEM093_I_MEM_PRTY_E5_SHIFT 19 + #define NIG_REG_PRTY_MASK_H_3_MEM093_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM093_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_3_MEM093_I_MEM_PRTY_E5_SHIFT 21 #define NIG_REG_PRTY_MASK_H_3_MEM094_I_MEM_PRTY_BB (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM094_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_3_MEM094_I_MEM_PRTY_BB_SHIFT 5 - #define NIG_REG_PRTY_MASK_H_3_MEM094_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM094_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_3_MEM094_I_MEM_PRTY_E5_SHIFT 20 - #define NIG_REG_PRTY_MASK_H_3_MEM095_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM095_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_3_MEM095_I_MEM_PRTY_E5_SHIFT 21 - #define NIG_REG_PRTY_MASK_H_3_MEM096_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM096_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_3_MEM096_I_MEM_PRTY_E5_SHIFT 22 - #define NIG_REG_PRTY_MASK_H_3_MEM024_I_MEM_PRTY_BB (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM024_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_3_MEM024_I_MEM_PRTY_BB_SHIFT 1 - #define NIG_REG_PRTY_MASK_H_3_MEM024_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM024_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_3_MEM024_I_MEM_PRTY_E5_SHIFT 23 - #define NIG_REG_PRTY_MASK_H_3_MEM023_I_MEM_PRTY_BB (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM023_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_3_MEM023_I_MEM_PRTY_BB_SHIFT 0 - #define NIG_REG_PRTY_MASK_H_3_MEM023_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM023_I_MEM_PRTY . - #define NIG_REG_PRTY_MASK_H_3_MEM023_I_MEM_PRTY_E5_SHIFT 24 + #define NIG_REG_PRTY_MASK_H_3_MEM094_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM094_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_3_MEM094_I_MEM_PRTY_E5_SHIFT 22 #define NIG_REG_PRTY_MASK_H_3_MEM011_I_MEM_PRTY_K2 (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM011_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_3_MEM011_I_MEM_PRTY_K2_SHIFT 0 #define NIG_REG_PRTY_MASK_H_3_MEM012_I_MEM_PRTY_K2 (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM012_I_MEM_PRTY . @@ -55822,6 +59292,10 @@ #define NIG_REG_PRTY_MASK_H_3_MEM081_I_MEM_PRTY_K2_SHIFT 8 #define NIG_REG_PRTY_MASK_H_3_MEM082_I_MEM_PRTY_K2 (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM082_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_3_MEM082_I_MEM_PRTY_K2_SHIFT 9 + #define NIG_REG_PRTY_MASK_H_3_MEM023_I_MEM_PRTY_BB (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM023_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_3_MEM023_I_MEM_PRTY_BB_SHIFT 0 + #define NIG_REG_PRTY_MASK_H_3_MEM024_I_MEM_PRTY_BB (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM024_I_MEM_PRTY . + #define NIG_REG_PRTY_MASK_H_3_MEM024_I_MEM_PRTY_BB_SHIFT 1 #define NIG_REG_PRTY_MASK_H_3_MEM017_I_MEM_PRTY_BB (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM017_I_MEM_PRTY . #define NIG_REG_PRTY_MASK_H_3_MEM017_I_MEM_PRTY_BB_SHIFT 2 #define NIG_REG_PRTY_MASK_H_3_MEM018_I_MEM_PRTY_BB (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM018_I_MEM_PRTY . @@ -57812,7 +61286,7 @@ #define BMB_REG_INT_STS_0_WC3_PROTOCOL_ERROR_SHIFT 26 #define BMB_REG_INT_STS_0_LL_BLK_ERROR (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks. #define BMB_REG_INT_STS_0_LL_BLK_ERROR_SHIFT 28 - #define BMB_REG_INT_STS_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. + #define BMB_REG_INT_STS_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. When unified_shared_area is 1, then the error applies to the common area for all MAC ports. #define BMB_REG_INT_STS_0_MAC0_FC_CNT_ERROR_SHIFT 31 #define BMB_REG_INT_MASK_0 0x5400c4UL //Access:RW DataWidth:0x20 // Multi Field Register. #define BMB_REG_INT_MASK_0_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.ADDRESS_ERROR . @@ -57878,7 +61352,7 @@ #define BMB_REG_INT_STS_WR_0_WC3_PROTOCOL_ERROR_SHIFT 26 #define BMB_REG_INT_STS_WR_0_LL_BLK_ERROR (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks. #define BMB_REG_INT_STS_WR_0_LL_BLK_ERROR_SHIFT 28 - #define BMB_REG_INT_STS_WR_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. + #define BMB_REG_INT_STS_WR_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. When unified_shared_area is 1, then the error applies to the common area for all MAC ports. #define BMB_REG_INT_STS_WR_0_MAC0_FC_CNT_ERROR_SHIFT 31 #define BMB_REG_INT_STS_CLR_0 0x5400ccUL //Access:RC DataWidth:0x20 // Multi Field Register. #define BMB_REG_INT_STS_CLR_0_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. @@ -57911,7 +61385,7 @@ #define BMB_REG_INT_STS_CLR_0_WC3_PROTOCOL_ERROR_SHIFT 26 #define BMB_REG_INT_STS_CLR_0_LL_BLK_ERROR (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks. #define BMB_REG_INT_STS_CLR_0_LL_BLK_ERROR_SHIFT 28 - #define BMB_REG_INT_STS_CLR_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. + #define BMB_REG_INT_STS_CLR_0_MAC0_FC_CNT_ERROR (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments. When unified_shared_area is 1, then the error applies to the common area for all MAC ports. #define BMB_REG_INT_STS_CLR_0_MAC0_FC_CNT_ERROR_SHIFT 31 #define BMB_REG_INT_STS_1 0x5400d8UL //Access:R DataWidth:0x20 // Multi Field Register. #define BMB_REG_INT_STS_1_LL_ARB_CALC_ERROR (0x1<<1) // Calculations error in LL arbiter block. @@ -60520,8 +63994,8 @@ #define BMB_REG_FREE_LIST_SIZE_SIZE 4 #define BMB_REG_MAX_RELEASES 0x540840UL //Access:RW DataWidth:0x2 // Number of packet copies that should be released before whole packet is released::s/MAX_RLS_WDTH/10/g in Data Width::s/MAX_RLS_RST/512/g in Reset Value::s/MAX_RLS_REQ/required/g in Required::s/MAX_RLS_REQ/required/g in Software init. #define BMB_REG_STOP_ON_LEN_ERR 0x540844UL //Access:RW DataWidth:0x3 // There is bit for each PACKET read client. When bit is set then read client will not execute more requests till reset in a case of length error other way it will continue to work as usual.::s/STOP_LEN_ERR_RST/7/g in Reset Value::s/PKT_RC_NUM/5/g in Data Width. -#define BMB_REG_SHARED_HR_AREA 0x540848UL //Access:RW DataWidth:0xb // The total number available blocks for each MAC port that includes shared and headroom areas. This register should be equal to total_mac_size - SUM(tc_guarantied) Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance. -#define BMB_REG_TOTAL_MAC_SIZE 0x54084cUL //Access:RW DataWidth:0xb // The total number available blocks for each MAC port that includes guaranteed and shared and headroom areas. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance. +#define BMB_REG_SHARED_HR_AREA 0x540848UL //Access:RW DataWidth:0xb // The total number available blocks for each MAC port that includes shared and headroom areas. This register should be equal to total_mac_size - SUM(tc_guarantied) Reset value is right for 128B block size only. It should be twice smaller for 256B block size. When unified_shared_area is 1, then the value applies to the common area for all MAC ports. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance. +#define BMB_REG_TOTAL_MAC_SIZE 0x54084cUL //Access:RW DataWidth:0xb // The total number available blocks for each MAC port that includes guaranteed and shared and headroom areas. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. When unified_shared_area is 1, then the threshold applies to the common area for all MAC ports. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance. #define BMB_REG_TC_GUARANTIED_0 0x540850UL //Access:RW DataWidth:0xb // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance. #define BMB_REG_TC_GUARANTIED_1 0x540854UL //Access:RW DataWidth:0xb // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance. #define BMB_REG_TC_GUARANTIED_2 0x540858UL //Access:RW DataWidth:0xb // The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance. @@ -60772,7 +64246,7 @@ #define BMB_REG_TC_OCCUPANCY_3 0x540dc0UL //Access:R DataWidth:0xb // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance. #define BMB_REG_TC_OCCUPANCY_4 0x540dc4UL //Access:R DataWidth:0xb // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance. #define BMB_REG_TC_OCCUPANCY_5 0x540dc8UL //Access:R DataWidth:0xb // Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance. -#define BMB_REG_AVAILABLE_MAC_SIZE_0 0x540df4UL //Access:R DataWidth:0xb // Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance. +#define BMB_REG_AVAILABLE_MAC_SIZE_0 0x540df4UL //Access:R DataWidth:0xb // Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas. When unified_shared_area is 1, then the value applies to the common area for all MAC ports, and only the first index of this field is valid. ::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance. #define BMB_REG_TC_PAUSE_0 0x540e0cUL //Access:R DataWidth:0x6 // Debug register. Output pause signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance. #define BMB_REG_TC_FULL_0 0x540e24UL //Access:R DataWidth:0x6 // Debug register. Output full signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance. #define BMB_REG_BIG_RAM_DATA 0x540f00UL //Access:WB DataWidth:0x80 // Debug register. Data to BIG RAM memory. Write to 32 MSB bits of this register will generate write to BIG RAM according to address that is written in big_ram_address register. Read from 32 LSB bits of this register will generate read from BIG RAM according to address written in big_ram_address register. @@ -60809,6 +64283,7 @@ #define BMB_REG_LINK_LIST_SIZE 1152 #define BMB_REG_WC_LL_HIGH_PRI_E5 0x544000UL //Access:RW DataWidth:0xa // This is a bitmap per WC which is 1 for WC with high priority and 0 o/w. #define BMB_REG_BR_FIX_HIGH_PRI_COLLISION_E5 0x544004UL //Access:RW DataWidth:0x1 // This is a bitmap per WC which is 1 for WC with high priority and 0 o/w. +#define BMB_REG_NCSI_IF_SEL_E5 0x544008UL //Access:RW DataWidth:0x1 // When this bit is enabled, then BMC is connected and BMB WC9/RC2 is connected to NCSI. When this bit is cleared, then MCP second IF is connected to BMB WC9/RC2. #define PTU_REG_ATC_INIT_ARRAY 0x560000UL //Access:RW DataWidth:0x1 // Initiate the ATC array - reset all the valid bits. #define PTU_REG_ATC_INIT_DONE 0x560004UL //Access:R DataWidth:0x1 // ATC initalization done. #define PTU_REG_LOG_TRANSPEND_REUSE_MISS_TID 0x560040UL //Access:RC DataWidth:0x20 // Logging register for reuse miss on transpend entry [31:0] - TID of the problematic request @@ -61539,9 +65014,7 @@ #define PTLD_REG_MEM_ECC_EVENTS_E5 0x5a021cUL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. #define PTLD_REG_DESC_QUEUE_Q0_E5 0x5a0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access. #define PTLD_REG_DESC_QUEUE_Q0_SIZE 150 -#define PTLD_REG_DESC_QUEUE_Q1_E5 0x5a0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access. -#define PTLD_REG_DESC_QUEUE_Q1_SIZE 150 -#define PTLD_REG_L2MA_AGGR_CONFIG1_E5 0x5a0c00UL //Access:RW DataWidth:0x14 // Multi Field Register. +#define PTLD_REG_L2MA_AGGR_CONFIG1_E5 0x5a0800UL //Access:RW DataWidth:0x14 // Multi Field Register. #define PTLD_REG_L2MA_AGGR_CONFIG1_L2MA_EN_E5 (0x1<<0) // Enables L2 message aggregation #define PTLD_REG_L2MA_AGGR_CONFIG1_L2MA_EN_E5_SHIFT 0 #define PTLD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5 (0x1<<1) // indicates not to perform the aggregation logic if there is no L2MA command in the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this configuration is reset, messages without L2MA command are treated like messages with L2MA command where EnL2MA flag in the command is reset (i.e. they break existing aggregation). @@ -61554,7 +65027,7 @@ #define PTLD_REG_L2MA_AGGR_CONFIG1_MIN_QUEUE_OCC_E5_SHIFT 4 #define PTLD_REG_L2MA_AGGR_CONFIG1_MAX_L2MA_DIFF_E5 (0xff<<12) // the maximal difference between the serial number of the parent message and the serial number of its child message #define PTLD_REG_L2MA_AGGR_CONFIG1_MAX_L2MA_DIFF_E5_SHIFT 12 -#define PTLD_REG_L2MA_AGGR_CONFIG2_E5 0x5a0c04UL //Access:RW DataWidth:0x18 // Multi Field Register. +#define PTLD_REG_L2MA_AGGR_CONFIG2_E5 0x5a0804UL //Access:RW DataWidth:0x18 // Multi Field Register. #define PTLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_0_E5 (0x3f<<0) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams) #define PTLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_0_E5_SHIFT 0 #define PTLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_1_E5 (0x3f<<6) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams) @@ -61563,8 +65036,8 @@ #define PTLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_2_E5_SHIFT 12 #define PTLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_3_E5 (0x3f<<18) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams) #define PTLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_3_E5_SHIFT 18 -#define PTLD_REG_L2MA_MAX_NUMBER_IN_QUEUE_E5 0x5a0c08UL //Access:RW DataWidth:0x10 // Limit the number of ‘packets’ in the Loader according to the number of parents + childs messages. -#define PTLD_REG_L2MA_SAME_OFFSET_SET_0_E5 0x5a0c0cUL //Access:RW DataWidth:0x20 // Multi Field Register. +#define PTLD_REG_L2MA_MAX_NUMBER_IN_QUEUE_E5 0x5a0808UL //Access:RW DataWidth:0x10 // Limit the number of ‘packets’ in the Loader according to the number of parents + childs messages. +#define PTLD_REG_L2MA_SAME_OFFSET_SET_0_E5 0x5a080cUL //Access:RW DataWidth:0x20 // Multi Field Register. #define PTLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_00_E5 (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0. #define PTLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_00_E5_SHIFT 0 #define PTLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5 (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0. @@ -61573,7 +65046,7 @@ #define PTLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_02_E5_SHIFT 16 #define PTLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_03_E5 (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0. #define PTLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_03_E5_SHIFT 24 -#define PTLD_REG_L2MA_SAME_OFFSET_SET_1_E5 0x5a0c10UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define PTLD_REG_L2MA_SAME_OFFSET_SET_1_E5 0x5a0810UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PTLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_10_E5 (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1. #define PTLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_10_E5_SHIFT 0 #define PTLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5 (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1. @@ -61582,7 +65055,7 @@ #define PTLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_12_E5_SHIFT 16 #define PTLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_13_E5 (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1. #define PTLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_13_E5_SHIFT 24 -#define PTLD_REG_L2MA_SAME_OFFSET_SET_2_E5 0x5a0c14UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define PTLD_REG_L2MA_SAME_OFFSET_SET_2_E5 0x5a0814UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PTLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_20_E5 (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2. #define PTLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_20_E5_SHIFT 0 #define PTLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5 (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2. @@ -61591,7 +65064,7 @@ #define PTLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_22_E5_SHIFT 16 #define PTLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_23_E5 (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2. #define PTLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_23_E5_SHIFT 24 -#define PTLD_REG_L2MA_SAME_OFFSET_SET_3_E5 0x5a0c18UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define PTLD_REG_L2MA_SAME_OFFSET_SET_3_E5 0x5a0818UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PTLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_30_E5 (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3. #define PTLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_30_E5_SHIFT 0 #define PTLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5 (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3. @@ -61600,7 +65073,7 @@ #define PTLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_32_E5_SHIFT 16 #define PTLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_33_E5 (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3. #define PTLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_33_E5_SHIFT 24 -#define PTLD_REG_L2MA_SAME_LEN_SET_0_1_E5 0x5a0c1cUL //Access:RW DataWidth:0x20 // Multi Field Register. +#define PTLD_REG_L2MA_SAME_LEN_SET_0_1_E5 0x5a081cUL //Access:RW DataWidth:0x20 // Multi Field Register. #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_00_E5 (0xf<<0) // length in 32b units from the same 00 . #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_00_E5_SHIFT 0 #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_01_E5 (0xf<<4) // length in 32b units from the same 01 . @@ -61617,7 +65090,7 @@ #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_12_E5_SHIFT 24 #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_13_E5 (0xf<<28) // length in 32b units from the same 13 . #define PTLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_13_E5_SHIFT 28 -#define PTLD_REG_L2MA_SAME_LEN_SET_2_3_E5 0x5a0c20UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define PTLD_REG_L2MA_SAME_LEN_SET_2_3_E5 0x5a0820UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_20_E5 (0xf<<0) // length in 32b units from the same 20 . #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_20_E5_SHIFT 0 #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_21_E5 (0xf<<4) // length in 32b units from the same 21 . @@ -61634,39 +65107,39 @@ #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_32_E5_SHIFT 24 #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_33_E5 (0xf<<28) // length in 32b units from the same 33 . #define PTLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_33_E5_SHIFT 28 -#define PTLD_REG_L2MA_SAME_MASK_BITS_31_0_SET_0_E5 0x5a0c24UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_63_32_SET_0_E5 0x5a0c28UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_95_64_SET_0_E5 0x5a0c2cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_127_96_SET_0_E5 0x5a0c30UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_159_128_SET_0_E5 0x5a0c34UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_191_160_SET_0_E5 0x5a0c38UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_223_192_SET_0_E5 0x5a0c3cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_255_224_SET_0_E5 0x5a0c40UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_31_0_SET_1_E5 0x5a0c44UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_63_32_SET_1_E5 0x5a0c48UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_95_64_SET_1_E5 0x5a0c4cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_127_96_SET_1_E5 0x5a0c50UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_159_128_SET_1_E5 0x5a0c54UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_191_160_SET_1_E5 0x5a0c58UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_223_192_SET_1_E5 0x5a0c5cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_255_224_SET_1_E5 0x5a0c60UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_31_0_SET_2_E5 0x5a0c64UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_63_32_SET_2_E5 0x5a0c68UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_95_64_SET_2_E5 0x5a0c6cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_127_96_SET_2_E5 0x5a0c70UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_159_128_SET_2_E5 0x5a0c74UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_191_160_SET_2_E5 0x5a0c78UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_223_192_SET_2_E5 0x5a0c7cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_255_224_SET_2_E5 0x5a0c80UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_31_0_SET_3_E5 0x5a0c84UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_63_32_SET_3_E5 0x5a0c88UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_95_64_SET_3_E5 0x5a0c8cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_127_96_SET_3_E5 0x5a0c90UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_159_128_SET_3_E5 0x5a0c94UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_191_160_SET_3_E5 0x5a0c98UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_223_192_SET_3_E5 0x5a0c9cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . -#define PTLD_REG_L2MA_SAME_MASK_BITS_255_224_SET_3_E5 0x5a0ca0UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . -#define PTLD_REG_L2MA_DUP_OFFSET_SET_0_E5 0x5a0ca4UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define PTLD_REG_L2MA_SAME_MASK_BITS_31_0_SET_0_E5 0x5a0824UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_63_32_SET_0_E5 0x5a0828UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_95_64_SET_0_E5 0x5a082cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_127_96_SET_0_E5 0x5a0830UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_159_128_SET_0_E5 0x5a0834UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_191_160_SET_0_E5 0x5a0838UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_223_192_SET_0_E5 0x5a083cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_255_224_SET_0_E5 0x5a0840UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_31_0_SET_1_E5 0x5a0844UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_63_32_SET_1_E5 0x5a0848UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_95_64_SET_1_E5 0x5a084cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_127_96_SET_1_E5 0x5a0850UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_159_128_SET_1_E5 0x5a0854UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_191_160_SET_1_E5 0x5a0858UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_223_192_SET_1_E5 0x5a085cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_255_224_SET_1_E5 0x5a0860UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_31_0_SET_2_E5 0x5a0864UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_63_32_SET_2_E5 0x5a0868UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_95_64_SET_2_E5 0x5a086cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_127_96_SET_2_E5 0x5a0870UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_159_128_SET_2_E5 0x5a0874UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_191_160_SET_2_E5 0x5a0878UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_223_192_SET_2_E5 0x5a087cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_255_224_SET_2_E5 0x5a0880UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_31_0_SET_3_E5 0x5a0884UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_63_32_SET_3_E5 0x5a0888UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_95_64_SET_3_E5 0x5a088cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_127_96_SET_3_E5 0x5a0890UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_159_128_SET_3_E5 0x5a0894UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_191_160_SET_3_E5 0x5a0898UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_223_192_SET_3_E5 0x5a089cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . +#define PTLD_REG_L2MA_SAME_MASK_BITS_255_224_SET_3_E5 0x5a08a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . +#define PTLD_REG_L2MA_DUP_OFFSET_SET_0_E5 0x5a08a4UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PTLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_00_E5 (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0. #define PTLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_00_E5_SHIFT 0 #define PTLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5 (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0. @@ -61675,7 +65148,7 @@ #define PTLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_02_E5_SHIFT 16 #define PTLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_03_E5 (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0. #define PTLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_03_E5_SHIFT 24 -#define PTLD_REG_L2MA_DUP_OFFSET_SET_1_E5 0x5a0ca8UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define PTLD_REG_L2MA_DUP_OFFSET_SET_1_E5 0x5a08a8UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PTLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_10_E5 (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1. #define PTLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_10_E5_SHIFT 0 #define PTLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5 (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1. @@ -61684,7 +65157,7 @@ #define PTLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_12_E5_SHIFT 16 #define PTLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_13_E5 (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1. #define PTLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_13_E5_SHIFT 24 -#define PTLD_REG_L2MA_DUP_OFFSET_SET_2_E5 0x5a0cacUL //Access:RW DataWidth:0x20 // Multi Field Register. +#define PTLD_REG_L2MA_DUP_OFFSET_SET_2_E5 0x5a08acUL //Access:RW DataWidth:0x20 // Multi Field Register. #define PTLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_20_E5 (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2. #define PTLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_20_E5_SHIFT 0 #define PTLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5 (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2. @@ -61693,7 +65166,7 @@ #define PTLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_22_E5_SHIFT 16 #define PTLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_23_E5 (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2. #define PTLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_23_E5_SHIFT 24 -#define PTLD_REG_L2MA_DUP_OFFSET_SET_3_E5 0x5a0cb0UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define PTLD_REG_L2MA_DUP_OFFSET_SET_3_E5 0x5a08b0UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PTLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_30_E5 (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3. #define PTLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_30_E5_SHIFT 0 #define PTLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5 (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3. @@ -61702,7 +65175,7 @@ #define PTLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_32_E5_SHIFT 16 #define PTLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_33_E5 (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3. #define PTLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_33_E5_SHIFT 24 -#define PTLD_REG_L2MA_DUP_LEN_SET_0_E5 0x5a0cb4UL //Access:RW DataWidth:0x18 // Multi Field Register. +#define PTLD_REG_L2MA_DUP_LEN_SET_0_E5 0x5a08b4UL //Access:RW DataWidth:0x18 // Multi Field Register. #define PTLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_00_E5 (0x3f<<0) // length in 32b units from the dup 00 . #define PTLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_00_E5_SHIFT 0 #define PTLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_01_E5 (0x3f<<6) // length in 32b units from the dup 01 . @@ -61711,7 +65184,7 @@ #define PTLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_02_E5_SHIFT 12 #define PTLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_03_E5 (0x3f<<18) // length in 32b units from the dup 03 . #define PTLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_03_E5_SHIFT 18 -#define PTLD_REG_L2MA_DUP_LEN_SET_1_E5 0x5a0cb8UL //Access:RW DataWidth:0x18 // Multi Field Register. +#define PTLD_REG_L2MA_DUP_LEN_SET_1_E5 0x5a08b8UL //Access:RW DataWidth:0x18 // Multi Field Register. #define PTLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_10_E5 (0x3f<<0) // length in 32b units from the dup 10 . #define PTLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_10_E5_SHIFT 0 #define PTLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_11_E5 (0x3f<<6) // length in 32b units from the dup 11 . @@ -61720,7 +65193,7 @@ #define PTLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_12_E5_SHIFT 12 #define PTLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_13_E5 (0x3f<<18) // length in 32b units from the dup 13 . #define PTLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_13_E5_SHIFT 18 -#define PTLD_REG_L2MA_DUP_LEN_SET_2_E5 0x5a0cbcUL //Access:RW DataWidth:0x18 // Multi Field Register. +#define PTLD_REG_L2MA_DUP_LEN_SET_2_E5 0x5a08bcUL //Access:RW DataWidth:0x18 // Multi Field Register. #define PTLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_20_E5 (0x3f<<0) // length in 32b units from the dup 20 . #define PTLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_20_E5_SHIFT 0 #define PTLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_21_E5 (0x3f<<6) // length in 32b units from the dup 21 . @@ -61729,7 +65202,7 @@ #define PTLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_22_E5_SHIFT 12 #define PTLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_23_E5 (0x3f<<18) // length in 32b units from the dup 23 . #define PTLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_23_E5_SHIFT 18 -#define PTLD_REG_L2MA_DUP_LEN_SET_3_E5 0x5a0cc0UL //Access:RW DataWidth:0x18 // Multi Field Register. +#define PTLD_REG_L2MA_DUP_LEN_SET_3_E5 0x5a08c0UL //Access:RW DataWidth:0x18 // Multi Field Register. #define PTLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_30_E5 (0x3f<<0) // length in 32b units from the dup 30 . #define PTLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_30_E5_SHIFT 0 #define PTLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_31_E5 (0x3f<<6) // length in 32b units from the dup 31 . @@ -61738,7 +65211,7 @@ #define PTLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_32_E5_SHIFT 12 #define PTLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_33_E5 (0x3f<<18) // length in 32b units from the dup 33 . #define PTLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_33_E5_SHIFT 18 -#define PTLD_REG_L2MA_FLOW_ID_E5 0x5a0cc4UL //Access:RW DataWidth:0x18 // Multi Field Register. +#define PTLD_REG_L2MA_FLOW_ID_E5 0x5a08c4UL //Access:RW DataWidth:0x18 // Multi Field Register. #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0_E5 (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0. #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0_E5_SHIFT 0 #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5 (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1. @@ -61755,7 +65228,7 @@ #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_2_E5_SHIFT 14 #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_3_E5 (0x1f<<19) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 3 . #define PTLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_3_E5_SHIFT 19 -#define PTLD_REG_L2MA_SN_OFFSET_E5 0x5a0cc8UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define PTLD_REG_L2MA_SN_OFFSET_E5 0x5a08c8UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_0_E5 (0xff<<0) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 0. #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_0_E5_SHIFT 0 #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5 (0xff<<8) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1. @@ -61764,7 +65237,7 @@ #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_2_E5_SHIFT 16 #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_3_E5 (0xff<<24) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3. #define PTLD_REG_L2MA_SN_OFFSET_SN_OFFSET_3_E5_SHIFT 24 -#define PTLD_REG_L2MA_MAX_L2MA_CHILD_E5 0x5a0cccUL //Access:RW DataWidth:0x10 // Multi Field Register. +#define PTLD_REG_L2MA_MAX_L2MA_CHILD_E5 0x5a08ccUL //Access:RW DataWidth:0x10 // Multi Field Register. #define PTLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_0_E5 (0xf<<0) // the maximal number of children in a specific aggregation. for set 0. #define PTLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_0_E5_SHIFT 0 #define PTLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_1_E5 (0xf<<4) // the maximal number of children in a specific aggregation. for set 1. @@ -61773,7 +65246,7 @@ #define PTLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5_SHIFT 8 #define PTLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_3_E5 (0xf<<12) // the maximal number of children in a specific aggregation. for set 3. #define PTLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_3_E5_SHIFT 12 -#define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_E5 0x5a0cd0UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_E5 0x5a08d0UL //Access:RW DataWidth:0x20 // Multi Field Register. #define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_0_E5 (0xff<<0) // The value by which to increment the event-ID in case of successful aggregation. for set 0. #define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_0_E5_SHIFT 0 #define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5 (0xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for set 1. @@ -61782,7 +65255,7 @@ #define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_2_E5_SHIFT 16 #define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_3_E5 (0xff<<24) // The value by which to increment the event-ID in case of successful aggregation. for set 3. #define PTLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_3_E5_SHIFT 24 -#define PTLD_REG_LD_MAX_MSG_SIZE_E5 0x5a0cd4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words +#define PTLD_REG_LD_MAX_MSG_SIZE_E5 0x5a08d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words #define PTLD_REG_DBG_SELECT_E5 0x5a1600UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output #define PTLD_REG_DBG_DWORD_ENABLE_E5 0x5a1604UL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line) in the selected line (before shift).for selecting a line to output #define PTLD_REG_DBG_SHIFT_E5 0x5a1608UL //Access:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) right shifting of the selected line (after the masking). @@ -61893,9 +65366,7 @@ #define YPLD_REG_MEM_ECC_EVENTS_E5 0x5c021cUL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. #define YPLD_REG_DESC_QUEUE_Q0_E5 0x5c0400UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue0 - Debug access. #define YPLD_REG_DESC_QUEUE_Q0_SIZE 150 -#define YPLD_REG_DESC_QUEUE_Q1_E5 0x5c0800UL //Access:WB DataWidth:0x23 // Descriptor FIFO queue1 - Debug access. -#define YPLD_REG_DESC_QUEUE_Q1_SIZE 150 -#define YPLD_REG_L2MA_AGGR_CONFIG1_E5 0x5c0c00UL //Access:RW DataWidth:0x14 // Multi Field Register. +#define YPLD_REG_L2MA_AGGR_CONFIG1_E5 0x5c0800UL //Access:RW DataWidth:0x14 // Multi Field Register. #define YPLD_REG_L2MA_AGGR_CONFIG1_L2MA_EN_E5 (0x1<<0) // Enables L2 message aggregation #define YPLD_REG_L2MA_AGGR_CONFIG1_L2MA_EN_E5_SHIFT 0 #define YPLD_REG_L2MA_AGGR_CONFIG1_IGNORE_CM_AGG_MSG_E5 (0x1<<1) // indicates not to perform the aggregation logic if there is no L2MA command in the message (there is no L2MA command if DstStormFlg is reset OR ErrFlg is set). If this configuration is reset, messages without L2MA command are treated like messages with L2MA command where EnL2MA flag in the command is reset (i.e. they break existing aggregation). @@ -61908,7 +65379,7 @@ #define YPLD_REG_L2MA_AGGR_CONFIG1_MIN_QUEUE_OCC_E5_SHIFT 4 #define YPLD_REG_L2MA_AGGR_CONFIG1_MAX_L2MA_DIFF_E5 (0xff<<12) // the maximal difference between the serial number of the parent message and the serial number of its child message #define YPLD_REG_L2MA_AGGR_CONFIG1_MAX_L2MA_DIFF_E5_SHIFT 12 -#define YPLD_REG_L2MA_AGGR_CONFIG2_E5 0x5c0c04UL //Access:RW DataWidth:0x18 // Multi Field Register. +#define YPLD_REG_L2MA_AGGR_CONFIG2_E5 0x5c0804UL //Access:RW DataWidth:0x18 // Multi Field Register. #define YPLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_0_E5 (0x3f<<0) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams) #define YPLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_0_E5_SHIFT 0 #define YPLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_1_E5 (0x3f<<6) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams) @@ -61917,8 +65388,8 @@ #define YPLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_2_E5_SHIFT 12 #define YPLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_3_E5 (0x3f<<18) // the size of the message associated with each child in number of 128b units for set 0(should be in accordance to DupParams) #define YPLD_REG_L2MA_AGGR_CONFIG2_CHILD_MSG_SIZE_3_E5_SHIFT 18 -#define YPLD_REG_L2MA_MAX_NUMBER_IN_QUEUE_E5 0x5c0c08UL //Access:RW DataWidth:0x10 // Limit the number of ‘packets’ in the Loader according to the number of parents + childs messages. -#define YPLD_REG_L2MA_SAME_OFFSET_SET_0_E5 0x5c0c0cUL //Access:RW DataWidth:0x20 // Multi Field Register. +#define YPLD_REG_L2MA_MAX_NUMBER_IN_QUEUE_E5 0x5c0808UL //Access:RW DataWidth:0x10 // Limit the number of ‘packets’ in the Loader according to the number of parents + childs messages. +#define YPLD_REG_L2MA_SAME_OFFSET_SET_0_E5 0x5c080cUL //Access:RW DataWidth:0x20 // Multi Field Register. #define YPLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_00_E5 (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 0. #define YPLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_00_E5_SHIFT 0 #define YPLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_01_E5 (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 0. @@ -61927,7 +65398,7 @@ #define YPLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_02_E5_SHIFT 16 #define YPLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_03_E5 (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 0. #define YPLD_REG_L2MA_SAME_OFFSET_SET_0_OFFSET_03_E5_SHIFT 24 -#define YPLD_REG_L2MA_SAME_OFFSET_SET_1_E5 0x5c0c10UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define YPLD_REG_L2MA_SAME_OFFSET_SET_1_E5 0x5c0810UL //Access:RW DataWidth:0x20 // Multi Field Register. #define YPLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_10_E5 (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 1. #define YPLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_10_E5_SHIFT 0 #define YPLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_11_E5 (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 1. @@ -61936,7 +65407,7 @@ #define YPLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_12_E5_SHIFT 16 #define YPLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_13_E5 (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 1. #define YPLD_REG_L2MA_SAME_OFFSET_SET_1_OFFSET_13_E5_SHIFT 24 -#define YPLD_REG_L2MA_SAME_OFFSET_SET_2_E5 0x5c0c14UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define YPLD_REG_L2MA_SAME_OFFSET_SET_2_E5 0x5c0814UL //Access:RW DataWidth:0x20 // Multi Field Register. #define YPLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_20_E5 (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 2. #define YPLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_20_E5_SHIFT 0 #define YPLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_21_E5 (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 2. @@ -61945,7 +65416,7 @@ #define YPLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_22_E5_SHIFT 16 #define YPLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_23_E5 (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 2. #define YPLD_REG_L2MA_SAME_OFFSET_SET_2_OFFSET_23_E5_SHIFT 24 -#define YPLD_REG_L2MA_SAME_OFFSET_SET_3_E5 0x5c0c18UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define YPLD_REG_L2MA_SAME_OFFSET_SET_3_E5 0x5c0818UL //Access:RW DataWidth:0x20 // Multi Field Register. #define YPLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_30_E5 (0xff<<0) // Offset in 32b units from the beginning of the message to same parameter 0 of configuration-set 3. #define YPLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_30_E5_SHIFT 0 #define YPLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_31_E5 (0xff<<8) // Offset in 32b units from the beginning of the message to same parameter 1 of configuration-set 3. @@ -61954,7 +65425,7 @@ #define YPLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_32_E5_SHIFT 16 #define YPLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_33_E5 (0xff<<24) // Offset in 32b units from the beginning of the message to same parameter 3 of configuration-set 3. #define YPLD_REG_L2MA_SAME_OFFSET_SET_3_OFFSET_33_E5_SHIFT 24 -#define YPLD_REG_L2MA_SAME_LEN_SET_0_1_E5 0x5c0c1cUL //Access:RW DataWidth:0x20 // Multi Field Register. +#define YPLD_REG_L2MA_SAME_LEN_SET_0_1_E5 0x5c081cUL //Access:RW DataWidth:0x20 // Multi Field Register. #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_00_E5 (0xf<<0) // length in 32b units from the same 00 . #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_00_E5_SHIFT 0 #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_01_E5 (0xf<<4) // length in 32b units from the same 01 . @@ -61971,7 +65442,7 @@ #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_12_E5_SHIFT 24 #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_13_E5 (0xf<<28) // length in 32b units from the same 13 . #define YPLD_REG_L2MA_SAME_LEN_SET_0_1_LEN_13_E5_SHIFT 28 -#define YPLD_REG_L2MA_SAME_LEN_SET_2_3_E5 0x5c0c20UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define YPLD_REG_L2MA_SAME_LEN_SET_2_3_E5 0x5c0820UL //Access:RW DataWidth:0x20 // Multi Field Register. #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_20_E5 (0xf<<0) // length in 32b units from the same 20 . #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_20_E5_SHIFT 0 #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_21_E5 (0xf<<4) // length in 32b units from the same 21 . @@ -61988,39 +65459,39 @@ #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_32_E5_SHIFT 24 #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_33_E5 (0xf<<28) // length in 32b units from the same 33 . #define YPLD_REG_L2MA_SAME_LEN_SET_2_3_LEN_33_E5_SHIFT 28 -#define YPLD_REG_L2MA_SAME_MASK_BITS_31_0_SET_0_E5 0x5c0c24UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_63_32_SET_0_E5 0x5c0c28UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_95_64_SET_0_E5 0x5c0c2cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_127_96_SET_0_E5 0x5c0c30UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_159_128_SET_0_E5 0x5c0c34UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_191_160_SET_0_E5 0x5c0c38UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_223_192_SET_0_E5 0x5c0c3cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_255_224_SET_0_E5 0x5c0c40UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_31_0_SET_1_E5 0x5c0c44UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_63_32_SET_1_E5 0x5c0c48UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_95_64_SET_1_E5 0x5c0c4cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_127_96_SET_1_E5 0x5c0c50UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_159_128_SET_1_E5 0x5c0c54UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_191_160_SET_1_E5 0x5c0c58UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_223_192_SET_1_E5 0x5c0c5cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_255_224_SET_1_E5 0x5c0c60UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_31_0_SET_2_E5 0x5c0c64UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_63_32_SET_2_E5 0x5c0c68UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_95_64_SET_2_E5 0x5c0c6cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_127_96_SET_2_E5 0x5c0c70UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_159_128_SET_2_E5 0x5c0c74UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_191_160_SET_2_E5 0x5c0c78UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_223_192_SET_2_E5 0x5c0c7cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_255_224_SET_2_E5 0x5c0c80UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_31_0_SET_3_E5 0x5c0c84UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_63_32_SET_3_E5 0x5c0c88UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_95_64_SET_3_E5 0x5c0c8cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_127_96_SET_3_E5 0x5c0c90UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_159_128_SET_3_E5 0x5c0c94UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_191_160_SET_3_E5 0x5c0c98UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_223_192_SET_3_E5 0x5c0c9cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . -#define YPLD_REG_L2MA_SAME_MASK_BITS_255_224_SET_3_E5 0x5c0ca0UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . -#define YPLD_REG_L2MA_DUP_OFFSET_SET_0_E5 0x5c0ca4UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define YPLD_REG_L2MA_SAME_MASK_BITS_31_0_SET_0_E5 0x5c0824UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_63_32_SET_0_E5 0x5c0828UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_95_64_SET_0_E5 0x5c082cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_127_96_SET_0_E5 0x5c0830UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_159_128_SET_0_E5 0x5c0834UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_191_160_SET_0_E5 0x5c0838UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_223_192_SET_0_E5 0x5c083cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_255_224_SET_0_E5 0x5c0840UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 0 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_31_0_SET_1_E5 0x5c0844UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_63_32_SET_1_E5 0x5c0848UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_95_64_SET_1_E5 0x5c084cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_127_96_SET_1_E5 0x5c0850UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_159_128_SET_1_E5 0x5c0854UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_191_160_SET_1_E5 0x5c0858UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_223_192_SET_1_E5 0x5c085cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_255_224_SET_1_E5 0x5c0860UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 1 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_31_0_SET_2_E5 0x5c0864UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_63_32_SET_2_E5 0x5c0868UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_95_64_SET_2_E5 0x5c086cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_127_96_SET_2_E5 0x5c0870UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_159_128_SET_2_E5 0x5c0874UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_191_160_SET_2_E5 0x5c0878UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_223_192_SET_2_E5 0x5c087cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_255_224_SET_2_E5 0x5c0880UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 2 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_31_0_SET_3_E5 0x5c0884UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_63_32_SET_3_E5 0x5c0888UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_95_64_SET_3_E5 0x5c088cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_127_96_SET_3_E5 0x5c0890UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_159_128_SET_3_E5 0x5c0894UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_191_160_SET_3_E5 0x5c0898UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_223_192_SET_3_E5 0x5c089cUL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . +#define YPLD_REG_L2MA_SAME_MASK_BITS_255_224_SET_3_E5 0x5c08a0UL //Access:RW DataWidth:0x20 // bit-mask on the selected 32B same 3 parameters . +#define YPLD_REG_L2MA_DUP_OFFSET_SET_0_E5 0x5c08a4UL //Access:RW DataWidth:0x20 // Multi Field Register. #define YPLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_00_E5 (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 0. #define YPLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_00_E5_SHIFT 0 #define YPLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_01_E5 (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 0. @@ -62029,7 +65500,7 @@ #define YPLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_02_E5_SHIFT 16 #define YPLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_03_E5 (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 0. #define YPLD_REG_L2MA_DUP_OFFSET_SET_0_DUP_OFFSET_03_E5_SHIFT 24 -#define YPLD_REG_L2MA_DUP_OFFSET_SET_1_E5 0x5c0ca8UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define YPLD_REG_L2MA_DUP_OFFSET_SET_1_E5 0x5c08a8UL //Access:RW DataWidth:0x20 // Multi Field Register. #define YPLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_10_E5 (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 1. #define YPLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_10_E5_SHIFT 0 #define YPLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_11_E5 (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 1. @@ -62038,7 +65509,7 @@ #define YPLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_12_E5_SHIFT 16 #define YPLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_13_E5 (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 1. #define YPLD_REG_L2MA_DUP_OFFSET_SET_1_DUP_OFFSET_13_E5_SHIFT 24 -#define YPLD_REG_L2MA_DUP_OFFSET_SET_2_E5 0x5c0cacUL //Access:RW DataWidth:0x20 // Multi Field Register. +#define YPLD_REG_L2MA_DUP_OFFSET_SET_2_E5 0x5c08acUL //Access:RW DataWidth:0x20 // Multi Field Register. #define YPLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_20_E5 (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 2. #define YPLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_20_E5_SHIFT 0 #define YPLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_21_E5 (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 2. @@ -62047,7 +65518,7 @@ #define YPLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_22_E5_SHIFT 16 #define YPLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_23_E5 (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 2. #define YPLD_REG_L2MA_DUP_OFFSET_SET_2_DUP_OFFSET_23_E5_SHIFT 24 -#define YPLD_REG_L2MA_DUP_OFFSET_SET_3_E5 0x5c0cb0UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define YPLD_REG_L2MA_DUP_OFFSET_SET_3_E5 0x5c08b0UL //Access:RW DataWidth:0x20 // Multi Field Register. #define YPLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_30_E5 (0xff<<0) // Offset in 32b units from the beginning of the message to dup parameter 0 of configuration-set 3. #define YPLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_30_E5_SHIFT 0 #define YPLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_31_E5 (0xff<<8) // Offset in 32b units from the beginning of the message to dup parameter 1 of configuration-set 3. @@ -62056,7 +65527,7 @@ #define YPLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_32_E5_SHIFT 16 #define YPLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_33_E5 (0xff<<24) // Offset in 32b units from the beginning of the message to dup parameter 3 of configuration-set 3. #define YPLD_REG_L2MA_DUP_OFFSET_SET_3_DUP_OFFSET_33_E5_SHIFT 24 -#define YPLD_REG_L2MA_DUP_LEN_SET_0_E5 0x5c0cb4UL //Access:RW DataWidth:0x18 // Multi Field Register. +#define YPLD_REG_L2MA_DUP_LEN_SET_0_E5 0x5c08b4UL //Access:RW DataWidth:0x18 // Multi Field Register. #define YPLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_00_E5 (0x3f<<0) // length in 32b units from the dup 00 . #define YPLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_00_E5_SHIFT 0 #define YPLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_01_E5 (0x3f<<6) // length in 32b units from the dup 01 . @@ -62065,7 +65536,7 @@ #define YPLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_02_E5_SHIFT 12 #define YPLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_03_E5 (0x3f<<18) // length in 32b units from the dup 03 . #define YPLD_REG_L2MA_DUP_LEN_SET_0_DUP_LEN_03_E5_SHIFT 18 -#define YPLD_REG_L2MA_DUP_LEN_SET_1_E5 0x5c0cb8UL //Access:RW DataWidth:0x18 // Multi Field Register. +#define YPLD_REG_L2MA_DUP_LEN_SET_1_E5 0x5c08b8UL //Access:RW DataWidth:0x18 // Multi Field Register. #define YPLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_10_E5 (0x3f<<0) // length in 32b units from the dup 10 . #define YPLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_10_E5_SHIFT 0 #define YPLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_11_E5 (0x3f<<6) // length in 32b units from the dup 11 . @@ -62074,7 +65545,7 @@ #define YPLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_12_E5_SHIFT 12 #define YPLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_13_E5 (0x3f<<18) // length in 32b units from the dup 13 . #define YPLD_REG_L2MA_DUP_LEN_SET_1_DUP_LEN_13_E5_SHIFT 18 -#define YPLD_REG_L2MA_DUP_LEN_SET_2_E5 0x5c0cbcUL //Access:RW DataWidth:0x18 // Multi Field Register. +#define YPLD_REG_L2MA_DUP_LEN_SET_2_E5 0x5c08bcUL //Access:RW DataWidth:0x18 // Multi Field Register. #define YPLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_20_E5 (0x3f<<0) // length in 32b units from the dup 20 . #define YPLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_20_E5_SHIFT 0 #define YPLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_21_E5 (0x3f<<6) // length in 32b units from the dup 21 . @@ -62083,7 +65554,7 @@ #define YPLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_22_E5_SHIFT 12 #define YPLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_23_E5 (0x3f<<18) // length in 32b units from the dup 23 . #define YPLD_REG_L2MA_DUP_LEN_SET_2_DUP_LEN_23_E5_SHIFT 18 -#define YPLD_REG_L2MA_DUP_LEN_SET_3_E5 0x5c0cc0UL //Access:RW DataWidth:0x18 // Multi Field Register. +#define YPLD_REG_L2MA_DUP_LEN_SET_3_E5 0x5c08c0UL //Access:RW DataWidth:0x18 // Multi Field Register. #define YPLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_30_E5 (0x3f<<0) // length in 32b units from the dup 30 . #define YPLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_30_E5_SHIFT 0 #define YPLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_31_E5 (0x3f<<6) // length in 32b units from the dup 31 . @@ -62092,7 +65563,7 @@ #define YPLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_32_E5_SHIFT 12 #define YPLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_33_E5 (0x3f<<18) // length in 32b units from the dup 33 . #define YPLD_REG_L2MA_DUP_LEN_SET_3_DUP_LEN_33_E5_SHIFT 18 -#define YPLD_REG_L2MA_FLOW_ID_E5 0x5c0cc4UL //Access:RW DataWidth:0x18 // Multi Field Register. +#define YPLD_REG_L2MA_FLOW_ID_E5 0x5c08c4UL //Access:RW DataWidth:0x18 // Multi Field Register. #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0_E5 (0x1<<0) // indication if to include the flow-ID in the stream-ID for set 0. #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_0_E5_SHIFT 0 #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_INCLUDE_1_E5 (0x1<<1) // indication if to include the flow-ID in the stream-ID for set 1. @@ -62109,7 +65580,7 @@ #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_2_E5_SHIFT 14 #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_3_E5 (0x1f<<19) // offset of the flow-ID, in 32b units, from the beginning of the message. Should be at most in the 3rd 256b cycle of the incoming message (i.e. max value is 23). This parameter is NA if FlowIdInclude is reset. For set 3 . #define YPLD_REG_L2MA_FLOW_ID_FLOW_ID_OFFSET_3_E5_SHIFT 19 -#define YPLD_REG_L2MA_SN_OFFSET_E5 0x5c0cc8UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define YPLD_REG_L2MA_SN_OFFSET_E5 0x5c08c8UL //Access:RW DataWidth:0x20 // Multi Field Register. #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_0_E5 (0xff<<0) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 0. #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_0_E5_SHIFT 0 #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_1_E5 (0xff<<8) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 1. @@ -62118,7 +65589,7 @@ #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_2_E5_SHIFT 16 #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_3_E5 (0xff<<24) // offset in 32b units from the beginning of the message in which to put (overwrite) the serial number. Sn Offset should point to an offset which is part of a duplicate parameter.for set 3. #define YPLD_REG_L2MA_SN_OFFSET_SN_OFFSET_3_E5_SHIFT 24 -#define YPLD_REG_L2MA_MAX_L2MA_CHILD_E5 0x5c0cccUL //Access:RW DataWidth:0x10 // Multi Field Register. +#define YPLD_REG_L2MA_MAX_L2MA_CHILD_E5 0x5c08ccUL //Access:RW DataWidth:0x10 // Multi Field Register. #define YPLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_0_E5 (0xf<<0) // the maximal number of children in a specific aggregation. for set 0. #define YPLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_0_E5_SHIFT 0 #define YPLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_1_E5 (0xf<<4) // the maximal number of children in a specific aggregation. for set 1. @@ -62127,7 +65598,7 @@ #define YPLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_2_E5_SHIFT 8 #define YPLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_3_E5 (0xf<<12) // the maximal number of children in a specific aggregation. for set 3. #define YPLD_REG_L2MA_MAX_L2MA_CHILD_MAX_L2MA_3_E5_SHIFT 12 -#define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_E5 0x5c0cd0UL //Access:RW DataWidth:0x20 // Multi Field Register. +#define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_E5 0x5c08d0UL //Access:RW DataWidth:0x20 // Multi Field Register. #define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_0_E5 (0xff<<0) // The value by which to increment the event-ID in case of successful aggregation. for set 0. #define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_0_E5_SHIFT 0 #define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_1_E5 (0xff<<8) // The value by which to increment the event-ID in case of successful aggregation. for set 1. @@ -62136,7 +65607,7 @@ #define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_2_E5_SHIFT 16 #define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_3_E5 (0xff<<24) // The value by which to increment the event-ID in case of successful aggregation. for set 3. #define YPLD_REG_L2MA_INC_L2MA_EVENT_ID_INC_EVENT_ID_3_E5_SHIFT 24 -#define YPLD_REG_LD_MAX_MSG_SIZE_E5 0x5c0cd4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words +#define YPLD_REG_LD_MAX_MSG_SIZE_E5 0x5c08d4UL //Access:RW DataWidth:0xc // maximum loader size in 256 bit words #define YPLD_REG_DBG_SELECT_E5 0x5c1600UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output #define YPLD_REG_DBG_DWORD_ENABLE_E5 0x5c1604UL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line) in the selected line (before shift).for selecting a line to output #define YPLD_REG_DBG_SHIFT_E5 0x5c1608UL //Access:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) right shifting of the selected line (after the masking). @@ -62598,375 +66069,788 @@ #define LED_REG_INT_STS_CLR_0_K2_E5 0x6b818cUL //Access:RC DataWidth:0x1 // Multi Field Register. #define LED_REG_INT_STS_CLR_0_ADDRESS_ERROR_K2_E5 (0x1<<0) // Signals an unknown address to the rf module. #define LED_REG_INT_STS_CLR_0_ADDRESS_ERROR_K2_E5_SHIFT 0 -#define NWS_REG_COMMON_CONTROL_K2_E5 0x700000UL //Access:RW DataWidth:0x1e // Multi Field Register. - #define NWS_REG_COMMON_CONTROL_REFCLK_INPUT_SEL_I_K2_E5 (0x3<<0) // 0x0 - Select reference clock from Bump 0x1 - Select inter-macro refrence clock from the left side 0x2 - Same as 0x0 0x3 - Select inter-macro refrence clock from the right side - #define NWS_REG_COMMON_CONTROL_REFCLK_INPUT_SEL_I_K2_E5_SHIFT 0 - #define NWS_REG_COMMON_CONTROL_REFCLK_LEFT_SEL_I_K2_E5 (0x3<<2) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro refrence clock from the right side 0x3 - Same as 0x2 - #define NWS_REG_COMMON_CONTROL_REFCLK_LEFT_SEL_I_K2_E5_SHIFT 2 - #define NWS_REG_COMMON_CONTROL_REFCLK_RIGHT_SEL_I_K2_E5 (0x3<<4) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro refrence clock from the left side 0x3 - Same as 0x2 - #define NWS_REG_COMMON_CONTROL_REFCLK_RIGHT_SEL_I_K2_E5_SHIFT 4 - #define NWS_REG_COMMON_CONTROL_STAT_LOS_SELECT_K2_E5 (0x3<<6) // Selects which stat_los signal is used for nws_nwm_sd_energy_detect. 0 - use ~lnX_stat_los_o 1 - use ~lnX_stat_los_deglitch_o (Default) 2 - use lnX_stat_rxvalid_o - #define NWS_REG_COMMON_CONTROL_STAT_LOS_SELECT_K2_E5_SHIFT 6 - #define NWS_REG_COMMON_CONTROL_CPU_RESET_K2_E5 (0x1<<10) // Controls cpu_reset_i reset signal into the SerDes. - #define NWS_REG_COMMON_CONTROL_CPU_RESET_K2_E5_SHIFT 10 - #define NWS_REG_COMMON_CONTROL_POR_N_K2_E5 (0x1<<11) // Controls por_n_i reset signal into the SerDes. This should be 0 (Reset value) while the SerDes program and data rams are being written, and the serdes is being configured. This holds the SerDes in Reset. Once the memory is configured, write 1 to this bit to allow the SerDes to begin normal Operation. - #define NWS_REG_COMMON_CONTROL_POR_N_K2_E5_SHIFT 11 - #define NWS_REG_COMMON_CONTROL_CM0_RST_N_K2_E5 (0x1<<12) // Controls cm0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the cmu0 in Reset. write 1 to this bit to allow the SerDes to begin normal Operation. - #define NWS_REG_COMMON_CONTROL_CM0_RST_N_K2_E5_SHIFT 12 - #define NWS_REG_COMMON_CONTROL_CM1_RST_N_K2_E5 (0x1<<13) // Controls cm1_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the cmu0 in Reset. write 1 to this bit to allow the SerDes to begin normal Operation. - #define NWS_REG_COMMON_CONTROL_CM1_RST_N_K2_E5_SHIFT 13 - #define NWS_REG_COMMON_CONTROL_LN0_RST_N_K2_E5 (0x1<<14) // Controls ln0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln0 in Reset. write 1 to begin normal Operation on ln0. - #define NWS_REG_COMMON_CONTROL_LN0_RST_N_K2_E5_SHIFT 14 - #define NWS_REG_COMMON_CONTROL_LN1_RST_N_K2_E5 (0x1<<15) // Controls ln1_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln1 in Reset. write 1 to begin normal Operation on ln1. - #define NWS_REG_COMMON_CONTROL_LN1_RST_N_K2_E5_SHIFT 15 - #define NWS_REG_COMMON_CONTROL_LN2_RST_N_K2_E5 (0x1<<16) // Controls ln0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln2 in Reset. write 1 to begin normal Operation on ln2. - #define NWS_REG_COMMON_CONTROL_LN2_RST_N_K2_E5_SHIFT 16 - #define NWS_REG_COMMON_CONTROL_LN3_RST_N_K2_E5 (0x1<<17) // Controls ln3_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln3 in Reset. write 1 to begin normal Operation on ln3. - #define NWS_REG_COMMON_CONTROL_LN3_RST_N_K2_E5_SHIFT 17 - #define NWS_REG_COMMON_CONTROL_CM0_PD_K2_E5 (0x3<<18) // CMU Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode) - #define NWS_REG_COMMON_CONTROL_CM0_PD_K2_E5_SHIFT 18 - #define NWS_REG_COMMON_CONTROL_CM1_PD_K2_E5 (0x3<<20) // CMU Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode) - #define NWS_REG_COMMON_CONTROL_CM1_PD_K2_E5_SHIFT 20 - #define NWS_REG_COMMON_CONTROL_LN0_PD_K2_E5 (0x3<<22) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode) - #define NWS_REG_COMMON_CONTROL_LN0_PD_K2_E5_SHIFT 22 - #define NWS_REG_COMMON_CONTROL_LN1_PD_K2_E5 (0x3<<24) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode) - #define NWS_REG_COMMON_CONTROL_LN1_PD_K2_E5_SHIFT 24 - #define NWS_REG_COMMON_CONTROL_LN2_PD_K2_E5 (0x3<<26) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode) - #define NWS_REG_COMMON_CONTROL_LN2_PD_K2_E5_SHIFT 26 - #define NWS_REG_COMMON_CONTROL_LN3_PD_K2_E5 (0x3<<28) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode) - #define NWS_REG_COMMON_CONTROL_LN3_PD_K2_E5_SHIFT 28 -#define NWS_REG_PHY_CTRL_K2_E5 0x700004UL //Access:RW DataWidth:0x11 // Multi Field Register. - #define NWS_REG_PHY_CTRL_REFCLK_K2_E5 (0x1f<<0) // Sets phy_ctrl_refclk_i used for CMU0 0x09 - refclk is 257.8125Mhz - #define NWS_REG_PHY_CTRL_REFCLK_K2_E5_SHIFT 0 - #define NWS_REG_PHY_CTRL_RATE1_K2_E5 (0x3f<<5) // Sets phy_ctrl_rate1_i used for CMU0 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125 Gbps 0x2F - Data rate is 1.25 Gbps - #define NWS_REG_PHY_CTRL_RATE1_K2_E5_SHIFT 5 - #define NWS_REG_PHY_CTRL_RATE2_K2_E5 (0x3f<<11) // Sets phy_ctrl_rate1_i used for CMU1 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125 Gbps 0x2F - Data rate is 1.25 Gbps - #define NWS_REG_PHY_CTRL_RATE2_K2_E5_SHIFT 11 -#define NWS_REG_ANEG_CFG_K2_E5 0x700008UL //Access:RW DataWidth:0x8 // Multi Field Register. - #define NWS_REG_ANEG_CFG_LN0_ANEG_CFG_I_K2_E5 (0x3<<0) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved - #define NWS_REG_ANEG_CFG_LN0_ANEG_CFG_I_K2_E5_SHIFT 0 - #define NWS_REG_ANEG_CFG_LN1_ANEG_CFG_I_K2_E5 (0x3<<2) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved - #define NWS_REG_ANEG_CFG_LN1_ANEG_CFG_I_K2_E5_SHIFT 2 - #define NWS_REG_ANEG_CFG_LN2_ANEG_CFG_I_K2_E5 (0x3<<4) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved - #define NWS_REG_ANEG_CFG_LN2_ANEG_CFG_I_K2_E5_SHIFT 4 - #define NWS_REG_ANEG_CFG_LN3_ANEG_CFG_I_K2_E5 (0x3<<6) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved - #define NWS_REG_ANEG_CFG_LN3_ANEG_CFG_I_K2_E5_SHIFT 6 -#define NWS_REG_COMMON_STATUS_K2_E5 0x70000cUL //Access:R DataWidth:0x9 // Multi Field Register. - #define NWS_REG_COMMON_STATUS_ERR_O_K2_E5 (0x1<<0) // 0x0 - No error 0x1 - Phy has internal error - #define NWS_REG_COMMON_STATUS_ERR_O_K2_E5_SHIFT 0 - #define NWS_REG_COMMON_STATUS_CM0_OK_O_K2_E5 (0x1<<1) // 0x1 - Indicates CMU0 PLL has locked to the reference clock and all output clocks are at the correct frequency - #define NWS_REG_COMMON_STATUS_CM0_OK_O_K2_E5_SHIFT 1 - #define NWS_REG_COMMON_STATUS_CM1_OK_O_K2_E5 (0x1<<2) // 0x1 - Indicates CMU1 PLL has locked to the reference clock and all output clocks are at the correct frequency - #define NWS_REG_COMMON_STATUS_CM1_OK_O_K2_E5_SHIFT 2 - #define NWS_REG_COMMON_STATUS_CM0_RST_PD_READY_O_K2_E5 (0x1<<3) // 0x0 - PHY is not ready to respond to cm0_rst_n_i and cm0_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to cm0_rst_n_i and cm0_pd_i[1:0]. - #define NWS_REG_COMMON_STATUS_CM0_RST_PD_READY_O_K2_E5_SHIFT 3 - #define NWS_REG_COMMON_STATUS_CM1_RST_PD_READY_O_K2_E5 (0x1<<4) // 0x0 - PHY is not ready to respond to cm1_rst_n_i and cm1_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to cm1_rst_n_i and cm1_pd_i[1:0]. - #define NWS_REG_COMMON_STATUS_CM1_RST_PD_READY_O_K2_E5_SHIFT 4 - #define NWS_REG_COMMON_STATUS_LN0_RST_PD_READY_O_K2_E5 (0x1<<5) // 0x0 - PHY is not ready to respond to ln0_rst_n_i and ln0_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln0_rst_n_i and ln0_pd_i[1:0]. - #define NWS_REG_COMMON_STATUS_LN0_RST_PD_READY_O_K2_E5_SHIFT 5 - #define NWS_REG_COMMON_STATUS_LN1_RST_PD_READY_O_K2_E5 (0x1<<6) // 0x0 - PHY is not ready to respond to ln1_rst_n_i and ln1_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln1_rst_n_i and ln1_pd_i[1:0]. - #define NWS_REG_COMMON_STATUS_LN1_RST_PD_READY_O_K2_E5_SHIFT 6 - #define NWS_REG_COMMON_STATUS_LN2_RST_PD_READY_O_K2_E5 (0x1<<7) // 0x0 - PHY is not ready to respond to ln2_rst_n_i and ln2_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln2_rst_n_i and ln2_pd_i[1:0]. - #define NWS_REG_COMMON_STATUS_LN2_RST_PD_READY_O_K2_E5_SHIFT 7 - #define NWS_REG_COMMON_STATUS_LN3_RST_PD_READY_O_K2_E5 (0x1<<8) // 0x0 - PHY is not ready to respond to ln3_rst_n_i and ln3_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln3_rst_n_i and ln3_pd_i[1:0]. - #define NWS_REG_COMMON_STATUS_LN3_RST_PD_READY_O_K2_E5_SHIFT 8 -#define NWS_REG_LN0_CNTL_K2_E5 0x700010UL //Access:RW DataWidth:0xa // Multi Field Register. - #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_WIDTH_K2_E5 (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved - #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_WIDTH_K2_E5_SHIFT 0 - #define NWS_REG_LN0_CNTL_LN0_CTRL_RXPOLARITY_K2_E5 (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion. - #define NWS_REG_LN0_CNTL_LN0_CTRL_RXPOLARITY_K2_E5_SHIFT 3 - #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_EN_K2_E5 (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register). - #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_EN_K2_E5_SHIFT 4 - #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_VALUE_K2_E5 (0x1<<5) // Informs the PHY that the received signal was lost. - #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_VALUE_K2_E5_SHIFT 5 - #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_RATE_I_K2_E5 (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved - #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_RATE_I_K2_E5_SHIFT 8 -#define NWS_REG_LN0_STATUS_K2_E5 0x700014UL //Access:R DataWidth:0x5 // Multi Field Register. - #define NWS_REG_LN0_STATUS_LN0_STAT_OK_K2_E5 (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data. - #define NWS_REG_LN0_STATUS_LN0_STAT_OK_K2_E5_SHIFT 0 - #define NWS_REG_LN0_STATUS_LN0_STAT_RXVALID_K2_E5 (0x1<<1) // 0x0 - data on ln0_rxdata_o is invalid. 0x1 - data on the active bits of ln0_rxdata_o is valid. - #define NWS_REG_LN0_STATUS_LN0_STAT_RXVALID_K2_E5_SHIFT 1 - #define NWS_REG_LN0_STATUS_LN0_STAT_RUNLEN_ERR_K2_E5 (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold. - #define NWS_REG_LN0_STATUS_LN0_STAT_RUNLEN_ERR_K2_E5_SHIFT 2 - #define NWS_REG_LN0_STATUS_LN0_STAT_LOS_K2_E5 (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. 0x1 - No Signal detected on ln0_rxp_i / ln0_rxm_i pins. - #define NWS_REG_LN0_STATUS_LN0_STAT_LOS_K2_E5_SHIFT 3 - #define NWS_REG_LN0_STATUS_LN0_STAT_LOS_DEGLITCH_K2_E5 (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. 0x1 - No Signal detected on ln0_rxp_i / ln0_rxm_i pins. - #define NWS_REG_LN0_STATUS_LN0_STAT_LOS_DEGLITCH_K2_E5_SHIFT 4 -#define NWS_REG_LN0_AN_LINK_INPUTS_K2_E5 0x700018UL //Access:RW DataWidth:0x9 // Multi Field Register. - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_CR2_I_K2_E5 (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_CR2_I_K2_E5_SHIFT 0 - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_KR2_I_K2_E5 (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_KR2_I_K2_E5_SHIFT 1 - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_CR4_I_K2_E5 (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_CR4_I_K2_E5_SHIFT 2 - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_KR4_I_K2_E5 (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_KR4_I_K2_E5_SHIFT 3 - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_CR_I_K2_E5 (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_CR_I_K2_E5_SHIFT 4 - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_GR_I_K2_E5 (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_GR_I_K2_E5_SHIFT 5 - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_KR_I_K2_E5 (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_KR_I_K2_E5_SHIFT 6 - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_10G_KR_I_K2_E5 (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_10G_KR_I_K2_E5_SHIFT 7 - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_1G_KX_I_K2_E5 (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_1G_KX_I_K2_E5_SHIFT 8 -#define NWS_REG_LN0_AN_LINK_OUTPUTS_K2_E5 0x70001cUL //Access:R DataWidth:0x19 // Multi Field Register. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_CR2_O_K2_E5 (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_CR2_O_K2_E5_SHIFT 0 - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_KR2_O_K2_E5 (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_KR2_O_K2_E5_SHIFT 2 - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_CR4_O_K2_E5 (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_CR4_O_K2_E5_SHIFT 4 - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_KR4_O_K2_E5 (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_KR4_O_K2_E5_SHIFT 6 - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_CR_O_K2_E5 (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_CR_O_K2_E5_SHIFT 8 - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_GR_O_K2_E5 (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_GR_O_K2_E5_SHIFT 10 - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_KR_O_K2_E5 (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_KR_O_K2_E5_SHIFT 12 - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_10G_KR_O_K2_E5 (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_10G_KR_O_K2_E5_SHIFT 14 - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_1G_KX_O_K2_E5 (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_1G_KX_O_K2_E5_SHIFT 16 - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_STAT_LT_SIGDET_O_K2_E5 (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_STAT_LT_SIGDET_O_K2_E5_SHIFT 18 - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_DME_OP_O_K2_E5 (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_DME_OP_O_K2_E5_SHIFT 19 - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_TX_PAUSE_EN_O_K2_E5 (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_TX_PAUSE_EN_O_K2_E5_SHIFT 20 - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RX_PAUSE_EN_O_K2_E5 (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RX_PAUSE_EN_O_K2_E5_SHIFT 21 - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_FC_FEC_EN_O_K2_E5 (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_FC_FEC_EN_O_K2_E5_SHIFT 22 - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RS_FEC_EN_O_K2_E5 (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RS_FEC_EN_O_K2_E5_SHIFT 23 - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_EEE_EN_O_K2_E5 (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output. - #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_EEE_EN_O_K2_E5_SHIFT 24 -#define NWS_REG_LN1_CNTL_K2_E5 0x700020UL //Access:RW DataWidth:0xa // Multi Field Register. - #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_WIDTH_K2_E5 (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved - #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_WIDTH_K2_E5_SHIFT 0 - #define NWS_REG_LN1_CNTL_LN1_CTRL_RXPOLARITY_K2_E5 (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion. - #define NWS_REG_LN1_CNTL_LN1_CTRL_RXPOLARITY_K2_E5_SHIFT 3 - #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_EN_K2_E5 (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register). - #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_EN_K2_E5_SHIFT 4 - #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_VALUE_K2_E5 (0x1<<5) // Informs the PHY that the received signal was lost. - #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_VALUE_K2_E5_SHIFT 5 - #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_RATE_I_K2_E5 (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved - #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_RATE_I_K2_E5_SHIFT 8 -#define NWS_REG_LN1_STATUS_K2_E5 0x700024UL //Access:R DataWidth:0x5 // Multi Field Register. - #define NWS_REG_LN1_STATUS_LN1_STAT_OK_K2_E5 (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data. - #define NWS_REG_LN1_STATUS_LN1_STAT_OK_K2_E5_SHIFT 0 - #define NWS_REG_LN1_STATUS_LN1_STAT_RXVALID_K2_E5 (0x1<<1) // 0x0 - data on ln1_rxdata_o is invalid. 0x1 - data on the active bits of ln1_rxdata_o is valid. - #define NWS_REG_LN1_STATUS_LN1_STAT_RXVALID_K2_E5_SHIFT 1 - #define NWS_REG_LN1_STATUS_LN1_STAT_RUNLEN_ERR_K2_E5 (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold. - #define NWS_REG_LN1_STATUS_LN1_STAT_RUNLEN_ERR_K2_E5_SHIFT 2 - #define NWS_REG_LN1_STATUS_LN1_STAT_LOS_K2_E5 (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. 0x1 - No Signal detected on ln1_rxp_i / ln1_rxm_i pins. - #define NWS_REG_LN1_STATUS_LN1_STAT_LOS_K2_E5_SHIFT 3 - #define NWS_REG_LN1_STATUS_LN1_STAT_LOS_DEGLITCH_K2_E5 (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. 0x1 - No Signal detected on ln1_rxp_i / ln1_rxm_i pins. - #define NWS_REG_LN1_STATUS_LN1_STAT_LOS_DEGLITCH_K2_E5_SHIFT 4 -#define NWS_REG_LN1_AN_LINK_INPUTS_K2_E5 0x700028UL //Access:RW DataWidth:0x9 // Multi Field Register. - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_CR2_I_K2_E5 (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_CR2_I_K2_E5_SHIFT 0 - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_KR2_I_K2_E5 (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_KR2_I_K2_E5_SHIFT 1 - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_CR4_I_K2_E5 (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_CR4_I_K2_E5_SHIFT 2 - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_KR4_I_K2_E5 (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_KR4_I_K2_E5_SHIFT 3 - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_CR_I_K2_E5 (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_CR_I_K2_E5_SHIFT 4 - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_GR_I_K2_E5 (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_GR_I_K2_E5_SHIFT 5 - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_KR_I_K2_E5 (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_KR_I_K2_E5_SHIFT 6 - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_10G_KR_I_K2_E5 (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_10G_KR_I_K2_E5_SHIFT 7 - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_1G_KX_I_K2_E5 (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_1G_KX_I_K2_E5_SHIFT 8 -#define NWS_REG_LN1_AN_LINK_OUTPUTS_K2_E5 0x70002cUL //Access:R DataWidth:0x19 // Multi Field Register. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_CR2_O_K2_E5 (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_CR2_O_K2_E5_SHIFT 0 - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_KR2_O_K2_E5 (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_KR2_O_K2_E5_SHIFT 2 - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_CR4_O_K2_E5 (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_CR4_O_K2_E5_SHIFT 4 - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_KR4_O_K2_E5 (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_KR4_O_K2_E5_SHIFT 6 - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_CR_O_K2_E5 (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_CR_O_K2_E5_SHIFT 8 - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_GR_O_K2_E5 (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_GR_O_K2_E5_SHIFT 10 - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_KR_O_K2_E5 (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_KR_O_K2_E5_SHIFT 12 - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_10G_KR_O_K2_E5 (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_10G_KR_O_K2_E5_SHIFT 14 - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_1G_KX_O_K2_E5 (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_1G_KX_O_K2_E5_SHIFT 16 - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_STAT_LT_SIGDET_O_K2_E5 (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_STAT_LT_SIGDET_O_K2_E5_SHIFT 18 - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_DME_OP_O_K2_E5 (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_DME_OP_O_K2_E5_SHIFT 19 - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_TX_PAUSE_EN_O_K2_E5 (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_TX_PAUSE_EN_O_K2_E5_SHIFT 20 - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RX_PAUSE_EN_O_K2_E5 (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RX_PAUSE_EN_O_K2_E5_SHIFT 21 - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_FC_FEC_EN_O_K2_E5 (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_FC_FEC_EN_O_K2_E5_SHIFT 22 - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RS_FEC_EN_O_K2_E5 (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RS_FEC_EN_O_K2_E5_SHIFT 23 - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_EEE_EN_O_K2_E5 (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output. - #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_EEE_EN_O_K2_E5_SHIFT 24 -#define NWS_REG_LN2_CNTL_K2_E5 0x700030UL //Access:RW DataWidth:0xa // Multi Field Register. - #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_WIDTH_K2_E5 (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved - #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_WIDTH_K2_E5_SHIFT 0 - #define NWS_REG_LN2_CNTL_LN2_CTRL_RXPOLARITY_K2_E5 (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion. - #define NWS_REG_LN2_CNTL_LN2_CTRL_RXPOLARITY_K2_E5_SHIFT 3 - #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_EN_K2_E5 (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register). - #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_EN_K2_E5_SHIFT 4 - #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_VALUE_K2_E5 (0x1<<5) // Informs the PHY that the received signal was lost. - #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_VALUE_K2_E5_SHIFT 5 - #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_RATE_I_K2_E5 (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved - #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_RATE_I_K2_E5_SHIFT 8 -#define NWS_REG_LN2_STATUS_K2_E5 0x700034UL //Access:R DataWidth:0x5 // Multi Field Register. - #define NWS_REG_LN2_STATUS_LN2_STAT_OK_K2_E5 (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data. - #define NWS_REG_LN2_STATUS_LN2_STAT_OK_K2_E5_SHIFT 0 - #define NWS_REG_LN2_STATUS_LN2_STAT_RXVALID_K2_E5 (0x1<<1) // 0x0 - data on ln2_rxdata_o is invalid. 0x1 - data on the active bits of ln2_rxdata_o is valid. - #define NWS_REG_LN2_STATUS_LN2_STAT_RXVALID_K2_E5_SHIFT 1 - #define NWS_REG_LN2_STATUS_LN2_STAT_RUNLEN_ERR_K2_E5 (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold. - #define NWS_REG_LN2_STATUS_LN2_STAT_RUNLEN_ERR_K2_E5_SHIFT 2 - #define NWS_REG_LN2_STATUS_LN2_STAT_LOS_K2_E5 (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. 0x1 - No Signal detected on ln2_rxp_i / ln2_rxm_i pins. - #define NWS_REG_LN2_STATUS_LN2_STAT_LOS_K2_E5_SHIFT 3 - #define NWS_REG_LN2_STATUS_LN2_STAT_LOS_DEGLITCH_K2_E5 (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. 0x1 - No Signal detected on ln2_rxp_i / ln2_rxm_i pins. - #define NWS_REG_LN2_STATUS_LN2_STAT_LOS_DEGLITCH_K2_E5_SHIFT 4 -#define NWS_REG_LN2_AN_LINK_INPUTS_K2_E5 0x700038UL //Access:RW DataWidth:0x9 // Multi Field Register. - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_CR2_I_K2_E5 (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_CR2_I_K2_E5_SHIFT 0 - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_KR2_I_K2_E5 (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_KR2_I_K2_E5_SHIFT 1 - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_CR4_I_K2_E5 (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_CR4_I_K2_E5_SHIFT 2 - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_KR4_I_K2_E5 (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_KR4_I_K2_E5_SHIFT 3 - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_CR_I_K2_E5 (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_CR_I_K2_E5_SHIFT 4 - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_GR_I_K2_E5 (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_GR_I_K2_E5_SHIFT 5 - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_KR_I_K2_E5 (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_KR_I_K2_E5_SHIFT 6 - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_10G_KR_I_K2_E5 (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_10G_KR_I_K2_E5_SHIFT 7 - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_1G_KX_I_K2_E5 (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_1G_KX_I_K2_E5_SHIFT 8 -#define NWS_REG_LN2_AN_LINK_OUTPUTS_K2_E5 0x70003cUL //Access:R DataWidth:0x19 // Multi Field Register. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_CR2_O_K2_E5 (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_CR2_O_K2_E5_SHIFT 0 - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_KR2_O_K2_E5 (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_KR2_O_K2_E5_SHIFT 2 - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_CR4_O_K2_E5 (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_CR4_O_K2_E5_SHIFT 4 - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_KR4_O_K2_E5 (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_KR4_O_K2_E5_SHIFT 6 - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_CR_O_K2_E5 (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_CR_O_K2_E5_SHIFT 8 - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_GR_O_K2_E5 (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_GR_O_K2_E5_SHIFT 10 - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_KR_O_K2_E5 (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_KR_O_K2_E5_SHIFT 12 - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_10G_KR_O_K2_E5 (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_10G_KR_O_K2_E5_SHIFT 14 - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_1G_KX_O_K2_E5 (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_1G_KX_O_K2_E5_SHIFT 16 - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_STAT_LT_SIGDET_O_K2_E5 (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_STAT_LT_SIGDET_O_K2_E5_SHIFT 18 - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_DME_OP_O_K2_E5 (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_DME_OP_O_K2_E5_SHIFT 19 - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_TX_PAUSE_EN_O_K2_E5 (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_TX_PAUSE_EN_O_K2_E5_SHIFT 20 - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RX_PAUSE_EN_O_K2_E5 (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RX_PAUSE_EN_O_K2_E5_SHIFT 21 - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_FC_FEC_EN_O_K2_E5 (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_FC_FEC_EN_O_K2_E5_SHIFT 22 - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RS_FEC_EN_O_K2_E5 (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RS_FEC_EN_O_K2_E5_SHIFT 23 - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_EEE_EN_O_K2_E5 (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output. - #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_EEE_EN_O_K2_E5_SHIFT 24 -#define NWS_REG_LN3_CNTL_K2_E5 0x700040UL //Access:RW DataWidth:0xa // Multi Field Register. - #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_WIDTH_K2_E5 (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved - #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_WIDTH_K2_E5_SHIFT 0 - #define NWS_REG_LN3_CNTL_LN3_CTRL_RXPOLARITY_K2_E5 (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion. - #define NWS_REG_LN3_CNTL_LN3_CTRL_RXPOLARITY_K2_E5_SHIFT 3 - #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_EN_K2_E5 (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register). - #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_EN_K2_E5_SHIFT 4 - #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_VALUE_K2_E5 (0x1<<5) // Informs the PHY that the received signal was lost. - #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_VALUE_K2_E5_SHIFT 5 - #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_RATE_I_K2_E5 (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved - #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_RATE_I_K2_E5_SHIFT 8 -#define NWS_REG_LN3_STATUS_K2_E5 0x700044UL //Access:R DataWidth:0x5 // Multi Field Register. - #define NWS_REG_LN3_STATUS_LN3_STAT_OK_K2_E5 (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data. - #define NWS_REG_LN3_STATUS_LN3_STAT_OK_K2_E5_SHIFT 0 - #define NWS_REG_LN3_STATUS_LN3_STAT_RXVALID_K2_E5 (0x1<<1) // 0x0 - data on ln3_rxdata_o is invalid. 0x1 - data on the active bits of ln3_rxdata_o is valid. - #define NWS_REG_LN3_STATUS_LN3_STAT_RXVALID_K2_E5_SHIFT 1 - #define NWS_REG_LN3_STATUS_LN3_STAT_RUNLEN_ERR_K2_E5 (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold. - #define NWS_REG_LN3_STATUS_LN3_STAT_RUNLEN_ERR_K2_E5_SHIFT 2 - #define NWS_REG_LN3_STATUS_LN3_STAT_LOS_K2_E5 (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. 0x1 - No Signal detected on ln3_rxp_i / ln3_rxm_i pins. - #define NWS_REG_LN3_STATUS_LN3_STAT_LOS_K2_E5_SHIFT 3 - #define NWS_REG_LN3_STATUS_LN3_STAT_LOS_DEGLITCH_K2_E5 (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. 0x1 - No Signal detected on ln3_rxp_i / ln3_rxm_i pins. - #define NWS_REG_LN3_STATUS_LN3_STAT_LOS_DEGLITCH_K2_E5_SHIFT 4 -#define NWS_REG_LN3_AN_LINK_INPUTS_K2_E5 0x700048UL //Access:RW DataWidth:0x9 // Multi Field Register. - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_CR2_I_K2_E5 (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_CR2_I_K2_E5_SHIFT 0 - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_KR2_I_K2_E5 (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_KR2_I_K2_E5_SHIFT 1 - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_CR4_I_K2_E5 (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_CR4_I_K2_E5_SHIFT 2 - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_KR4_I_K2_E5 (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_KR4_I_K2_E5_SHIFT 3 - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_CR_I_K2_E5 (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_CR_I_K2_E5_SHIFT 4 - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_GR_I_K2_E5 (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_GR_I_K2_E5_SHIFT 5 - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_KR_I_K2_E5 (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_KR_I_K2_E5_SHIFT 6 - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_10G_KR_I_K2_E5 (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_10G_KR_I_K2_E5_SHIFT 7 - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_1G_KX_I_K2_E5 (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner - #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_1G_KX_I_K2_E5_SHIFT 8 -#define NWS_REG_LN3_AN_LINK_OUTPUTS_K2_E5 0x70004cUL //Access:R DataWidth:0x19 // Multi Field Register. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_CR2_O_K2_E5 (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_CR2_O_K2_E5_SHIFT 0 - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_KR2_O_K2_E5 (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_KR2_O_K2_E5_SHIFT 2 - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_CR4_O_K2_E5 (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_CR4_O_K2_E5_SHIFT 4 - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_KR4_O_K2_E5 (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_KR4_O_K2_E5_SHIFT 6 - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_CR_O_K2_E5 (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_CR_O_K2_E5_SHIFT 8 - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_GR_O_K2_E5 (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_GR_O_K2_E5_SHIFT 10 - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_KR_O_K2_E5 (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_KR_O_K2_E5_SHIFT 12 - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_10G_KR_O_K2_E5 (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_10G_KR_O_K2_E5_SHIFT 14 - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_1G_KX_O_K2_E5 (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_1G_KX_O_K2_E5_SHIFT 16 - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_STAT_LT_SIGDET_O_K2_E5 (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_STAT_LT_SIGDET_O_K2_E5_SHIFT 18 - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_DME_OP_O_K2_E5 (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_DME_OP_O_K2_E5_SHIFT 19 - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_TX_PAUSE_EN_O_K2_E5 (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_TX_PAUSE_EN_O_K2_E5_SHIFT 20 - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RX_PAUSE_EN_O_K2_E5 (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RX_PAUSE_EN_O_K2_E5_SHIFT 21 - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_FC_FEC_EN_O_K2_E5 (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_FC_FEC_EN_O_K2_E5_SHIFT 22 - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RS_FEC_EN_O_K2_E5 (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RS_FEC_EN_O_K2_E5_SHIFT 23 - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_EEE_EN_O_K2_E5 (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output. - #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_EEE_EN_O_K2_E5_SHIFT 24 -#define NWS_REG_EXTERNAL_SIGNAL_DETECT_K2_E5 0x700050UL //Access:R DataWidth:0x4 // Multi Field Register. +#define NWS_REG_HSS0_CONTROL_COMMON_E5 0x700000UL //Access:RW DataWidth:0x6 // Multi Field Register. + #define NWS_REG_HSS0_CONTROL_COMMON_HSS0RESET_E5 (0x1<<0) // HSS Core Reset. Asynchronous reset input signal. This signal must be asserted for a minimum of 170 ns (see HSSRESET on page 48). This signal is sampled within the core and initiates a complete reset sequence of all core functions, including HS PLL calibration and lock. When this signal is deasserted, the internal reset and TX resync sequence is initiated. 0 Normal Operation. 1 Reset. This reset signal is level sensitive, active high within the logic. Its falling edge initiates the required internal reset sequence that initializes the core. + #define NWS_REG_HSS0_CONTROL_COMMON_HSS0RESET_E5_SHIFT 0 + #define NWS_REG_HSS0_CONTROL_COMMON_HSS0RXACMODE_E5 (0x1<<1) // Receiver AC-coupling Mode Selector. Sets the receiver termination. + #define NWS_REG_HSS0_CONTROL_COMMON_HSS0RXACMODE_E5_SHIFT 1 + #define NWS_REG_HSS0_CONTROL_COMMON_HSS0PORPWREN_E5 (0x1<<2) // Power-On-Reset Power Enable. When low, this input powers down the TX and RX analog circuits. It can be used to manage the analog supply currents to a predictable low level before the assertion of HSSRESET. If used, it must come from circuits that can hold it low, without glitching, from the time VDD is ramped up until after HSSRESET is asserted high. + #define NWS_REG_HSS0_CONTROL_COMMON_HSS0PORPWREN_E5_SHIFT 2 + #define NWS_REG_HSS0_CONTROL_COMMON_HSS0RECCALA_E5 (0x1<<3) // Unknown signal, not in users guide + #define NWS_REG_HSS0_CONTROL_COMMON_HSS0RECCALA_E5_SHIFT 3 + #define NWS_REG_HSS0_CONTROL_COMMON_HSS0RECCALB_E5 (0x1<<4) // Unknown signal, not in users guide + #define NWS_REG_HSS0_CONTROL_COMMON_HSS0RECCALB_E5_SHIFT 4 + #define NWS_REG_HSS0_CONTROL_COMMON_HSS0NWS_RBC_CLK_SEL_E5 (0x1<<5) // Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pllA (1G and 10G) (default) + #define NWS_REG_HSS0_CONTROL_COMMON_HSS0NWS_RBC_CLK_SEL_E5_SHIFT 5 +#define NWS_REG_COMMON_CONTROL_K2 0x700000UL //Access:RW DataWidth:0x1e // Multi Field Register. + #define NWS_REG_COMMON_CONTROL_REFCLK_INPUT_SEL_I_K2 (0x3<<0) // 0x0 - Select reference clock from Bump 0x1 - Select inter-macro refrence clock from the left side 0x2 - Same as 0x0 0x3 - Select inter-macro refrence clock from the right side + #define NWS_REG_COMMON_CONTROL_REFCLK_INPUT_SEL_I_K2_SHIFT 0 + #define NWS_REG_COMMON_CONTROL_REFCLK_LEFT_SEL_I_K2 (0x3<<2) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro refrence clock from the right side 0x3 - Same as 0x2 + #define NWS_REG_COMMON_CONTROL_REFCLK_LEFT_SEL_I_K2_SHIFT 2 + #define NWS_REG_COMMON_CONTROL_REFCLK_RIGHT_SEL_I_K2 (0x3<<4) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro refrence clock from the left side 0x3 - Same as 0x2 + #define NWS_REG_COMMON_CONTROL_REFCLK_RIGHT_SEL_I_K2_SHIFT 4 + #define NWS_REG_COMMON_CONTROL_STAT_LOS_SELECT_K2 (0x3<<6) // Selects which stat_los signal is used for nws_nwm_sd_energy_detect. 0 - use ~lnX_stat_los_o 1 - use ~lnX_stat_los_deglitch_o (Default) 2 - use lnX_stat_rxvalid_o + #define NWS_REG_COMMON_CONTROL_STAT_LOS_SELECT_K2_SHIFT 6 + #define NWS_REG_COMMON_CONTROL_CPU_RESET_K2 (0x1<<10) // Controls cpu_reset_i reset signal into the SerDes. + #define NWS_REG_COMMON_CONTROL_CPU_RESET_K2_SHIFT 10 + #define NWS_REG_COMMON_CONTROL_POR_N_K2 (0x1<<11) // Controls por_n_i reset signal into the SerDes. This should be 0 (Reset value) while the SerDes program and data rams are being written, and the serdes is being configured. This holds the SerDes in Reset. Once the memory is configured, write 1 to this bit to allow the SerDes to begin normal Operation. + #define NWS_REG_COMMON_CONTROL_POR_N_K2_SHIFT 11 + #define NWS_REG_COMMON_CONTROL_CM0_RST_N_K2 (0x1<<12) // Controls cm0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the cmu0 in Reset. write 1 to this bit to allow the SerDes to begin normal Operation. + #define NWS_REG_COMMON_CONTROL_CM0_RST_N_K2_SHIFT 12 + #define NWS_REG_COMMON_CONTROL_CM1_RST_N_K2 (0x1<<13) // Controls cm1_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the cmu0 in Reset. write 1 to this bit to allow the SerDes to begin normal Operation. + #define NWS_REG_COMMON_CONTROL_CM1_RST_N_K2_SHIFT 13 + #define NWS_REG_COMMON_CONTROL_LN0_RST_N_K2 (0x1<<14) // Controls ln0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln0 in Reset. write 1 to begin normal Operation on ln0. + #define NWS_REG_COMMON_CONTROL_LN0_RST_N_K2_SHIFT 14 + #define NWS_REG_COMMON_CONTROL_LN1_RST_N_K2 (0x1<<15) // Controls ln1_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln1 in Reset. write 1 to begin normal Operation on ln1. + #define NWS_REG_COMMON_CONTROL_LN1_RST_N_K2_SHIFT 15 + #define NWS_REG_COMMON_CONTROL_LN2_RST_N_K2 (0x1<<16) // Controls ln0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln2 in Reset. write 1 to begin normal Operation on ln2. + #define NWS_REG_COMMON_CONTROL_LN2_RST_N_K2_SHIFT 16 + #define NWS_REG_COMMON_CONTROL_LN3_RST_N_K2 (0x1<<17) // Controls ln3_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln3 in Reset. write 1 to begin normal Operation on ln3. + #define NWS_REG_COMMON_CONTROL_LN3_RST_N_K2_SHIFT 17 + #define NWS_REG_COMMON_CONTROL_CM0_PD_K2 (0x3<<18) // CMU Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode) + #define NWS_REG_COMMON_CONTROL_CM0_PD_K2_SHIFT 18 + #define NWS_REG_COMMON_CONTROL_CM1_PD_K2 (0x3<<20) // CMU Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode) + #define NWS_REG_COMMON_CONTROL_CM1_PD_K2_SHIFT 20 + #define NWS_REG_COMMON_CONTROL_LN0_PD_K2 (0x3<<22) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode) + #define NWS_REG_COMMON_CONTROL_LN0_PD_K2_SHIFT 22 + #define NWS_REG_COMMON_CONTROL_LN1_PD_K2 (0x3<<24) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode) + #define NWS_REG_COMMON_CONTROL_LN1_PD_K2_SHIFT 24 + #define NWS_REG_COMMON_CONTROL_LN2_PD_K2 (0x3<<26) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode) + #define NWS_REG_COMMON_CONTROL_LN2_PD_K2_SHIFT 26 + #define NWS_REG_COMMON_CONTROL_LN3_PD_K2 (0x3<<28) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode) + #define NWS_REG_COMMON_CONTROL_LN3_PD_K2_SHIFT 28 +#define NWS_REG_HSS0_CONTROLA_E5 0x700004UL //Access:RW DataWidth:0x1b // Multi Field Register. + #define NWS_REG_HSS0_CONTROLA_HSS0DIVSELA_E5 (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88 + #define NWS_REG_HSS0_CONTROLA_HSS0DIVSELA_E5_SHIFT 0 + #define NWS_REG_HSS0_CONTROLA_HSS0REFDIVA_E5 (0xf<<9) // Bandgap Refclock Divider Ratio + #define NWS_REG_HSS0_CONTROLA_HSS0REFDIVA_E5_SHIFT 9 + #define NWS_REG_HSS0_CONTROLA_HSS0PLLCONFIGA_E5 (0x3fff<<13) // HS PLLp Configuration and Tuning Bits + #define NWS_REG_HSS0_CONTROLA_HSS0PLLCONFIGA_E5_SHIFT 13 +#define NWS_REG_PHY_CTRL_K2 0x700004UL //Access:RW DataWidth:0x11 // Multi Field Register. + #define NWS_REG_PHY_CTRL_REFCLK_K2 (0x1f<<0) // Sets phy_ctrl_refclk_i used for CMU0 0x09 - refclk is 257.8125Mhz + #define NWS_REG_PHY_CTRL_REFCLK_K2_SHIFT 0 + #define NWS_REG_PHY_CTRL_RATE1_K2 (0x3f<<5) // Sets phy_ctrl_rate1_i used for CMU0 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125 Gbps 0x2F - Data rate is 1.25 Gbps + #define NWS_REG_PHY_CTRL_RATE1_K2_SHIFT 5 + #define NWS_REG_PHY_CTRL_RATE2_K2 (0x3f<<11) // Sets phy_ctrl_rate1_i used for CMU1 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125 Gbps 0x2F - Data rate is 1.25 Gbps + #define NWS_REG_PHY_CTRL_RATE2_K2_SHIFT 11 +#define NWS_REG_HSS0_CONTROL1A_E5 0x700008UL //Access:RW DataWidth:0x6 // Multi Field Register. + #define NWS_REG_HSS0_CONTROL1A_HSS0VCOSELA_E5 (0x1<<0) // Frequency Range Control + #define NWS_REG_HSS0_CONTROL1A_HSS0VCOSELA_E5_SHIFT 0 + #define NWS_REG_HSS0_CONTROL1A_HSS0RESYNCA_E5 (0x1<<1) // Core Resync + #define NWS_REG_HSS0_CONTROL1A_HSS0RESYNCA_E5_SHIFT 1 + #define NWS_REG_HSS0_CONTROL1A_HSS0VREGBYPA_E5 (0x1<<2) // HS PLLp Voltage Regulator Bypass + #define NWS_REG_HSS0_CONTROL1A_HSS0VREGBYPA_E5_SHIFT 2 + #define NWS_REG_HSS0_CONTROL1A_HSS0PDWNPLLA_E5 (0x1<<3) // HS PLLp Power Down + #define NWS_REG_HSS0_CONTROL1A_HSS0PDWNPLLA_E5_SHIFT 3 + #define NWS_REG_HSS0_CONTROL1A_HSS0PLLFASTCALA_E5 (0x1<<4) // HS PLLp Fast Calibration. + #define NWS_REG_HSS0_CONTROL1A_HSS0PLLFASTCALA_E5_SHIFT 4 + #define NWS_REG_HSS0_CONTROL1A_HSS0REFCLKVALIDA_E5 (0x1<<5) // HS PLLp ref clk valid. + #define NWS_REG_HSS0_CONTROL1A_HSS0REFCLKVALIDA_E5_SHIFT 5 +#define NWS_REG_ANEG_CFG_K2 0x700008UL //Access:RW DataWidth:0x8 // Multi Field Register. + #define NWS_REG_ANEG_CFG_LN0_ANEG_CFG_I_K2 (0x3<<0) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved + #define NWS_REG_ANEG_CFG_LN0_ANEG_CFG_I_K2_SHIFT 0 + #define NWS_REG_ANEG_CFG_LN1_ANEG_CFG_I_K2 (0x3<<2) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved + #define NWS_REG_ANEG_CFG_LN1_ANEG_CFG_I_K2_SHIFT 2 + #define NWS_REG_ANEG_CFG_LN2_ANEG_CFG_I_K2 (0x3<<4) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved + #define NWS_REG_ANEG_CFG_LN2_ANEG_CFG_I_K2_SHIFT 4 + #define NWS_REG_ANEG_CFG_LN3_ANEG_CFG_I_K2 (0x3<<6) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved + #define NWS_REG_ANEG_CFG_LN3_ANEG_CFG_I_K2_SHIFT 6 +#define NWS_REG_HSS0_CONTROLB_E5 0x70000cUL //Access:RW DataWidth:0x1b // Multi Field Register. + #define NWS_REG_HSS0_CONTROLB_HSS0DIVSELB_E5 (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441 + #define NWS_REG_HSS0_CONTROLB_HSS0DIVSELB_E5_SHIFT 0 + #define NWS_REG_HSS0_CONTROLB_HSS0REFDIVB_E5 (0xf<<9) // Bandgap Refclock Divider Ratio + #define NWS_REG_HSS0_CONTROLB_HSS0REFDIVB_E5_SHIFT 9 + #define NWS_REG_HSS0_CONTROLB_HSS0PLLCONFIGB_E5 (0x3fff<<13) // HS PLLp Configuration and Tuning Bits + #define NWS_REG_HSS0_CONTROLB_HSS0PLLCONFIGB_E5_SHIFT 13 +#define NWS_REG_COMMON_STATUS_K2 0x70000cUL //Access:R DataWidth:0x9 // Multi Field Register. + #define NWS_REG_COMMON_STATUS_ERR_O_K2 (0x1<<0) // 0x0 - No error 0x1 - Phy has internal error + #define NWS_REG_COMMON_STATUS_ERR_O_K2_SHIFT 0 + #define NWS_REG_COMMON_STATUS_CM0_OK_O_K2 (0x1<<1) // 0x1 - Indicates CMU0 PLL has locked to the reference clock and all output clocks are at the correct frequency + #define NWS_REG_COMMON_STATUS_CM0_OK_O_K2_SHIFT 1 + #define NWS_REG_COMMON_STATUS_CM1_OK_O_K2 (0x1<<2) // 0x1 - Indicates CMU1 PLL has locked to the reference clock and all output clocks are at the correct frequency + #define NWS_REG_COMMON_STATUS_CM1_OK_O_K2_SHIFT 2 + #define NWS_REG_COMMON_STATUS_CM0_RST_PD_READY_O_K2 (0x1<<3) // 0x0 - PHY is not ready to respond to cm0_rst_n_i and cm0_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to cm0_rst_n_i and cm0_pd_i[1:0]. + #define NWS_REG_COMMON_STATUS_CM0_RST_PD_READY_O_K2_SHIFT 3 + #define NWS_REG_COMMON_STATUS_CM1_RST_PD_READY_O_K2 (0x1<<4) // 0x0 - PHY is not ready to respond to cm1_rst_n_i and cm1_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to cm1_rst_n_i and cm1_pd_i[1:0]. + #define NWS_REG_COMMON_STATUS_CM1_RST_PD_READY_O_K2_SHIFT 4 + #define NWS_REG_COMMON_STATUS_LN0_RST_PD_READY_O_K2 (0x1<<5) // 0x0 - PHY is not ready to respond to ln0_rst_n_i and ln0_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln0_rst_n_i and ln0_pd_i[1:0]. + #define NWS_REG_COMMON_STATUS_LN0_RST_PD_READY_O_K2_SHIFT 5 + #define NWS_REG_COMMON_STATUS_LN1_RST_PD_READY_O_K2 (0x1<<6) // 0x0 - PHY is not ready to respond to ln1_rst_n_i and ln1_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln1_rst_n_i and ln1_pd_i[1:0]. + #define NWS_REG_COMMON_STATUS_LN1_RST_PD_READY_O_K2_SHIFT 6 + #define NWS_REG_COMMON_STATUS_LN2_RST_PD_READY_O_K2 (0x1<<7) // 0x0 - PHY is not ready to respond to ln2_rst_n_i and ln2_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln2_rst_n_i and ln2_pd_i[1:0]. + #define NWS_REG_COMMON_STATUS_LN2_RST_PD_READY_O_K2_SHIFT 7 + #define NWS_REG_COMMON_STATUS_LN3_RST_PD_READY_O_K2 (0x1<<8) // 0x0 - PHY is not ready to respond to ln3_rst_n_i and ln3_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln3_rst_n_i and ln3_pd_i[1:0]. + #define NWS_REG_COMMON_STATUS_LN3_RST_PD_READY_O_K2_SHIFT 8 +#define NWS_REG_HSS0_CONTROL1B_E5 0x700010UL //Access:RW DataWidth:0x6 // Multi Field Register. + #define NWS_REG_HSS0_CONTROL1B_HSS0VCOSELB_E5 (0x1<<0) // Frequency Range Control + #define NWS_REG_HSS0_CONTROL1B_HSS0VCOSELB_E5_SHIFT 0 + #define NWS_REG_HSS0_CONTROL1B_HSS0RESYNCB_E5 (0x1<<1) // Core Resync + #define NWS_REG_HSS0_CONTROL1B_HSS0RESYNCB_E5_SHIFT 1 + #define NWS_REG_HSS0_CONTROL1B_HSS0VREGBYPB_E5 (0x1<<2) // HS PLLp Voltage Regulator Bypass + #define NWS_REG_HSS0_CONTROL1B_HSS0VREGBYPB_E5_SHIFT 2 + #define NWS_REG_HSS0_CONTROL1B_HSS0PDWNPLLB_E5 (0x1<<3) // HS PLLp Power Down + #define NWS_REG_HSS0_CONTROL1B_HSS0PDWNPLLB_E5_SHIFT 3 + #define NWS_REG_HSS0_CONTROL1B_HSS0PLLFASTCALB_E5 (0x1<<4) // HS PLLp Fast Calibration. + #define NWS_REG_HSS0_CONTROL1B_HSS0PLLFASTCALB_E5_SHIFT 4 + #define NWS_REG_HSS0_CONTROL1B_HSS0REFCLKVALIDB_E5 (0x1<<5) // HS PLLp ref clk valid. + #define NWS_REG_HSS0_CONTROL1B_HSS0REFCLKVALIDB_E5_SHIFT 5 +#define NWS_REG_LN0_CNTL_K2 0x700010UL //Access:RW DataWidth:0xa // Multi Field Register. + #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_WIDTH_K2 (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved + #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_WIDTH_K2_SHIFT 0 + #define NWS_REG_LN0_CNTL_LN0_CTRL_RXPOLARITY_K2 (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion. + #define NWS_REG_LN0_CNTL_LN0_CTRL_RXPOLARITY_K2_SHIFT 3 + #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_EN_K2 (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register). + #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_EN_K2_SHIFT 4 + #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_VALUE_K2 (0x1<<5) // Informs the PHY that the received signal was lost. + #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_VALUE_K2_SHIFT 5 + #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_RATE_I_K2 (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved + #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_RATE_I_K2_SHIFT 8 +#define NWS_REG_HSS0_STATUS_E5 0x700014UL //Access:R DataWidth:0x5 // Multi Field Register. + #define NWS_REG_HSS0_STATUS_HSS0PLLLOCKA_E5 (0x1<<0) // 0x0 - Unlocked 0x1 - Locked + #define NWS_REG_HSS0_STATUS_HSS0PLLLOCKA_E5_SHIFT 0 + #define NWS_REG_HSS0_STATUS_HSS0PLLLOCKB_E5 (0x1<<1) // 0x0 - Unlocked 0x1 - Locked + #define NWS_REG_HSS0_STATUS_HSS0PLLLOCKB_E5_SHIFT 1 + #define NWS_REG_HSS0_STATUS_HSS0PRTREADYA_E5 (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after reset sequence and offset calibration) + #define NWS_REG_HSS0_STATUS_HSS0PRTREADYA_E5_SHIFT 2 + #define NWS_REG_HSS0_STATUS_HSS0PRTREADYB_E5 (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after reset sequence and offset calibration) + #define NWS_REG_HSS0_STATUS_HSS0PRTREADYB_E5_SHIFT 3 + #define NWS_REG_HSS0_STATUS_HSS0EYEQUALITY_E5 (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX links in the core. 0x1 - Active. New status information is available for at least one RX in the core. When active, register 0x1E for each RX link can be read to determine updated status + #define NWS_REG_HSS0_STATUS_HSS0EYEQUALITY_E5_SHIFT 4 +#define NWS_REG_LN0_STATUS_K2 0x700014UL //Access:R DataWidth:0x5 // Multi Field Register. + #define NWS_REG_LN0_STATUS_LN0_STAT_OK_K2 (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data. + #define NWS_REG_LN0_STATUS_LN0_STAT_OK_K2_SHIFT 0 + #define NWS_REG_LN0_STATUS_LN0_STAT_RXVALID_K2 (0x1<<1) // 0x0 - data on ln0_rxdata_o is invalid. 0x1 - data on the active bits of ln0_rxdata_o is valid. + #define NWS_REG_LN0_STATUS_LN0_STAT_RXVALID_K2_SHIFT 1 + #define NWS_REG_LN0_STATUS_LN0_STAT_RUNLEN_ERR_K2 (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold. + #define NWS_REG_LN0_STATUS_LN0_STAT_RUNLEN_ERR_K2_SHIFT 2 + #define NWS_REG_LN0_STATUS_LN0_STAT_LOS_K2 (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. 0x1 - No Signal detected on ln0_rxp_i / ln0_rxm_i pins. + #define NWS_REG_LN0_STATUS_LN0_STAT_LOS_K2_SHIFT 3 + #define NWS_REG_LN0_STATUS_LN0_STAT_LOS_DEGLITCH_K2 (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. 0x1 - No Signal detected on ln0_rxp_i / ln0_rxm_i pins. + #define NWS_REG_LN0_STATUS_LN0_STAT_LOS_DEGLITCH_K2_SHIFT 4 +#define NWS_REG_HSS1_CONTROL_COMMON_E5 0x700018UL //Access:RW DataWidth:0x6 // Multi Field Register. + #define NWS_REG_HSS1_CONTROL_COMMON_HSS1RESET_E5 (0x1<<0) // HSS Core Reset. Asynchronous reset input signal. This signal must be asserted for a minimum of 170 ns (see HSSRESET on page 48). This signal is sampled within the core and initiates a complete reset sequence of all core functions, including HS PLL calibration and lock. When this signal is deasserted, the internal reset and TX resync sequence is initiated. 0 Normal Operation. 1 Reset. This reset signal is level sensitive, active high within the logic. Its falling edge initiates the required internal reset sequence that initializes the core. + #define NWS_REG_HSS1_CONTROL_COMMON_HSS1RESET_E5_SHIFT 0 + #define NWS_REG_HSS1_CONTROL_COMMON_HSS1RXACMODE_E5 (0x1<<1) // Receiver AC-coupling Mode Selector. Sets the receiver termination. + #define NWS_REG_HSS1_CONTROL_COMMON_HSS1RXACMODE_E5_SHIFT 1 + #define NWS_REG_HSS1_CONTROL_COMMON_HSS1PORPWREN_E5 (0x1<<2) // Power-On-Reset Power Enable. When low, this input powers down the TX and RX analog circuits. It can be used to manage the analog supply currents to a predictable low level before the assertion of HSSRESET. If used, it must come from circuits that can hold it low, without glitching, from the time VDD is ramped up until after HSSRESET is asserted high. + #define NWS_REG_HSS1_CONTROL_COMMON_HSS1PORPWREN_E5_SHIFT 2 + #define NWS_REG_HSS1_CONTROL_COMMON_HSS1RECCALA_E5 (0x1<<3) // Unknown signal, not in users guide + #define NWS_REG_HSS1_CONTROL_COMMON_HSS1RECCALA_E5_SHIFT 3 + #define NWS_REG_HSS1_CONTROL_COMMON_HSS1RECCALB_E5 (0x1<<4) // Unknown signal, not in users guide + #define NWS_REG_HSS1_CONTROL_COMMON_HSS1RECCALB_E5_SHIFT 4 + #define NWS_REG_HSS1_CONTROL_COMMON_HSS1NWS_RBC_CLK_SEL_E5 (0x1<<5) // Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pllA (1G and 10G) (default) + #define NWS_REG_HSS1_CONTROL_COMMON_HSS1NWS_RBC_CLK_SEL_E5_SHIFT 5 +#define NWS_REG_LN0_AN_LINK_INPUTS_K2 0x700018UL //Access:RW DataWidth:0x9 // Multi Field Register. + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_CR2_I_K2 (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_CR2_I_K2_SHIFT 0 + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_KR2_I_K2 (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_KR2_I_K2_SHIFT 1 + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_CR4_I_K2 (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_CR4_I_K2_SHIFT 2 + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_KR4_I_K2_SHIFT 3 + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_CR_I_K2 (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_CR_I_K2_SHIFT 4 + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_GR_I_K2 (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_GR_I_K2_SHIFT 5 + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_KR_I_K2 (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_KR_I_K2_SHIFT 6 + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_10G_KR_I_K2 (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_10G_KR_I_K2_SHIFT 7 + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_1G_KX_I_K2 (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_1G_KX_I_K2_SHIFT 8 +#define NWS_REG_HSS1_CONTROLA_E5 0x70001cUL //Access:RW DataWidth:0x1b // Multi Field Register. + #define NWS_REG_HSS1_CONTROLA_HSS1DIVSELA_E5 (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88 + #define NWS_REG_HSS1_CONTROLA_HSS1DIVSELA_E5_SHIFT 0 + #define NWS_REG_HSS1_CONTROLA_HSS1REFDIVA_E5 (0xf<<9) // Bandgap Refclock Divider Ratio + #define NWS_REG_HSS1_CONTROLA_HSS1REFDIVA_E5_SHIFT 9 + #define NWS_REG_HSS1_CONTROLA_HSS1PLLCONFIGA_E5 (0x3fff<<13) // HS PLLp Configuration and Tuning Bits + #define NWS_REG_HSS1_CONTROLA_HSS1PLLCONFIGA_E5_SHIFT 13 +#define NWS_REG_LN0_AN_LINK_OUTPUTS_K2 0x70001cUL //Access:R DataWidth:0x19 // Multi Field Register. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_CR2_O_K2 (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_CR2_O_K2_SHIFT 0 + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_KR2_O_K2 (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_KR2_O_K2_SHIFT 2 + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_CR4_O_K2 (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_CR4_O_K2_SHIFT 4 + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_KR4_O_K2 (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_KR4_O_K2_SHIFT 6 + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_CR_O_K2 (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_CR_O_K2_SHIFT 8 + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_GR_O_K2 (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_GR_O_K2_SHIFT 10 + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_KR_O_K2 (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_KR_O_K2_SHIFT 12 + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_10G_KR_O_K2 (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_10G_KR_O_K2_SHIFT 14 + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_1G_KX_O_K2 (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_1G_KX_O_K2_SHIFT 16 + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_STAT_LT_SIGDET_O_K2 (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_STAT_LT_SIGDET_O_K2_SHIFT 18 + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_DME_OP_O_K2 (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_DME_OP_O_K2_SHIFT 19 + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_TX_PAUSE_EN_O_K2 (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_TX_PAUSE_EN_O_K2_SHIFT 20 + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RX_PAUSE_EN_O_K2 (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RX_PAUSE_EN_O_K2_SHIFT 21 + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_FC_FEC_EN_O_K2 (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_FC_FEC_EN_O_K2_SHIFT 22 + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RS_FEC_EN_O_K2 (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RS_FEC_EN_O_K2_SHIFT 23 + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_EEE_EN_O_K2 (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output. + #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_EEE_EN_O_K2_SHIFT 24 +#define NWS_REG_HSS1_CONTROL1A_E5 0x700020UL //Access:RW DataWidth:0x6 // Multi Field Register. + #define NWS_REG_HSS1_CONTROL1A_HSS1VCOSELA_E5 (0x1<<0) // Frequency Range Control + #define NWS_REG_HSS1_CONTROL1A_HSS1VCOSELA_E5_SHIFT 0 + #define NWS_REG_HSS1_CONTROL1A_HSS1RESYNCA_E5 (0x1<<1) // Core Resync + #define NWS_REG_HSS1_CONTROL1A_HSS1RESYNCA_E5_SHIFT 1 + #define NWS_REG_HSS1_CONTROL1A_HSS1VREGBYPA_E5 (0x1<<2) // HS PLLp Voltage Regulator Bypass + #define NWS_REG_HSS1_CONTROL1A_HSS1VREGBYPA_E5_SHIFT 2 + #define NWS_REG_HSS1_CONTROL1A_HSS1PDWNPLLA_E5 (0x1<<3) // HS PLLp Power Down + #define NWS_REG_HSS1_CONTROL1A_HSS1PDWNPLLA_E5_SHIFT 3 + #define NWS_REG_HSS1_CONTROL1A_HSS1PLLFASTCALA_E5 (0x1<<4) // HS PLLp Fast Calibration. + #define NWS_REG_HSS1_CONTROL1A_HSS1PLLFASTCALA_E5_SHIFT 4 + #define NWS_REG_HSS1_CONTROL1A_HSS1REFCLKVALIDA_E5 (0x1<<5) // HS PLLp ref clk valid. + #define NWS_REG_HSS1_CONTROL1A_HSS1REFCLKVALIDA_E5_SHIFT 5 +#define NWS_REG_LN1_CNTL_K2 0x700020UL //Access:RW DataWidth:0xa // Multi Field Register. + #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_WIDTH_K2 (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved + #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_WIDTH_K2_SHIFT 0 + #define NWS_REG_LN1_CNTL_LN1_CTRL_RXPOLARITY_K2 (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion. + #define NWS_REG_LN1_CNTL_LN1_CTRL_RXPOLARITY_K2_SHIFT 3 + #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_EN_K2 (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register). + #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_EN_K2_SHIFT 4 + #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_VALUE_K2 (0x1<<5) // Informs the PHY that the received signal was lost. + #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_VALUE_K2_SHIFT 5 + #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_RATE_I_K2 (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved + #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_RATE_I_K2_SHIFT 8 +#define NWS_REG_HSS1_CONTROLB_E5 0x700024UL //Access:RW DataWidth:0x1b // Multi Field Register. + #define NWS_REG_HSS1_CONTROLB_HSS1DIVSELB_E5 (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441 + #define NWS_REG_HSS1_CONTROLB_HSS1DIVSELB_E5_SHIFT 0 + #define NWS_REG_HSS1_CONTROLB_HSS1REFDIVB_E5 (0xf<<9) // Bandgap Refclock Divider Ratio + #define NWS_REG_HSS1_CONTROLB_HSS1REFDIVB_E5_SHIFT 9 + #define NWS_REG_HSS1_CONTROLB_HSS1PLLCONFIGB_E5 (0x3fff<<13) // HS PLLp Configuration and Tuning Bits + #define NWS_REG_HSS1_CONTROLB_HSS1PLLCONFIGB_E5_SHIFT 13 +#define NWS_REG_LN1_STATUS_K2 0x700024UL //Access:R DataWidth:0x5 // Multi Field Register. + #define NWS_REG_LN1_STATUS_LN1_STAT_OK_K2 (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data. + #define NWS_REG_LN1_STATUS_LN1_STAT_OK_K2_SHIFT 0 + #define NWS_REG_LN1_STATUS_LN1_STAT_RXVALID_K2 (0x1<<1) // 0x0 - data on ln1_rxdata_o is invalid. 0x1 - data on the active bits of ln1_rxdata_o is valid. + #define NWS_REG_LN1_STATUS_LN1_STAT_RXVALID_K2_SHIFT 1 + #define NWS_REG_LN1_STATUS_LN1_STAT_RUNLEN_ERR_K2 (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold. + #define NWS_REG_LN1_STATUS_LN1_STAT_RUNLEN_ERR_K2_SHIFT 2 + #define NWS_REG_LN1_STATUS_LN1_STAT_LOS_K2 (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. 0x1 - No Signal detected on ln1_rxp_i / ln1_rxm_i pins. + #define NWS_REG_LN1_STATUS_LN1_STAT_LOS_K2_SHIFT 3 + #define NWS_REG_LN1_STATUS_LN1_STAT_LOS_DEGLITCH_K2 (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. 0x1 - No Signal detected on ln1_rxp_i / ln1_rxm_i pins. + #define NWS_REG_LN1_STATUS_LN1_STAT_LOS_DEGLITCH_K2_SHIFT 4 +#define NWS_REG_HSS1_CONTROL1B_E5 0x700028UL //Access:RW DataWidth:0x6 // Multi Field Register. + #define NWS_REG_HSS1_CONTROL1B_HSS1VCOSELB_E5 (0x1<<0) // Frequency Range Control + #define NWS_REG_HSS1_CONTROL1B_HSS1VCOSELB_E5_SHIFT 0 + #define NWS_REG_HSS1_CONTROL1B_HSS1RESYNCB_E5 (0x1<<1) // Core Resync + #define NWS_REG_HSS1_CONTROL1B_HSS1RESYNCB_E5_SHIFT 1 + #define NWS_REG_HSS1_CONTROL1B_HSS1VREGBYPB_E5 (0x1<<2) // HS PLLp Voltage Regulator Bypass + #define NWS_REG_HSS1_CONTROL1B_HSS1VREGBYPB_E5_SHIFT 2 + #define NWS_REG_HSS1_CONTROL1B_HSS1PDWNPLLB_E5 (0x1<<3) // HS PLLp Power Down + #define NWS_REG_HSS1_CONTROL1B_HSS1PDWNPLLB_E5_SHIFT 3 + #define NWS_REG_HSS1_CONTROL1B_HSS1PLLFASTCALB_E5 (0x1<<4) // HS PLLp Fast Calibration. + #define NWS_REG_HSS1_CONTROL1B_HSS1PLLFASTCALB_E5_SHIFT 4 + #define NWS_REG_HSS1_CONTROL1B_HSS1REFCLKVALIDB_E5 (0x1<<5) // HS PLLp ref clk valid. + #define NWS_REG_HSS1_CONTROL1B_HSS1REFCLKVALIDB_E5_SHIFT 5 +#define NWS_REG_LN1_AN_LINK_INPUTS_K2 0x700028UL //Access:RW DataWidth:0x9 // Multi Field Register. + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_CR2_I_K2 (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_CR2_I_K2_SHIFT 0 + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_KR2_I_K2 (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_KR2_I_K2_SHIFT 1 + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_CR4_I_K2 (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_CR4_I_K2_SHIFT 2 + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_KR4_I_K2_SHIFT 3 + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_CR_I_K2 (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_CR_I_K2_SHIFT 4 + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_GR_I_K2 (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_GR_I_K2_SHIFT 5 + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_KR_I_K2 (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_KR_I_K2_SHIFT 6 + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_10G_KR_I_K2 (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_10G_KR_I_K2_SHIFT 7 + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_1G_KX_I_K2 (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_1G_KX_I_K2_SHIFT 8 +#define NWS_REG_HSS1_STATUS_E5 0x70002cUL //Access:R DataWidth:0x5 // Multi Field Register. + #define NWS_REG_HSS1_STATUS_HSS1PLLLOCKA_E5 (0x1<<0) // 0x0 - Unlocked 0x1 - Locked + #define NWS_REG_HSS1_STATUS_HSS1PLLLOCKA_E5_SHIFT 0 + #define NWS_REG_HSS1_STATUS_HSS1PLLLOCKB_E5 (0x1<<1) // 0x0 - Unlocked 0x1 - Locked + #define NWS_REG_HSS1_STATUS_HSS1PLLLOCKB_E5_SHIFT 1 + #define NWS_REG_HSS1_STATUS_HSS1PRTREADYA_E5 (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after reset sequence and offset calibration) + #define NWS_REG_HSS1_STATUS_HSS1PRTREADYA_E5_SHIFT 2 + #define NWS_REG_HSS1_STATUS_HSS1PRTREADYB_E5 (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after reset sequence and offset calibration) + #define NWS_REG_HSS1_STATUS_HSS1PRTREADYB_E5_SHIFT 3 + #define NWS_REG_HSS1_STATUS_HSS1EYEQUALITY_E5 (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX links in the core. 0x1 - Active. New status information is available for at least one RX in the core. When active, register 0x1E for each RX link can be read to determine updated status + #define NWS_REG_HSS1_STATUS_HSS1EYEQUALITY_E5_SHIFT 4 +#define NWS_REG_LN1_AN_LINK_OUTPUTS_K2 0x70002cUL //Access:R DataWidth:0x19 // Multi Field Register. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_CR2_O_K2 (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_CR2_O_K2_SHIFT 0 + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_KR2_O_K2 (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_KR2_O_K2_SHIFT 2 + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_CR4_O_K2 (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_CR4_O_K2_SHIFT 4 + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_KR4_O_K2 (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_KR4_O_K2_SHIFT 6 + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_CR_O_K2 (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_CR_O_K2_SHIFT 8 + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_GR_O_K2 (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_GR_O_K2_SHIFT 10 + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_KR_O_K2 (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_KR_O_K2_SHIFT 12 + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_10G_KR_O_K2 (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_10G_KR_O_K2_SHIFT 14 + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_1G_KX_O_K2 (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_1G_KX_O_K2_SHIFT 16 + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_STAT_LT_SIGDET_O_K2 (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_STAT_LT_SIGDET_O_K2_SHIFT 18 + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_DME_OP_O_K2 (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_DME_OP_O_K2_SHIFT 19 + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_TX_PAUSE_EN_O_K2 (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_TX_PAUSE_EN_O_K2_SHIFT 20 + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RX_PAUSE_EN_O_K2 (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RX_PAUSE_EN_O_K2_SHIFT 21 + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_FC_FEC_EN_O_K2 (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_FC_FEC_EN_O_K2_SHIFT 22 + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RS_FEC_EN_O_K2 (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RS_FEC_EN_O_K2_SHIFT 23 + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_EEE_EN_O_K2 (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output. + #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_EEE_EN_O_K2_SHIFT 24 +#define NWS_REG_HSS2_CONTROL_COMMON_E5 0x700030UL //Access:RW DataWidth:0x6 // Multi Field Register. + #define NWS_REG_HSS2_CONTROL_COMMON_HSS2RESET_E5 (0x1<<0) // HSS Core Reset. Asynchronous reset input signal. This signal must be asserted for a minimum of 170 ns (see HSSRESET on page 48). This signal is sampled within the core and initiates a complete reset sequence of all core functions, including HS PLL calibration and lock. When this signal is deasserted, the internal reset and TX resync sequence is initiated. 0 Normal Operation. 1 Reset. This reset signal is level sensitive, active high within the logic. Its falling edge initiates the required internal reset sequence that initializes the core. + #define NWS_REG_HSS2_CONTROL_COMMON_HSS2RESET_E5_SHIFT 0 + #define NWS_REG_HSS2_CONTROL_COMMON_HSS2RXACMODE_E5 (0x1<<1) // Receiver AC-coupling Mode Selector. Sets the receiver termination. + #define NWS_REG_HSS2_CONTROL_COMMON_HSS2RXACMODE_E5_SHIFT 1 + #define NWS_REG_HSS2_CONTROL_COMMON_HSS2PORPWREN_E5 (0x1<<2) // Power-On-Reset Power Enable. When low, this input powers down the TX and RX analog circuits. It can be used to manage the analog supply currents to a predictable low level before the assertion of HSSRESET. If used, it must come from circuits that can hold it low, without glitching, from the time VDD is ramped up until after HSSRESET is asserted high. + #define NWS_REG_HSS2_CONTROL_COMMON_HSS2PORPWREN_E5_SHIFT 2 + #define NWS_REG_HSS2_CONTROL_COMMON_HSS2RECCALA_E5 (0x1<<3) // Unknown signal, not in users guide + #define NWS_REG_HSS2_CONTROL_COMMON_HSS2RECCALA_E5_SHIFT 3 + #define NWS_REG_HSS2_CONTROL_COMMON_HSS2RECCALB_E5 (0x1<<4) // Unknown signal, not in users guide + #define NWS_REG_HSS2_CONTROL_COMMON_HSS2RECCALB_E5_SHIFT 4 + #define NWS_REG_HSS2_CONTROL_COMMON_HSS2NWS_RBC_CLK_SEL_E5 (0x1<<5) // Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pllA (1G and 10G) (default) + #define NWS_REG_HSS2_CONTROL_COMMON_HSS2NWS_RBC_CLK_SEL_E5_SHIFT 5 +#define NWS_REG_LN2_CNTL_K2 0x700030UL //Access:RW DataWidth:0xa // Multi Field Register. + #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_WIDTH_K2 (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved + #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_WIDTH_K2_SHIFT 0 + #define NWS_REG_LN2_CNTL_LN2_CTRL_RXPOLARITY_K2 (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion. + #define NWS_REG_LN2_CNTL_LN2_CTRL_RXPOLARITY_K2_SHIFT 3 + #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_EN_K2 (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register). + #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_EN_K2_SHIFT 4 + #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_VALUE_K2 (0x1<<5) // Informs the PHY that the received signal was lost. + #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_VALUE_K2_SHIFT 5 + #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_RATE_I_K2 (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved + #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_RATE_I_K2_SHIFT 8 +#define NWS_REG_HSS2_CONTROLA_E5 0x700034UL //Access:RW DataWidth:0x1b // Multi Field Register. + #define NWS_REG_HSS2_CONTROLA_HSS2DIVSELA_E5 (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88 + #define NWS_REG_HSS2_CONTROLA_HSS2DIVSELA_E5_SHIFT 0 + #define NWS_REG_HSS2_CONTROLA_HSS2REFDIVA_E5 (0xf<<9) // Bandgap Refclock Divider Ratio + #define NWS_REG_HSS2_CONTROLA_HSS2REFDIVA_E5_SHIFT 9 + #define NWS_REG_HSS2_CONTROLA_HSS2PLLCONFIGA_E5 (0x3fff<<13) // HS PLLp Configuration and Tuning Bits + #define NWS_REG_HSS2_CONTROLA_HSS2PLLCONFIGA_E5_SHIFT 13 +#define NWS_REG_LN2_STATUS_K2 0x700034UL //Access:R DataWidth:0x5 // Multi Field Register. + #define NWS_REG_LN2_STATUS_LN2_STAT_OK_K2 (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data. + #define NWS_REG_LN2_STATUS_LN2_STAT_OK_K2_SHIFT 0 + #define NWS_REG_LN2_STATUS_LN2_STAT_RXVALID_K2 (0x1<<1) // 0x0 - data on ln2_rxdata_o is invalid. 0x1 - data on the active bits of ln2_rxdata_o is valid. + #define NWS_REG_LN2_STATUS_LN2_STAT_RXVALID_K2_SHIFT 1 + #define NWS_REG_LN2_STATUS_LN2_STAT_RUNLEN_ERR_K2 (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold. + #define NWS_REG_LN2_STATUS_LN2_STAT_RUNLEN_ERR_K2_SHIFT 2 + #define NWS_REG_LN2_STATUS_LN2_STAT_LOS_K2 (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. 0x1 - No Signal detected on ln2_rxp_i / ln2_rxm_i pins. + #define NWS_REG_LN2_STATUS_LN2_STAT_LOS_K2_SHIFT 3 + #define NWS_REG_LN2_STATUS_LN2_STAT_LOS_DEGLITCH_K2 (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. 0x1 - No Signal detected on ln2_rxp_i / ln2_rxm_i pins. + #define NWS_REG_LN2_STATUS_LN2_STAT_LOS_DEGLITCH_K2_SHIFT 4 +#define NWS_REG_HSS2_CONTROL1A_E5 0x700038UL //Access:RW DataWidth:0x6 // Multi Field Register. + #define NWS_REG_HSS2_CONTROL1A_HSS2VCOSELA_E5 (0x1<<0) // Frequency Range Control + #define NWS_REG_HSS2_CONTROL1A_HSS2VCOSELA_E5_SHIFT 0 + #define NWS_REG_HSS2_CONTROL1A_HSS2RESYNCA_E5 (0x1<<1) // Core Resync + #define NWS_REG_HSS2_CONTROL1A_HSS2RESYNCA_E5_SHIFT 1 + #define NWS_REG_HSS2_CONTROL1A_HSS2VREGBYPA_E5 (0x1<<2) // HS PLLp Voltage Regulator Bypass + #define NWS_REG_HSS2_CONTROL1A_HSS2VREGBYPA_E5_SHIFT 2 + #define NWS_REG_HSS2_CONTROL1A_HSS2PDWNPLLA_E5 (0x1<<3) // HS PLLp Power Down + #define NWS_REG_HSS2_CONTROL1A_HSS2PDWNPLLA_E5_SHIFT 3 + #define NWS_REG_HSS2_CONTROL1A_HSS2PLLFASTCALA_E5 (0x1<<4) // HS PLLp Fast Calibration. + #define NWS_REG_HSS2_CONTROL1A_HSS2PLLFASTCALA_E5_SHIFT 4 + #define NWS_REG_HSS2_CONTROL1A_HSS2REFCLKVALIDA_E5 (0x1<<5) // HS PLLp ref clk valid. + #define NWS_REG_HSS2_CONTROL1A_HSS2REFCLKVALIDA_E5_SHIFT 5 +#define NWS_REG_LN2_AN_LINK_INPUTS_K2 0x700038UL //Access:RW DataWidth:0x9 // Multi Field Register. + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_CR2_I_K2 (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_CR2_I_K2_SHIFT 0 + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_KR2_I_K2 (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_KR2_I_K2_SHIFT 1 + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_CR4_I_K2 (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_CR4_I_K2_SHIFT 2 + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_KR4_I_K2_SHIFT 3 + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_CR_I_K2 (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_CR_I_K2_SHIFT 4 + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_GR_I_K2 (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_GR_I_K2_SHIFT 5 + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_KR_I_K2 (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_KR_I_K2_SHIFT 6 + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_10G_KR_I_K2 (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_10G_KR_I_K2_SHIFT 7 + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_1G_KX_I_K2 (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_1G_KX_I_K2_SHIFT 8 +#define NWS_REG_HSS2_CONTROLB_E5 0x70003cUL //Access:RW DataWidth:0x1b // Multi Field Register. + #define NWS_REG_HSS2_CONTROLB_HSS2DIVSELB_E5 (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441 + #define NWS_REG_HSS2_CONTROLB_HSS2DIVSELB_E5_SHIFT 0 + #define NWS_REG_HSS2_CONTROLB_HSS2REFDIVB_E5 (0xf<<9) // Bandgap Refclock Divider Ratio + #define NWS_REG_HSS2_CONTROLB_HSS2REFDIVB_E5_SHIFT 9 + #define NWS_REG_HSS2_CONTROLB_HSS2PLLCONFIGB_E5 (0x3fff<<13) // HS PLLp Configuration and Tuning Bits + #define NWS_REG_HSS2_CONTROLB_HSS2PLLCONFIGB_E5_SHIFT 13 +#define NWS_REG_LN2_AN_LINK_OUTPUTS_K2 0x70003cUL //Access:R DataWidth:0x19 // Multi Field Register. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_CR2_O_K2 (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_CR2_O_K2_SHIFT 0 + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_KR2_O_K2 (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_KR2_O_K2_SHIFT 2 + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_CR4_O_K2 (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_CR4_O_K2_SHIFT 4 + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_KR4_O_K2 (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_KR4_O_K2_SHIFT 6 + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_CR_O_K2 (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_CR_O_K2_SHIFT 8 + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_GR_O_K2 (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_GR_O_K2_SHIFT 10 + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_KR_O_K2 (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_KR_O_K2_SHIFT 12 + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_10G_KR_O_K2 (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_10G_KR_O_K2_SHIFT 14 + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_1G_KX_O_K2 (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_1G_KX_O_K2_SHIFT 16 + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_STAT_LT_SIGDET_O_K2 (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_STAT_LT_SIGDET_O_K2_SHIFT 18 + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_DME_OP_O_K2 (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_DME_OP_O_K2_SHIFT 19 + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_TX_PAUSE_EN_O_K2 (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_TX_PAUSE_EN_O_K2_SHIFT 20 + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RX_PAUSE_EN_O_K2 (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RX_PAUSE_EN_O_K2_SHIFT 21 + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_FC_FEC_EN_O_K2 (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_FC_FEC_EN_O_K2_SHIFT 22 + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RS_FEC_EN_O_K2 (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RS_FEC_EN_O_K2_SHIFT 23 + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_EEE_EN_O_K2 (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output. + #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_EEE_EN_O_K2_SHIFT 24 +#define NWS_REG_HSS2_CONTROL1B_E5 0x700040UL //Access:RW DataWidth:0x6 // Multi Field Register. + #define NWS_REG_HSS2_CONTROL1B_HSS2VCOSELB_E5 (0x1<<0) // Frequency Range Control + #define NWS_REG_HSS2_CONTROL1B_HSS2VCOSELB_E5_SHIFT 0 + #define NWS_REG_HSS2_CONTROL1B_HSS2RESYNCB_E5 (0x1<<1) // Core Resync + #define NWS_REG_HSS2_CONTROL1B_HSS2RESYNCB_E5_SHIFT 1 + #define NWS_REG_HSS2_CONTROL1B_HSS2VREGBYPB_E5 (0x1<<2) // HS PLLp Voltage Regulator Bypass + #define NWS_REG_HSS2_CONTROL1B_HSS2VREGBYPB_E5_SHIFT 2 + #define NWS_REG_HSS2_CONTROL1B_HSS2PDWNPLLB_E5 (0x1<<3) // HS PLLp Power Down + #define NWS_REG_HSS2_CONTROL1B_HSS2PDWNPLLB_E5_SHIFT 3 + #define NWS_REG_HSS2_CONTROL1B_HSS2PLLFASTCALB_E5 (0x1<<4) // HS PLLp Fast Calibration. + #define NWS_REG_HSS2_CONTROL1B_HSS2PLLFASTCALB_E5_SHIFT 4 + #define NWS_REG_HSS2_CONTROL1B_HSS2REFCLKVALIDB_E5 (0x1<<5) // HS PLLp ref clk valid. + #define NWS_REG_HSS2_CONTROL1B_HSS2REFCLKVALIDB_E5_SHIFT 5 +#define NWS_REG_LN3_CNTL_K2 0x700040UL //Access:RW DataWidth:0xa // Multi Field Register. + #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_WIDTH_K2 (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved + #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_WIDTH_K2_SHIFT 0 + #define NWS_REG_LN3_CNTL_LN3_CTRL_RXPOLARITY_K2 (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion. + #define NWS_REG_LN3_CNTL_LN3_CTRL_RXPOLARITY_K2_SHIFT 3 + #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_EN_K2 (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register). + #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_EN_K2_SHIFT 4 + #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_VALUE_K2 (0x1<<5) // Informs the PHY that the received signal was lost. + #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_VALUE_K2_SHIFT 5 + #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_RATE_I_K2 (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved + #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_RATE_I_K2_SHIFT 8 +#define NWS_REG_HSS2_STATUS_E5 0x700044UL //Access:R DataWidth:0x5 // Multi Field Register. + #define NWS_REG_HSS2_STATUS_HSS2PLLLOCKA_E5 (0x1<<0) // 0x0 - Unlocked 0x1 - Locked + #define NWS_REG_HSS2_STATUS_HSS2PLLLOCKA_E5_SHIFT 0 + #define NWS_REG_HSS2_STATUS_HSS2PLLLOCKB_E5 (0x1<<1) // 0x0 - Unlocked 0x1 - Locked + #define NWS_REG_HSS2_STATUS_HSS2PLLLOCKB_E5_SHIFT 1 + #define NWS_REG_HSS2_STATUS_HSS2PRTREADYA_E5 (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after reset sequence and offset calibration) + #define NWS_REG_HSS2_STATUS_HSS2PRTREADYA_E5_SHIFT 2 + #define NWS_REG_HSS2_STATUS_HSS2PRTREADYB_E5 (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after reset sequence and offset calibration) + #define NWS_REG_HSS2_STATUS_HSS2PRTREADYB_E5_SHIFT 3 + #define NWS_REG_HSS2_STATUS_HSS2EYEQUALITY_E5 (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX links in the core. 0x1 - Active. New status information is available for at least one RX in the core. When active, register 0x1E for each RX link can be read to determine updated status + #define NWS_REG_HSS2_STATUS_HSS2EYEQUALITY_E5_SHIFT 4 +#define NWS_REG_LN3_STATUS_K2 0x700044UL //Access:R DataWidth:0x5 // Multi Field Register. + #define NWS_REG_LN3_STATUS_LN3_STAT_OK_K2 (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data. + #define NWS_REG_LN3_STATUS_LN3_STAT_OK_K2_SHIFT 0 + #define NWS_REG_LN3_STATUS_LN3_STAT_RXVALID_K2 (0x1<<1) // 0x0 - data on ln3_rxdata_o is invalid. 0x1 - data on the active bits of ln3_rxdata_o is valid. + #define NWS_REG_LN3_STATUS_LN3_STAT_RXVALID_K2_SHIFT 1 + #define NWS_REG_LN3_STATUS_LN3_STAT_RUNLEN_ERR_K2 (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold. + #define NWS_REG_LN3_STATUS_LN3_STAT_RUNLEN_ERR_K2_SHIFT 2 + #define NWS_REG_LN3_STATUS_LN3_STAT_LOS_K2 (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. 0x1 - No Signal detected on ln3_rxp_i / ln3_rxm_i pins. + #define NWS_REG_LN3_STATUS_LN3_STAT_LOS_K2_SHIFT 3 + #define NWS_REG_LN3_STATUS_LN3_STAT_LOS_DEGLITCH_K2 (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. 0x1 - No Signal detected on ln3_rxp_i / ln3_rxm_i pins. + #define NWS_REG_LN3_STATUS_LN3_STAT_LOS_DEGLITCH_K2_SHIFT 4 +#define NWS_REG_HSS3_CONTROL_COMMON_E5 0x700048UL //Access:RW DataWidth:0x6 // Multi Field Register. + #define NWS_REG_HSS3_CONTROL_COMMON_HSS3RESET_E5 (0x1<<0) // HSS Core Reset. Asynchronous reset input signal. This signal must be asserted for a minimum of 170 ns (see HSSRESET on page 48). This signal is sampled within the core and initiates a complete reset sequence of all core functions, including HS PLL calibration and lock. When this signal is deasserted, the internal reset and TX resync sequence is initiated. 0 Normal Operation. 1 Reset. This reset signal is level sensitive, active high within the logic. Its falling edge initiates the required internal reset sequence that initializes the core. + #define NWS_REG_HSS3_CONTROL_COMMON_HSS3RESET_E5_SHIFT 0 + #define NWS_REG_HSS3_CONTROL_COMMON_HSS3RXACMODE_E5 (0x1<<1) // Receiver AC-coupling Mode Selector. Sets the receiver termination. + #define NWS_REG_HSS3_CONTROL_COMMON_HSS3RXACMODE_E5_SHIFT 1 + #define NWS_REG_HSS3_CONTROL_COMMON_HSS3PORPWREN_E5 (0x1<<2) // Power-On-Reset Power Enable. When low, this input powers down the TX and RX analog circuits. It can be used to manage the analog supply currents to a predictable low level before the assertion of HSSRESET. If used, it must come from circuits that can hold it low, without glitching, from the time VDD is ramped up until after HSSRESET is asserted high. + #define NWS_REG_HSS3_CONTROL_COMMON_HSS3PORPWREN_E5_SHIFT 2 + #define NWS_REG_HSS3_CONTROL_COMMON_HSS3RECCALA_E5 (0x1<<3) // Unknown signal, not in users guide + #define NWS_REG_HSS3_CONTROL_COMMON_HSS3RECCALA_E5_SHIFT 3 + #define NWS_REG_HSS3_CONTROL_COMMON_HSS3RECCALB_E5 (0x1<<4) // Unknown signal, not in users guide + #define NWS_REG_HSS3_CONTROL_COMMON_HSS3RECCALB_E5_SHIFT 4 + #define NWS_REG_HSS3_CONTROL_COMMON_HSS3NWS_RBC_CLK_SEL_E5 (0x1<<5) // Used to select which PLL output to use for this serdes lane 0 - Use pllB (25G and 50G) 1 - Use pllA (1G and 10G) (default) + #define NWS_REG_HSS3_CONTROL_COMMON_HSS3NWS_RBC_CLK_SEL_E5_SHIFT 5 +#define NWS_REG_LN3_AN_LINK_INPUTS_K2 0x700048UL //Access:RW DataWidth:0x9 // Multi Field Register. + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_CR2_I_K2 (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_CR2_I_K2_SHIFT 0 + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_KR2_I_K2 (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_KR2_I_K2_SHIFT 1 + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_CR4_I_K2 (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_CR4_I_K2_SHIFT 2 + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_KR4_I_K2 (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_KR4_I_K2_SHIFT 3 + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_CR_I_K2 (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_CR_I_K2_SHIFT 4 + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_GR_I_K2 (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_GR_I_K2_SHIFT 5 + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_KR_I_K2 (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_KR_I_K2_SHIFT 6 + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_10G_KR_I_K2 (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_10G_KR_I_K2_SHIFT 7 + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_1G_KX_I_K2 (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner + #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_1G_KX_I_K2_SHIFT 8 +#define NWS_REG_HSS3_CONTROLA_E5 0x70004cUL //Access:RW DataWidth:0x1b // Multi Field Register. + #define NWS_REG_HSS3_CONTROLA_HSS3DIVSELA_E5 (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 1G - 106 ??? 10G - 88 + #define NWS_REG_HSS3_CONTROLA_HSS3DIVSELA_E5_SHIFT 0 + #define NWS_REG_HSS3_CONTROLA_HSS3REFDIVA_E5 (0xf<<9) // Bandgap Refclock Divider Ratio + #define NWS_REG_HSS3_CONTROLA_HSS3REFDIVA_E5_SHIFT 9 + #define NWS_REG_HSS3_CONTROLA_HSS3PLLCONFIGA_E5 (0x3fff<<13) // HS PLLp Configuration and Tuning Bits + #define NWS_REG_HSS3_CONTROLA_HSS3PLLCONFIGA_E5_SHIFT 13 +#define NWS_REG_LN3_AN_LINK_OUTPUTS_K2 0x70004cUL //Access:R DataWidth:0x19 // Multi Field Register. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_CR2_O_K2 (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_CR2_O_K2_SHIFT 0 + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_KR2_O_K2 (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_KR2_O_K2_SHIFT 2 + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_CR4_O_K2 (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_CR4_O_K2_SHIFT 4 + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_KR4_O_K2 (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_KR4_O_K2_SHIFT 6 + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_CR_O_K2 (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_CR_O_K2_SHIFT 8 + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_GR_O_K2 (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_GR_O_K2_SHIFT 10 + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_KR_O_K2 (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_KR_O_K2_SHIFT 12 + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_10G_KR_O_K2 (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_10G_KR_O_K2_SHIFT 14 + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_1G_KX_O_K2 (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_1G_KX_O_K2_SHIFT 16 + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_STAT_LT_SIGDET_O_K2 (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_STAT_LT_SIGDET_O_K2_SHIFT 18 + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_DME_OP_O_K2 (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_DME_OP_O_K2_SHIFT 19 + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_TX_PAUSE_EN_O_K2 (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_TX_PAUSE_EN_O_K2_SHIFT 20 + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RX_PAUSE_EN_O_K2 (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RX_PAUSE_EN_O_K2_SHIFT 21 + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_FC_FEC_EN_O_K2 (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_FC_FEC_EN_O_K2_SHIFT 22 + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RS_FEC_EN_O_K2 (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RS_FEC_EN_O_K2_SHIFT 23 + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_EEE_EN_O_K2 (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output. + #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_EEE_EN_O_K2_SHIFT 24 +#define NWS_REG_HSS3_CONTROL1A_E5 0x700050UL //Access:RW DataWidth:0x6 // Multi Field Register. + #define NWS_REG_HSS3_CONTROL1A_HSS3VCOSELA_E5 (0x1<<0) // Frequency Range Control + #define NWS_REG_HSS3_CONTROL1A_HSS3VCOSELA_E5_SHIFT 0 + #define NWS_REG_HSS3_CONTROL1A_HSS3RESYNCA_E5 (0x1<<1) // Core Resync + #define NWS_REG_HSS3_CONTROL1A_HSS3RESYNCA_E5_SHIFT 1 + #define NWS_REG_HSS3_CONTROL1A_HSS3VREGBYPA_E5 (0x1<<2) // HS PLLp Voltage Regulator Bypass + #define NWS_REG_HSS3_CONTROL1A_HSS3VREGBYPA_E5_SHIFT 2 + #define NWS_REG_HSS3_CONTROL1A_HSS3PDWNPLLA_E5 (0x1<<3) // HS PLLp Power Down + #define NWS_REG_HSS3_CONTROL1A_HSS3PDWNPLLA_E5_SHIFT 3 + #define NWS_REG_HSS3_CONTROL1A_HSS3PLLFASTCALA_E5 (0x1<<4) // HS PLLp Fast Calibration. + #define NWS_REG_HSS3_CONTROL1A_HSS3PLLFASTCALA_E5_SHIFT 4 + #define NWS_REG_HSS3_CONTROL1A_HSS3REFCLKVALIDA_E5 (0x1<<5) // HS PLLp ref clk valid. + #define NWS_REG_HSS3_CONTROL1A_HSS3REFCLKVALIDA_E5_SHIFT 5 +#define NWS_REG_HSS3_CONTROLB_E5 0x700054UL //Access:RW DataWidth:0x1b // Multi Field Register. + #define NWS_REG_HSS3_CONTROLB_HSS3DIVSELB_E5 (0x1ff<<0) // HS PLLp Feedback Divisor Ratio 25G - 471 50G - 441 + #define NWS_REG_HSS3_CONTROLB_HSS3DIVSELB_E5_SHIFT 0 + #define NWS_REG_HSS3_CONTROLB_HSS3REFDIVB_E5 (0xf<<9) // Bandgap Refclock Divider Ratio + #define NWS_REG_HSS3_CONTROLB_HSS3REFDIVB_E5_SHIFT 9 + #define NWS_REG_HSS3_CONTROLB_HSS3PLLCONFIGB_E5 (0x3fff<<13) // HS PLLp Configuration and Tuning Bits + #define NWS_REG_HSS3_CONTROLB_HSS3PLLCONFIGB_E5_SHIFT 13 +#define NWS_REG_HSS3_CONTROL1B_E5 0x700058UL //Access:RW DataWidth:0x6 // Multi Field Register. + #define NWS_REG_HSS3_CONTROL1B_HSS3VCOSELB_E5 (0x1<<0) // Frequency Range Control + #define NWS_REG_HSS3_CONTROL1B_HSS3VCOSELB_E5_SHIFT 0 + #define NWS_REG_HSS3_CONTROL1B_HSS3RESYNCB_E5 (0x1<<1) // Core Resync + #define NWS_REG_HSS3_CONTROL1B_HSS3RESYNCB_E5_SHIFT 1 + #define NWS_REG_HSS3_CONTROL1B_HSS3VREGBYPB_E5 (0x1<<2) // HS PLLp Voltage Regulator Bypass + #define NWS_REG_HSS3_CONTROL1B_HSS3VREGBYPB_E5_SHIFT 2 + #define NWS_REG_HSS3_CONTROL1B_HSS3PDWNPLLB_E5 (0x1<<3) // HS PLLp Power Down + #define NWS_REG_HSS3_CONTROL1B_HSS3PDWNPLLB_E5_SHIFT 3 + #define NWS_REG_HSS3_CONTROL1B_HSS3PLLFASTCALB_E5 (0x1<<4) // HS PLLp Fast Calibration. + #define NWS_REG_HSS3_CONTROL1B_HSS3PLLFASTCALB_E5_SHIFT 4 + #define NWS_REG_HSS3_CONTROL1B_HSS3REFCLKVALIDB_E5 (0x1<<5) // HS PLLp ref clk valid. + #define NWS_REG_HSS3_CONTROL1B_HSS3REFCLKVALIDB_E5_SHIFT 5 +#define NWS_REG_HSS3_STATUS_E5 0x70005cUL //Access:R DataWidth:0x5 // Multi Field Register. + #define NWS_REG_HSS3_STATUS_HSS3PLLLOCKA_E5 (0x1<<0) // 0x0 - Unlocked 0x1 - Locked + #define NWS_REG_HSS3_STATUS_HSS3PLLLOCKA_E5_SHIFT 0 + #define NWS_REG_HSS3_STATUS_HSS3PLLLOCKB_E5 (0x1<<1) // 0x0 - Unlocked 0x1 - Locked + #define NWS_REG_HSS3_STATUS_HSS3PLLLOCKB_E5_SHIFT 1 + #define NWS_REG_HSS3_STATUS_HSS3PRTREADYA_E5 (0x1<<2) // 0x0 - Not Ready 0x1 - Ready (after reset sequence and offset calibration) + #define NWS_REG_HSS3_STATUS_HSS3PRTREADYA_E5_SHIFT 2 + #define NWS_REG_HSS3_STATUS_HSS3PRTREADYB_E5 (0x1<<3) // 0x0 - Not Ready 0x1 - Ready (after reset sequence and offset calibration) + #define NWS_REG_HSS3_STATUS_HSS3PRTREADYB_E5_SHIFT 3 + #define NWS_REG_HSS3_STATUS_HSS3EYEQUALITY_E5 (0x1<<4) // 0x0 - Inactive. No new status information is available for any RX links in the core. 0x1 - Active. New status information is available for at least one RX in the core. When active, register 0x1E for each RX link can be read to determine updated status + #define NWS_REG_HSS3_STATUS_HSS3EYEQUALITY_E5_SHIFT 4 +#define NWS_REG_RX0_CONTROL_E5 0x700060UL //Access:RW DataWidth:0x8 // Multi Field Register. + #define NWS_REG_RX0_CONTROL_RX0CONFIGSEL_E5 (0x3<<0) // Receiver Port Configuration Selection. Selects one of four possible receiver preconfigurations if bit 10 of Receiver Configuration Mode Register is set to ‘1’. Otherwise, these pins are ignored. 00 Preconfiguration 0 selected. 01 Preconfiguration 1 selected. 10 Preconfiguration 2 selected. 11 Preconfiguration 3 selected. Note: When changing between preconfigurations that require both pins to change (such as from ‘00’ to ‘11’), the pins must change state within 500 ps of each other. + #define NWS_REG_RX0_CONTROL_RX0CONFIGSEL_E5_SHIFT 0 + #define NWS_REG_RX0_CONTROL_RX0DATASYNC_E5 (0x1<<2) // Data Synchronization Control. Use for byte alignment. Each rising edge of this signal causes one bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustment. This signal must maintain a level for a minimum of one C16 cycle to be recognized. 0 Normal. 1 Discard one bit. Note: This pin must be held ‘0’ until HSSPRTREADY[A,B] = ‘1’ during a reset sequence or calibrations are invalid. In simulation, this pin must always be driven to a valid value (1 or 0, not X) or the RXxDCLK output is an X. In real hardware, this value can be unknown. However, it is always a valid 1 or 0 and the RXxDCLK is valid. + #define NWS_REG_RX0_CONTROL_RX0DATASYNC_E5_SHIFT 2 + #define NWS_REG_RX0_CONTROL_RX0EARLYIN_E5 (0x1<<3) // Early Input. External EARLY input to internal rotator control logic. Based on the setting of the Internal/External Early/Late Selection Control in the Receiver Phase Rotator Control Register, bit 4, each rising edge of this input moves the rotator control logic down by one step. Early information entered this way makes use of the internal filter state machine and flywheel. 0 Normal. 1 Step rotator down. This signal must maintain a level for a minimum of one C16 cycle to be recognized. Note: Do not use this until the core has completed initial calibration. + #define NWS_REG_RX0_CONTROL_RX0EARLYIN_E5_SHIFT 3 + #define NWS_REG_RX0_CONTROL_RX0LATEIN_E5 (0x1<<4) // Late Input. External LATE input to internal rotator control logic. Based on the setting of the Internal/External Early/Late Selection Control in Receiver Phase Rotator Control Register, bit 4, each rising edge of this input moves the rotator control logic up by one step. Late information entered this way makes use of the internal filter state machine and flywheel. 0 Normal. 1 Step rotator up. This signal must maintain a level for a minimum of one C16 cycle to be recognized. Note: Do not use this until the core has completed initial calibration + #define NWS_REG_RX0_CONTROL_RX0LATEIN_E5_SHIFT 4 + #define NWS_REG_RX0_CONTROL_RX0PHSDNIN_E5 (0x1<<5) // Phase Down Input. External adjustment control to retard the phase rotators. Each rising edge of this signal causes one incremental adjustment (retard) of the phase rotators. RXxPHSLOCK must be ‘1’ to enable this. This signal must maintain a level for a minimum of one C16 cycle to be recognized. 0 Normal. 1 Retard phase rotator 1 increment. + #define NWS_REG_RX0_CONTROL_RX0PHSDNIN_E5_SHIFT 5 + #define NWS_REG_RX0_CONTROL_RX0PHSUPIN_E5 (0x1<<6) // Phase Up Input. External adjustment control to advance the phase rotators. Each rising edge of this signal causes one incremental adjustment (advance) of the phase rotators. RXxPHSLOCK must be ‘1’ to enable this. This signal must maintain a level for a minimum of one C16 cycle to be recognized. 0 Normal. 1 Advance phase rotator 1 increment + #define NWS_REG_RX0_CONTROL_RX0PHSUPIN_E5_SHIFT 6 + #define NWS_REG_RX0_CONTROL_RX0PHSLOCK_E5 (0x1<<7) // Phase Lock. Enable external adjustment of phase rotator through RXxPHSDNIN and RXxPHSUPIN input signals. 0 Disabled (normal operation). 1 Enabled (external control of phase rotators). Note: Do not set this bit to ‘1’ until the core has completed initial calibration. + #define NWS_REG_RX0_CONTROL_RX0PHSLOCK_E5_SHIFT 7 +#define NWS_REG_RX1_CONTROL_E5 0x700064UL //Access:RW DataWidth:0x8 // Multi Field Register. + #define NWS_REG_RX1_CONTROL_RX1CONFIGSEL_E5 (0x3<<0) // Receiver Port Configuration Selection. Selects one of four possible receiver preconfigurations if bit 10 of Receiver Configuration Mode Register is set to ‘1’. Otherwise, these pins are ignored. 00 Preconfiguration 0 selected. 01 Preconfiguration 1 selected. 10 Preconfiguration 2 selected. 11 Preconfiguration 3 selected. Note: When changing between preconfigurations that require both pins to change (such as from ‘00’ to ‘11’), the pins must change state within 500 ps of each other. + #define NWS_REG_RX1_CONTROL_RX1CONFIGSEL_E5_SHIFT 0 + #define NWS_REG_RX1_CONTROL_RX1DATASYNC_E5 (0x1<<2) // Data Synchronization Control. Use for byte alignment. Each rising edge of this signal causes one bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustment. This signal must maintain a level for a minimum of one C16 cycle to be recognized. 0 Normal. 1 Discard one bit. Note: This pin must be held ‘0’ until HSSPRTREADY[A,B] = ‘1’ during a reset sequence or calibrations are invalid. In simulation, this pin must always be driven to a valid value (1 or 0, not X) or the RXxDCLK output is an X. In real hardware, this value can be unknown. However, it is always a valid 1 or 0 and the RXxDCLK is valid. + #define NWS_REG_RX1_CONTROL_RX1DATASYNC_E5_SHIFT 2 + #define NWS_REG_RX1_CONTROL_RX1EARLYIN_E5 (0x1<<3) // Early Input. External EARLY input to internal rotator control logic. Based on the setting of the Internal/External Early/Late Selection Control in the Receiver Phase Rotator Control Register, bit 4, each rising edge of this input moves the rotator control logic down by one step. Early information entered this way makes use of the internal filter state machine and flywheel. 0 Normal. 1 Step rotator down. This signal must maintain a level for a minimum of one C16 cycle to be recognized. Note: Do not use this until the core has completed initial calibration. + #define NWS_REG_RX1_CONTROL_RX1EARLYIN_E5_SHIFT 3 + #define NWS_REG_RX1_CONTROL_RX1LATEIN_E5 (0x1<<4) // Late Input. External LATE input to internal rotator control logic. Based on the setting of the Internal/External Early/Late Selection Control in Receiver Phase Rotator Control Register, bit 4, each rising edge of this input moves the rotator control logic up by one step. Late information entered this way makes use of the internal filter state machine and flywheel. 0 Normal. 1 Step rotator up. This signal must maintain a level for a minimum of one C16 cycle to be recognized. Note: Do not use this until the core has completed initial calibration + #define NWS_REG_RX1_CONTROL_RX1LATEIN_E5_SHIFT 4 + #define NWS_REG_RX1_CONTROL_RX1PHSDNIN_E5 (0x1<<5) // Phase Down Input. External adjustment control to retard the phase rotators. Each rising edge of this signal causes one incremental adjustment (retard) of the phase rotators. RXxPHSLOCK must be ‘1’ to enable this. This signal must maintain a level for a minimum of one C16 cycle to be recognized. 0 Normal. 1 Retard phase rotator 1 increment. + #define NWS_REG_RX1_CONTROL_RX1PHSDNIN_E5_SHIFT 5 + #define NWS_REG_RX1_CONTROL_RX1PHSUPIN_E5 (0x1<<6) // Phase Up Input. External adjustment control to advance the phase rotators. Each rising edge of this signal causes one incremental adjustment (advance) of the phase rotators. RXxPHSLOCK must be ‘1’ to enable this. This signal must maintain a level for a minimum of one C16 cycle to be recognized. 0 Normal. 1 Advance phase rotator 1 increment + #define NWS_REG_RX1_CONTROL_RX1PHSUPIN_E5_SHIFT 6 + #define NWS_REG_RX1_CONTROL_RX1PHSLOCK_E5 (0x1<<7) // Phase Lock. Enable external adjustment of phase rotator through RXxPHSDNIN and RXxPHSUPIN input signals. 0 Disabled (normal operation). 1 Enabled (external control of phase rotators). Note: Do not set this bit to ‘1’ until the core has completed initial calibration. + #define NWS_REG_RX1_CONTROL_RX1PHSLOCK_E5_SHIFT 7 +#define NWS_REG_RX2_CONTROL_E5 0x700068UL //Access:RW DataWidth:0x8 // Multi Field Register. + #define NWS_REG_RX2_CONTROL_RX2CONFIGSEL_E5 (0x3<<0) // Receiver Port Configuration Selection. Selects one of four possible receiver preconfigurations if bit 10 of Receiver Configuration Mode Register is set to ‘1’. Otherwise, these pins are ignored. 00 Preconfiguration 0 selected. 01 Preconfiguration 1 selected. 10 Preconfiguration 2 selected. 11 Preconfiguration 3 selected. Note: When changing between preconfigurations that require both pins to change (such as from ‘00’ to ‘11’), the pins must change state within 500 ps of each other. + #define NWS_REG_RX2_CONTROL_RX2CONFIGSEL_E5_SHIFT 0 + #define NWS_REG_RX2_CONTROL_RX2DATASYNC_E5 (0x1<<2) // Data Synchronization Control. Use for byte alignment. Each rising edge of this signal causes one bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustment. This signal must maintain a level for a minimum of one C16 cycle to be recognized. 0 Normal. 1 Discard one bit. Note: This pin must be held ‘0’ until HSSPRTREADY[A,B] = ‘1’ during a reset sequence or calibrations are invalid. In simulation, this pin must always be driven to a valid value (1 or 0, not X) or the RXxDCLK output is an X. In real hardware, this value can be unknown. However, it is always a valid 1 or 0 and the RXxDCLK is valid. + #define NWS_REG_RX2_CONTROL_RX2DATASYNC_E5_SHIFT 2 + #define NWS_REG_RX2_CONTROL_RX2EARLYIN_E5 (0x1<<3) // Early Input. External EARLY input to internal rotator control logic. Based on the setting of the Internal/External Early/Late Selection Control in the Receiver Phase Rotator Control Register, bit 4, each rising edge of this input moves the rotator control logic down by one step. Early information entered this way makes use of the internal filter state machine and flywheel. 0 Normal. 1 Step rotator down. This signal must maintain a level for a minimum of one C16 cycle to be recognized. Note: Do not use this until the core has completed initial calibration. + #define NWS_REG_RX2_CONTROL_RX2EARLYIN_E5_SHIFT 3 + #define NWS_REG_RX2_CONTROL_RX2LATEIN_E5 (0x1<<4) // Late Input. External LATE input to internal rotator control logic. Based on the setting of the Internal/External Early/Late Selection Control in Receiver Phase Rotator Control Register, bit 4, each rising edge of this input moves the rotator control logic up by one step. Late information entered this way makes use of the internal filter state machine and flywheel. 0 Normal. 1 Step rotator up. This signal must maintain a level for a minimum of one C16 cycle to be recognized. Note: Do not use this until the core has completed initial calibration + #define NWS_REG_RX2_CONTROL_RX2LATEIN_E5_SHIFT 4 + #define NWS_REG_RX2_CONTROL_RX2PHSDNIN_E5 (0x1<<5) // Phase Down Input. External adjustment control to retard the phase rotators. Each rising edge of this signal causes one incremental adjustment (retard) of the phase rotators. RXxPHSLOCK must be ‘1’ to enable this. This signal must maintain a level for a minimum of one C16 cycle to be recognized. 0 Normal. 1 Retard phase rotator 1 increment. + #define NWS_REG_RX2_CONTROL_RX2PHSDNIN_E5_SHIFT 5 + #define NWS_REG_RX2_CONTROL_RX2PHSUPIN_E5 (0x1<<6) // Phase Up Input. External adjustment control to advance the phase rotators. Each rising edge of this signal causes one incremental adjustment (advance) of the phase rotators. RXxPHSLOCK must be ‘1’ to enable this. This signal must maintain a level for a minimum of one C16 cycle to be recognized. 0 Normal. 1 Advance phase rotator 1 increment + #define NWS_REG_RX2_CONTROL_RX2PHSUPIN_E5_SHIFT 6 + #define NWS_REG_RX2_CONTROL_RX2PHSLOCK_E5 (0x1<<7) // Phase Lock. Enable external adjustment of phase rotator through RXxPHSDNIN and RXxPHSUPIN input signals. 0 Disabled (normal operation). 1 Enabled (external control of phase rotators). Note: Do not set this bit to ‘1’ until the core has completed initial calibration. + #define NWS_REG_RX2_CONTROL_RX2PHSLOCK_E5_SHIFT 7 +#define NWS_REG_RX3_CONTROL_E5 0x70006cUL //Access:RW DataWidth:0x8 // Multi Field Register. + #define NWS_REG_RX3_CONTROL_RX3CONFIGSEL_E5 (0x3<<0) // Receiver Port Configuration Selection. Selects one of four possible receiver preconfigurations if bit 10 of Receiver Configuration Mode Register is set to ‘1’. Otherwise, these pins are ignored. 00 Preconfiguration 0 selected. 01 Preconfiguration 1 selected. 10 Preconfiguration 2 selected. 11 Preconfiguration 3 selected. Note: When changing between preconfigurations that require both pins to change (such as from ‘00’ to ‘11’), the pins must change state within 500 ps of each other. + #define NWS_REG_RX3_CONTROL_RX3CONFIGSEL_E5_SHIFT 0 + #define NWS_REG_RX3_CONTROL_RX3DATASYNC_E5 (0x1<<2) // Data Synchronization Control. Use for byte alignment. Each rising edge of this signal causes one bit to be discarded from the recovered data stream, which results in a 1-bit alignment adjustment. This signal must maintain a level for a minimum of one C16 cycle to be recognized. 0 Normal. 1 Discard one bit. Note: This pin must be held ‘0’ until HSSPRTREADY[A,B] = ‘1’ during a reset sequence or calibrations are invalid. In simulation, this pin must always be driven to a valid value (1 or 0, not X) or the RXxDCLK output is an X. In real hardware, this value can be unknown. However, it is always a valid 1 or 0 and the RXxDCLK is valid. + #define NWS_REG_RX3_CONTROL_RX3DATASYNC_E5_SHIFT 2 + #define NWS_REG_RX3_CONTROL_RX3EARLYIN_E5 (0x1<<3) // Early Input. External EARLY input to internal rotator control logic. Based on the setting of the Internal/External Early/Late Selection Control in the Receiver Phase Rotator Control Register, bit 4, each rising edge of this input moves the rotator control logic down by one step. Early information entered this way makes use of the internal filter state machine and flywheel. 0 Normal. 1 Step rotator down. This signal must maintain a level for a minimum of one C16 cycle to be recognized. Note: Do not use this until the core has completed initial calibration. + #define NWS_REG_RX3_CONTROL_RX3EARLYIN_E5_SHIFT 3 + #define NWS_REG_RX3_CONTROL_RX3LATEIN_E5 (0x1<<4) // Late Input. External LATE input to internal rotator control logic. Based on the setting of the Internal/External Early/Late Selection Control in Receiver Phase Rotator Control Register, bit 4, each rising edge of this input moves the rotator control logic up by one step. Late information entered this way makes use of the internal filter state machine and flywheel. 0 Normal. 1 Step rotator up. This signal must maintain a level for a minimum of one C16 cycle to be recognized. Note: Do not use this until the core has completed initial calibration + #define NWS_REG_RX3_CONTROL_RX3LATEIN_E5_SHIFT 4 + #define NWS_REG_RX3_CONTROL_RX3PHSDNIN_E5 (0x1<<5) // Phase Down Input. External adjustment control to retard the phase rotators. Each rising edge of this signal causes one incremental adjustment (retard) of the phase rotators. RXxPHSLOCK must be ‘1’ to enable this. This signal must maintain a level for a minimum of one C16 cycle to be recognized. 0 Normal. 1 Retard phase rotator 1 increment. + #define NWS_REG_RX3_CONTROL_RX3PHSDNIN_E5_SHIFT 5 + #define NWS_REG_RX3_CONTROL_RX3PHSUPIN_E5 (0x1<<6) // Phase Up Input. External adjustment control to advance the phase rotators. Each rising edge of this signal causes one incremental adjustment (advance) of the phase rotators. RXxPHSLOCK must be ‘1’ to enable this. This signal must maintain a level for a minimum of one C16 cycle to be recognized. 0 Normal. 1 Advance phase rotator 1 increment + #define NWS_REG_RX3_CONTROL_RX3PHSUPIN_E5_SHIFT 6 + #define NWS_REG_RX3_CONTROL_RX3PHSLOCK_E5 (0x1<<7) // Phase Lock. Enable external adjustment of phase rotator through RXxPHSDNIN and RXxPHSUPIN input signals. 0 Disabled (normal operation). 1 Enabled (external control of phase rotators). Note: Do not set this bit to ‘1’ until the core has completed initial calibration. + #define NWS_REG_RX3_CONTROL_RX3PHSLOCK_E5_SHIFT 7 +#define NWS_REG_TX0_CONTROL_E5 0x700070UL //Access:RW DataWidth:0x13 // Multi Field Register. + #define NWS_REG_TX0_CONTROL_TX0CONFIGSEL_E5 (0x3<<0) // Transmitter Port Configuration Selection. Selects one of four possible Transmitter preconfigurations if bit 10 of the Transmitter Configuration Mode Register is set to ‘1’. Otherwise, these pins are ignored. 00 Preconfiguration 0 selected. 01 Preconfiguration 1 selected. 10 Preconfiguration 2 selected. 11 Preconfiguration 3 selected. Note: When changing between preconfigurations that require both pins to change (such as from ‘00’ to ‘11’), the pins must change state within 500 ps of each other. + #define NWS_REG_TX0_CONTROL_TX0CONFIGSEL_E5_SHIFT 0 + #define NWS_REG_TX0_CONTROL_TX0AAECMD_E5 (0xff<<2) // Adaptive Equalization Command. For use with an external macro to support the 802.3ap standard. When TXxAECMDVAL is asserted, the command on these bits is read and executed by the TX logic. This provides a means for controlling coefficients other than the parallel or JTAG register ports. The bits are defined as follows: Bit 13. Coefficient preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coefficient update. 00 Hold. 01 Increment. 10 Decrement. 11 Reserved. Bits 5:4. Postcursor coefficient update. 00 Hold. 01 Increment. 10 Decrement. 11 Reserved. Bits 3:2. Cursor coefficient update. 00 Hold. 01 Increment. 10 Decrement. 11 Reserved. Bits 1:0. Precursor coefficient update. 00 Hold. 01 Increment. 10 Decrement. 11 Reserved. See Section 3.1.7.12 Transmit DCLK Drift Tolerance Register on page 177 for more details. + #define NWS_REG_TX0_CONTROL_TX0AAECMD_E5_SHIFT 2 + #define NWS_REG_TX0_CONTROL_TX0AAECMD10_E5 (0x1<<10) // See above. + #define NWS_REG_TX0_CONTROL_TX0AAECMD10_E5_SHIFT 10 + #define NWS_REG_TX0_CONTROL_TX0AAECMD11_E5 (0x1<<11) // See above. + #define NWS_REG_TX0_CONTROL_TX0AAECMD11_E5_SHIFT 11 + #define NWS_REG_TX0_CONTROL_TX0AAECMD12_E5 (0x1<<12) // See above. + #define NWS_REG_TX0_CONTROL_TX0AAECMD12_E5_SHIFT 12 + #define NWS_REG_TX0_CONTROL_TX0AAECMD13_E5 (0x1<<13) // See above. + #define NWS_REG_TX0_CONTROL_TX0AAECMD13_E5_SHIFT 13 + #define NWS_REG_TX0_CONTROL_TX0AAECMDVAL_E5 (0x1<<14) // Adaptive Equalization Command Valid. For use with an external macro to support the 802.3ap standard. This strobe signal is used to indicate to the TX logic that a valid command is present on TXxAECMD. NOTE: the ascmd signals are for use with an external macro. Delete these if we get the macro. + #define NWS_REG_TX0_CONTROL_TX0AAECMDVAL_E5_SHIFT 14 + #define NWS_REG_TX0_CONTROL_TX0AOBS_E5 (0x1<<15) // Out of Band Signaling. Drives transmitter outputs to the DC common mode voltage. See Section 2.3.3.13 , Out of Band Signaling Mode (OBS), on page 85. 0 Normal. 1 OBS mode enabled. + #define NWS_REG_TX0_CONTROL_TX0AOBS_E5_SHIFT 15 + #define NWS_REG_TX0_CONTROL_TX0AOE_E5 (0x1<<16) // Transmitter Output Enable. Enables the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.) 1 Normal operation. Notes: 1. This pin is ignored if HSSJTAGCE = ‘1’ and the transmitter output is controlled by TXxJTAGOE. 2. The transmitter output can also be disabled by setting bit 5 of Transmit Mode Register, offset 0x03, to ‘1’ regardless of the setting of this pin. + #define NWS_REG_TX0_CONTROL_TX0AOE_E5_SHIFT 16 + #define NWS_REG_TX0_CONTROL_TX0AQUIET_E5 (0x1<<17) // + #define NWS_REG_TX0_CONTROL_TX0AQUIET_E5_SHIFT 17 + #define NWS_REG_TX0_CONTROL_TX0AREFRESH_E5 (0x1<<18) // + #define NWS_REG_TX0_CONTROL_TX0AREFRESH_E5_SHIFT 18 +#define NWS_REG_TX0_STATUS_E5 0x700074UL //Access:R DataWidth:0x8 // Adaptive Equalization Status. For use with an external macro to support the 802.3ap standard. This is a continuously updated status of the applied command with bits defined as follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Reserved. Bits 5:4. Post-cursor coefficient status. 00 Not updated 01 Updated 10 Minimum 11 Maximum Bits 3:2. Cursor coefficient status. 00 Not updated 01 Updated 10 Minimum 11 Maximum Bits 1:0. Precursor coefficient status. 00 Not updated 01 Updated 10 Minimum 11 Maximum See Section 3.1.7.21 Transmit Adaptive Equalization Status Register on page 189 for more details. NOTE: for use with an external macro. Delete these if we get the macro. +#define NWS_REG_TX1_CONTROL_E5 0x700078UL //Access:RW DataWidth:0x13 // Multi Field Register. + #define NWS_REG_TX1_CONTROL_TX1CONFIGSEL_E5 (0x3<<0) // Transmitter Port Configuration Selection. Selects one of four possible Transmitter preconfigurations if bit 10 of the Transmitter Configuration Mode Register is set to ‘1’. Otherwise, these pins are ignored. 00 Preconfiguration 0 selected. 01 Preconfiguration 1 selected. 10 Preconfiguration 2 selected. 11 Preconfiguration 3 selected. Note: When changing between preconfigurations that require both pins to change (such as from ‘00’ to ‘11’), the pins must change state within 500 ps of each other. + #define NWS_REG_TX1_CONTROL_TX1CONFIGSEL_E5_SHIFT 0 + #define NWS_REG_TX1_CONTROL_TX1AAECMD_E5 (0xff<<2) // Adaptive Equalization Command. For use with an external macro to support the 802.3ap standard. When TXxAECMDVAL is asserted, the command on these bits is read and executed by the TX logic. This provides a means for controlling coefficients other than the parallel or JTAG register ports. The bits are defined as follows: Bit 13. Coefficient preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coefficient update. 00 Hold. 01 Increment. 10 Decrement. 11 Reserved. Bits 5:4. Postcursor coefficient update. 00 Hold. 01 Increment. 10 Decrement. 11 Reserved. Bits 3:2. Cursor coefficient update. 00 Hold. 01 Increment. 10 Decrement. 11 Reserved. Bits 1:0. Precursor coefficient update. 00 Hold. 01 Increment. 10 Decrement. 11 Reserved. See Section 3.1.7.12 Transmit DCLK Drift Tolerance Register on page 177 for more details. + #define NWS_REG_TX1_CONTROL_TX1AAECMD_E5_SHIFT 2 + #define NWS_REG_TX1_CONTROL_TX1AAECMD10_E5 (0x1<<10) // See above. + #define NWS_REG_TX1_CONTROL_TX1AAECMD10_E5_SHIFT 10 + #define NWS_REG_TX1_CONTROL_TX1AAECMD11_E5 (0x1<<11) // See above. + #define NWS_REG_TX1_CONTROL_TX1AAECMD11_E5_SHIFT 11 + #define NWS_REG_TX1_CONTROL_TX1AAECMD12_E5 (0x1<<12) // See above. + #define NWS_REG_TX1_CONTROL_TX1AAECMD12_E5_SHIFT 12 + #define NWS_REG_TX1_CONTROL_TX1AAECMD13_E5 (0x1<<13) // See above. + #define NWS_REG_TX1_CONTROL_TX1AAECMD13_E5_SHIFT 13 + #define NWS_REG_TX1_CONTROL_TX1AAECMDVAL_E5 (0x1<<14) // Adaptive Equalization Command Valid. For use with an external macro to support the 802.3ap standard. This strobe signal is used to indicate to the TX logic that a valid command is present on TXxAECMD. NOTE: the ascmd signals are for use with an external macro. Delete these if we get the macro. + #define NWS_REG_TX1_CONTROL_TX1AAECMDVAL_E5_SHIFT 14 + #define NWS_REG_TX1_CONTROL_TX1AOBS_E5 (0x1<<15) // Out of Band Signaling. Drives transmitter outputs to the DC common mode voltage. See Section 2.3.3.13 , Out of Band Signaling Mode (OBS), on page 85. 0 Normal. 1 OBS mode enabled. + #define NWS_REG_TX1_CONTROL_TX1AOBS_E5_SHIFT 15 + #define NWS_REG_TX1_CONTROL_TX1AOE_E5 (0x1<<16) // Transmitter Output Enable. Enables the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.) 1 Normal operation. Notes: 1. This pin is ignored if HSSJTAGCE = ‘1’ and the transmitter output is controlled by TXxJTAGOE. 2. The transmitter output can also be disabled by setting bit 5 of Transmit Mode Register, offset 0x03, to ‘1’ regardless of the setting of this pin. + #define NWS_REG_TX1_CONTROL_TX1AOE_E5_SHIFT 16 + #define NWS_REG_TX1_CONTROL_TX1AQUIET_E5 (0x1<<17) // + #define NWS_REG_TX1_CONTROL_TX1AQUIET_E5_SHIFT 17 + #define NWS_REG_TX1_CONTROL_TX1AREFRESH_E5 (0x1<<18) // + #define NWS_REG_TX1_CONTROL_TX1AREFRESH_E5_SHIFT 18 +#define NWS_REG_TX1_STATUS_E5 0x70007cUL //Access:R DataWidth:0x8 // Adaptive Equalization Status. For use with an external macro to support the 802.3ap standard. This is a continuously updated status of the applied command with bits defined as follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Reserved. Bits 5:4. Post-cursor coefficient status. 00 Not updated 01 Updated 10 Minimum 11 Maximum Bits 3:2. Cursor coefficient status. 00 Not updated 01 Updated 10 Minimum 11 Maximum Bits 1:0. Precursor coefficient status. 00 Not updated 01 Updated 10 Minimum 11 Maximum See Section 3.1.7.21 Transmit Adaptive Equalization Status Register on page 189 for more details. NOTE: for use with an external macro. Delete these if we get the macro. +#define NWS_REG_TX2_CONTROL_E5 0x700080UL //Access:RW DataWidth:0x13 // Multi Field Register. + #define NWS_REG_TX2_CONTROL_TX2CONFIGSEL_E5 (0x3<<0) // Transmitter Port Configuration Selection. Selects one of four possible Transmitter preconfigurations if bit 10 of the Transmitter Configuration Mode Register is set to ‘1’. Otherwise, these pins are ignored. 00 Preconfiguration 0 selected. 01 Preconfiguration 1 selected. 10 Preconfiguration 2 selected. 11 Preconfiguration 3 selected. Note: When changing between preconfigurations that require both pins to change (such as from ‘00’ to ‘11’), the pins must change state within 500 ps of each other. + #define NWS_REG_TX2_CONTROL_TX2CONFIGSEL_E5_SHIFT 0 + #define NWS_REG_TX2_CONTROL_TX2AAECMD_E5 (0xff<<2) // Adaptive Equalization Command. For use with an external macro to support the 802.3ap standard. When TXxAECMDVAL is asserted, the command on these bits is read and executed by the TX logic. This provides a means for controlling coefficients other than the parallel or JTAG register ports. The bits are defined as follows: Bit 13. Coefficient preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coefficient update. 00 Hold. 01 Increment. 10 Decrement. 11 Reserved. Bits 5:4. Postcursor coefficient update. 00 Hold. 01 Increment. 10 Decrement. 11 Reserved. Bits 3:2. Cursor coefficient update. 00 Hold. 01 Increment. 10 Decrement. 11 Reserved. Bits 1:0. Precursor coefficient update. 00 Hold. 01 Increment. 10 Decrement. 11 Reserved. See Section 3.1.7.12 Transmit DCLK Drift Tolerance Register on page 177 for more details. + #define NWS_REG_TX2_CONTROL_TX2AAECMD_E5_SHIFT 2 + #define NWS_REG_TX2_CONTROL_TX2AAECMD10_E5 (0x1<<10) // See above. + #define NWS_REG_TX2_CONTROL_TX2AAECMD10_E5_SHIFT 10 + #define NWS_REG_TX2_CONTROL_TX2AAECMD11_E5 (0x1<<11) // See above. + #define NWS_REG_TX2_CONTROL_TX2AAECMD11_E5_SHIFT 11 + #define NWS_REG_TX2_CONTROL_TX2AAECMD12_E5 (0x1<<12) // See above. + #define NWS_REG_TX2_CONTROL_TX2AAECMD12_E5_SHIFT 12 + #define NWS_REG_TX2_CONTROL_TX2AAECMD13_E5 (0x1<<13) // See above. + #define NWS_REG_TX2_CONTROL_TX2AAECMD13_E5_SHIFT 13 + #define NWS_REG_TX2_CONTROL_TX2AAECMDVAL_E5 (0x1<<14) // Adaptive Equalization Command Valid. For use with an external macro to support the 802.3ap standard. This strobe signal is used to indicate to the TX logic that a valid command is present on TXxAECMD. NOTE: the ascmd signals are for use with an external macro. Delete these if we get the macro. + #define NWS_REG_TX2_CONTROL_TX2AAECMDVAL_E5_SHIFT 14 + #define NWS_REG_TX2_CONTROL_TX2AOBS_E5 (0x1<<15) // Out of Band Signaling. Drives transmitter outputs to the DC common mode voltage. See Section 2.3.3.13 , Out of Band Signaling Mode (OBS), on page 85. 0 Normal. 1 OBS mode enabled. + #define NWS_REG_TX2_CONTROL_TX2AOBS_E5_SHIFT 15 + #define NWS_REG_TX2_CONTROL_TX2AOE_E5 (0x1<<16) // Transmitter Output Enable. Enables the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.) 1 Normal operation. Notes: 1. This pin is ignored if HSSJTAGCE = ‘1’ and the transmitter output is controlled by TXxJTAGOE. 2. The transmitter output can also be disabled by setting bit 5 of Transmit Mode Register, offset 0x03, to ‘1’ regardless of the setting of this pin. + #define NWS_REG_TX2_CONTROL_TX2AOE_E5_SHIFT 16 + #define NWS_REG_TX2_CONTROL_TX2AQUIET_E5 (0x1<<17) // + #define NWS_REG_TX2_CONTROL_TX2AQUIET_E5_SHIFT 17 + #define NWS_REG_TX2_CONTROL_TX2AREFRESH_E5 (0x1<<18) // + #define NWS_REG_TX2_CONTROL_TX2AREFRESH_E5_SHIFT 18 +#define NWS_REG_TX2_STATUS_E5 0x700084UL //Access:R DataWidth:0x8 // Adaptive Equalization Status. For use with an external macro to support the 802.3ap standard. This is a continuously updated status of the applied command with bits defined as follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Reserved. Bits 5:4. Post-cursor coefficient status. 00 Not updated 01 Updated 10 Minimum 11 Maximum Bits 3:2. Cursor coefficient status. 00 Not updated 01 Updated 10 Minimum 11 Maximum Bits 1:0. Precursor coefficient status. 00 Not updated 01 Updated 10 Minimum 11 Maximum See Section 3.1.7.21 Transmit Adaptive Equalization Status Register on page 189 for more details. NOTE: for use with an external macro. Delete these if we get the macro. +#define NWS_REG_TX3_CONTROL_E5 0x700088UL //Access:RW DataWidth:0x13 // Multi Field Register. + #define NWS_REG_TX3_CONTROL_TX3CONFIGSEL_E5 (0x3<<0) // Transmitter Port Configuration Selection. Selects one of four possible Transmitter preconfigurations if bit 10 of the Transmitter Configuration Mode Register is set to ‘1’. Otherwise, these pins are ignored. 00 Preconfiguration 0 selected. 01 Preconfiguration 1 selected. 10 Preconfiguration 2 selected. 11 Preconfiguration 3 selected. Note: When changing between preconfigurations that require both pins to change (such as from ‘00’ to ‘11’), the pins must change state within 500 ps of each other. + #define NWS_REG_TX3_CONTROL_TX3CONFIGSEL_E5_SHIFT 0 + #define NWS_REG_TX3_CONTROL_TX3AAECMD_E5 (0xff<<2) // Adaptive Equalization Command. For use with an external macro to support the 802.3ap standard. When TXxAECMDVAL is asserted, the command on these bits is read and executed by the TX logic. This provides a means for controlling coefficients other than the parallel or JTAG register ports. The bits are defined as follows: Bit 13. Coefficient preset. Bit 12. Coefficient initialize. Bits 11:8. Not used. Bits 7:6. Second post-cursor coefficient update. 00 Hold. 01 Increment. 10 Decrement. 11 Reserved. Bits 5:4. Postcursor coefficient update. 00 Hold. 01 Increment. 10 Decrement. 11 Reserved. Bits 3:2. Cursor coefficient update. 00 Hold. 01 Increment. 10 Decrement. 11 Reserved. Bits 1:0. Precursor coefficient update. 00 Hold. 01 Increment. 10 Decrement. 11 Reserved. See Section 3.1.7.12 Transmit DCLK Drift Tolerance Register on page 177 for more details. + #define NWS_REG_TX3_CONTROL_TX3AAECMD_E5_SHIFT 2 + #define NWS_REG_TX3_CONTROL_TX3AAECMD10_E5 (0x1<<10) // See above. + #define NWS_REG_TX3_CONTROL_TX3AAECMD10_E5_SHIFT 10 + #define NWS_REG_TX3_CONTROL_TX3AAECMD11_E5 (0x1<<11) // See above. + #define NWS_REG_TX3_CONTROL_TX3AAECMD11_E5_SHIFT 11 + #define NWS_REG_TX3_CONTROL_TX3AAECMD12_E5 (0x1<<12) // See above. + #define NWS_REG_TX3_CONTROL_TX3AAECMD12_E5_SHIFT 12 + #define NWS_REG_TX3_CONTROL_TX3AAECMD13_E5 (0x1<<13) // See above. + #define NWS_REG_TX3_CONTROL_TX3AAECMD13_E5_SHIFT 13 + #define NWS_REG_TX3_CONTROL_TX3AAECMDVAL_E5 (0x1<<14) // Adaptive Equalization Command Valid. For use with an external macro to support the 802.3ap standard. This strobe signal is used to indicate to the TX logic that a valid command is present on TXxAECMD. NOTE: the ascmd signals are for use with an external macro. Delete these if we get the macro. + #define NWS_REG_TX3_CONTROL_TX3AAECMDVAL_E5_SHIFT 14 + #define NWS_REG_TX3_CONTROL_TX3AOBS_E5 (0x1<<15) // Out of Band Signaling. Drives transmitter outputs to the DC common mode voltage. See Section 2.3.3.13 , Out of Band Signaling Mode (OBS), on page 85. 0 Normal. 1 OBS mode enabled. + #define NWS_REG_TX3_CONTROL_TX3AOBS_E5_SHIFT 15 + #define NWS_REG_TX3_CONTROL_TX3AOE_E5 (0x1<<16) // Transmitter Output Enable. Enables the transmitter output drivers. 0 Disable (transmitter outputs are in a high-impedance state.) 1 Normal operation. Notes: 1. This pin is ignored if HSSJTAGCE = ‘1’ and the transmitter output is controlled by TXxJTAGOE. 2. The transmitter output can also be disabled by setting bit 5 of Transmit Mode Register, offset 0x03, to ‘1’ regardless of the setting of this pin. + #define NWS_REG_TX3_CONTROL_TX3AOE_E5_SHIFT 16 + #define NWS_REG_TX3_CONTROL_TX3AQUIET_E5 (0x1<<17) // + #define NWS_REG_TX3_CONTROL_TX3AQUIET_E5_SHIFT 17 + #define NWS_REG_TX3_CONTROL_TX3AREFRESH_E5 (0x1<<18) // + #define NWS_REG_TX3_CONTROL_TX3AREFRESH_E5_SHIFT 18 +#define NWS_REG_TX3_STATUS_E5 0x70008cUL //Access:R DataWidth:0x8 // Adaptive Equalization Status. For use with an external macro to support the 802.3ap standard. This is a continuously updated status of the applied command with bits defined as follows: Bits 7:6. Second post-cursor coefficient status. 00 Hold 01 Increment 10 Decrement 11 Reserved. Bits 5:4. Post-cursor coefficient status. 00 Not updated 01 Updated 10 Minimum 11 Maximum Bits 3:2. Cursor coefficient status. 00 Not updated 01 Updated 10 Minimum 11 Maximum Bits 1:0. Precursor coefficient status. 00 Not updated 01 Updated 10 Minimum 11 Maximum See Section 3.1.7.21 Transmit Adaptive Equalization Status Register on page 189 for more details. NOTE: for use with an external macro. Delete these if we get the macro. +#define NWS_REG_EXTERNAL_SIGNAL_DETECT_K2 0x700050UL //Access:R DataWidth:0x4 // Multi Field Register. +#define NWS_REG_EXTERNAL_SIGNAL_DETECT_E5 0x700090UL //Access:R DataWidth:0x4 // Multi Field Register. #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P0_K2_E5 (0x1<<0) // Used to detect the presence of energy on SerDes receive channels or to detect the receiver loss condition(RX_LOS) from an external optical module Connects directly to pin P0_SIGDET #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P0_K2_E5_SHIFT 0 #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P1_K2_E5 (0x1<<1) // Used to detect the presence of energy on SerDes receive channels or to detect the receiver loss condition(RX_LOS) from an external optical module Connects directly to pin P1_SIGDET @@ -62975,7 +66859,8 @@ #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P2_K2_E5_SHIFT 2 #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P3_K2_E5 (0x1<<3) // Used to detect the presence of energy on SerDes receive channels or to detect the receiver loss condition(RX_LOS) from an external optical module Connects directly to pin P3_SIGDET #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P3_K2_E5_SHIFT 3 -#define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_K2_E5 0x700054UL //Access:R DataWidth:0x4 // Multi Field Register. +#define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_K2 0x700054UL //Access:R DataWidth:0x4 // Multi Field Register. +#define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_E5 0x700094UL //Access:R DataWidth:0x4 // Multi Field Register. #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P0_K2_E5 (0x1<<0) // Link Alarm Status Indication An asserted low input from the optical module or external PHY. When asserted, this signal indicates that a fault condition has been detected or cleared. Refer to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY that can drive LASI to the Controller to indicate a link status change or other events outlined in the XENPAK MSA standard. Connects directly to pin P0_PHY_LASI_B #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P0_K2_E5_SHIFT 0 #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P1_K2_E5 (0x1<<1) // Link Alarm Status Indication An asserted low input from the optical module or external PHY. When asserted, this signal indicates that a fault condition has been detected or cleared. Refer to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY that can drive LASI to the Controller to indicate a link status change or other events outlined in the XENPAK MSA standard. Connects directly to pin P1_PHY_LASI_B @@ -62984,11 +66869,12 @@ #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P2_K2_E5_SHIFT 2 #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P3_K2_E5 (0x1<<3) // Link Alarm Status Indication An asserted low input from the optical module or external PHY. When asserted, this signal indicates that a fault condition has been detected or cleared. Refer to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY that can drive LASI to the Controller to indicate a link status change or other events outlined in the XENPAK MSA standard. Connects directly to pin P3_PHY_LASI_B #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P3_K2_E5_SHIFT 3 -#define NWS_REG_ECO_RESERVED_K2_E5 0x700058UL //Access:RW DataWidth:0x20 // This is unused register for future ECOs. +#define NWS_REG_ECO_RESERVED_K2 0x700058UL //Access:RW DataWidth:0x20 // This is unused register for future ECOs. +#define NWS_REG_ECO_RESERVED_E5 0x700098UL //Access:RW DataWidth:0x20 // This is unused register for future ECOs. #define NWS_REG_DBG_OUT_DATA_K2_E5 0x700100UL //Access:WB_R DataWidth:0x100 // Dbgmux output data #define NWS_REG_DBG_OUT_DATA_SIZE 8 -#define NWS_REG_DBG_OUT_VALID_K2_E5 0x700120UL //Access:R DataWidth:0x4 // Dbgmux output valid -#define NWS_REG_DBG_OUT_FRAME_K2_E5 0x700124UL //Access:R DataWidth:0x4 // Dbgmux output frame +#define NWS_REG_DBG_OUT_VALID_K2_E5 0x700120UL //Access:R DataWidth:0x8 // Dbgmux output valid per Dword +#define NWS_REG_DBG_OUT_FRAME_K2_E5 0x700124UL //Access:R DataWidth:0x8 // Dbgmux output frame per Dword #define NWS_REG_DBG_SELECT_K2_E5 0x700128UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output #define NWS_REG_DBG_DWORD_ENABLE_K2_E5 0x70012cUL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line) in the selected line (before shift).for selecting a line to output #define NWS_REG_DBG_SHIFT_K2_E5 0x700130UL //Access:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) right shifting of the selected line (after the masking). @@ -63000,333 +66886,337 @@ #define NWS_REG_DBG_REPEAT_THRESHOLD_COUNT_K2_E5 0x700148UL //Access:RW DataWidth:0x4 // Debug only: If 0 or 1, trigger on first occurrence. If greater than 1, wait until counter value match to trigger. #define NWS_REG_DBG_POST_TRIGGER_LATENCY_COUNT_K2_E5 0x70014cUL //Access:RW DataWidth:0x18 // Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms #define NWS_REG_DBG_FW_TRIGGER_ENABLE_K2_E5 0x700150UL //Access:RW DataWidth:0x1 // Debug only: FW trigger is set. -#define NWS_REG_INT_STS_0_K2_E5 0x700180UL //Access:R DataWidth:0xa // Multi Field Register. +#define NWS_REG_INT_STS_0_K2_E5 0x700180UL //Access:R DataWidth:0x1 // Multi Field Register. #define NWS_REG_INT_STS_0_ADDRESS_ERROR_K2_E5 (0x1<<0) // Signals an unknown address to the rf module. #define NWS_REG_INT_STS_0_ADDRESS_ERROR_K2_E5_SHIFT 0 - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_CR2_K2_E5 (0x1<<1) // Autonegotiation resolved to 50g_cr2 - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_CR2_K2_E5_SHIFT 1 - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_KR2_K2_E5 (0x1<<2) // Autonegotiation resolved to 50g_kr2 - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_KR2_K2_E5_SHIFT 2 - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_CR4_K2_E5 (0x1<<3) // Autonegotiation resolved to 40g_cr4 - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_CR4_K2_E5_SHIFT 3 - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_KR4_K2_E5 (0x1<<4) // Autonegotiation resolved to 40g_kr4 - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_KR4_K2_E5_SHIFT 4 - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_GR_K2_E5 (0x1<<5) // Autonegotiation resolved to 25g_gr - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_GR_K2_E5_SHIFT 5 - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_CR_K2_E5 (0x1<<6) // Autonegotiation resolved to 25g_cr - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_CR_K2_E5_SHIFT 6 - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_KR_K2_E5 (0x1<<7) // Autonegotiation resolved to 25g_kr - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_KR_K2_E5_SHIFT 7 - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_10G_KR_K2_E5 (0x1<<8) // Autonegotiation resolved to 10g_kr - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_10G_KR_K2_E5_SHIFT 8 - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_1G_KX_K2_E5 (0x1<<9) // Autonegotiation resolved to 1g_kx - #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_1G_KX_K2_E5_SHIFT 9 -#define NWS_REG_INT_MASK_0_K2_E5 0x700184UL //Access:RW DataWidth:0xa // Multi Field Register. + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation resolved to 50g_cr2 + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_CR2_K2_SHIFT 1 + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_KR2_K2 (0x1<<2) // Autonegotiation resolved to 50g_kr2 + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_KR2_K2_SHIFT 2 + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation resolved to 40g_cr4 + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_CR4_K2_SHIFT 3 + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_KR4_K2 (0x1<<4) // Autonegotiation resolved to 40g_kr4 + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_KR4_K2_SHIFT 4 + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_GR_K2 (0x1<<5) // Autonegotiation resolved to 25g_gr + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_GR_K2_SHIFT 5 + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_CR_K2 (0x1<<6) // Autonegotiation resolved to 25g_cr + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_CR_K2_SHIFT 6 + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation resolved to 25g_kr + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_KR_K2_SHIFT 7 + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation resolved to 10g_kr + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_10G_KR_K2_SHIFT 8 + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_1G_KX_K2 (0x1<<9) // Autonegotiation resolved to 1g_kx + #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_1G_KX_K2_SHIFT 9 +#define NWS_REG_INT_MASK_0_K2_E5 0x700184UL //Access:RW DataWidth:0x1 // Multi Field Register. #define NWS_REG_INT_MASK_0_ADDRESS_ERROR_K2_E5 (0x1<<0) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.ADDRESS_ERROR . #define NWS_REG_INT_MASK_0_ADDRESS_ERROR_K2_E5_SHIFT 0 - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_CR2_K2_E5 (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_50G_CR2 . - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_CR2_K2_E5_SHIFT 1 - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_KR2_K2_E5 (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_50G_KR2 . - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_KR2_K2_E5_SHIFT 2 - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_CR4_K2_E5 (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_40G_CR4 . - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_CR4_K2_E5_SHIFT 3 - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_KR4_K2_E5 (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_40G_KR4 . - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_KR4_K2_E5_SHIFT 4 - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_GR_K2_E5 (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_25G_GR . - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_GR_K2_E5_SHIFT 5 - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_CR_K2_E5 (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_25G_CR . - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_CR_K2_E5_SHIFT 6 - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_KR_K2_E5 (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_25G_KR . - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_KR_K2_E5_SHIFT 7 - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_10G_KR_K2_E5 (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_10G_KR . - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_10G_KR_K2_E5_SHIFT 8 - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_1G_KX_K2_E5 (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_1G_KX . - #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_1G_KX_K2_E5_SHIFT 9 -#define NWS_REG_INT_STS_WR_0_K2_E5 0x700188UL //Access:WR DataWidth:0xa // Multi Field Register. + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_CR2_K2 (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_50G_CR2 . + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_CR2_K2_SHIFT 1 + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_KR2_K2 (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_50G_KR2 . + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_KR2_K2_SHIFT 2 + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_CR4_K2 (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_40G_CR4 . + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_CR4_K2_SHIFT 3 + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_KR4_K2 (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_40G_KR4 . + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_KR4_K2_SHIFT 4 + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_GR_K2 (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_25G_GR . + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_GR_K2_SHIFT 5 + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_CR_K2 (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_25G_CR . + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_CR_K2_SHIFT 6 + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_KR_K2 (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_25G_KR . + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_KR_K2_SHIFT 7 + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_10G_KR_K2 (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_10G_KR . + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_10G_KR_K2_SHIFT 8 + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_1G_KX_K2 (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_1G_KX . + #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_1G_KX_K2_SHIFT 9 +#define NWS_REG_INT_STS_WR_0_K2_E5 0x700188UL //Access:WR DataWidth:0x1 // Multi Field Register. #define NWS_REG_INT_STS_WR_0_ADDRESS_ERROR_K2_E5 (0x1<<0) // Signals an unknown address to the rf module. #define NWS_REG_INT_STS_WR_0_ADDRESS_ERROR_K2_E5_SHIFT 0 - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_CR2_K2_E5 (0x1<<1) // Autonegotiation resolved to 50g_cr2 - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_CR2_K2_E5_SHIFT 1 - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_KR2_K2_E5 (0x1<<2) // Autonegotiation resolved to 50g_kr2 - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_KR2_K2_E5_SHIFT 2 - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_CR4_K2_E5 (0x1<<3) // Autonegotiation resolved to 40g_cr4 - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_CR4_K2_E5_SHIFT 3 - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_KR4_K2_E5 (0x1<<4) // Autonegotiation resolved to 40g_kr4 - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_KR4_K2_E5_SHIFT 4 - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_GR_K2_E5 (0x1<<5) // Autonegotiation resolved to 25g_gr - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_GR_K2_E5_SHIFT 5 - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_CR_K2_E5 (0x1<<6) // Autonegotiation resolved to 25g_cr - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_CR_K2_E5_SHIFT 6 - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_KR_K2_E5 (0x1<<7) // Autonegotiation resolved to 25g_kr - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_KR_K2_E5_SHIFT 7 - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_10G_KR_K2_E5 (0x1<<8) // Autonegotiation resolved to 10g_kr - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_10G_KR_K2_E5_SHIFT 8 - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_1G_KX_K2_E5 (0x1<<9) // Autonegotiation resolved to 1g_kx - #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_1G_KX_K2_E5_SHIFT 9 -#define NWS_REG_INT_STS_CLR_0_K2_E5 0x70018cUL //Access:RC DataWidth:0xa // Multi Field Register. + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation resolved to 50g_cr2 + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_CR2_K2_SHIFT 1 + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_KR2_K2 (0x1<<2) // Autonegotiation resolved to 50g_kr2 + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_KR2_K2_SHIFT 2 + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation resolved to 40g_cr4 + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_CR4_K2_SHIFT 3 + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_KR4_K2 (0x1<<4) // Autonegotiation resolved to 40g_kr4 + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_KR4_K2_SHIFT 4 + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_GR_K2 (0x1<<5) // Autonegotiation resolved to 25g_gr + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_GR_K2_SHIFT 5 + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_CR_K2 (0x1<<6) // Autonegotiation resolved to 25g_cr + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_CR_K2_SHIFT 6 + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation resolved to 25g_kr + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_KR_K2_SHIFT 7 + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation resolved to 10g_kr + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_10G_KR_K2_SHIFT 8 + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_1G_KX_K2 (0x1<<9) // Autonegotiation resolved to 1g_kx + #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_1G_KX_K2_SHIFT 9 +#define NWS_REG_INT_STS_CLR_0_K2_E5 0x70018cUL //Access:RC DataWidth:0x1 // Multi Field Register. #define NWS_REG_INT_STS_CLR_0_ADDRESS_ERROR_K2_E5 (0x1<<0) // Signals an unknown address to the rf module. #define NWS_REG_INT_STS_CLR_0_ADDRESS_ERROR_K2_E5_SHIFT 0 - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_CR2_K2_E5 (0x1<<1) // Autonegotiation resolved to 50g_cr2 - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_CR2_K2_E5_SHIFT 1 - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_KR2_K2_E5 (0x1<<2) // Autonegotiation resolved to 50g_kr2 - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_KR2_K2_E5_SHIFT 2 - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_CR4_K2_E5 (0x1<<3) // Autonegotiation resolved to 40g_cr4 - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_CR4_K2_E5_SHIFT 3 - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_KR4_K2_E5 (0x1<<4) // Autonegotiation resolved to 40g_kr4 - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_KR4_K2_E5_SHIFT 4 - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_GR_K2_E5 (0x1<<5) // Autonegotiation resolved to 25g_gr - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_GR_K2_E5_SHIFT 5 - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_CR_K2_E5 (0x1<<6) // Autonegotiation resolved to 25g_cr - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_CR_K2_E5_SHIFT 6 - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_KR_K2_E5 (0x1<<7) // Autonegotiation resolved to 25g_kr - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_KR_K2_E5_SHIFT 7 - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_10G_KR_K2_E5 (0x1<<8) // Autonegotiation resolved to 10g_kr - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_10G_KR_K2_E5_SHIFT 8 - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_1G_KX_K2_E5 (0x1<<9) // Autonegotiation resolved to 1g_kx - #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_1G_KX_K2_E5_SHIFT 9 -#define NWS_REG_INT_STS_1_K2_E5 0x700190UL //Access:R DataWidth:0xa // Multi Field Register. - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_CR2_K2_E5 (0x1<<1) // Autonegotiation resolved to 50g_cr2 - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_CR2_K2_E5_SHIFT 1 - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_KR2_K2_E5 (0x1<<2) // Autonegotiation resolved to 50g_kr2 - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_KR2_K2_E5_SHIFT 2 - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_CR4_K2_E5 (0x1<<3) // Autonegotiation resolved to 40g_cr4 - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_CR4_K2_E5_SHIFT 3 - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_KR4_K2_E5 (0x1<<4) // Autonegotiation resolved to 40g_kr4 - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_KR4_K2_E5_SHIFT 4 - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_GR_K2_E5 (0x1<<5) // Autonegotiation resolved to 25g_gr - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_GR_K2_E5_SHIFT 5 - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_CR_K2_E5 (0x1<<6) // Autonegotiation resolved to 25g_cr - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_CR_K2_E5_SHIFT 6 - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_KR_K2_E5 (0x1<<7) // Autonegotiation resolved to 25g_kr - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_KR_K2_E5_SHIFT 7 - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_10G_KR_K2_E5 (0x1<<8) // Autonegotiation resolved to 10g_kr - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_10G_KR_K2_E5_SHIFT 8 - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_1G_KX_K2_E5 (0x1<<9) // Autonegotiation resolved to 1g_kx - #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_1G_KX_K2_E5_SHIFT 9 -#define NWS_REG_INT_MASK_1_K2_E5 0x700194UL //Access:RW DataWidth:0xa // Multi Field Register. - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_CR2_K2_E5 (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_50G_CR2 . - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_CR2_K2_E5_SHIFT 1 - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_KR2_K2_E5 (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_50G_KR2 . - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_KR2_K2_E5_SHIFT 2 - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_CR4_K2_E5 (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_40G_CR4 . - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_CR4_K2_E5_SHIFT 3 - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_KR4_K2_E5 (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_40G_KR4 . - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_KR4_K2_E5_SHIFT 4 - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_GR_K2_E5 (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_25G_GR . - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_GR_K2_E5_SHIFT 5 - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_CR_K2_E5 (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_25G_CR . - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_CR_K2_E5_SHIFT 6 - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_KR_K2_E5 (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_25G_KR . - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_KR_K2_E5_SHIFT 7 - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_10G_KR_K2_E5 (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_10G_KR . - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_10G_KR_K2_E5_SHIFT 8 - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_1G_KX_K2_E5 (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_1G_KX . - #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_1G_KX_K2_E5_SHIFT 9 -#define NWS_REG_INT_STS_WR_1_K2_E5 0x700198UL //Access:WR DataWidth:0xa // Multi Field Register. - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_CR2_K2_E5 (0x1<<1) // Autonegotiation resolved to 50g_cr2 - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_CR2_K2_E5_SHIFT 1 - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_KR2_K2_E5 (0x1<<2) // Autonegotiation resolved to 50g_kr2 - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_KR2_K2_E5_SHIFT 2 - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_CR4_K2_E5 (0x1<<3) // Autonegotiation resolved to 40g_cr4 - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_CR4_K2_E5_SHIFT 3 - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_KR4_K2_E5 (0x1<<4) // Autonegotiation resolved to 40g_kr4 - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_KR4_K2_E5_SHIFT 4 - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_GR_K2_E5 (0x1<<5) // Autonegotiation resolved to 25g_gr - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_GR_K2_E5_SHIFT 5 - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_CR_K2_E5 (0x1<<6) // Autonegotiation resolved to 25g_cr - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_CR_K2_E5_SHIFT 6 - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_KR_K2_E5 (0x1<<7) // Autonegotiation resolved to 25g_kr - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_KR_K2_E5_SHIFT 7 - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_10G_KR_K2_E5 (0x1<<8) // Autonegotiation resolved to 10g_kr - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_10G_KR_K2_E5_SHIFT 8 - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_1G_KX_K2_E5 (0x1<<9) // Autonegotiation resolved to 1g_kx - #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_1G_KX_K2_E5_SHIFT 9 -#define NWS_REG_INT_STS_CLR_1_K2_E5 0x70019cUL //Access:RC DataWidth:0xa // Multi Field Register. - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_CR2_K2_E5 (0x1<<1) // Autonegotiation resolved to 50g_cr2 - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_CR2_K2_E5_SHIFT 1 - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_KR2_K2_E5 (0x1<<2) // Autonegotiation resolved to 50g_kr2 - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_KR2_K2_E5_SHIFT 2 - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_CR4_K2_E5 (0x1<<3) // Autonegotiation resolved to 40g_cr4 - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_CR4_K2_E5_SHIFT 3 - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_KR4_K2_E5 (0x1<<4) // Autonegotiation resolved to 40g_kr4 - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_KR4_K2_E5_SHIFT 4 - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_GR_K2_E5 (0x1<<5) // Autonegotiation resolved to 25g_gr - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_GR_K2_E5_SHIFT 5 - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_CR_K2_E5 (0x1<<6) // Autonegotiation resolved to 25g_cr - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_CR_K2_E5_SHIFT 6 - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_KR_K2_E5 (0x1<<7) // Autonegotiation resolved to 25g_kr - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_KR_K2_E5_SHIFT 7 - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_10G_KR_K2_E5 (0x1<<8) // Autonegotiation resolved to 10g_kr - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_10G_KR_K2_E5_SHIFT 8 - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_1G_KX_K2_E5 (0x1<<9) // Autonegotiation resolved to 1g_kx - #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_1G_KX_K2_E5_SHIFT 9 -#define NWS_REG_INT_STS_2_K2_E5 0x7001a0UL //Access:R DataWidth:0xa // Multi Field Register. - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_CR2_K2_E5 (0x1<<1) // Autonegotiation resolved to 50g_cr2 - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_CR2_K2_E5_SHIFT 1 - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_KR2_K2_E5 (0x1<<2) // Autonegotiation resolved to 50g_kr2 - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_KR2_K2_E5_SHIFT 2 - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_CR4_K2_E5 (0x1<<3) // Autonegotiation resolved to 40g_cr4 - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_CR4_K2_E5_SHIFT 3 - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_KR4_K2_E5 (0x1<<4) // Autonegotiation resolved to 40g_kr4 - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_KR4_K2_E5_SHIFT 4 - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_GR_K2_E5 (0x1<<5) // Autonegotiation resolved to 25g_gr - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_GR_K2_E5_SHIFT 5 - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_CR_K2_E5 (0x1<<6) // Autonegotiation resolved to 25g_cr - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_CR_K2_E5_SHIFT 6 - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_KR_K2_E5 (0x1<<7) // Autonegotiation resolved to 25g_kr - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_KR_K2_E5_SHIFT 7 - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_10G_KR_K2_E5 (0x1<<8) // Autonegotiation resolved to 10g_kr - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_10G_KR_K2_E5_SHIFT 8 - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_1G_KX_K2_E5 (0x1<<9) // Autonegotiation resolved to 1g_kx - #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_1G_KX_K2_E5_SHIFT 9 -#define NWS_REG_INT_MASK_2_K2_E5 0x7001a4UL //Access:RW DataWidth:0xa // Multi Field Register. - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_CR2_K2_E5 (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_50G_CR2 . - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_CR2_K2_E5_SHIFT 1 - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_KR2_K2_E5 (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_50G_KR2 . - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_KR2_K2_E5_SHIFT 2 - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_CR4_K2_E5 (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_40G_CR4 . - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_CR4_K2_E5_SHIFT 3 - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_KR4_K2_E5 (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_40G_KR4 . - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_KR4_K2_E5_SHIFT 4 - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_GR_K2_E5 (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_25G_GR . - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_GR_K2_E5_SHIFT 5 - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_CR_K2_E5 (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_25G_CR . - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_CR_K2_E5_SHIFT 6 - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_KR_K2_E5 (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_25G_KR . - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_KR_K2_E5_SHIFT 7 - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_10G_KR_K2_E5 (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_10G_KR . - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_10G_KR_K2_E5_SHIFT 8 - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_1G_KX_K2_E5 (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_1G_KX . - #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_1G_KX_K2_E5_SHIFT 9 -#define NWS_REG_INT_STS_WR_2_K2_E5 0x7001a8UL //Access:WR DataWidth:0xa // Multi Field Register. - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_CR2_K2_E5 (0x1<<1) // Autonegotiation resolved to 50g_cr2 - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_CR2_K2_E5_SHIFT 1 - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_KR2_K2_E5 (0x1<<2) // Autonegotiation resolved to 50g_kr2 - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_KR2_K2_E5_SHIFT 2 - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_CR4_K2_E5 (0x1<<3) // Autonegotiation resolved to 40g_cr4 - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_CR4_K2_E5_SHIFT 3 - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_KR4_K2_E5 (0x1<<4) // Autonegotiation resolved to 40g_kr4 - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_KR4_K2_E5_SHIFT 4 - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_GR_K2_E5 (0x1<<5) // Autonegotiation resolved to 25g_gr - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_GR_K2_E5_SHIFT 5 - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_CR_K2_E5 (0x1<<6) // Autonegotiation resolved to 25g_cr - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_CR_K2_E5_SHIFT 6 - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_KR_K2_E5 (0x1<<7) // Autonegotiation resolved to 25g_kr - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_KR_K2_E5_SHIFT 7 - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_10G_KR_K2_E5 (0x1<<8) // Autonegotiation resolved to 10g_kr - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_10G_KR_K2_E5_SHIFT 8 - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_1G_KX_K2_E5 (0x1<<9) // Autonegotiation resolved to 1g_kx - #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_1G_KX_K2_E5_SHIFT 9 -#define NWS_REG_INT_STS_CLR_2_K2_E5 0x7001acUL //Access:RC DataWidth:0xa // Multi Field Register. - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_CR2_K2_E5 (0x1<<1) // Autonegotiation resolved to 50g_cr2 - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_CR2_K2_E5_SHIFT 1 - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_KR2_K2_E5 (0x1<<2) // Autonegotiation resolved to 50g_kr2 - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_KR2_K2_E5_SHIFT 2 - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_CR4_K2_E5 (0x1<<3) // Autonegotiation resolved to 40g_cr4 - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_CR4_K2_E5_SHIFT 3 - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_KR4_K2_E5 (0x1<<4) // Autonegotiation resolved to 40g_kr4 - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_KR4_K2_E5_SHIFT 4 - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_GR_K2_E5 (0x1<<5) // Autonegotiation resolved to 25g_gr - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_GR_K2_E5_SHIFT 5 - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_CR_K2_E5 (0x1<<6) // Autonegotiation resolved to 25g_cr - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_CR_K2_E5_SHIFT 6 - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_KR_K2_E5 (0x1<<7) // Autonegotiation resolved to 25g_kr - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_KR_K2_E5_SHIFT 7 - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_10G_KR_K2_E5 (0x1<<8) // Autonegotiation resolved to 10g_kr - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_10G_KR_K2_E5_SHIFT 8 - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_1G_KX_K2_E5 (0x1<<9) // Autonegotiation resolved to 1g_kx - #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_1G_KX_K2_E5_SHIFT 9 -#define NWS_REG_INT_STS_3_K2_E5 0x7001b0UL //Access:R DataWidth:0xa // Multi Field Register. - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_CR2_K2_E5 (0x1<<1) // Autonegotiation resolved to 50g_cr2 - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_CR2_K2_E5_SHIFT 1 - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_KR2_K2_E5 (0x1<<2) // Autonegotiation resolved to 50g_kr2 - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_KR2_K2_E5_SHIFT 2 - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_CR4_K2_E5 (0x1<<3) // Autonegotiation resolved to 40g_cr4 - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_CR4_K2_E5_SHIFT 3 - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_KR4_K2_E5 (0x1<<4) // Autonegotiation resolved to 40g_kr4 - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_KR4_K2_E5_SHIFT 4 - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_GR_K2_E5 (0x1<<5) // Autonegotiation resolved to 25g_gr - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_GR_K2_E5_SHIFT 5 - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_CR_K2_E5 (0x1<<6) // Autonegotiation resolved to 25g_cr - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_CR_K2_E5_SHIFT 6 - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_KR_K2_E5 (0x1<<7) // Autonegotiation resolved to 25g_kr - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_KR_K2_E5_SHIFT 7 - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_10G_KR_K2_E5 (0x1<<8) // Autonegotiation resolved to 10g_kr - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_10G_KR_K2_E5_SHIFT 8 - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_1G_KX_K2_E5 (0x1<<9) // Autonegotiation resolved to 1g_kx - #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_1G_KX_K2_E5_SHIFT 9 -#define NWS_REG_INT_MASK_3_K2_E5 0x7001b4UL //Access:RW DataWidth:0xa // Multi Field Register. - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_CR2_K2_E5 (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_50G_CR2 . - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_CR2_K2_E5_SHIFT 1 - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_KR2_K2_E5 (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_50G_KR2 . - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_KR2_K2_E5_SHIFT 2 - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_CR4_K2_E5 (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_40G_CR4 . - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_CR4_K2_E5_SHIFT 3 - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_KR4_K2_E5 (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_40G_KR4 . - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_KR4_K2_E5_SHIFT 4 - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_GR_K2_E5 (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_25G_GR . - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_GR_K2_E5_SHIFT 5 - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_CR_K2_E5 (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_25G_CR . - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_CR_K2_E5_SHIFT 6 - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_KR_K2_E5 (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_25G_KR . - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_KR_K2_E5_SHIFT 7 - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_10G_KR_K2_E5 (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_10G_KR . - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_10G_KR_K2_E5_SHIFT 8 - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_1G_KX_K2_E5 (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_1G_KX . - #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_1G_KX_K2_E5_SHIFT 9 -#define NWS_REG_INT_STS_WR_3_K2_E5 0x7001b8UL //Access:WR DataWidth:0xa // Multi Field Register. - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_CR2_K2_E5 (0x1<<1) // Autonegotiation resolved to 50g_cr2 - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_CR2_K2_E5_SHIFT 1 - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_KR2_K2_E5 (0x1<<2) // Autonegotiation resolved to 50g_kr2 - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_KR2_K2_E5_SHIFT 2 - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_CR4_K2_E5 (0x1<<3) // Autonegotiation resolved to 40g_cr4 - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_CR4_K2_E5_SHIFT 3 - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_KR4_K2_E5 (0x1<<4) // Autonegotiation resolved to 40g_kr4 - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_KR4_K2_E5_SHIFT 4 - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_GR_K2_E5 (0x1<<5) // Autonegotiation resolved to 25g_gr - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_GR_K2_E5_SHIFT 5 - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_CR_K2_E5 (0x1<<6) // Autonegotiation resolved to 25g_cr - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_CR_K2_E5_SHIFT 6 - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_KR_K2_E5 (0x1<<7) // Autonegotiation resolved to 25g_kr - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_KR_K2_E5_SHIFT 7 - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_10G_KR_K2_E5 (0x1<<8) // Autonegotiation resolved to 10g_kr - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_10G_KR_K2_E5_SHIFT 8 - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_1G_KX_K2_E5 (0x1<<9) // Autonegotiation resolved to 1g_kx - #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_1G_KX_K2_E5_SHIFT 9 -#define NWS_REG_INT_STS_CLR_3_K2_E5 0x7001bcUL //Access:RC DataWidth:0xa // Multi Field Register. - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_CR2_K2_E5 (0x1<<1) // Autonegotiation resolved to 50g_cr2 - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_CR2_K2_E5_SHIFT 1 - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_KR2_K2_E5 (0x1<<2) // Autonegotiation resolved to 50g_kr2 - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_KR2_K2_E5_SHIFT 2 - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_CR4_K2_E5 (0x1<<3) // Autonegotiation resolved to 40g_cr4 - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_CR4_K2_E5_SHIFT 3 - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_KR4_K2_E5 (0x1<<4) // Autonegotiation resolved to 40g_kr4 - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_KR4_K2_E5_SHIFT 4 - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_GR_K2_E5 (0x1<<5) // Autonegotiation resolved to 25g_gr - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_GR_K2_E5_SHIFT 5 - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_CR_K2_E5 (0x1<<6) // Autonegotiation resolved to 25g_cr - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_CR_K2_E5_SHIFT 6 - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_KR_K2_E5 (0x1<<7) // Autonegotiation resolved to 25g_kr - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_KR_K2_E5_SHIFT 7 - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_10G_KR_K2_E5 (0x1<<8) // Autonegotiation resolved to 10g_kr - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_10G_KR_K2_E5_SHIFT 8 - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_1G_KX_K2_E5 (0x1<<9) // Autonegotiation resolved to 1g_kx - #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_1G_KX_K2_E5_SHIFT 9 -#define NWS_REG_PRTY_MASK_H_0_K2_E5 0x700204UL //Access:RW DataWidth:0x4 // Multi Field Register. - #define NWS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_E5 (0x1<<0) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . - #define NWS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_E5_SHIFT 0 - #define NWS_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_E5 (0x1<<1) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY . - #define NWS_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_E5_SHIFT 1 - #define NWS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_E5 (0x1<<2) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . - #define NWS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_E5_SHIFT 2 - #define NWS_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_E5 (0x1<<3) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . - #define NWS_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_E5_SHIFT 3 + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation resolved to 50g_cr2 + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_CR2_K2_SHIFT 1 + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_KR2_K2 (0x1<<2) // Autonegotiation resolved to 50g_kr2 + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_KR2_K2_SHIFT 2 + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation resolved to 40g_cr4 + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_CR4_K2_SHIFT 3 + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_KR4_K2 (0x1<<4) // Autonegotiation resolved to 40g_kr4 + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_KR4_K2_SHIFT 4 + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_GR_K2 (0x1<<5) // Autonegotiation resolved to 25g_gr + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_GR_K2_SHIFT 5 + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_CR_K2 (0x1<<6) // Autonegotiation resolved to 25g_cr + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_CR_K2_SHIFT 6 + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation resolved to 25g_kr + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_KR_K2_SHIFT 7 + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation resolved to 10g_kr + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_10G_KR_K2_SHIFT 8 + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_1G_KX_K2 (0x1<<9) // Autonegotiation resolved to 1g_kx + #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_1G_KX_K2_SHIFT 9 +#define NWS_REG_INT_STS_1_K2 0x700190UL //Access:R DataWidth:0xa // Multi Field Register. + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation resolved to 50g_cr2 + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_CR2_K2_SHIFT 1 + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_KR2_K2 (0x1<<2) // Autonegotiation resolved to 50g_kr2 + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_KR2_K2_SHIFT 2 + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation resolved to 40g_cr4 + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_CR4_K2_SHIFT 3 + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_KR4_K2 (0x1<<4) // Autonegotiation resolved to 40g_kr4 + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_KR4_K2_SHIFT 4 + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_GR_K2 (0x1<<5) // Autonegotiation resolved to 25g_gr + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_GR_K2_SHIFT 5 + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_CR_K2 (0x1<<6) // Autonegotiation resolved to 25g_cr + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_CR_K2_SHIFT 6 + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation resolved to 25g_kr + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_KR_K2_SHIFT 7 + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation resolved to 10g_kr + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_10G_KR_K2_SHIFT 8 + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_1G_KX_K2 (0x1<<9) // Autonegotiation resolved to 1g_kx + #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_1G_KX_K2_SHIFT 9 +#define NWS_REG_INT_MASK_1_K2 0x700194UL //Access:RW DataWidth:0xa // Multi Field Register. + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_CR2_K2 (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_50G_CR2 . + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_CR2_K2_SHIFT 1 + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_KR2_K2 (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_50G_KR2 . + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_KR2_K2_SHIFT 2 + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_CR4_K2 (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_40G_CR4 . + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_CR4_K2_SHIFT 3 + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_KR4_K2 (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_40G_KR4 . + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_KR4_K2_SHIFT 4 + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_GR_K2 (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_25G_GR . + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_GR_K2_SHIFT 5 + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_CR_K2 (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_25G_CR . + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_CR_K2_SHIFT 6 + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_KR_K2 (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_25G_KR . + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_KR_K2_SHIFT 7 + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_10G_KR_K2 (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_10G_KR . + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_10G_KR_K2_SHIFT 8 + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_1G_KX_K2 (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_1G_KX . + #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_1G_KX_K2_SHIFT 9 +#define NWS_REG_INT_STS_WR_1_K2 0x700198UL //Access:WR DataWidth:0xa // Multi Field Register. + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation resolved to 50g_cr2 + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_CR2_K2_SHIFT 1 + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_KR2_K2 (0x1<<2) // Autonegotiation resolved to 50g_kr2 + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_KR2_K2_SHIFT 2 + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation resolved to 40g_cr4 + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_CR4_K2_SHIFT 3 + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_KR4_K2 (0x1<<4) // Autonegotiation resolved to 40g_kr4 + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_KR4_K2_SHIFT 4 + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_GR_K2 (0x1<<5) // Autonegotiation resolved to 25g_gr + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_GR_K2_SHIFT 5 + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_CR_K2 (0x1<<6) // Autonegotiation resolved to 25g_cr + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_CR_K2_SHIFT 6 + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation resolved to 25g_kr + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_KR_K2_SHIFT 7 + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation resolved to 10g_kr + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_10G_KR_K2_SHIFT 8 + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_1G_KX_K2 (0x1<<9) // Autonegotiation resolved to 1g_kx + #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_1G_KX_K2_SHIFT 9 +#define NWS_REG_INT_STS_CLR_1_K2 0x70019cUL //Access:RC DataWidth:0xa // Multi Field Register. + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation resolved to 50g_cr2 + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_CR2_K2_SHIFT 1 + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_KR2_K2 (0x1<<2) // Autonegotiation resolved to 50g_kr2 + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_KR2_K2_SHIFT 2 + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation resolved to 40g_cr4 + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_CR4_K2_SHIFT 3 + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_KR4_K2 (0x1<<4) // Autonegotiation resolved to 40g_kr4 + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_KR4_K2_SHIFT 4 + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_GR_K2 (0x1<<5) // Autonegotiation resolved to 25g_gr + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_GR_K2_SHIFT 5 + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_CR_K2 (0x1<<6) // Autonegotiation resolved to 25g_cr + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_CR_K2_SHIFT 6 + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation resolved to 25g_kr + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_KR_K2_SHIFT 7 + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation resolved to 10g_kr + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_10G_KR_K2_SHIFT 8 + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_1G_KX_K2 (0x1<<9) // Autonegotiation resolved to 1g_kx + #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_1G_KX_K2_SHIFT 9 +#define NWS_REG_INT_STS_2_K2 0x7001a0UL //Access:R DataWidth:0xa // Multi Field Register. + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation resolved to 50g_cr2 + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_CR2_K2_SHIFT 1 + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_KR2_K2 (0x1<<2) // Autonegotiation resolved to 50g_kr2 + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_KR2_K2_SHIFT 2 + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation resolved to 40g_cr4 + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_CR4_K2_SHIFT 3 + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_KR4_K2 (0x1<<4) // Autonegotiation resolved to 40g_kr4 + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_KR4_K2_SHIFT 4 + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_GR_K2 (0x1<<5) // Autonegotiation resolved to 25g_gr + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_GR_K2_SHIFT 5 + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_CR_K2 (0x1<<6) // Autonegotiation resolved to 25g_cr + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_CR_K2_SHIFT 6 + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation resolved to 25g_kr + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_KR_K2_SHIFT 7 + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation resolved to 10g_kr + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_10G_KR_K2_SHIFT 8 + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_1G_KX_K2 (0x1<<9) // Autonegotiation resolved to 1g_kx + #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_1G_KX_K2_SHIFT 9 +#define NWS_REG_INT_MASK_2_K2 0x7001a4UL //Access:RW DataWidth:0xa // Multi Field Register. + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_CR2_K2 (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_50G_CR2 . + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_CR2_K2_SHIFT 1 + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_KR2_K2 (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_50G_KR2 . + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_KR2_K2_SHIFT 2 + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_CR4_K2 (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_40G_CR4 . + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_CR4_K2_SHIFT 3 + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_KR4_K2 (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_40G_KR4 . + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_KR4_K2_SHIFT 4 + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_GR_K2 (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_25G_GR . + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_GR_K2_SHIFT 5 + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_CR_K2 (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_25G_CR . + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_CR_K2_SHIFT 6 + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_KR_K2 (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_25G_KR . + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_KR_K2_SHIFT 7 + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_10G_KR_K2 (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_10G_KR . + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_10G_KR_K2_SHIFT 8 + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_1G_KX_K2 (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_1G_KX . + #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_1G_KX_K2_SHIFT 9 +#define NWS_REG_INT_STS_WR_2_K2 0x7001a8UL //Access:WR DataWidth:0xa // Multi Field Register. + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation resolved to 50g_cr2 + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_CR2_K2_SHIFT 1 + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_KR2_K2 (0x1<<2) // Autonegotiation resolved to 50g_kr2 + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_KR2_K2_SHIFT 2 + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation resolved to 40g_cr4 + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_CR4_K2_SHIFT 3 + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_KR4_K2 (0x1<<4) // Autonegotiation resolved to 40g_kr4 + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_KR4_K2_SHIFT 4 + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_GR_K2 (0x1<<5) // Autonegotiation resolved to 25g_gr + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_GR_K2_SHIFT 5 + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_CR_K2 (0x1<<6) // Autonegotiation resolved to 25g_cr + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_CR_K2_SHIFT 6 + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation resolved to 25g_kr + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_KR_K2_SHIFT 7 + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation resolved to 10g_kr + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_10G_KR_K2_SHIFT 8 + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_1G_KX_K2 (0x1<<9) // Autonegotiation resolved to 1g_kx + #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_1G_KX_K2_SHIFT 9 +#define NWS_REG_INT_STS_CLR_2_K2 0x7001acUL //Access:RC DataWidth:0xa // Multi Field Register. + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation resolved to 50g_cr2 + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_CR2_K2_SHIFT 1 + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_KR2_K2 (0x1<<2) // Autonegotiation resolved to 50g_kr2 + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_KR2_K2_SHIFT 2 + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation resolved to 40g_cr4 + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_CR4_K2_SHIFT 3 + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_KR4_K2 (0x1<<4) // Autonegotiation resolved to 40g_kr4 + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_KR4_K2_SHIFT 4 + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_GR_K2 (0x1<<5) // Autonegotiation resolved to 25g_gr + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_GR_K2_SHIFT 5 + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_CR_K2 (0x1<<6) // Autonegotiation resolved to 25g_cr + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_CR_K2_SHIFT 6 + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation resolved to 25g_kr + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_KR_K2_SHIFT 7 + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation resolved to 10g_kr + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_10G_KR_K2_SHIFT 8 + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_1G_KX_K2 (0x1<<9) // Autonegotiation resolved to 1g_kx + #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_1G_KX_K2_SHIFT 9 +#define NWS_REG_INT_STS_3_K2 0x7001b0UL //Access:R DataWidth:0xa // Multi Field Register. + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation resolved to 50g_cr2 + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_CR2_K2_SHIFT 1 + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_KR2_K2 (0x1<<2) // Autonegotiation resolved to 50g_kr2 + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_KR2_K2_SHIFT 2 + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation resolved to 40g_cr4 + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_CR4_K2_SHIFT 3 + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_KR4_K2 (0x1<<4) // Autonegotiation resolved to 40g_kr4 + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_KR4_K2_SHIFT 4 + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_GR_K2 (0x1<<5) // Autonegotiation resolved to 25g_gr + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_GR_K2_SHIFT 5 + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_CR_K2 (0x1<<6) // Autonegotiation resolved to 25g_cr + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_CR_K2_SHIFT 6 + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation resolved to 25g_kr + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_KR_K2_SHIFT 7 + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation resolved to 10g_kr + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_10G_KR_K2_SHIFT 8 + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_1G_KX_K2 (0x1<<9) // Autonegotiation resolved to 1g_kx + #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_1G_KX_K2_SHIFT 9 +#define NWS_REG_INT_MASK_3_K2 0x7001b4UL //Access:RW DataWidth:0xa // Multi Field Register. + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_CR2_K2 (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_50G_CR2 . + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_CR2_K2_SHIFT 1 + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_KR2_K2 (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_50G_KR2 . + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_KR2_K2_SHIFT 2 + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_CR4_K2 (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_40G_CR4 . + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_CR4_K2_SHIFT 3 + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_KR4_K2 (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_40G_KR4 . + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_KR4_K2_SHIFT 4 + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_GR_K2 (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_25G_GR . + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_GR_K2_SHIFT 5 + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_CR_K2 (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_25G_CR . + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_CR_K2_SHIFT 6 + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_KR_K2 (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_25G_KR . + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_KR_K2_SHIFT 7 + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_10G_KR_K2 (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_10G_KR . + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_10G_KR_K2_SHIFT 8 + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_1G_KX_K2 (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_1G_KX . + #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_1G_KX_K2_SHIFT 9 +#define NWS_REG_INT_STS_WR_3_K2 0x7001b8UL //Access:WR DataWidth:0xa // Multi Field Register. + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation resolved to 50g_cr2 + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_CR2_K2_SHIFT 1 + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_KR2_K2 (0x1<<2) // Autonegotiation resolved to 50g_kr2 + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_KR2_K2_SHIFT 2 + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation resolved to 40g_cr4 + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_CR4_K2_SHIFT 3 + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_KR4_K2 (0x1<<4) // Autonegotiation resolved to 40g_kr4 + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_KR4_K2_SHIFT 4 + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_GR_K2 (0x1<<5) // Autonegotiation resolved to 25g_gr + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_GR_K2_SHIFT 5 + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_CR_K2 (0x1<<6) // Autonegotiation resolved to 25g_cr + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_CR_K2_SHIFT 6 + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation resolved to 25g_kr + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_KR_K2_SHIFT 7 + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation resolved to 10g_kr + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_10G_KR_K2_SHIFT 8 + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_1G_KX_K2 (0x1<<9) // Autonegotiation resolved to 1g_kx + #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_1G_KX_K2_SHIFT 9 +#define NWS_REG_INT_STS_CLR_3_K2 0x7001bcUL //Access:RC DataWidth:0xa // Multi Field Register. + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_CR2_K2 (0x1<<1) // Autonegotiation resolved to 50g_cr2 + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_CR2_K2_SHIFT 1 + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_KR2_K2 (0x1<<2) // Autonegotiation resolved to 50g_kr2 + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_KR2_K2_SHIFT 2 + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_CR4_K2 (0x1<<3) // Autonegotiation resolved to 40g_cr4 + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_CR4_K2_SHIFT 3 + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_KR4_K2 (0x1<<4) // Autonegotiation resolved to 40g_kr4 + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_KR4_K2_SHIFT 4 + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_GR_K2 (0x1<<5) // Autonegotiation resolved to 25g_gr + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_GR_K2_SHIFT 5 + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_CR_K2 (0x1<<6) // Autonegotiation resolved to 25g_cr + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_CR_K2_SHIFT 6 + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_KR_K2 (0x1<<7) // Autonegotiation resolved to 25g_kr + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_KR_K2_SHIFT 7 + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_10G_KR_K2 (0x1<<8) // Autonegotiation resolved to 10g_kr + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_10G_KR_K2_SHIFT 8 + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_1G_KX_K2 (0x1<<9) // Autonegotiation resolved to 1g_kx + #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_1G_KX_K2_SHIFT 9 +#define NWS_REG_PRTY_MASK_H_0_K2_E5 0x700204UL //Access:RW DataWidth:0x1 // Multi Field Register. + #define NWS_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2 (0x1<<1) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY . + #define NWS_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_SHIFT 1 + #define NWS_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY . + #define NWS_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5_SHIFT 0 + #define NWS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2 (0x1<<0) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . + #define NWS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_SHIFT 0 + #define NWS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2 (0x1<<2) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . + #define NWS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT 2 + #define NWS_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2 (0x1<<3) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . + #define NWS_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_SHIFT 3 #define NWS_REG_MEM_ECC_EVENTS_K2_E5 0x700210UL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. -#define NWS_REG_NWS_CMU_K2_E5 0x720000UL //Access:RW DataWidth:0x8 // PHY Top registers = 0-0x7ff. CMU0 registers = 0x0800-0x0bff. CMU1 registers = 0x0c00-0x0fff. Reserved = 0x1000-0x17ff. LANE0 registers = 0x1800-0x1fff. LANE1 registers = 0x2000-0x27ff. LANE2 registers = 0x2800-0x2fff. LANE3 registers = 0x3000-0x37ff. Please see IPXACT_Capri_4l2c.xml for details. +#define NWS_REG_NWS_APB_E5 0x720000UL //Access:RW DataWidth:0x10 // PHY instance0 = 0x000-0x1fff. PHY instance1 = 0x2000-0x3fff. PHY instance2 = 0x4000-0x5fff. PHY instance3 = 0x6000-0x7fff. Please see HSS56GB_FX14 3.1 Regisisters +#define NWS_REG_NWS_APB_SIZE 32768 +#define NWS_REG_NWS_CMU_K2 0x720000UL //Access:RW DataWidth:0x8 // PHY Top registers = 0-0x7ff. CMU0 registers = 0x0800-0x0bff. CMU1 registers = 0x0c00-0x0fff. Reserved = 0x1000-0x17ff. LANE0 registers = 0x1800-0x1fff. LANE1 registers = 0x2000-0x27ff. LANE2 registers = 0x2800-0x2fff. LANE3 registers = 0x3000-0x37ff. Please see IPXACT_Capri_4l2c.xml for details. #define NWS_REG_NWS_CMU_SIZE 20479 -#define NWS_REG_NWS_DATA_RAM_ACCESS_K2_E5 0x740000UL //Access:RW DataWidth:0x20 // Used to load operating tables into data ram. Each register location is 4 bytes in ram. bits[31:24] = ram address [0] bits[23:16] = ram address [1] bits[15:8] = ram address [2] bits[7:0] = ram address [3] register 0 = ram location [3:0] register 1 = ram location [7:4] register 2 = ram location [11:8] +#define NWS_REG_NWS_DATA_RAM_ACCESS_K2 0x740000UL //Access:RW DataWidth:0x20 // Used to load operating tables into data ram. Each register location is 4 bytes in ram. bits[31:24] = ram address [0] bits[23:16] = ram address [1] bits[15:8] = ram address [2] bits[7:0] = ram address [3] register 0 = ram location [3:0] register 1 = ram location [7:4] register 2 = ram location [11:8] #define NWS_REG_NWS_DATA_RAM_ACCESS_SIZE 2048 -#define NWS_REG_NWS_PROGRAM_RAM_ACCESS_K2_E5 0x760000UL //Access:RW DataWidth:0x20 // Used to load operating firmware into program ram. Each register location is 4 bytes in ram. bits[31:24] = ram address [0] bits[23:16] = ram address [1] bits[15:8] = ram address [2] bits[7:0] = ram address [3] register 0 = ram location [3:0] register 1 = ram location [7:4] register 2 = ram location [11:8] +#define NWS_REG_NWS_PROGRAM_RAM_ACCESS_K2 0x760000UL //Access:RW DataWidth:0x20 // Used to load operating firmware into program ram. Each register location is 4 bytes in ram. bits[31:24] = ram address [0] bits[23:16] = ram address [1] bits[15:8] = ram address [2] bits[7:0] = ram address [3] register 0 = ram location [3:0] register 1 = ram location [7:4] register 2 = ram location [11:8] #define NWS_REG_NWS_PROGRAM_RAM_ACCESS_SIZE 32768 #define NWM_REG_INT_STS_K2_E5 0x800004UL //Access:R DataWidth:0x18 // Multi Field Register. #define NWM_REG_INT_STS_ADDRESS_ERROR_K2_E5 (0x1<<0) // Signals an unknown address to the rf module. @@ -63977,16 +67867,25 @@ #define PBF_REG_FC_DBG_SELECT 0xd800a8UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output #define PBF_REG_FC_DBG_DWORD_ENABLE 0xd800acUL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line) in the selected line (before shift).for selecting a line to output #define PBF_REG_FC_DBG_SHIFT 0xd800b0UL //Access:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) right shifting of the selected line (after the masking). +#define PBF_REG_FC_DBG_SELECT_B_E5 0xd800b4UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output +#define PBF_REG_FC_DBG_DWORD_ENABLE_B_E5 0xd800b8UL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line) in the selected line (before shift).for selecting a line to output +#define PBF_REG_FC_DBG_SHIFT_B_E5 0xd800bcUL //Access:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) right shifting of the selected line (after the masking). #define PBF_REG_FC_DBG_OUT_DATA 0xd800c0UL //Access:WB_R DataWidth:0x100 // Dbgmux output data #define PBF_REG_FC_DBG_OUT_DATA_SIZE 8 #define PBF_REG_FC_DBG_FORCE_VALID 0xd800e0UL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line) / qword (256bit line) (before shift). #define PBF_REG_FC_DBG_FORCE_FRAME 0xd800e4UL //Access:RW DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift). #define PBF_REG_FC_DBG_OUT_VALID 0xd800e8UL //Access:R DataWidth:0x8 // Dbgmux output valid per Dword #define PBF_REG_FC_DBG_OUT_FRAME 0xd800ecUL //Access:R DataWidth:0x8 // Dbgmux output frame per Dword +#define PBF_REG_FC_DBG_FORCE_VALID_B_E5 0xd800f0UL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line) / qword (256bit line) (before shift). +#define PBF_REG_FC_DBG_FORCE_FRAME_B_E5 0xd800f4UL //Access:RW DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift). +#define PBF_REG_FC_DBG_OUT_VALID_B_E5 0xd800f8UL //Access:R DataWidth:0x8 // Dbgmux output valid per Dword +#define PBF_REG_FC_DBG_OUT_FRAME_B_E5 0xd800fcUL //Access:R DataWidth:0x8 // Dbgmux output frame per Dword #define PBF_REG_MEMCTRL_WR_RD_N_BB 0xd80100UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST #define PBF_REG_MEMCTRL_CMD_BB 0xd80104UL //Access:RW DataWidth:0x8 // command to CPU BIST #define PBF_REG_MEMCTRL_ADDRESS_BB 0xd80108UL //Access:RW DataWidth:0x8 // address to CPU BIST #define PBF_REG_MEMCTRL_STATUS 0xd8010cUL //Access:R DataWidth:0x20 // obsolete +#define PBF_REG_FC_DBG_OUT_DATA_B_E5 0xd80160UL //Access:WB_R DataWidth:0x100 // Dbgmux output data +#define PBF_REG_FC_DBG_OUT_DATA_B_SIZE 8 #define PBF_REG_INT_STS 0xd80180UL //Access:R DataWidth:0x1 // Multi Field Register. #define PBF_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define PBF_REG_INT_STS_ADDRESS_ERROR_SHIFT 0 @@ -64002,15 +67901,81 @@ #define PBF_REG_PRTY_MASK 0xd80194UL //Access:RW DataWidth:0x1 // Multi Field Register. #define PBF_REG_PRTY_MASK_DATAPATH_REGISTERS (0x1<<0) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS.DATAPATH_REGISTERS . #define PBF_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT 0 -#define PBF_REG_PRTY_MASK_H_0_BB_K2 0xd80204UL //Access:RW DataWidth:0x1f // Multi Field Register. +#define PBF_REG_PRTY_MASK_H_0 0xd80204UL //Access:RW DataWidth:0x1f // Multi Field Register. + #define PBF_REG_PRTY_MASK_H_0_MEM049_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM049_I_ECC_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM049_I_ECC_RF_INT_E5_SHIFT 0 + #define PBF_REG_PRTY_MASK_H_0_MEM050_I_ECC_RF_INT_E5 (0x1<<1) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM050_I_ECC_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM050_I_ECC_RF_INT_E5_SHIFT 1 + #define PBF_REG_PRTY_MASK_H_0_MEM048_I_ECC_RF_INT_E5 (0x1<<2) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM048_I_ECC_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM048_I_ECC_RF_INT_E5_SHIFT 2 + #define PBF_REG_PRTY_MASK_H_0_MEM040_I_ECC_RF_INT_E5 (0x1<<3) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM040_I_ECC_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM040_I_ECC_RF_INT_E5_SHIFT 3 + #define PBF_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2 (0x1<<3) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2_SHIFT 3 + #define PBF_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_E5 (0x1<<4) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_E5_SHIFT 4 + #define PBF_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_E5 (0x1<<5) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM022_I_ECC_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_E5_SHIFT 5 + #define PBF_REG_PRTY_MASK_H_0_MEM011_I_ECC_0_RF_INT_E5 (0x1<<6) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM011_I_ECC_0_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM011_I_ECC_0_RF_INT_E5_SHIFT 6 + #define PBF_REG_PRTY_MASK_H_0_MEM011_I_ECC_1_RF_INT_E5 (0x1<<7) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM011_I_ECC_1_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM011_I_ECC_1_RF_INT_E5_SHIFT 7 + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_0_RF_INT_E5 (0x1<<8) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM016_I_ECC_0_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_0_RF_INT_E5_SHIFT 8 + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_1_RF_INT_E5 (0x1<<9) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM016_I_ECC_1_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_1_RF_INT_E5_SHIFT 9 + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_2_RF_INT_E5 (0x1<<10) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM016_I_ECC_2_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_2_RF_INT_E5_SHIFT 10 + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_3_RF_INT_E5 (0x1<<11) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM016_I_ECC_3_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_3_RF_INT_E5_SHIFT 11 + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_4_RF_INT_E5 (0x1<<12) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM016_I_ECC_4_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_4_RF_INT_E5_SHIFT 12 + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_5_RF_INT_E5 (0x1<<13) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM016_I_ECC_5_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_5_RF_INT_E5_SHIFT 13 + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_6_RF_INT_E5 (0x1<<14) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM016_I_ECC_6_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_6_RF_INT_E5_SHIFT 14 + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_7_RF_INT_E5 (0x1<<15) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM016_I_ECC_7_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_7_RF_INT_E5_SHIFT 15 + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_8_RF_INT_E5 (0x1<<16) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM016_I_ECC_8_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_8_RF_INT_E5_SHIFT 16 + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_9_RF_INT_E5 (0x1<<17) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM016_I_ECC_9_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_9_RF_INT_E5_SHIFT 17 + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_10_RF_INT_E5 (0x1<<18) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM016_I_ECC_10_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_10_RF_INT_E5_SHIFT 18 + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_11_RF_INT_E5 (0x1<<19) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM016_I_ECC_11_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_11_RF_INT_E5_SHIFT 19 + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_12_RF_INT_E5 (0x1<<20) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM016_I_ECC_12_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_12_RF_INT_E5_SHIFT 20 + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_13_RF_INT_E5 (0x1<<21) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM016_I_ECC_13_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_13_RF_INT_E5_SHIFT 21 + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_14_RF_INT_E5 (0x1<<22) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM016_I_ECC_14_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_14_RF_INT_E5_SHIFT 22 + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_15_RF_INT_E5 (0x1<<23) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM016_I_ECC_15_RF_INT . + #define PBF_REG_PRTY_MASK_H_0_MEM016_I_ECC_15_RF_INT_E5_SHIFT 23 + #define PBF_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM047_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY_E5_SHIFT 24 + #define PBF_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM046_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY_E5_SHIFT 25 + #define PBF_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM045_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY_E5_SHIFT 26 + #define PBF_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_E5_SHIFT 27 + #define PBF_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_K2 (0x1<<24) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_K2_SHIFT 24 + #define PBF_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_E5_SHIFT 28 + #define PBF_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_K2 (0x1<<25) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_K2_SHIFT 25 + #define PBF_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_E5_SHIFT 29 + #define PBF_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_E5_SHIFT 30 #define PBF_REG_PRTY_MASK_H_0_MEM041_I_ECC_RF_INT_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM041_I_ECC_RF_INT . #define PBF_REG_PRTY_MASK_H_0_MEM041_I_ECC_RF_INT_BB_K2_SHIFT 0 #define PBF_REG_PRTY_MASK_H_0_MEM042_I_ECC_RF_INT_BB_K2 (0x1<<1) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM042_I_ECC_RF_INT . #define PBF_REG_PRTY_MASK_H_0_MEM042_I_ECC_RF_INT_BB_K2_SHIFT 1 #define PBF_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT_BB_K2 (0x1<<2) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM033_I_ECC_RF_INT . #define PBF_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT_BB_K2_SHIFT 2 - #define PBF_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2 (0x1<<3) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT . - #define PBF_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_K2_SHIFT 3 #define PBF_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT_BB_K2 (0x1<<4) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM018_I_ECC_RF_INT . #define PBF_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT_BB_K2_SHIFT 4 #define PBF_REG_PRTY_MASK_H_0_MEM009_I_ECC_0_RF_INT_BB_K2 (0x1<<5) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM009_I_ECC_0_RF_INT . @@ -64051,10 +68016,6 @@ #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_15_RF_INT_BB_K2_SHIFT 22 #define PBF_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB_K2 (0x1<<23) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY . #define PBF_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB_K2_SHIFT 23 - #define PBF_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_K2 (0x1<<24) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_K2_SHIFT 24 - #define PBF_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_K2 (0x1<<25) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_K2_SHIFT 25 #define PBF_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_K2 (0x1<<26) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY . #define PBF_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_K2_SHIFT 26 #define PBF_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_K2 (0x1<<27) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY . @@ -64065,72 +68026,195 @@ #define PBF_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2_SHIFT 29 #define PBF_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_K2 (0x1<<30) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . #define PBF_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_K2_SHIFT 30 -#define PBF_REG_PRTY_MASK_H_1_BB_K2 0xd80214UL //Access:RW DataWidth:0x1b // Multi Field Register. - #define PBF_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_K2_SHIFT 0 - #define PBF_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_BB_K2 (0x1<<1) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM023_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_BB_K2_SHIFT 1 - #define PBF_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_K2 (0x1<<2) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_K2_SHIFT 2 - #define PBF_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_K2 (0x1<<3) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_K2_SHIFT 3 - #define PBF_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_K2 (0x1<<4) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_K2_SHIFT 4 +#define PBF_REG_PRTY_MASK_H_1 0xd80214UL //Access:RW DataWidth:0x1f // Multi Field Register. + #define PBF_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_BB_K2 (0x1<<21) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_BB_K2_SHIFT 21 + #define PBF_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_E5_SHIFT 0 + #define PBF_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_BB_K2 (0x1<<23) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_BB_K2_SHIFT 23 + #define PBF_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_E5_SHIFT 1 + #define PBF_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_BB_K2 (0x1<<10) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_BB_K2_SHIFT 10 + #define PBF_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_E5_SHIFT 2 + #define PBF_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_E5_SHIFT 3 + #define PBF_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_K2 (0x1<<12) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_K2_SHIFT 12 + #define PBF_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_E5_SHIFT 4 + #define PBF_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_K2 (0x1<<11) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_K2_SHIFT 11 + #define PBF_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_E5_SHIFT 5 + #define PBF_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_BB_K2 (0x1<<19) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_BB_K2_SHIFT 19 + #define PBF_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_E5_SHIFT 6 + #define PBF_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_BB_K2 (0x1<<20) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_BB_K2_SHIFT 20 + #define PBF_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_E5_SHIFT 7 #define PBF_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_K2 (0x1<<5) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . #define PBF_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_K2_SHIFT 5 + #define PBF_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5_SHIFT 8 + #define PBF_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_K2 (0x1<<4) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_K2_SHIFT 4 + #define PBF_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5_SHIFT 9 + #define PBF_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5_SHIFT 10 + #define PBF_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB_K2 (0x1<<16) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB_K2_SHIFT 16 + #define PBF_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_E5_SHIFT 11 + #define PBF_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_BB_K2 (0x1<<9) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_BB_K2_SHIFT 9 + #define PBF_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_E5_SHIFT 12 + #define PBF_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM005_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_BB_K2_SHIFT 8 + #define PBF_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM005_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_E5_SHIFT 13 #define PBF_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_BB_K2 (0x1<<6) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY . #define PBF_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_BB_K2_SHIFT 6 + #define PBF_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_E5_SHIFT 14 #define PBF_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_BB_K2 (0x1<<7) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY . #define PBF_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_BB_K2_SHIFT 7 - #define PBF_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_BB_K2 (0x1<<8) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM005_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_BB_K2_SHIFT 8 - #define PBF_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_BB_K2 (0x1<<9) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_BB_K2_SHIFT 9 - #define PBF_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_BB_K2 (0x1<<10) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_BB_K2_SHIFT 10 - #define PBF_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_K2 (0x1<<11) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_K2_SHIFT 11 - #define PBF_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_K2 (0x1<<12) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_K2_SHIFT 12 + #define PBF_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_E5_SHIFT 15 + #define PBF_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM034_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_E5_SHIFT 16 + #define PBF_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_E5_SHIFT 17 + #define PBF_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_E5_SHIFT 18 + #define PBF_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_BB_K2 (0x1<<1) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM023_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_BB_K2_SHIFT 1 + #define PBF_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM023_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_E5_SHIFT 19 + #define PBF_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_K2 (0x1<<3) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_K2_SHIFT 3 + #define PBF_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_E5_SHIFT 20 + #define PBF_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_K2 (0x1<<2) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_K2_SHIFT 2 + #define PBF_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_E5_SHIFT 21 + #define PBF_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_K2 (0x1<<18) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_K2_SHIFT 18 + #define PBF_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_E5_SHIFT 22 + #define PBF_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_E5_SHIFT 23 + #define PBF_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_K2 (0x1<<26) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_K2_SHIFT 26 + #define PBF_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_E5_SHIFT 24 + #define PBF_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_K2 (0x1<<24) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_K2_SHIFT 24 + #define PBF_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_E5_SHIFT 25 + #define PBF_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_K2 (0x1<<25) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_K2_SHIFT 25 + #define PBF_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_E5_SHIFT 26 + #define PBF_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM030_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_E5_SHIFT 27 + #define PBF_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_E5_SHIFT 28 + #define PBF_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_E5_SHIFT 29 + #define PBF_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM043_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_E5_SHIFT 30 + #define PBF_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_K2_SHIFT 0 #define PBF_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_K2 (0x1<<13) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY . #define PBF_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_K2_SHIFT 13 #define PBF_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_BB_K2 (0x1<<14) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY . #define PBF_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_BB_K2_SHIFT 14 #define PBF_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_K2 (0x1<<15) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY . #define PBF_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_K2_SHIFT 15 - #define PBF_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB_K2 (0x1<<16) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB_K2_SHIFT 16 #define PBF_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_K2 (0x1<<17) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY . #define PBF_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_K2_SHIFT 17 - #define PBF_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_K2 (0x1<<18) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_K2_SHIFT 18 - #define PBF_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_BB_K2 (0x1<<19) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_BB_K2_SHIFT 19 - #define PBF_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_BB_K2 (0x1<<20) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_BB_K2_SHIFT 20 - #define PBF_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_BB_K2 (0x1<<21) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_BB_K2_SHIFT 21 #define PBF_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_K2 (0x1<<22) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY . #define PBF_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_K2_SHIFT 22 - #define PBF_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_BB_K2 (0x1<<23) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_BB_K2_SHIFT 23 - #define PBF_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_K2 (0x1<<24) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_K2_SHIFT 24 - #define PBF_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_K2 (0x1<<25) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_K2_SHIFT 25 - #define PBF_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_K2 (0x1<<26) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY . - #define PBF_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_K2_SHIFT 26 #define PBF_REG_MEM041_RF_ECC_ERROR_CONNECT_BB_K2 0xd80220UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PBF_REG_PRTY_MASK_H_2_E5 0xd80224UL //Access:RW DataWidth:0x4 // Multi Field Register. + #define PBF_REG_PRTY_MASK_H_2_MEM042_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_2.MEM042_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_2_MEM042_I_MEM_PRTY_E5_SHIFT 0 + #define PBF_REG_PRTY_MASK_H_2_MEM018_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_2.MEM018_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_2_MEM018_I_MEM_PRTY_E5_SHIFT 1 + #define PBF_REG_PRTY_MASK_H_2_MEM019_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_2.MEM019_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_2_MEM019_I_MEM_PRTY_E5_SHIFT 2 + #define PBF_REG_PRTY_MASK_H_2_MEM017_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_2.MEM017_I_MEM_PRTY . + #define PBF_REG_PRTY_MASK_H_2_MEM017_I_MEM_PRTY_E5_SHIFT 3 #define PBF_REG_MEM042_RF_ECC_ERROR_CONNECT_BB_K2 0xd80224UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PBF_REG_MEM049_RF_ECC_ERROR_CONNECT_E5 0xd80230UL //Access:W DataWidth:0x14 // Register to generate up to two ECC errors on the next write to memory: pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.rf_ecc_error_connect Includes 2 words of 10 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 256. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PBF_REG_MEM050_RF_ECC_ERROR_CONNECT_E5 0xd80234UL //Access:W DataWidth:0x14 // Register to generate up to two ECC errors on the next write to memory: pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.rf_ecc_error_connect Includes 2 words of 10 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 256. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PBF_REG_MEM048_RF_ECC_ERROR_CONNECT_E5 0xd80238UL //Access:W DataWidth:0xe // Register to generate up to two ECC errors on the next write to memory: pbf.i_pbf_ycmd_qs.i_ycmd_hdr.rf_ecc_error_connect Includes 2 words of 7 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 33. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define PBF_REG_MEM_ECC_ENABLE_0_BB_K2 0xd80228UL //Access:RW DataWidth:0x17 // Multi Field Register. +#define PBF_REG_MEM_ECC_ENABLE_0_E5 0xd8023cUL //Access:RW DataWidth:0x18 // Multi Field Register. + #define PBF_REG_MEM_ECC_ENABLE_0_MEM049_I_ECC_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_qs_mem_even + #define PBF_REG_MEM_ECC_ENABLE_0_MEM049_I_ECC_EN_E5_SHIFT 0 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM050_I_ECC_EN_E5 (0x1<<1) // Enable ECC for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_qs_mem_odd + #define PBF_REG_MEM_ECC_ENABLE_0_MEM050_I_ECC_EN_E5_SHIFT 1 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM048_I_ECC_EN_E5 (0x1<<2) // Enable ECC for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_hdr.i_ecc in module pbf_mem_ycmd_hdr + #define PBF_REG_MEM_ECC_ENABLE_0_MEM048_I_ECC_EN_E5_SHIFT 2 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM040_I_ECC_EN_E5 (0x1<<3) // Enable ECC for memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsing_info_database_new + #define PBF_REG_MEM_ECC_ENABLE_0_MEM040_I_ECC_EN_E5_SHIFT 3 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2 (0x1<<3) // Enable ECC for memory ecc instance pbf.i_pb1_db.i_ecc in module pbf_mem_pb1_data_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2_SHIFT 3 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_E5 (0x1<<4) // Enable ECC for memory ecc instance pbf.i_pb1_db_new.i_ecc in module pbf_mem_pb1_data_buffer_new + #define PBF_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_E5_SHIFT 4 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN_E5 (0x1<<5) // Enable ECC for memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_header_database + #define PBF_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_EN_E5_SHIFT 5 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_0_EN_E5 (0x1<<6) // Enable ECC for memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_0_EN_E5_SHIFT 6 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_1_EN_E5 (0x1<<7) // Enable ECC for memory ecc instance pbf.i_pb2_l1.i_ecc_1 in module pbf_mem_pb2_l1 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_1_EN_E5_SHIFT 7 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_0_EN_E5 (0x1<<8) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_0 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_0_EN_E5_SHIFT 8 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_1_EN_E5 (0x1<<9) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_1 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_1_EN_E5_SHIFT 9 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_2_EN_E5 (0x1<<10) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_2 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_2_EN_E5_SHIFT 10 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_3_EN_E5 (0x1<<11) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_3 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_3_EN_E5_SHIFT 11 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_4_EN_E5 (0x1<<12) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_4 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_4_EN_E5_SHIFT 12 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_5_EN_E5 (0x1<<13) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_5 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_5_EN_E5_SHIFT 13 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_6_EN_E5 (0x1<<14) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_6 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_6_EN_E5_SHIFT 14 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_7_EN_E5 (0x1<<15) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_7 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_7_EN_E5_SHIFT 15 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_8_EN_E5 (0x1<<16) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_8 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_8_EN_E5_SHIFT 16 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_9_EN_E5 (0x1<<17) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_9 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_9_EN_E5_SHIFT 17 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_10_EN_E5 (0x1<<18) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_10 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_10_EN_E5_SHIFT 18 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_11_EN_E5 (0x1<<19) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_11 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_11_EN_E5_SHIFT 19 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_12_EN_E5 (0x1<<20) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_12 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_12_EN_E5_SHIFT 20 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_13_EN_E5 (0x1<<21) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_13 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_13_EN_E5_SHIFT 21 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_14_EN_E5 (0x1<<22) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_14 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_14_EN_E5_SHIFT 22 + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_15_EN_E5 (0x1<<23) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ENABLE_0_MEM016_I_ECC_15_EN_E5_SHIFT 23 #define PBF_REG_MEM_ECC_ENABLE_0_MEM041_I_ECC_EN_BB_K2 (0x1<<0) // Enable ECC for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_qs_mem_even #define PBF_REG_MEM_ECC_ENABLE_0_MEM041_I_ECC_EN_BB_K2_SHIFT 0 #define PBF_REG_MEM_ECC_ENABLE_0_MEM042_I_ECC_EN_BB_K2 (0x1<<1) // Enable ECC for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_qs_mem_odd #define PBF_REG_MEM_ECC_ENABLE_0_MEM042_I_ECC_EN_BB_K2_SHIFT 1 #define PBF_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_EN_BB_K2 (0x1<<2) // Enable ECC for memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsing_info_database #define PBF_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_EN_BB_K2_SHIFT 2 - #define PBF_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2 (0x1<<3) // Enable ECC for memory ecc instance pbf.i_pb1_db.i_ecc in module pbf_mem_pb1_data_buffer - #define PBF_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_BB_K2_SHIFT 3 #define PBF_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN_BB_K2 (0x1<<4) // Enable ECC for memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_header_database #define PBF_REG_MEM_ECC_ENABLE_0_MEM018_I_ECC_EN_BB_K2_SHIFT 4 #define PBF_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_0_EN_BB_K2 (0x1<<5) // Enable ECC for memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1 @@ -64170,14 +68254,63 @@ #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_15_EN_BB_K2 (0x1<<22) // Enable ECC for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif_buffer #define PBF_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_15_EN_BB_K2_SHIFT 22 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_BB_K2 0xd8022cUL //Access:RW DataWidth:0x17 // Multi Field Register. +#define PBF_REG_MEM_ECC_PARITY_ONLY_0_E5 0xd80240UL //Access:RW DataWidth:0x18 // Multi Field Register. + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM049_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_qs_mem_even + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM049_I_ECC_PRTY_E5_SHIFT 0 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM050_I_ECC_PRTY_E5 (0x1<<1) // Set parity only for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_qs_mem_odd + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM050_I_ECC_PRTY_E5_SHIFT 1 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM048_I_ECC_PRTY_E5 (0x1<<2) // Set parity only for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_hdr.i_ecc in module pbf_mem_ycmd_hdr + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM048_I_ECC_PRTY_E5_SHIFT 2 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM040_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsing_info_database_new + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM040_I_ECC_PRTY_E5_SHIFT 3 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2 (0x1<<3) // Set parity only for memory ecc instance pbf.i_pb1_db.i_ecc in module pbf_mem_pb1_data_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2_SHIFT 3 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_E5 (0x1<<4) // Set parity only for memory ecc instance pbf.i_pb1_db_new.i_ecc in module pbf_mem_pb1_data_buffer_new + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_E5_SHIFT 4 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY_E5 (0x1<<5) // Set parity only for memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_header_database + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_PRTY_E5_SHIFT 5 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_0_PRTY_E5 (0x1<<6) // Set parity only for memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_0_PRTY_E5_SHIFT 6 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_1_PRTY_E5 (0x1<<7) // Set parity only for memory ecc instance pbf.i_pb2_l1.i_ecc_1 in module pbf_mem_pb2_l1 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_1_PRTY_E5_SHIFT 7 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_0_PRTY_E5 (0x1<<8) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_0 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_0_PRTY_E5_SHIFT 8 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_1_PRTY_E5 (0x1<<9) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_1 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_1_PRTY_E5_SHIFT 9 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_2_PRTY_E5 (0x1<<10) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_2 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_2_PRTY_E5_SHIFT 10 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_3_PRTY_E5 (0x1<<11) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_3 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_3_PRTY_E5_SHIFT 11 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_4_PRTY_E5 (0x1<<12) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_4 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_4_PRTY_E5_SHIFT 12 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_5_PRTY_E5 (0x1<<13) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_5 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_5_PRTY_E5_SHIFT 13 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_6_PRTY_E5 (0x1<<14) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_6 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_6_PRTY_E5_SHIFT 14 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_7_PRTY_E5 (0x1<<15) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_7 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_7_PRTY_E5_SHIFT 15 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_8_PRTY_E5 (0x1<<16) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_8 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_8_PRTY_E5_SHIFT 16 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_9_PRTY_E5 (0x1<<17) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_9 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_9_PRTY_E5_SHIFT 17 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_10_PRTY_E5 (0x1<<18) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_10 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_10_PRTY_E5_SHIFT 18 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_11_PRTY_E5 (0x1<<19) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_11 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_11_PRTY_E5_SHIFT 19 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_12_PRTY_E5 (0x1<<20) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_12 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_12_PRTY_E5_SHIFT 20 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_13_PRTY_E5 (0x1<<21) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_13 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_13_PRTY_E5_SHIFT 21 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_14_PRTY_E5 (0x1<<22) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_14 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_14_PRTY_E5_SHIFT 22 + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_15_PRTY_E5 (0x1<<23) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM016_I_ECC_15_PRTY_E5_SHIFT 23 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM041_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_qs_mem_even #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM041_I_ECC_PRTY_BB_K2_SHIFT 0 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM042_I_ECC_PRTY_BB_K2 (0x1<<1) // Set parity only for memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_qs_mem_odd #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM042_I_ECC_PRTY_BB_K2_SHIFT 1 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_PRTY_BB_K2 (0x1<<2) // Set parity only for memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsing_info_database #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_PRTY_BB_K2_SHIFT 2 - #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2 (0x1<<3) // Set parity only for memory ecc instance pbf.i_pb1_db.i_ecc in module pbf_mem_pb1_data_buffer - #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_BB_K2_SHIFT 3 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY_BB_K2 (0x1<<4) // Set parity only for memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_header_database #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM018_I_ECC_PRTY_BB_K2_SHIFT 4 #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_0_PRTY_BB_K2 (0x1<<5) // Set parity only for memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1 @@ -64217,14 +68350,63 @@ #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_15_PRTY_BB_K2 (0x1<<22) // Set parity only for memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif_buffer #define PBF_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_15_PRTY_BB_K2_SHIFT 22 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2 0xd80230UL //Access:RC DataWidth:0x17 // Multi Field Register. +#define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_E5 0xd80244UL //Access:RC DataWidth:0x18 // Multi Field Register. + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM049_I_ECC_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_qs_mem_even + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM049_I_ECC_CORRECT_E5_SHIFT 0 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM050_I_ECC_CORRECT_E5 (0x1<<1) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_qs_mem_odd + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM050_I_ECC_CORRECT_E5_SHIFT 1 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM048_I_ECC_CORRECT_E5 (0x1<<2) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_hdr.i_ecc in module pbf_mem_ycmd_hdr + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM048_I_ECC_CORRECT_E5_SHIFT 2 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM040_I_ECC_CORRECT_E5 (0x1<<3) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsing_info_database_new + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM040_I_ECC_CORRECT_E5_SHIFT 3 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2 (0x1<<3) // Record if a correctable error occurred on memory ecc instance pbf.i_pb1_db.i_ecc in module pbf_mem_pb1_data_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2_SHIFT 3 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_E5 (0x1<<4) // Record if a correctable error occurred on memory ecc instance pbf.i_pb1_db_new.i_ecc in module pbf_mem_pb1_data_buffer_new + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_E5_SHIFT 4 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT_E5 (0x1<<5) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_header_database + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_CORRECT_E5_SHIFT 5 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_0_CORRECT_E5 (0x1<<6) // Record if a correctable error occurred on memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_0_CORRECT_E5_SHIFT 6 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_1_CORRECT_E5 (0x1<<7) // Record if a correctable error occurred on memory ecc instance pbf.i_pb2_l1.i_ecc_1 in module pbf_mem_pb2_l1 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_1_CORRECT_E5_SHIFT 7 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_0_CORRECT_E5 (0x1<<8) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_0 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_0_CORRECT_E5_SHIFT 8 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_1_CORRECT_E5 (0x1<<9) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_1 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_1_CORRECT_E5_SHIFT 9 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_2_CORRECT_E5 (0x1<<10) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_2 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_2_CORRECT_E5_SHIFT 10 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_3_CORRECT_E5 (0x1<<11) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_3 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_3_CORRECT_E5_SHIFT 11 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_4_CORRECT_E5 (0x1<<12) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_4 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_4_CORRECT_E5_SHIFT 12 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_5_CORRECT_E5 (0x1<<13) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_5 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_5_CORRECT_E5_SHIFT 13 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_6_CORRECT_E5 (0x1<<14) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_6 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_6_CORRECT_E5_SHIFT 14 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_7_CORRECT_E5 (0x1<<15) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_7 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_7_CORRECT_E5_SHIFT 15 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_8_CORRECT_E5 (0x1<<16) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_8 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_8_CORRECT_E5_SHIFT 16 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_9_CORRECT_E5 (0x1<<17) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_9 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_9_CORRECT_E5_SHIFT 17 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_10_CORRECT_E5 (0x1<<18) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_10 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_10_CORRECT_E5_SHIFT 18 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_11_CORRECT_E5 (0x1<<19) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_11 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_11_CORRECT_E5_SHIFT 19 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_12_CORRECT_E5 (0x1<<20) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_12 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_12_CORRECT_E5_SHIFT 20 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_13_CORRECT_E5 (0x1<<21) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_13 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_13_CORRECT_E5_SHIFT 21 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_14_CORRECT_E5 (0x1<<22) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_14 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_14_CORRECT_E5_SHIFT 22 + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_15_CORRECT_E5 (0x1<<23) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif_buffer + #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM016_I_ECC_15_CORRECT_E5_SHIFT 23 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM041_I_ECC_CORRECT_BB_K2 (0x1<<0) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_ecc in module pbf_mem_ycmd_qs_mem_even #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM041_I_ECC_CORRECT_BB_K2_SHIFT 0 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM042_I_ECC_CORRECT_BB_K2 (0x1<<1) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_ecc in module pbf_mem_ycmd_qs_mem_odd #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM042_I_ECC_CORRECT_BB_K2_SHIFT 1 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_CORRECT_BB_K2 (0x1<<2) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_ecc in module pbf_mem_parsing_info_database #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_CORRECT_BB_K2_SHIFT 2 - #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2 (0x1<<3) // Record if a correctable error occurred on memory ecc instance pbf.i_pb1_db.i_ecc in module pbf_mem_pb1_data_buffer - #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_BB_K2_SHIFT 3 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT_BB_K2 (0x1<<4) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_ecc in module pbf_mem_header_database #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM018_I_ECC_CORRECT_BB_K2_SHIFT 4 #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM009_I_ECC_0_CORRECT_BB_K2 (0x1<<5) // Record if a correctable error occurred on memory ecc instance pbf.i_pb2_l1.i_ecc_0 in module pbf_mem_pb2_l1 @@ -64264,6 +68446,7 @@ #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_15_CORRECT_BB_K2 (0x1<<22) // Record if a correctable error occurred on memory ecc instance pbf.i_pbf_btbif.i_btbif_buff.i_ecc_15 in module pbf_mem_btbif_buffer #define PBF_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_15_CORRECT_BB_K2_SHIFT 22 #define PBF_REG_MEM_ECC_EVENTS_BB_K2 0xd80234UL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. +#define PBF_REG_MEM_ECC_EVENTS_E5 0xd80248UL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. #define PBF_REG_PXP_REQ_IF_INIT_CRD 0xd80400UL //Access:RW DataWidth:0x3 // PXP read request interface initial credit - transoriented. #define PBF_REG_TDIF_PASS_THROUGH_INIT_CRD 0xd80404UL //Access:RW DataWidth:0x6 // TDIF pass-through command interface initial credit. #define PBF_REG_TDIF_NON_PASS_THROUGH_INIT_CRD 0xd80408UL //Access:RW DataWidth:0x6 // TDIF non_pass-through command interface initial credit. @@ -64372,6 +68555,90 @@ #define PBF_REG_NUM_HITS_IN_SAL_SIZE 2 #define PBF_REG_NUM_LOOKUPS_IN_SAL_E5 0xd80540UL //Access:ST DataWidth:0x38 // Number of lookup requests for Same as Last Lookup #define PBF_REG_NUM_LOOKUPS_IN_SAL_SIZE 2 +#define PBF_REG_MPLS_IPV4_LABEL_E5 0xd80548UL //Access:RW DataWidth:0x14 // mpls_ipv4_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set. +#define PBF_REG_MPLS_IPV6_LABEL_E5 0xd8054cUL //Access:RW DataWidth:0x14 // mpls_ipv6_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set. +#define PBF_REG_MPLS_TYPES_E5 0xd80550UL //Access:RW DataWidth:0x20 // Multi Field Register. + #define PBF_REG_MPLS_TYPES_MPLS_UNI_TYPE_E5 (0xffff<<0) // Ethernet Type of MPLS + #define PBF_REG_MPLS_TYPES_MPLS_UNI_TYPE_E5_SHIFT 0 + #define PBF_REG_MPLS_TYPES_MPLS_MULTI_TYPE_E5 (0xffff<<16) // Ethernet Type of MPLS + #define PBF_REG_MPLS_TYPES_MPLS_MULTI_TYPE_E5_SHIFT 16 +#define PBF_REG_MPLS_COMPARE_LABEL_E5 0xd80554UL //Access:RW DataWidth:0x1 // mpls_ipv6_label/mpls_ipv4_label to be compared Vs the label field of the last mpls label if mpls_compare_label is set. This is enabled per PF +#define PBF_REG_IPV6_EXT_HDR_TYPES_0_3_E5 0xd80558UL //Access:RW DataWidth:0x20 // Multi Field Register. + #define PBF_REG_IPV6_EXT_HDR_TYPES_0_3_IPV6_EXT_UNIFORM_HDR_TYPE_0_E5 (0xff<<0) // ipv6 extension uniform header type 0 + #define PBF_REG_IPV6_EXT_HDR_TYPES_0_3_IPV6_EXT_UNIFORM_HDR_TYPE_0_E5_SHIFT 0 + #define PBF_REG_IPV6_EXT_HDR_TYPES_0_3_IPV6_EXT_UNIFORM_HDR_TYPE_1_E5 (0xff<<8) // ipv6 extension uniform header type 1 + #define PBF_REG_IPV6_EXT_HDR_TYPES_0_3_IPV6_EXT_UNIFORM_HDR_TYPE_1_E5_SHIFT 8 + #define PBF_REG_IPV6_EXT_HDR_TYPES_0_3_IPV6_EXT_UNIFORM_HDR_TYPE_2_E5 (0xff<<16) // ipv6 extension uniform header type 2 + #define PBF_REG_IPV6_EXT_HDR_TYPES_0_3_IPV6_EXT_UNIFORM_HDR_TYPE_2_E5_SHIFT 16 + #define PBF_REG_IPV6_EXT_HDR_TYPES_0_3_IPV6_EXT_UNIFORM_HDR_TYPE_3_E5 (0xff<<24) // ipv6 extension uniform header type 3 + #define PBF_REG_IPV6_EXT_HDR_TYPES_0_3_IPV6_EXT_UNIFORM_HDR_TYPE_3_E5_SHIFT 24 +#define PBF_REG_IPV6_EXT_HDR_TYPES_4_7_E5 0xd8055cUL //Access:RW DataWidth:0x20 // Multi Field Register. + #define PBF_REG_IPV6_EXT_HDR_TYPES_4_7_IPV6_EXT_UNIFORM_HDR_TYPE_4_E5 (0xff<<0) // ipv6 extension uniform header type 4 + #define PBF_REG_IPV6_EXT_HDR_TYPES_4_7_IPV6_EXT_UNIFORM_HDR_TYPE_4_E5_SHIFT 0 + #define PBF_REG_IPV6_EXT_HDR_TYPES_4_7_IPV6_EXT_UNIFORM_HDR_TYPE_5_E5 (0xff<<8) // ipv6 extension uniform header type 5 + #define PBF_REG_IPV6_EXT_HDR_TYPES_4_7_IPV6_EXT_UNIFORM_HDR_TYPE_5_E5_SHIFT 8 + #define PBF_REG_IPV6_EXT_HDR_TYPES_4_7_IPV6_EXT_UNIFORM_HDR_TYPE_6_E5 (0xff<<16) // ipv6 extension uniform header type 6 + #define PBF_REG_IPV6_EXT_HDR_TYPES_4_7_IPV6_EXT_UNIFORM_HDR_TYPE_6_E5_SHIFT 16 + #define PBF_REG_IPV6_EXT_HDR_TYPES_4_7_IPV6_EXT_UNIFORM_HDR_TYPE_7_E5 (0xff<<24) // ipv6 extension uniform header type 7 + #define PBF_REG_IPV6_EXT_HDR_TYPES_4_7_IPV6_EXT_UNIFORM_HDR_TYPE_7_E5_SHIFT 24 +#define PBF_REG_IPV6_EXT_HDR_TYPES_8_11_E5 0xd80560UL //Access:RW DataWidth:0x20 // Multi Field Register. + #define PBF_REG_IPV6_EXT_HDR_TYPES_8_11_IPV6_EXT_UNIFORM_HDR_TYPE_8_E5 (0xff<<0) // ipv6 extension uniform header type 8 + #define PBF_REG_IPV6_EXT_HDR_TYPES_8_11_IPV6_EXT_UNIFORM_HDR_TYPE_8_E5_SHIFT 0 + #define PBF_REG_IPV6_EXT_HDR_TYPES_8_11_IPV6_EXT_UNIFORM_HDR_TYPE_9_E5 (0xff<<8) // ipv6 extension uniform header type 9 + #define PBF_REG_IPV6_EXT_HDR_TYPES_8_11_IPV6_EXT_UNIFORM_HDR_TYPE_9_E5_SHIFT 8 + #define PBF_REG_IPV6_EXT_HDR_TYPES_8_11_IPV6_EXT_UNIFORM_HDR_TYPE_10_E5 (0xff<<16) // ipv6 extension uniform header type 10 + #define PBF_REG_IPV6_EXT_HDR_TYPES_8_11_IPV6_EXT_UNIFORM_HDR_TYPE_10_E5_SHIFT 16 + #define PBF_REG_IPV6_EXT_HDR_TYPES_8_11_IPV6_EXT_UNIFORM_HDR_TYPE_11_E5 (0xff<<24) // ipv6 extension uniform header type 11 + #define PBF_REG_IPV6_EXT_HDR_TYPES_8_11_IPV6_EXT_UNIFORM_HDR_TYPE_11_E5_SHIFT 24 +#define PBF_REG_IPV6_EXT_HDR_TYPES_MISC_E5 0xd80564UL //Access:RW DataWidth:0x20 // Multi Field Register. + #define PBF_REG_IPV6_EXT_HDR_TYPES_MISC_IPV6_EXT_UNIFORM_HDR_TYPE_12_E5 (0xff<<0) // ipv6 extension uniform header type 13 + #define PBF_REG_IPV6_EXT_HDR_TYPES_MISC_IPV6_EXT_UNIFORM_HDR_TYPE_12_E5_SHIFT 0 + #define PBF_REG_IPV6_EXT_HDR_TYPES_MISC_IPV6_EXT_UNIFORM_HDR_TYPE_13_E5 (0xff<<8) // ipv6 extension uniform header type 13 + #define PBF_REG_IPV6_EXT_HDR_TYPES_MISC_IPV6_EXT_UNIFORM_HDR_TYPE_13_E5_SHIFT 8 + #define PBF_REG_IPV6_EXT_HDR_TYPES_MISC_IPV6_EXT_FRAGMENT_HDR_TYPE_E5 (0xff<<16) // ipv6 extension fragment header type + #define PBF_REG_IPV6_EXT_HDR_TYPES_MISC_IPV6_EXT_FRAGMENT_HDR_TYPE_E5_SHIFT 16 + #define PBF_REG_IPV6_EXT_HDR_TYPES_MISC_IPV6_EXT_AUTHENTICATION_HDR_TYPE_E5 (0xff<<24) // ipv6 extension authentication header type + #define PBF_REG_IPV6_EXT_HDR_TYPES_MISC_IPV6_EXT_AUTHENTICATION_HDR_TYPE_E5_SHIFT 24 +#define PBF_REG_TUNNEL_MISC_CFG_E5 0xd80568UL //Access:RW DataWidth:0x5 // Multi Field Register. + #define PBF_REG_TUNNEL_MISC_CFG_COMPARE_GRE_VERSION_E5 (0x1<<0) // compare the GRE version field to the gre_version register. + #define PBF_REG_TUNNEL_MISC_CFG_COMPARE_GRE_VERSION_E5_SHIFT 0 + #define PBF_REG_TUNNEL_MISC_CFG_GRE_VERSION_E5 (0x7<<1) // compare the GRE version field to gre_version register if compare_gre_version=1 + #define PBF_REG_TUNNEL_MISC_CFG_GRE_VERSION_E5_SHIFT 1 + #define PBF_REG_TUNNEL_MISC_CFG_USE_SINGLE_FC_CHICKEN_BIT_E5 (0x1<<4) // Chicken bit to use single fc engine + #define PBF_REG_TUNNEL_MISC_CFG_USE_SINGLE_FC_CHICKEN_BIT_E5_SHIFT 4 +#define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_E5 0xd8056cUL //Access:RW DataWidth:0x10 // Multi Field Register. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_0_VALID_E5 (0x1<<0) // If set, validates the corresponding IPV6 extension header Type. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_0_VALID_E5_SHIFT 0 + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_1_VALID_E5 (0x1<<1) // If set, validates the corresponding IPV6 extension header Type. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_1_VALID_E5_SHIFT 1 + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_2_VALID_E5 (0x1<<2) // If set, validates the corresponding IPV6 extension header Type. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_2_VALID_E5_SHIFT 2 + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_3_VALID_E5 (0x1<<3) // If set, validates the corresponding IPV6 extension header Type. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_3_VALID_E5_SHIFT 3 + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_4_VALID_E5 (0x1<<4) // If set, validates the corresponding IPV6 extension header Type. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_4_VALID_E5_SHIFT 4 + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_5_VALID_E5 (0x1<<5) // If set, validates the corresponding IPV6 extension header Type. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_5_VALID_E5_SHIFT 5 + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_6_VALID_E5 (0x1<<6) // If set, validates the corresponding IPV6 extension header Type. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_6_VALID_E5_SHIFT 6 + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_7_VALID_E5 (0x1<<7) // If set, validates the corresponding IPV6 extension header Type. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_7_VALID_E5_SHIFT 7 + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_8_VALID_E5 (0x1<<8) // If set, validates the corresponding IPV6 extension header Type. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_8_VALID_E5_SHIFT 8 + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_9_VALID_E5 (0x1<<9) // If set, validates the corresponding IPV6 extension header Type. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_9_VALID_E5_SHIFT 9 + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_10_VALID_E5 (0x1<<10) // If set, validates the corresponding IPV6 extension header Type. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_10_VALID_E5_SHIFT 10 + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_11_VALID_E5 (0x1<<11) // If set, validates the corresponding IPV6 extension header Type. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_11_VALID_E5_SHIFT 11 + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_12_VALID_E5 (0x1<<12) // If set, validates the corresponding IPV6 extension header Type. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_12_VALID_E5_SHIFT 12 + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_13_VALID_E5 (0x1<<13) // If set, validates the corresponding IPV6 extension header Type. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_UNIFORM_HDR_TYPE_13_VALID_E5_SHIFT 13 + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_FRAGMENT_HDR_TYPE_VALID_E5 (0x1<<14) // If set, validates the corresponding IPV6 extension header Type. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_FRAGMENT_HDR_TYPE_VALID_E5_SHIFT 14 + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_AUTHENTICATION_HDR_TYPE_VALID_E5 (0x1<<15) // If set, validates the corresponding IPV6 extension header Type. + #define PBF_REG_IPV6_EXT_HDR_TYPE_VALIDS_IPV6_EXT_AUTHENTICATION_HDR_TYPE_VALID_E5_SHIFT 15 #define PBF_REG_PROP_HDR_SIZE_BB_K2 0xd80580UL //Access:RW DataWidth:0x3 // PORT SPLIT. Size of the Propriatery/HiGig header. (in 4B increments). If HiGig is disabled this value should be 0. #define PBF_REG_REGULAR_INBAND_TAG_ORDER 0xd80584UL //Access:RW DataWidth:0x1c // The regular inband TAG order. Reset value is in the order from left to right: tag0; tag1; tag2; tag3; tag4; tag5; llc-snap. #define PBF_REG_T_TAG_TAGNUM 0xd80588UL //Access:RW DataWidth:0x4 // Per-Port: Specifies the flexible L2 tag to be used for T-tag. The MSB enables T-tag recognition. @@ -64394,6 +68661,7 @@ #define PBF_REG_EVENT_ID_L2_TAGS_EXIST_MASK_CONFIG_EVENTID_FIRST_L2_TAGS_EXIST_MASK_E5_SHIFT 0 #define PBF_REG_EVENT_ID_L2_TAGS_EXIST_MASK_CONFIG_EVENTID_INNER_L2_TAGS_EXIST_MASK_E5 (0xff<<8) // Mask for Inner L2 Tags Exist field in Event ID modification logic. Setting to 1 selects or unmasks the condition. Bit 0 of this mask corresponds to Inner L2 Tag Exist Bit 0. #define PBF_REG_EVENT_ID_L2_TAGS_EXIST_MASK_CONFIG_EVENTID_INNER_L2_TAGS_EXIST_MASK_E5_SHIFT 8 +#define PBF_REG_MISC_PARSING_CONFIG_E5 0xd805b0UL //Access:RW DataWidth:0x1 // If set, enables inclusion of Future Header in the TGFS message instead of Extracted Header. #define PBF_REG_BTB_SHARED_AREA_SIZE 0xd805c0UL //Access:RW DataWidth:0xb // Number of shared BTB 256 byte blocks which can be used by all TC-s in the port. #define PBF_REG_BTB_ALLOCATED_BLOCKS_SHARED 0xd805c4UL //Access:R DataWidth:0xc // Number of blocks that are currently allocated in the shared area of the port. #define PBF_REG_JUMBO_PKT_THRSH 0xd805c8UL //Access:RW DataWidth:0x6 // Jumbo packet threshold in 256 byte blocks to determine if a TC can use the BTB shared area. @@ -64401,6 +68669,7 @@ #define PBF_REG_NUM_STRICT_PRIORITY_SLOTS 0xd805d0UL //Access:RW DataWidth:0xa // The number of strict priority arbitration slots between 2 RR arbitration slots in the ycommand arbiter. A value of 0 means no strict priority cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR arbiter. A value of all ones means no RR slots; i.e. the strict-priority w/ anti-starvation arbiter is a strict-priority arbiter. #define PBF_REG_L2_EDPM_THRSH 0xd805d4UL //Access:RW DataWidth:0x8 // L2 EDPM threshold in 256 byte blocks. Only if all TC-s have allocated blocks below this threshold, L2 EDPM will be enabled. #define PBF_REG_CPMU_THRSH 0xd805d8UL //Access:RW DataWidth:0xb // CPMU threshold in 256 byte blocks. Only if all TC-s in port N have allocated blocks above this threshold, the corresponding bit for that port will be set towards CPMU. +#define PBF_REG_RDMA_EDPM_THRSH_E5 0xd805dcUL //Access:RW DataWidth:0xb // RDMA EDPM threshold in 256 byte blocks. Only if all TC-s have allocated blocks below this threshold, RDMA EDPM will be enabled. #define PBF_REG_IP_ID_MASK_0 0xd80600UL //Access:RW DataWidth:0x10 // 1st bit mask used to control the rollover when increasing the IP ID field in the packet. Selected per command. #define PBF_REG_IP_ID_MASK_1 0xd80604UL //Access:RW DataWidth:0x10 // 2nd bit mask used to control the rollover when increasing the IP ID field in the packet. Selected per command. #define PBF_REG_IP_ID_MASK_2 0xd80608UL //Access:RW DataWidth:0x10 // 3rd bit mask used to control the rollover when increasing the IP ID field in the packet. Selected per command. @@ -64425,6 +68694,16 @@ #define PBF_REG_NUM_PKTS_SENT_WITH_ERROR_TO_BTB 0xd8066cUL //Access:RC DataWidth:0x8 // Number of packets sent to BTB with error indication #define PBF_REG_NUM_PKTS_SENT_WITH_DROP_TO_BTB 0xd80670UL //Access:RC DataWidth:0x8 // Number of packets sent to BTB with drop indication #define PBF_REG_PER_VOQ_STAT_MASK_LOOPBACK_E5 0xd80674UL //Access:RW DataWidth:0x4 // per VOQ indication if it should be accounted for in bytes/packet statistics Note: This is exclusively for LB queues +#define PBF_REG_TUNNEL_GRE_ETH_EN_E5 0xd80678UL //Access:RW DataWidth:0x1 // If set, Ethernet over GRE tunneling is enabled for this PF. +#define PBF_REG_TUNNEL_GRE_IP_EN_E5 0xd8067cUL //Access:RW DataWidth:0x1 // If set, IP over GRE tunneling is enabled for this PF. +#define PBF_REG_TUNNEL_VXLAN_EN_E5 0xd80680UL //Access:RW DataWidth:0x1 // If set, VXLAN tunneling is enabled for this PF. +#define PBF_REG_TUNNEL_NGE_ETH_EN_E5 0xd80684UL //Access:RW DataWidth:0x1 // If set, Ethernet over NGE tunneling is enabled for this PF. +#define PBF_REG_TUNNEL_NGE_IP_EN_E5 0xd80688UL //Access:RW DataWidth:0x1 // If set, IP over NGE tunneling is enabled for this PF. +#define PBF_REG_TUNNEL_GRE_MPLS_ETH_EN_E5 0xd8068cUL //Access:RW DataWidth:0x1 // If set, Ethernet over MPLS over GRE tunneling is enabled for this PF. +#define PBF_REG_TUNNEL_GRE_MPLS_IP_EN_E5 0xd80690UL //Access:RW DataWidth:0x1 // If set, IP over MPLS over GRE tunneling is enabled for this PF. +#define PBF_REG_TUNNEL_UDP_MPLS_ETH_EN_E5 0xd80694UL //Access:RW DataWidth:0x1 // If set, Ethernet over MPLS over UDP tunneling is enabled for this PF. +#define PBF_REG_TUNNEL_UDP_MPLS_IP_EN_E5 0xd80698UL //Access:RW DataWidth:0x1 // If set, IP over MPLS over UDP tunneling is enabled for this PF. +#define PBF_REG_TUNNEL_MPLS_ETH_EN_E5 0xd8069cUL //Access:RW DataWidth:0x1 // If set, Ethernet over MPLS tunneling is enabled for this PF. #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0 0xd806a0UL //Access:RW DataWidth:0xd // Number of 32 byte lines in the YSTORM command Q reserved for VOQ 0. #define PBF_REG_YCMD_QS_THRSH_VOQ0 0xd806a4UL //Access:RW DataWidth:0x5 // Almost full threshold for VOQ 0 in the YSTORM command Q in 32 byte lines. #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ0 0xd806a8UL //Access:RW DataWidth:0x1 // Disable processing further Y commands from VOQ 0 (after ending the current command in process). @@ -68405,7 +72684,8 @@ #define MCP_REG_ROM 0xe10000UL //Access:R DataWidth:0x20 // This location provides a location for the ROM contents to be read for debug pourposes. #define MCP_REG_ROM_SIZE 320 #define MCP_REG_SCRATCH 0xe20000UL //Access:RW DataWidth:0x20 // This is the supported processor scratch pad space that is visible at 0x0 by the processor. This can be modified at any time and may be used for processor-to-processor communication. -#define MCP_REG_SCRATCH_SIZE 57344 +#define MCP_REG_SCRATCH_SIZE_BB_K2 57344 +#define MCP_REG_SCRATCH_SIZE_E5 81920 #define XSDM_REG_ENABLE_IN1 0xf80004UL //Access:RW DataWidth:0x14 // Multi Field Register. #define XSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN (0x1<<0) // Enable for input command from STORM. #define XSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN_SHIFT 0 @@ -68525,7 +72805,7 @@ #define XSDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT 8 #define XSDM_REG_DISABLE_ENGINE_DISABLE_DORQ (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands. #define XSDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT 9 -#define XSDM_REG_INT_STS 0xf80040UL //Access:R DataWidth:0x1c // Multi Field Register. +#define XSDM_REG_INT_STS 0xf80040UL //Access:R DataWidth:0x1f // Multi Field Register. #define XSDM_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define XSDM_REG_INT_STS_ADDRESS_ERROR_SHIFT 0 #define XSDM_REG_INT_STS_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -68582,7 +72862,13 @@ #define XSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define XSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define XSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define XSDM_REG_INT_MASK 0xf80044UL //Access:RW DataWidth:0x1c // Multi Field Register. + #define XSDM_REG_INT_STS_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define XSDM_REG_INT_STS_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define XSDM_REG_INT_STS_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define XSDM_REG_INT_STS_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define XSDM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define XSDM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define XSDM_REG_INT_MASK 0xf80044UL //Access:RW DataWidth:0x1f // Multi Field Register. #define XSDM_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.ADDRESS_ERROR . #define XSDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT 0 #define XSDM_REG_INT_MASK_INP_QUEUE_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.INP_QUEUE_ERROR . @@ -68639,7 +72925,13 @@ #define XSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define XSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR . #define XSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define XSDM_REG_INT_STS_WR 0xf80048UL //Access:WR DataWidth:0x1c // Multi Field Register. + #define XSDM_REG_INT_MASK_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.TIMERS_EXCEEDED_MAX_CMP_MSG_NUM . + #define XSDM_REG_INT_MASK_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define XSDM_REG_INT_MASK_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.EXPECTED_LAST_CYCLE . + #define XSDM_REG_INT_MASK_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define XSDM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.UNEXPECTED_LAST_CYCLE . + #define XSDM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define XSDM_REG_INT_STS_WR 0xf80048UL //Access:WR DataWidth:0x1f // Multi Field Register. #define XSDM_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define XSDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT 0 #define XSDM_REG_INT_STS_WR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -68696,7 +72988,13 @@ #define XSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define XSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define XSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define XSDM_REG_INT_STS_CLR 0xf8004cUL //Access:RC DataWidth:0x1c // Multi Field Register. + #define XSDM_REG_INT_STS_WR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define XSDM_REG_INT_STS_WR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define XSDM_REG_INT_STS_WR_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define XSDM_REG_INT_STS_WR_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define XSDM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define XSDM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define XSDM_REG_INT_STS_CLR 0xf8004cUL //Access:RC DataWidth:0x1f // Multi Field Register. #define XSDM_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define XSDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT 0 #define XSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -68753,6 +73051,12 @@ #define XSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define XSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define XSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 + #define XSDM_REG_INT_STS_CLR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define XSDM_REG_INT_STS_CLR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define XSDM_REG_INT_STS_CLR_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define XSDM_REG_INT_STS_CLR_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define XSDM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define XSDM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 #define XSDM_REG_PRTY_MASK_H_0 0xf80204UL //Access:RW DataWidth:0xb // Multi Field Register. #define XSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2 (0x1<<5) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY . #define XSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2_SHIFT 5 @@ -68822,10 +73126,12 @@ #define XSDM_REG_BRB_ALMOST_FULL 0xf80700UL //Access:RW DataWidth:0x5 // Almost full signal for read data from BRB in DMA_RSP block. #define XSDM_REG_PXP_ALMOST_FULL 0xf80704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block. #define XSDM_REG_DORQ_ALMOST_FULL 0xf80708UL //Access:RW DataWidth:0x6 // Almost full signal for read data from DORQ in SDM_DORQ block. -#define XSDM_REG_AGG_INT_CTRL 0xf80800UL //Access:RW DataWidth:0x12 // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [17:16] Affinity [15:12] NumL2m: Field is passed transparently to FIC message in case of direct messge. [11] Exclusive: . [10] Core-selection where 0=Core_A and 1=Core_B. [9] Mode bit where 0=normal and 1=auto-mask-mode. [7:0] EventID which selects the event ID of the associated handler. -#define XSDM_REG_AGG_INT_CTRL_SIZE 32 +#define XSDM_REG_AGG_INT_CTRL 0xf80800UL //Access:RW DataWidth:0x16 // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [21:20] Affinity [19:16] NumL2m: Field is passed transparently to FIC message in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode bit where 0=normal and 1=auto-mask-mode. [8] Reserved/Unused. [7:0] EventID which selects the event ID of the associated handler. +#define XSDM_REG_AGG_INT_CTRL_SIZE_BB_K2 32 +#define XSDM_REG_AGG_INT_CTRL_SIZE_E5 16 #define XSDM_REG_AGG_INT_STATE 0xf80a00UL //Access:R DataWidth:0x2 // This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM. -#define XSDM_REG_AGG_INT_STATE_SIZE 32 +#define XSDM_REG_AGG_INT_STATE_SIZE_BB_K2 32 +#define XSDM_REG_AGG_INT_STATE_SIZE_E5 16 #define XSDM_REG_QUEUE_FULL 0xf80c00UL //Access:R DataWidth:0x9 // Input queue fifo full in sdm_inp block. #define XSDM_REG_INT_CMPL_PEND_FULL 0xf80c04UL //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block. #define XSDM_REG_INT_CPRM_PEND_FULL 0xf80c08UL //Access:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block. @@ -69040,7 +73346,7 @@ #define YSDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT 8 #define YSDM_REG_DISABLE_ENGINE_DISABLE_DORQ (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands. #define YSDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT 9 -#define YSDM_REG_INT_STS 0xf90040UL //Access:R DataWidth:0x1c // Multi Field Register. +#define YSDM_REG_INT_STS 0xf90040UL //Access:R DataWidth:0x1f // Multi Field Register. #define YSDM_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define YSDM_REG_INT_STS_ADDRESS_ERROR_SHIFT 0 #define YSDM_REG_INT_STS_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -69097,7 +73403,13 @@ #define YSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define YSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define YSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define YSDM_REG_INT_MASK 0xf90044UL //Access:RW DataWidth:0x1c // Multi Field Register. + #define YSDM_REG_INT_STS_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define YSDM_REG_INT_STS_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define YSDM_REG_INT_STS_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define YSDM_REG_INT_STS_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define YSDM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define YSDM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define YSDM_REG_INT_MASK 0xf90044UL //Access:RW DataWidth:0x1f // Multi Field Register. #define YSDM_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.ADDRESS_ERROR . #define YSDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT 0 #define YSDM_REG_INT_MASK_INP_QUEUE_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.INP_QUEUE_ERROR . @@ -69154,7 +73466,13 @@ #define YSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define YSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR . #define YSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define YSDM_REG_INT_STS_WR 0xf90048UL //Access:WR DataWidth:0x1c // Multi Field Register. + #define YSDM_REG_INT_MASK_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.TIMERS_EXCEEDED_MAX_CMP_MSG_NUM . + #define YSDM_REG_INT_MASK_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define YSDM_REG_INT_MASK_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.EXPECTED_LAST_CYCLE . + #define YSDM_REG_INT_MASK_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define YSDM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.UNEXPECTED_LAST_CYCLE . + #define YSDM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define YSDM_REG_INT_STS_WR 0xf90048UL //Access:WR DataWidth:0x1f // Multi Field Register. #define YSDM_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define YSDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT 0 #define YSDM_REG_INT_STS_WR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -69211,7 +73529,13 @@ #define YSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define YSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define YSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define YSDM_REG_INT_STS_CLR 0xf9004cUL //Access:RC DataWidth:0x1c // Multi Field Register. + #define YSDM_REG_INT_STS_WR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define YSDM_REG_INT_STS_WR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define YSDM_REG_INT_STS_WR_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define YSDM_REG_INT_STS_WR_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define YSDM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define YSDM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define YSDM_REG_INT_STS_CLR 0xf9004cUL //Access:RC DataWidth:0x1f // Multi Field Register. #define YSDM_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define YSDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT 0 #define YSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -69268,6 +73592,12 @@ #define YSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define YSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define YSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 + #define YSDM_REG_INT_STS_CLR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define YSDM_REG_INT_STS_CLR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define YSDM_REG_INT_STS_CLR_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define YSDM_REG_INT_STS_CLR_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define YSDM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define YSDM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 #define YSDM_REG_PRTY_MASK_H_0 0xf90204UL //Access:RW DataWidth:0xa // Multi Field Register. #define YSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2 (0x1<<5) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . #define YSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT 5 @@ -69334,10 +73664,12 @@ #define YSDM_REG_BRB_ALMOST_FULL 0xf90700UL //Access:RW DataWidth:0x5 // Almost full signal for read data from BRB in DMA_RSP block. #define YSDM_REG_PXP_ALMOST_FULL 0xf90704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block. #define YSDM_REG_DORQ_ALMOST_FULL 0xf90708UL //Access:RW DataWidth:0x6 // Almost full signal for read data from DORQ in SDM_DORQ block. -#define YSDM_REG_AGG_INT_CTRL 0xf90800UL //Access:RW DataWidth:0x12 // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [17:16] Affinity [15:12] NumL2m: Field is passed transparently to FIC message in case of direct messge. [11] Exclusive: . [10] Core-selection where 0=Core_A and 1=Core_B. [9] Mode bit where 0=normal and 1=auto-mask-mode. [7:0] EventID which selects the event ID of the associated handler. -#define YSDM_REG_AGG_INT_CTRL_SIZE 32 +#define YSDM_REG_AGG_INT_CTRL 0xf90800UL //Access:RW DataWidth:0x16 // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [21:20] Affinity [19:16] NumL2m: Field is passed transparently to FIC message in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode bit where 0=normal and 1=auto-mask-mode. [8] Reserved/Unused. [7:0] EventID which selects the event ID of the associated handler. +#define YSDM_REG_AGG_INT_CTRL_SIZE_BB_K2 32 +#define YSDM_REG_AGG_INT_CTRL_SIZE_E5 16 #define YSDM_REG_AGG_INT_STATE 0xf90a00UL //Access:R DataWidth:0x2 // This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM. -#define YSDM_REG_AGG_INT_STATE_SIZE 32 +#define YSDM_REG_AGG_INT_STATE_SIZE_BB_K2 32 +#define YSDM_REG_AGG_INT_STATE_SIZE_E5 16 #define YSDM_REG_QUEUE_FULL 0xf90c00UL //Access:R DataWidth:0x9 // Input queue fifo full in sdm_inp block. #define YSDM_REG_INT_CMPL_PEND_FULL 0xf90c04UL //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block. #define YSDM_REG_INT_CPRM_PEND_FULL 0xf90c08UL //Access:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block. @@ -69552,7 +73884,7 @@ #define PSDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT 8 #define PSDM_REG_DISABLE_ENGINE_DISABLE_DORQ (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands. #define PSDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT 9 -#define PSDM_REG_INT_STS 0xfa0040UL //Access:R DataWidth:0x1c // Multi Field Register. +#define PSDM_REG_INT_STS 0xfa0040UL //Access:R DataWidth:0x1f // Multi Field Register. #define PSDM_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define PSDM_REG_INT_STS_ADDRESS_ERROR_SHIFT 0 #define PSDM_REG_INT_STS_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -69609,7 +73941,13 @@ #define PSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define PSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define PSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define PSDM_REG_INT_MASK 0xfa0044UL //Access:RW DataWidth:0x1c // Multi Field Register. + #define PSDM_REG_INT_STS_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define PSDM_REG_INT_STS_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define PSDM_REG_INT_STS_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define PSDM_REG_INT_STS_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define PSDM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define PSDM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define PSDM_REG_INT_MASK 0xfa0044UL //Access:RW DataWidth:0x1f // Multi Field Register. #define PSDM_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.ADDRESS_ERROR . #define PSDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT 0 #define PSDM_REG_INT_MASK_INP_QUEUE_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.INP_QUEUE_ERROR . @@ -69666,7 +74004,13 @@ #define PSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define PSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR . #define PSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define PSDM_REG_INT_STS_WR 0xfa0048UL //Access:WR DataWidth:0x1c // Multi Field Register. + #define PSDM_REG_INT_MASK_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.TIMERS_EXCEEDED_MAX_CMP_MSG_NUM . + #define PSDM_REG_INT_MASK_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define PSDM_REG_INT_MASK_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.EXPECTED_LAST_CYCLE . + #define PSDM_REG_INT_MASK_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define PSDM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.UNEXPECTED_LAST_CYCLE . + #define PSDM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define PSDM_REG_INT_STS_WR 0xfa0048UL //Access:WR DataWidth:0x1f // Multi Field Register. #define PSDM_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define PSDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT 0 #define PSDM_REG_INT_STS_WR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -69723,7 +74067,13 @@ #define PSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define PSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define PSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define PSDM_REG_INT_STS_CLR 0xfa004cUL //Access:RC DataWidth:0x1c // Multi Field Register. + #define PSDM_REG_INT_STS_WR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define PSDM_REG_INT_STS_WR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define PSDM_REG_INT_STS_WR_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define PSDM_REG_INT_STS_WR_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define PSDM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define PSDM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define PSDM_REG_INT_STS_CLR 0xfa004cUL //Access:RC DataWidth:0x1f // Multi Field Register. #define PSDM_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define PSDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT 0 #define PSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -69780,6 +74130,12 @@ #define PSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define PSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define PSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 + #define PSDM_REG_INT_STS_CLR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define PSDM_REG_INT_STS_CLR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define PSDM_REG_INT_STS_CLR_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define PSDM_REG_INT_STS_CLR_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define PSDM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define PSDM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 #define PSDM_REG_PRTY_MASK_H_0 0xfa0204UL //Access:RW DataWidth:0xa // Multi Field Register. #define PSDM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT . #define PSDM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_E5_SHIFT 0 @@ -69870,10 +74226,12 @@ #define PSDM_REG_BRB_ALMOST_FULL 0xfa0700UL //Access:RW DataWidth:0x5 // Almost full signal for read data from BRB in DMA_RSP block. #define PSDM_REG_PXP_ALMOST_FULL 0xfa0704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block. #define PSDM_REG_DORQ_ALMOST_FULL 0xfa0708UL //Access:RW DataWidth:0x6 // Almost full signal for read data from DORQ in SDM_DORQ block. -#define PSDM_REG_AGG_INT_CTRL 0xfa0800UL //Access:RW DataWidth:0x12 // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [17:16] Affinity [15:12] NumL2m: Field is passed transparently to FIC message in case of direct messge. [11] Exclusive: . [10] Core-selection where 0=Core_A and 1=Core_B. [9] Mode bit where 0=normal and 1=auto-mask-mode. [7:0] EventID which selects the event ID of the associated handler. -#define PSDM_REG_AGG_INT_CTRL_SIZE 32 +#define PSDM_REG_AGG_INT_CTRL 0xfa0800UL //Access:RW DataWidth:0x16 // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [21:20] Affinity [19:16] NumL2m: Field is passed transparently to FIC message in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode bit where 0=normal and 1=auto-mask-mode. [8] Reserved/Unused. [7:0] EventID which selects the event ID of the associated handler. +#define PSDM_REG_AGG_INT_CTRL_SIZE_BB_K2 32 +#define PSDM_REG_AGG_INT_CTRL_SIZE_E5 16 #define PSDM_REG_AGG_INT_STATE 0xfa0a00UL //Access:R DataWidth:0x2 // This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM. -#define PSDM_REG_AGG_INT_STATE_SIZE 32 +#define PSDM_REG_AGG_INT_STATE_SIZE_BB_K2 32 +#define PSDM_REG_AGG_INT_STATE_SIZE_E5 16 #define PSDM_REG_QUEUE_FULL 0xfa0c00UL //Access:R DataWidth:0x9 // Input queue fifo full in sdm_inp block. #define PSDM_REG_INT_CMPL_PEND_FULL 0xfa0c04UL //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block. #define PSDM_REG_INT_CPRM_PEND_FULL 0xfa0c08UL //Access:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block. @@ -70088,7 +74446,7 @@ #define TSDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT 8 #define TSDM_REG_DISABLE_ENGINE_DISABLE_DORQ (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands. #define TSDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT 9 -#define TSDM_REG_INT_STS 0xfb0040UL //Access:R DataWidth:0x1c // Multi Field Register. +#define TSDM_REG_INT_STS 0xfb0040UL //Access:R DataWidth:0x1f // Multi Field Register. #define TSDM_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define TSDM_REG_INT_STS_ADDRESS_ERROR_SHIFT 0 #define TSDM_REG_INT_STS_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -70145,7 +74503,13 @@ #define TSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define TSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define TSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define TSDM_REG_INT_MASK 0xfb0044UL //Access:RW DataWidth:0x1c // Multi Field Register. + #define TSDM_REG_INT_STS_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define TSDM_REG_INT_STS_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define TSDM_REG_INT_STS_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define TSDM_REG_INT_STS_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define TSDM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define TSDM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define TSDM_REG_INT_MASK 0xfb0044UL //Access:RW DataWidth:0x1f // Multi Field Register. #define TSDM_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.ADDRESS_ERROR . #define TSDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT 0 #define TSDM_REG_INT_MASK_INP_QUEUE_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.INP_QUEUE_ERROR . @@ -70202,7 +74566,13 @@ #define TSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define TSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR . #define TSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define TSDM_REG_INT_STS_WR 0xfb0048UL //Access:WR DataWidth:0x1c // Multi Field Register. + #define TSDM_REG_INT_MASK_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.TIMERS_EXCEEDED_MAX_CMP_MSG_NUM . + #define TSDM_REG_INT_MASK_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define TSDM_REG_INT_MASK_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.EXPECTED_LAST_CYCLE . + #define TSDM_REG_INT_MASK_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define TSDM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.UNEXPECTED_LAST_CYCLE . + #define TSDM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define TSDM_REG_INT_STS_WR 0xfb0048UL //Access:WR DataWidth:0x1f // Multi Field Register. #define TSDM_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define TSDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT 0 #define TSDM_REG_INT_STS_WR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -70259,7 +74629,13 @@ #define TSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define TSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define TSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define TSDM_REG_INT_STS_CLR 0xfb004cUL //Access:RC DataWidth:0x1c // Multi Field Register. + #define TSDM_REG_INT_STS_WR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define TSDM_REG_INT_STS_WR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define TSDM_REG_INT_STS_WR_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define TSDM_REG_INT_STS_WR_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define TSDM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define TSDM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define TSDM_REG_INT_STS_CLR 0xfb004cUL //Access:RC DataWidth:0x1f // Multi Field Register. #define TSDM_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define TSDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT 0 #define TSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -70316,6 +74692,12 @@ #define TSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define TSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define TSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 + #define TSDM_REG_INT_STS_CLR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define TSDM_REG_INT_STS_CLR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define TSDM_REG_INT_STS_CLR_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define TSDM_REG_INT_STS_CLR_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define TSDM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define TSDM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 #define TSDM_REG_PRTY_MASK_H_0 0xfb0204UL //Access:RW DataWidth:0xb // Multi Field Register. #define TSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2 (0x1<<6) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY . #define TSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_K2_SHIFT 6 @@ -70385,10 +74767,12 @@ #define TSDM_REG_BRB_ALMOST_FULL 0xfb0700UL //Access:RW DataWidth:0x5 // Almost full signal for read data from BRB in DMA_RSP block. #define TSDM_REG_PXP_ALMOST_FULL 0xfb0704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block. #define TSDM_REG_DORQ_ALMOST_FULL 0xfb0708UL //Access:RW DataWidth:0x6 // Almost full signal for read data from DORQ in SDM_DORQ block. -#define TSDM_REG_AGG_INT_CTRL 0xfb0800UL //Access:RW DataWidth:0x12 // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [17:16] Affinity [15:12] NumL2m: Field is passed transparently to FIC message in case of direct messge. [11] Exclusive: . [10] Core-selection where 0=Core_A and 1=Core_B. [9] Mode bit where 0=normal and 1=auto-mask-mode. [7:0] EventID which selects the event ID of the associated handler. -#define TSDM_REG_AGG_INT_CTRL_SIZE 32 +#define TSDM_REG_AGG_INT_CTRL 0xfb0800UL //Access:RW DataWidth:0x16 // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [21:20] Affinity [19:16] NumL2m: Field is passed transparently to FIC message in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode bit where 0=normal and 1=auto-mask-mode. [8] Reserved/Unused. [7:0] EventID which selects the event ID of the associated handler. +#define TSDM_REG_AGG_INT_CTRL_SIZE_BB_K2 32 +#define TSDM_REG_AGG_INT_CTRL_SIZE_E5 16 #define TSDM_REG_AGG_INT_STATE 0xfb0a00UL //Access:R DataWidth:0x2 // This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM. -#define TSDM_REG_AGG_INT_STATE_SIZE 32 +#define TSDM_REG_AGG_INT_STATE_SIZE_BB_K2 32 +#define TSDM_REG_AGG_INT_STATE_SIZE_E5 16 #define TSDM_REG_QUEUE_FULL 0xfb0c00UL //Access:R DataWidth:0x9 // Input queue fifo full in sdm_inp block. #define TSDM_REG_INT_CMPL_PEND_FULL 0xfb0c04UL //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block. #define TSDM_REG_INT_CPRM_PEND_FULL 0xfb0c08UL //Access:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block. @@ -70603,7 +74987,7 @@ #define MSDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT 8 #define MSDM_REG_DISABLE_ENGINE_DISABLE_DORQ (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands. #define MSDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT 9 -#define MSDM_REG_INT_STS 0xfc0040UL //Access:R DataWidth:0x1c // Multi Field Register. +#define MSDM_REG_INT_STS 0xfc0040UL //Access:R DataWidth:0x1f // Multi Field Register. #define MSDM_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define MSDM_REG_INT_STS_ADDRESS_ERROR_SHIFT 0 #define MSDM_REG_INT_STS_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -70660,7 +75044,13 @@ #define MSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define MSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define MSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define MSDM_REG_INT_MASK 0xfc0044UL //Access:RW DataWidth:0x1c // Multi Field Register. + #define MSDM_REG_INT_STS_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define MSDM_REG_INT_STS_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define MSDM_REG_INT_STS_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define MSDM_REG_INT_STS_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define MSDM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define MSDM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define MSDM_REG_INT_MASK 0xfc0044UL //Access:RW DataWidth:0x1f // Multi Field Register. #define MSDM_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.ADDRESS_ERROR . #define MSDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT 0 #define MSDM_REG_INT_MASK_INP_QUEUE_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.INP_QUEUE_ERROR . @@ -70717,7 +75107,13 @@ #define MSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define MSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR . #define MSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define MSDM_REG_INT_STS_WR 0xfc0048UL //Access:WR DataWidth:0x1c // Multi Field Register. + #define MSDM_REG_INT_MASK_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.TIMERS_EXCEEDED_MAX_CMP_MSG_NUM . + #define MSDM_REG_INT_MASK_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define MSDM_REG_INT_MASK_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.EXPECTED_LAST_CYCLE . + #define MSDM_REG_INT_MASK_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define MSDM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.UNEXPECTED_LAST_CYCLE . + #define MSDM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define MSDM_REG_INT_STS_WR 0xfc0048UL //Access:WR DataWidth:0x1f // Multi Field Register. #define MSDM_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define MSDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT 0 #define MSDM_REG_INT_STS_WR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -70774,7 +75170,13 @@ #define MSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define MSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define MSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define MSDM_REG_INT_STS_CLR 0xfc004cUL //Access:RC DataWidth:0x1c // Multi Field Register. + #define MSDM_REG_INT_STS_WR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define MSDM_REG_INT_STS_WR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define MSDM_REG_INT_STS_WR_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define MSDM_REG_INT_STS_WR_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define MSDM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define MSDM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define MSDM_REG_INT_STS_CLR 0xfc004cUL //Access:RC DataWidth:0x1f // Multi Field Register. #define MSDM_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define MSDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT 0 #define MSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -70831,6 +75233,12 @@ #define MSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define MSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define MSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 + #define MSDM_REG_INT_STS_CLR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define MSDM_REG_INT_STS_CLR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define MSDM_REG_INT_STS_CLR_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define MSDM_REG_INT_STS_CLR_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define MSDM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define MSDM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 #define MSDM_REG_PRTY_MASK_H_0 0xfc0204UL //Access:RW DataWidth:0xc // Multi Field Register. #define MSDM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT . #define MSDM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_E5_SHIFT 0 @@ -70930,10 +75338,12 @@ #define MSDM_REG_BRB_ALMOST_FULL 0xfc0700UL //Access:RW DataWidth:0x5 // Almost full signal for read data from BRB in DMA_RSP block. #define MSDM_REG_PXP_ALMOST_FULL 0xfc0704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block. #define MSDM_REG_DORQ_ALMOST_FULL 0xfc0708UL //Access:RW DataWidth:0x6 // Almost full signal for read data from DORQ in SDM_DORQ block. -#define MSDM_REG_AGG_INT_CTRL 0xfc0800UL //Access:RW DataWidth:0x12 // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [17:16] Affinity [15:12] NumL2m: Field is passed transparently to FIC message in case of direct messge. [11] Exclusive: . [10] Core-selection where 0=Core_A and 1=Core_B. [9] Mode bit where 0=normal and 1=auto-mask-mode. [7:0] EventID which selects the event ID of the associated handler. -#define MSDM_REG_AGG_INT_CTRL_SIZE 32 +#define MSDM_REG_AGG_INT_CTRL 0xfc0800UL //Access:RW DataWidth:0x16 // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [21:20] Affinity [19:16] NumL2m: Field is passed transparently to FIC message in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode bit where 0=normal and 1=auto-mask-mode. [8] Reserved/Unused. [7:0] EventID which selects the event ID of the associated handler. +#define MSDM_REG_AGG_INT_CTRL_SIZE_BB_K2 32 +#define MSDM_REG_AGG_INT_CTRL_SIZE_E5 16 #define MSDM_REG_AGG_INT_STATE 0xfc0a00UL //Access:R DataWidth:0x2 // This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM. -#define MSDM_REG_AGG_INT_STATE_SIZE 32 +#define MSDM_REG_AGG_INT_STATE_SIZE_BB_K2 32 +#define MSDM_REG_AGG_INT_STATE_SIZE_E5 16 #define MSDM_REG_QUEUE_FULL 0xfc0c00UL //Access:R DataWidth:0x9 // Input queue fifo full in sdm_inp block. #define MSDM_REG_INT_CMPL_PEND_FULL 0xfc0c04UL //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block. #define MSDM_REG_INT_CPRM_PEND_FULL 0xfc0c08UL //Access:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block. @@ -71148,7 +75558,7 @@ #define USDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT 8 #define USDM_REG_DISABLE_ENGINE_DISABLE_DORQ (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands. #define USDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT 9 -#define USDM_REG_INT_STS 0xfd0040UL //Access:R DataWidth:0x1c // Multi Field Register. +#define USDM_REG_INT_STS 0xfd0040UL //Access:R DataWidth:0x1f // Multi Field Register. #define USDM_REG_INT_STS_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define USDM_REG_INT_STS_ADDRESS_ERROR_SHIFT 0 #define USDM_REG_INT_STS_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -71205,7 +75615,13 @@ #define USDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define USDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define USDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define USDM_REG_INT_MASK 0xfd0044UL //Access:RW DataWidth:0x1c // Multi Field Register. + #define USDM_REG_INT_STS_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define USDM_REG_INT_STS_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define USDM_REG_INT_STS_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define USDM_REG_INT_STS_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define USDM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define USDM_REG_INT_STS_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define USDM_REG_INT_MASK 0xfd0044UL //Access:RW DataWidth:0x1f // Multi Field Register. #define USDM_REG_INT_MASK_ADDRESS_ERROR (0x1<<0) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.ADDRESS_ERROR . #define USDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT 0 #define USDM_REG_INT_MASK_INP_QUEUE_ERROR (0x1<<1) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.INP_QUEUE_ERROR . @@ -71262,7 +75678,13 @@ #define USDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define USDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR . #define USDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define USDM_REG_INT_STS_WR 0xfd0048UL //Access:WR DataWidth:0x1c // Multi Field Register. + #define USDM_REG_INT_MASK_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.TIMERS_EXCEEDED_MAX_CMP_MSG_NUM . + #define USDM_REG_INT_MASK_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define USDM_REG_INT_MASK_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.EXPECTED_LAST_CYCLE . + #define USDM_REG_INT_MASK_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define USDM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.UNEXPECTED_LAST_CYCLE . + #define USDM_REG_INT_MASK_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define USDM_REG_INT_STS_WR 0xfd0048UL //Access:WR DataWidth:0x1f // Multi Field Register. #define USDM_REG_INT_STS_WR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define USDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT 0 #define USDM_REG_INT_STS_WR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -71319,7 +75741,13 @@ #define USDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define USDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define USDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 -#define USDM_REG_INT_STS_CLR 0xfd004cUL //Access:RC DataWidth:0x1c // Multi Field Register. + #define USDM_REG_INT_STS_WR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define USDM_REG_INT_STS_WR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define USDM_REG_INT_STS_WR_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define USDM_REG_INT_STS_WR_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define USDM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define USDM_REG_INT_STS_WR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 +#define USDM_REG_INT_STS_CLR 0xfd004cUL //Access:RC DataWidth:0x1f // Multi Field Register. #define USDM_REG_INT_STS_CLR_ADDRESS_ERROR (0x1<<0) // Signals an unknown address to the rf module. #define USDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT 0 #define USDM_REG_INT_STS_CLR_INP_QUEUE_ERROR (0x1<<1) // Indicates that one of the input queues had a FIFO error. @@ -71376,6 +75804,12 @@ #define USDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 26 #define USDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM and MSDM =>YCM interface #define USDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_K2_E5_SHIFT 27 + #define USDM_REG_INT_STS_CLR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5 (0x1<<28) // Attempted to allocate a timer completion message entry, when no entries were available. + #define USDM_REG_INT_STS_CLR_TIMERS_EXCEEDED_MAX_CMP_MSG_NUM_E5_SHIFT 28 + #define USDM_REG_INT_STS_CLR_EXPECTED_LAST_CYCLE_E5 (0x1<<29) // Last-cycle indication not found during external store request. + #define USDM_REG_INT_STS_CLR_EXPECTED_LAST_CYCLE_E5_SHIFT 29 + #define USDM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5 (0x1<<30) // Unexpected last_cycle indication seen during external store requeset. + #define USDM_REG_INT_STS_CLR_UNEXPECTED_LAST_CYCLE_E5_SHIFT 30 #define USDM_REG_PRTY_MASK_H_0 0xfd0204UL //Access:RW DataWidth:0xb // Multi Field Register. #define USDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2 (0x1<<9) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . #define USDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT 9 @@ -71446,10 +75880,12 @@ #define USDM_REG_BRB_ALMOST_FULL 0xfd0700UL //Access:RW DataWidth:0x5 // Almost full signal for read data from BRB in DMA_RSP block. #define USDM_REG_PXP_ALMOST_FULL 0xfd0704UL //Access:RW DataWidth:0x4 // Almost full signal for read data from pxp in DMA_RSP block. #define USDM_REG_DORQ_ALMOST_FULL 0xfd0708UL //Access:RW DataWidth:0x6 // Almost full signal for read data from DORQ in SDM_DORQ block. -#define USDM_REG_AGG_INT_CTRL 0xfd0800UL //Access:RW DataWidth:0x12 // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [17:16] Affinity [15:12] NumL2m: Field is passed transparently to FIC message in case of direct messge. [11] Exclusive: . [10] Core-selection where 0=Core_A and 1=Core_B. [9] Mode bit where 0=normal and 1=auto-mask-mode. [7:0] EventID which selects the event ID of the associated handler. -#define USDM_REG_AGG_INT_CTRL_SIZE 32 +#define USDM_REG_AGG_INT_CTRL 0xfd0800UL //Access:RW DataWidth:0x16 // This array of registers provides controls for each of the aggregated interrupts; The fields are defined as follows: [21:20] Affinity [19:16] NumL2m: Field is passed transparently to FIC message in case of direct messge. [15] Exclusive: . [14:12] Core-selection where 0=Core_0 and 1=Core_1,... [11:10] Reserved/Unused. [9] Mode bit where 0=normal and 1=auto-mask-mode. [8] Reserved/Unused. [7:0] EventID which selects the event ID of the associated handler. +#define USDM_REG_AGG_INT_CTRL_SIZE_BB_K2 32 +#define USDM_REG_AGG_INT_CTRL_SIZE_E5 16 #define USDM_REG_AGG_INT_STATE 0xfd0a00UL //Access:R DataWidth:0x2 // This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM. -#define USDM_REG_AGG_INT_STATE_SIZE 32 +#define USDM_REG_AGG_INT_STATE_SIZE_BB_K2 32 +#define USDM_REG_AGG_INT_STATE_SIZE_E5 16 #define USDM_REG_QUEUE_FULL 0xfd0c00UL //Access:R DataWidth:0x9 // Input queue fifo full in sdm_inp block. #define USDM_REG_INT_CMPL_PEND_FULL 0xfd0c04UL //Access:R DataWidth:0x1 // Internal write completion pending full in internal write block. #define USDM_REG_INT_CPRM_PEND_FULL 0xfd0c08UL //Access:R DataWidth:0x1 // Internal write completion parameter pending full in internal write block. @@ -72059,8 +76495,10 @@ #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_ILLEG_PQNUM (0x1<<7) // Access to illegal PQ number in QM Active State Counter (more than 447). #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_ILLEG_PQNUM_SHIFT 7 #define XCM_REG_PRTY_MASK_H_0 0x1000204UL //Access:RW DataWidth:0x1f // Multi Field Register. - #define XCM_REG_PRTY_MASK_H_0_MEM036_I_ECC_RF_INT_K2_E5 (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM036_I_ECC_RF_INT . - #define XCM_REG_PRTY_MASK_H_0_MEM036_I_ECC_RF_INT_K2_E5_SHIFT 0 + #define XCM_REG_PRTY_MASK_H_0_MEM035_I_ECC_RF_INT_BB (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM035_I_ECC_RF_INT . + #define XCM_REG_PRTY_MASK_H_0_MEM035_I_ECC_RF_INT_BB_SHIFT 0 + #define XCM_REG_PRTY_MASK_H_0_MEM035_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM035_I_ECC_RF_INT . + #define XCM_REG_PRTY_MASK_H_0_MEM035_I_ECC_RF_INT_E5_SHIFT 0 #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT . #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_SHIFT 1 #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT . @@ -72073,226 +76511,168 @@ #define XCM_REG_PRTY_MASK_H_0_MEM004_I_ECC_0_RF_INT_E5_SHIFT 5 #define XCM_REG_PRTY_MASK_H_0_MEM004_I_ECC_1_RF_INT_E5 (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM004_I_ECC_1_RF_INT . #define XCM_REG_PRTY_MASK_H_0_MEM004_I_ECC_1_RF_INT_E5_SHIFT 6 - #define XCM_REG_PRTY_MASK_H_0_MEM034_I_ECC_0_RF_INT_E5 (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM034_I_ECC_0_RF_INT . - #define XCM_REG_PRTY_MASK_H_0_MEM034_I_ECC_0_RF_INT_E5_SHIFT 7 - #define XCM_REG_PRTY_MASK_H_0_MEM034_I_ECC_1_RF_INT_E5 (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM034_I_ECC_1_RF_INT . - #define XCM_REG_PRTY_MASK_H_0_MEM034_I_ECC_1_RF_INT_E5_SHIFT 8 + #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_0_RF_INT_K2 (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_ECC_0_RF_INT . + #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_0_RF_INT_K2_SHIFT 6 + #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_0_RF_INT_E5 (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_ECC_0_RF_INT . + #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_0_RF_INT_E5_SHIFT 7 + #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_1_RF_INT_K2 (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_ECC_1_RF_INT . + #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_1_RF_INT_K2_SHIFT 7 + #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_1_RF_INT_E5 (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_ECC_1_RF_INT . + #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_1_RF_INT_E5_SHIFT 8 #define XCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY (0x1<<9) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_SHIFT 9 - #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB (0x1<<17) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_SHIFT 17 - #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2 (0x1<<18) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2_SHIFT 18 - #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_E5_SHIFT 10 - #define XCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_K2 (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_K2_SHIFT 10 - #define XCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5_SHIFT 11 - #define XCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_K2 (0x1<<11) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_K2_SHIFT 11 - #define XCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5_SHIFT 12 - #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB (0x1<<27) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_SHIFT 27 - #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2 (0x1<<15) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2_SHIFT 15 - #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_E5_SHIFT 13 - #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB (0x1<<12) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_SHIFT 12 - #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2 (0x1<<13) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT 13 - #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5_SHIFT 14 + #define XCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_SHIFT 10 + #define XCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY (0x1<<11) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_SHIFT 11 #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB (0x1<<14) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_SHIFT 14 - #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2 (0x1<<12) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT 12 - #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_E5_SHIFT 15 - #define XCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2 (0x1<<28) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2_SHIFT 28 - #define XCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_E5_SHIFT 16 + #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_E5 (0x1<<12) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_E5_SHIFT 12 + #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB (0x1<<12) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_SHIFT 12 + #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_E5 (0x1<<13) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_E5_SHIFT 13 + #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB (0x1<<13) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_SHIFT 13 + #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_E5 (0x1<<14) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_E5_SHIFT 14 + #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB (0x1<<27) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_SHIFT 27 + #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2_E5 (0x1<<15) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2_E5_SHIFT 15 #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB (0x1<<15) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_SHIFT 15 - #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2 (0x1<<16) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT 16 - #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5_SHIFT 17 + #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_E5 (0x1<<16) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_E5_SHIFT 16 #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB (0x1<<16) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_SHIFT 16 - #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2 (0x1<<17) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_SHIFT 17 - #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5_SHIFT 18 - #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB (0x1<<13) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_SHIFT 13 - #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2 (0x1<<14) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_SHIFT 14 - #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_E5_SHIFT 19 + #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_E5 (0x1<<17) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_E5_SHIFT 17 + #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB (0x1<<17) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_SHIFT 17 + #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2_E5 (0x1<<18) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2_E5_SHIFT 18 #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB (0x1<<18) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_SHIFT 18 - #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2 (0x1<<19) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_SHIFT 19 - #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5_SHIFT 20 + #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_E5 (0x1<<19) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_E5_SHIFT 19 #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB (0x1<<19) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_SHIFT 19 - #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2 (0x1<<20) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT 20 - #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5_SHIFT 21 + #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_E5 (0x1<<20) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_E5_SHIFT 20 #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB (0x1<<20) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_SHIFT 20 - #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2 (0x1<<21) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT 21 - #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5_SHIFT 22 + #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_E5 (0x1<<21) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_E5_SHIFT 21 #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB (0x1<<21) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_SHIFT 21 - #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2 (0x1<<22) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT 22 - #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5_SHIFT 23 - #define XCM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_K2 (0x1<<23) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_K2_SHIFT 23 - #define XCM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_E5_SHIFT 24 + #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_E5 (0x1<<22) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_E5_SHIFT 22 #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB (0x1<<22) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_SHIFT 22 #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_K2 (0x1<<24) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_K2_SHIFT 24 - #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_E5_SHIFT 25 + #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_E5_SHIFT 23 #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB (0x1<<23) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB_SHIFT 23 #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_K2 (0x1<<25) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_K2_SHIFT 25 - #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_E5_SHIFT 26 + #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_E5_SHIFT 24 + #define XCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB (0x1<<24) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB_SHIFT 24 + #define XCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_E5_SHIFT 25 #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB (0x1<<25) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_SHIFT 25 - #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2 (0x1<<26) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_SHIFT 26 - #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5_SHIFT 27 - #define XCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2 (0x1<<27) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2_SHIFT 27 - #define XCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_E5_SHIFT 28 - #define XCM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_E5_SHIFT 29 + #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_E5 (0x1<<26) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_E5_SHIFT 26 + #define XCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB (0x1<<26) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_SHIFT 26 + #define XCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5_SHIFT 27 + #define XCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2_E5 (0x1<<28) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2_E5_SHIFT 28 #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB (0x1<<28) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT 28 - #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2 (0x1<<29) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT 29 - #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_E5_SHIFT 30 + #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_E5 (0x1<<29) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_E5_SHIFT 29 + #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB (0x1<<29) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_SHIFT 29 + #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_E5 (0x1<<30) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_E5_SHIFT 30 + #define XCM_REG_PRTY_MASK_H_0_MEM036_I_ECC_RF_INT_K2 (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM036_I_ECC_RF_INT . + #define XCM_REG_PRTY_MASK_H_0_MEM036_I_ECC_RF_INT_K2_SHIFT 0 #define XCM_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_BB_K2 (0x1<<5) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT . #define XCM_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_BB_K2_SHIFT 5 - #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_0_RF_INT_K2 (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_ECC_0_RF_INT . - #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_0_RF_INT_K2_SHIFT 6 - #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_1_RF_INT_K2 (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_ECC_1_RF_INT . - #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_1_RF_INT_K2_SHIFT 7 #define XCM_REG_PRTY_MASK_H_0_MEM034_I_ECC_RF_INT_K2 (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM034_I_ECC_RF_INT . #define XCM_REG_PRTY_MASK_H_0_MEM034_I_ECC_RF_INT_K2_SHIFT 8 - #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB (0x1<<29) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_SHIFT 29 - #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2 (0x1<<30) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT 30 - #define XCM_REG_PRTY_MASK_H_0_MEM035_I_ECC_RF_INT_BB (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM035_I_ECC_RF_INT . - #define XCM_REG_PRTY_MASK_H_0_MEM035_I_ECC_RF_INT_BB_SHIFT 0 + #define XCM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_K2 (0x1<<23) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_K2_SHIFT 23 + #define XCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2 (0x1<<27) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2_SHIFT 27 #define XCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_0_RF_INT_BB (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM032_I_ECC_0_RF_INT . #define XCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_0_RF_INT_BB_SHIFT 6 #define XCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_1_RF_INT_BB (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM032_I_ECC_1_RF_INT . #define XCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_1_RF_INT_BB_SHIFT 7 #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT_BB (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_ECC_RF_INT . #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT_BB_SHIFT 8 - #define XCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB (0x1<<24) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB_SHIFT 24 - #define XCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB (0x1<<26) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_SHIFT 26 #define XCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB (0x1<<30) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_SHIFT 30 -#define XCM_REG_PRTY_MASK_H_1 0x1000214UL //Access:RW DataWidth:0xd // Multi Field Register. - #define XCM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_E5_SHIFT 0 - #define XCM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_K2 (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_K2_SHIFT 0 - #define XCM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_E5_SHIFT 1 - #define XCM_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_E5_SHIFT 2 +#define XCM_REG_PRTY_MASK_H_1 0x1000214UL //Access:RW DataWidth:0xc // Multi Field Register. + #define XCM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_K2_E5 (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_K2_E5_SHIFT 0 + #define XCM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_K2_E5 (0x1<<1) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_K2_E5_SHIFT 1 #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_BB (0x1<<1) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_BB_SHIFT 1 - #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_K2 (0x1<<2) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_K2_SHIFT 2 - #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_E5_SHIFT 3 + #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_K2_E5 (0x1<<2) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_K2_E5_SHIFT 2 #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB (0x1<<2) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB_SHIFT 2 - #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_K2 (0x1<<3) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_K2_SHIFT 3 - #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_E5_SHIFT 4 + #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_K2_E5 (0x1<<3) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_K2_E5_SHIFT 3 #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_BB (0x1<<3) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_BB_SHIFT 3 - #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2 (0x1<<4) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2_SHIFT 4 - #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5_SHIFT 5 + #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2_E5 (0x1<<4) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2_E5_SHIFT 4 #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB (0x1<<4) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_SHIFT 4 - #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2 (0x1<<5) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2_SHIFT 5 - #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_E5_SHIFT 6 + #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2_E5 (0x1<<5) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2_E5_SHIFT 5 #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB (0x1<<5) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_SHIFT 5 - #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_K2 (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_K2_SHIFT 6 - #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_E5_SHIFT 7 + #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_K2_E5 (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_K2_E5_SHIFT 6 #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_BB (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_BB_SHIFT 6 - #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_K2 (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_K2_SHIFT 7 - #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_E5_SHIFT 8 + #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_K2_E5 (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_K2_E5_SHIFT 7 #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_SHIFT 7 - #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_K2 (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_K2_SHIFT 8 - #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_E5_SHIFT 9 + #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_K2_E5 (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_K2_E5_SHIFT 8 #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_SHIFT 8 - #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_K2 (0x1<<9) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_K2_SHIFT 9 - #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_E5_SHIFT 10 + #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_K2_E5 (0x1<<9) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_K2_E5_SHIFT 9 #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB (0x1<<9) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_SHIFT 9 - #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2 (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_SHIFT 10 - #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5_SHIFT 11 + #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_E5 (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_E5_SHIFT 10 #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_SHIFT 10 - #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2 (0x1<<11) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_SHIFT 11 - #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5_SHIFT 12 - #define XCM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_K2 (0x1<<1) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY . - #define XCM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_K2_SHIFT 1 + #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_E5 (0x1<<11) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . + #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_E5_SHIFT 11 #define XCM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY . #define XCM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB_SHIFT 0 #define XCM_REG_MEM_ECC_ENABLE_0 0x1000220UL //Access:RW DataWidth:0x9 // Multi Field Register. - #define XCM_REG_MEM_ECC_ENABLE_0_MEM036_I_ECC_EN_K2_E5 (0x1<<0) // Enable ECC for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram - #define XCM_REG_MEM_ECC_ENABLE_0_MEM036_I_ECC_EN_K2_E5_SHIFT 0 + #define XCM_REG_MEM_ECC_ENABLE_0_MEM035_I_ECC_EN_BB (0x1<<0) // Enable ECC for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram + #define XCM_REG_MEM_ECC_ENABLE_0_MEM035_I_ECC_EN_BB_SHIFT 0 + #define XCM_REG_MEM_ECC_ENABLE_0_MEM035_I_ECC_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram + #define XCM_REG_MEM_ECC_ENABLE_0_MEM035_I_ECC_EN_E5_SHIFT 0 #define XCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN (0x1<<1) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_0 in module xcm_mem_agg_con_ctx_0_7 #define XCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN_SHIFT 1 #define XCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN (0x1<<2) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_1 in module xcm_mem_agg_con_ctx_0_7 @@ -72305,20 +76685,20 @@ #define XCM_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_0_EN_E5_SHIFT 5 #define XCM_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_1_EN_E5 (0x1<<6) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_8_9.i_ecc_1 in module xcm_mem_agg_con_ctx_8_9 #define XCM_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_1_EN_E5_SHIFT 6 - #define XCM_REG_MEM_ECC_ENABLE_0_MEM034_I_ECC_0_EN_E5 (0x1<<7) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx.i_ecc_0 in module xcm_mem_sm_con_ctx - #define XCM_REG_MEM_ECC_ENABLE_0_MEM034_I_ECC_0_EN_E5_SHIFT 7 - #define XCM_REG_MEM_ECC_ENABLE_0_MEM034_I_ECC_1_EN_E5 (0x1<<8) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx.i_ecc_1 in module xcm_mem_sm_con_ctx - #define XCM_REG_MEM_ECC_ENABLE_0_MEM034_I_ECC_1_EN_E5_SHIFT 8 - #define XCM_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_BB_K2 (0x1<<5) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_8.i_ecc in module xcm_mem_agg_con_ctx_8 - #define XCM_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_BB_K2_SHIFT 5 #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_0_EN_K2 (0x1<<6) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13 #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_0_EN_K2_SHIFT 6 + #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_0_EN_E5 (0x1<<7) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx.i_ecc_0 in module xcm_mem_sm_con_ctx + #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_0_EN_E5_SHIFT 7 #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_1_EN_K2 (0x1<<7) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13 #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_1_EN_K2_SHIFT 7 + #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_1_EN_E5 (0x1<<8) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx.i_ecc_1 in module xcm_mem_sm_con_ctx + #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_1_EN_E5_SHIFT 8 + #define XCM_REG_MEM_ECC_ENABLE_0_MEM036_I_ECC_EN_K2 (0x1<<0) // Enable ECC for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram + #define XCM_REG_MEM_ECC_ENABLE_0_MEM036_I_ECC_EN_K2_SHIFT 0 + #define XCM_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_BB_K2 (0x1<<5) // Enable ECC for memory ecc instance xcm.i_agg_con_ctx_8.i_ecc in module xcm_mem_agg_con_ctx_8 + #define XCM_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_BB_K2_SHIFT 5 #define XCM_REG_MEM_ECC_ENABLE_0_MEM034_I_ECC_EN_K2 (0x1<<8) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14 #define XCM_REG_MEM_ECC_ENABLE_0_MEM034_I_ECC_EN_K2_SHIFT 8 - #define XCM_REG_MEM_ECC_ENABLE_0_MEM035_I_ECC_EN_BB (0x1<<0) // Enable ECC for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram - #define XCM_REG_MEM_ECC_ENABLE_0_MEM035_I_ECC_EN_BB_SHIFT 0 #define XCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_0_EN_BB (0x1<<6) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13 #define XCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_0_EN_BB_SHIFT 6 #define XCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_1_EN_BB (0x1<<7) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13 @@ -72326,8 +76706,10 @@ #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_EN_BB (0x1<<8) // Enable ECC for memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14 #define XCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_EN_BB_SHIFT 8 #define XCM_REG_MEM_ECC_PARITY_ONLY_0 0x1000224UL //Access:RW DataWidth:0x9 // Multi Field Register. - #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM036_I_ECC_PRTY_K2_E5 (0x1<<0) // Set parity only for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram - #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM036_I_ECC_PRTY_K2_E5_SHIFT 0 + #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM035_I_ECC_PRTY_BB (0x1<<0) // Set parity only for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram + #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM035_I_ECC_PRTY_BB_SHIFT 0 + #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM035_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram + #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM035_I_ECC_PRTY_E5_SHIFT 0 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY (0x1<<1) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_0 in module xcm_mem_agg_con_ctx_0_7 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY_SHIFT 1 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY (0x1<<2) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_1 in module xcm_mem_agg_con_ctx_0_7 @@ -72340,20 +76722,20 @@ #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_0_PRTY_E5_SHIFT 5 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_1_PRTY_E5 (0x1<<6) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_8_9.i_ecc_1 in module xcm_mem_agg_con_ctx_8_9 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_1_PRTY_E5_SHIFT 6 - #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM034_I_ECC_0_PRTY_E5 (0x1<<7) // Set parity only for memory ecc instance xcm.i_sm_con_ctx.i_ecc_0 in module xcm_mem_sm_con_ctx - #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM034_I_ECC_0_PRTY_E5_SHIFT 7 - #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM034_I_ECC_1_PRTY_E5 (0x1<<8) // Set parity only for memory ecc instance xcm.i_sm_con_ctx.i_ecc_1 in module xcm_mem_sm_con_ctx - #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM034_I_ECC_1_PRTY_E5_SHIFT 8 - #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_BB_K2 (0x1<<5) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_8.i_ecc in module xcm_mem_agg_con_ctx_8 - #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_BB_K2_SHIFT 5 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_0_PRTY_K2 (0x1<<6) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_0_PRTY_K2_SHIFT 6 + #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_0_PRTY_E5 (0x1<<7) // Set parity only for memory ecc instance xcm.i_sm_con_ctx.i_ecc_0 in module xcm_mem_sm_con_ctx + #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_0_PRTY_E5_SHIFT 7 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_1_PRTY_K2 (0x1<<7) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_1_PRTY_K2_SHIFT 7 + #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_1_PRTY_E5 (0x1<<8) // Set parity only for memory ecc instance xcm.i_sm_con_ctx.i_ecc_1 in module xcm_mem_sm_con_ctx + #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_1_PRTY_E5_SHIFT 8 + #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM036_I_ECC_PRTY_K2 (0x1<<0) // Set parity only for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram + #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM036_I_ECC_PRTY_K2_SHIFT 0 + #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_BB_K2 (0x1<<5) // Set parity only for memory ecc instance xcm.i_agg_con_ctx_8.i_ecc in module xcm_mem_agg_con_ctx_8 + #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_BB_K2_SHIFT 5 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM034_I_ECC_PRTY_K2 (0x1<<8) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM034_I_ECC_PRTY_K2_SHIFT 8 - #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM035_I_ECC_PRTY_BB (0x1<<0) // Set parity only for memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram - #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM035_I_ECC_PRTY_BB_SHIFT 0 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_0_PRTY_BB (0x1<<6) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_0_PRTY_BB_SHIFT 6 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_1_PRTY_BB (0x1<<7) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13 @@ -72361,8 +76743,10 @@ #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_PRTY_BB (0x1<<8) // Set parity only for memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14 #define XCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_PRTY_BB_SHIFT 8 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0 0x1000228UL //Access:RC DataWidth:0x9 // Multi Field Register. - #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM036_I_ECC_CORRECT_K2_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram - #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM036_I_ECC_CORRECT_K2_E5_SHIFT 0 + #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM035_I_ECC_CORRECT_BB (0x1<<0) // Record if a correctable error occurred on memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram + #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM035_I_ECC_CORRECT_BB_SHIFT 0 + #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM035_I_ECC_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram + #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM035_I_ECC_CORRECT_E5_SHIFT 0 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_0 in module xcm_mem_agg_con_ctx_0_7 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT_SHIFT 1 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance xcm.i_agg_con_ctx_0_7.i_ecc_1 in module xcm_mem_agg_con_ctx_0_7 @@ -72375,20 +76759,20 @@ #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_0_CORRECT_E5_SHIFT 5 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_1_CORRECT_E5 (0x1<<6) // Record if a correctable error occurred on memory ecc instance xcm.i_agg_con_ctx_8_9.i_ecc_1 in module xcm_mem_agg_con_ctx_8_9 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_1_CORRECT_E5_SHIFT 6 - #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM034_I_ECC_0_CORRECT_E5 (0x1<<7) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx.i_ecc_0 in module xcm_mem_sm_con_ctx - #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM034_I_ECC_0_CORRECT_E5_SHIFT 7 - #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM034_I_ECC_1_CORRECT_E5 (0x1<<8) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx.i_ecc_1 in module xcm_mem_sm_con_ctx - #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM034_I_ECC_1_CORRECT_E5_SHIFT 8 - #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_BB_K2 (0x1<<5) // Record if a correctable error occurred on memory ecc instance xcm.i_agg_con_ctx_8.i_ecc in module xcm_mem_agg_con_ctx_8 - #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_BB_K2_SHIFT 5 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_0_CORRECT_K2 (0x1<<6) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_0_CORRECT_K2_SHIFT 6 + #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_0_CORRECT_E5 (0x1<<7) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx.i_ecc_0 in module xcm_mem_sm_con_ctx + #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_0_CORRECT_E5_SHIFT 7 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_1_CORRECT_K2 (0x1<<7) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_1_CORRECT_K2_SHIFT 7 + #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_1_CORRECT_E5 (0x1<<8) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx.i_ecc_1 in module xcm_mem_sm_con_ctx + #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_1_CORRECT_E5_SHIFT 8 + #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM036_I_ECC_CORRECT_K2 (0x1<<0) // Record if a correctable error occurred on memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram + #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM036_I_ECC_CORRECT_K2_SHIFT 0 + #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_BB_K2 (0x1<<5) // Record if a correctable error occurred on memory ecc instance xcm.i_agg_con_ctx_8.i_ecc in module xcm_mem_agg_con_ctx_8 + #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_BB_K2_SHIFT 5 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM034_I_ECC_CORRECT_K2 (0x1<<8) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_14.i_ecc in module xcm_mem_sm_con_ctx_14 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM034_I_ECC_CORRECT_K2_SHIFT 8 - #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM035_I_ECC_CORRECT_BB (0x1<<0) // Record if a correctable error occurred on memory ecc instance xcm.i_xx_msg_ram.i_ecc in module xcm_mem_xx_msg_ram - #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM035_I_ECC_CORRECT_BB_SHIFT 0 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_0_CORRECT_BB (0x1<<6) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_0 in module xcm_mem_sm_con_ctx_0_13 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_0_CORRECT_BB_SHIFT 6 #define XCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_1_CORRECT_BB (0x1<<7) // Record if a correctable error occurred on memory ecc instance xcm.i_sm_con_ctx_0_13.i_ecc_1 in module xcm_mem_sm_con_ctx_0_13 @@ -72483,7 +76867,7 @@ #define XCM_REG_PBF_FRWRD_MODE_BB_K2 0x100067cUL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward. #define XCM_REG_SDM_ERR_HANDLE_EN 0x1000680UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message. #define XCM_REG_DIR_BYP_EN 0x1000684UL //Access:RW DataWidth:0x1 // Direct bypass enable. -#define XCM_REG_FI_DESC_INPUT_VIOLATE 0x1000688UL //Access:R DataWidth:0x13 // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0 then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation: Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS; [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: XxBypass message in PCM block; [15] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [16] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [17]- Violation: Connection domain AggCtxLdStFlg==0 then AffinityType != 2; [18]- Violation: single Task domain AggCtxLdStFlg==0 then AffinityType != 3; +#define XCM_REG_FI_DESC_INPUT_VIOLATE 0x1000688UL //Access:R DataWidth:0x13 // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0 then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation: Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS; [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: Agg Store message then Loader done with error; [15] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [16] - Violation: Direct message: Task domain doesn't exist then AffinityType != 3; [17]- Violation: Connection domain AggCtxLdStFlg==0 then AffinityType != 2; [18]- Violation: single Task domain AggCtxLdStFlg==0 then AffinityType != 3; #define XCM_REG_IA_AGG_CON_PART_FILL_LVL 0x100068cUL //Access:R DataWidth:0x3 // Input Arbiter Aggregation Connection part FIFO fill level (in messages). #define XCM_REG_IA_SM_CON_PART_FILL_LVL 0x1000690UL //Access:R DataWidth:0x3 // Input Arbiter Storm Connection part FIFO fill level (in messages). #define XCM_REG_IA_TRANS_PART_FILL_LVL 0x1000694UL //Access:R DataWidth:0x3 // Input Arbiter Transparent part FIFO fill level (in messages). @@ -72568,27 +76952,27 @@ #define XCM_REG_CCFC_CURR_ST 0x1000a1cUL //Access:R DataWidth:0x1 // CFC connection output FSM current state. #define XCM_REG_CMPL_DIR_CURR_ST 0x1000a20UL //Access:R DataWidth:0x4 // Direct Completer FSM current state. #define XCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG 0x1000a24UL //Access:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM output Event ID. -#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_0_E5 0x1000a28UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_1_E5 0x1000a2cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_2_E5 0x1000a30UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_3_E5 0x1000a34UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_4_E5 0x1000a38UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_5_E5 0x1000a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_6_E5 0x1000a40UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_7_E5 0x1000a44UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_8_E5 0x1000a48UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_9_E5 0x1000a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_10_E5 0x1000a50UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_11_E5 0x1000a54UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_12_E5 0x1000a58UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_13_E5 0x1000a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_14_E5 0x1000a60UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_15_E5 0x1000a64UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. +#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_0_E5 0x1000a28UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_1_E5 0x1000a2cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_2_E5 0x1000a30UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_3_E5 0x1000a34UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_4_E5 0x1000a38UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_5_E5 0x1000a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_6_E5 0x1000a40UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_7_E5 0x1000a44UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_8_E5 0x1000a48UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_9_E5 0x1000a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_10_E5 0x1000a50UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_11_E5 0x1000a54UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_12_E5 0x1000a58UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_13_E5 0x1000a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_14_E5 0x1000a60UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define XCM_REG_CM_CON_EVENT_ID_BWIDTH_15_E5 0x1000a64UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. #define XCM_REG_CCFC_INIT_CRD 0x1000a84UL //Access:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. #define XCM_REG_QM_INIT_CRD0 0x1000a88UL //Access:RW DataWidth:0x5 // QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter. #define XCM_REG_QM_INIT_CRD1 0x1000a8cUL //Access:RW DataWidth:0x5 // QM output initial credit (XCM TX queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter. #define XCM_REG_TM_INIT_CRD 0x1000a90UL //Access:RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. -#define XCM_REG_FIC_INIT_CRD 0x1000a94UL //Access:RW DataWidth:0x6 // FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up. +#define XCM_REG_FIC_INIT_CRD 0x1000a94UL //Access:RW DataWidth:0x5 // FIC output initial credit in REGQ pairs. Write writes the initial credit value; read returns the current value of the credit counter. #define XCM_REG_DIR_BYP_MSG_CNT 0x1000aa4UL //Access:RC DataWidth:0x20 // Counter of direct bypassed messages. #define XCM_REG_XSDM_LENGTH_MIS 0x1000aacUL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at XSDM interface. #define XCM_REG_YSDM_LENGTH_MIS 0x1000ab0UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at YSDM interface. @@ -72668,7 +77052,7 @@ #define XCM_REG_XX_TBL 0x1001a00UL //Access:R DataWidth:0x18 // Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:12]; Next pointer: PCM - [11:10]; M/T/U/X/YCM - [23:18]; #define XCM_REG_XX_TBL_SIZE_BB_K2 30 #define XCM_REG_XX_TBL_SIZE_E5 64 -#define XCM_REG_XX_DSCR_TBL 0x1001b00UL //Access:RW DataWidth:0x11 // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek. +#define XCM_REG_XX_DSCR_TBL 0x1001b00UL //Access:RW DataWidth:0x11 // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[14:9]); Next pointer (MCM [20:15]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [20:15]); LTID (MCM [29:21]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [29:21]). Task Domain Exist (MCM [30]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [30]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek. #define XCM_REG_XX_DSCR_TBL_SIZE 64 #define XCM_REG_TM_CON_EVNT_ID_0_BB_K2 0x10004a4UL //Access:RW DataWidth:0x8 // TM connection Event ID per connection type. #define XCM_REG_TM_CON_EVNT_ID_0_E5 0x1001c00UL //Access:RW DataWidth:0x8 // TM connection Event ID per connection type. @@ -73279,16 +77663,16 @@ #define YCM_REG_INT_STS_CLR_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations. #define YCM_REG_INT_STS_CLR_2_QMREG_MORE4_SHIFT 0 #define YCM_REG_PRTY_MASK_H_0 0x1080204UL //Access:RW DataWidth:0x1f // Multi Field Register. - #define YCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM032_I_ECC_RF_INT . - #define YCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_RF_INT_E5_SHIFT 0 + #define YCM_REG_PRTY_MASK_H_0_MEM031_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM031_I_ECC_RF_INT . + #define YCM_REG_PRTY_MASK_H_0_MEM031_I_ECC_RF_INT_E5_SHIFT 0 #define YCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT . #define YCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_SHIFT 1 #define YCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT . #define YCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_SHIFT 2 - #define YCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_0_RF_INT_E5 (0x1<<3) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM028_I_ECC_0_RF_INT . - #define YCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_0_RF_INT_E5_SHIFT 3 - #define YCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_1_RF_INT_E5 (0x1<<4) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM028_I_ECC_1_RF_INT . - #define YCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_1_RF_INT_E5_SHIFT 4 + #define YCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_0_RF_INT_E5 (0x1<<3) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM027_I_ECC_0_RF_INT . + #define YCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_0_RF_INT_E5_SHIFT 3 + #define YCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_1_RF_INT_E5 (0x1<<4) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM027_I_ECC_1_RF_INT . + #define YCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_1_RF_INT_E5_SHIFT 4 #define YCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2 (0x1<<6) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT . #define YCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_K2_SHIFT 6 #define YCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_E5 (0x1<<5) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT . @@ -73299,42 +77683,42 @@ #define YCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_E5_SHIFT 6 #define YCM_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_E5 (0x1<<7) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT . #define YCM_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_E5_SHIFT 7 - #define YCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_0_RF_INT_E5 (0x1<<8) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM030_I_ECC_0_RF_INT . - #define YCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_0_RF_INT_E5_SHIFT 8 - #define YCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_1_RF_INT_E5 (0x1<<9) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM030_I_ECC_1_RF_INT . - #define YCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_1_RF_INT_E5_SHIFT 9 + #define YCM_REG_PRTY_MASK_H_0_MEM029_I_ECC_0_RF_INT_E5 (0x1<<8) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM029_I_ECC_0_RF_INT . + #define YCM_REG_PRTY_MASK_H_0_MEM029_I_ECC_0_RF_INT_E5_SHIFT 8 + #define YCM_REG_PRTY_MASK_H_0_MEM029_I_ECC_1_RF_INT_E5 (0x1<<9) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM029_I_ECC_1_RF_INT . + #define YCM_REG_PRTY_MASK_H_0_MEM029_I_ECC_1_RF_INT_E5_SHIFT 9 #define YCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2 (0x1<<27) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT 27 #define YCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5_SHIFT 10 - #define YCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5_SHIFT 11 #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB (0x1<<13) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_SHIFT 13 #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2 (0x1<<14) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT 14 - #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5_SHIFT 12 + #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5_SHIFT 11 #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB (0x1<<26) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_SHIFT 26 #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2 (0x1<<11) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT 11 - #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5_SHIFT 13 - #define YCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2 (0x1<<26) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2_SHIFT 26 - #define YCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5_SHIFT 14 + #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5_SHIFT 12 + #define YCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB (0x1<<25) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_SHIFT 25 + #define YCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5_SHIFT 13 #define YCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2 (0x1<<10) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2_SHIFT 10 - #define YCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5_SHIFT 15 + #define YCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5_SHIFT 14 #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB (0x1<<11) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_SHIFT 11 #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2 (0x1<<12) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT 12 - #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5_SHIFT 16 + #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5_SHIFT 15 + #define YCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5_SHIFT 16 #define YCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB (0x1<<23) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_SHIFT 23 #define YCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . @@ -73343,60 +77727,60 @@ #define YCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_SHIFT 24 #define YCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5_SHIFT 18 - #define YCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB (0x1<<25) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_SHIFT 25 - #define YCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5_SHIFT 19 #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB (0x1<<12) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_SHIFT 12 #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2 (0x1<<13) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT 13 - #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5_SHIFT 20 + #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5_SHIFT 19 #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB (0x1<<16) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_SHIFT 16 #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2 (0x1<<17) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2_SHIFT 17 - #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5_SHIFT 21 + #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5_SHIFT 20 #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB (0x1<<17) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_SHIFT 17 #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2 (0x1<<18) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT 18 - #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5_SHIFT 22 + #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5_SHIFT 21 #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB (0x1<<18) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_SHIFT 18 #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2 (0x1<<19) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT 19 - #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5_SHIFT 23 + #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5_SHIFT 22 #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB (0x1<<14) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_SHIFT 14 #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2 (0x1<<15) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT 15 - #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5_SHIFT 24 - #define YCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_E5_SHIFT 25 - #define YCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5_SHIFT 26 - #define YCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_E5_SHIFT 27 + #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5_SHIFT 23 + #define YCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5_SHIFT 24 + #define YCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_E5_SHIFT 25 + #define YCM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_E5_SHIFT 26 #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB (0x1<<22) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_SHIFT 22 #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2 (0x1<<23) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT 23 - #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5_SHIFT 28 - #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB (0x1<<19) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_SHIFT 19 - #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2 (0x1<<21) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT 21 - #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_E5_SHIFT 29 - #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5_SHIFT 30 + #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5_SHIFT 27 + #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB (0x1<<20) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_SHIFT 20 + #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2 (0x1<<22) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_SHIFT 22 + #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_E5_SHIFT 28 + #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5_SHIFT 29 + #define YCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2 (0x1<<20) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2_SHIFT 20 + #define YCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_E5_SHIFT 30 #define YCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_RF_INT_K2 (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM027_I_ECC_RF_INT . #define YCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_RF_INT_K2_SHIFT 0 #define YCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_0_RF_INT_K2 (0x1<<3) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM022_I_ECC_0_RF_INT . @@ -73413,16 +77797,16 @@ #define YCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_SHIFT 15 #define YCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2 (0x1<<16) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT 16 - #define YCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2 (0x1<<20) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2_SHIFT 20 - #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB (0x1<<20) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_SHIFT 20 - #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2 (0x1<<22) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_SHIFT 22 + #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB (0x1<<19) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_SHIFT 19 + #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2 (0x1<<21) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT 21 #define YCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB (0x1<<24) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT 24 #define YCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2 (0x1<<25) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT 25 + #define YCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2 (0x1<<26) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2_SHIFT 26 #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB (0x1<<27) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 . #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB_SHIFT 27 #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_K2 (0x1<<28) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 . @@ -73451,54 +77835,52 @@ #define YCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_SHIFT 21 #define YCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB (0x1<<30) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_SHIFT 30 -#define YCM_REG_PRTY_MASK_H_1 0x1080214UL //Access:RW DataWidth:0x9 // Multi Field Register. - #define YCM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_E5_SHIFT 0 - #define YCM_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_E5_SHIFT 1 - #define YCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_0_E5 (0x1<<2) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY_0 . - #define YCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_0_E5_SHIFT 2 - #define YCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_1_E5 (0x1<<3) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY_1 . - #define YCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_1_E5_SHIFT 3 +#define YCM_REG_PRTY_MASK_H_1 0x1080214UL //Access:RW DataWidth:0x8 // Multi Field Register. + #define YCM_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_E5_SHIFT 0 + #define YCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_0_E5 (0x1<<1) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY_0 . + #define YCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_0_E5_SHIFT 1 + #define YCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_1_E5 (0x1<<2) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY_1 . + #define YCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_1_E5_SHIFT 2 #define YCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2 (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2_SHIFT 0 - #define YCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5_SHIFT 4 + #define YCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5_SHIFT 3 #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_SHIFT 0 #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2 (0x1<<1) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2_SHIFT 1 - #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_E5_SHIFT 5 - #define YCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_E5_SHIFT 6 + #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_E5_SHIFT 4 + #define YCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_E5_SHIFT 5 #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB (0x1<<1) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_SHIFT 1 #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2 (0x1<<2) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_SHIFT 2 - #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5_SHIFT 7 + #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5_SHIFT 6 #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB (0x1<<2) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_SHIFT 2 #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2 (0x1<<3) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_SHIFT 3 - #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . - #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5_SHIFT 8 + #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . + #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5_SHIFT 7 #define YCM_REG_MEM005_RF_ECC_ERROR_CONNECT_0 0x1080220UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: ycm.i_agg_task_ctx_0_1.rf_ecc_error_connect_0 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define YCM_REG_MEM005_RF_ECC_ERROR_CONNECT_1 0x1080224UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: ycm.i_agg_task_ctx_0_1.rf_ecc_error_connect_1 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define YCM_REG_MEM006_RF_ECC_ERROR_CONNECT_E5 0x1080228UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: ycm.i_agg_task_ctx_2.rf_ecc_error_connect Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define YCM_REG_MEM_ECC_ENABLE_0_BB_K2 0x1080228UL //Access:RW DataWidth:0xa // Multi Field Register. #define YCM_REG_MEM_ECC_ENABLE_0_E5 0x108022cUL //Access:RW DataWidth:0xa // Multi Field Register. - #define YCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram - #define YCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_EN_E5_SHIFT 0 + #define YCM_REG_MEM_ECC_ENABLE_0_MEM031_I_ECC_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram + #define YCM_REG_MEM_ECC_ENABLE_0_MEM031_I_ECC_EN_E5_SHIFT 0 #define YCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN (0x1<<1) // Enable ECC for memory ecc instance ycm.i_agg_con_ctx.i_ecc_0 in module ycm_mem_agg_con_ctx #define YCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN_SHIFT 1 #define YCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN (0x1<<2) // Enable ECC for memory ecc instance ycm.i_agg_con_ctx.i_ecc_1 in module ycm_mem_agg_con_ctx #define YCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN_SHIFT 2 - #define YCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_0_EN_E5 (0x1<<3) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx.i_ecc_0 in module ycm_mem_sm_con_ctx - #define YCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_0_EN_E5_SHIFT 3 - #define YCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_1_EN_E5 (0x1<<4) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx.i_ecc_1 in module ycm_mem_sm_con_ctx - #define YCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_1_EN_E5_SHIFT 4 + #define YCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_0_EN_E5 (0x1<<3) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx.i_ecc_0 in module ycm_mem_sm_con_ctx + #define YCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_0_EN_E5_SHIFT 3 + #define YCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_1_EN_E5 (0x1<<4) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx.i_ecc_1 in module ycm_mem_sm_con_ctx + #define YCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_1_EN_E5_SHIFT 4 #define YCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2 (0x1<<6) // Enable ECC for memory ecc instance ycm.i_agg_task_ctx.i_ecc_0 in module ycm_mem_agg_task_ctx #define YCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_BB_K2_SHIFT 6 #define YCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_E5 (0x1<<5) // Enable ECC for memory ecc instance ycm.i_agg_task_ctx_0_1.i_ecc_0 in module ycm_mem_agg_task_ctx_0_1 @@ -73509,10 +77891,10 @@ #define YCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_E5_SHIFT 6 #define YCM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_E5 (0x1<<7) // Enable ECC for memory ecc instance ycm.i_agg_task_ctx_2.i_ecc in module ycm_mem_agg_task_ctx_2 #define YCM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_E5_SHIFT 7 - #define YCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_0_EN_E5 (0x1<<8) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx - #define YCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_0_EN_E5_SHIFT 8 - #define YCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_1_EN_E5 (0x1<<9) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx - #define YCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_1_EN_E5_SHIFT 9 + #define YCM_REG_MEM_ECC_ENABLE_0_MEM029_I_ECC_0_EN_E5 (0x1<<8) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx + #define YCM_REG_MEM_ECC_ENABLE_0_MEM029_I_ECC_0_EN_E5_SHIFT 8 + #define YCM_REG_MEM_ECC_ENABLE_0_MEM029_I_ECC_1_EN_E5 (0x1<<9) // Enable ECC for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx + #define YCM_REG_MEM_ECC_ENABLE_0_MEM029_I_ECC_1_EN_E5_SHIFT 9 #define YCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_EN_K2 (0x1<<0) // Enable ECC for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram #define YCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_EN_K2_SHIFT 0 #define YCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_0_EN_K2 (0x1<<3) // Enable ECC for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_con_ctx_0_1 @@ -73539,16 +77921,16 @@ #define YCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_1_EN_BB_SHIFT 9 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_BB_K2 0x108022cUL //Access:RW DataWidth:0xa // Multi Field Register. #define YCM_REG_MEM_ECC_PARITY_ONLY_0_E5 0x1080230UL //Access:RW DataWidth:0xa // Multi Field Register. - #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram - #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_PRTY_E5_SHIFT 0 + #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM031_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram + #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM031_I_ECC_PRTY_E5_SHIFT 0 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY (0x1<<1) // Set parity only for memory ecc instance ycm.i_agg_con_ctx.i_ecc_0 in module ycm_mem_agg_con_ctx #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY_SHIFT 1 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY (0x1<<2) // Set parity only for memory ecc instance ycm.i_agg_con_ctx.i_ecc_1 in module ycm_mem_agg_con_ctx #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY_SHIFT 2 - #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_0_PRTY_E5 (0x1<<3) // Set parity only for memory ecc instance ycm.i_sm_con_ctx.i_ecc_0 in module ycm_mem_sm_con_ctx - #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_0_PRTY_E5_SHIFT 3 - #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_1_PRTY_E5 (0x1<<4) // Set parity only for memory ecc instance ycm.i_sm_con_ctx.i_ecc_1 in module ycm_mem_sm_con_ctx - #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_1_PRTY_E5_SHIFT 4 + #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_0_PRTY_E5 (0x1<<3) // Set parity only for memory ecc instance ycm.i_sm_con_ctx.i_ecc_0 in module ycm_mem_sm_con_ctx + #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_0_PRTY_E5_SHIFT 3 + #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_1_PRTY_E5 (0x1<<4) // Set parity only for memory ecc instance ycm.i_sm_con_ctx.i_ecc_1 in module ycm_mem_sm_con_ctx + #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_1_PRTY_E5_SHIFT 4 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2 (0x1<<6) // Set parity only for memory ecc instance ycm.i_agg_task_ctx.i_ecc_0 in module ycm_mem_agg_task_ctx #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_BB_K2_SHIFT 6 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_E5 (0x1<<5) // Set parity only for memory ecc instance ycm.i_agg_task_ctx_0_1.i_ecc_0 in module ycm_mem_agg_task_ctx_0_1 @@ -73559,10 +77941,10 @@ #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_E5_SHIFT 6 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_E5 (0x1<<7) // Set parity only for memory ecc instance ycm.i_agg_task_ctx_2.i_ecc in module ycm_mem_agg_task_ctx_2 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_E5_SHIFT 7 - #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_0_PRTY_E5 (0x1<<8) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx - #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_0_PRTY_E5_SHIFT 8 - #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_1_PRTY_E5 (0x1<<9) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx - #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_1_PRTY_E5_SHIFT 9 + #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM029_I_ECC_0_PRTY_E5 (0x1<<8) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx + #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM029_I_ECC_0_PRTY_E5_SHIFT 8 + #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM029_I_ECC_1_PRTY_E5 (0x1<<9) // Set parity only for memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx + #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM029_I_ECC_1_PRTY_E5_SHIFT 9 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_PRTY_K2 (0x1<<0) // Set parity only for memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_PRTY_K2_SHIFT 0 #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_0_PRTY_K2 (0x1<<3) // Set parity only for memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_con_ctx_0_1 @@ -73589,16 +77971,16 @@ #define YCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_1_PRTY_BB_SHIFT 9 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_BB_K2 0x1080230UL //Access:RC DataWidth:0xa // Multi Field Register. #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_E5 0x1080234UL //Access:RC DataWidth:0xa // Multi Field Register. - #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram - #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_CORRECT_E5_SHIFT 0 + #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM031_I_ECC_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram + #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM031_I_ECC_CORRECT_E5_SHIFT 0 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance ycm.i_agg_con_ctx.i_ecc_0 in module ycm_mem_agg_con_ctx #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT_SHIFT 1 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance ycm.i_agg_con_ctx.i_ecc_1 in module ycm_mem_agg_con_ctx #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT_SHIFT 2 - #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_0_CORRECT_E5 (0x1<<3) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx.i_ecc_0 in module ycm_mem_sm_con_ctx - #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_0_CORRECT_E5_SHIFT 3 - #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_1_CORRECT_E5 (0x1<<4) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx.i_ecc_1 in module ycm_mem_sm_con_ctx - #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_1_CORRECT_E5_SHIFT 4 + #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_0_CORRECT_E5 (0x1<<3) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx.i_ecc_0 in module ycm_mem_sm_con_ctx + #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_0_CORRECT_E5_SHIFT 3 + #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_1_CORRECT_E5 (0x1<<4) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx.i_ecc_1 in module ycm_mem_sm_con_ctx + #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_1_CORRECT_E5_SHIFT 4 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2 (0x1<<6) // Record if a correctable error occurred on memory ecc instance ycm.i_agg_task_ctx.i_ecc_0 in module ycm_mem_agg_task_ctx #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_BB_K2_SHIFT 6 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_E5 (0x1<<5) // Record if a correctable error occurred on memory ecc instance ycm.i_agg_task_ctx_0_1.i_ecc_0 in module ycm_mem_agg_task_ctx_0_1 @@ -73609,10 +77991,10 @@ #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_E5_SHIFT 6 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_E5 (0x1<<7) // Record if a correctable error occurred on memory ecc instance ycm.i_agg_task_ctx_2.i_ecc in module ycm_mem_agg_task_ctx_2 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_E5_SHIFT 7 - #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_0_CORRECT_E5 (0x1<<8) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx - #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_0_CORRECT_E5_SHIFT 8 - #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_1_CORRECT_E5 (0x1<<9) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx - #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_1_CORRECT_E5_SHIFT 9 + #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM029_I_ECC_0_CORRECT_E5 (0x1<<8) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_0 in module ycm_mem_sm_task_ctx + #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM029_I_ECC_0_CORRECT_E5_SHIFT 8 + #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM029_I_ECC_1_CORRECT_E5 (0x1<<9) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_task_ctx.i_ecc_1 in module ycm_mem_sm_task_ctx + #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM029_I_ECC_1_CORRECT_E5_SHIFT 9 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_CORRECT_K2 (0x1<<0) // Record if a correctable error occurred on memory ecc instance ycm.i_xx_msg_ram.i_ecc in module ycm_mem_xx_msg_ram #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_CORRECT_K2_SHIFT 0 #define YCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_0_CORRECT_K2 (0x1<<3) // Record if a correctable error occurred on memory ecc instance ycm.i_sm_con_ctx_0_1.i_ecc_0 in module ycm_mem_sm_con_ctx_0_1 @@ -73724,7 +78106,7 @@ #define YCM_REG_PBF_FRWRD_MODE_BB_K2 0x1080660UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward. #define YCM_REG_SDM_ERR_HANDLE_EN 0x1080664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message. #define YCM_REG_DIR_BYP_EN 0x1080668UL //Access:RW DataWidth:0x1 // Direct bypass enable. -#define YCM_REG_FI_DESC_INPUT_VIOLATE 0x108066cUL //Access:R DataWidth:0x13 // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0 then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation: Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS; [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: XxBypass message in PCM block; [15] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [16] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [17]- Violation: Connection domain AggCtxLdStFlg==0 then AffinityType != 2; [18]- Violation: single Task domain AggCtxLdStFlg==0 then AffinityType != 3; +#define YCM_REG_FI_DESC_INPUT_VIOLATE 0x108066cUL //Access:R DataWidth:0x13 // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0 then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation: Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS; [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: Agg Store message then Loader done with error; [15] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [16] - Violation: Direct message: Task domain doesn't exist then AffinityType != 3; [17]- Violation: Connection domain AggCtxLdStFlg==0 then AffinityType != 2; [18]- Violation: single Task domain AggCtxLdStFlg==0 then AffinityType != 3; #define YCM_REG_SE_DESC_INPUT_VIOLATE 0x1080670UL //Access:R DataWidth:0xd // Input message second descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0 then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation: Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0; [12]- Violation: dual Task domain AggCtxLdStFlg==0 then AffinityType != 3;Read only register. #define YCM_REG_IA_AGG_CON_PART_FILL_LVL 0x1080674UL //Access:R DataWidth:0x3 // Input Arbiter Aggregation Connection part FIFO fill level (in messages). #define YCM_REG_IA_SM_CON_PART_FILL_LVL 0x1080678UL //Access:R DataWidth:0x3 // Input Arbiter Storm Connection part FIFO fill level (in messages). @@ -73733,7 +78115,7 @@ #define YCM_REG_IA_TRANS_PART_FILL_LVL 0x1080684UL //Access:R DataWidth:0x3 // Input Arbiter Transparent part FIFO fill level (in messages). #define YCM_REG_EXT_RD_FILL_LVL_E5 0x1080688UL //Access:R DataWidth:0x2 // External read buffer FIFO fill level (in FIFO entries). #define YCM_REG_XX_MSG_UP_BND 0x1080704UL //Access:RW DataWidth:0x7 // The maximum number of Xx RAM messages; which may be stored in XX protection. Is restricted by Xx Messages RAM size and the size of Xx protected message CM_REGISTERS_XX_MSG_SIZE.XX_MSG_SIZE -#define YCM_REG_XX_MSG_SIZE 0x1080708UL //Access:RW DataWidth:0x5 // The size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to 4 and multiplied by CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND should not exceed XxMessagesRam size which is: MCM: 0d1792 PCM: 0d176 TCM: 0d1536 UCM: 0d1792 XCM: 0d256 YCM: 0d1536 +#define YCM_REG_XX_MSG_SIZE 0x1080708UL //Access:RW DataWidth:0x6 // The size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to 4 and multiplied by CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND should not exceed XxMessagesRam size which is: MCM: 0d1792 PCM: 0d176 TCM: 0d1536 UCM: 0d1792 XCM: 0d256 YCM: 0d1536 #define YCM_REG_XX_LCID_CAM_UP_BND 0x108070cUL //Access:RW DataWidth:0x7 // The maximum number of connections in the XX protection LCID CAM. #define YCM_REG_XX_FREE_CNT 0x1080710UL //Access:R DataWidth:0x7 // Used to read the XX protection Free counter. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND #define YCM_REG_XX_LCID_CAM_FILL_LVL 0x1080714UL //Access:R DataWidth:0x7 // Used to read XX protection LCID CAM fill level. Fill level is calculated as the number of locked LCIDs, i.e. LCIDs that have at least one Xx locked message or LCIDs that have no Xx locked messages but haven't been unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM. @@ -73760,9 +78142,9 @@ #define YCM_REG_XX_TBYP_TBL_ST_STAT 0x1080768UL //Access:RC DataWidth:0x7 // Xx Task Bypass Table sticky status. Reset on read. #define YCM_REG_XX_TBYP_TBL_UP_BND 0x108076cUL //Access:RW DataWidth:0x7 // Xx Bypass Table (Task) maximum fill level. #define YCM_REG_XX_BYP_LOCK_MSG_THR 0x1080790UL //Access:RW DataWidth:0x6 // Xx Bypass messages lock threshold. The number of locked messages per LCID is above this threshold is one of conditions to start XxBypass for this LCID. -#define YCM_REG_XX_PREF_DIR_FILL_LVL 0x1080794UL //Access:R DataWidth:0x5 // Xx LCID Arbiter direct prefetch FIFO fill level (in entries). -#define YCM_REG_XX_PREF_AGGST_FILL_LVL 0x1080798UL //Access:R DataWidth:0x5 // Xx LCID Arbiter aggregation store prefetch FIFO fill level (in entries). -#define YCM_REG_XX_PREF_BYP_FILL_LVL 0x108079cUL //Access:R DataWidth:0x5 // Xx LCID Arbiter bypass prefetch FIFO fill level (in entries). +#define YCM_REG_XX_PREF_DIR_FILL_LVL 0x1080794UL //Access:R DataWidth:0x6 // Xx LCID Arbiter direct prefetch FIFO fill level (in entries). +#define YCM_REG_XX_PREF_AGGST_FILL_LVL 0x1080798UL //Access:R DataWidth:0x6 // Xx LCID Arbiter aggregation store prefetch FIFO fill level (in entries). +#define YCM_REG_XX_PREF_BYP_FILL_LVL 0x108079cUL //Access:R DataWidth:0x6 // Xx LCID Arbiter bypass prefetch FIFO fill level (in entries). #define YCM_REG_UNLOCK_MISS 0x10807a0UL //Access:RC DataWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM. #define YCM_REG_ERR_AFFINITY_TYPE_E5 0x10807a4UL //Access:RW DataWidth:0x2 // Affinity type in case of input message error. #define YCM_REG_ERR_EXCLUSIVE_FLG_E5 0x10807a8UL //Access:RW DataWidth:0x1 // Exclusive type in case of input message error. @@ -73851,14 +78233,14 @@ #define YCM_REG_AGG_TASK_RULE6_Q_BB_K2 0x1080954UL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). #define YCM_REG_AGG_TASK_RULE6_Q_E5 0x108095cUL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). #define YCM_REG_AGG_TASK_RULE7_Q_E5 0x1080960UL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). -#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_0_E5 0x1080964UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_1_E5 0x1080968UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_2_E5 0x108096cUL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_3_E5 0x1080970UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_4_E5 0x1080974UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_5_E5 0x1080978UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_6_E5 0x108097cUL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_7_E5 0x1080980UL //Access:RW DataWidth:0x3 // EventID bit width per task type. +#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_0_E5 0x1080964UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_1_E5 0x1080968UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_2_E5 0x108096cUL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_3_E5 0x1080970UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_4_E5 0x1080974UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_5_E5 0x1080978UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_6_E5 0x108097cUL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define YCM_REG_CM_TASK_EVENT_ID_BWIDTH_7_E5 0x1080980UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. #define YCM_REG_IN_PRCS_TBL_CRD_AGG 0x1080a04UL //Access:RW DataWidth:0x4 // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.IN_PRCS_TBL_CRD_AGGST need be no more than In-process table size=12. #define YCM_REG_IN_PRCS_TBL_CRD_AGGST 0x1080a08UL //Access:RW DataWidth:0x4 // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGG.IN_PRCS_TBL_CRD_AGG need be no more than In-process table size=12. #define YCM_REG_IN_PRCS_TBL_FILL_LVL 0x1080a0cUL //Access:R DataWidth:0x4 // In-process Table fill level (in messages). @@ -73870,28 +78252,28 @@ #define YCM_REG_CMPL_DIR_CURR_ST 0x1080a24UL //Access:R DataWidth:0x4 // Direct Completer FSM current state. #define YCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG 0x1080a28UL //Access:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM output Event ID. #define YCM_REG_XX_BYP_TASK_STATE_EVNT_ID_FLG 0x1080a2cUL //Access:RW DataWidth:0x1 // If set, Xx task bypass state will be added in calculation of CM output Event ID. -#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_0_E5 0x1080a30UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_1_E5 0x1080a34UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_2_E5 0x1080a38UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_3_E5 0x1080a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_4_E5 0x1080a40UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_5_E5 0x1080a44UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_6_E5 0x1080a48UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_7_E5 0x1080a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_8_E5 0x1080a50UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_9_E5 0x1080a54UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_10_E5 0x1080a58UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_11_E5 0x1080a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_12_E5 0x1080a60UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_13_E5 0x1080a64UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_14_E5 0x1080a68UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_15_E5 0x1080a6cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. +#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_0_E5 0x1080a30UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_1_E5 0x1080a34UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_2_E5 0x1080a38UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_3_E5 0x1080a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_4_E5 0x1080a40UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_5_E5 0x1080a44UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_6_E5 0x1080a48UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_7_E5 0x1080a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_8_E5 0x1080a50UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_9_E5 0x1080a54UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_10_E5 0x1080a58UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_11_E5 0x1080a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_12_E5 0x1080a60UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_13_E5 0x1080a64UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_14_E5 0x1080a68UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define YCM_REG_CM_CON_EVENT_ID_BWIDTH_15_E5 0x1080a6cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. #define YCM_REG_CCFC_INIT_CRD 0x1080a84UL //Access:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. #define YCM_REG_TCFC_INIT_CRD 0x1080a88UL //Access:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. #define YCM_REG_QM_INIT_CRD0 0x1080a8cUL //Access:RW DataWidth:0x5 // QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter. #define YCM_REG_TCFC_INCLOCK_INIT_CRD 0x1080a90UL //Access:RW DataWidth:0x1 // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the initial credit value; read returns the current value of the credit counter. #define YCM_REG_TCFC_DEC_INIT_CRD 0x1080a94UL //Access:RW DataWidth:0x3 // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the initial credit value; read returns the current value of the credit counter. -#define YCM_REG_FIC_INIT_CRD 0x1080a98UL //Access:RW DataWidth:0x6 // FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up. +#define YCM_REG_FIC_INIT_CRD 0x1080a98UL //Access:RW DataWidth:0x5 // FIC output initial credit in REGQ pairs. Write writes the initial credit value; read returns the current value of the credit counter. #define YCM_REG_DIR_BYP_MSG_CNT 0x1080aa4UL //Access:RC DataWidth:0x20 // Counter of direct bypassed messages. #define YCM_REG_YSDM_LENGTH_MIS 0x1080aacUL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at YSDM interface. #define YCM_REG_PBF_LENGTH_MIS 0x1080ab0UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PBF interface. @@ -73953,7 +78335,7 @@ #define YCM_REG_XX_TBL 0x1081b00UL //Access:R DataWidth:0x18 // Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:12]; Next pointer: PCM - [11:10]; M/T/U/X/YCM - [23:18]; #define YCM_REG_XX_TBL_SIZE_BB_K2 22 #define YCM_REG_XX_TBL_SIZE_E5 64 -#define YCM_REG_XX_DSCR_TBL 0x1081c00UL //Access:RW DataWidth:0x1e // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek. +#define YCM_REG_XX_DSCR_TBL 0x1081c00UL //Access:RW DataWidth:0x1f // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[14:9]); Next pointer (MCM [20:15]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [20:15]); LTID (MCM [29:21]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [29:21]). Task Domain Exist (MCM [30]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [30]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek. #define YCM_REG_XX_DSCR_TBL_SIZE 64 #define YCM_REG_N_SM_CON_CTX_LD_0_BB_K2 0x1080814UL //Access:RW DataWidth:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8). #define YCM_REG_N_SM_CON_CTX_LD_0_E5 0x1081d00UL //Access:RW DataWidth:0x4 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8). @@ -74152,8 +78534,10 @@ #define YCM_REG_AGG_TASK_CF1_Q_E5 0x1082c04UL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). #define YCM_REG_AGG_TASK_CF3_Q_E5 0x1082c08UL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). #define YCM_REG_AGG_TASK_CF4_Q_E5 0x1082c0cUL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). -#define YCM_REG_XX_MSG_RAM 0x1088000UL //Access:R DataWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only. -#define YCM_REG_XX_MSG_RAM_SIZE 6240 +#define YCM_REG_XX_MSG_RAM_BB_K2 0x1088000UL //Access:R DataWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only. +#define YCM_REG_XX_MSG_RAM_E5 0x1090000UL //Access:R DataWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only. +#define YCM_REG_XX_MSG_RAM_SIZE_BB_K2 6240 +#define YCM_REG_XX_MSG_RAM_SIZE_E5 11264 #define PCM_REG_INIT 0x1100000UL //Access:RW DataWidth:0x1 // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0. #define PCM_REG_DBG_SELECT 0x1100040UL //Access:RW DataWidth:0x8 // DBMUX register for selecting a line to output #define PCM_REG_DBG_DWORD_ENABLE 0x1100044UL //Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line) in the selected line (before shift).for selecting a line to output @@ -74464,104 +78848,104 @@ #define PCM_REG_INT_STS_CLR_2 0x11001acUL //Access:RC DataWidth:0x1 // Multi Field Register. #define PCM_REG_INT_STS_CLR_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations. #define PCM_REG_INT_STS_CLR_2_QMREG_MORE4_SHIFT 0 -#define PCM_REG_PRTY_MASK_H_0 0x1100204UL //Access:RW DataWidth:0x11 // Multi Field Register. - #define PCM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT . - #define PCM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_E5_SHIFT 0 - #define PCM_REG_PRTY_MASK_H_0_MEM012_I_ECC_0_RF_INT_E5 (0x1<<1) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM012_I_ECC_0_RF_INT . - #define PCM_REG_PRTY_MASK_H_0_MEM012_I_ECC_0_RF_INT_E5_SHIFT 1 - #define PCM_REG_PRTY_MASK_H_0_MEM012_I_ECC_1_RF_INT_E5 (0x1<<2) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM012_I_ECC_1_RF_INT . - #define PCM_REG_PRTY_MASK_H_0_MEM012_I_ECC_1_RF_INT_E5_SHIFT 2 +#define PCM_REG_PRTY_MASK_H_0 0x1100204UL //Access:RW DataWidth:0x10 // Multi Field Register. + #define PCM_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT . + #define PCM_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_E5_SHIFT 0 + #define PCM_REG_PRTY_MASK_H_0_MEM011_I_ECC_0_RF_INT_E5 (0x1<<1) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM011_I_ECC_0_RF_INT . + #define PCM_REG_PRTY_MASK_H_0_MEM011_I_ECC_0_RF_INT_E5_SHIFT 1 + #define PCM_REG_PRTY_MASK_H_0_MEM011_I_ECC_1_RF_INT_E5 (0x1<<2) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM011_I_ECC_1_RF_INT . + #define PCM_REG_PRTY_MASK_H_0_MEM011_I_ECC_1_RF_INT_E5_SHIFT 2 #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB (0x1<<3) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_SHIFT 3 #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2 (0x1<<4) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_SHIFT 4 #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5_SHIFT 3 - #define PCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2 (0x1<<3) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT 3 - #define PCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_E5_SHIFT 4 #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB (0x1<<4) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_SHIFT 4 - #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_E5 (0x1<<5) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_E5_SHIFT 5 + #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2 (0x1<<5) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT 5 + #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_E5_SHIFT 4 + #define PCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2 (0x1<<3) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT 3 + #define PCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_E5_SHIFT 5 #define PCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2 (0x1<<13) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . #define PCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_SHIFT 13 #define PCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . #define PCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_E5_SHIFT 6 - #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB (0x1<<9) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_SHIFT 9 - #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_E5_SHIFT 7 #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB (0x1<<5) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_SHIFT 5 #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2 (0x1<<6) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_SHIFT 6 - #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5_SHIFT 8 + #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_E5_SHIFT 7 #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB (0x1<<6) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_SHIFT 6 #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2 (0x1<<7) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_SHIFT 7 - #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_E5_SHIFT 9 + #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_E5_SHIFT 8 #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB (0x1<<7) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_SHIFT 7 #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2 (0x1<<8) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT 8 - #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5_SHIFT 10 + #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5_SHIFT 9 #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB (0x1<<8) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_SHIFT 8 #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2 (0x1<<9) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_SHIFT 9 - #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5_SHIFT 11 - #define PCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5_SHIFT 12 - #define PCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5_SHIFT 13 - #define PCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2 (0x1<<11) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT 11 - #define PCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5_SHIFT 14 - #define PCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2 (0x1<<12) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT 12 - #define PCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5_SHIFT 15 + #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5_SHIFT 10 + #define PCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5_SHIFT 11 + #define PCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2 (0x1<<10) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT 10 + #define PCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5_SHIFT 12 + #define PCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5_SHIFT 13 + #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB (0x1<<9) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_SHIFT 9 + #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_E5_SHIFT 14 #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB (0x1<<10) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY . #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_SHIFT 10 #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2 (0x1<<14) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY . #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_SHIFT 14 - #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5_SHIFT 16 + #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_E5_SHIFT 15 #define PCM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_K2 (0x1<<0) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT . #define PCM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_K2_SHIFT 0 #define PCM_REG_PRTY_MASK_H_0_MEM010_I_ECC_0_RF_INT_K2 (0x1<<1) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_ECC_0_RF_INT . #define PCM_REG_PRTY_MASK_H_0_MEM010_I_ECC_0_RF_INT_K2_SHIFT 1 #define PCM_REG_PRTY_MASK_H_0_MEM010_I_ECC_1_RF_INT_K2 (0x1<<2) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_ECC_1_RF_INT . #define PCM_REG_PRTY_MASK_H_0_MEM010_I_ECC_1_RF_INT_K2_SHIFT 2 - #define PCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2 (0x1<<10) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . - #define PCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT 10 + #define PCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2 (0x1<<11) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT 11 + #define PCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2 (0x1<<12) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY . + #define PCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT 12 #define PCM_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_BB (0x1<<0) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT . #define PCM_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_BB_SHIFT 0 #define PCM_REG_PRTY_MASK_H_0_MEM009_I_ECC_0_RF_INT_BB (0x1<<1) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM009_I_ECC_0_RF_INT . #define PCM_REG_PRTY_MASK_H_0_MEM009_I_ECC_0_RF_INT_BB_SHIFT 1 #define PCM_REG_PRTY_MASK_H_0_MEM009_I_ECC_1_RF_INT_BB (0x1<<2) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM009_I_ECC_1_RF_INT . #define PCM_REG_PRTY_MASK_H_0_MEM009_I_ECC_1_RF_INT_BB_SHIFT 2 -#define PCM_REG_MEM012_RF_ECC_ERROR_CONNECT_0_E5 0x1100210UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: pcm.i_sm_con_ctx.rf_ecc_error_connect_0 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PCM_REG_MEM011_RF_ECC_ERROR_CONNECT_0_E5 0x1100210UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: pcm.i_sm_con_ctx.rf_ecc_error_connect_0 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define PCM_REG_MEM010_RF_ECC_ERROR_CONNECT_0_K2 0x1100210UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: pcm.i_sm_con_ctx.rf_ecc_error_connect_0 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define PCM_REG_MEM009_RF_ECC_ERROR_CONNECT_0_BB 0x1100210UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: pcm.i_sm_con_ctx.rf_ecc_error_connect_0 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define PCM_REG_MEM012_RF_ECC_ERROR_CONNECT_1_E5 0x1100214UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: pcm.i_sm_con_ctx.rf_ecc_error_connect_1 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define PCM_REG_MEM011_RF_ECC_ERROR_CONNECT_1_E5 0x1100214UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: pcm.i_sm_con_ctx.rf_ecc_error_connect_1 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define PCM_REG_MEM010_RF_ECC_ERROR_CONNECT_1_K2 0x1100214UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: pcm.i_sm_con_ctx.rf_ecc_error_connect_1 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define PCM_REG_MEM009_RF_ECC_ERROR_CONNECT_1_BB 0x1100214UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: pcm.i_sm_con_ctx.rf_ecc_error_connect_1 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define PCM_REG_MEM_ECC_ENABLE_0 0x1100218UL //Access:RW DataWidth:0x3 // Multi Field Register. - #define PCM_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram - #define PCM_REG_MEM_ECC_ENABLE_0_MEM014_I_ECC_EN_E5_SHIFT 0 - #define PCM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_0_EN_E5 (0x1<<1) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx - #define PCM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_0_EN_E5_SHIFT 1 - #define PCM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_1_EN_E5 (0x1<<2) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx - #define PCM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_1_EN_E5_SHIFT 2 + #define PCM_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram + #define PCM_REG_MEM_ECC_ENABLE_0_MEM013_I_ECC_EN_E5_SHIFT 0 + #define PCM_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_0_EN_E5 (0x1<<1) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx + #define PCM_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_0_EN_E5_SHIFT 1 + #define PCM_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_1_EN_E5 (0x1<<2) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx + #define PCM_REG_MEM_ECC_ENABLE_0_MEM011_I_ECC_1_EN_E5_SHIFT 2 #define PCM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_K2 (0x1<<0) // Enable ECC for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram #define PCM_REG_MEM_ECC_ENABLE_0_MEM012_I_ECC_EN_K2_SHIFT 0 #define PCM_REG_MEM_ECC_ENABLE_0_MEM010_I_ECC_0_EN_K2 (0x1<<1) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx @@ -74575,12 +78959,12 @@ #define PCM_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_1_EN_BB (0x1<<2) // Enable ECC for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx #define PCM_REG_MEM_ECC_ENABLE_0_MEM009_I_ECC_1_EN_BB_SHIFT 2 #define PCM_REG_MEM_ECC_PARITY_ONLY_0 0x110021cUL //Access:RW DataWidth:0x3 // Multi Field Register. - #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram - #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM014_I_ECC_PRTY_E5_SHIFT 0 - #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_0_PRTY_E5 (0x1<<1) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx - #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_0_PRTY_E5_SHIFT 1 - #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_1_PRTY_E5 (0x1<<2) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx - #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_1_PRTY_E5_SHIFT 2 + #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram + #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM013_I_ECC_PRTY_E5_SHIFT 0 + #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_0_PRTY_E5 (0x1<<1) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx + #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_0_PRTY_E5_SHIFT 1 + #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_1_PRTY_E5 (0x1<<2) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx + #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM011_I_ECC_1_PRTY_E5_SHIFT 2 #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_K2 (0x1<<0) // Set parity only for memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM012_I_ECC_PRTY_K2_SHIFT 0 #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM010_I_ECC_0_PRTY_K2 (0x1<<1) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx @@ -74594,12 +78978,12 @@ #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_1_PRTY_BB (0x1<<2) // Set parity only for memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx #define PCM_REG_MEM_ECC_PARITY_ONLY_0_MEM009_I_ECC_1_PRTY_BB_SHIFT 2 #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0 0x1100220UL //Access:RC DataWidth:0x3 // Multi Field Register. - #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram - #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM014_I_ECC_CORRECT_E5_SHIFT 0 - #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_0_CORRECT_E5 (0x1<<1) // Record if a correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx - #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_0_CORRECT_E5_SHIFT 1 - #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_1_CORRECT_E5 (0x1<<2) // Record if a correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx - #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_1_CORRECT_E5_SHIFT 2 + #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram + #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM013_I_ECC_CORRECT_E5_SHIFT 0 + #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_0_CORRECT_E5 (0x1<<1) // Record if a correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx + #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_0_CORRECT_E5_SHIFT 1 + #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_1_CORRECT_E5 (0x1<<2) // Record if a correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_1 in module pcm_mem_sm_con_ctx + #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM011_I_ECC_1_CORRECT_E5_SHIFT 2 #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_K2 (0x1<<0) // Record if a correctable error occurred on memory ecc instance pcm.i_xx_msg_ram.i_ecc in module pcm_mem_xx_msg_ram #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM012_I_ECC_CORRECT_K2_SHIFT 0 #define PCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM010_I_ECC_0_CORRECT_K2 (0x1<<1) // Record if a correctable error occurred on memory ecc instance pcm.i_sm_con_ctx.i_ecc_0 in module pcm_mem_sm_con_ctx @@ -74630,7 +79014,7 @@ #define PCM_REG_PBF_FRWRD_MODE_BB_K2 0x1100638UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward. #define PCM_REG_SDM_ERR_HANDLE_EN 0x110063cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message. #define PCM_REG_DIR_BYP_EN 0x1100640UL //Access:RW DataWidth:0x1 // Direct bypass enable. -#define PCM_REG_FI_DESC_INPUT_VIOLATE 0x1100644UL //Access:R DataWidth:0x13 // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0 then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation: Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS; [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: XxBypass message in PCM block; [15] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [16] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [17]- Violation: Connection domain AggCtxLdStFlg==0 then AffinityType != 2; [18]- Violation: single Task domain AggCtxLdStFlg==0 then AffinityType != 3; +#define PCM_REG_FI_DESC_INPUT_VIOLATE 0x1100644UL //Access:R DataWidth:0x13 // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0 then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation: Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS; [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: Agg Store message then Loader done with error; [15] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [16] - Violation: Direct message: Task domain doesn't exist then AffinityType != 3; [17]- Violation: Connection domain AggCtxLdStFlg==0 then AffinityType != 2; [18]- Violation: single Task domain AggCtxLdStFlg==0 then AffinityType != 3; #define PCM_REG_IA_SM_CON_PART_FILL_LVL 0x1100648UL //Access:R DataWidth:0x3 // Input Arbiter Storm Connection part FIFO fill level (in messages). #define PCM_REG_IA_TRANS_PART_FILL_LVL 0x110064cUL //Access:R DataWidth:0x3 // Input Arbiter Transparent part FIFO fill level (in messages). #define PCM_REG_EXT_RD_FILL_LVL_E5 0x1100650UL //Access:R DataWidth:0x2 // External read buffer FIFO fill level (in FIFO entries). @@ -74676,7 +79060,7 @@ #define PCM_REG_CMPL_DIR_CURR_ST 0x1100a18UL //Access:R DataWidth:0x4 // Direct Completer FSM current state. #define PCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG 0x1100a1cUL //Access:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM output Event ID. #define PCM_REG_CCFC_INIT_CRD 0x1100a84UL //Access:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. -#define PCM_REG_FIC_INIT_CRD 0x1100a88UL //Access:RW DataWidth:0x6 // FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up. +#define PCM_REG_FIC_INIT_CRD 0x1100a88UL //Access:RW DataWidth:0x5 // FIC output initial credit in REGQ pairs. Write writes the initial credit value; read returns the current value of the credit counter. #define PCM_REG_DIR_BYP_MSG_CNT 0x1100aa4UL //Access:RC DataWidth:0x20 // Counter of direct bypassed messages. #define PCM_REG_PBF_LENGTH_MIS_BB_K2 0x1100aacUL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PBF interface. #define PCM_REG_GRC_BUF_EMPTY 0x1100ab0UL //Access:R DataWidth:0x1 // Input Stage GRC buffer is empty. @@ -74702,7 +79086,7 @@ #define PCM_REG_XX_LCID_CAM_SIZE 2 #define PCM_REG_XX_TBL 0x1101600UL //Access:R DataWidth:0xc // Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:12]; Next pointer: PCM - [11:10]; M/T/U/X/YCM - [23:18]; #define PCM_REG_XX_TBL_SIZE 2 -#define PCM_REG_XX_DSCR_TBL 0x1101700UL //Access:RW DataWidth:0x11 // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek. +#define PCM_REG_XX_DSCR_TBL 0x1101700UL //Access:RW DataWidth:0x11 // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[14:9]); Next pointer (MCM [20:15]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [20:15]); LTID (MCM [29:21]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [29:21]). Task Domain Exist (MCM [30]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [30]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek. #define PCM_REG_XX_DSCR_TBL_SIZE 4 #define PCM_REG_N_SM_CON_CTX_LD_0_BB_K2 0x1100808UL //Access:RW DataWidth:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8). #define PCM_REG_N_SM_CON_CTX_LD_0_E5 0x1101710UL //Access:RW DataWidth:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8). @@ -75260,122 +79644,120 @@ #define TCM_REG_INT_STS_CLR_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations. #define TCM_REG_INT_STS_CLR_2_QMREG_MORE4_SHIFT 0 #define TCM_REG_PRTY_MASK_H_0 0x1180204UL //Access:RW DataWidth:0x1f // Multi Field Register. - #define TCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM033_I_ECC_RF_INT . - #define TCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT_E5_SHIFT 0 + #define TCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM032_I_ECC_RF_INT . + #define TCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_RF_INT_E5_SHIFT 0 #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT . #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_SHIFT 1 #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT . #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_SHIFT 2 #define TCM_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_E5 (0x1<<3) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT . #define TCM_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_E5_SHIFT 3 - #define TCM_REG_PRTY_MASK_H_0_MEM029_I_ECC_0_RF_INT_E5 (0x1<<4) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM029_I_ECC_0_RF_INT . - #define TCM_REG_PRTY_MASK_H_0_MEM029_I_ECC_0_RF_INT_E5_SHIFT 4 - #define TCM_REG_PRTY_MASK_H_0_MEM029_I_ECC_1_RF_INT_E5 (0x1<<5) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM029_I_ECC_1_RF_INT . - #define TCM_REG_PRTY_MASK_H_0_MEM029_I_ECC_1_RF_INT_E5_SHIFT 5 + #define TCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_0_RF_INT_E5 (0x1<<4) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM028_I_ECC_0_RF_INT . + #define TCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_0_RF_INT_E5_SHIFT 4 + #define TCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_1_RF_INT_E5 (0x1<<5) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM028_I_ECC_1_RF_INT . + #define TCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_1_RF_INT_E5_SHIFT 5 #define TCM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_E5 (0x1<<6) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM006_I_ECC_0_RF_INT . #define TCM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_E5_SHIFT 6 #define TCM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_E5 (0x1<<7) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM006_I_ECC_1_RF_INT . #define TCM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_E5_SHIFT 7 - #define TCM_REG_PRTY_MASK_H_0_MEM031_I_ECC_0_RF_INT_E5 (0x1<<8) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM031_I_ECC_0_RF_INT . - #define TCM_REG_PRTY_MASK_H_0_MEM031_I_ECC_0_RF_INT_E5_SHIFT 8 - #define TCM_REG_PRTY_MASK_H_0_MEM031_I_ECC_1_RF_INT_E5 (0x1<<9) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM031_I_ECC_1_RF_INT . - #define TCM_REG_PRTY_MASK_H_0_MEM031_I_ECC_1_RF_INT_E5_SHIFT 9 + #define TCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_0_RF_INT_E5 (0x1<<8) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM030_I_ECC_0_RF_INT . + #define TCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_0_RF_INT_E5_SHIFT 8 + #define TCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_1_RF_INT_E5 (0x1<<9) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM030_I_ECC_1_RF_INT . + #define TCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_1_RF_INT_E5_SHIFT 9 #define TCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB (0x1<<25) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_SHIFT 25 #define TCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5_SHIFT 10 - #define TCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2 (0x1<<26) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2_SHIFT 26 - #define TCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5_SHIFT 11 #define TCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB (0x1<<23) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_SHIFT 23 - #define TCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5_SHIFT 12 + #define TCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5_SHIFT 11 #define TCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2 (0x1<<24) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT 24 - #define TCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5_SHIFT 13 - #define TCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB (0x1<<21) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_SHIFT 21 - #define TCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5_SHIFT 14 + #define TCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5_SHIFT 12 + #define TCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2 (0x1<<26) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2_SHIFT 26 + #define TCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5_SHIFT 13 #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB (0x1<<12) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_SHIFT 12 #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2 (0x1<<13) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT 13 - #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5_SHIFT 15 + #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5_SHIFT 14 #define TCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2 (0x1<<9) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2_SHIFT 9 - #define TCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5_SHIFT 16 + #define TCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5_SHIFT 15 #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB (0x1<<26) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_SHIFT 26 #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2 (0x1<<15) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT 15 - #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5_SHIFT 17 + #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5_SHIFT 16 #define TCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2 (0x1<<27) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT 27 - #define TCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5_SHIFT 18 + #define TCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5_SHIFT 17 #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB (0x1<<15) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_SHIFT 15 #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2 (0x1<<16) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT 16 - #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5_SHIFT 19 - #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB (0x1<<20) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_SHIFT 20 - #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2 (0x1<<22) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2_SHIFT 22 - #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_E5_SHIFT 20 + #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_E5_SHIFT 18 + #define TCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB (0x1<<21) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_SHIFT 21 + #define TCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5_SHIFT 19 #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB (0x1<<11) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_SHIFT 11 #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2 (0x1<<12) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT 12 - #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5_SHIFT 21 + #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5_SHIFT 20 #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB (0x1<<14) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_SHIFT 14 #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2 (0x1<<10) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT 10 - #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5_SHIFT 22 + #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5_SHIFT 21 #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB (0x1<<16) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_SHIFT 16 #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2 (0x1<<17) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2_SHIFT 17 - #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5_SHIFT 23 + #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5_SHIFT 22 #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB (0x1<<17) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_SHIFT 17 #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2 (0x1<<18) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT 18 - #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5_SHIFT 24 + #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5_SHIFT 23 #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB (0x1<<18) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_SHIFT 18 #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2 (0x1<<19) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT 19 - #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5_SHIFT 25 + #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5_SHIFT 24 #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB (0x1<<10) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_SHIFT 10 #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2 (0x1<<11) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT 11 - #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5_SHIFT 26 - #define TCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_E5_SHIFT 27 - #define TCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_E5_SHIFT 28 - #define TCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5_SHIFT 29 - #define TCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5_SHIFT 30 + #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5_SHIFT 25 + #define TCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_E5_SHIFT 26 + #define TCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5_SHIFT 27 + #define TCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_E5_SHIFT 28 + #define TCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_E5_SHIFT 29 + #define TCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2 (0x1<<20) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT 20 + #define TCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_E5_SHIFT 30 #define TCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_K2 (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT . #define TCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_K2_SHIFT 0 #define TCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_0_RF_INT_K2 (0x1<<3) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM022_I_ECC_0_RF_INT . @@ -75394,12 +79776,14 @@ #define TCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_SHIFT 13 #define TCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2 (0x1<<14) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_SHIFT 14 - #define TCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2 (0x1<<20) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT 20 #define TCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB (0x1<<19) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_SHIFT 19 #define TCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2 (0x1<<21) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_SHIFT 21 + #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB (0x1<<20) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_SHIFT 20 + #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2 (0x1<<22) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2_SHIFT 22 #define TCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB (0x1<<22) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_SHIFT 22 #define TCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2 (0x1<<23) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . @@ -75432,58 +79816,56 @@ #define TCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT_BB_SHIFT 8 #define TCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB (0x1<<30) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_SHIFT 30 -#define TCM_REG_PRTY_MASK_H_1 0x1180214UL //Access:RW DataWidth:0xa // Multi Field Register. - #define TCM_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM030_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_E5_SHIFT 0 - #define TCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_E5_SHIFT 1 - #define TCM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_E5_SHIFT 2 - #define TCM_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_E5_SHIFT 3 - #define TCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_0_E5 (0x1<<4) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY_0 . - #define TCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_0_E5_SHIFT 4 - #define TCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_1_E5 (0x1<<5) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY_1 . - #define TCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_1_E5_SHIFT 5 +#define TCM_REG_PRTY_MASK_H_1 0x1180214UL //Access:RW DataWidth:0x9 // Multi Field Register. + #define TCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_E5_SHIFT 0 + #define TCM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_E5_SHIFT 1 + #define TCM_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_E5_SHIFT 2 + #define TCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_0_E5 (0x1<<3) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY_0 . + #define TCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_0_E5_SHIFT 3 + #define TCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_1_E5 (0x1<<4) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY_1 . + #define TCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_1_E5_SHIFT 4 #define TCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2 (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2_SHIFT 0 - #define TCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5_SHIFT 6 - #define TCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_E5_SHIFT 7 + #define TCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5_SHIFT 5 + #define TCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_E5_SHIFT 6 #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_SHIFT 0 #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2 (0x1<<1) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_SHIFT 1 - #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5_SHIFT 8 + #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5_SHIFT 7 #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB (0x1<<1) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_SHIFT 1 #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2 (0x1<<2) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_SHIFT 2 - #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . - #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5_SHIFT 9 + #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . + #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5_SHIFT 8 #define TCM_REG_MEM_ECC_ENABLE_0 0x1180220UL //Access:RW DataWidth:0xa // Multi Field Register. - #define TCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram - #define TCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_EN_E5_SHIFT 0 + #define TCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram + #define TCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_EN_E5_SHIFT 0 #define TCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN (0x1<<1) // Enable ECC for memory ecc instance tcm.i_agg_con_ctx_0_3.i_ecc_0 in module tcm_mem_agg_con_ctx_0_3 #define TCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_0_EN_SHIFT 1 #define TCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN (0x1<<2) // Enable ECC for memory ecc instance tcm.i_agg_con_ctx_0_3.i_ecc_1 in module tcm_mem_agg_con_ctx_0_3 #define TCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_1_EN_SHIFT 2 #define TCM_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_E5 (0x1<<3) // Enable ECC for memory ecc instance tcm.i_agg_con_ctx_4.i_ecc in module tcm_mem_agg_con_ctx_4 #define TCM_REG_MEM_ECC_ENABLE_0_MEM004_I_ECC_EN_E5_SHIFT 3 - #define TCM_REG_MEM_ECC_ENABLE_0_MEM029_I_ECC_0_EN_E5 (0x1<<4) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx - #define TCM_REG_MEM_ECC_ENABLE_0_MEM029_I_ECC_0_EN_E5_SHIFT 4 - #define TCM_REG_MEM_ECC_ENABLE_0_MEM029_I_ECC_1_EN_E5 (0x1<<5) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx - #define TCM_REG_MEM_ECC_ENABLE_0_MEM029_I_ECC_1_EN_E5_SHIFT 5 + #define TCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_0_EN_E5 (0x1<<4) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx + #define TCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_0_EN_E5_SHIFT 4 + #define TCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_1_EN_E5 (0x1<<5) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx + #define TCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_1_EN_E5_SHIFT 5 #define TCM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN_E5 (0x1<<6) // Enable ECC for memory ecc instance tcm.i_agg_task_ctx.i_ecc_0 in module tcm_mem_agg_task_ctx #define TCM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_0_EN_E5_SHIFT 6 #define TCM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_E5 (0x1<<7) // Enable ECC for memory ecc instance tcm.i_agg_task_ctx.i_ecc_1 in module tcm_mem_agg_task_ctx #define TCM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_1_EN_E5_SHIFT 7 - #define TCM_REG_MEM_ECC_ENABLE_0_MEM031_I_ECC_0_EN_E5 (0x1<<8) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx - #define TCM_REG_MEM_ECC_ENABLE_0_MEM031_I_ECC_0_EN_E5_SHIFT 8 - #define TCM_REG_MEM_ECC_ENABLE_0_MEM031_I_ECC_1_EN_E5 (0x1<<9) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx - #define TCM_REG_MEM_ECC_ENABLE_0_MEM031_I_ECC_1_EN_E5_SHIFT 9 + #define TCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_0_EN_E5 (0x1<<8) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx + #define TCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_0_EN_E5_SHIFT 8 + #define TCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_1_EN_E5 (0x1<<9) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx + #define TCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_1_EN_E5_SHIFT 9 #define TCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_K2 (0x1<<0) // Enable ECC for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram #define TCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_K2_SHIFT 0 #define TCM_REG_MEM_ECC_ENABLE_0_MEM022_I_ECC_0_EN_K2 (0x1<<3) // Enable ECC for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx @@ -75509,26 +79891,26 @@ #define TCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_1_EN_BB (0x1<<8) // Enable ECC for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx #define TCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_1_EN_BB_SHIFT 8 #define TCM_REG_MEM_ECC_PARITY_ONLY_0 0x1180224UL //Access:RW DataWidth:0xa // Multi Field Register. - #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram - #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_PRTY_E5_SHIFT 0 + #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram + #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_PRTY_E5_SHIFT 0 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY (0x1<<1) // Set parity only for memory ecc instance tcm.i_agg_con_ctx_0_3.i_ecc_0 in module tcm_mem_agg_con_ctx_0_3 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_0_PRTY_SHIFT 1 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY (0x1<<2) // Set parity only for memory ecc instance tcm.i_agg_con_ctx_0_3.i_ecc_1 in module tcm_mem_agg_con_ctx_0_3 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_1_PRTY_SHIFT 2 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for memory ecc instance tcm.i_agg_con_ctx_4.i_ecc in module tcm_mem_agg_con_ctx_4 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM004_I_ECC_PRTY_E5_SHIFT 3 - #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM029_I_ECC_0_PRTY_E5 (0x1<<4) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx - #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM029_I_ECC_0_PRTY_E5_SHIFT 4 - #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM029_I_ECC_1_PRTY_E5 (0x1<<5) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx - #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM029_I_ECC_1_PRTY_E5_SHIFT 5 + #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_0_PRTY_E5 (0x1<<4) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx + #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_0_PRTY_E5_SHIFT 4 + #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_1_PRTY_E5 (0x1<<5) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx + #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_1_PRTY_E5_SHIFT 5 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY_E5 (0x1<<6) // Set parity only for memory ecc instance tcm.i_agg_task_ctx.i_ecc_0 in module tcm_mem_agg_task_ctx #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_0_PRTY_E5_SHIFT 6 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_E5 (0x1<<7) // Set parity only for memory ecc instance tcm.i_agg_task_ctx.i_ecc_1 in module tcm_mem_agg_task_ctx #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_1_PRTY_E5_SHIFT 7 - #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM031_I_ECC_0_PRTY_E5 (0x1<<8) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx - #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM031_I_ECC_0_PRTY_E5_SHIFT 8 - #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM031_I_ECC_1_PRTY_E5 (0x1<<9) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx - #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM031_I_ECC_1_PRTY_E5_SHIFT 9 + #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_0_PRTY_E5 (0x1<<8) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx + #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_0_PRTY_E5_SHIFT 8 + #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_1_PRTY_E5 (0x1<<9) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx + #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_1_PRTY_E5_SHIFT 9 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_K2 (0x1<<0) // Set parity only for memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_K2_SHIFT 0 #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM022_I_ECC_0_PRTY_K2 (0x1<<3) // Set parity only for memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx @@ -75554,26 +79936,26 @@ #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_1_PRTY_BB (0x1<<8) // Set parity only for memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx #define TCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_1_PRTY_BB_SHIFT 8 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0 0x1180228UL //Access:RC DataWidth:0xa // Multi Field Register. - #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram - #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_CORRECT_E5_SHIFT 0 + #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram + #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_CORRECT_E5_SHIFT 0 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance tcm.i_agg_con_ctx_0_3.i_ecc_0 in module tcm_mem_agg_con_ctx_0_3 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_0_CORRECT_SHIFT 1 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance tcm.i_agg_con_ctx_0_3.i_ecc_1 in module tcm_mem_agg_con_ctx_0_3 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_1_CORRECT_SHIFT 2 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_E5 (0x1<<3) // Record if a correctable error occurred on memory ecc instance tcm.i_agg_con_ctx_4.i_ecc in module tcm_mem_agg_con_ctx_4 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM004_I_ECC_CORRECT_E5_SHIFT 3 - #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM029_I_ECC_0_CORRECT_E5 (0x1<<4) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx - #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM029_I_ECC_0_CORRECT_E5_SHIFT 4 - #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM029_I_ECC_1_CORRECT_E5 (0x1<<5) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx - #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM029_I_ECC_1_CORRECT_E5_SHIFT 5 + #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_0_CORRECT_E5 (0x1<<4) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx + #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_0_CORRECT_E5_SHIFT 4 + #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_1_CORRECT_E5 (0x1<<5) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_1 in module tcm_mem_sm_con_ctx + #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_1_CORRECT_E5_SHIFT 5 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT_E5 (0x1<<6) // Record if a correctable error occurred on memory ecc instance tcm.i_agg_task_ctx.i_ecc_0 in module tcm_mem_agg_task_ctx #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_0_CORRECT_E5_SHIFT 6 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_E5 (0x1<<7) // Record if a correctable error occurred on memory ecc instance tcm.i_agg_task_ctx.i_ecc_1 in module tcm_mem_agg_task_ctx #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_1_CORRECT_E5_SHIFT 7 - #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM031_I_ECC_0_CORRECT_E5 (0x1<<8) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx - #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM031_I_ECC_0_CORRECT_E5_SHIFT 8 - #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM031_I_ECC_1_CORRECT_E5 (0x1<<9) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx - #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM031_I_ECC_1_CORRECT_E5_SHIFT 9 + #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_0_CORRECT_E5 (0x1<<8) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_0 in module tcm_mem_sm_task_ctx + #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_0_CORRECT_E5_SHIFT 8 + #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_1_CORRECT_E5 (0x1<<9) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_task_ctx.i_ecc_1 in module tcm_mem_sm_task_ctx + #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_1_CORRECT_E5_SHIFT 9 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT_K2 (0x1<<0) // Record if a correctable error occurred on memory ecc instance tcm.i_xx_msg_ram.i_ecc in module tcm_mem_xx_msg_ram #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_CORRECT_K2_SHIFT 0 #define TCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM022_I_ECC_0_CORRECT_K2 (0x1<<3) // Record if a correctable error occurred on memory ecc instance tcm.i_sm_con_ctx.i_ecc_0 in module tcm_mem_sm_con_ctx @@ -75685,7 +80067,7 @@ #define TCM_REG_PBF_FRWRD_MODE_BB_K2 0x1180660UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward. #define TCM_REG_SDM_ERR_HANDLE_EN 0x1180664UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message. #define TCM_REG_DIR_BYP_EN 0x1180668UL //Access:RW DataWidth:0x1 // Direct bypass enable. -#define TCM_REG_FI_DESC_INPUT_VIOLATE 0x118066cUL //Access:R DataWidth:0x13 // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0 then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation: Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS; [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: XxBypass message in PCM block; [15] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [16] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [17]- Violation: Connection domain AggCtxLdStFlg==0 then AffinityType != 2; [18]- Violation: single Task domain AggCtxLdStFlg==0 then AffinityType != 3; +#define TCM_REG_FI_DESC_INPUT_VIOLATE 0x118066cUL //Access:R DataWidth:0x13 // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0 then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation: Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS; [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: Agg Store message then Loader done with error; [15] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [16] - Violation: Direct message: Task domain doesn't exist then AffinityType != 3; [17]- Violation: Connection domain AggCtxLdStFlg==0 then AffinityType != 2; [18]- Violation: single Task domain AggCtxLdStFlg==0 then AffinityType != 3; #define TCM_REG_SE_DESC_INPUT_VIOLATE 0x1180670UL //Access:R DataWidth:0xd // Input message second descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0 then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation: Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0; [12]- Violation: dual Task domain AggCtxLdStFlg==0 then AffinityType != 3;Read only register. #define TCM_REG_IA_AGG_CON_PART_FILL_LVL 0x1180674UL //Access:R DataWidth:0x3 // Input Arbiter Aggregation Connection part FIFO fill level (in messages). #define TCM_REG_IA_SM_CON_PART_FILL_LVL 0x1180678UL //Access:R DataWidth:0x3 // Input Arbiter Storm Connection part FIFO fill level (in messages). @@ -75803,14 +80185,14 @@ #define TCM_REG_AGG_TASK_RULE3_Q 0x1180990UL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). #define TCM_REG_AGG_TASK_RULE4_Q 0x1180994UL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). #define TCM_REG_AGG_TASK_RULE5_Q 0x1180998UL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). -#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_0_E5 0x118099cUL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_1_E5 0x11809a0UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_2_E5 0x11809a4UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_3_E5 0x11809a8UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_4_E5 0x11809acUL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_5_E5 0x11809b0UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_6_E5 0x11809b4UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_7_E5 0x11809b8UL //Access:RW DataWidth:0x3 // EventID bit width per task type. +#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_0_E5 0x118099cUL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_1_E5 0x11809a0UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_2_E5 0x11809a4UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_3_E5 0x11809a8UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_4_E5 0x11809acUL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_5_E5 0x11809b0UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_6_E5 0x11809b4UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define TCM_REG_CM_TASK_EVENT_ID_BWIDTH_7_E5 0x11809b8UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. #define TCM_REG_IN_PRCS_TBL_CRD_AGG 0x1180a04UL //Access:RW DataWidth:0x4 // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.IN_PRCS_TBL_CRD_AGGST need be no more than In-process table size=12. #define TCM_REG_IN_PRCS_TBL_CRD_AGGST 0x1180a08UL //Access:RW DataWidth:0x4 // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGG.IN_PRCS_TBL_CRD_AGG need be no more than In-process table size=12. #define TCM_REG_IN_PRCS_TBL_FILL_LVL 0x1180a0cUL //Access:R DataWidth:0x4 // In-process Table fill level (in messages). @@ -75824,27 +80206,27 @@ #define TCM_REG_CMPL_DIR_CURR_ST 0x1180a2cUL //Access:R DataWidth:0x4 // Direct Completer FSM current state. #define TCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG 0x1180a30UL //Access:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM output Event ID. #define TCM_REG_XX_BYP_TASK_STATE_EVNT_ID_FLG 0x1180a34UL //Access:RW DataWidth:0x1 // If set, Xx task bypass state will be added in calculation of CM output Event ID. -#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_0_E5 0x1180a38UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_1_E5 0x1180a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_2_E5 0x1180a40UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_3_E5 0x1180a44UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_4_E5 0x1180a48UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_5_E5 0x1180a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_6_E5 0x1180a50UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_7_E5 0x1180a54UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_8_E5 0x1180a58UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_9_E5 0x1180a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_10_E5 0x1180a60UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_11_E5 0x1180a64UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_12_E5 0x1180a68UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_13_E5 0x1180a6cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_14_E5 0x1180a70UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_15_E5 0x1180a74UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. +#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_0_E5 0x1180a38UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_1_E5 0x1180a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_2_E5 0x1180a40UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_3_E5 0x1180a44UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_4_E5 0x1180a48UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_5_E5 0x1180a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_6_E5 0x1180a50UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_7_E5 0x1180a54UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_8_E5 0x1180a58UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_9_E5 0x1180a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_10_E5 0x1180a60UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_11_E5 0x1180a64UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_12_E5 0x1180a68UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_13_E5 0x1180a6cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_14_E5 0x1180a70UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define TCM_REG_CM_CON_EVENT_ID_BWIDTH_15_E5 0x1180a74UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. #define TCM_REG_CCFC_INIT_CRD 0x1180a84UL //Access:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. #define TCM_REG_TCFC_INIT_CRD 0x1180a88UL //Access:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. #define TCM_REG_QM_INIT_CRD0 0x1180a8cUL //Access:RW DataWidth:0x5 // QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter. #define TCM_REG_TM_INIT_CRD 0x1180a90UL //Access:RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. -#define TCM_REG_FIC_INIT_CRD 0x1180a94UL //Access:RW DataWidth:0x6 // FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up. +#define TCM_REG_FIC_INIT_CRD 0x1180a94UL //Access:RW DataWidth:0x5 // FIC output initial credit in REGQ pairs. Write writes the initial credit value; read returns the current value of the credit counter. #define TCM_REG_DIR_BYP_MSG_CNT 0x1180aa4UL //Access:RC DataWidth:0x20 // Counter of direct bypassed messages. #define TCM_REG_DORQ_LENGTH_MIS 0x1180aacUL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at the dorq interface. #define TCM_REG_PBF_LENGTH_MIS 0x1180ab0UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at PBF interface. @@ -75908,7 +80290,7 @@ #define TCM_REG_XX_TBL 0x1181700UL //Access:R DataWidth:0x18 // Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:12]; Next pointer: PCM - [11:10]; M/T/U/X/YCM - [23:18]; #define TCM_REG_XX_TBL_SIZE_BB_K2 32 #define TCM_REG_XX_TBL_SIZE_E5 64 -#define TCM_REG_XX_DSCR_TBL 0x1181800UL //Access:RW DataWidth:0x1e // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek. +#define TCM_REG_XX_DSCR_TBL 0x1181800UL //Access:RW DataWidth:0x1e // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[14:9]); Next pointer (MCM [20:15]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [20:15]); LTID (MCM [29:21]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [29:21]). Task Domain Exist (MCM [30]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [30]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek. #define TCM_REG_XX_DSCR_TBL_SIZE 64 #define TCM_REG_TM_CON_EVNT_ID_0_BB_K2 0x1180524UL //Access:RW DataWidth:0x8 // TM connection Event ID per connection type. #define TCM_REG_TM_CON_EVNT_ID_0_E5 0x1181900UL //Access:RW DataWidth:0x8 // TM connection Event ID per connection type. @@ -76659,98 +81041,96 @@ #define MCM_REG_INT_STS_CLR_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations. #define MCM_REG_INT_STS_CLR_2_QMREG_MORE4_SHIFT 0 #define MCM_REG_PRTY_MASK_H_0 0x1200204UL //Access:RW DataWidth:0x1f // Multi Field Register. - #define MCM_REG_PRTY_MASK_H_0_MEM034_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM034_I_ECC_RF_INT . - #define MCM_REG_PRTY_MASK_H_0_MEM034_I_ECC_RF_INT_E5_SHIFT 0 + #define MCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM033_I_ECC_RF_INT . + #define MCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT_E5_SHIFT 0 #define MCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT . #define MCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_SHIFT 1 - #define MCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_0_RF_INT_E5 (0x1<<2) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM030_I_ECC_0_RF_INT . - #define MCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_0_RF_INT_E5_SHIFT 2 - #define MCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_1_RF_INT_E5 (0x1<<3) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM030_I_ECC_1_RF_INT . - #define MCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_1_RF_INT_E5_SHIFT 3 + #define MCM_REG_PRTY_MASK_H_0_MEM029_I_ECC_0_RF_INT_E5 (0x1<<2) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM029_I_ECC_0_RF_INT . + #define MCM_REG_PRTY_MASK_H_0_MEM029_I_ECC_0_RF_INT_E5_SHIFT 2 + #define MCM_REG_PRTY_MASK_H_0_MEM029_I_ECC_1_RF_INT_E5 (0x1<<3) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM029_I_ECC_1_RF_INT . + #define MCM_REG_PRTY_MASK_H_0_MEM029_I_ECC_1_RF_INT_E5_SHIFT 3 #define MCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT (0x1<<4) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT . #define MCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_SHIFT 4 #define MCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT (0x1<<5) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT . #define MCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_SHIFT 5 #define MCM_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_E5 (0x1<<6) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT . #define MCM_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_E5_SHIFT 6 - #define MCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_0_RF_INT_E5 (0x1<<7) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM032_I_ECC_0_RF_INT . - #define MCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_0_RF_INT_E5_SHIFT 7 - #define MCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_1_RF_INT_E5 (0x1<<8) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM032_I_ECC_1_RF_INT . - #define MCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_1_RF_INT_E5_SHIFT 8 + #define MCM_REG_PRTY_MASK_H_0_MEM031_I_ECC_0_RF_INT_E5 (0x1<<7) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM031_I_ECC_0_RF_INT . + #define MCM_REG_PRTY_MASK_H_0_MEM031_I_ECC_0_RF_INT_E5_SHIFT 7 + #define MCM_REG_PRTY_MASK_H_0_MEM031_I_ECC_1_RF_INT_E5 (0x1<<8) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM031_I_ECC_1_RF_INT . + #define MCM_REG_PRTY_MASK_H_0_MEM031_I_ECC_1_RF_INT_E5_SHIFT 8 #define MCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_K2 (0x1<<14) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_K2_SHIFT 14 #define MCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5_SHIFT 9 - #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_K2 (0x1<<27) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_K2_SHIFT 27 - #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5_SHIFT 10 - #define MCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_K2 (0x1<<10) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_K2_SHIFT 10 - #define MCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5_SHIFT 11 + #define MCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY (0x1<<10) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_SHIFT 10 #define MCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_K2 (0x1<<13) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_K2_SHIFT 13 - #define MCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5_SHIFT 12 - #define MCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5_SHIFT 13 + #define MCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5_SHIFT 11 + #define MCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5_SHIFT 12 #define MCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_K2 (0x1<<9) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_K2_SHIFT 9 - #define MCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5_SHIFT 14 + #define MCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5_SHIFT 13 #define MCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_K2 (0x1<<11) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_K2_SHIFT 11 - #define MCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5_SHIFT 15 + #define MCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5_SHIFT 14 + #define MCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5_SHIFT 15 #define MCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_K2 (0x1<<26) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_K2_SHIFT 26 #define MCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_E5_SHIFT 16 - #define MCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_E5_SHIFT 17 + #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_K2 (0x1<<27) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_K2_SHIFT 27 + #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5_SHIFT 17 #define MCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5_SHIFT 18 #define MCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_K2 (0x1<<24) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_K2_SHIFT 24 #define MCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5_SHIFT 19 - #define MCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5_SHIFT 20 #define MCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2 (0x1<<15) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2_SHIFT 15 - #define MCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5_SHIFT 21 + #define MCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5_SHIFT 20 #define MCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_K2 (0x1<<17) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_K2_SHIFT 17 - #define MCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5_SHIFT 22 + #define MCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_E5_SHIFT 21 #define MCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2 (0x1<<18) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2_SHIFT 18 - #define MCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5_SHIFT 23 + #define MCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5_SHIFT 22 #define MCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_K2 (0x1<<19) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_K2_SHIFT 19 - #define MCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5_SHIFT 24 + #define MCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5_SHIFT 23 #define MCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_K2 (0x1<<12) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_K2_SHIFT 12 - #define MCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5_SHIFT 25 - #define MCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_E5_SHIFT 26 - #define MCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_E5_SHIFT 27 - #define MCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_E5_SHIFT 28 + #define MCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5_SHIFT 24 + #define MCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_E5_SHIFT 25 + #define MCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_E5_SHIFT 26 + #define MCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_E5_SHIFT 27 #define MCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2 (0x1<<23) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_K2_SHIFT 23 - #define MCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5_SHIFT 29 - #define MCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2 (0x1<<20) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2_SHIFT 20 - #define MCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_E5_SHIFT 30 + #define MCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_E5_SHIFT 28 + #define MCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2 (0x1<<21) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2_SHIFT 21 + #define MCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_E5_SHIFT 29 + #define MCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5 (0x1<<30) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5_SHIFT 30 #define MCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM028_I_ECC_RF_INT . #define MCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_BB_K2_SHIFT 0 #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_0_RF_INT_BB_K2 (0x1<<2) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM023_I_ECC_0_RF_INT . @@ -76765,8 +81145,8 @@ #define MCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_BB_K2_SHIFT 8 #define MCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_K2 (0x1<<16) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_K2_SHIFT 16 - #define MCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2 (0x1<<21) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_K2_SHIFT 21 + #define MCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2 (0x1<<20) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2_SHIFT 20 #define MCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_K2 (0x1<<22) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_K2_SHIFT 22 #define MCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2 (0x1<<25) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . @@ -76777,58 +81157,56 @@ #define MCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB_K2_SHIFT 29 #define MCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2 (0x1<<30) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_K2_SHIFT 30 -#define MCM_REG_PRTY_MASK_H_1 0x1200214UL //Access:RW DataWidth:0xa // Multi Field Register. - #define MCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_E5_SHIFT 0 - #define MCM_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_E5_SHIFT 1 - #define MCM_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_E5_SHIFT 2 - #define MCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_0_E5 (0x1<<3) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY_0 . - #define MCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_0_E5_SHIFT 3 - #define MCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_1_E5 (0x1<<4) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY_1 . - #define MCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_1_E5_SHIFT 4 +#define MCM_REG_PRTY_MASK_H_1 0x1200214UL //Access:RW DataWidth:0x9 // Multi Field Register. + #define MCM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_E5_SHIFT 0 + #define MCM_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_E5_SHIFT 1 + #define MCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_0_E5 (0x1<<2) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY_0 . + #define MCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_0_E5_SHIFT 2 + #define MCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_1_E5 (0x1<<3) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY_1 . + #define MCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_1_E5_SHIFT 3 #define MCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_BB_K2_SHIFT 0 - #define MCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5_SHIFT 5 + #define MCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_E5_SHIFT 4 #define MCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_K2 (0x1<<1) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_K2_SHIFT 1 - #define MCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_E5_SHIFT 6 - #define MCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_E5_SHIFT 7 + #define MCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_E5_SHIFT 5 + #define MCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_E5 (0x1<<6) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_E5_SHIFT 6 #define MCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_K2 (0x1<<2) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_K2_SHIFT 2 - #define MCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5_SHIFT 8 + #define MCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5 (0x1<<7) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5_SHIFT 7 #define MCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_K2 (0x1<<3) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . #define MCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_K2_SHIFT 3 - #define MCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5 (0x1<<9) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . - #define MCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5_SHIFT 9 -#define MCM_REG_MEM030_RF_ECC_ERROR_CONNECT_0_E5 0x1200220UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: mcm.i_sm_con_ctx.rf_ecc_error_connect_0 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. + #define MCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5 (0x1<<8) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . + #define MCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5_SHIFT 8 +#define MCM_REG_MEM029_RF_ECC_ERROR_CONNECT_0_E5 0x1200220UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: mcm.i_sm_con_ctx.rf_ecc_error_connect_0 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define MCM_REG_MEM023_RF_ECC_ERROR_CONNECT_0_BB_K2 0x1200220UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: mcm.i_sm_con_ctx.rf_ecc_error_connect_0 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define MCM_REG_MEM030_RF_ECC_ERROR_CONNECT_1_E5 0x1200224UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: mcm.i_sm_con_ctx.rf_ecc_error_connect_1 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define MCM_REG_MEM029_RF_ECC_ERROR_CONNECT_1_E5 0x1200224UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: mcm.i_sm_con_ctx.rf_ecc_error_connect_1 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define MCM_REG_MEM023_RF_ECC_ERROR_CONNECT_1_BB_K2 0x1200224UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: mcm.i_sm_con_ctx.rf_ecc_error_connect_1 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define MCM_REG_MEM_ECC_ENABLE_0 0x1200228UL //Access:RW DataWidth:0x9 // Multi Field Register. - #define MCM_REG_MEM_ECC_ENABLE_0_MEM034_I_ECC_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_msg_ram - #define MCM_REG_MEM_ECC_ENABLE_0_MEM034_I_ECC_EN_E5_SHIFT 0 + #define MCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_msg_ram + #define MCM_REG_MEM_ECC_ENABLE_0_MEM033_I_ECC_EN_E5_SHIFT 0 #define MCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN (0x1<<1) // Enable ECC for memory ecc instance mcm.i_agg_con_ctx.i_ecc in module mcm_mem_agg_con_ctx #define MCM_REG_MEM_ECC_ENABLE_0_MEM003_I_ECC_EN_SHIFT 1 - #define MCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_0_EN_E5 (0x1<<2) // Enable ECC for memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_con_ctx - #define MCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_0_EN_E5_SHIFT 2 - #define MCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_1_EN_E5 (0x1<<3) // Enable ECC for memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_con_ctx - #define MCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_1_EN_E5_SHIFT 3 + #define MCM_REG_MEM_ECC_ENABLE_0_MEM029_I_ECC_0_EN_E5 (0x1<<2) // Enable ECC for memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_con_ctx + #define MCM_REG_MEM_ECC_ENABLE_0_MEM029_I_ECC_0_EN_E5_SHIFT 2 + #define MCM_REG_MEM_ECC_ENABLE_0_MEM029_I_ECC_1_EN_E5 (0x1<<3) // Enable ECC for memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_con_ctx + #define MCM_REG_MEM_ECC_ENABLE_0_MEM029_I_ECC_1_EN_E5_SHIFT 3 #define MCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN (0x1<<4) // Enable ECC for memory ecc instance mcm.i_agg_task_ctx_0_1.i_ecc_0 in module mcm_mem_agg_task_ctx_0_1 #define MCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_SHIFT 4 #define MCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN (0x1<<5) // Enable ECC for memory ecc instance mcm.i_agg_task_ctx_0_1.i_ecc_1 in module mcm_mem_agg_task_ctx_0_1 #define MCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_SHIFT 5 #define MCM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_E5 (0x1<<6) // Enable ECC for memory ecc instance mcm.i_agg_task_ctx_2.i_ecc in module mcm_mem_agg_task_ctx_2 #define MCM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_E5_SHIFT 6 - #define MCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_0_EN_E5 (0x1<<7) // Enable ECC for memory ecc instance mcm.i_sm_task_ctx.i_ecc_0 in module mcm_mem_sm_task_ctx - #define MCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_0_EN_E5_SHIFT 7 - #define MCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_1_EN_E5 (0x1<<8) // Enable ECC for memory ecc instance mcm.i_sm_task_ctx.i_ecc_1 in module mcm_mem_sm_task_ctx - #define MCM_REG_MEM_ECC_ENABLE_0_MEM032_I_ECC_1_EN_E5_SHIFT 8 + #define MCM_REG_MEM_ECC_ENABLE_0_MEM031_I_ECC_0_EN_E5 (0x1<<7) // Enable ECC for memory ecc instance mcm.i_sm_task_ctx.i_ecc_0 in module mcm_mem_sm_task_ctx + #define MCM_REG_MEM_ECC_ENABLE_0_MEM031_I_ECC_0_EN_E5_SHIFT 7 + #define MCM_REG_MEM_ECC_ENABLE_0_MEM031_I_ECC_1_EN_E5 (0x1<<8) // Enable ECC for memory ecc instance mcm.i_sm_task_ctx.i_ecc_1 in module mcm_mem_sm_task_ctx + #define MCM_REG_MEM_ECC_ENABLE_0_MEM031_I_ECC_1_EN_E5_SHIFT 8 #define MCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_EN_BB_K2 (0x1<<0) // Enable ECC for memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_msg_ram #define MCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_EN_BB_K2_SHIFT 0 #define MCM_REG_MEM_ECC_ENABLE_0_MEM023_I_ECC_0_EN_BB_K2 (0x1<<2) // Enable ECC for memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_con_ctx @@ -76842,24 +81220,24 @@ #define MCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_BB_K2 (0x1<<8) // Enable ECC for memory ecc instance mcm.i_sm_task_ctx_6.i_ecc in module mcm_mem_sm_task_ctx_6 #define MCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_EN_BB_K2_SHIFT 8 #define MCM_REG_MEM_ECC_PARITY_ONLY_0 0x120022cUL //Access:RW DataWidth:0x9 // Multi Field Register. - #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM034_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_msg_ram - #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM034_I_ECC_PRTY_E5_SHIFT 0 + #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_msg_ram + #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM033_I_ECC_PRTY_E5_SHIFT 0 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY (0x1<<1) // Set parity only for memory ecc instance mcm.i_agg_con_ctx.i_ecc in module mcm_mem_agg_con_ctx #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM003_I_ECC_PRTY_SHIFT 1 - #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_0_PRTY_E5 (0x1<<2) // Set parity only for memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_con_ctx - #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_0_PRTY_E5_SHIFT 2 - #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_1_PRTY_E5 (0x1<<3) // Set parity only for memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_con_ctx - #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_1_PRTY_E5_SHIFT 3 + #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM029_I_ECC_0_PRTY_E5 (0x1<<2) // Set parity only for memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_con_ctx + #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM029_I_ECC_0_PRTY_E5_SHIFT 2 + #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM029_I_ECC_1_PRTY_E5 (0x1<<3) // Set parity only for memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_con_ctx + #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM029_I_ECC_1_PRTY_E5_SHIFT 3 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY (0x1<<4) // Set parity only for memory ecc instance mcm.i_agg_task_ctx_0_1.i_ecc_0 in module mcm_mem_agg_task_ctx_0_1 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_SHIFT 4 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY (0x1<<5) // Set parity only for memory ecc instance mcm.i_agg_task_ctx_0_1.i_ecc_1 in module mcm_mem_agg_task_ctx_0_1 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_SHIFT 5 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_E5 (0x1<<6) // Set parity only for memory ecc instance mcm.i_agg_task_ctx_2.i_ecc in module mcm_mem_agg_task_ctx_2 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_E5_SHIFT 6 - #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_0_PRTY_E5 (0x1<<7) // Set parity only for memory ecc instance mcm.i_sm_task_ctx.i_ecc_0 in module mcm_mem_sm_task_ctx - #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_0_PRTY_E5_SHIFT 7 - #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_1_PRTY_E5 (0x1<<8) // Set parity only for memory ecc instance mcm.i_sm_task_ctx.i_ecc_1 in module mcm_mem_sm_task_ctx - #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM032_I_ECC_1_PRTY_E5_SHIFT 8 + #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM031_I_ECC_0_PRTY_E5 (0x1<<7) // Set parity only for memory ecc instance mcm.i_sm_task_ctx.i_ecc_0 in module mcm_mem_sm_task_ctx + #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM031_I_ECC_0_PRTY_E5_SHIFT 7 + #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM031_I_ECC_1_PRTY_E5 (0x1<<8) // Set parity only for memory ecc instance mcm.i_sm_task_ctx.i_ecc_1 in module mcm_mem_sm_task_ctx + #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM031_I_ECC_1_PRTY_E5_SHIFT 8 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_msg_ram #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_PRTY_BB_K2_SHIFT 0 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM023_I_ECC_0_PRTY_BB_K2 (0x1<<2) // Set parity only for memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_con_ctx @@ -76873,24 +81251,24 @@ #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_BB_K2 (0x1<<8) // Set parity only for memory ecc instance mcm.i_sm_task_ctx_6.i_ecc in module mcm_mem_sm_task_ctx_6 #define MCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_PRTY_BB_K2_SHIFT 8 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0 0x1200230UL //Access:RC DataWidth:0x9 // Multi Field Register. - #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM034_I_ECC_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_msg_ram - #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM034_I_ECC_CORRECT_E5_SHIFT 0 + #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_msg_ram + #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM033_I_ECC_CORRECT_E5_SHIFT 0 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance mcm.i_agg_con_ctx.i_ecc in module mcm_mem_agg_con_ctx #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM003_I_ECC_CORRECT_SHIFT 1 - #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_0_CORRECT_E5 (0x1<<2) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_con_ctx - #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_0_CORRECT_E5_SHIFT 2 - #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_1_CORRECT_E5 (0x1<<3) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_con_ctx - #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_1_CORRECT_E5_SHIFT 3 + #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM029_I_ECC_0_CORRECT_E5 (0x1<<2) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_con_ctx + #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM029_I_ECC_0_CORRECT_E5_SHIFT 2 + #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM029_I_ECC_1_CORRECT_E5 (0x1<<3) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_con_ctx.i_ecc_1 in module mcm_mem_sm_con_ctx + #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM029_I_ECC_1_CORRECT_E5_SHIFT 3 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT (0x1<<4) // Record if a correctable error occurred on memory ecc instance mcm.i_agg_task_ctx_0_1.i_ecc_0 in module mcm_mem_agg_task_ctx_0_1 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_SHIFT 4 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT (0x1<<5) // Record if a correctable error occurred on memory ecc instance mcm.i_agg_task_ctx_0_1.i_ecc_1 in module mcm_mem_agg_task_ctx_0_1 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_SHIFT 5 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_E5 (0x1<<6) // Record if a correctable error occurred on memory ecc instance mcm.i_agg_task_ctx_2.i_ecc in module mcm_mem_agg_task_ctx_2 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_E5_SHIFT 6 - #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_0_CORRECT_E5 (0x1<<7) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_task_ctx.i_ecc_0 in module mcm_mem_sm_task_ctx - #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_0_CORRECT_E5_SHIFT 7 - #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_1_CORRECT_E5 (0x1<<8) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_task_ctx.i_ecc_1 in module mcm_mem_sm_task_ctx - #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM032_I_ECC_1_CORRECT_E5_SHIFT 8 + #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM031_I_ECC_0_CORRECT_E5 (0x1<<7) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_task_ctx.i_ecc_0 in module mcm_mem_sm_task_ctx + #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM031_I_ECC_0_CORRECT_E5_SHIFT 7 + #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM031_I_ECC_1_CORRECT_E5 (0x1<<8) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_task_ctx.i_ecc_1 in module mcm_mem_sm_task_ctx + #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM031_I_ECC_1_CORRECT_E5_SHIFT 8 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_CORRECT_BB_K2 (0x1<<0) // Record if a correctable error occurred on memory ecc instance mcm.i_xx_msg_ram.i_ecc in module mcm_mem_xx_msg_ram #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_CORRECT_BB_K2_SHIFT 0 #define MCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM023_I_ECC_0_CORRECT_BB_K2 (0x1<<2) // Record if a correctable error occurred on memory ecc instance mcm.i_sm_con_ctx.i_ecc_0 in module mcm_mem_sm_con_ctx @@ -76990,7 +81368,7 @@ #define MCM_REG_PBF_FRWRD_MODE_BB_K2 0x1200668UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward. #define MCM_REG_SDM_ERR_HANDLE_EN 0x120066cUL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message. #define MCM_REG_DIR_BYP_EN 0x1200670UL //Access:RW DataWidth:0x1 // Direct bypass enable. -#define MCM_REG_FI_DESC_INPUT_VIOLATE 0x1200674UL //Access:R DataWidth:0x13 // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0 then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation: Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS; [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: XxBypass message in PCM block; [15] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [16] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [17]- Violation: Connection domain AggCtxLdStFlg==0 then AffinityType != 2; [18]- Violation: single Task domain AggCtxLdStFlg==0 then AffinityType != 3; +#define MCM_REG_FI_DESC_INPUT_VIOLATE 0x1200674UL //Access:R DataWidth:0x13 // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0 then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation: Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS; [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: Agg Store message then Loader done with error; [15] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [16] - Violation: Direct message: Task domain doesn't exist then AffinityType != 3; [17]- Violation: Connection domain AggCtxLdStFlg==0 then AffinityType != 2; [18]- Violation: single Task domain AggCtxLdStFlg==0 then AffinityType != 3; #define MCM_REG_SE_DESC_INPUT_VIOLATE 0x1200678UL //Access:R DataWidth:0xd // Input message second descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0 then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation: Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0; [12]- Violation: dual Task domain AggCtxLdStFlg==0 then AffinityType != 3;Read only register. #define MCM_REG_IA_AGG_CON_PART_FILL_LVL 0x120067cUL //Access:R DataWidth:0x3 // Input Arbiter Aggregation Connection part FIFO fill level (in messages). #define MCM_REG_IA_SM_CON_PART_FILL_LVL 0x1200680UL //Access:R DataWidth:0x3 // Input Arbiter Storm Connection part FIFO fill level (in messages). @@ -76999,7 +81377,7 @@ #define MCM_REG_IA_TRANS_PART_FILL_LVL 0x120068cUL //Access:R DataWidth:0x3 // Input Arbiter Transparent part FIFO fill level (in messages). #define MCM_REG_EXT_RD_FILL_LVL_E5 0x1200690UL //Access:R DataWidth:0x2 // External read buffer FIFO fill level (in FIFO entries). #define MCM_REG_XX_MSG_UP_BND 0x1200704UL //Access:RW DataWidth:0x7 // The maximum number of Xx RAM messages; which may be stored in XX protection. Is restricted by Xx Messages RAM size and the size of Xx protected message CM_REGISTERS_XX_MSG_SIZE.XX_MSG_SIZE -#define MCM_REG_XX_MSG_SIZE 0x1200708UL //Access:RW DataWidth:0x5 // The size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to 4 and multiplied by CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND should not exceed XxMessagesRam size which is: MCM: 0d1792 PCM: 0d176 TCM: 0d1536 UCM: 0d1792 XCM: 0d256 YCM: 0d1536 +#define MCM_REG_XX_MSG_SIZE 0x1200708UL //Access:RW DataWidth:0x6 // The size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to 4 and multiplied by CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND should not exceed XxMessagesRam size which is: MCM: 0d1792 PCM: 0d176 TCM: 0d1536 UCM: 0d1792 XCM: 0d256 YCM: 0d1536 #define MCM_REG_XX_LCID_CAM_UP_BND 0x120070cUL //Access:RW DataWidth:0x7 // The maximum number of connections in the XX protection LCID CAM. #define MCM_REG_XX_FREE_CNT 0x1200710UL //Access:R DataWidth:0x7 // Used to read the XX protection Free counter. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND #define MCM_REG_XX_LCID_CAM_FILL_LVL 0x1200714UL //Access:R DataWidth:0x7 // Used to read XX protection LCID CAM fill level. Fill level is calculated as the number of locked LCIDs, i.e. LCIDs that have at least one Xx locked message or LCIDs that have no Xx locked messages but haven't been unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM. @@ -77026,9 +81404,9 @@ #define MCM_REG_XX_TBYP_TBL_ST_STAT 0x1200768UL //Access:RC DataWidth:0x7 // Xx Task Bypass Table sticky status. Reset on read. #define MCM_REG_XX_TBYP_TBL_UP_BND 0x120076cUL //Access:RW DataWidth:0x7 // Xx Bypass Table (Task) maximum fill level. #define MCM_REG_XX_BYP_LOCK_MSG_THR 0x1200790UL //Access:RW DataWidth:0x6 // Xx Bypass messages lock threshold. The number of locked messages per LCID is above this threshold is one of conditions to start XxBypass for this LCID. -#define MCM_REG_XX_PREF_DIR_FILL_LVL 0x1200794UL //Access:R DataWidth:0x5 // Xx LCID Arbiter direct prefetch FIFO fill level (in entries). -#define MCM_REG_XX_PREF_AGGST_FILL_LVL 0x1200798UL //Access:R DataWidth:0x5 // Xx LCID Arbiter aggregation store prefetch FIFO fill level (in entries). -#define MCM_REG_XX_PREF_BYP_FILL_LVL 0x120079cUL //Access:R DataWidth:0x5 // Xx LCID Arbiter bypass prefetch FIFO fill level (in entries). +#define MCM_REG_XX_PREF_DIR_FILL_LVL 0x1200794UL //Access:R DataWidth:0x6 // Xx LCID Arbiter direct prefetch FIFO fill level (in entries). +#define MCM_REG_XX_PREF_AGGST_FILL_LVL 0x1200798UL //Access:R DataWidth:0x6 // Xx LCID Arbiter aggregation store prefetch FIFO fill level (in entries). +#define MCM_REG_XX_PREF_BYP_FILL_LVL 0x120079cUL //Access:R DataWidth:0x6 // Xx LCID Arbiter bypass prefetch FIFO fill level (in entries). #define MCM_REG_UNLOCK_MISS 0x12007a0UL //Access:RC DataWidth:0x1 // Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM. #define MCM_REG_ERR_AFFINITY_TYPE_E5 0x12007a4UL //Access:RW DataWidth:0x2 // Affinity type in case of input message error. #define MCM_REG_ERR_EXCLUSIVE_FLG_E5 0x12007a8UL //Access:RW DataWidth:0x1 // Exclusive type in case of input message error. @@ -77110,14 +81488,14 @@ #define MCM_REG_AGG_TASK_RULE5_Q 0x1200954UL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). #define MCM_REG_AGG_TASK_RULE6_Q 0x1200958UL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). #define MCM_REG_AGG_TASK_RULE7_Q_E5 0x120095cUL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). -#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_0_E5 0x1200960UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_1_E5 0x1200964UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_2_E5 0x1200968UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_3_E5 0x120096cUL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_4_E5 0x1200970UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_5_E5 0x1200974UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_6_E5 0x1200978UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_7_E5 0x120097cUL //Access:RW DataWidth:0x3 // EventID bit width per task type. +#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_0_E5 0x1200960UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_1_E5 0x1200964UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_2_E5 0x1200968UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_3_E5 0x120096cUL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_4_E5 0x1200970UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_5_E5 0x1200974UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_6_E5 0x1200978UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define MCM_REG_CM_TASK_EVENT_ID_BWIDTH_7_E5 0x120097cUL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. #define MCM_REG_IN_PRCS_TBL_CRD_AGG 0x1200a04UL //Access:RW DataWidth:0x4 // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.IN_PRCS_TBL_CRD_AGGST need be no more than In-process table size=12. #define MCM_REG_IN_PRCS_TBL_CRD_AGGST 0x1200a08UL //Access:RW DataWidth:0x4 // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGG.IN_PRCS_TBL_CRD_AGG need be no more than In-process table size=12. #define MCM_REG_IN_PRCS_TBL_FILL_LVL 0x1200a0cUL //Access:R DataWidth:0x4 // In-process Table fill level (in messages). @@ -77129,28 +81507,28 @@ #define MCM_REG_CMPL_DIR_CURR_ST 0x1200a24UL //Access:R DataWidth:0x4 // Direct Completer FSM current state. #define MCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG 0x1200a28UL //Access:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM output Event ID. #define MCM_REG_XX_BYP_TASK_STATE_EVNT_ID_FLG 0x1200a2cUL //Access:RW DataWidth:0x1 // If set, Xx task bypass state will be added in calculation of CM output Event ID. -#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_0_E5 0x1200a30UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_1_E5 0x1200a34UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_2_E5 0x1200a38UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_3_E5 0x1200a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_4_E5 0x1200a40UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_5_E5 0x1200a44UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_6_E5 0x1200a48UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_7_E5 0x1200a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_8_E5 0x1200a50UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_9_E5 0x1200a54UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_10_E5 0x1200a58UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_11_E5 0x1200a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_12_E5 0x1200a60UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_13_E5 0x1200a64UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_14_E5 0x1200a68UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_15_E5 0x1200a6cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. +#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_0_E5 0x1200a30UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_1_E5 0x1200a34UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_2_E5 0x1200a38UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_3_E5 0x1200a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_4_E5 0x1200a40UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_5_E5 0x1200a44UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_6_E5 0x1200a48UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_7_E5 0x1200a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_8_E5 0x1200a50UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_9_E5 0x1200a54UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_10_E5 0x1200a58UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_11_E5 0x1200a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_12_E5 0x1200a60UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_13_E5 0x1200a64UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_14_E5 0x1200a68UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define MCM_REG_CM_CON_EVENT_ID_BWIDTH_15_E5 0x1200a6cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. #define MCM_REG_CCFC_INIT_CRD 0x1200a84UL //Access:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. #define MCM_REG_TCFC_INIT_CRD 0x1200a88UL //Access:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. #define MCM_REG_QM_INIT_CRD0 0x1200a8cUL //Access:RW DataWidth:0x5 // QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter. #define MCM_REG_TCFC_INCLOCK_INIT_CRD 0x1200a90UL //Access:RW DataWidth:0x1 // TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the initial credit value; read returns the current value of the credit counter. #define MCM_REG_TCFC_DEC_INIT_CRD 0x1200a94UL //Access:RW DataWidth:0x3 // TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the initial credit value; read returns the current value of the credit counter. -#define MCM_REG_FIC_INIT_CRD 0x1200a98UL //Access:RW DataWidth:0x6 // FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up. +#define MCM_REG_FIC_INIT_CRD 0x1200a98UL //Access:RW DataWidth:0x5 // FIC output initial credit in REGQ pairs. Write writes the initial credit value; read returns the current value of the credit counter. #define MCM_REG_DIR_BYP_MSG_CNT 0x1200aa4UL //Access:RC DataWidth:0x20 // Counter of direct bypassed messages. #define MCM_REG_YSDM_LENGTH_MIS 0x1200aacUL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at YSDM interface. #define MCM_REG_USDM_LENGTH_MIS 0x1200ab0UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at USDM interface. @@ -77216,7 +81594,7 @@ #define MCM_REG_XX_TBL 0x1201b00UL //Access:R DataWidth:0x18 // Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:12]; Next pointer: PCM - [11:10]; M/T/U/X/YCM - [23:18]; #define MCM_REG_XX_TBL_SIZE_BB_K2 22 #define MCM_REG_XX_TBL_SIZE_E5 64 -#define MCM_REG_XX_DSCR_TBL 0x1201c00UL //Access:RW DataWidth:0x1e // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek. +#define MCM_REG_XX_DSCR_TBL 0x1201c00UL //Access:RW DataWidth:0x1f // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[14:9]); Next pointer (MCM [20:15]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [20:15]); LTID (MCM [29:21]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [29:21]). Task Domain Exist (MCM [30]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [30]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek. #define MCM_REG_XX_DSCR_TBL_SIZE 64 #define MCM_REG_N_SM_CON_CTX_LD_0_BB_K2 0x1200814UL //Access:RW DataWidth:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8). #define MCM_REG_N_SM_CON_CTX_LD_0_E5 0x1201d00UL //Access:RW DataWidth:0x5 // The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8). @@ -77437,9 +81815,10 @@ #define MCM_REG_AGG_TASK_CF2_Q_E5 0x1202e08UL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). #define MCM_REG_AGG_TASK_CF3_Q_E5 0x1202e0cUL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). #define MCM_REG_AGG_TASK_CF4_Q_E5 0x1202e10UL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). -#define MCM_REG_XX_MSG_RAM 0x1208000UL //Access:R DataWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only. +#define MCM_REG_XX_MSG_RAM_BB_K2 0x1208000UL //Access:R DataWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only. +#define MCM_REG_XX_MSG_RAM_E5 0x1210000UL //Access:R DataWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only. #define MCM_REG_XX_MSG_RAM_SIZE_BB_K2 6656 -#define MCM_REG_XX_MSG_RAM_SIZE_E5 7168 +#define MCM_REG_XX_MSG_RAM_SIZE_E5 9216 #define UCM_REG_INIT 0x1280000UL //Access:RW DataWidth:0x1 // Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0. #define UCM_REG_MEMCTRL_WR_RD_N_BB 0x1280040UL //Access:RW DataWidth:0x1 // wr/rd indication to CPU BIST #define UCM_REG_MEMCTRL_CMD_BB 0x1280044UL //Access:RW DataWidth:0x8 // command to CPU BIST @@ -78155,26 +82534,30 @@ #define UCM_REG_INT_STS_CLR_2_QMREG_MORE4 (0x1<<0) // More than 4 QM registrations. #define UCM_REG_INT_STS_CLR_2_QMREG_MORE4_SHIFT 0 #define UCM_REG_PRTY_MASK_H_0 0x1280204UL //Access:RW DataWidth:0x1f // Multi Field Register. - #define UCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_RF_INT (0x1<<0) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM030_I_ECC_RF_INT . - #define UCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_RF_INT_SHIFT 0 + #define UCM_REG_PRTY_MASK_H_0_MEM029_I_ECC_RF_INT_E5 (0x1<<0) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM029_I_ECC_RF_INT . + #define UCM_REG_PRTY_MASK_H_0_MEM029_I_ECC_RF_INT_E5_SHIFT 0 #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT (0x1<<1) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT . #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_SHIFT 1 #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT (0x1<<2) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT . #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_SHIFT 2 #define UCM_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_E5 (0x1<<3) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT . #define UCM_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_E5_SHIFT 3 - #define UCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_0_RF_INT_E5 (0x1<<4) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM026_I_ECC_0_RF_INT . - #define UCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_0_RF_INT_E5_SHIFT 4 - #define UCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_1_RF_INT_E5 (0x1<<5) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM026_I_ECC_1_RF_INT . - #define UCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_1_RF_INT_E5_SHIFT 5 + #define UCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_0_RF_INT_E5 (0x1<<4) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM025_I_ECC_0_RF_INT . + #define UCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_0_RF_INT_E5_SHIFT 4 + #define UCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_1_RF_INT_E5 (0x1<<5) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM025_I_ECC_1_RF_INT . + #define UCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_1_RF_INT_E5_SHIFT 5 #define UCM_REG_PRTY_MASK_H_0_MEM008_I_ECC_0_RF_INT_E5 (0x1<<6) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM008_I_ECC_0_RF_INT . #define UCM_REG_PRTY_MASK_H_0_MEM008_I_ECC_0_RF_INT_E5_SHIFT 6 #define UCM_REG_PRTY_MASK_H_0_MEM008_I_ECC_1_RF_INT_E5 (0x1<<7) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM008_I_ECC_1_RF_INT . #define UCM_REG_PRTY_MASK_H_0_MEM008_I_ECC_1_RF_INT_E5_SHIFT 7 - #define UCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_0_RF_INT_E5 (0x1<<8) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM028_I_ECC_0_RF_INT . - #define UCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_0_RF_INT_E5_SHIFT 8 - #define UCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_1_RF_INT_E5 (0x1<<9) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM028_I_ECC_1_RF_INT . - #define UCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_1_RF_INT_E5_SHIFT 9 + #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_0_RF_INT_BB_K2 (0x1<<9) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM027_I_ECC_0_RF_INT . + #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_0_RF_INT_BB_K2_SHIFT 9 + #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_0_RF_INT_E5 (0x1<<8) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM027_I_ECC_0_RF_INT . + #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_0_RF_INT_E5_SHIFT 8 + #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_1_RF_INT_BB_K2 (0x1<<10) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM027_I_ECC_1_RF_INT . + #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_1_RF_INT_BB_K2_SHIFT 10 + #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_1_RF_INT_E5 (0x1<<9) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM027_I_ECC_1_RF_INT . + #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_1_RF_INT_E5_SHIFT 9 #define UCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_K2 (0x1<<13) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . #define UCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_K2_SHIFT 13 #define UCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_E5 (0x1<<10) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY . @@ -78183,54 +82566,72 @@ #define UCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_K2_SHIFT 17 #define UCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5 (0x1<<11) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY . #define UCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_E5_SHIFT 11 - #define UCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_K2 (0x1<<29) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_K2_SHIFT 29 - #define UCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5 (0x1<<12) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5_SHIFT 12 - #define UCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_K2 (0x1<<12) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_K2_SHIFT 12 - #define UCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_E5_SHIFT 13 + #define UCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY (0x1<<12) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_SHIFT 12 #define UCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2 (0x1<<15) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . #define UCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_K2_SHIFT 15 - #define UCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5_SHIFT 14 + #define UCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5 (0x1<<13) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_E5_SHIFT 13 #define UCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2 (0x1<<16) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . #define UCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_K2_SHIFT 16 - #define UCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5_SHIFT 15 + #define UCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5 (0x1<<14) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_E5_SHIFT 14 #define UCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_K2 (0x1<<14) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . #define UCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_K2_SHIFT 14 - #define UCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5_SHIFT 16 - #define UCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5_SHIFT 17 - #define UCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY (0x1<<18) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_SHIFT 18 - #define UCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY (0x1<<19) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_SHIFT 19 - #define UCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY (0x1<<20) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_SHIFT 20 - #define UCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY (0x1<<21) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_SHIFT 21 - #define UCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY (0x1<<22) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_SHIFT 22 - #define UCM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY (0x1<<23) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_SHIFT 23 - #define UCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY (0x1<<24) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_SHIFT 24 - #define UCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5_SHIFT 25 - #define UCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_E5_SHIFT 26 - #define UCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY (0x1<<27) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT 27 - #define UCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY (0x1<<28) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_SHIFT 28 - #define UCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5 (0x1<<29) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_E5_SHIFT 29 - #define UCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0 (0x1<<30) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_0 . - #define UCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0_SHIFT 30 + #define UCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5 (0x1<<15) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_E5_SHIFT 15 + #define UCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_K2 (0x1<<29) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_K2_SHIFT 29 + #define UCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5 (0x1<<16) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_E5_SHIFT 16 + #define UCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_K2 (0x1<<18) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_K2_SHIFT 18 + #define UCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5 (0x1<<17) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_E5_SHIFT 17 + #define UCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_K2 (0x1<<19) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_K2_SHIFT 19 + #define UCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5 (0x1<<18) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_E5_SHIFT 18 + #define UCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_K2 (0x1<<20) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_K2_SHIFT 20 + #define UCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5 (0x1<<19) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_E5_SHIFT 19 + #define UCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_K2 (0x1<<21) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_K2_SHIFT 21 + #define UCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5 (0x1<<20) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_E5_SHIFT 20 + #define UCM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_K2 (0x1<<23) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_K2_SHIFT 23 + #define UCM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_E5 (0x1<<21) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_E5_SHIFT 21 + #define UCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2 (0x1<<24) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_K2_SHIFT 24 + #define UCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_E5 (0x1<<22) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_E5_SHIFT 22 + #define UCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_E5 (0x1<<23) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_E5_SHIFT 23 + #define UCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5 (0x1<<24) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_E5_SHIFT 24 + #define UCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_K2 (0x1<<26) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_K2_SHIFT 26 + #define UCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5 (0x1<<25) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_E5_SHIFT 25 + #define UCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2 (0x1<<27) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_K2_SHIFT 27 + #define UCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_E5 (0x1<<26) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_E5_SHIFT 26 + #define UCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_E5 (0x1<<27) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_E5_SHIFT 27 + #define UCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5 (0x1<<28) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_E5_SHIFT 28 + #define UCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0_BB_K2 (0x1<<30) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_0 . + #define UCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0_BB_K2_SHIFT 30 + #define UCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0_E5 (0x1<<29) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_0 . + #define UCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0_E5_SHIFT 29 + #define UCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_1_E5 (0x1<<30) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_1 . + #define UCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_1_E5_SHIFT 30 + #define UCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_RF_INT_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM030_I_ECC_RF_INT . + #define UCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_RF_INT_BB_K2_SHIFT 0 #define UCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT_BB_K2 (0x1<<3) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM024_I_ECC_0_RF_INT . #define UCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT_BB_K2_SHIFT 3 #define UCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT_BB_K2 (0x1<<4) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM024_I_ECC_1_RF_INT . @@ -78243,56 +82644,72 @@ #define UCM_REG_PRTY_MASK_H_0_MEM007_I_ECC_1_RF_INT_BB_K2_SHIFT 7 #define UCM_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_BB_K2 (0x1<<8) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT . #define UCM_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_BB_K2_SHIFT 8 - #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_0_RF_INT_BB_K2 (0x1<<9) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM027_I_ECC_0_RF_INT . - #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_0_RF_INT_BB_K2_SHIFT 9 - #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_1_RF_INT_BB_K2 (0x1<<10) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM027_I_ECC_1_RF_INT . - #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_1_RF_INT_BB_K2_SHIFT 10 #define UCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_BB_K2 (0x1<<11) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM028_I_ECC_RF_INT . #define UCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_BB_K2_SHIFT 11 + #define UCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_K2 (0x1<<22) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_K2_SHIFT 22 #define UCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2 (0x1<<25) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY . #define UCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_K2_SHIFT 25 - #define UCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_K2 (0x1<<26) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_K2_SHIFT 26 -#define UCM_REG_PRTY_MASK_H_1 0x1280214UL //Access:RW DataWidth:0x7 // Multi Field Register. - #define UCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_1 (0x1<<0) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY_1 . - #define UCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_1_SHIFT 0 - #define UCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY (0x1<<1) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_SHIFT 1 - #define UCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY (0x1<<2) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_SHIFT 2 - #define UCM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY (0x1<<3) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM003_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_SHIFT 3 - #define UCM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY (0x1<<4) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_SHIFT 4 - #define UCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY (0x1<<5) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_SHIFT 5 - #define UCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY (0x1<<6) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . - #define UCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_SHIFT 6 -#define UCM_REG_MEM026_RF_ECC_ERROR_CONNECT_0_E5 0x1280220UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: ucm.i_sm_con_ctx.rf_ecc_error_connect_0 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. + #define UCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_K2 (0x1<<28) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_K2_SHIFT 28 +#define UCM_REG_PRTY_MASK_H_1 0x1280214UL //Access:RW DataWidth:0x6 // Multi Field Register. + #define UCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_K2 (0x1<<1) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_K2_SHIFT 1 + #define UCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_E5 (0x1<<0) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_E5_SHIFT 0 + #define UCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_BB_K2 (0x1<<2) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_BB_K2_SHIFT 2 + #define UCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_E5 (0x1<<1) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_E5_SHIFT 1 + #define UCM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_BB_K2 (0x1<<3) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM003_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_BB_K2_SHIFT 3 + #define UCM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_E5 (0x1<<2) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM003_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_E5_SHIFT 2 + #define UCM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_BB_K2 (0x1<<4) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_BB_K2_SHIFT 4 + #define UCM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_E5 (0x1<<3) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_E5_SHIFT 3 + #define UCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_K2 (0x1<<5) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_K2_SHIFT 5 + #define UCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5 (0x1<<4) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_E5_SHIFT 4 + #define UCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_K2 (0x1<<6) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_K2_SHIFT 6 + #define UCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5 (0x1<<5) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY . + #define UCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_E5_SHIFT 5 + #define UCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_1_BB_K2 (0x1<<0) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY_1 . + #define UCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_1_BB_K2_SHIFT 0 +#define UCM_REG_MEM025_RF_ECC_ERROR_CONNECT_0_E5 0x1280220UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: ucm.i_sm_con_ctx.rf_ecc_error_connect_0 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define UCM_REG_MEM024_RF_ECC_ERROR_CONNECT_0_BB_K2 0x1280220UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: ucm.i_sm_con_ctx_0_11.rf_ecc_error_connect_0 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. -#define UCM_REG_MEM026_RF_ECC_ERROR_CONNECT_1_E5 0x1280224UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: ucm.i_sm_con_ctx.rf_ecc_error_connect_1 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. +#define UCM_REG_MEM025_RF_ECC_ERROR_CONNECT_1_E5 0x1280224UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: ucm.i_sm_con_ctx.rf_ecc_error_connect_1 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define UCM_REG_MEM024_RF_ECC_ERROR_CONNECT_1_BB_K2 0x1280224UL //Access:W DataWidth:0x12 // Register to generate up to two ECC errors on the next write to memory: ucm.i_sm_con_ctx_0_11.rf_ecc_error_connect_1 Includes 2 words of 9 bits each. The msb of each word is an error enable and the other bits decode which data bit should have an error. Do not decode past the memory data width of 128. The two words must not be equal when they are both enabled. For a single error use the lower word. The register is cleared after the memory write. #define UCM_REG_MEM_ECC_ENABLE_0 0x1280228UL //Access:RW DataWidth:0xa // Multi Field Register. - #define UCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_EN (0x1<<0) // Enable ECC for memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_msg_ram - #define UCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_EN_SHIFT 0 + #define UCM_REG_MEM_ECC_ENABLE_0_MEM029_I_ECC_EN_E5 (0x1<<0) // Enable ECC for memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_msg_ram + #define UCM_REG_MEM_ECC_ENABLE_0_MEM029_I_ECC_EN_E5_SHIFT 0 #define UCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN (0x1<<1) // Enable ECC for memory ecc instance ucm.i_agg_con_ctx.i_ecc_0 in module ucm_mem_agg_con_ctx_0_1 #define UCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_0_EN_SHIFT 1 #define UCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN (0x1<<2) // Enable ECC for memory ecc instance ucm.i_agg_con_ctx.i_ecc_1 in module ucm_mem_agg_con_ctx_0_1 #define UCM_REG_MEM_ECC_ENABLE_0_MEM005_I_ECC_1_EN_SHIFT 2 #define UCM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_E5 (0x1<<3) // Enable ECC for memory ecc instance ucm.i_agg_con_ctx_2.i_ecc in module ucm_mem_agg_con_ctx_2 #define UCM_REG_MEM_ECC_ENABLE_0_MEM006_I_ECC_EN_E5_SHIFT 3 - #define UCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_0_EN_E5 (0x1<<4) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx.i_ecc_0 in module ucm_mem_sm_con_ctx - #define UCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_0_EN_E5_SHIFT 4 - #define UCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_1_EN_E5 (0x1<<5) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx.i_ecc_1 in module ucm_mem_sm_con_ctx - #define UCM_REG_MEM_ECC_ENABLE_0_MEM026_I_ECC_1_EN_E5_SHIFT 5 + #define UCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_0_EN_E5 (0x1<<4) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx.i_ecc_0 in module ucm_mem_sm_con_ctx + #define UCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_0_EN_E5_SHIFT 4 + #define UCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_1_EN_E5 (0x1<<5) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx.i_ecc_1 in module ucm_mem_sm_con_ctx + #define UCM_REG_MEM_ECC_ENABLE_0_MEM025_I_ECC_1_EN_E5_SHIFT 5 #define UCM_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_0_EN_E5 (0x1<<6) // Enable ECC for memory ecc instance ucm.i_agg_task_ctx.i_ecc_0 in module ucm_mem_agg_task_ctx #define UCM_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_0_EN_E5_SHIFT 6 #define UCM_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_1_EN_E5 (0x1<<7) // Enable ECC for memory ecc instance ucm.i_agg_task_ctx.i_ecc_1 in module ucm_mem_agg_task_ctx #define UCM_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_1_EN_E5_SHIFT 7 - #define UCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_0_EN_E5 (0x1<<8) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx.i_ecc_0 in module ucm_mem_sm_task_ctx - #define UCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_0_EN_E5_SHIFT 8 - #define UCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_1_EN_E5 (0x1<<9) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx.i_ecc_1 in module ucm_mem_sm_task_ctx - #define UCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_1_EN_E5_SHIFT 9 + #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_0_EN_BB_K2 (0x1<<9) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_0 in module ucm_mem_sm_task_ctx_0_1 + #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_0_EN_BB_K2_SHIFT 9 + #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_0_EN_E5 (0x1<<8) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx.i_ecc_0 in module ucm_mem_sm_task_ctx + #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_0_EN_E5_SHIFT 8 + #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_1_EN_BB_K2 (0x1<<10) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_1 in module ucm_mem_sm_task_ctx_0_1 + #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_1_EN_BB_K2_SHIFT 10 + #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_1_EN_E5 (0x1<<9) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx.i_ecc_1 in module ucm_mem_sm_task_ctx + #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_1_EN_E5_SHIFT 9 + #define UCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_EN_BB_K2 (0x1<<0) // Enable ECC for memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_msg_ram + #define UCM_REG_MEM_ECC_ENABLE_0_MEM030_I_ECC_EN_BB_K2_SHIFT 0 #define UCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_0_EN_BB_K2 (0x1<<3) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_0 in module ucm_mem_sm_con_ctx_0_11 #define UCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_0_EN_BB_K2_SHIFT 3 #define UCM_REG_MEM_ECC_ENABLE_0_MEM024_I_ECC_1_EN_BB_K2 (0x1<<4) // Enable ECC for memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_1 in module ucm_mem_sm_con_ctx_0_11 @@ -78305,33 +82722,35 @@ #define UCM_REG_MEM_ECC_ENABLE_0_MEM007_I_ECC_1_EN_BB_K2_SHIFT 7 #define UCM_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN_BB_K2 (0x1<<8) // Enable ECC for memory ecc instance ucm.i_agg_task_ctx_2.i_ecc in module ucm_mem_agg_task_ctx_2 #define UCM_REG_MEM_ECC_ENABLE_0_MEM008_I_ECC_EN_BB_K2_SHIFT 8 - #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_0_EN_BB_K2 (0x1<<9) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_0 in module ucm_mem_sm_task_ctx_0_1 - #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_0_EN_BB_K2_SHIFT 9 - #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_1_EN_BB_K2 (0x1<<10) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_1 in module ucm_mem_sm_task_ctx_0_1 - #define UCM_REG_MEM_ECC_ENABLE_0_MEM027_I_ECC_1_EN_BB_K2_SHIFT 10 #define UCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_EN_BB_K2 (0x1<<11) // Enable ECC for memory ecc instance ucm.i_sm_task_ctx_2.i_ecc in module ucm_mem_sm_task_ctx_2 #define UCM_REG_MEM_ECC_ENABLE_0_MEM028_I_ECC_EN_BB_K2_SHIFT 11 #define UCM_REG_MEM_ECC_PARITY_ONLY_0 0x128022cUL //Access:RW DataWidth:0xa // Multi Field Register. - #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_PRTY (0x1<<0) // Set parity only for memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_msg_ram - #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_PRTY_SHIFT 0 + #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM029_I_ECC_PRTY_E5 (0x1<<0) // Set parity only for memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_msg_ram + #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM029_I_ECC_PRTY_E5_SHIFT 0 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY (0x1<<1) // Set parity only for memory ecc instance ucm.i_agg_con_ctx.i_ecc_0 in module ucm_mem_agg_con_ctx_0_1 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_0_PRTY_SHIFT 1 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY (0x1<<2) // Set parity only for memory ecc instance ucm.i_agg_con_ctx.i_ecc_1 in module ucm_mem_agg_con_ctx_0_1 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM005_I_ECC_1_PRTY_SHIFT 2 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_E5 (0x1<<3) // Set parity only for memory ecc instance ucm.i_agg_con_ctx_2.i_ecc in module ucm_mem_agg_con_ctx_2 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM006_I_ECC_PRTY_E5_SHIFT 3 - #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_0_PRTY_E5 (0x1<<4) // Set parity only for memory ecc instance ucm.i_sm_con_ctx.i_ecc_0 in module ucm_mem_sm_con_ctx - #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_0_PRTY_E5_SHIFT 4 - #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_1_PRTY_E5 (0x1<<5) // Set parity only for memory ecc instance ucm.i_sm_con_ctx.i_ecc_1 in module ucm_mem_sm_con_ctx - #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM026_I_ECC_1_PRTY_E5_SHIFT 5 + #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_0_PRTY_E5 (0x1<<4) // Set parity only for memory ecc instance ucm.i_sm_con_ctx.i_ecc_0 in module ucm_mem_sm_con_ctx + #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_0_PRTY_E5_SHIFT 4 + #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_1_PRTY_E5 (0x1<<5) // Set parity only for memory ecc instance ucm.i_sm_con_ctx.i_ecc_1 in module ucm_mem_sm_con_ctx + #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM025_I_ECC_1_PRTY_E5_SHIFT 5 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_0_PRTY_E5 (0x1<<6) // Set parity only for memory ecc instance ucm.i_agg_task_ctx.i_ecc_0 in module ucm_mem_agg_task_ctx #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_0_PRTY_E5_SHIFT 6 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_1_PRTY_E5 (0x1<<7) // Set parity only for memory ecc instance ucm.i_agg_task_ctx.i_ecc_1 in module ucm_mem_agg_task_ctx #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_1_PRTY_E5_SHIFT 7 - #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_0_PRTY_E5 (0x1<<8) // Set parity only for memory ecc instance ucm.i_sm_task_ctx.i_ecc_0 in module ucm_mem_sm_task_ctx - #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_0_PRTY_E5_SHIFT 8 - #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_1_PRTY_E5 (0x1<<9) // Set parity only for memory ecc instance ucm.i_sm_task_ctx.i_ecc_1 in module ucm_mem_sm_task_ctx - #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_1_PRTY_E5_SHIFT 9 + #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_0_PRTY_BB_K2 (0x1<<9) // Set parity only for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_0 in module ucm_mem_sm_task_ctx_0_1 + #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_0_PRTY_BB_K2_SHIFT 9 + #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_0_PRTY_E5 (0x1<<8) // Set parity only for memory ecc instance ucm.i_sm_task_ctx.i_ecc_0 in module ucm_mem_sm_task_ctx + #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_0_PRTY_E5_SHIFT 8 + #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_1_PRTY_BB_K2 (0x1<<10) // Set parity only for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_1 in module ucm_mem_sm_task_ctx_0_1 + #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_1_PRTY_BB_K2_SHIFT 10 + #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_1_PRTY_E5 (0x1<<9) // Set parity only for memory ecc instance ucm.i_sm_task_ctx.i_ecc_1 in module ucm_mem_sm_task_ctx + #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_1_PRTY_E5_SHIFT 9 + #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_PRTY_BB_K2 (0x1<<0) // Set parity only for memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_msg_ram + #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM030_I_ECC_PRTY_BB_K2_SHIFT 0 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_0_PRTY_BB_K2 (0x1<<3) // Set parity only for memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_0 in module ucm_mem_sm_con_ctx_0_11 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_0_PRTY_BB_K2_SHIFT 3 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM024_I_ECC_1_PRTY_BB_K2 (0x1<<4) // Set parity only for memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_1 in module ucm_mem_sm_con_ctx_0_11 @@ -78344,33 +82763,35 @@ #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM007_I_ECC_1_PRTY_BB_K2_SHIFT 7 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY_BB_K2 (0x1<<8) // Set parity only for memory ecc instance ucm.i_agg_task_ctx_2.i_ecc in module ucm_mem_agg_task_ctx_2 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM008_I_ECC_PRTY_BB_K2_SHIFT 8 - #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_0_PRTY_BB_K2 (0x1<<9) // Set parity only for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_0 in module ucm_mem_sm_task_ctx_0_1 - #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_0_PRTY_BB_K2_SHIFT 9 - #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_1_PRTY_BB_K2 (0x1<<10) // Set parity only for memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_1 in module ucm_mem_sm_task_ctx_0_1 - #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM027_I_ECC_1_PRTY_BB_K2_SHIFT 10 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_PRTY_BB_K2 (0x1<<11) // Set parity only for memory ecc instance ucm.i_sm_task_ctx_2.i_ecc in module ucm_mem_sm_task_ctx_2 #define UCM_REG_MEM_ECC_PARITY_ONLY_0_MEM028_I_ECC_PRTY_BB_K2_SHIFT 11 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0 0x1280230UL //Access:RC DataWidth:0xa // Multi Field Register. - #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_CORRECT (0x1<<0) // Record if a correctable error occurred on memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_msg_ram - #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_CORRECT_SHIFT 0 + #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM029_I_ECC_CORRECT_E5 (0x1<<0) // Record if a correctable error occurred on memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_msg_ram + #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM029_I_ECC_CORRECT_E5_SHIFT 0 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT (0x1<<1) // Record if a correctable error occurred on memory ecc instance ucm.i_agg_con_ctx.i_ecc_0 in module ucm_mem_agg_con_ctx_0_1 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_0_CORRECT_SHIFT 1 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT (0x1<<2) // Record if a correctable error occurred on memory ecc instance ucm.i_agg_con_ctx.i_ecc_1 in module ucm_mem_agg_con_ctx_0_1 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM005_I_ECC_1_CORRECT_SHIFT 2 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_E5 (0x1<<3) // Record if a correctable error occurred on memory ecc instance ucm.i_agg_con_ctx_2.i_ecc in module ucm_mem_agg_con_ctx_2 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM006_I_ECC_CORRECT_E5_SHIFT 3 - #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_0_CORRECT_E5 (0x1<<4) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_con_ctx.i_ecc_0 in module ucm_mem_sm_con_ctx - #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_0_CORRECT_E5_SHIFT 4 - #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_1_CORRECT_E5 (0x1<<5) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_con_ctx.i_ecc_1 in module ucm_mem_sm_con_ctx - #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM026_I_ECC_1_CORRECT_E5_SHIFT 5 + #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_0_CORRECT_E5 (0x1<<4) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_con_ctx.i_ecc_0 in module ucm_mem_sm_con_ctx + #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_0_CORRECT_E5_SHIFT 4 + #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_1_CORRECT_E5 (0x1<<5) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_con_ctx.i_ecc_1 in module ucm_mem_sm_con_ctx + #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM025_I_ECC_1_CORRECT_E5_SHIFT 5 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_0_CORRECT_E5 (0x1<<6) // Record if a correctable error occurred on memory ecc instance ucm.i_agg_task_ctx.i_ecc_0 in module ucm_mem_agg_task_ctx #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_0_CORRECT_E5_SHIFT 6 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_1_CORRECT_E5 (0x1<<7) // Record if a correctable error occurred on memory ecc instance ucm.i_agg_task_ctx.i_ecc_1 in module ucm_mem_agg_task_ctx #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_1_CORRECT_E5_SHIFT 7 - #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_0_CORRECT_E5 (0x1<<8) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_task_ctx.i_ecc_0 in module ucm_mem_sm_task_ctx - #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_0_CORRECT_E5_SHIFT 8 - #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_1_CORRECT_E5 (0x1<<9) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_task_ctx.i_ecc_1 in module ucm_mem_sm_task_ctx - #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_1_CORRECT_E5_SHIFT 9 + #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_0_CORRECT_BB_K2 (0x1<<9) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_0 in module ucm_mem_sm_task_ctx_0_1 + #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_0_CORRECT_BB_K2_SHIFT 9 + #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_0_CORRECT_E5 (0x1<<8) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_task_ctx.i_ecc_0 in module ucm_mem_sm_task_ctx + #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_0_CORRECT_E5_SHIFT 8 + #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_1_CORRECT_BB_K2 (0x1<<10) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_1 in module ucm_mem_sm_task_ctx_0_1 + #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_1_CORRECT_BB_K2_SHIFT 10 + #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_1_CORRECT_E5 (0x1<<9) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_task_ctx.i_ecc_1 in module ucm_mem_sm_task_ctx + #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_1_CORRECT_E5_SHIFT 9 + #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_CORRECT_BB_K2 (0x1<<0) // Record if a correctable error occurred on memory ecc instance ucm.i_xx_msg_ram.i_ecc in module ucm_mem_xx_msg_ram + #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM030_I_ECC_CORRECT_BB_K2_SHIFT 0 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_0_CORRECT_BB_K2 (0x1<<3) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_0 in module ucm_mem_sm_con_ctx_0_11 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_0_CORRECT_BB_K2_SHIFT 3 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM024_I_ECC_1_CORRECT_BB_K2 (0x1<<4) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_con_ctx_0_11.i_ecc_1 in module ucm_mem_sm_con_ctx_0_11 @@ -78383,10 +82804,6 @@ #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM007_I_ECC_1_CORRECT_BB_K2_SHIFT 7 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT_BB_K2 (0x1<<8) // Record if a correctable error occurred on memory ecc instance ucm.i_agg_task_ctx_2.i_ecc in module ucm_mem_agg_task_ctx_2 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM008_I_ECC_CORRECT_BB_K2_SHIFT 8 - #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_0_CORRECT_BB_K2 (0x1<<9) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_0 in module ucm_mem_sm_task_ctx_0_1 - #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_0_CORRECT_BB_K2_SHIFT 9 - #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_1_CORRECT_BB_K2 (0x1<<10) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_task_ctx_0_1.i_ecc_1 in module ucm_mem_sm_task_ctx_0_1 - #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM027_I_ECC_1_CORRECT_BB_K2_SHIFT 10 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_CORRECT_BB_K2 (0x1<<11) // Record if a correctable error occurred on memory ecc instance ucm.i_sm_task_ctx_2.i_ecc in module ucm_mem_sm_task_ctx_2 #define UCM_REG_MEM_ECC_ERROR_CORRECTED_0_MEM028_I_ECC_CORRECT_BB_K2_SHIFT 11 #define UCM_REG_MEM_ECC_EVENTS 0x1280234UL //Access:RC DataWidth:0x20 // Count all the block memories ECC events. @@ -78484,7 +82901,7 @@ #define UCM_REG_PBF_FRWRD_MODE_BB_K2 0x1280680UL //Access:RW DataWidth:0x1 // Input message mode. If 0 - cut-through; if 1 - store-forward. #define UCM_REG_SDM_ERR_HANDLE_EN 0x1280684UL //Access:RW DataWidth:0x1 // 0 - disable error handling in SDM message; 1 - enable error handling in SDM message. #define UCM_REG_DIR_BYP_EN 0x1280688UL //Access:RW DataWidth:0x1 // Direct bypass enable. -#define UCM_REG_FI_DESC_INPUT_VIOLATE 0x128068cUL //Access:R DataWidth:0x13 // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0 then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation: Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS; [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: XxBypass message in PCM block; [15] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [16] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [17]- Violation: Connection domain AggCtxLdStFlg==0 then AffinityType != 2; [18]- Violation: single Task domain AggCtxLdStFlg==0 then AffinityType != 3; +#define UCM_REG_FI_DESC_INPUT_VIOLATE 0x128068cUL //Access:R DataWidth:0x13 // Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0 then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation: Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS; [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: Agg Store message then Loader done with error; [15] - Violation: Direct message: Connection domain doesn't exist then AffinityType != 2; [16] - Violation: Direct message: Task domain doesn't exist then AffinityType != 3; [17]- Violation: Connection domain AggCtxLdStFlg==0 then AffinityType != 2; [18]- Violation: single Task domain AggCtxLdStFlg==0 then AffinityType != 3; #define UCM_REG_SE_DESC_INPUT_VIOLATE 0x1280690UL //Access:R DataWidth:0xd // Input message second descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0 then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation: Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0; [12]- Violation: dual Task domain AggCtxLdStFlg==0 then AffinityType != 3;Read only register. #define UCM_REG_IA_AGG_CON_PART_FILL_LVL 0x1280694UL //Access:R DataWidth:0x3 // Input Arbiter Aggregation Connection part FIFO fill level (in messages). #define UCM_REG_IA_SM_CON_PART_FILL_LVL 0x1280698UL //Access:R DataWidth:0x3 // Input Arbiter Storm Connection part FIFO fill level (in messages). @@ -78605,14 +83022,14 @@ #define UCM_REG_AGG_TASK_RULE6_Q 0x1280980UL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). #define UCM_REG_AGG_TASK_RULE7_Q_E5 0x1280984UL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). #define UCM_REG_AGG_TASK_RULE8_Q_E5 0x1280988UL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). -#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_0_E5 0x128098cUL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_1_E5 0x1280990UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_2_E5 0x1280994UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_3_E5 0x1280998UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_4_E5 0x128099cUL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_5_E5 0x12809a0UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_6_E5 0x12809a4UL //Access:RW DataWidth:0x3 // EventID bit width per task type. -#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_7_E5 0x12809a8UL //Access:RW DataWidth:0x3 // EventID bit width per task type. +#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_0_E5 0x128098cUL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_1_E5 0x1280990UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_2_E5 0x1280994UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_3_E5 0x1280998UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_4_E5 0x128099cUL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_5_E5 0x12809a0UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_6_E5 0x12809a4UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. +#define UCM_REG_CM_TASK_EVENT_ID_BWIDTH_7_E5 0x12809a8UL //Access:RW DataWidth:0x3 // EventID bit width per task type. Value of 0 is illegal. #define UCM_REG_IN_PRCS_TBL_CRD_AGG 0x1280a04UL //Access:RW DataWidth:0x4 // In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.IN_PRCS_TBL_CRD_AGGST need be no more than In-process table size=12. #define UCM_REG_IN_PRCS_TBL_CRD_AGGST 0x1280a08UL //Access:RW DataWidth:0x4 // In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGG.IN_PRCS_TBL_CRD_AGG need be no more than In-process table size=12. #define UCM_REG_IN_PRCS_TBL_FILL_LVL 0x1280a0cUL //Access:R DataWidth:0x4 // In-process Table fill level (in messages). @@ -78626,27 +83043,27 @@ #define UCM_REG_CMPL_DIR_CURR_ST 0x1280a2cUL //Access:R DataWidth:0x4 // Direct Completer FSM current state. #define UCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG 0x1280a30UL //Access:RW DataWidth:0x1 // If set, Xx connection bypass state will be added in calculation of CM output Event ID. #define UCM_REG_XX_BYP_TASK_STATE_EVNT_ID_FLG 0x1280a34UL //Access:RW DataWidth:0x1 // If set, Xx task bypass state will be added in calculation of CM output Event ID. -#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_0_E5 0x1280a38UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_1_E5 0x1280a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_2_E5 0x1280a40UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_3_E5 0x1280a44UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_4_E5 0x1280a48UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_5_E5 0x1280a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_6_E5 0x1280a50UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_7_E5 0x1280a54UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_8_E5 0x1280a58UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_9_E5 0x1280a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_10_E5 0x1280a60UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_11_E5 0x1280a64UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_12_E5 0x1280a68UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_13_E5 0x1280a6cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_14_E5 0x1280a70UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. -#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_15_E5 0x1280a74UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. +#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_0_E5 0x1280a38UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_1_E5 0x1280a3cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_2_E5 0x1280a40UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_3_E5 0x1280a44UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_4_E5 0x1280a48UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_5_E5 0x1280a4cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_6_E5 0x1280a50UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_7_E5 0x1280a54UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_8_E5 0x1280a58UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_9_E5 0x1280a5cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_10_E5 0x1280a60UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_11_E5 0x1280a64UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_12_E5 0x1280a68UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_13_E5 0x1280a6cUL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_14_E5 0x1280a70UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. +#define UCM_REG_CM_CON_EVENT_ID_BWIDTH_15_E5 0x1280a74UL //Access:RW DataWidth:0x3 // EventID bit width per connection type. Value of 0 is illegal. #define UCM_REG_CCFC_INIT_CRD 0x1280a84UL //Access:RW DataWidth:0x4 // CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. #define UCM_REG_TCFC_INIT_CRD 0x1280a88UL //Access:RW DataWidth:0x4 // TCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. #define UCM_REG_QM_INIT_CRD0 0x1280a8cUL //Access:RW DataWidth:0x5 // QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter. #define UCM_REG_TM_INIT_CRD 0x1280a90UL //Access:RW DataWidth:0x4 // Timers output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter. -#define UCM_REG_FIC_INIT_CRD 0x1280a94UL //Access:RW DataWidth:0x6 // FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up. +#define UCM_REG_FIC_INIT_CRD 0x1280a94UL //Access:RW DataWidth:0x5 // FIC output initial credit in REGQ pairs. Write writes the initial credit value; read returns the current value of the credit counter. #define UCM_REG_DIR_BYP_MSG_CNT 0x1280aa4UL //Access:RC DataWidth:0x20 // Counter of direct bypassed messages. #define UCM_REG_XSDM_LENGTH_MIS 0x1280aa8UL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at XSDM interface. #define UCM_REG_YSDM_LENGTH_MIS 0x1280aacUL //Access:RC DataWidth:0x1 // Set at message length mismatch (relative to last indication) at YSDM interface. @@ -78741,7 +83158,7 @@ #define UCM_REG_XX_TBL 0x1281a00UL //Access:R DataWidth:0x18 // Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [4:1] - Connection type; LL size: PCM - [7:5]; M/T/U/X/YCM - [11:5]; Tail pointer: PCM - [9:8]; M/T/U/X/YCM - [17:12]; Next pointer: PCM - [11:10]; M/T/U/X/YCM - [23:18]; #define UCM_REG_XX_TBL_SIZE_BB_K2 24 #define UCM_REG_XX_TBL_SIZE_E5 64 -#define UCM_REG_XX_DSCR_TBL 0x1281b00UL //Access:RW DataWidth:0x1e // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek. +#define UCM_REG_XX_DSCR_TBL 0x1281b00UL //Access:RW DataWidth:0x1e // Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [14:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[14:9]); Next pointer (MCM [20:15]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [20:15]); LTID (MCM [29:21]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [29:21]). Task Domain Exist (MCM [30]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [30]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek. #define UCM_REG_XX_DSCR_TBL_SIZE 64 #define UCM_REG_TM_CON_EVNT_ID_0_BB_K2 0x1280524UL //Access:RW DataWidth:0x8 // TM connection Event ID per connection type. #define UCM_REG_TM_CON_EVNT_ID_0_E5 0x1281c00UL //Access:RW DataWidth:0x8 // TM connection Event ID per connection type. @@ -78960,7 +83377,7 @@ #define UCM_REG_AGG_TASK_CF5_Q_E5 0x1282a14UL //Access:RW DataWidth:0x2 // Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable). #define UCM_REG_XX_MSG_RAM 0x1288000UL //Access:R DataWidth:0x20 // Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only. #define UCM_REG_XX_MSG_RAM_SIZE_BB_K2 6656 -#define UCM_REG_XX_MSG_RAM_SIZE_E5 7168 +#define UCM_REG_XX_MSG_RAM_SIZE_E5 8192 #define XSEM_REG_ENABLE_IN_BB_K2 0x1400004UL //Access:RW DataWidth:0xa // Multi Field Register. #define XSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_BB_K2 (0x1<<0) // Full input from external IF to LS input enable. #define XSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_BB_K2_SHIFT 0 @@ -80257,7 +84674,7 @@ #define XSEM_REG_THREADS_LIST_BB_K2 0x1400b14UL //Access:RW DataWidth:0x18 // List of free threads. #define XSEM_REG_THREAD_NUMBER_E5 0x1400b18UL //Access:RW DataWidth:0x6 // Defines the maixmum number of supported threads in SEMI. #define XSEM_REG_THREAD_ERROR_HIGH_E5 0x1400b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32 -#define XSEM_REG_FOC_MIN_MESSAGE_CREDIT_E5 0x1400b40UL //Access:RW DataWidth:0x8 // This field defines for each FOC the minimum message reuired for the FOC transfer to start. +#define XSEM_REG_FOC_MIN_MESSAGE_CREDIT_E5 0x1400b40UL //Access:RW DataWidth:0x8 // This field defines for each FOC the minimum message reuired for the FOC transfer to start. The values define in this register represents the number of Quad-IOR that the maximum message for each FOC interface may include. #define XSEM_REG_FOC_MIN_MESSAGE_CREDIT_SIZE 2 #define XSEM_REG_ORDER_HEAD_BB_K2 0x1400c00UL //Access:RW DataWidth:0x5 // This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues. #define XSEM_REG_ORDER_HEAD_SIZE 8 @@ -80272,6 +84689,7 @@ #define XSEM_REG_PF_NUM_ORDER_BASE_BB_K2 0x1400e10UL //Access:RW DataWidth:0x3 // This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues. #define XSEM_REG_DBG_ALM_FULL 0x1401000UL //Access:RW DataWidth:0x6 // Almost full for slow debug fifo. #define XSEM_REG_PASSIVE_ALM_FULL 0x1401004UL //Access:RW DataWidth:0x5 // The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted. +#define XSEM_REG_SYNC_DRA_WR_CREDIT_E5 0x1401008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DRA WR FIFO credit (in SEM_PD_CORE). #define XSEM_REG_SYNC_DRA_WR_ALM_FULL_BB_K2 0x1401008UL //Access:RW DataWidth:0x5 // Almost full for sync dra_wr fifo (data from DRA to STORM). #define XSEM_REG_SYNC_RAM_WR_ALM_FULL 0x140100cUL //Access:RW DataWidth:0x6 // Almost full for sync ram_wr fifo. #define XSEM_REG_SYNC_FOC_FIFO_WR_ALM_FULL_E5 0x1401010UL //Access:RW DataWidth:0x4 // Almost full for indication for FOC Sync FIFO. @@ -80369,7 +84787,7 @@ #define XSEM_REG_INT_TABLE_SIZE 256 #define XSEM_REG_FIC_COUNTER_GROUP_E5 0x1411000UL //Access:RW DataWidth:0x8 // This field enables a RD/WR access to the 24 counters of the "FIC Counters". #define XSEM_REG_FIC_COUNTER_GROUP_SIZE 24 -#define XSEM_REG_PB_THRD_STM_GROUP_E5 0x1412000UL //Access:R DataWidth:0x18 // Read the State mahcine state of teh trheads. 0:3 - state. 5:4 - Pending FOC cnt 6 - pending ready. 8:7 - Affinity type. 9 - Destination FOC. 10 - Destination Storm. 11 - counter increment ready. 16:12 - counter index. 17 - Debug monitor enable. 18 - Exlucsive. 22:19 - DRA size. +#define XSEM_REG_PB_THRD_STM_GROUP_E5 0x1412000UL //Access:R DataWidth:0x18 // Read the State mahcine state of teh trheads. 0:3 - state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10 - Destination FOC. 11 - Destination Storm. 12 - counter increment ready. 17:13 - counter index. 18 - Debug monitor enable. 19 - Exlucsive. 23:20 - DRA size. #define XSEM_REG_PB_THRD_STM_GROUP_SIZE 56 #define XSEM_REG_PASSIVE_BUFFER 0x1420000UL //Access:R DataWidth:0x20 // Passive buffer memory read only. #define XSEM_REG_PASSIVE_BUFFER_SIZE_BB_K2 4320 @@ -81679,7 +86097,7 @@ #define YSEM_REG_THREADS_LIST_BB_K2 0x1500b14UL //Access:RW DataWidth:0xe // List of free threads. #define YSEM_REG_THREAD_NUMBER_E5 0x1500b18UL //Access:RW DataWidth:0x6 // Defines the maixmum number of supported threads in SEMI. #define YSEM_REG_THREAD_ERROR_HIGH_E5 0x1500b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32 -#define YSEM_REG_FOC_MIN_MESSAGE_CREDIT_E5 0x1500b40UL //Access:RW DataWidth:0x8 // This field defines for each FOC the minimum message reuired for the FOC transfer to start. +#define YSEM_REG_FOC_MIN_MESSAGE_CREDIT_E5 0x1500b40UL //Access:RW DataWidth:0x8 // This field defines for each FOC the minimum message reuired for the FOC transfer to start. The values define in this register represents the number of Quad-IOR that the maximum message for each FOC interface may include. #define YSEM_REG_FOC_MIN_MESSAGE_CREDIT_SIZE 6 #define YSEM_REG_ORDER_HEAD_BB_K2 0x1500c00UL //Access:RW DataWidth:0x4 // This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues. #define YSEM_REG_ORDER_HEAD_SIZE 16 @@ -81694,6 +86112,7 @@ #define YSEM_REG_PF_NUM_ORDER_BASE_BB_K2 0x1500e10UL //Access:RW DataWidth:0x4 // This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues. #define YSEM_REG_DBG_ALM_FULL 0x1501000UL //Access:RW DataWidth:0x6 // Almost full for slow debug fifo. #define YSEM_REG_PASSIVE_ALM_FULL 0x1501004UL //Access:RW DataWidth:0x5 // The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted. +#define YSEM_REG_SYNC_DRA_WR_CREDIT_E5 0x1501008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DRA WR FIFO credit (in SEM_PD_CORE). #define YSEM_REG_SYNC_DRA_WR_ALM_FULL_BB_K2 0x1501008UL //Access:RW DataWidth:0x5 // Almost full for sync dra_wr fifo (data from DRA to STORM). #define YSEM_REG_SYNC_RAM_WR_ALM_FULL 0x150100cUL //Access:RW DataWidth:0x6 // Almost full for sync ram_wr fifo. #define YSEM_REG_SYNC_FOC_FIFO_WR_ALM_FULL_E5 0x1501010UL //Access:RW DataWidth:0x4 // Almost full for indication for FOC Sync FIFO. @@ -81791,7 +86210,7 @@ #define YSEM_REG_INT_TABLE_SIZE 256 #define YSEM_REG_FIC_COUNTER_GROUP_E5 0x1511000UL //Access:RW DataWidth:0x8 // This field enables a RD/WR access to the 24 counters of the "FIC Counters". #define YSEM_REG_FIC_COUNTER_GROUP_SIZE 24 -#define YSEM_REG_PB_THRD_STM_GROUP_E5 0x1512000UL //Access:R DataWidth:0x18 // Read the State mahcine state of teh trheads. 0:3 - state. 5:4 - Pending FOC cnt 6 - pending ready. 8:7 - Affinity type. 9 - Destination FOC. 10 - Destination Storm. 11 - counter increment ready. 16:12 - counter index. 17 - Debug monitor enable. 18 - Exlucsive. 22:19 - DRA size. +#define YSEM_REG_PB_THRD_STM_GROUP_E5 0x1512000UL //Access:R DataWidth:0x18 // Read the State mahcine state of teh trheads. 0:3 - state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10 - Destination FOC. 11 - Destination Storm. 12 - counter increment ready. 17:13 - counter index. 18 - Debug monitor enable. 19 - Exlucsive. 23:20 - DRA size. #define YSEM_REG_PB_THRD_STM_GROUP_SIZE 56 #define YSEM_REG_PASSIVE_BUFFER 0x1520000UL //Access:R DataWidth:0x20 // Passive buffer memory read only. #define YSEM_REG_PASSIVE_BUFFER_SIZE_BB_K2 2520 @@ -83099,7 +87518,7 @@ #define PSEM_REG_THREADS_LIST_BB_K2 0x1600b14UL //Access:RW DataWidth:0x4 // List of free threads. #define PSEM_REG_THREAD_NUMBER_E5 0x1600b18UL //Access:RW DataWidth:0x6 // Defines the maixmum number of supported threads in SEMI. #define PSEM_REG_THREAD_ERROR_HIGH_E5 0x1600b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32 -#define PSEM_REG_FOC_MIN_MESSAGE_CREDIT_E5 0x1600b40UL //Access:RW DataWidth:0x8 // This field defines for each FOC the minimum message reuired for the FOC transfer to start. +#define PSEM_REG_FOC_MIN_MESSAGE_CREDIT_E5 0x1600b40UL //Access:RW DataWidth:0x8 // This field defines for each FOC the minimum message reuired for the FOC transfer to start. The values define in this register represents the number of Quad-IOR that the maximum message for each FOC interface may include. #define PSEM_REG_FOC_MIN_MESSAGE_CREDIT_SIZE 2 #define PSEM_REG_ORDER_HEAD_BB_K2 0x1600c00UL //Access:RW DataWidth:0x2 // This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues. #define PSEM_REG_ORDER_HEAD_SIZE 2 @@ -83114,6 +87533,7 @@ #define PSEM_REG_PF_NUM_ORDER_BASE_BB_K2 0x1600e10UL //Access:RW DataWidth:0x1 // This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues. #define PSEM_REG_DBG_ALM_FULL 0x1601000UL //Access:RW DataWidth:0x6 // Almost full for slow debug fifo. #define PSEM_REG_PASSIVE_ALM_FULL 0x1601004UL //Access:RW DataWidth:0x5 // The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted. +#define PSEM_REG_SYNC_DRA_WR_CREDIT_E5 0x1601008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DRA WR FIFO credit (in SEM_PD_CORE). #define PSEM_REG_SYNC_DRA_WR_ALM_FULL_BB_K2 0x1601008UL //Access:RW DataWidth:0x5 // Almost full for sync dra_wr fifo (data from DRA to STORM). #define PSEM_REG_SYNC_RAM_WR_ALM_FULL 0x160100cUL //Access:RW DataWidth:0x6 // Almost full for sync ram_wr fifo. #define PSEM_REG_SYNC_FOC_FIFO_WR_ALM_FULL_E5 0x1601010UL //Access:RW DataWidth:0x4 // Almost full for indication for FOC Sync FIFO. @@ -83209,7 +87629,7 @@ #define PSEM_REG_INT_TABLE_SIZE 256 #define PSEM_REG_FIC_COUNTER_GROUP_E5 0x1611000UL //Access:RW DataWidth:0x8 // This field enables a RD/WR access to the 24 counters of the "FIC Counters". #define PSEM_REG_FIC_COUNTER_GROUP_SIZE 24 -#define PSEM_REG_PB_THRD_STM_GROUP_E5 0x1612000UL //Access:R DataWidth:0x18 // Read the State mahcine state of teh trheads. 0:3 - state. 5:4 - Pending FOC cnt 6 - pending ready. 8:7 - Affinity type. 9 - Destination FOC. 10 - Destination Storm. 11 - counter increment ready. 16:12 - counter index. 17 - Debug monitor enable. 18 - Exlucsive. 22:19 - DRA size. +#define PSEM_REG_PB_THRD_STM_GROUP_E5 0x1612000UL //Access:R DataWidth:0x18 // Read the State mahcine state of teh trheads. 0:3 - state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10 - Destination FOC. 11 - Destination Storm. 12 - counter increment ready. 17:13 - counter index. 18 - Debug monitor enable. 19 - Exlucsive. 23:20 - DRA size. #define PSEM_REG_PB_THRD_STM_GROUP_SIZE 56 #define PSEM_REG_PASSIVE_BUFFER 0x1620000UL //Access:R DataWidth:0x20 // Passive buffer memory read only. #define PSEM_REG_PASSIVE_BUFFER_SIZE_BB_K2 720 @@ -84517,7 +88937,7 @@ #define TSEM_REG_THREADS_LIST_BB_K2 0x1700b14UL //Access:RW DataWidth:0x18 // List of free threads. #define TSEM_REG_THREAD_NUMBER_E5 0x1700b18UL //Access:RW DataWidth:0x6 // Defines the maixmum number of supported threads in SEMI. #define TSEM_REG_THREAD_ERROR_HIGH_E5 0x1700b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32 -#define TSEM_REG_FOC_MIN_MESSAGE_CREDIT_E5 0x1700b40UL //Access:RW DataWidth:0x8 // This field defines for each FOC the minimum message reuired for the FOC transfer to start. +#define TSEM_REG_FOC_MIN_MESSAGE_CREDIT_E5 0x1700b40UL //Access:RW DataWidth:0x8 // This field defines for each FOC the minimum message reuired for the FOC transfer to start. The values define in this register represents the number of Quad-IOR that the maximum message for each FOC interface may include. #define TSEM_REG_FOC_MIN_MESSAGE_CREDIT_SIZE 2 #define TSEM_REG_ORDER_HEAD_BB_K2 0x1700c00UL //Access:RW DataWidth:0x5 // This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues. #define TSEM_REG_ORDER_HEAD_SIZE 24 @@ -84532,6 +88952,7 @@ #define TSEM_REG_PF_NUM_ORDER_BASE_BB_K2 0x1700e10UL //Access:RW DataWidth:0x5 // This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues. #define TSEM_REG_DBG_ALM_FULL 0x1701000UL //Access:RW DataWidth:0x6 // Almost full for slow debug fifo. #define TSEM_REG_PASSIVE_ALM_FULL 0x1701004UL //Access:RW DataWidth:0x5 // The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted. +#define TSEM_REG_SYNC_DRA_WR_CREDIT_E5 0x1701008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DRA WR FIFO credit (in SEM_PD_CORE). #define TSEM_REG_SYNC_DRA_WR_ALM_FULL_BB_K2 0x1701008UL //Access:RW DataWidth:0x5 // Almost full for sync dra_wr fifo (data from DRA to STORM). #define TSEM_REG_SYNC_RAM_WR_ALM_FULL 0x170100cUL //Access:RW DataWidth:0x6 // Almost full for sync ram_wr fifo. #define TSEM_REG_SYNC_FOC_FIFO_WR_ALM_FULL_E5 0x1701010UL //Access:RW DataWidth:0x4 // Almost full for indication for FOC Sync FIFO. @@ -84627,7 +89048,7 @@ #define TSEM_REG_INT_TABLE_SIZE 256 #define TSEM_REG_FIC_COUNTER_GROUP_E5 0x1711000UL //Access:RW DataWidth:0x8 // This field enables a RD/WR access to the 24 counters of the "FIC Counters". #define TSEM_REG_FIC_COUNTER_GROUP_SIZE 24 -#define TSEM_REG_PB_THRD_STM_GROUP_E5 0x1712000UL //Access:R DataWidth:0x18 // Read the State mahcine state of teh trheads. 0:3 - state. 5:4 - Pending FOC cnt 6 - pending ready. 8:7 - Affinity type. 9 - Destination FOC. 10 - Destination Storm. 11 - counter increment ready. 16:12 - counter index. 17 - Debug monitor enable. 18 - Exlucsive. 22:19 - DRA size. +#define TSEM_REG_PB_THRD_STM_GROUP_E5 0x1712000UL //Access:R DataWidth:0x18 // Read the State mahcine state of teh trheads. 0:3 - state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10 - Destination FOC. 11 - Destination Storm. 12 - counter increment ready. 17:13 - counter index. 18 - Debug monitor enable. 19 - Exlucsive. 23:20 - DRA size. #define TSEM_REG_PB_THRD_STM_GROUP_SIZE 56 #define TSEM_REG_PASSIVE_BUFFER 0x1720000UL //Access:R DataWidth:0x20 // Passive buffer memory read only. #define TSEM_REG_PASSIVE_BUFFER_SIZE_BB_K2 4320 @@ -85998,7 +90419,7 @@ #define MSEM_REG_THREADS_LIST_BB_K2 0x1800b14UL //Access:RW DataWidth:0x18 // List of free threads. #define MSEM_REG_THREAD_NUMBER_E5 0x1800b18UL //Access:RW DataWidth:0x6 // Defines the maixmum number of supported threads in SEMI. #define MSEM_REG_THREAD_ERROR_HIGH_E5 0x1800b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32 -#define MSEM_REG_FOC_MIN_MESSAGE_CREDIT_E5 0x1800b40UL //Access:RW DataWidth:0x8 // This field defines for each FOC the minimum message reuired for the FOC transfer to start. +#define MSEM_REG_FOC_MIN_MESSAGE_CREDIT_E5 0x1800b40UL //Access:RW DataWidth:0x8 // This field defines for each FOC the minimum message reuired for the FOC transfer to start. The values define in this register represents the number of Quad-IOR that the maximum message for each FOC interface may include. #define MSEM_REG_FOC_MIN_MESSAGE_CREDIT_SIZE 6 #define MSEM_REG_ORDER_HEAD_BB_K2 0x1800c00UL //Access:RW DataWidth:0x5 // This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues. #define MSEM_REG_ORDER_HEAD_SIZE 24 @@ -86013,6 +90434,7 @@ #define MSEM_REG_PF_NUM_ORDER_BASE_BB_K2 0x1800e10UL //Access:RW DataWidth:0x5 // This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues. #define MSEM_REG_DBG_ALM_FULL 0x1801000UL //Access:RW DataWidth:0x6 // Almost full for slow debug fifo. #define MSEM_REG_PASSIVE_ALM_FULL 0x1801004UL //Access:RW DataWidth:0x5 // The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted. +#define MSEM_REG_SYNC_DRA_WR_CREDIT_E5 0x1801008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DRA WR FIFO credit (in SEM_PD_CORE). #define MSEM_REG_SYNC_DRA_WR_ALM_FULL_BB_K2 0x1801008UL //Access:RW DataWidth:0x5 // Almost full for sync dra_wr fifo (data from DRA to STORM). #define MSEM_REG_SYNC_RAM_WR_ALM_FULL 0x180100cUL //Access:RW DataWidth:0x6 // Almost full for sync ram_wr fifo. #define MSEM_REG_SYNC_FOC_FIFO_WR_ALM_FULL_E5 0x1801010UL //Access:RW DataWidth:0x4 // Almost full for indication for FOC Sync FIFO. @@ -86108,7 +90530,7 @@ #define MSEM_REG_INT_TABLE_SIZE 256 #define MSEM_REG_FIC_COUNTER_GROUP_E5 0x1811000UL //Access:RW DataWidth:0x8 // This field enables a RD/WR access to the 24 counters of the "FIC Counters". #define MSEM_REG_FIC_COUNTER_GROUP_SIZE 24 -#define MSEM_REG_PB_THRD_STM_GROUP_E5 0x1812000UL //Access:R DataWidth:0x18 // Read the State mahcine state of teh trheads. 0:3 - state. 5:4 - Pending FOC cnt 6 - pending ready. 8:7 - Affinity type. 9 - Destination FOC. 10 - Destination Storm. 11 - counter increment ready. 16:12 - counter index. 17 - Debug monitor enable. 18 - Exlucsive. 22:19 - DRA size. +#define MSEM_REG_PB_THRD_STM_GROUP_E5 0x1812000UL //Access:R DataWidth:0x18 // Read the State mahcine state of teh trheads. 0:3 - state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10 - Destination FOC. 11 - Destination Storm. 12 - counter increment ready. 17:13 - counter index. 18 - Debug monitor enable. 19 - Exlucsive. 23:20 - DRA size. #define MSEM_REG_PB_THRD_STM_GROUP_SIZE 56 #define MSEM_REG_PASSIVE_BUFFER 0x1820000UL //Access:R DataWidth:0x20 // Passive buffer memory read only. #define MSEM_REG_PASSIVE_BUFFER_SIZE_BB_K2 4320 @@ -87416,7 +91838,7 @@ #define USEM_REG_THREADS_LIST_BB_K2 0x1900b14UL //Access:RW DataWidth:0x10 // List of free threads. #define USEM_REG_THREAD_NUMBER_E5 0x1900b18UL //Access:RW DataWidth:0x6 // Defines the maixmum number of supported threads in SEMI. #define USEM_REG_THREAD_ERROR_HIGH_E5 0x1900b1cUL //Access:R DataWidth:0x18 // Thread error high indication. Represents threads 55-32 -#define USEM_REG_FOC_MIN_MESSAGE_CREDIT_E5 0x1900b40UL //Access:RW DataWidth:0x8 // This field defines for each FOC the minimum message reuired for the FOC transfer to start. +#define USEM_REG_FOC_MIN_MESSAGE_CREDIT_E5 0x1900b40UL //Access:RW DataWidth:0x8 // This field defines for each FOC the minimum message reuired for the FOC transfer to start. The values define in this register represents the number of Quad-IOR that the maximum message for each FOC interface may include. #define USEM_REG_FOC_MIN_MESSAGE_CREDIT_SIZE 5 #define USEM_REG_ORDER_HEAD_BB_K2 0x1900c00UL //Access:RW DataWidth:0x4 // This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues. #define USEM_REG_ORDER_HEAD_SIZE 16 @@ -87431,6 +91853,7 @@ #define USEM_REG_PF_NUM_ORDER_BASE_BB_K2 0x1900e10UL //Access:RW DataWidth:0x4 // This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues. #define USEM_REG_DBG_ALM_FULL 0x1901000UL //Access:RW DataWidth:0x6 // Almost full for slow debug fifo. #define USEM_REG_PASSIVE_ALM_FULL 0x1901004UL //Access:RW DataWidth:0x5 // The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted. +#define USEM_REG_SYNC_DRA_WR_CREDIT_E5 0x1901008UL //Access:RW DataWidth:0x3 // Set the vlaue of the DRA WR FIFO credit (in SEM_PD_CORE). #define USEM_REG_SYNC_DRA_WR_ALM_FULL_BB_K2 0x1901008UL //Access:RW DataWidth:0x5 // Almost full for sync dra_wr fifo (data from DRA to STORM). #define USEM_REG_SYNC_RAM_WR_ALM_FULL 0x190100cUL //Access:RW DataWidth:0x6 // Almost full for sync ram_wr fifo. #define USEM_REG_SYNC_FOC_FIFO_WR_ALM_FULL_E5 0x1901010UL //Access:RW DataWidth:0x4 // Almost full for indication for FOC Sync FIFO. @@ -87526,7 +91949,7 @@ #define USEM_REG_INT_TABLE_SIZE 256 #define USEM_REG_FIC_COUNTER_GROUP_E5 0x1911000UL //Access:RW DataWidth:0x8 // This field enables a RD/WR access to the 24 counters of the "FIC Counters". #define USEM_REG_FIC_COUNTER_GROUP_SIZE 24 -#define USEM_REG_PB_THRD_STM_GROUP_E5 0x1912000UL //Access:R DataWidth:0x18 // Read the State mahcine state of teh trheads. 0:3 - state. 5:4 - Pending FOC cnt 6 - pending ready. 8:7 - Affinity type. 9 - Destination FOC. 10 - Destination Storm. 11 - counter increment ready. 16:12 - counter index. 17 - Debug monitor enable. 18 - Exlucsive. 22:19 - DRA size. +#define USEM_REG_PB_THRD_STM_GROUP_E5 0x1912000UL //Access:R DataWidth:0x18 // Read the State mahcine state of teh trheads. 0:3 - state. 4 - Pending FOC. 6:5 - Pending Pratial FIN cnt 7 - pending ready. 9:8 - Affinity type. 10 - Destination FOC. 11 - Destination Storm. 12 - counter increment ready. 17:13 - counter index. 18 - Debug monitor enable. 19 - Exlucsive. 23:20 - DRA size. #define USEM_REG_PB_THRD_STM_GROUP_SIZE 56 #define USEM_REG_PASSIVE_BUFFER 0x1920000UL //Access:R DataWidth:0x20 // Passive buffer memory read only. #define USEM_REG_PASSIVE_BUFFER_SIZE_BB_K2 2880 |