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authorMarcel Moolenaar <marcel@FreeBSD.org>2013-08-29 16:26:04 +0000
committerMarcel Moolenaar <marcel@FreeBSD.org>2013-08-29 16:26:04 +0000
commit4fc499753563c782036f76e5a2293ffa12477444 (patch)
tree98d2aa4dd93d27834208a12eaf8d083843f88283 /sys/dev/uart
parente289e9f2ca00bdde7ea898c1007d487104dcbee6 (diff)
Notes
Diffstat (limited to 'sys/dev/uart')
-rw-r--r--sys/dev/uart/uart_dev_ns8250.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/sys/dev/uart/uart_dev_ns8250.c b/sys/dev/uart/uart_dev_ns8250.c
index 1c337cacf3ac..2fad76c7615c 100644
--- a/sys/dev/uart/uart_dev_ns8250.c
+++ b/sys/dev/uart/uart_dev_ns8250.c
@@ -453,7 +453,19 @@ ns8250_bus_attach(struct uart_softc *sc)
ns8250->ier |= ns8250->ier_rxbits;
uart_setreg(bas, REG_IER, ns8250->ier);
uart_barrier(bas);
-
+
+ /*
+ * Timing of the H/W access was changed with r253161 of uart_core.c
+ * It has been observed that an ITE IT8513E would signal a break
+ * condition with pretty much every character it received, unless
+ * it had enough time to settle between ns8250_bus_attach() and
+ * ns8250_bus_ipend() -- which it accidentally had before r253161.
+ * It's not understood why the UART chip behaves this way and it
+ * could very well be that the DELAY make the H/W work in the same
+ * accidental manner as before. More analysis is warranted, but
+ * at least now we fixed a known regression.
+ */
+ DELAY(150);
return (0);
}