diff options
| author | Andre Silva <andasilv@amd.com> | 2026-04-23 19:27:06 +0000 |
|---|---|---|
| committer | Mitchell Horne <mhorne@FreeBSD.org> | 2026-04-28 18:49:22 +0000 |
| commit | 146b30bad9f65a098e6c09ae93bb1da2ff59616d (patch) | |
| tree | 3a9e991f9a901c23848e6414cfa424c68b4dabd3 /sys/dev | |
| parent | 39f48829a045e22c39e7099fa39c1a8b7d3fa7f4 (diff) | |
Diffstat (limited to 'sys/dev')
| -rw-r--r-- | sys/dev/hwpmc/hwpmc_amd.c | 25 | ||||
| -rw-r--r-- | sys/dev/hwpmc/hwpmc_ibs.c | 18 |
2 files changed, 39 insertions, 4 deletions
diff --git a/sys/dev/hwpmc/hwpmc_amd.c b/sys/dev/hwpmc/hwpmc_amd.c index 8531db13dc6f..299021494716 100644 --- a/sys/dev/hwpmc/hwpmc_amd.c +++ b/sys/dev/hwpmc/hwpmc_amd.c @@ -40,6 +40,7 @@ #include <sys/pmc.h> #include <sys/pmckern.h> #include <sys/smp.h> +#include <sys/sysctl.h> #include <sys/systm.h> #include <machine/cpu.h> @@ -183,6 +184,24 @@ static uint64_t amd_core_allowed_mask; static uint64_t amd_l3_allowed_mask; static uint64_t amd_df_allowed_mask; +static uint64_t amd_core_extra_mask; +static uint64_t amd_l3_extra_mask; +static uint64_t amd_df_extra_mask; + +SYSCTL_DECL(_kern_hwpmc); + +SYSCTL_U64(_kern_hwpmc, OID_AUTO, amd_core_extra_mask, CTLFLAG_RDTUN, + &amd_core_extra_mask, 0, + "Extra allowed bits in AMD core PMU PERFEVTSEL (override; default 0)"); + +SYSCTL_U64(_kern_hwpmc, OID_AUTO, amd_l3_extra_mask, CTLFLAG_RDTUN, + &amd_l3_extra_mask, 0, + "Extra allowed bits in AMD L3 PMU control (override; default 0)"); + +SYSCTL_U64(_kern_hwpmc, OID_AUTO, amd_df_extra_mask, CTLFLAG_RDTUN, + &amd_df_extra_mask, 0, + "Extra allowed bits in AMD DF PMU control (override; default 0)"); + static void amd_init_policy(void) { @@ -205,13 +224,13 @@ amd_config_mask(enum sub_class subclass, uint64_t caps) switch (subclass) { case PMC_AMD_SUB_CLASS_CORE: - return (amd_core_allowed_mask | + return (amd_core_allowed_mask | amd_core_extra_mask | (((caps & PMC_CAP_PRECISE) != 0) ? AMD_PMC_PRECISERETIRE : 0)); case PMC_AMD_SUB_CLASS_L3_CACHE: - return (amd_l3_allowed_mask); + return (amd_l3_allowed_mask | amd_l3_extra_mask); case PMC_AMD_SUB_CLASS_DATA_FABRIC: - return (amd_df_allowed_mask); + return (amd_df_allowed_mask | amd_df_extra_mask); default: return (0); } diff --git a/sys/dev/hwpmc/hwpmc_ibs.c b/sys/dev/hwpmc/hwpmc_ibs.c index 93e43d657633..8cfe7b2df145 100644 --- a/sys/dev/hwpmc/hwpmc_ibs.c +++ b/sys/dev/hwpmc/hwpmc_ibs.c @@ -36,6 +36,7 @@ #include <sys/pmckern.h> #include <sys/pmclog.h> #include <sys/smp.h> +#include <sys/sysctl.h> #include <sys/systm.h> #define EXTERR_CATEGORY EXTERR_CAT_HWPMC_IBS @@ -60,6 +61,19 @@ static uint64_t ibs_features; static uint64_t ibs_fetch_allowed_mask; static uint64_t ibs_op_allowed_mask; +static uint64_t ibs_fetch_extra_mask; +static uint64_t ibs_op_extra_mask; + +SYSCTL_DECL(_kern_hwpmc); + +SYSCTL_U64(_kern_hwpmc, OID_AUTO, ibs_fetch_extra_mask, CTLFLAG_RDTUN, + &ibs_fetch_extra_mask, 0, + "Extra allowed bits in the IBS fetch control MSR (override; default 0)"); + +SYSCTL_U64(_kern_hwpmc, OID_AUTO, ibs_op_extra_mask, CTLFLAG_RDTUN, + &ibs_op_extra_mask, 0, + "Extra allowed bits in the IBS op control MSR (override; default 0)"); + /* * Per-processor information */ @@ -98,7 +112,7 @@ static int ibs_validate_fetch_config(uint64_t config) { - if ((config & ~ibs_fetch_allowed_mask) != 0) + if ((config & ~(ibs_fetch_allowed_mask | ibs_fetch_extra_mask)) != 0) return (EINVAL); return (0); @@ -120,6 +134,8 @@ ibs_validate_op_config(uint64_t config) allowed_mask |= IBS_OP_CTL_LDLATMASK | IBS_OP_CTL_L3MISSONLY; } + allowed_mask |= ibs_op_extra_mask; + if ((config & ~allowed_mask) != 0) return (EINVAL); |