diff options
| author | Leandro Lupori <luporl@FreeBSD.org> | 2020-11-06 14:12:45 +0000 |
|---|---|---|
| committer | Leandro Lupori <luporl@FreeBSD.org> | 2020-11-06 14:12:45 +0000 |
| commit | e2d6c417e3030c814e048ec2cda803cb7971bd75 (patch) | |
| tree | 41b1c511a9ead5d7bd50a96f4ad93ddb7026caec /sys/powerpc/include | |
| parent | 5d0e861910978450c46d2a65385aeb3286a17fa4 (diff) | |
Notes
Diffstat (limited to 'sys/powerpc/include')
| -rw-r--r-- | sys/powerpc/include/pmap.h | 4 | ||||
| -rw-r--r-- | sys/powerpc/include/pte.h | 12 | ||||
| -rw-r--r-- | sys/powerpc/include/slb.h | 8 | ||||
| -rw-r--r-- | sys/powerpc/include/vmparam.h | 23 |
4 files changed, 35 insertions, 12 deletions
diff --git a/sys/powerpc/include/pmap.h b/sys/powerpc/include/pmap.h index 1ae90494ebfa..fd36e55a12e0 100644 --- a/sys/powerpc/include/pmap.h +++ b/sys/powerpc/include/pmap.h @@ -148,8 +148,8 @@ RB_PROTOTYPE(pvo_tree, pvo_entry, pvo_plink, pvo_vaddr_compare); #define PVO_MANAGED 0x020UL /* PVO entry is managed */ #define PVO_BOOTSTRAP 0x080UL /* PVO entry allocated during bootstrap */ -#define PVO_DEAD 0x100UL /* waiting to be deleted */ -#define PVO_LARGE 0x200UL /* large page */ +#define PVO_DEAD 0x100UL /* waiting to be deleted */ +#define PVO_LARGE 0x200UL /* large page */ #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) diff --git a/sys/powerpc/include/pte.h b/sys/powerpc/include/pte.h index 5e38e6bbcf28..9dc2787cf2ff 100644 --- a/sys/powerpc/include/pte.h +++ b/sys/powerpc/include/pte.h @@ -111,6 +111,7 @@ typedef struct lpte lpte_t; /* High quadword: */ #define LPTE_VSID_SHIFT 12 #define LPTE_AVPN_MASK 0xFFFFFFFFFFFFFF80ULL +#define LPTE_AVA_MASK 0x3FFFFFFFFFFFFF80ULL #define LPTE_API 0x0000000000000F80ULL #define LPTE_SWBITS 0x0000000000000078ULL #define LPTE_WIRED 0x0000000000000010ULL @@ -120,8 +121,13 @@ typedef struct lpte lpte_t; #define LPTE_VALID 0x0000000000000001ULL /* Low quadword: */ +#define LP_4K_16M 0x38 /* 4KB base, 16MB actual page size */ + #define EXTEND_PTE(x) UINT64_C(x) /* make constants 64-bit */ #define LPTE_RPGN 0xfffffffffffff000ULL +#define LPTE_LP_MASK 0x00000000000ff000ULL +#define LPTE_LP_SHIFT 12 +#define LPTE_LP_4K_16M ((unsigned long long)(LP_4K_16M) << LPTE_LP_SHIFT) #define LPTE_REF EXTEND_PTE( PTE_REF ) #define LPTE_CHG EXTEND_PTE( PTE_CHG ) #define LPTE_WIMG EXTEND_PTE( PTE_WIMG ) @@ -139,6 +145,12 @@ typedef struct lpte lpte_t; #define LPTE_RW LPTE_BW #define LPTE_RO LPTE_BR +/* HPT superpage definitions */ +#define HPT_SP_SHIFT (VM_LEVEL_0_ORDER + PAGE_SHIFT) +#define HPT_SP_SIZE (1 << HPT_SP_SHIFT) +#define HPT_SP_MASK (HPT_SP_SIZE - 1) +#define HPT_SP_PAGES (1 << VM_LEVEL_0_ORDER) + /* POWER ISA 3.0 Radix Table Definitions */ #define RPTE_VALID 0x8000000000000000ULL #define RPTE_LEAF 0x4000000000000000ULL /* is a PTE: always 1 */ diff --git a/sys/powerpc/include/slb.h b/sys/powerpc/include/slb.h index f93280030f94..f710aca8de97 100644 --- a/sys/powerpc/include/slb.h +++ b/sys/powerpc/include/slb.h @@ -64,6 +64,14 @@ #define SLBE_ESID_MASK 0xfffffffff0000000UL /* Effective segment ID mask */ #define SLBE_ESID_SHIFT 28 +/* + * SLB page sizes encoding, as present in property ibm,segment-page-sizes + * of CPU device tree node. + * + * See LoPAPR: CPU Node Properties, section C.6.1.4. + */ +#define SLB_PGSZ_4K_4K 0 + /* Virtual real-mode VSID in LPARs */ #define VSID_VRMA 0x1ffffff diff --git a/sys/powerpc/include/vmparam.h b/sys/powerpc/include/vmparam.h index ab4c6aa2a651..77457717a3fd 100644 --- a/sys/powerpc/include/vmparam.h +++ b/sys/powerpc/include/vmparam.h @@ -185,31 +185,34 @@ struct pmap_physseg { #define VM_NFREELIST 1 #define VM_FREELIST_DEFAULT 0 -/* - * The largest allocation size is 4MB. - */ #ifdef __powerpc64__ +/* The largest allocation size is 16MB. */ #define VM_NFREEORDER 13 #else +/* The largest allocation size is 4MB. */ #define VM_NFREEORDER 11 #endif #ifndef VM_NRESERVLEVEL #ifdef __powerpc64__ +/* Enable superpage reservations: 1 level. */ #define VM_NRESERVLEVEL 1 #else -/* - * Disable superpage reservations. - */ +/* Disable superpage reservations. */ #define VM_NRESERVLEVEL 0 #endif #endif -/* - * Level 0 reservations consist of 512 pages. - */ #ifndef VM_LEVEL_0_ORDER -#define VM_LEVEL_0_ORDER 9 +/* Level 0 reservations consist of 512 (RPT) or 4096 (HPT) pages. */ +#define VM_LEVEL_0_ORDER vm_level_0_order +#ifndef __ASSEMBLER__ +extern int vm_level_0_order; +#endif +#endif + +#ifndef VM_LEVEL_0_ORDER_MAX +#define VM_LEVEL_0_ORDER_MAX 12 #endif #ifdef __powerpc64__ |
