diff options
| author | Michal Meloun <mmel@FreeBSD.org> | 2015-11-30 17:09:25 +0000 |
|---|---|---|
| committer | Michal Meloun <mmel@FreeBSD.org> | 2015-11-30 17:09:25 +0000 |
| commit | e53ea2ab774acbe490b813bb4d9e01b4990c7156 (patch) | |
| tree | 2599b75ad73abdd103e31b577c52cf28dbd7b781 /sys | |
| parent | a2a45f908ab1b9c102197404956ed1c72e78d550 (diff) | |
Notes
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/arm/arm/pmap-v6-new.c | 16 | ||||
| -rw-r--r-- | sys/arm/include/pte-v6.h | 1 | ||||
| -rw-r--r-- | sys/arm/include/vm.h | 16 |
3 files changed, 18 insertions, 15 deletions
diff --git a/sys/arm/arm/pmap-v6-new.c b/sys/arm/arm/pmap-v6-new.c index 8b7676e914ab..2196f916b672 100644 --- a/sys/arm/arm/pmap-v6-new.c +++ b/sys/arm/arm/pmap-v6-new.c @@ -388,14 +388,14 @@ pmap_debug(int level) static uint32_t tex_class[8] = { /* type inner cache outer cache */ - TEX(PRRR_MEM, NMRR_WB_WA, NMRR_WB_WA, 0), /* 0 - ATTR_WB_WA */ - TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 1 - ATTR_NOCACHE */ - TEX(PRRR_DEV, NMRR_NC, NMRR_NC, 0), /* 2 - ATTR_DEVICE */ - TEX(PRRR_SO, NMRR_NC, NMRR_NC, 0), /* 3 - ATTR_SO */ - TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 4 - NOT USED YET */ - TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 5 - NOT USED YET */ - TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 6 - NOT USED YET */ - TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 7 - NOT USED YET */ + TEX(PRRR_MEM, NMRR_WB_WA, NMRR_WB_WA, 0), /* 0 - ATTR_WB_WA */ + TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 1 - ATTR_NOCACHE */ + TEX(PRRR_DEV, NMRR_NC, NMRR_NC, 0), /* 2 - ATTR_DEVICE */ + TEX(PRRR_SO, NMRR_NC, NMRR_NC, 0), /* 3 - ATTR_SO */ + TEX(PRRR_MEM, NMRR_WT, NMRR_WT, 0), /* 4 - ATTR_WT */ + TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 5 - NOT USED YET */ + TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 6 - NOT USED YET */ + TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 7 - NOT USED YET */ }; #undef TEX diff --git a/sys/arm/include/pte-v6.h b/sys/arm/include/pte-v6.h index 536c1e1258d7..c0eb4173360e 100644 --- a/sys/arm/include/pte-v6.h +++ b/sys/arm/include/pte-v6.h @@ -196,6 +196,7 @@ #define PTE2_ATTR_NOCACHE TEX2_CLASS_1 #define PTE2_ATTR_DEVICE TEX2_CLASS_2 #define PTE2_ATTR_SO TEX2_CLASS_3 +#define PTE2_ATTR_WT TEX2_CLASS_4 /* * Software defined bits for L1 descriptors * - L1_AP0 is used as page accessed bit diff --git a/sys/arm/include/vm.h b/sys/arm/include/vm.h index 5b2f125d1265..8fb230e23de8 100644 --- a/sys/arm/include/vm.h +++ b/sys/arm/include/vm.h @@ -32,14 +32,16 @@ #ifdef ARM_NEW_PMAP #include <machine/pte-v6.h> -#define VM_MEMATTR_WB_WA ((vm_memattr_t)PTE2_ATTR_WB_WA) -#define VM_MEMATTR_NOCACHE ((vm_memattr_t)PTE2_ATTR_NOCACHE) -#define VM_MEMATTR_DEVICE ((vm_memattr_t)PTE2_ATTR_DEVICE) -#define VM_MEMATTR_SO ((vm_memattr_t)PTE2_ATTR_SO) - -#define VM_MEMATTR_DEFAULT VM_MEMATTR_WB_WA -#define VM_MEMATTR_UNCACHEABLE VM_MEMATTR_SO /*name is misused by DMA */ +#define VM_MEMATTR_WB_WA ((vm_memattr_t)PTE2_ATTR_WB_WA) +#define VM_MEMATTR_NOCACHE ((vm_memattr_t)PTE2_ATTR_NOCACHE) +#define VM_MEMATTR_DEVICE ((vm_memattr_t)PTE2_ATTR_DEVICE) +#define VM_MEMATTR_SO ((vm_memattr_t)PTE2_ATTR_SO) +#define VM_MEMATTR_WT ((vm_memattr_t)PTE2_ATTR_WT) +#define VM_MEMATTR_DEFAULT VM_MEMATTR_WB_WA +#define VM_MEMATTR_UNCACHEABLE VM_MEMATTR_SO /* misused by DMA */ +#define VM_MEMATTR_WRITE_COMBINING VM_MEMATTR_WT /* for DRM */ +#define VM_MEMATTR_WRITE_BACK VM_MEMATTR_WB_WA /* for DRM */ #else /* Memory attribute configuration. */ |