diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2014-11-24 09:08:18 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2014-11-24 09:08:18 +0000 |
| commit | 5ca98fd98791947eba83a1ed3f2c8191ef7afa6c (patch) | |
| tree | f5944309621cee4fe0976be6f9ac619b7ebfc4c2 /test/Bitcode | |
| parent | 68bcb7db193e4bc81430063148253d30a791023e (diff) | |
Notes
Diffstat (limited to 'test/Bitcode')
49 files changed, 1851 insertions, 5 deletions
diff --git a/test/Bitcode/aggregateInstructions.3.2.ll b/test/Bitcode/aggregateInstructions.3.2.ll new file mode 100644 index 000000000000..9352390b131b --- /dev/null +++ b/test/Bitcode/aggregateInstructions.3.2.ll @@ -0,0 +1,33 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s
+
+; aggregateOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
+; The test checks that LLVM does not misread instructions with aggregate operands
+; in older bitcode files.
+
+define void @extractvalue([4 x i8] %x1, [4 x [4 x i8]] %x2, {{i32, float}} %x3){
+entry:
+; CHECK: %res1 = extractvalue [4 x i8] %x1, 0
+ %res1 = extractvalue [4 x i8] %x1, 0
+
+; CHECK-NEXT: %res2 = extractvalue [4 x [4 x i8]] %x2, 1
+ %res2 = extractvalue [4 x [4 x i8 ]] %x2, 1
+
+; CHECK-NEXT: %res3 = extractvalue [4 x [4 x i8]] %x2, 0, 1
+ %res3 = extractvalue [4 x [4 x i8 ]] %x2, 0, 1
+
+; CHECK-NEXT: %res4 = extractvalue { { i32, float } } %x3, 0, 1
+ %res4 = extractvalue {{i32, float}} %x3, 0, 1
+
+ ret void
+}
+
+define void @insertvalue([4 x [4 x i8 ]] %x1){
+entry:
+; CHECK: %res1 = insertvalue [4 x [4 x i8]] %x1, i8 0, 0, 0
+ %res1 = insertvalue [4 x [4 x i8 ]] %x1, i8 0, 0, 0
+
+; CHECK-NEXT: %res2 = insertvalue [4 x [4 x i8]] undef, i8 0, 0, 0
+ %res2 = insertvalue [4 x [4 x i8 ]] undef, i8 0, 0, 0
+
+ ret void
+}
\ No newline at end of file diff --git a/test/Bitcode/aggregateInstructions.3.2.ll.bc b/test/Bitcode/aggregateInstructions.3.2.ll.bc Binary files differnew file mode 100644 index 000000000000..053f85fda645 --- /dev/null +++ b/test/Bitcode/aggregateInstructions.3.2.ll.bc diff --git a/test/Bitcode/atomic.ll b/test/Bitcode/atomic.ll new file mode 100644 index 000000000000..37815a749b55 --- /dev/null +++ b/test/Bitcode/atomic.ll @@ -0,0 +1,17 @@ +; RUN: llvm-as %s -o - | llvm-dis | FileCheck %s + +define void @test_cmpxchg(i32* %addr, i32 %desired, i32 %new) { + cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst + ; CHECK: cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst + + cmpxchg volatile i32* %addr, i32 %desired, i32 %new seq_cst monotonic + ; CHECK: cmpxchg volatile i32* %addr, i32 %desired, i32 %new seq_cst monotonic + + cmpxchg weak i32* %addr, i32 %desired, i32 %new acq_rel acquire + ; CHECK: cmpxchg weak i32* %addr, i32 %desired, i32 %new acq_rel acquire + + cmpxchg weak volatile i32* %addr, i32 %desired, i32 %new singlethread release monotonic + ; CHECK: cmpxchg weak volatile i32* %addr, i32 %desired, i32 %new singlethread release monotonic + + ret void +}
\ No newline at end of file diff --git a/test/Bitcode/attributes.ll b/test/Bitcode/attributes.ll index 1789878e9f50..2490e5920726 100644 --- a/test/Bitcode/attributes.ll +++ b/test/Bitcode/attributes.ll @@ -203,7 +203,7 @@ define void @f34() ; CHECK: define void @f34() { call void @nobuiltin() nobuiltin -; CHECK: call void @nobuiltin() #24 +; CHECK: call void @nobuiltin() #25 ret void; } @@ -213,6 +213,32 @@ define void @f35() optnone noinline ret void; } +define void @f36(i8* inalloca) { +; CHECK: define void @f36(i8* inalloca) { + ret void +} + +define nonnull i8* @f37(i8* nonnull %a) { +; CHECK: define nonnull i8* @f37(i8* nonnull %a) { + ret i8* %a +} + +define void @f38() unnamed_addr jumptable { +; CHECK: define void @f38() unnamed_addr #24 + call void bitcast (void (i8*)* @f36 to void ()*)() + unreachable +} + +define dereferenceable(2) i8* @f39(i8* dereferenceable(1) %a) { +; CHECK: define dereferenceable(2) i8* @f39(i8* dereferenceable(1) %a) { + ret i8* %a +} + +define dereferenceable(18446744073709551606) i8* @f40(i8* dereferenceable(18446744073709551615) %a) { +; CHECK: define dereferenceable(18446744073709551606) i8* @f40(i8* dereferenceable(18446744073709551615) %a) { + ret i8* %a +} + ; CHECK: attributes #0 = { noreturn } ; CHECK: attributes #1 = { nounwind } ; CHECK: attributes #2 = { readnone } @@ -237,5 +263,5 @@ define void @f35() optnone noinline ; CHECK: attributes #21 = { sspstrong } ; CHECK: attributes #22 = { minsize } ; CHECK: attributes #23 = { noinline optnone } -; CHECK: attributes #24 = { nobuiltin } - +; CHECK: attributes #24 = { jumptable } +; CHECK: attributes #25 = { nobuiltin } diff --git a/test/Bitcode/binaryFloatInstructions.3.2.ll b/test/Bitcode/binaryFloatInstructions.3.2.ll new file mode 100644 index 000000000000..f94d82d23c9f --- /dev/null +++ b/test/Bitcode/binaryFloatInstructions.3.2.ll @@ -0,0 +1,120 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s
+
+; BinaryFloatOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
+; The test checks that LLVM does not misread binary float instructions from
+; older bitcode files.
+
+define void @fadd(float %x1, double %x2 ,half %x3, fp128 %x4, x86_fp80 %x5, ppc_fp128 %x6){
+entry:
+; CHECK: %res1 = fadd float %x1, %x1
+ %res1 = fadd float %x1, %x1
+
+; CHECK-NEXT: %res2 = fadd double %x2, %x2
+ %res2 = fadd double %x2, %x2
+
+; CHECK-NEXT: %res3 = fadd half %x3, %x3
+ %res3 = fadd half %x3, %x3
+
+; CHECK-NEXT: %res4 = fadd fp128 %x4, %x4
+ %res4 = fadd fp128 %x4, %x4
+
+; CHECK-NEXT: %res5 = fadd x86_fp80 %x5, %x5
+ %res5 = fadd x86_fp80 %x5, %x5
+
+; CHECK-NEXT: %res6 = fadd ppc_fp128 %x6, %x6
+ %res6 = fadd ppc_fp128 %x6, %x6
+
+ ret void
+}
+
+define void @faddFloatVec(<2 x float> %x1, <3 x float> %x2 ,<4 x float> %x3, <8 x float> %x4, <16 x float> %x5){
+entry:
+; CHECK: %res1 = fadd <2 x float> %x1, %x1
+ %res1 = fadd <2 x float> %x1, %x1
+
+; CHECK-NEXT: %res2 = fadd <3 x float> %x2, %x2
+ %res2 = fadd <3 x float> %x2, %x2
+
+; CHECK-NEXT: %res3 = fadd <4 x float> %x3, %x3
+ %res3 = fadd <4 x float> %x3, %x3
+
+; CHECK-NEXT: %res4 = fadd <8 x float> %x4, %x4
+ %res4 = fadd <8 x float> %x4, %x4
+
+; CHECK-NEXT: %res5 = fadd <16 x float> %x5, %x5
+ %res5 = fadd <16 x float> %x5, %x5
+
+ ret void
+}
+
+define void @faddDoubleVec(<2 x double> %x1, <3 x double> %x2 ,<4 x double> %x3, <8 x double> %x4, <16 x double> %x5){
+entry:
+; CHECK: %res1 = fadd <2 x double> %x1, %x1
+ %res1 = fadd <2 x double> %x1, %x1
+
+; CHECK-NEXT: %res2 = fadd <3 x double> %x2, %x2
+ %res2 = fadd <3 x double> %x2, %x2
+
+; CHECK-NEXT: %res3 = fadd <4 x double> %x3, %x3
+ %res3 = fadd <4 x double> %x3, %x3
+
+; CHECK-NEXT: %res4 = fadd <8 x double> %x4, %x4
+ %res4 = fadd <8 x double> %x4, %x4
+
+; CHECK-NEXT: %res5 = fadd <16 x double> %x5, %x5
+ %res5 = fadd <16 x double> %x5, %x5
+
+ ret void
+}
+
+define void @faddHalfVec(<2 x half> %x1, <3 x half> %x2 ,<4 x half> %x3, <8 x half> %x4, <16 x half> %x5){
+entry:
+; CHECK: %res1 = fadd <2 x half> %x1, %x1
+ %res1 = fadd <2 x half> %x1, %x1
+
+; CHECK-NEXT: %res2 = fadd <3 x half> %x2, %x2
+ %res2 = fadd <3 x half> %x2, %x2
+
+; CHECK-NEXT: %res3 = fadd <4 x half> %x3, %x3
+ %res3 = fadd <4 x half> %x3, %x3
+
+; CHECK-NEXT: %res4 = fadd <8 x half> %x4, %x4
+ %res4 = fadd <8 x half> %x4, %x4
+
+; CHECK-NEXT: %res5 = fadd <16 x half> %x5, %x5
+ %res5 = fadd <16 x half> %x5, %x5
+
+ ret void
+}
+
+define void @fsub(float %x1){
+entry:
+; CHECK: %res1 = fsub float %x1, %x1
+ %res1 = fsub float %x1, %x1
+
+ ret void
+}
+
+define void @fmul(float %x1){
+entry:
+; CHECK: %res1 = fmul float %x1, %x1
+ %res1 = fmul float %x1, %x1
+
+ ret void
+}
+
+define void @fdiv(float %x1){
+entry:
+; CHECK: %res1 = fdiv float %x1, %x1
+ %res1 = fdiv float %x1, %x1
+
+ ret void
+}
+
+define void @frem(float %x1){
+entry:
+; CHECK: %res1 = frem float %x1, %x1
+ %res1 = frem float %x1, %x1
+
+ ret void
+}
diff --git a/test/Bitcode/binaryFloatInstructions.3.2.ll.bc b/test/Bitcode/binaryFloatInstructions.3.2.ll.bc Binary files differnew file mode 100644 index 000000000000..8dbb4e456a04 --- /dev/null +++ b/test/Bitcode/binaryFloatInstructions.3.2.ll.bc diff --git a/test/Bitcode/binaryIntInstructions.3.2.ll b/test/Bitcode/binaryIntInstructions.3.2.ll new file mode 100644 index 000000000000..b08501ca932a --- /dev/null +++ b/test/Bitcode/binaryIntInstructions.3.2.ll @@ -0,0 +1,177 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s
+
+; BinaryIntOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
+; The test checks that LLVM does not misread binary integer instructions from
+; older bitcode files.
+
+define void @add(i1 %x1, i8 %x2 ,i16 %x3, i32 %x4, i64 %x5){
+entry:
+; CHECK: %res1 = add i1 %x1, %x1
+ %res1 = add i1 %x1, %x1
+
+; CHECK-NEXT: %res2 = add i8 %x2, %x2
+ %res2 = add i8 %x2, %x2
+
+; CHECK-NEXT: %res3 = add i16 %x3, %x3
+ %res3 = add i16 %x3, %x3
+
+; CHECK-NEXT: %res4 = add i32 %x4, %x4
+ %res4 = add i32 %x4, %x4
+
+; CHECK-NEXT: %res5 = add i64 %x5, %x5
+ %res5 = add i64 %x5, %x5
+
+; CHECK: %res6 = add nuw i1 %x1, %x1
+ %res6 = add nuw i1 %x1, %x1
+
+; CHECK: %res7 = add nsw i1 %x1, %x1
+ %res7 = add nsw i1 %x1, %x1
+
+; CHECK: %res8 = add nuw nsw i1 %x1, %x1
+ %res8 = add nuw nsw i1 %x1, %x1
+
+ ret void
+}
+
+define void @addvec8NuwNsw(<2 x i8> %x1, <3 x i8> %x2 ,<4 x i8> %x3, <8 x i8> %x4, <16 x i8> %x5){
+entry:
+; CHECK: %res1 = add nuw nsw <2 x i8> %x1, %x1
+ %res1 = add nuw nsw <2 x i8> %x1, %x1
+
+; CHECK-NEXT: %res2 = add nuw nsw <3 x i8> %x2, %x2
+ %res2 = add nuw nsw <3 x i8> %x2, %x2
+
+; CHECK-NEXT: %res3 = add nuw nsw <4 x i8> %x3, %x3
+ %res3 = add nuw nsw <4 x i8> %x3, %x3
+
+; CHECK-NEXT: %res4 = add nuw nsw <8 x i8> %x4, %x4
+ %res4 = add nuw nsw <8 x i8> %x4, %x4
+
+; CHECK-NEXT: %res5 = add nuw nsw <16 x i8> %x5, %x5
+ %res5 = add nuw nsw <16 x i8> %x5, %x5
+
+ ret void
+}
+
+define void @addvec16NuwNsw(<2 x i16> %x1, <3 x i16> %x2 ,<4 x i16> %x3, <8 x i16> %x4, <16 x i16> %x5){
+entry:
+; CHECK: %res1 = add nuw nsw <2 x i16> %x1, %x1
+ %res1 = add nuw nsw <2 x i16> %x1, %x1
+
+; CHECK-NEXT: %res2 = add nuw nsw <3 x i16> %x2, %x2
+ %res2 = add nuw nsw <3 x i16> %x2, %x2
+
+; CHECK-NEXT: %res3 = add nuw nsw <4 x i16> %x3, %x3
+ %res3 = add nuw nsw <4 x i16> %x3, %x3
+
+; CHECK-NEXT: %res4 = add nuw nsw <8 x i16> %x4, %x4
+ %res4 = add nuw nsw <8 x i16> %x4, %x4
+
+; CHECK-NEXT: %res5 = add nuw nsw <16 x i16> %x5, %x5
+ %res5 = add nuw nsw <16 x i16> %x5, %x5
+
+ ret void
+}
+
+define void @addvec32NuwNsw(<2 x i32> %x1, <3 x i32> %x2 ,<4 x i32> %x3, <8 x i32> %x4, <16 x i32> %x5){
+entry:
+; CHECK: %res1 = add nuw nsw <2 x i32> %x1, %x1
+ %res1 = add nuw nsw <2 x i32> %x1, %x1
+
+; CHECK-NEXT: %res2 = add nuw nsw <3 x i32> %x2, %x2
+ %res2 = add nuw nsw <3 x i32> %x2, %x2
+
+; CHECK-NEXT: %res3 = add nuw nsw <4 x i32> %x3, %x3
+ %res3 = add nuw nsw <4 x i32> %x3, %x3
+
+; CHECK-NEXT: %res4 = add nuw nsw <8 x i32> %x4, %x4
+ %res4 = add nuw nsw <8 x i32> %x4, %x4
+
+; CHECK-NEXT: %res5 = add nuw nsw <16 x i32> %x5, %x5
+ %res5 = add nuw nsw <16 x i32> %x5, %x5
+
+ ret void
+}
+
+define void @addvec64NuwNsw(<2 x i64> %x1, <3 x i64> %x2 ,<4 x i64> %x3, <8 x i64> %x4, <16 x i64> %x5){
+entry:
+; CHECK: %res1 = add nuw nsw <2 x i64> %x1, %x1
+ %res1 = add nuw nsw <2 x i64> %x1, %x1
+
+; CHECK-NEXT: %res2 = add nuw nsw <3 x i64> %x2, %x2
+ %res2 = add nuw nsw <3 x i64> %x2, %x2
+
+; CHECK-NEXT: %res3 = add nuw nsw <4 x i64> %x3, %x3
+ %res3 = add nuw nsw <4 x i64> %x3, %x3
+
+; CHECK-NEXT: %res4 = add nuw nsw <8 x i64> %x4, %x4
+ %res4 = add nuw nsw <8 x i64> %x4, %x4
+
+; CHECK-NEXT: %res5 = add nuw nsw <16 x i64> %x5, %x5
+ %res5 = add nuw nsw <16 x i64> %x5, %x5
+
+ ret void
+}
+
+define void @sub(i8 %x1){
+entry:
+; CHECK: %res1 = sub i8 %x1, %x1
+ %res1 = sub i8 %x1, %x1
+
+; CHECK: %res2 = sub nuw i8 %x1, %x1
+ %res2 = sub nuw i8 %x1, %x1
+
+; CHECK: %res3 = sub nsw i8 %x1, %x1
+ %res3 = sub nsw i8 %x1, %x1
+
+; CHECK: %res4 = sub nuw nsw i8 %x1, %x1
+ %res4 = sub nuw nsw i8 %x1, %x1
+
+ ret void
+}
+
+define void @mul(i8 %x1){
+entry:
+; CHECK: %res1 = mul i8 %x1, %x1
+ %res1 = mul i8 %x1, %x1
+
+ ret void
+}
+
+define void @udiv(i8 %x1){
+entry:
+; CHECK: %res1 = udiv i8 %x1, %x1
+ %res1 = udiv i8 %x1, %x1
+
+; CHECK-NEXT: %res2 = udiv exact i8 %x1, %x1
+ %res2 = udiv exact i8 %x1, %x1
+
+ ret void
+}
+
+define void @sdiv(i8 %x1){
+entry:
+; CHECK: %res1 = sdiv i8 %x1, %x1
+ %res1 = sdiv i8 %x1, %x1
+
+; CHECK-NEXT: %res2 = sdiv exact i8 %x1, %x1
+ %res2 = sdiv exact i8 %x1, %x1
+
+ ret void
+}
+
+define void @urem(i32 %x1){
+entry:
+; CHECK: %res1 = urem i32 %x1, %x1
+ %res1 = urem i32 %x1, %x1
+
+ ret void
+}
+
+define void @srem(i32 %x1){
+entry:
+; CHECK: %res1 = srem i32 %x1, %x1
+ %res1 = srem i32 %x1, %x1
+
+ ret void
+}
diff --git a/test/Bitcode/binaryIntInstructions.3.2.ll.bc b/test/Bitcode/binaryIntInstructions.3.2.ll.bc Binary files differnew file mode 100644 index 000000000000..749e0c34dc84 --- /dev/null +++ b/test/Bitcode/binaryIntInstructions.3.2.ll.bc diff --git a/test/Bitcode/bitwiseInstructions.3.2.ll b/test/Bitcode/bitwiseInstructions.3.2.ll new file mode 100644 index 000000000000..6225a08f2064 --- /dev/null +++ b/test/Bitcode/bitwiseInstructions.3.2.ll @@ -0,0 +1,68 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s
+
+; bitwiseOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
+; The test checks that LLVM does not misread bitwise instructions from
+; older bitcode files.
+
+define void @shl(i8 %x1){
+entry:
+; CHECK: %res1 = shl i8 %x1, %x1
+ %res1 = shl i8 %x1, %x1
+
+; CHECK: %res2 = shl nuw i8 %x1, %x1
+ %res2 = shl nuw i8 %x1, %x1
+
+; CHECK: %res3 = shl nsw i8 %x1, %x1
+ %res3 = shl nsw i8 %x1, %x1
+
+; CHECK: %res4 = shl nuw nsw i8 %x1, %x1
+ %res4 = shl nuw nsw i8 %x1, %x1
+
+ ret void
+}
+
+define void @lshr(i8 %x1){
+entry:
+; CHECK: %res1 = lshr i8 %x1, %x1
+ %res1 = lshr i8 %x1, %x1
+
+; CHECK: %res2 = lshr exact i8 %x1, %x1
+ %res2 = lshr exact i8 %x1, %x1
+
+ ret void
+}
+
+define void @ashr(i8 %x1){
+entry:
+; CHECK: %res1 = ashr i8 %x1, %x1
+ %res1 = ashr i8 %x1, %x1
+
+; CHECK-NEXT: %res2 = ashr exact i8 %x1, %x1
+ %res2 = ashr exact i8 %x1, %x1
+
+ ret void
+}
+
+define void @and(i8 %x1){
+entry:
+; CHECK: %res1 = and i8 %x1, %x1
+ %res1 = and i8 %x1, %x1
+
+ ret void
+}
+
+define void @or(i8 %x1){
+entry:
+; CHECK: %res1 = or i8 %x1, %x1
+ %res1 = or i8 %x1, %x1
+
+ ret void
+}
+
+define void @xor(i8 %x1){
+entry:
+; CHECK: %res1 = xor i8 %x1, %x1
+ %res1 = xor i8 %x1, %x1
+
+ ret void
+}
\ No newline at end of file diff --git a/test/Bitcode/bitwiseInstructions.3.2.ll.bc b/test/Bitcode/bitwiseInstructions.3.2.ll.bc Binary files differnew file mode 100644 index 000000000000..136a7c9a0a2d --- /dev/null +++ b/test/Bitcode/bitwiseInstructions.3.2.ll.bc diff --git a/test/Bitcode/calling-conventions.3.2.ll b/test/Bitcode/calling-conventions.3.2.ll new file mode 100644 index 000000000000..aca9efd0892b --- /dev/null +++ b/test/Bitcode/calling-conventions.3.2.ll @@ -0,0 +1,150 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; calling-conventions.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not silently misread calling conventions of +; older bitcode files. + +declare ccc void @ccc() +; CHECK: declare void @ccc + +declare fastcc void @fastcc() +; CHECK: declare fastcc void @fastcc + +declare coldcc void @coldcc() +; CHECK: declare coldcc void @coldcc + +declare cc10 void @cc10() +; CHECK: declare cc10 void @cc10 + +declare spir_kernel void @spir_kernel() +; CHECK: declare spir_kernel void @spir_kernel + +declare spir_func void @spir_func() +; CHECK: declare spir_func void @spir_func + +declare intel_ocl_bicc void @intel_ocl_bicc() +; CHECK: declare intel_ocl_bicc void @intel_ocl_bicc + +declare x86_stdcallcc void @x86_stdcallcc() +; CHECK: declare x86_stdcallcc void @x86_stdcallcc + +declare x86_fastcallcc void @x86_fastcallcc() +; CHECK: declare x86_fastcallcc void @x86_fastcallcc + +declare x86_thiscallcc void @x86_thiscallcc() +; CHECK: declare x86_thiscallcc void @x86_thiscallcc + +declare arm_apcscc void @arm_apcscc() +; CHECK: declare arm_apcscc void @arm_apcscc + +declare arm_aapcscc void @arm_aapcscc() +; CHECK: declare arm_aapcscc void @arm_aapcscc + +declare arm_aapcs_vfpcc void @arm_aapcs_vfpcc() +; CHECK: declare arm_aapcs_vfpcc void @arm_aapcs_vfpcc + +declare msp430_intrcc void @msp430_intrcc() +; CHECK: declare msp430_intrcc void @msp430_intrcc + +declare ptx_kernel void @ptx_kernel() +; CHECK: declare ptx_kernel void @ptx_kernel + +declare ptx_device void @ptx_device() +; CHECK: declare ptx_device void @ptx_device + +define void @call_ccc() { +; CHECK: call void @ccc + call ccc void @ccc() + ret void +} + +define void @call_fastcc() { +; CHECK: call fastcc void @fastcc + call fastcc void @fastcc() + ret void +} + +define void @call_coldcc() { +; CHECK: call coldcc void @coldcc + call coldcc void @coldcc() + ret void +} + +define void @call_cc10 () { +; CHECK: call cc10 void @cc10 + call cc10 void @cc10 () + ret void +} + +define void @call_spir_kernel() { +; CHECK: call spir_kernel void @spir_kernel + call spir_kernel void @spir_kernel() + ret void +} + +define void @call_spir_func() { +; CHECK: call spir_func void @spir_func + call spir_func void @spir_func() + ret void +} + +define void @call_intel_ocl_bicc() { +; CHECK: call intel_ocl_bicc void @intel_ocl_bicc + call intel_ocl_bicc void @intel_ocl_bicc() + ret void +} + +define void @call_x86_stdcallcc() { +; CHECK: call x86_stdcallcc void @x86_stdcallcc + call x86_stdcallcc void @x86_stdcallcc() + ret void +} + +define void @call_x86_fastcallcc() { +; CHECK: call x86_fastcallcc void @x86_fastcallcc + call x86_fastcallcc void @x86_fastcallcc() + ret void +} + +define void @call_x86_thiscallcc() { +; CHECK: call x86_thiscallcc void @x86_thiscallcc + call x86_thiscallcc void @x86_thiscallcc() + ret void +} + +define void @call_arm_apcscc() { +; CHECK: call arm_apcscc void @arm_apcscc + call arm_apcscc void @arm_apcscc() + ret void +} + +define void @call_arm_aapcscc() { +; CHECK: call arm_aapcscc void @arm_aapcscc + call arm_aapcscc void @arm_aapcscc() + ret void +} + +define void @call_arm_aapcs_vfpcc() { +; CHECK: call arm_aapcs_vfpcc void @arm_aapcs_vfpcc + call arm_aapcs_vfpcc void @arm_aapcs_vfpcc() + ret void +} + +define void @call_msp430_intrcc() { +; CHECK: call msp430_intrcc void @msp430_intrcc + call msp430_intrcc void @msp430_intrcc() + ret void +} + +define void @call_ptx_kernel() { +; CHECK: call ptx_kernel void @ptx_kernel + call ptx_kernel void @ptx_kernel() + ret void +} + +define void @call_ptx_device() { +; CHECK: call ptx_device void @ptx_device + call ptx_device void @ptx_device() + ret void +} + diff --git a/test/Bitcode/calling-conventions.3.2.ll.bc b/test/Bitcode/calling-conventions.3.2.ll.bc Binary files differnew file mode 100644 index 000000000000..b3fad967db0e --- /dev/null +++ b/test/Bitcode/calling-conventions.3.2.ll.bc diff --git a/test/Bitcode/cmpxchg-upgrade.ll b/test/Bitcode/cmpxchg-upgrade.ll new file mode 100644 index 000000000000..d36ac1c17909 --- /dev/null +++ b/test/Bitcode/cmpxchg-upgrade.ll @@ -0,0 +1,23 @@ +; RUN: llvm-dis < %s.bc | FileCheck %s + +; cmpxchg-upgrade.ll.bc was produced by running a version of llvm-as from just +; before the IR change on this file. + +define void @test(i32* %addr) { + cmpxchg i32* %addr, i32 42, i32 0 monotonic +; CHECK: cmpxchg i32* %addr, i32 42, i32 0 monotonic monotonic + + cmpxchg i32* %addr, i32 42, i32 0 acquire +; CHECK: cmpxchg i32* %addr, i32 42, i32 0 acquire acquire + + cmpxchg i32* %addr, i32 42, i32 0 release +; CHECK: cmpxchg i32* %addr, i32 42, i32 0 release monotonic + + cmpxchg i32* %addr, i32 42, i32 0 acq_rel +; CHECK: cmpxchg i32* %addr, i32 42, i32 0 acq_rel acquire + + cmpxchg i32* %addr, i32 42, i32 0 seq_cst +; CHECK: cmpxchg i32* %addr, i32 42, i32 0 seq_cst seq_cst + + ret void +}
\ No newline at end of file diff --git a/test/Bitcode/cmpxchg-upgrade.ll.bc b/test/Bitcode/cmpxchg-upgrade.ll.bc Binary files differnew file mode 100644 index 000000000000..922f2eb84edf --- /dev/null +++ b/test/Bitcode/cmpxchg-upgrade.ll.bc diff --git a/test/Bitcode/conversionInstructions.3.2.ll b/test/Bitcode/conversionInstructions.3.2.ll new file mode 100644 index 000000000000..4b3f27386eff --- /dev/null +++ b/test/Bitcode/conversionInstructions.3.2.ll @@ -0,0 +1,104 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s
+
+; conversionOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
+; The test checks that LLVM does not misread conversion instructions from
+; older bitcode files.
+
+define void @trunc(i32 %src){
+entry:
+; CHECK: %res1 = trunc i32 %src to i8
+ %res1 = trunc i32 %src to i8
+
+ ret void
+}
+
+define void @zext(i32 %src){
+entry:
+; CHECK: %res1 = zext i32 %src to i64
+ %res1 = zext i32 %src to i64
+
+ ret void
+}
+
+define void @sext(i32 %src){
+entry:
+; CHECK: %res1 = sext i32 %src to i64
+ %res1 = sext i32 %src to i64
+
+ ret void
+}
+
+define void @fptrunc(double %src){
+entry:
+; CHECK: %res1 = fptrunc double %src to float
+ %res1 = fptrunc double %src to float
+
+ ret void
+}
+
+define void @fpext(float %src){
+entry:
+; CHECK: %res1 = fpext float %src to double
+ %res1 = fpext float %src to double
+
+ ret void
+}
+
+define void @fptoui(float %src){
+entry:
+; CHECK: %res1 = fptoui float %src to i32
+ %res1 = fptoui float %src to i32
+
+ ret void
+}
+
+define void @fptosi(float %src){
+entry:
+; CHECK: %res1 = fptosi float %src to i32
+ %res1 = fptosi float %src to i32
+
+ ret void
+}
+
+define void @uitofp(i32 %src){
+entry:
+; CHECK: %res1 = uitofp i32 %src to float
+ %res1 = uitofp i32 %src to float
+
+ ret void
+}
+
+define void @sitofp(i32 %src){
+entry:
+; CHECK: %res1 = sitofp i32 %src to float
+ %res1 = sitofp i32 %src to float
+
+ ret void
+}
+
+define void @ptrtoint(i32* %src){
+entry:
+; CHECK: %res1 = ptrtoint i32* %src to i8
+ %res1 = ptrtoint i32* %src to i8
+
+ ret void
+}
+
+define void @inttoptr(i32 %src){
+entry:
+; CHECK: %res1 = inttoptr i32 %src to i32*
+ %res1 = inttoptr i32 %src to i32*
+
+ ret void
+}
+
+define void @bitcast(i32 %src1, i32* %src2){
+entry:
+; CHECK: %res1 = bitcast i32 %src1 to i32
+ %res1 = bitcast i32 %src1 to i32
+
+; CHECK: %res2 = bitcast i32* %src2 to i64*
+ %res2 = bitcast i32* %src2 to i64*
+
+ ret void
+}
\ No newline at end of file diff --git a/test/Bitcode/conversionInstructions.3.2.ll.bc b/test/Bitcode/conversionInstructions.3.2.ll.bc Binary files differnew file mode 100644 index 000000000000..fabf7dab6fb8 --- /dev/null +++ b/test/Bitcode/conversionInstructions.3.2.ll.bc diff --git a/test/Bitcode/deprecated-linker_private-linker_private_weak.ll b/test/Bitcode/deprecated-linker_private-linker_private_weak.ll new file mode 100644 index 000000000000..12a527c7738f --- /dev/null +++ b/test/Bitcode/deprecated-linker_private-linker_private_weak.ll @@ -0,0 +1,17 @@ +; RUN: llvm-as -o - %s | llvm-dis | FileCheck %s +; RUN: llvm-as -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-WARNINGS + +@.linker_private = linker_private unnamed_addr constant [15 x i8] c"linker_private\00", align 64 +@.linker_private_weak = linker_private_weak unnamed_addr constant [20 x i8] c"linker_private_weak\00", align 64 + +; CHECK: @.linker_private = private unnamed_addr constant [15 x i8] c"linker_private\00", align 64 +; CHECK: @.linker_private_weak = private unnamed_addr constant [20 x i8] c"linker_private_weak\00", align 64 + +; CHECK-WARNINGS: warning: '.linker_private' is deprecated, treating as PrivateLinkage +; CHECK-WARNINGS: @.linker_private = linker_private unnamed_addr constant [15 x i8] c"linker_private\00", align 64 +; CHECK-WARNINGS: ^ + +; CHECK-WARNINGS: warning: '.linker_private_weak' is deprecated, treating as PrivateLinkage +; CHECK-WARNINGS: @.linker_private_weak = linker_private_weak unnamed_addr constant [20 x i8] c"linker_private_weak\00", align 64 +; CHECK-WARNINGS: ^ + diff --git a/test/Bitcode/drop-debug-info.ll b/test/Bitcode/drop-debug-info.ll index da4ae0c541eb..5123018577ee 100644 --- a/test/Bitcode/drop-debug-info.ll +++ b/test/Bitcode/drop-debug-info.ll @@ -1,4 +1,5 @@ -; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; RUN: llvm-as < %s -o %t.bc 2>&1 >/dev/null | FileCheck -check-prefix=WARN %s +; RUN: llvm-dis < %t.bc | FileCheck %s define i32 @main() { entry: @@ -22,5 +23,6 @@ entry: !9 = metadata !{i32 2, metadata !"Dwarf Version", i32 2} !12 = metadata !{i32 4, i32 0, metadata !4, null} +; WARN: warning: ignoring debug info with an invalid version (0) ; CHECK-NOT: !dbg ; CHECK-NOT: !llvm.dbg.cu diff --git a/test/Bitcode/global-variables.3.2.ll b/test/Bitcode/global-variables.3.2.ll new file mode 100644 index 000000000000..549d025549be --- /dev/null +++ b/test/Bitcode/global-variables.3.2.ll @@ -0,0 +1,41 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; global-variables.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not silently misread global variables attributes of +; older bitcode files. + +@global.var = global i32 1 +; CHECK: @global.var = global i32 1 + +@constant.var = constant i32 1 +; CHECK: @constant.var = constant i32 1 + +@noinit.var = global float undef +; CHECK: @noinit.var = global float undef + +@section.var = global i32 1, section "foo" +; CHECK: @section.var = global i32 1, section "foo" + +@align.var = global i64 undef, align 8 +; CHECK: @align.var = global i64 undef, align 8 + +@unnamed_addr.var = unnamed_addr global i8 1 +; CHECK: @unnamed_addr.var = unnamed_addr global i8 1 + +@default_addrspace.var = addrspace(0) global i8 1 +; CHECK: @default_addrspace.var = global i8 1 + +@non_default_addrspace.var = addrspace(1) global i8* undef +; CHECK: @non_default_addrspace.var = addrspace(1) global i8* undef + +@initialexec.var = thread_local(initialexec) global i32 0, align 4 +; CHECK: @initialexec.var = thread_local(initialexec) global i32 0, align 4 + +@localdynamic.var = thread_local(localdynamic) constant i32 0, align 4 +; CHECK: @localdynamic.var = thread_local(localdynamic) constant i32 0, align 4 + +@localexec.var = thread_local(localexec) constant i32 0, align 4 +; CHECK: @localexec.var = thread_local(localexec) constant i32 0, align 4 + +@string.var = private unnamed_addr constant [13 x i8] c"hello world\0A\00" +; CHECK: @string.var = private unnamed_addr constant [13 x i8] c"hello world\0A\00" diff --git a/test/Bitcode/global-variables.3.2.ll.bc b/test/Bitcode/global-variables.3.2.ll.bc Binary files differnew file mode 100644 index 000000000000..c105f2fb1831 --- /dev/null +++ b/test/Bitcode/global-variables.3.2.ll.bc diff --git a/test/Bitcode/inalloca.ll b/test/Bitcode/inalloca.ll new file mode 100644 index 000000000000..bad87a9b03f0 --- /dev/null +++ b/test/Bitcode/inalloca.ll @@ -0,0 +1,18 @@ +; RUN: llvm-as < %s | llvm-dis | FileCheck %s + +; inalloca should roundtrip. + +define void @foo(i32* inalloca %args) { + ret void +} +; CHECK-LABEL: define void @foo(i32* inalloca %args) + +define void @bar() { + ; Use the maximum alignment, since we stuff our bit with alignment. + %args = alloca inalloca i32, align 536870912 + call void @foo(i32* inalloca %args) + ret void +} +; CHECK-LABEL: define void @bar() { +; CHECK: %args = alloca inalloca i32, align 536870912 +; CHECK: call void @foo(i32* inalloca %args) diff --git a/test/Bitcode/linkage-types-3.2.ll b/test/Bitcode/linkage-types-3.2.ll new file mode 100644 index 000000000000..fd070efbd444 --- /dev/null +++ b/test/Bitcode/linkage-types-3.2.ll @@ -0,0 +1,128 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; linkage-types-3.2.ll.bc was generated by passing this file to llvm-as-3.2 +; The test checks that LLVM does not silently misread linkage types of +; older bitcode files. + +@common.var = common global i32 0 +; CHECK: @common.var = common global i32 0 + +@appending.var = appending global [8 x i32] undef +; CHECK: @appending.var = appending global [8 x i32] undef + +@extern_weak.var = extern_weak global i32 +; CHECK: @extern_weak.var = extern_weak global i32 + +@private.var = private constant i32 0 +; CHECK: @private.var = private constant i32 0 + +@linker_private.var = linker_private constant i32 0 +; CHECK: @linker_private.var = private constant i32 0 + +@linker_private_weak.var = linker_private_weak constant i32 0 +; CHECK: @linker_private_weak.var = private constant i32 0 + +@linker_private_weak_def_auto.var = linker_private_weak_def_auto constant i32 0 +; CHECK: @linker_private_weak_def_auto.var = constant i32 0 + +@internal.var = internal constant i32 0 +; CHECK: @internal.var = internal constant i32 0 + +@available_externally.var = available_externally constant i32 0 +; CHECK: @available_externally.var = available_externally constant i32 0 + +@linkonce.var = linkonce constant i32 0 +; CHECK: @linkonce.var = linkonce constant i32 0 + +@weak.var = weak constant i32 0 +; CHECK: @weak.var = weak constant i32 0 + +@linkonce_odr.var = linkonce_odr constant i32 0 +; CHECK: @linkonce_odr.var = linkonce_odr constant i32 0 + +@linkonce_odr_auto_hide.var = linkonce_odr_auto_hide constant i32 0 +; CHECK: @linkonce_odr_auto_hide.var = constant i32 0 + +@external.var = external constant i32 +; CHECK: @external.var = external constant i32 + +@dllexport.var = dllexport global i32 0 +; CHECK: @dllexport.var = dllexport global i32 0 + +@dllimport.var = dllimport global i32 +; CHECK: @dllimport.var = external dllimport global i32 + +define private void @private() +; CHECK: define private void @private +{ + ret void; +} + +define linker_private void @linker_private() +; CHECK: define private void @linker_private +{ + ret void; +} + +define linker_private_weak void @linker_private_weak() +; CHECK: define private void @linker_private_weak +{ + ret void; +} + +define linker_private_weak_def_auto void @linker_private_weak_def_auto() +; CHECK: define void @linker_private_weak_def_auto +{ + ret void; +} + +define internal void @internal() +; CHECK: define internal void @internal +{ + ret void; +} + +define available_externally void @available_externally() +; CHECK: define available_externally void @available_externally +{ + ret void; +} + +define linkonce void @linkonce() +; CHECK: define linkonce void @linkonce +{ + ret void; +} + +define weak void @weak() +; CHECK: define weak void @weak +{ + ret void; +} + +define linkonce_odr void @linkonce_odr() +; CHECK: define linkonce_odr void @linkonce_odr +{ + ret void; +} + +define linkonce_odr_auto_hide void @linkonce_odr_auto_hide() +; CHECK: define void @linkonce_odr_auto_hide +{ + ret void; +} + +define external void @external() +; CHECK: define void @external +{ + ret void; +} + +declare dllimport void @dllimport() +; CHECK: declare dllimport void @dllimport + +define dllexport void @dllexport() +; CHECK: define dllexport void @dllexport() +{ + ret void; +} diff --git a/test/Bitcode/linkage-types-3.2.ll.bc b/test/Bitcode/linkage-types-3.2.ll.bc Binary files differnew file mode 100644 index 000000000000..c856ddf7aa7b --- /dev/null +++ b/test/Bitcode/linkage-types-3.2.ll.bc diff --git a/test/Bitcode/local-linkage-default-visibility.3.4.ll b/test/Bitcode/local-linkage-default-visibility.3.4.ll new file mode 100644 index 000000000000..45a7b1213a8c --- /dev/null +++ b/test/Bitcode/local-linkage-default-visibility.3.4.ll @@ -0,0 +1,79 @@ +; RUN: llvm-dis < %s.bc | FileCheck %s + +; local-linkage-default-visibility.3.4.ll.bc was generated by passing this file +; to llvm-as-3.4. The test checks that LLVM upgrades visibility of symbols +; with local linkage to default visibility. + +@default.internal.var = internal global i32 0 +; CHECK: @default.internal.var = internal global i32 0 + +@hidden.internal.var = internal hidden global i32 0 +; CHECK: @hidden.internal.var = internal global i32 0 + +@protected.internal.var = internal protected global i32 0 +; CHECK: @protected.internal.var = internal global i32 0 + +@default.private.var = private global i32 0 +; CHECK: @default.private.var = private global i32 0 + +@hidden.private.var = private hidden global i32 0 +; CHECK: @hidden.private.var = private global i32 0 + +@protected.private.var = private protected global i32 0 +; CHECK: @protected.private.var = private global i32 0 + +@global = global i32 0 + +@default.internal.alias = alias internal i32* @global +; CHECK: @default.internal.alias = alias internal i32* @global + +@hidden.internal.alias = hidden alias internal i32* @global +; CHECK: @hidden.internal.alias = alias internal i32* @global + +@protected.internal.alias = protected alias internal i32* @global +; CHECK: @protected.internal.alias = alias internal i32* @global + +@default.private.alias = alias private i32* @global +; CHECK: @default.private.alias = alias private i32* @global + +@hidden.private.alias = hidden alias private i32* @global +; CHECK: @hidden.private.alias = alias private i32* @global + +@protected.private.alias = protected alias private i32* @global +; CHECK: @protected.private.alias = alias private i32* @global + +define internal void @default.internal() { +; CHECK: define internal void @default.internal +entry: + ret void +} + +define internal hidden void @hidden.internal() { +; CHECK: define internal void @hidden.internal +entry: + ret void +} + +define internal protected void @protected.internal() { +; CHECK: define internal void @protected.internal +entry: + ret void +} + +define private void @default.private() { +; CHECK: define private void @default.private +entry: + ret void +} + +define private hidden void @hidden.private() { +; CHECK: define private void @hidden.private +entry: + ret void +} + +define private protected void @protected.private() { +; CHECK: define private void @protected.private +entry: + ret void +} diff --git a/test/Bitcode/local-linkage-default-visibility.3.4.ll.bc b/test/Bitcode/local-linkage-default-visibility.3.4.ll.bc Binary files differnew file mode 100644 index 000000000000..6e49f7e365b7 --- /dev/null +++ b/test/Bitcode/local-linkage-default-visibility.3.4.ll.bc diff --git a/test/Bitcode/memInstructions.3.2.ll b/test/Bitcode/memInstructions.3.2.ll new file mode 100644 index 000000000000..e4cb6bdbe96b --- /dev/null +++ b/test/Bitcode/memInstructions.3.2.ll @@ -0,0 +1,328 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s
+
+; memOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
+; The test checks that LLVM does not misread memory related instructions of
+; older bitcode files.
+
+define void @alloca(){
+entry:
+; CHECK: %res1 = alloca i8
+ %res1 = alloca i8
+
+; CHECK-NEXT: %res2 = alloca i8, i32 2
+ %res2 = alloca i8, i32 2
+
+; CHECK-NEXT: %res3 = alloca i8, i32 2, align 4
+ %res3 = alloca i8, i32 2, align 4
+
+; CHECK-NEXT: %res4 = alloca i8, align 4
+ %res4 = alloca i8, align 4
+
+ ret void
+}
+
+define void @load(){
+entry:
+ %ptr1 = alloca i8
+ store i8 2, i8* %ptr1
+
+; CHECK: %res1 = load i8* %ptr1
+ %res1 = load i8* %ptr1
+
+; CHECK-NEXT: %res2 = load volatile i8* %ptr1
+ %res2 = load volatile i8* %ptr1
+
+; CHECK-NEXT: %res3 = load i8* %ptr1, align 1
+ %res3 = load i8* %ptr1, align 1
+
+; CHECK-NEXT: %res4 = load volatile i8* %ptr1, align 1
+ %res4 = load volatile i8* %ptr1, align 1
+
+; CHECK-NEXT: %res5 = load i8* %ptr1, !nontemporal !0
+ %res5 = load i8* %ptr1, !nontemporal !0
+
+; CHECK-NEXT: %res6 = load volatile i8* %ptr1, !nontemporal !0
+ %res6 = load volatile i8* %ptr1, !nontemporal !0
+
+; CHECK-NEXT: %res7 = load i8* %ptr1, align 1, !nontemporal !0
+ %res7 = load i8* %ptr1, align 1, !nontemporal !0
+
+; CHECK-NEXT: %res8 = load volatile i8* %ptr1, align 1, !nontemporal !0
+ %res8 = load volatile i8* %ptr1, align 1, !nontemporal !0
+
+; CHECK-NEXT: %res9 = load i8* %ptr1, !invariant.load !1
+ %res9 = load i8* %ptr1, !invariant.load !1
+
+; CHECK-NEXT: %res10 = load volatile i8* %ptr1, !invariant.load !1
+ %res10 = load volatile i8* %ptr1, !invariant.load !1
+
+; CHECK-NEXT: %res11 = load i8* %ptr1, align 1, !invariant.load !1
+ %res11 = load i8* %ptr1, align 1, !invariant.load !1
+
+; CHECK-NEXT: %res12 = load volatile i8* %ptr1, align 1, !invariant.load !1
+ %res12 = load volatile i8* %ptr1, align 1, !invariant.load !1
+
+; CHECK-NEXT: %res13 = load i8* %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
+ %res13 = load i8* %ptr1, !nontemporal !0, !invariant.load !1
+
+; CHECK-NEXT: %res14 = load volatile i8* %ptr1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
+ %res14 = load volatile i8* %ptr1, !nontemporal !0, !invariant.load !1
+
+; CHECK-NEXT: %res15 = load i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
+ %res15 = load i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
+
+; CHECK-NEXT: %res16 = load volatile i8* %ptr1, align 1, {{[(!nontemporal !0, !invariant.load !1) | (!invariant.load !1, !nontemporal !0)]}}
+ %res16 = load volatile i8* %ptr1, align 1, !nontemporal !0, !invariant.load !1
+
+ ret void
+}
+
+define void @loadAtomic(){
+entry:
+ %ptr1 = alloca i8
+ store i8 2, i8* %ptr1
+
+; CHECK: %res1 = load atomic i8* %ptr1 unordered, align 1
+ %res1 = load atomic i8* %ptr1 unordered, align 1
+
+; CHECK-NEXT: %res2 = load atomic i8* %ptr1 monotonic, align 1
+ %res2 = load atomic i8* %ptr1 monotonic, align 1
+
+; CHECK-NEXT: %res3 = load atomic i8* %ptr1 acquire, align 1
+ %res3 = load atomic i8* %ptr1 acquire, align 1
+
+; CHECK-NEXT: %res4 = load atomic i8* %ptr1 seq_cst, align 1
+ %res4 = load atomic i8* %ptr1 seq_cst, align 1
+
+; CHECK-NEXT: %res5 = load atomic volatile i8* %ptr1 unordered, align 1
+ %res5 = load atomic volatile i8* %ptr1 unordered, align 1
+
+; CHECK-NEXT: %res6 = load atomic volatile i8* %ptr1 monotonic, align 1
+ %res6 = load atomic volatile i8* %ptr1 monotonic, align 1
+
+; CHECK-NEXT: %res7 = load atomic volatile i8* %ptr1 acquire, align 1
+ %res7 = load atomic volatile i8* %ptr1 acquire, align 1
+
+; CHECK-NEXT: %res8 = load atomic volatile i8* %ptr1 seq_cst, align 1
+ %res8 = load atomic volatile i8* %ptr1 seq_cst, align 1
+
+; CHECK-NEXT: %res9 = load atomic i8* %ptr1 singlethread unordered, align 1
+ %res9 = load atomic i8* %ptr1 singlethread unordered, align 1
+
+; CHECK-NEXT: %res10 = load atomic i8* %ptr1 singlethread monotonic, align 1
+ %res10 = load atomic i8* %ptr1 singlethread monotonic, align 1
+
+; CHECK-NEXT: %res11 = load atomic i8* %ptr1 singlethread acquire, align 1
+ %res11 = load atomic i8* %ptr1 singlethread acquire, align 1
+
+; CHECK-NEXT: %res12 = load atomic i8* %ptr1 singlethread seq_cst, align 1
+ %res12 = load atomic i8* %ptr1 singlethread seq_cst, align 1
+
+; CHECK-NEXT: %res13 = load atomic volatile i8* %ptr1 singlethread unordered, align 1
+ %res13 = load atomic volatile i8* %ptr1 singlethread unordered, align 1
+
+; CHECK-NEXT: %res14 = load atomic volatile i8* %ptr1 singlethread monotonic, align 1
+ %res14 = load atomic volatile i8* %ptr1 singlethread monotonic, align 1
+
+; CHECK-NEXT: %res15 = load atomic volatile i8* %ptr1 singlethread acquire, align 1
+ %res15 = load atomic volatile i8* %ptr1 singlethread acquire, align 1
+
+; CHECK-NEXT: %res16 = load atomic volatile i8* %ptr1 singlethread seq_cst, align 1
+ %res16 = load atomic volatile i8* %ptr1 singlethread seq_cst, align 1
+
+ ret void
+}
+
+define void @store(){
+entry:
+ %ptr1 = alloca i8
+
+; CHECK: store i8 2, i8* %ptr1
+ store i8 2, i8* %ptr1
+
+; CHECK-NEXT: store volatile i8 2, i8* %ptr1
+ store volatile i8 2, i8* %ptr1
+
+; CHECK-NEXT: store i8 2, i8* %ptr1, align 1
+ store i8 2, i8* %ptr1, align 1
+
+; CHECK-NEXT: store volatile i8 2, i8* %ptr1, align 1
+ store volatile i8 2, i8* %ptr1, align 1
+
+; CHECK-NEXT: store i8 2, i8* %ptr1, !nontemporal !0
+ store i8 2, i8* %ptr1, !nontemporal !0
+
+; CHECK-NEXT: store volatile i8 2, i8* %ptr1, !nontemporal !0
+ store volatile i8 2, i8* %ptr1, !nontemporal !0
+
+; CHECK-NEXT: store i8 2, i8* %ptr1, align 1, !nontemporal !0
+ store i8 2, i8* %ptr1, align 1, !nontemporal !0
+
+; CHECK-NEXT: store volatile i8 2, i8* %ptr1, align 1, !nontemporal !0
+ store volatile i8 2, i8* %ptr1, align 1, !nontemporal !0
+
+ ret void
+}
+
+define void @storeAtomic(){
+entry:
+ %ptr1 = alloca i8
+
+; CHECK: store atomic i8 2, i8* %ptr1 unordered, align 1
+ store atomic i8 2, i8* %ptr1 unordered, align 1
+
+; CHECK-NEXT: store atomic i8 2, i8* %ptr1 monotonic, align 1
+ store atomic i8 2, i8* %ptr1 monotonic, align 1
+
+; CHECK-NEXT: store atomic i8 2, i8* %ptr1 release, align 1
+ store atomic i8 2, i8* %ptr1 release, align 1
+
+; CHECK-NEXT: store atomic i8 2, i8* %ptr1 seq_cst, align 1
+ store atomic i8 2, i8* %ptr1 seq_cst, align 1
+
+; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 unordered, align 1
+ store atomic volatile i8 2, i8* %ptr1 unordered, align 1
+
+; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 monotonic, align 1
+ store atomic volatile i8 2, i8* %ptr1 monotonic, align 1
+
+; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 release, align 1
+ store atomic volatile i8 2, i8* %ptr1 release, align 1
+
+; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 seq_cst, align 1
+ store atomic volatile i8 2, i8* %ptr1 seq_cst, align 1
+
+; CHECK-NEXT: store atomic i8 2, i8* %ptr1 singlethread unordered, align 1
+ store atomic i8 2, i8* %ptr1 singlethread unordered, align 1
+
+; CHECK-NEXT: store atomic i8 2, i8* %ptr1 singlethread monotonic, align 1
+ store atomic i8 2, i8* %ptr1 singlethread monotonic, align 1
+
+; CHECK-NEXT: store atomic i8 2, i8* %ptr1 singlethread release, align 1
+ store atomic i8 2, i8* %ptr1 singlethread release, align 1
+
+; CHECK-NEXT: store atomic i8 2, i8* %ptr1 singlethread seq_cst, align 1
+ store atomic i8 2, i8* %ptr1 singlethread seq_cst, align 1
+
+; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 singlethread unordered, align 1
+ store atomic volatile i8 2, i8* %ptr1 singlethread unordered, align 1
+
+; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 singlethread monotonic, align 1
+ store atomic volatile i8 2, i8* %ptr1 singlethread monotonic, align 1
+
+; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 singlethread release, align 1
+ store atomic volatile i8 2, i8* %ptr1 singlethread release, align 1
+
+; CHECK-NEXT: store atomic volatile i8 2, i8* %ptr1 singlethread seq_cst, align 1
+ store atomic volatile i8 2, i8* %ptr1 singlethread seq_cst, align 1
+
+ ret void
+}
+
+define void @cmpxchg(i32* %ptr,i32 %cmp,i32 %new){
+entry:
+ ;cmpxchg [volatile] <ty>* <pointer>, <ty> <cmp>, <ty> <new> [singlethread] <ordering>
+
+; CHECK: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new monotonic monotonic
+; CHECK-NEXT: %res1 = extractvalue { i32, i1 } [[TMP]], 0
+ %res1 = cmpxchg i32* %ptr, i32 %cmp, i32 %new monotonic monotonic
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new monotonic monotonic
+; CHECK-NEXT: %res2 = extractvalue { i32, i1 } [[TMP]], 0
+ %res2 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new monotonic monotonic
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread monotonic monotonic
+; CHECK-NEXT: %res3 = extractvalue { i32, i1 } [[TMP]], 0
+ %res3 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread monotonic monotonic
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread monotonic monotonic
+; CHECK-NEXT: %res4 = extractvalue { i32, i1 } [[TMP]], 0
+ %res4 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread monotonic monotonic
+
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new acquire acquire
+; CHECK-NEXT: %res5 = extractvalue { i32, i1 } [[TMP]], 0
+ %res5 = cmpxchg i32* %ptr, i32 %cmp, i32 %new acquire acquire
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acquire acquire
+; CHECK-NEXT: %res6 = extractvalue { i32, i1 } [[TMP]], 0
+ %res6 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acquire acquire
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acquire acquire
+; CHECK-NEXT: %res7 = extractvalue { i32, i1 } [[TMP]], 0
+ %res7 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acquire acquire
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acquire acquire
+; CHECK-NEXT: %res8 = extractvalue { i32, i1 } [[TMP]], 0
+ %res8 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acquire acquire
+
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new release monotonic
+; CHECK-NEXT: %res9 = extractvalue { i32, i1 } [[TMP]], 0
+ %res9 = cmpxchg i32* %ptr, i32 %cmp, i32 %new release monotonic
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new release monotonic
+; CHECK-NEXT: %res10 = extractvalue { i32, i1 } [[TMP]], 0
+ %res10 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new release monotonic
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread release monotonic
+; CHECK-NEXT: %res11 = extractvalue { i32, i1 } [[TMP]], 0
+ %res11 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread release monotonic
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread release monotonic
+; CHECK-NEXT: %res12 = extractvalue { i32, i1 } [[TMP]], 0
+ %res12 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread release monotonic
+
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
+; CHECK-NEXT: %res13 = extractvalue { i32, i1 } [[TMP]], 0
+ %res13 = cmpxchg i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
+; CHECK-NEXT: %res14 = extractvalue { i32, i1 } [[TMP]], 0
+ %res14 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new acq_rel acquire
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
+; CHECK-NEXT: %res15 = extractvalue { i32, i1 } [[TMP]], 0
+ %res15 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
+; CHECK-NEXT: %res16 = extractvalue { i32, i1 } [[TMP]], 0
+ %res16 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread acq_rel acquire
+
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst
+; CHECK-NEXT: %res17 = extractvalue { i32, i1 } [[TMP]], 0
+ %res17 = cmpxchg i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst
+; CHECK-NEXT: %res18 = extractvalue { i32, i1 } [[TMP]], 0
+ %res18 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread seq_cst seq_cst
+; CHECK-NEXT: %res19 = extractvalue { i32, i1 } [[TMP]], 0
+ %res19 = cmpxchg i32* %ptr, i32 %cmp, i32 %new singlethread seq_cst seq_cst
+
+; CHECK-NEXT: [[TMP:%[a-z0-9]+]] = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread seq_cst seq_cst
+; CHECK-NEXT: %res20 = extractvalue { i32, i1 } [[TMP]], 0
+ %res20 = cmpxchg volatile i32* %ptr, i32 %cmp, i32 %new singlethread seq_cst seq_cst
+
+ ret void
+}
+
+define void @getelementptr({i8, i8}* %s, <4 x i8*> %ptrs, <4 x i64> %offsets ){
+entry:
+; CHECK: %res1 = getelementptr { i8, i8 }* %s, i32 1, i32 1
+ %res1 = getelementptr {i8, i8}* %s, i32 1, i32 1
+
+; CHECK-NEXT: %res2 = getelementptr inbounds { i8, i8 }* %s, i32 1, i32 1
+ %res2 = getelementptr inbounds {i8, i8}* %s, i32 1, i32 1
+
+; CHECK-NEXT: %res3 = getelementptr <4 x i8*> %ptrs, <4 x i64> %offsets
+ %res3 = getelementptr <4 x i8*> %ptrs, <4 x i64> %offsets
+
+ ret void
+}
+
+!0 = metadata !{ i32 1 }
+!1 = metadata !{}
\ No newline at end of file diff --git a/test/Bitcode/memInstructions.3.2.ll.bc b/test/Bitcode/memInstructions.3.2.ll.bc Binary files differnew file mode 100644 index 000000000000..d75954a301b6 --- /dev/null +++ b/test/Bitcode/memInstructions.3.2.ll.bc diff --git a/test/Bitcode/miscInstructions.3.2.ll b/test/Bitcode/miscInstructions.3.2.ll new file mode 100644 index 000000000000..bceae20109c3 --- /dev/null +++ b/test/Bitcode/miscInstructions.3.2.ll @@ -0,0 +1,126 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s
+
+; miscInstructions.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
+; The test checks that LLVM does not misread miscellaneous instructions of
+; older bitcode files.
+
+define void @icmp(i32 %x1, i32 %x2, i32* %ptr1, i32* %ptr2, <2 x i32> %vec1, <2 x i32> %vec2){
+entry:
+; CHECK: %res1 = icmp eq i32 %x1, %x2
+ %res1 = icmp eq i32 %x1, %x2
+
+; CHECK-NEXT: %res2 = icmp ne i32 %x1, %x2
+ %res2 = icmp ne i32 %x1, %x2
+
+; CHECK-NEXT: %res3 = icmp ugt i32 %x1, %x2
+ %res3 = icmp ugt i32 %x1, %x2
+
+; CHECK-NEXT: %res4 = icmp uge i32 %x1, %x2
+ %res4 = icmp uge i32 %x1, %x2
+
+; CHECK-NEXT: %res5 = icmp ult i32 %x1, %x2
+ %res5 = icmp ult i32 %x1, %x2
+
+; CHECK-NEXT: %res6 = icmp ule i32 %x1, %x2
+ %res6 = icmp ule i32 %x1, %x2
+
+; CHECK-NEXT: %res7 = icmp sgt i32 %x1, %x2
+ %res7 = icmp sgt i32 %x1, %x2
+
+; CHECK-NEXT: %res8 = icmp sge i32 %x1, %x2
+ %res8 = icmp sge i32 %x1, %x2
+
+; CHECK-NEXT: %res9 = icmp slt i32 %x1, %x2
+ %res9 = icmp slt i32 %x1, %x2
+
+; CHECK-NEXT: %res10 = icmp sle i32 %x1, %x2
+ %res10 = icmp sle i32 %x1, %x2
+
+; CHECK-NEXT: %res11 = icmp eq i32* %ptr1, %ptr2
+ %res11 = icmp eq i32* %ptr1, %ptr2
+
+; CHECK-NEXT: %res12 = icmp eq <2 x i32> %vec1, %vec2
+ %res12 = icmp eq <2 x i32> %vec1, %vec2
+
+ ret void
+}
+
+
+define void @fcmp(float %x1, float %x2, <2 x float> %vec1, <2 x float> %vec2){
+entry:
+; CHECK: %res1 = fcmp oeq float %x1, %x2
+ %res1 = fcmp oeq float %x1, %x2
+
+; CHECK-NEXT: %res2 = fcmp one float %x1, %x2
+ %res2 = fcmp one float %x1, %x2
+
+; CHECK-NEXT: %res3 = fcmp ugt float %x1, %x2
+ %res3 = fcmp ugt float %x1, %x2
+
+; CHECK-NEXT: %res4 = fcmp uge float %x1, %x2
+ %res4 = fcmp uge float %x1, %x2
+
+; CHECK-NEXT: %res5 = fcmp ult float %x1, %x2
+ %res5 = fcmp ult float %x1, %x2
+
+; CHECK-NEXT: %res6 = fcmp ule float %x1, %x2
+ %res6 = fcmp ule float %x1, %x2
+
+; CHECK-NEXT: %res7 = fcmp ogt float %x1, %x2
+ %res7 = fcmp ogt float %x1, %x2
+
+; CHECK-NEXT: %res8 = fcmp oge float %x1, %x2
+ %res8 = fcmp oge float %x1, %x2
+
+; CHECK-NEXT: %res9 = fcmp olt float %x1, %x2
+ %res9 = fcmp olt float %x1, %x2
+
+; CHECK-NEXT: %res10 = fcmp ole float %x1, %x2
+ %res10 = fcmp ole float %x1, %x2
+
+; CHECK-NEXT: %res11 = fcmp ord float %x1, %x2
+ %res11 = fcmp ord float %x1, %x2
+
+; CHECK-NEXT: %res12 = fcmp ueq float %x1, %x2
+ %res12 = fcmp ueq float %x1, %x2
+
+; CHECK-NEXT: %res13 = fcmp une float %x1, %x2
+ %res13 = fcmp une float %x1, %x2
+
+; CHECK-NEXT: %res14 = fcmp uno float %x1, %x2
+ %res14 = fcmp uno float %x1, %x2
+
+; CHECK-NEXT: %res15 = fcmp true float %x1, %x2
+ %res15 = fcmp true float %x1, %x2
+
+; CHECK-NEXT: %res16 = fcmp false float %x1, %x2
+ %res16 = fcmp false float %x1, %x2
+
+; CHECK-NEXT: %res17 = fcmp oeq <2 x float> %vec1, %vec2
+ %res17 = fcmp oeq <2 x float> %vec1, %vec2
+
+ ret void
+}
+
+declare i32 @printf(i8* noalias nocapture, ...)
+
+define void @call(i32 %x, i8* %msg ){
+entry:
+
+; CHECK: %res1 = call i32 @test(i32 %x)
+ %res1 = call i32 @test(i32 %x)
+
+; CHECK-NEXT: %res2 = tail call i32 @test(i32 %x)
+ %res2 = tail call i32 @test(i32 %x)
+
+; CHECK-NEXT: %res3 = call i32 (i8*, ...)* @printf(i8* %msg, i32 12, i8 42)
+ %res3 = call i32 (i8*, ...)* @printf(i8* %msg, i32 12, i8 42)
+
+ ret void
+}
+
+define i32 @test(i32 %x){
+entry:
+
+ ret i32 %x
+}
diff --git a/test/Bitcode/miscInstructions.3.2.ll.bc b/test/Bitcode/miscInstructions.3.2.ll.bc Binary files differnew file mode 100644 index 000000000000..9d479b506171 --- /dev/null +++ b/test/Bitcode/miscInstructions.3.2.ll.bc diff --git a/test/Bitcode/old-aliases.ll b/test/Bitcode/old-aliases.ll new file mode 100644 index 000000000000..7a0eea2f3f24 --- /dev/null +++ b/test/Bitcode/old-aliases.ll @@ -0,0 +1,22 @@ +; RUN: llvm-dis < %s.bc | FileCheck %s + +; old-aliases.bc consist of this file assembled with an old llvm-as (3.5 trunk) +; from when aliases contained a ConstantExpr. + +@v1 = global i32 0 +; CHECK: @v1 = global i32 0 + +@v2 = global [1 x i32] zeroinitializer +; CHECK: @v2 = global [1 x i32] zeroinitializer + +@v3 = alias bitcast (i32* @v1 to i16*) +; CHECK: @v3 = alias bitcast (i32* @v1 to i16*) + +@v4 = alias getelementptr ([1 x i32]* @v2, i32 0, i32 0) +; CHECK: @v4 = alias getelementptr inbounds ([1 x i32]* @v2, i32 0, i32 0) + +@v5 = alias i32 addrspace(2)* addrspacecast (i32 addrspace(0)* @v1 to i32 addrspace(2)*) +; CHECK: @v5 = alias addrspacecast (i32* @v1 to i32 addrspace(2)*) + +@v6 = alias i16* @v3 +; CHECK: @v6 = alias i16* @v3 diff --git a/test/Bitcode/old-aliases.ll.bc b/test/Bitcode/old-aliases.ll.bc Binary files differnew file mode 100644 index 000000000000..1f157b2a0452 --- /dev/null +++ b/test/Bitcode/old-aliases.ll.bc diff --git a/test/Bitcode/pr18704.ll b/test/Bitcode/pr18704.ll new file mode 100644 index 000000000000..f05fe53259fa --- /dev/null +++ b/test/Bitcode/pr18704.ll @@ -0,0 +1,158 @@ +; RUN: not llvm-dis < %s.bc 2>&1 | FileCheck %s + +; CHECK: llvm-dis{{(\.EXE|\.exe)?}}: Never resolved value found in function + +; pr18704.ll.bc has an instruction referring to invalid type. +; The test checks that LLVM reports the error and doesn't access freed memory +; in doing so. + +;<MODULE_BLOCK NumWords=217 BlockCodeSize=3> +; <VERSION op0=1/> +; <BLOCKINFO_BLOCK/> +; <TYPE_BLOCK_ID NumWords=23 BlockCodeSize=4> +; <NUMENTRY op0=25/> +; <INTEGER op0=8/> +; <POINTER abbrevid=4 op0=0 op1=0/> +; <POINTER abbrevid=4 op0=1 op1=0/> +; <ARRAY abbrevid=9 op0=6 op1=0/> +; <POINTER abbrevid=4 op0=3 op1=0/> +; <ARRAY abbrevid=9 op0=10 op1=0/> +; <POINTER abbrevid=4 op0=5 op1=0/> +; <ARRAY abbrevid=9 op0=4 op1=0/> +; <POINTER abbrevid=4 op0=7 op1=0/> +; <ARRAY abbrevid=9 op0=5 op1=0/> +; <POINTER abbrevid=4 op0=9 op1=0/> +; <STRUCT_NAME abbrevid=7 op0=115 op1=116 op2=114 op3=117 op4=99 op5=116 op6=46 op7=112 op8=97 op9=105 op10=114 op11=46 op12=48/> +; <STRUCT_NAMED abbrevid=8 op0=0 op1=1 op2=1/> +; <ARRAY abbrevid=9 op0=2 op1=11/> +; <POINTER abbrevid=4 op0=12 op1=0/> +; <FUNCTION abbrevid=5 op0=0 op1=1 op2=1 op3=1/> +; <POINTER abbrevid=4 op0=14 op1=0/> +; <FUNCTION abbrevid=5 op0=0 op1=1 op2=1/> +; <POINTER abbrevid=4 op0=16 op1=0/> +; <INTEGER op0=64/> +; <FUNCTION abbrevid=5 op0=0 op1=1 op2=18/> +; <POINTER abbrevid=4 op0=19 op1=0/> +; <INTEGER op0=32/> +; <FUNCTION abbrevid=5 op0=0 op1=21/> +; <POINTER abbrevid=4 op0=22 op1=0/> +; <VOID/> +; </TYPE_BLOCK_ID> +; <GLOBALVAR abbrevid=4 op0=2 op1=0 op2=0 op3=0 op4=0 op5=0/> +; <GLOBALVAR abbrevid=4 op0=2 op1=0 op2=0 op3=0 op4=0 op5=0/> +; <GLOBALVAR abbrevid=4 op0=2 op1=0 op2=0 op3=0 op4=0 op5=0/> +; <GLOBALVAR op0=4 op1=1 op2=25 op3=9 op4=0 op5=0 op6=0 op7=0 op8=1 op9=0/> +; <GLOBALVAR op0=6 op1=1 op2=26 op3=9 op4=0 op5=0 op6=0 op7=0 op8=1 op9=0/> +; <GLOBALVAR op0=8 op1=1 op2=27 op3=9 op4=0 op5=0 op6=0 op7=0 op8=1 op9=0/> +; <GLOBALVAR abbrevid=4 op0=10 op1=1 op2=28 op3=3 op4=0 op5=0/> +; <GLOBALVAR abbrevid=4 op0=6 op1=1 op2=26 op3=3 op4=0 op5=0/> +; <GLOBALVAR abbrevid=4 op0=13 op1=1 op2=31 op3=3 op4=0 op5=0/> +; <GLOBALVAR abbrevid=4 op0=2 op1=1 op2=23 op3=3 op4=0 op5=0/> +; <GLOBALVAR abbrevid=4 op0=2 op1=0 op2=24 op3=0 op4=0 op5=0/> +; <GLOBALVAR op0=10 op1=1 op2=28 op3=9 op4=0 op5=0 op6=0 op7=0 op8=1 op9=0/> +; <FUNCTION op0=15 op1=0 op2=1 op3=0 op4=0 op5=0 op6=0 op7=0 op8=0 op9=0/> +; <FUNCTION op0=17 op1=0 op2=1 op3=0 op4=0 op5=0 op6=0 op7=0 op8=0 op9=0/> +; <FUNCTION op0=20 op1=0 op2=1 op3=0 op4=0 op5=0 op6=0 op7=0 op8=0 op9=0/> +; <FUNCTION op0=15 op1=0 op2=0 op3=0 op4=0 op5=0 op6=0 op7=0 op8=0 op9=0/> +; <FUNCTION op0=17 op1=0 op2=0 op3=0 op4=0 op5=0 op6=0 op7=0 op8=0 op9=0/> +; <FUNCTION op0=23 op1=0 op2=0 op3=0 op4=0 op5=0 op6=0 op7=0 op8=0 op9=0/> +; <CONSTANTS_BLOCK NumWords=20 BlockCodeSize=4> +; <SETTYPE abbrevid=4 op0=21/> +; <NULL/> +; <SETTYPE abbrevid=4 op0=1/> +; <CE_CAST abbrevid=6 op0=11 op1=17 op2=16/> +; <CE_INBOUNDS_GEP op0=6 op1=7 op2=21 op3=18 op4=21 op5=18/> +; <CE_CAST abbrevid=6 op0=11 op1=15 op2=15/> +; <CE_CAST abbrevid=6 op0=11 op1=13 op2=8/> +; <CE_CAST abbrevid=6 op0=11 op1=2 op2=9/> +; <SETTYPE abbrevid=4 op0=3/> +; <CSTRING abbrevid=11 op0=112 op1=114 op2=105 op3=110 op4=116/> +; <SETTYPE abbrevid=4 op0=5/> +; <CSTRING abbrevid=11 op0=115 op1=97 op2=121 op3=72 op4=105 op5=87 op6=105 op7=116 op8=104/> +; <SETTYPE abbrevid=4 op0=7/> +; <CSTRING abbrevid=11 op0=110 op1=101 op2=119/> +; <SETTYPE abbrevid=4 op0=9/> +; <CSTRING abbrevid=11 op0=109 op1=97 op2=105 op3=110/> +; <SETTYPE abbrevid=4 op0=11/> +; <AGGREGATE abbrevid=8 op0=31 op1=19/> +; <AGGREGATE abbrevid=8 op0=20 op1=21/> +; <SETTYPE abbrevid=4 op0=12/> +; <AGGREGATE abbrevid=8 op0=28 op1=29/> +; <SETTYPE abbrevid=4 op0=1/> +; <CE_INBOUNDS_GEP op0=10 op1=6 op2=21 op3=18 op4=21 op5=18/> +; </CONSTANTS_BLOCK> +; <METADATA_BLOCK NumWords=23 BlockCodeSize=3> +; <METADATA_KIND op0=0 op1=100 op2=98 op3=103/> +; <METADATA_KIND op0=1 op1=116 op2=98 op3=97 op4=97/> +; <METADATA_KIND op0=2 op1=112 op2=114 op3=111 op4=102/> +; <METADATA_KIND op0=3 op1=102 op2=112 op3=109 op4=97 op5=116 op6=104/> +; <METADATA_KIND op0=4 op1=114 op2=97 op3=110 op4=103 op5=101/> +; <METADATA_KIND op0=5 op1=116 op2=98 op3=97 op4=97 op5=46 op6=115 op7=116 op8=114 op9=117 op10=99 op11=116/> +; <METADATA_KIND op0=6 op1=105 op2=110 op3=118 op4=97 op5=114 op6=105 op7=97 op8=110 op9=116 op10=46 op11=108 op12=111 op13=97 op14=100/> +; </METADATA_BLOCK> +; <VALUE_SYMTAB NumWords=29 BlockCodeSize=4> +; <ENTRY abbrevid=6 op0=16 op1=101 op2=120 op3=97 op4=109 op5=112 op6=108 op7=101 op8=95 op9=109 op10=97 op11=105 op12=110/> +; <ENTRY abbrevid=6 op0=1 op1=99 op2=111 op3=110 op4=115 op5=111 op6=108 op7=101/> +; <ENTRY abbrevid=6 op0=2 op1=103 op2=114 op3=101 op4=101 op5=116 op6=105 op7=110 op8=103/> +; <ENTRY abbrevid=6 op0=15 op1=101 op2=120 op3=97 op4=109 op5=112 op6=108 op7=101 op8=95 op9=115 op10=97 op11=121 op12=72 op13=105 op14=87 op15=105 op16=116 op17=104/> +; <ENTRY abbrevid=6 op0=0 op1=115 op2=116 op3=114 op4=105 op5=110 op6=103/> +; <ENTRY abbrevid=6 op0=14 op1=109 op2=97 op3=108 op4=108 op5=111 op6=99/> +; <ENTRY abbrevid=6 op0=8 op1=101 op2=120 op3=97 op4=109 op5=112 op6=108 op7=101 op8=95 op9=118 op10=116 op11=97 op12=98/> +; <ENTRY abbrevid=6 op0=13 op1=115 op2=116 op3=114 op4=105 op5=110 op6=103 op7=95 op8=115 op9=116 op10=114 op11=105 op12=110 op13=103 op14=76 op15=105 op16=116 op17=101 op18=114 op19=97 op20=108/> +; <ENTRY abbrevid=6 op0=9 op1=95 op2=95 op3=101 op4=120 op5=97 op6=109 op7=112 op8=108 op9=101/> +; <ENTRY abbrevid=6 op0=12 op1=103 op2=101 op3=116 op4=102 op5=117 op6=110 op7=99/> +; <ENTRY abbrevid=6 op0=10 op1=101 op2=120 op3=97 op4=109 op5=112 op6=108 op7=101/> +; <ENTRY abbrevid=6 op0=17 op1=109 op2=97 op3=105 op4=110/> +; </VALUE_SYMTAB> +; <FUNCTION_BLOCK NumWords=18 BlockCodeSize=4> +; <DECLAREBLOCKS op0=1/> +; <CONSTANTS_BLOCK NumWords=3 BlockCodeSize=4> +; <SETTYPE abbrevid=4 op0=1/> +; <CE_INBOUNDS_GEP op0=4 op1=3 op2=21 op3=18 op4=21 op5=18/> +; </CONSTANTS_BLOCK> +; <INST_LOAD abbrevid=4 op0=34 op1=0 op2=0/> +; <INST_CALL op0=0 op1=0 op2=24 op3=1 op4=2/> +; <INST_CAST abbrevid=7 op0=1 op1=15 op2=11/> +; <INST_CALL op0=0 op1=0 op2=1 op3=3 op4=5/> +; <INST_RET abbrevid=9 op0=1/> +; <VALUE_SYMTAB NumWords=4 BlockCodeSize=4> +; <BBENTRY abbrevid=7 op0=0 op1=101 op2=110 op3=116 op4=114 op5=121/> +; <ENTRY abbrevid=6 op0=33 op1=115 op2=97 op3=121 op4=105 op5=110 op6=103/> +; </VALUE_SYMTAB> +; </FUNCTION_BLOCK> +; <FUNCTION_BLOCK NumWords=23 BlockCodeSize=4> +; <DECLAREBLOCKS op0=1/> +; <CONSTANTS_BLOCK NumWords=4 BlockCodeSize=4> +; <SETTYPE abbrevid=4 op0=1/> +; <CE_INBOUNDS_GEP op0=6 op1=4 op2=21 op3=18 op4=21 op5=18/> +; <CE_INBOUNDS_GEP op0=8 op1=5 op2=21 op3=18 op4=21 op5=18/> +; </CONSTANTS_BLOCK> +; <INST_LOAD op0=4294966291 op1=2 op2=0 op3=0/> +; <INST_CALL op0=0 op1=0 op2=24 op3=1 op4=3/> +; <INST_CAST abbrevid=7 op0=1 op1=15 op2=11/> +; <INST_LOAD abbrevid=4 op0=36 op1=0 op2=0/> +; <INST_CALL op0=0 op1=0 op2=27 op3=1 op4=5/> +; <INST_CAST abbrevid=7 op0=1 op1=17 op2=11/> +; <INST_CALL op0=0 op1=0 op2=1 op3=3/> +; <INST_CALL op0=0 op1=0 op2=5 op3=7 op4=1/> +; <INST_RET abbrevid=9 op0=1/> +; <VALUE_SYMTAB NumWords=2 BlockCodeSize=4> +; <BBENTRY abbrevid=7 op0=0 op1=101 op2=110 op3=116 op4=114 op5=121/> +; </VALUE_SYMTAB> +; </FUNCTION_BLOCK> +; <FUNCTION_BLOCK NumWords=15 BlockCodeSize=4> +; <DECLAREBLOCKS op0=1/> +; <CONSTANTS_BLOCK NumWords=3 BlockCodeSize=4> +; <SETTYPE abbrevid=4 op0=1/> +; <CE_INBOUNDS_GEP op0=10 op1=11 op2=21 op3=18 op4=21 op5=18/> +; </CONSTANTS_BLOCK> +; <INST_LOAD abbrevid=4 op0=23 op1=0 op2=0/> +; <INST_CALL op0=0 op1=0 op2=22 op3=1 op4=2/> +; <INST_CAST abbrevid=7 op0=1 op1=17 op2=11/> +; <INST_CALL op0=0 op1=0 op2=1 op3=3/> +; <INST_RET abbrevid=9 op0=19/> +; <VALUE_SYMTAB NumWords=2 BlockCodeSize=4> +; <BBENTRY abbrevid=7 op0=0 op1=101 op2=110 op3=116 op4=114 op5=121/> +; </VALUE_SYMTAB> +; </FUNCTION_BLOCK> +;</MODULE_BLOCK> diff --git a/test/Bitcode/pr18704.ll.bc b/test/Bitcode/pr18704.ll.bc Binary files differnew file mode 100644 index 000000000000..dbfcf37b82ab --- /dev/null +++ b/test/Bitcode/pr18704.ll.bc diff --git a/test/Bitcode/select.ll b/test/Bitcode/select.ll index 71e669a90cdc..08a3061394db 100644 --- a/test/Bitcode/select.ll +++ b/test/Bitcode/select.ll @@ -5,5 +5,5 @@ define <2 x i32> @main() { } ; CHECK: define <2 x i32> @main() { -; CHECK: ret <2 x i32> select (<2 x i1> <i1 false, i1 undef>, <2 x i32> zeroinitializer, <2 x i32> <i32 0, i32 undef>) +; CHECK: ret <2 x i32> <i32 0, i32 undef> ; CHECK: } diff --git a/test/Bitcode/tailcall.ll b/test/Bitcode/tailcall.ll new file mode 100644 index 000000000000..765b47054cad --- /dev/null +++ b/test/Bitcode/tailcall.ll @@ -0,0 +1,17 @@ +; RUN: llvm-as < %s | llvm-dis | FileCheck %s + +; Check that musttail and tail roundtrip. + +declare cc8191 void @t1_callee() +define cc8191 void @t1() { +; CHECK: tail call cc8191 void @t1_callee() + tail call cc8191 void @t1_callee() + ret void +} + +declare cc8191 void @t2_callee() +define cc8191 void @t2() { +; CHECK: musttail call cc8191 void @t2_callee() + musttail call cc8191 void @t2_callee() + ret void +} diff --git a/test/Bitcode/terminatorInstructions.3.2.ll b/test/Bitcode/terminatorInstructions.3.2.ll new file mode 100644 index 000000000000..31e78967ee0c --- /dev/null +++ b/test/Bitcode/terminatorInstructions.3.2.ll @@ -0,0 +1,47 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s
+
+; TerminatorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
+; The test checks that LLVM does not misread terminator instructions from
+; older bitcode files.
+
+define i32 @condbr(i1 %cond){
+entry:
+; CHECK: br i1 %cond, label %TrueLabel, label %FalseLabel
+ br i1 %cond, label %TrueLabel, label %FalseLabel
+
+ TrueLabel:
+ ret i32 1
+
+ FalseLabel:
+ ret i32 0
+}
+
+define i32 @uncondbr(){
+entry:
+; CHECK: br label %uncondLabel
+ br label %uncondLabel
+
+ uncondLabel:
+ ret i32 1
+}
+
+define i32 @indirectbr(i8* %Addr){
+entry:
+; CHECK: indirectbr i8* %Addr, [label %bb1, label %bb2]
+ indirectbr i8* %Addr, [ label %bb1, label %bb2 ]
+
+ bb1:
+ ret i32 1
+
+ bb2:
+ ret i32 0
+}
+
+define void @unreachable(){
+entry:
+; CHECK: unreachable
+ unreachable
+
+ ret void
+}
+
diff --git a/test/Bitcode/terminatorInstructions.3.2.ll.bc b/test/Bitcode/terminatorInstructions.3.2.ll.bc Binary files differnew file mode 100644 index 000000000000..9d92ead8ad18 --- /dev/null +++ b/test/Bitcode/terminatorInstructions.3.2.ll.bc diff --git a/test/Bitcode/upgrade-global-ctors.ll b/test/Bitcode/upgrade-global-ctors.ll new file mode 100644 index 000000000000..bd253a81620f --- /dev/null +++ b/test/Bitcode/upgrade-global-ctors.ll @@ -0,0 +1,3 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; CHECK: @llvm.global_ctors = appending global [0 x { i32, void ()*, i8* }] zeroinitializer diff --git a/test/Bitcode/upgrade-global-ctors.ll.bc b/test/Bitcode/upgrade-global-ctors.ll.bc Binary files differnew file mode 100644 index 000000000000..927fd91867e9 --- /dev/null +++ b/test/Bitcode/upgrade-global-ctors.ll.bc diff --git a/test/Bitcode/upgrade-loop-metadata.ll b/test/Bitcode/upgrade-loop-metadata.ll new file mode 100644 index 000000000000..67a8d3935926 --- /dev/null +++ b/test/Bitcode/upgrade-loop-metadata.ll @@ -0,0 +1,37 @@ +; Test to make sure loop vectorizer metadata is automatically upgraded. +; +; RUN: llvm-dis < %s.bc | FileCheck %s + +define void @_Z28loop_with_vectorize_metadatav() { +entry: + %i = alloca i32, align 4 + store i32 0, i32* %i, align 4 + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + %0 = load i32* %i, align 4 + %cmp = icmp slt i32 %0, 16 + br i1 %cmp, label %for.body, label %for.end, !llvm.loop !1 + +for.body: ; preds = %for.cond + br label %for.inc + +for.inc: ; preds = %for.body + %1 = load i32* %i, align 4 + %inc = add nsw i32 %1, 1 + store i32 %inc, i32* %i, align 4 + br label %for.cond + +for.end: ; preds = %for.cond + ret void +} + +; CHECK: !{metadata !"llvm.loop.interleave.count", i32 4} +; CHECK: !{metadata !"llvm.loop.vectorize.width", i32 8} +; CHECK: !{metadata !"llvm.loop.vectorize.enable", i1 true} + +!0 = metadata !{metadata !"clang version 3.5.0 (trunk 211528)"} +!1 = metadata !{metadata !1, metadata !2, metadata !3, metadata !4, metadata !4} +!2 = metadata !{metadata !"llvm.vectorizer.unroll", i32 4} +!3 = metadata !{metadata !"llvm.vectorizer.width", i32 8} +!4 = metadata !{metadata !"llvm.vectorizer.enable", i1 true} diff --git a/test/Bitcode/upgrade-loop-metadata.ll.bc b/test/Bitcode/upgrade-loop-metadata.ll.bc Binary files differnew file mode 100644 index 000000000000..3f218cb7feb4 --- /dev/null +++ b/test/Bitcode/upgrade-loop-metadata.ll.bc diff --git a/test/Bitcode/variableArgumentIntrinsic.3.2.ll b/test/Bitcode/variableArgumentIntrinsic.3.2.ll new file mode 100644 index 000000000000..35fe0e252822 --- /dev/null +++ b/test/Bitcode/variableArgumentIntrinsic.3.2.ll @@ -0,0 +1,33 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s
+
+; vaArgIntrinsic.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
+; The test checks that LLVM does not misread variable argument intrinsic instructions
+; of older bitcode files.
+
+define i32 @varArgIntrinsic(i32 %X, ...) {
+
+ %ap = alloca i8*
+ %ap2 = bitcast i8** %ap to i8*
+
+; CHECK: call void @llvm.va_start(i8* %ap2)
+ call void @llvm.va_start(i8* %ap2)
+
+; CHECK-NEXT: %tmp = va_arg i8** %ap, i32
+ %tmp = va_arg i8** %ap, i32
+
+ %aq = alloca i8*
+ %aq2 = bitcast i8** %aq to i8*
+
+; CHECK: call void @llvm.va_copy(i8* %aq2, i8* %ap2)
+ call void @llvm.va_copy(i8* %aq2, i8* %ap2)
+; CHECK-NEXT: call void @llvm.va_end(i8* %aq2)
+ call void @llvm.va_end(i8* %aq2)
+
+; CHECK-NEXT: call void @llvm.va_end(i8* %ap2)
+ call void @llvm.va_end(i8* %ap2)
+ ret i32 %tmp
+}
+
+declare void @llvm.va_start(i8*)
+declare void @llvm.va_copy(i8*, i8*)
+declare void @llvm.va_end(i8*)
\ No newline at end of file diff --git a/test/Bitcode/variableArgumentIntrinsic.3.2.ll.bc b/test/Bitcode/variableArgumentIntrinsic.3.2.ll.bc Binary files differnew file mode 100644 index 000000000000..066e102b1da9 --- /dev/null +++ b/test/Bitcode/variableArgumentIntrinsic.3.2.ll.bc diff --git a/test/Bitcode/vectorInstructions.3.2.ll b/test/Bitcode/vectorInstructions.3.2.ll new file mode 100644 index 000000000000..b24ef75ef081 --- /dev/null +++ b/test/Bitcode/vectorInstructions.3.2.ll @@ -0,0 +1,34 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s
+
+; vectorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
+; The test checks that LLVM does not misread vector operations of
+; older bitcode files.
+
+define void @extractelement(<2 x i8> %x1){
+entry:
+; CHECK: %res1 = extractelement <2 x i8> %x1, i32 0
+ %res1 = extractelement <2 x i8> %x1, i32 0
+
+ ret void
+}
+
+define void @insertelement(<2 x i8> %x1){
+entry:
+; CHECK: %res1 = insertelement <2 x i8> %x1, i8 0, i32 0
+ %res1 = insertelement <2 x i8> %x1, i8 0, i32 0
+
+ ret void
+}
+
+define void @shufflevector(<2 x i8> %x1){
+entry:
+; CHECK: %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> <i32 0, i32 1>
+ %res1 = shufflevector <2 x i8> %x1, <2 x i8> %x1, <2 x i32> <i32 0, i32 1>
+
+; CHECK-NEXT: %res2 = shufflevector <2 x i8> %x1, <2 x i8> undef, <2 x i32> <i32 0, i32 1>
+ %res2 = shufflevector <2 x i8> %x1, <2 x i8> undef, <2 x i32> <i32 0, i32 1>
+
+ ret void
+}
+
+
diff --git a/test/Bitcode/vectorInstructions.3.2.ll.bc b/test/Bitcode/vectorInstructions.3.2.ll.bc Binary files differnew file mode 100644 index 000000000000..b1727031701b --- /dev/null +++ b/test/Bitcode/vectorInstructions.3.2.ll.bc diff --git a/test/Bitcode/visibility-styles.3.2.ll b/test/Bitcode/visibility-styles.3.2.ll new file mode 100644 index 000000000000..ec2ee6832063 --- /dev/null +++ b/test/Bitcode/visibility-styles.3.2.ll @@ -0,0 +1,23 @@ +; RUN: llvm-dis < %s.bc| FileCheck %s + +; visibility-styles.3.2.ll.bc was generated by passing this file to llvm-as-3.2. +; The test checks that LLVM does not silently misread visibility styles of +; older bitcode files. + +@default.var = default global i32 0 +; CHECK: @default.var = global i32 0 + +@hidden.var = hidden global i32 0 +; CHECK: @hidden.var = hidden global i32 0 + +@protected.var = protected global i32 0 +; CHECK: @protected.var = protected global i32 0 + +declare default void @default() +; CHECK: declare void @default + +declare hidden void @hidden() +; CHECK: declare hidden void @hidden + +declare protected void @protected() +; CHECK: declare protected void @protected diff --git a/test/Bitcode/visibility-styles.3.2.ll.bc b/test/Bitcode/visibility-styles.3.2.ll.bc Binary files differnew file mode 100644 index 000000000000..e2f0b058cce6 --- /dev/null +++ b/test/Bitcode/visibility-styles.3.2.ll.bc diff --git a/test/Bitcode/weak-cmpxchg-upgrade.ll b/test/Bitcode/weak-cmpxchg-upgrade.ll new file mode 100644 index 000000000000..dbcd150633ed --- /dev/null +++ b/test/Bitcode/weak-cmpxchg-upgrade.ll @@ -0,0 +1,15 @@ +; RUN: llvm-dis < %s.bc | FileCheck %s + +; cmpxchg-upgrade.ll.bc was produced by running a version of llvm-as from just +; before the IR change on this file. + +define i32 @test(i32* %addr, i32 %old, i32 %new) { +; CHECK: [[TMP:%.*]] = cmpxchg i32* %addr, i32 %old, i32 %new seq_cst monotonic +; CHECK: %val = extractvalue { i32, i1 } [[TMP]], 0 + %val = cmpxchg i32* %addr, i32 %old, i32 %new seq_cst monotonic + ret i32 %val +} + +define i32 @test(i32* %addr, i32 %old, i32 %new) { + ret i1 %val +} diff --git a/test/Bitcode/weak-cmpxchg-upgrade.ll.bc b/test/Bitcode/weak-cmpxchg-upgrade.ll.bc Binary files differnew file mode 100644 index 000000000000..f713c317d46f --- /dev/null +++ b/test/Bitcode/weak-cmpxchg-upgrade.ll.bc |