vendor/llvm/llvm-release_39-r276489

1 files changed, 173 insertions, 72 deletions

diff --git a/test/CodeGen/Mips/atomic.ll b/test/CodeGen/Mips/atomic.ll
index 031cce0b6074..8f4ccb19958a 100644
--- a/test/CodeGen/Mips/atomic.ll
+++ b/test/CodeGen/Mips/atomic.ll
@@ -1,15 +1,26 @@
-; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32   < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH  -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
-; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
-; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
-; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips4    < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH  -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
-; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64   < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH  -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
-; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
-; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS
-; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -mattr=micromips < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MICROMIPS
+; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32   -relocation-model=pic < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL,MIPS32-ANY,NO-SEB-SEH,CHECK-EL,NOT-MICROMIPS
+; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -relocation-model=pic -verify-machineinstrs < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL,MIPS32-ANY,HAS-SEB-SEH,CHECK-EL,NOT-MICROMIPS
+; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r6 -relocation-model=pic -verify-machineinstrs < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL,MIPS32-ANY,HAS-SEB-SEH,CHECK-EL,MIPSR6
+; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips4    -relocation-model=pic < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL,MIPS64-ANY,NO-SEB-SEH,CHECK-EL,NOT-MICROMIPS
+; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64   -relocation-model=pic < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL,MIPS64-ANY,NO-SEB-SEH,CHECK-EL,NOT-MICROMIPS
+; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r2 -relocation-model=pic -verify-machineinstrs < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL,MIPS64-ANY,HAS-SEB-SEH,CHECK-EL,NOT-MICROMIPS
+; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r6 -relocation-model=pic < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL,MIPS64-ANY,HAS-SEB-SEH,CHECK-EL,MIPSR6
+; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -relocation-model=pic -verify-machineinstrs < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL-LABEL,MIPS64-ANY,O0
+; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -mattr=micromips -relocation-model=pic < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL,MIPS32-ANY,HAS-SEB-SEH,CHECK-EL,MICROMIPS
 
 ; Keep one big-endian check so that we don't reduce testing, but don't add more
 ; since endianness doesn't affect the body of the atomic operations.
-; RUN: llc -march=mips   --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EB -check-prefix=NOT-MICROMIPS
+; RUN: llc -march=mips   --disable-machine-licm -mcpu=mips32 -relocation-model=pic < %s | \
+; RUN:   FileCheck %s -check-prefixes=ALL,MIPS32-ANY,NO-SEB-SEH,CHECK-EB,NOT-MICROMIPS
 
 @x = common global i32 0, align 4
 
@@ -23,12 +34,17 @@ entry:
 ; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(x)
 ; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(x)(
 
+; O0:        $[[BB0:[A-Z_0-9]+]]:
+; O0:            ld      $[[R1:[0-9]+]]
+; O0-NEXT:       ll      $[[R2:[0-9]+]], 0($[[R1]])
+
 ; ALL:       $[[BB0:[A-Z_0-9]+]]:
-; ALL:           ll      $[[R1:[0-9]+]], 0($[[R0]])
-; ALL:           addu    $[[R2:[0-9]+]], $[[R1]], $4
-; ALL:           sc      $[[R2]], 0($[[R0]])
-; NOT-MICROMIPS: beqz    $[[R2]], $[[BB0]]
-; MICROMIPS:     beqzc   $[[R2]], $[[BB0]]
+; ALL:           ll      $[[R3:[0-9]+]], 0($[[R0]])
+; ALL:           addu    $[[R4:[0-9]+]], $[[R3]], $4
+; ALL:           sc      $[[R4]], 0($[[R0]])
+; NOT-MICROMIPS: beqz    $[[R4]], $[[BB0]]
+; MICROMIPS:     beqzc   $[[R4]], $[[BB0]]
+; MIPSR6:        beqzc   $[[R4]], $[[BB0]]
 }
 
 define i32 @AtomicLoadNand32(i32 signext %incr) nounwind {
@@ -41,6 +57,8 @@ entry:
 ; MIPS32-ANY:    lw      $[[R0:[0-9]+]], %got(x)
 ; MIPS64-ANY:    ld      $[[R0:[0-9]+]], %got_disp(x)(
 
+
+
 ; ALL:       $[[BB0:[A-Z_0-9]+]]:
 ; ALL:           ll      $[[R1:[0-9]+]], 0($[[R0]])
 ; ALL:           and     $[[R3:[0-9]+]], $[[R1]], $4
@@ -48,6 +66,7 @@ entry:
 ; ALL:           sc      $[[R2]], 0($[[R0]])
 ; NOT-MICROMIPS: beqz    $[[R2]], $[[BB0]]
 ; MICROMIPS:     beqzc   $[[R2]], $[[BB0]]
+; MIPSR6:        beqzc   $[[R2]], $[[BB0]]
 }
 
 define i32 @AtomicSwap32(i32 signext %newval) nounwind {
@@ -68,6 +87,7 @@ entry:
 ; ALL:           sc      $[[R2:[0-9]+]], 0($[[R0]])
 ; NOT-MICROMIPS: beqz    $[[R2]], $[[BB0]]
 ; MICROMIPS:     beqzc   $[[R2]], $[[BB0]]
+; MIPSR6:        beqzc   $[[R2]], $[[BB0]]
 }
 
 define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind {
@@ -86,10 +106,13 @@ entry:
 
 ; ALL:       $[[BB0:[A-Z_0-9]+]]:
 ; ALL:           ll      $2, 0($[[R0]])
-; ALL:           bne     $2, $4, $[[BB1:[A-Z_0-9]+]]
+; NOT-MICROMIPS: bne     $2, $4, $[[BB1:[A-Z_0-9]+]]
+; MICROMIPS:     bne     $2, $4, $[[BB1:[A-Z_0-9]+]]
+; MIPSR6:        bnec    $2, $4, $[[BB1:[A-Z_0-9]+]]
 ; ALL:           sc      $[[R2:[0-9]+]], 0($[[R0]])
 ; NOT-MICROMIPS: beqz    $[[R2]], $[[BB0]]
 ; MICROMIPS:     beqzc   $[[R2]], $[[BB0]]
+; MIPSR6:        beqzc   $[[R2]], $[[BB0]]
 ; ALL:       $[[BB1]]:
 }
 
@@ -118,23 +141,28 @@ entry:
 ; ALL:           nor     $[[R8:[0-9]+]], $zero, $[[R7]]
 ; ALL:           sllv    $[[R9:[0-9]+]], $4, $[[R5]]
 
+; O0:        $[[BB0:[A-Z_0-9]+]]:
+; O0:            ld      $[[R10:[0-9]+]]
+; O0-NEXT:       ll      $[[R11:[0-9]+]], 0($[[R10]])
+
 ; ALL:       $[[BB0:[A-Z_0-9]+]]:
-; ALL:           ll      $[[R10:[0-9]+]], 0($[[R2]])
-; ALL:           addu    $[[R11:[0-9]+]], $[[R10]], $[[R9]]
-; ALL:           and     $[[R12:[0-9]+]], $[[R11]], $[[R7]]
-; ALL:           and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
-; ALL:           or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
-; ALL:           sc      $[[R14]], 0($[[R2]])
-; NOT-MICROMIPS: beqz    $[[R14]], $[[BB0]]
-; MICROMIPS:     beqzc   $[[R14]], $[[BB0]]
+; ALL:           ll      $[[R12:[0-9]+]], 0($[[R2]])
+; ALL:           addu    $[[R13:[0-9]+]], $[[R12]], $[[R9]]
+; ALL:           and     $[[R14:[0-9]+]], $[[R13]], $[[R7]]
+; ALL:           and     $[[R15:[0-9]+]], $[[R12]], $[[R8]]
+; ALL:           or      $[[R16:[0-9]+]], $[[R15]], $[[R14]]
+; ALL:           sc      $[[R16]], 0($[[R2]])
+; NOT-MICROMIPS: beqz    $[[R16]], $[[BB0]]
+; MICROMIPS:     beqzc   $[[R16]], $[[BB0]]
+; MIPSR6:        beqzc   $[[R16]], $[[BB0]]
 
-; ALL:           and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
-; ALL:           srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
+; ALL:           and     $[[R17:[0-9]+]], $[[R12]], $[[R7]]
+; ALL:           srlv    $[[R18:[0-9]+]], $[[R17]], $[[R5]]
 
-; NO-SEB-SEH:    sll     $[[R17:[0-9]+]], $[[R16]], 24
-; NO-SEB-SEH:    sra     $2, $[[R17]], 24
+; NO-SEB-SEH:    sll     $[[R19:[0-9]+]], $[[R18]], 24
+; NO-SEB-SEH:    sra     $2, $[[R19]], 24
 
-; HAS-SEB-SEH:   seb     $2, $[[R16]]
+; HAS-SEB-SEH:   seb     $2, $[[R18]]
 }
 
 define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind {
@@ -158,23 +186,28 @@ entry:
 ; ALL:        nor     $[[R8:[0-9]+]], $zero, $[[R7]]
 ; ALL:        sllv    $[[R9:[0-9]+]], $4, $[[R5]]
 
+; O0:        $[[BB0:[A-Z_0-9]+]]:
+; O0:            ld      $[[R10:[0-9]+]]
+; O0-NEXT:       ll      $[[R11:[0-9]+]], 0($[[R10]])
+
 ; ALL:    $[[BB0:[A-Z_0-9]+]]:
-; ALL:        ll      $[[R10:[0-9]+]], 0($[[R2]])
-; ALL:        subu    $[[R11:[0-9]+]], $[[R10]], $[[R9]]
-; ALL:        and     $[[R12:[0-9]+]], $[[R11]], $[[R7]]
-; ALL:        and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
-; ALL:        or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
-; ALL:        sc      $[[R14]], 0($[[R2]])
-; NOT-MICROMIPS: beqz    $[[R14]], $[[BB0]]
-; MICROMIPS:  beqzc   $[[R14]], $[[BB0]]
+; ALL:        ll      $[[R12:[0-9]+]], 0($[[R2]])
+; ALL:        subu    $[[R13:[0-9]+]], $[[R12]], $[[R9]]
+; ALL:        and     $[[R14:[0-9]+]], $[[R13]], $[[R7]]
+; ALL:        and     $[[R15:[0-9]+]], $[[R12]], $[[R8]]
+; ALL:        or      $[[R16:[0-9]+]], $[[R15]], $[[R14]]
+; ALL:        sc      $[[R16]], 0($[[R2]])
+; NOT-MICROMIPS: beqz    $[[R16]], $[[BB0]]
+; MICROMIPS:  beqzc   $[[R16]], $[[BB0]]
+; MIPSR6:     beqzc   $[[R16]], $[[BB0]]
 
-; ALL:        and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
-; ALL:        srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
+; ALL:        and     $[[R17:[0-9]+]], $[[R12]], $[[R7]]
+; ALL:        srlv    $[[R18:[0-9]+]], $[[R17]], $[[R5]]
 
-; NO-SEB-SEH: sll     $[[R17:[0-9]+]], $[[R16]], 24
-; NO-SEB-SEH: sra     $2, $[[R17]], 24
+; NO-SEB-SEH: sll     $[[R19:[0-9]+]], $[[R18]], 24
+; NO-SEB-SEH: sra     $2, $[[R19]], 24
 
-; HAS-SEB-SEH:seb     $2, $[[R16]]
+; HAS-SEB-SEH:seb     $2, $[[R18]]
 }
 
 define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind {
@@ -198,24 +231,29 @@ entry:
 ; ALL:           nor     $[[R8:[0-9]+]], $zero, $[[R7]]
 ; ALL:           sllv    $[[R9:[0-9]+]], $4, $[[R5]]
 
+; O0:        $[[BB0:[A-Z_0-9]+]]:
+; O0:            ld      $[[R10:[0-9]+]]
+; O0-NEXT:       ll      $[[R11:[0-9]+]], 0($[[R10]])
+
 ; ALL:       $[[BB0:[A-Z_0-9]+]]:
-; ALL:           ll      $[[R10:[0-9]+]], 0($[[R2]])
-; ALL:           and     $[[R18:[0-9]+]], $[[R10]], $[[R9]]
-; ALL:           nor     $[[R11:[0-9]+]], $zero, $[[R18]]
-; ALL:           and     $[[R12:[0-9]+]], $[[R11]], $[[R7]]
-; ALL:           and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
-; ALL:           or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
-; ALL:           sc      $[[R14]], 0($[[R2]])
-; NOT-MICROMIPS: beqz    $[[R14]], $[[BB0]]
-; MICROMIPS:     beqzc   $[[R14]], $[[BB0]]
+; ALL:           ll      $[[R12:[0-9]+]], 0($[[R2]])
+; ALL:           and     $[[R13:[0-9]+]], $[[R12]], $[[R9]]
+; ALL:           nor     $[[R14:[0-9]+]], $zero, $[[R13]]
+; ALL:           and     $[[R15:[0-9]+]], $[[R14]], $[[R7]]
+; ALL:           and     $[[R16:[0-9]+]], $[[R12]], $[[R8]]
+; ALL:           or      $[[R17:[0-9]+]], $[[R16]], $[[R15]]
+; ALL:           sc      $[[R17]], 0($[[R2]])
+; NOT-MICROMIPS: beqz    $[[R17]], $[[BB0]]
+; MICROMIPS:     beqzc   $[[R17]], $[[BB0]]
+; MIPSR6:        beqzc   $[[R17]], $[[BB0]]
 
-; ALL:           and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
-; ALL:           srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
+; ALL:           and     $[[R18:[0-9]+]], $[[R12]], $[[R7]]
+; ALL:           srlv    $[[R19:[0-9]+]], $[[R18]], $[[R5]]
 
-; NO-SEB-SEH:    sll     $[[R17:[0-9]+]], $[[R16]], 24
-; NO-SEB-SEH:    sra     $2, $[[R17]], 24
+; NO-SEB-SEH:    sll     $[[R20:[0-9]+]], $[[R19]], 24
+; NO-SEB-SEH:    sra     $2, $[[R20]], 24
 
-; HAS-SEB-SEH:   seb     $2, $[[R16]]
+; HAS-SEB-SEH:   seb     $2, $[[R19]]
 }
 
 define signext i8 @AtomicSwap8(i8 signext %newval) nounwind {
@@ -247,6 +285,7 @@ entry:
 ; ALL:           sc      $[[R14]], 0($[[R2]])
 ; NOT-MICROMIPS: beqz    $[[R14]], $[[BB0]]
 ; MICROMIPS:     beqzc   $[[R14]], $[[BB0]]
+; MIPSR6:        beqzc   $[[R14]], $[[BB0]]
 
 ; ALL:           and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
 ; ALL:           srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@@ -286,13 +325,16 @@ entry:
 ; ALL:       $[[BB0:[A-Z_0-9]+]]:
 ; ALL:           ll      $[[R13:[0-9]+]], 0($[[R2]])
 ; ALL:           and     $[[R14:[0-9]+]], $[[R13]], $[[R7]]
-; ALL:           bne     $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
+; NOT-MICROMIPS: bne     $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
+; MICROMIPS:     bne     $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
+; MIPSR6:        bnec    $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
 
 ; ALL:           and     $[[R15:[0-9]+]], $[[R13]], $[[R8]]
 ; ALL:           or      $[[R16:[0-9]+]], $[[R15]], $[[R12]]
 ; ALL:           sc      $[[R16]], 0($[[R2]])
 ; NOT-MICROMIPS: beqz    $[[R16]], $[[BB0]]
 ; MICROMIPS:     beqzc   $[[R16]], $[[BB0]]
+; MIPSR6:        beqzc   $[[R16]], $[[BB0]]
 
 ; ALL:       $[[BB1]]:
 ; ALL:           srlv    $[[R17:[0-9]+]], $[[R14]], $[[R5]]
@@ -327,13 +369,16 @@ entry:
 ; ALL:       $[[BB0:[A-Z_0-9]+]]:
 ; ALL:           ll      $[[R13:[0-9]+]], 0($[[R2]])
 ; ALL:           and     $[[R14:[0-9]+]], $[[R13]], $[[R7]]
-; ALL:           bne     $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
+; NOT-MICROMIPS: bne     $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
+; MICROMIPS:     bne     $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
+; MIPSR6:        bnec    $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
 
 ; ALL:           and     $[[R15:[0-9]+]], $[[R13]], $[[R8]]
 ; ALL:           or      $[[R16:[0-9]+]], $[[R15]], $[[R12]]
 ; ALL:           sc      $[[R16]], 0($[[R2]])
 ; NOT-MICROMIPS: beqz    $[[R16]], $[[BB0]]
 ; MICROMIPS:     beqzc   $[[R16]], $[[BB0]]
+; MIPSR6:        beqzc   $[[R16]], $[[BB0]]
 
 ; ALL:       $[[BB1]]:
 ; ALL:           srlv    $[[R17:[0-9]+]], $[[R14]], $[[R5]]
@@ -341,10 +386,17 @@ entry:
 ; NO-SEB-SEH:    sll     $[[R18:[0-9]+]], $[[R17]], 24
 ; NO-SEB-SEH:    sra     $[[R19:[0-9]+]], $[[R18]], 24
 
+; FIXME: -march=mips produces a redundant sign extension here...
+; NO-SEB-SEH:    sll     $[[R20:[0-9]+]], $5, 24
+; NO-SEB-SEH:    sra     $[[R20]], $[[R20]], 24
+
 ; HAS-SEB-SEH:   seb     $[[R19:[0-9]+]], $[[R17]]
 
-; ALL:           xor     $[[R20:[0-9]+]], $[[R19]], $5
-; ALL:           sltiu   $2, $[[R20]], 1
+; FIXME: ...Leading to this split check.
+; NO-SEB-SEH:    xor     $[[R21:[0-9]+]], $[[R19]], $[[R20]]
+; HAS-SEB-SEH:   xor     $[[R21:[0-9]+]], $[[R19]], $5
+
+; ALL: sltiu   $2, $[[R21]], 1
 }
 
 ; Check one i16 so that we cover the seh sign extend
@@ -371,25 +423,73 @@ entry:
 ; ALL:           nor     $[[R8:[0-9]+]], $zero, $[[R7]]
 ; ALL:           sllv    $[[R9:[0-9]+]], $4, $[[R5]]
 
+; O0:        $[[BB0:[A-Z_0-9]+]]:
+; O0:            ld      $[[R10:[0-9]+]]
+; O0-NEXT:       ll      $[[R11:[0-9]+]], 0($[[R10]])
+
 ; ALL:       $[[BB0:[A-Z_0-9]+]]:
-; ALL:           ll      $[[R10:[0-9]+]], 0($[[R2]])
-; ALL:           addu    $[[R11:[0-9]+]], $[[R10]], $[[R9]]
-; ALL:           and     $[[R12:[0-9]+]], $[[R11]], $[[R7]]
-; ALL:           and     $[[R13:[0-9]+]], $[[R10]], $[[R8]]
-; ALL:           or      $[[R14:[0-9]+]], $[[R13]], $[[R12]]
-; ALL:           sc      $[[R14]], 0($[[R2]])
-; NOT-MICROMIPS: beqz    $[[R14]], $[[BB0]]
-; MICROMIPS:     beqzc   $[[R14]], $[[BB0]]
+; ALL:           ll      $[[R12:[0-9]+]], 0($[[R2]])
+; ALL:           addu    $[[R13:[0-9]+]], $[[R12]], $[[R9]]
+; ALL:           and     $[[R14:[0-9]+]], $[[R13]], $[[R7]]
+; ALL:           and     $[[R15:[0-9]+]], $[[R12]], $[[R8]]
+; ALL:           or      $[[R16:[0-9]+]], $[[R15]], $[[R14]]
+; ALL:           sc      $[[R16]], 0($[[R2]])
+; NOT-MICROMIPS: beqz    $[[R16]], $[[BB0]]
+; MICROMIPS:     beqzc   $[[R16]], $[[BB0]]
+; MIPSR6:        beqzc   $[[R16]], $[[BB0]]
 
-; ALL:           and     $[[R15:[0-9]+]], $[[R10]], $[[R7]]
-; ALL:           srlv    $[[R16:[0-9]+]], $[[R15]], $[[R5]]
+; ALL:           and     $[[R17:[0-9]+]], $[[R12]], $[[R7]]
+; ALL:           srlv    $[[R18:[0-9]+]], $[[R17]], $[[R5]]
 
-; NO-SEB-SEH:    sll     $[[R17:[0-9]+]], $[[R16]], 16
-; NO-SEB-SEH:    sra     $2, $[[R17]], 16
+; NO-SEB-SEH:    sll     $[[R19:[0-9]+]], $[[R18]], 16
+; NO-SEB-SEH:    sra     $2, $[[R19]], 16
 
-; MIPS32R2:      seh     $2, $[[R16]]
+; MIPS32R2:      seh     $2, $[[R18]]
 }
 
+; Test that the i16 return value from cmpxchg is recognised as signed,
+; so that setCC doesn't end up comparing an unsigned value to a signed
+; value.
+; The rest of the functions here are testing the atomic expansion, so
+; we just match the end of the function.
+define {i16, i1} @foo(i16* %addr, i16 %l, i16 %r, i16 %new) {
+  %desired = add i16 %l, %r
+  %res = cmpxchg i16* %addr, i16 %desired, i16 %new seq_cst seq_cst
+  ret {i16, i1} %res
+
+; ALL-LABEL: foo
+; MIPSR6:        addu    $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]]
+; NOT-MICROMIPS: addu    $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]]
+; MICROMIPS:     addu16  $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]]
+
+; ALL:           sync
+
+; ALL:           andi    $[[R3:[0-9]+]], $[[R2]], 65535
+; ALL:       $[[BB0:[A-Z_0-9]+]]:
+; ALL:           ll      $[[R4:[0-9]+]], 0($[[R5:[0-9]+]])
+; ALL:           and     $[[R6:[0-9]+]], $[[R4]], $
+; ALL:           and     $[[R7:[0-9]+]], $[[R4]], $
+; ALL:           or      $[[R8:[0-9]+]], $[[R7]], $
+; ALL:           sc      $[[R8]], 0($[[R5]])
+; NOT-MICROMIPS: beqz    $[[R8]], $[[BB0]]
+; MICROMIPS:     beqzc   $[[R8]], $[[BB0]]
+; MIPSR6:        beqzc   $[[R8]], $[[BB0]]
+
+; ALL:           srlv    $[[R9:[0-9]+]], $[[R6]], $
+
+; NO-SEB-SEH:    sll     $[[R10:[0-9]+]], $[[R9]], 16
+; NO-SEB-SEH:    sra     $[[R11:[0-9]+]], $[[R10]], 16
+
+; NO-SEB-SEH:    sll     $[[R12:[0-9]+]], $[[R2]], 16
+; NO-SEB-SEH:    sra     $[[R13:[0-9]+]], $[[R12]], 16
+
+; HAS-SEB-SEH:   seh     $[[R11:[0-9]+]], $[[R9]]
+; HAS-SEB-SEH:   seh     $[[R13:[0-9]+]], $[[R2]]
+
+; ALL:           xor     $[[R12:[0-9]+]], $[[R11]], $[[R13]]
+; ALL:           sltiu   $3, $[[R12]], 1
+; ALL:           sync
+}
 
 @countsint = common global i32 0, align 4
 
@@ -444,4 +544,5 @@ entry:
 ; ALL:           sc      $[[R2]], 0($[[PTR]])
 ; NOT-MICROMIPS: beqz    $[[R2]], $[[BB0]]
 ; MICROMIPS:     beqzc   $[[R2]], $[[BB0]]
+; MIPSR6:        beqzc   $[[R2]], $[[BB0]]
 }