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authorDimitry Andric <dim@FreeBSD.org>2017-05-02 18:30:13 +0000
committerDimitry Andric <dim@FreeBSD.org>2017-05-02 18:30:13 +0000
commita303c417bbdb53703c2c17398b08486bde78f1f6 (patch)
tree98366d6b93d863cefdc53f16c66c0c5ae7fb2261 /test/CodeGen/Mips
parent12f3ca4cdb95b193af905a00e722a4dcb40b3de3 (diff)
vendor/llvm/llvm-trunk-r301939
Notes
Diffstat (limited to 'test/CodeGen/Mips')
-rw-r--r--test/CodeGen/Mips/llvm-ir/add.ll26
-rw-r--r--test/CodeGen/Mips/llvm-ir/sub.ll12
-rw-r--r--test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll11
3 files changed, 30 insertions, 19 deletions
diff --git a/test/CodeGen/Mips/llvm-ir/add.ll b/test/CodeGen/Mips/llvm-ir/add.ll
index eece03091044..a5ecdda94ce2 100644
--- a/test/CodeGen/Mips/llvm-ir/add.ll
+++ b/test/CodeGen/Mips/llvm-ir/add.ll
@@ -24,7 +24,7 @@
; RUN: -check-prefixes=ALL,R2-R6,GP64
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefixes=ALL,R2-R6,GP64
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -O2 | FileCheck %s \
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -O2 -verify-machineinstrs | FileCheck %s \
; RUN: -check-prefixes=ALL,MMR6,MM32
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \
; RUN: -check-prefixes=ALL,MMR6,MM32
@@ -117,7 +117,7 @@ entry:
; GP64: daddu $2, $4, $5
- ; MM32: addu $3, $5, $7
+ ; MM32: addu16 $3, $5, $7
; MM32: sltu $[[T0:[0-9]+]], $3, $7
; MM32: addu $[[T1:[0-9]+]], $[[T0]], $6
; MM32: addu $2, $4, $[[T1]]
@@ -158,16 +158,16 @@ entry:
; MM32: addu $[[T1:[0-9]+]], $7, $[[T0]]
; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
; MM32: lw $[[T3:[0-9]+]], 24($sp)
- ; MM32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
- ; MM32: addu $[[T5:[0-9]+]], $6, $[[T4]]
+ ; MM32: addu16 $[[T4:[0-9]+]], $[[T2]], $[[T3]]
+ ; MM32: addu16 $[[T5:[0-9]+]], $6, $[[T4]]
; MM32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
; MM32: lw $[[T7:[0-9]+]], 20($sp)
- ; MM32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]]
+ ; MM32: addu16 $[[T8:[0-9]+]], $[[T6]], $[[T7]]
; MM32: lw $[[T9:[0-9]+]], 16($sp)
- ; MM32: addu $[[T10:[0-9]+]], $5, $[[T8]]
+ ; MM32: addu16 $[[T10:[0-9]+]], $5, $[[T8]]
; MM32: sltu $[[T11:[0-9]+]], $[[T10]], $[[T7]]
; MM32: addu $[[T12:[0-9]+]], $[[T11]], $[[T9]]
- ; MM32: addu $[[T13:[0-9]+]], $4, $[[T12]]
+ ; MM32: addu16 $[[T13:[0-9]+]], $4, $[[T12]]
; MM32: move $4, $[[T5]]
; MM32: move $5, $[[T1]]
@@ -289,12 +289,12 @@ define signext i128 @add_i128_4(i128 signext %a) {
; MM32: addiu $[[T0:[0-9]+]], $7, 4
; MM32: li16 $[[T1:[0-9]+]], 4
; MM32: sltu $[[T1]], $[[T0]], $[[T1]]
- ; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]]
+ ; MM32: addu16 $[[T2:[0-9]+]], $6, $[[T1]]
; MM32: li16 $[[T1]], 0
; MM32: sltu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
- ; MM32: addu $[[T3]], $5, $[[T3]]
+ ; MM32: addu16 $[[T3]], $5, $[[T3]]
; MM32: sltu $[[T1]], $[[T3]], $[[T1]]
- ; MM32: addu $[[T1]], $4, $[[T1]]
+ ; MM32: addu16 $[[T1]], $4, $[[T1]]
; MM32: move $4, $[[T2]]
; MM32: move $5, $[[T0]]
@@ -419,12 +419,12 @@ define signext i128 @add_i128_3(i128 signext %a) {
; MM32: addiu $[[T0:[0-9]+]], $7, 3
; MM32: li16 $[[T1:[0-9]+]], 3
; MM32: sltu $[[T1]], $[[T0]], $[[T1]]
- ; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]]
+ ; MM32: addu16 $[[T2:[0-9]+]], $6, $[[T1]]
; MM32: li16 $[[T3:[0-9]+]], 0
; MM32: sltu $[[T4:[0-9]+]], $[[T2]], $[[T3]]
- ; MM32: addu $[[T4]], $5, $[[T4]]
+ ; MM32: addu16 $[[T4]], $5, $[[T4]]
; MM32: sltu $[[T5:[0-9]+]], $[[T4]], $[[T3]]
- ; MM32: addu $[[T5]], $4, $[[T5]]
+ ; MM32: addu16 $[[T5]], $4, $[[T5]]
; MM32: move $4, $[[T2]]
; MM32: move $5, $[[T0]]
diff --git a/test/CodeGen/Mips/llvm-ir/sub.ll b/test/CodeGen/Mips/llvm-ir/sub.ll
index 617ab3c1a21c..a730063c552f 100644
--- a/test/CodeGen/Mips/llvm-ir/sub.ll
+++ b/test/CodeGen/Mips/llvm-ir/sub.ll
@@ -10,7 +10,7 @@
; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM
-; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
; RUN: -check-prefixes=GP32-MM,GP32,MM
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefixes=GP32-MM,GP32,MM
@@ -100,7 +100,7 @@ define signext i64 @sub_i64(i64 signext %a, i64 signext %b) {
entry:
; ALL-LABEL: sub_i64:
- ; GP32: subu $3, $5, $7
+ ; GP32-NOT-MM subu $3, $5, $7
; GP32: sltu $[[T0:[0-9]+]], $5, $7
; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6
; GP32: subu $2, $4, $[[T1]]
@@ -138,13 +138,13 @@ entry:
; GP32-MM: lw $[[T4:[0-9]+]], 24($sp)
; GP32-MM: lw $[[T5:[0-9]+]], 28($sp)
; GP32-MM: subu $[[T1]], $7, $[[T5]]
- ; GP32-MM: subu $[[T3]], $[[T6:[0-9]+]], $[[T3]]
+ ; GP32-MM: subu16 $[[T3]], $[[T6:[0-9]+]], $[[T3]]
; GP32-MM: sltu $[[T6]], $6, $[[T4]]
- ; GP32-MM: addu $[[T0]], $[[T6]], $[[T0]]
- ; GP32-MM: subu $[[T0]], $5, $[[T0]]
+ ; GP32-MM: addu16 $[[T0]], $[[T6]], $[[T0]]
+ ; GP32-MM: subu16 $[[T0]], $5, $[[T0]]
; GP32-MM: sltu $[[T6]], $7, $[[T5]]
; GP32-MM: addu $[[T6]], $[[T6]], $[[T4]]
- ; GP32-MM: subu $[[T6]], $6, $[[T6]]
+ ; GP32-MM: subu16 $[[T6]], $6, $[[T6]]
; GP32-MM: move $[[T2]], $[[T1]]
; GP64: dsubu $3, $5, $7
diff --git a/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll b/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll
new file mode 100644
index 000000000000..b92554854c04
--- /dev/null
+++ b/test/CodeGen/Mips/micromips-sizereduction/micromips-lwsp-swsp.ll
@@ -0,0 +1,11 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips -asm-show-inst -verify-machineinstrs < %s | FileCheck %s
+
+; Function Attrs: nounwind
+define i32 @function1(i32 (i32)* %f) {
+entry:
+; CHECK-LABEL: function1:
+; CHECK: SWSP_MM
+; CHECK: LWSP_MM
+ %call = call i32 %f(i32 0)
+ ret i32 0
+}
generated by cgit v1.3 (git 2.53.0) at 2026-09-05 08:22:21 +0000