vendor/llvm/llvm-release_39-r276489

126 files changed, 4178 insertions, 872 deletions

diff --git a/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll
index aae914ecc435..3be596f9a531 100644
--- a/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll
+++ b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -march=ppc64 | FileCheck %s
+; RUN: llc < %s -march=ppc64 -O1 | FileCheck %s
+; RUN: llc < %s -march=ppc64 | FileCheck --check-prefix=CHECK-OPT  %s
 
         %struct.__db_region = type { %struct.__mutex_t, [4 x i8], %struct.anon, i32, [1 x i32] }
         %struct.__mutex_t = type { i32 }
@@ -15,6 +16,24 @@ entry:
 ; CHECK: @foo
 ; CHECK: lwzx
 ; CHECK: blr
+; CHECK-OPT: @foo
+; CHECK-OPT: lwz
+; CHECK-OPT: blr
 }
 
+define signext i32 @test(i32* noalias nocapture readonly %b, i32 signext %n)  {
+entry:
+  %idxprom = sext i32 %n to i64
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 %idxprom
+  %0 = load i32, i32* %arrayidx, align 4
+  %mul = mul nsw i32 %0, 7
+  ret i32 %mul
+
+; CHECK-OPT: @test
+; CHECK-OPT: lwzx
+; CHECK-OPT: blr
+
+}
+
+
 declare i32 @bork(...)
diff --git a/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll
index 01c83cb4bcbe..e1d19a7b246a 100644
--- a/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll
+++ b/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll
@@ -12,7 +12,7 @@
 	%struct.objc_selector = type opaque
 	%struct.pthread_mutex_t = type { i32, [40 x i8] }
 	%struct.pthread_rwlock_t = type { i32, [124 x i8] }
-external constant %struct.__builtin_CFString		; <%struct.__builtin_CFString*>:0 [#uses=1]
+@0 = external constant %struct.__builtin_CFString		; <%struct.__builtin_CFString*>:0 [#uses=1]
 
 define void @"-[PFTPersistentSymbols saveSymbolWithName:address:path:lineNumber:flags:owner:]"(%struct.PFTPersistentSymbols* %self, %struct.objc_selector* %_cmd, %struct.NSArray* %name, i64 %address, %struct.NSArray* %path, i32 %lineNumber, i64 %flags, %struct..0objc_object* %owner) nounwind  {
 entry:
diff --git a/test/CodeGen/PowerPC/2008-07-15-Bswap.ll b/test/CodeGen/PowerPC/2008-07-15-Bswap.ll
index b271048fd045..ab1973fa429c 100644
--- a/test/CodeGen/PowerPC/2008-07-15-Bswap.ll
+++ b/test/CodeGen/PowerPC/2008-07-15-Bswap.ll
@@ -68,8 +68,6 @@ declare void @_Z33LoopFilter_Internal_FilterChromaHPhiiiiii(i8*, i32, i32, i32,
 
 declare void @_Z42LoopFilter_Internal_filter_macroblock_lumaPK14LoopFilterInfoPhS2_iiiPK30PerMacroblockBoundaryStrengthsjj(%struct.LoopFilterInfo*, i8*, i8*, i32, i32, i32, %struct.PerMacroblockBoundaryStrengths*, i32, i32) nounwind 
 
-declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) nounwind 
-
 declare i32 @_Z40LoopFilter_Internal_FilterLumaPlaneMBAFFPK14LoopFilterInfojjj(%struct.LoopFilterInfo*, i32, i32, i32) nounwind 
 
 declare void @_Z18LoopFilter_DestroyP14LoopFilterInfo(%struct.LoopFilterInfo*)
@@ -86,8 +84,6 @@ declare void @jvtDisposePTRMemAligned(i8*)
 
 declare void @_Z31LoopFilter_Internal_ResetTablesP14LoopFilterInfo(%struct.LoopFilterInfo*) nounwind 
 
-declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind 
-
 define i32 @_Z60LoopFilter_Internal_CalculateBoundaryStrengths_MbaffFramePicPK14LoopFilterInfoP22FrameMotionVectorCachejj(%struct.LoopFilterInfo* %lfiPtr, %struct.FrameMotionVectorCache* %frameMotionVectorCachePtr, i32 %mbY_min, i32 %mbY_maxPlus1) nounwind  {
 entry:
 	icmp ult i32 %mbY_min, %mbY_maxPlus1		; <i1>:0 [#uses=1]
@@ -383,4 +379,3 @@ declare i32 @_Z22LoopFilter_FilterFrameP14LoopFilterInfoP11FramePixelsP22FrameMo
 
 declare void @_Z34LF_Threading2_ProcessTasks_WrapperPv(i8*)
 
-declare void @llvm.memset.i64(i8*, i8, i64, i32) nounwind 
diff --git a/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll b/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll
index 1ba11d3fd036..160b26e9078d 100644
--- a/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll
+++ b/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll
@@ -6,7 +6,7 @@
 @_cmd = constant %cmd.type zeroinitializer
 
 ; CHECK:      .globl __cmd
-; CHECK-NEXT: .align 3
+; CHECK-NEXT: .p2align 3
 ; CHECK-NEXT: __cmd:
 ; CHECK-NEXT: .byte 0
 
diff --git a/test/CodeGen/PowerPC/2012-11-16-mischedcall.ll b/test/CodeGen/PowerPC/2012-11-16-mischedcall.ll
index 35e3fdd26e72..dbc521fb8f1f 100644
--- a/test/CodeGen/PowerPC/2012-11-16-mischedcall.ll
+++ b/test/CodeGen/PowerPC/2012-11-16-mischedcall.ll
@@ -8,10 +8,10 @@ declare void @init() nounwind
 
 declare void @clock() nounwind
 
-; CHECK: %entry
+; CHECK: mflr 0
 ; CHECK: fmr 31, 1
 ; CHECK: bl init
-define void @s332(double %t) nounwind {
+define double @s332(double %t) nounwind {
 entry:
   tail call void @init()
   tail call void @clock() nounwind
@@ -29,5 +29,7 @@ for.body4:                                        ; preds = %for.cond2
 
 L20:                                              ; preds = %for.body4, %for.cond2
   %index.0 = phi i32 [ -2, %for.cond2 ], [ %i.0, %for.body4 ]
-  unreachable
+  %index.d = sitofp i32 %index.0 to double
+  %retval = fadd double %t, %index.d
+  ret double %retval
 }
diff --git a/test/CodeGen/PowerPC/2016-04-16-ADD8TLS.ll b/test/CodeGen/PowerPC/2016-04-16-ADD8TLS.ll
new file mode 100644
index 000000000000..c0b48d30bd48
--- /dev/null
+++ b/test/CodeGen/PowerPC/2016-04-16-ADD8TLS.ll
@@ -0,0 +1,43 @@
+; RUN: llc <%s | FileCheck %s
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@x = external thread_local global i32, align 4
+
+; Function Attrs: nounwind
+; CHECK-NOT: add [[REG1:[0-9]+]], 0, x@tls
+define void @f() {
+  %1 = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "nop", "={r3},={r4},={r5},={r6},={r7},={r8},={r9},={r10},={r11},={r12},={r14},={r15},={r16},={r17},={r18},={r19},={r20},={r21},={r22},={r23},={r24},={r25},={r26},={r27},={r28},={r29},={r30},~{memory}"()
+  %2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 0
+  %3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 1
+  %4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 2
+  %5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 3
+  %6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 4
+  %7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 5
+  %8 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 6
+  %9 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 7
+  %10 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 8
+  %11 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 9
+  %12 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 10
+  %13 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 11
+  %14 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 12
+  %15 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 13
+  %16 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 14
+  %17 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 15
+  %18 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 16
+  %19 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 17
+  %20 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 18
+  %21 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 19
+  %22 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 20
+  %23 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 21
+  %24 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 22
+  %25 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 23
+  %26 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 24
+  %27 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 25
+  %28 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 26
+  %29 = load i32, i32* @x, align 4
+  %30 = add nsw i32 %29, 1
+  store i32 %30, i32* @x, align 4
+  tail call void asm sideeffect "nop", "{r3},{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r14},{r15},{r16},{r17},{r18},{r19},{r20},{r21},{r22},{r23},{r24},{r25},{r26},{r27},{r28},{r29},{r30},~{memory}"(i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, i32 %14, i32 %15, i32 %16, i32 %17, i32 %18, i32 %19, i32 %20, i32 %21, i32 %22, i32 %23, i32 %24, i32 %25, i32 %26, i32 %27, i32 %28)
+  ret void
+}
diff --git a/test/CodeGen/PowerPC/2016-04-17-combine.ll b/test/CodeGen/PowerPC/2016-04-17-combine.ll
new file mode 100644
index 000000000000..7ad943cf35fe
--- /dev/null
+++ b/test/CodeGen/PowerPC/2016-04-17-combine.ll
@@ -0,0 +1,26 @@
+; RUN: llc <%s | FileCheck %s
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+; PR27390 crasher
+
+%typ = type { i32, i32 }
+
+; On release builds, it doesn't crash, spewing nonsense instead.
+; To make sure it works, check that and is still alive.
+; CHECK: and
+; Also, in release, it emits a COPY from a 32-bit register to
+; a 64-bit register, which happens to be emitted as cror [!]
+; by the confused CodeGen.  Just to be sure, check there isn't one.
+; CHECK-NOT: cror
+; Function Attrs: uwtable
+define signext i32 @_Z8access_pP1Tc(%typ* %p, i8 zeroext %type) {
+  %b = getelementptr inbounds %typ, %typ* %p, i64 0, i32 1
+  %1 = load i32, i32* %b, align 4
+  %2 = ptrtoint i32* %b to i64
+  %3 = and i64 %2, -35184372088833
+  %4 = inttoptr i64 %3 to i32*
+  %_msld = load i32, i32* %4, align 4
+  %zzz = add i32 %1,  %_msld
+  ret i32 %zzz
+}
diff --git a/test/CodeGen/PowerPC/2016-04-28-setjmp.ll b/test/CodeGen/PowerPC/2016-04-28-setjmp.ll
new file mode 100644
index 000000000000..09c0fa7ba972
--- /dev/null
+++ b/test/CodeGen/PowerPC/2016-04-28-setjmp.ll
@@ -0,0 +1,48 @@
+; RUN: llc -filetype=obj <%s | llvm-objdump --disassemble - | FileCheck %s
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@ptr = common global i8* null, align 8
+
+; Verify there's no junk between these two instructions from misemitted
+; EH_SjLj_Setup.
+
+; CHECK: li 3, 1
+; CHECK-NEXT: b .+4
+
+define void @h() nounwind {
+  %1 = load i8**, i8*** bitcast (i8** @ptr to i8***), align 8
+  %2 = tail call i8* @llvm.frameaddress(i32 0)
+  store i8* %2, i8** %1, align 8
+  %3 = tail call i8* @llvm.stacksave()
+  %4 = getelementptr inbounds i8*, i8** %1, i64 2
+  store i8* %3, i8** %4, align 8
+  %5 = bitcast i8** %1 to i8*
+  %6 = tail call i32 @llvm.eh.sjlj.setjmp(i8* %5)
+  %7 = icmp eq i32 %6, 0
+  br i1 %7, label %9, label %8
+
+; <label>:8:                                      ; preds = %0
+  tail call void @g()
+  br label %10
+
+; <label>:9:                                      ; preds = %0
+  tail call void @f()
+  br label %10
+
+; <label>:10:                                     ; preds = %9, %8
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare i8* @llvm.frameaddress(i32)
+
+; Function Attrs: nounwind
+declare i8* @llvm.stacksave()
+
+; Function Attrs: nounwind
+declare i32 @llvm.eh.sjlj.setjmp(i8*)
+
+declare void @g()
+
+declare void @f()
diff --git a/test/CodeGen/PowerPC/BreakableToken-reduced.ll b/test/CodeGen/PowerPC/BreakableToken-reduced.ll
index 2077dbb820f7..992d2aac4a58 100644
--- a/test/CodeGen/PowerPC/BreakableToken-reduced.ll
+++ b/test/CodeGen/PowerPC/BreakableToken-reduced.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -enable-shrink-wrap=true %s -o - | FileCheck %s --check-prefix=CHECK
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -enable-shrink-wrap=true %s -o - | FileCheck %s
 ;
 ; Test the use of a non-R0 register to save/restore the LR in function 
 ; prologue/epilogue.
diff --git a/test/CodeGen/PowerPC/aantidep-def-ec.mir b/test/CodeGen/PowerPC/aantidep-def-ec.mir
index d1cb6782f038..809d3693af60 100644
--- a/test/CodeGen/PowerPC/aantidep-def-ec.mir
+++ b/test/CodeGen/PowerPC/aantidep-def-ec.mir
@@ -45,6 +45,7 @@ name:            mm_update_next_owner
 alignment:       4
 exposesReturnsTwice: false
 hasInlineAsm:    true
+allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
diff --git a/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir b/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
index e4aaaf30f90f..6f52aa21a775 100644
--- a/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
+++ b/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
@@ -27,6 +27,7 @@ name:            test1
 alignment:       4
 exposesReturnsTwice: false
 hasInlineAsm:    false
+allVRegsAllocated: true
 isSSA:           false
 tracksRegLiveness: true
 tracksSubRegLiveness: false
diff --git a/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll b/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
new file mode 100644
index 000000000000..c57588668d8b
--- /dev/null
+++ b/test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll
@@ -0,0 +1,24 @@
+; RUN: llc %s -mtriple=powerpc64-unknown-linux-gnu -O2 -o - -optimize-regalloc=false -regalloc=fast | FileCheck %s
+
+declare void @func(i8*, i64, i64)
+
+define void @test(i8* %context, i32** %elementArrayPtr, i32 %value) {
+entry:
+  %cmp = icmp eq i32 %value, 0
+  br i1 %cmp, label %lreturn, label %lnext
+
+lnext:
+  %elementArray = load i32*, i32** %elementArrayPtr, align 8
+; CHECK: lwz [[LDREG:[0-9]+]], 124(1)                   # 4-byte Folded Reload
+; CHECK: # implicit-def: %X[[TEMPREG:[0-9]+]]
+  %element = load i32, i32* %elementArray, align 4
+; CHECK: mr [[TEMPREG]], [[LDREG]]
+; CHECK: clrldi   4, [[TEMPREG]], 32
+  %element.ext = zext i32 %element to i64
+  %value.ext = zext i32 %value to i64
+  call void @func(i8* %context, i64 %value.ext, i64 %element.ext)
+  br label %lreturn
+
+lreturn:
+  ret void
+}
diff --git a/test/CodeGen/PowerPC/align.ll b/test/CodeGen/PowerPC/align.ll
index 0797ca8d0be8..52ac2c12e03a 100644
--- a/test/CodeGen/PowerPC/align.ll
+++ b/test/CodeGen/PowerPC/align.ll
@@ -9,33 +9,33 @@
 ; no alignment
 
 @c = global i16 2
-;ELF: .align 1
+;ELF: .p2align 1
 ;ELF: c:
-;DARWIN: .align 1
+;DARWIN: .p2align 1
 ;DARWIN: _c:
 
 @d = global i32 3
-;ELF: .align 2
+;ELF: .p2align 2
 ;ELF: d:
-;DARWIN: .align 2
+;DARWIN: .p2align 2
 ;DARWIN: _d:
 
 @e = global i64 4
-;ELF: .align 3
+;ELF: .p2align 3
 ;ELF: e
-;DARWIN: .align 3
+;DARWIN: .p2align 3
 ;DARWIN: _e:
 
 @f = global float 5.0
-;ELF: .align 2
+;ELF: .p2align 2
 ;ELF: f:
-;DARWIN: .align 2
+;DARWIN: .p2align 2
 ;DARWIN: _f:
 
 @g = global double 6.0
-;ELF: .align 3
+;ELF: .p2align 3
 ;ELF: g:
-;DARWIN: .align 3
+;DARWIN: .p2align 3
 ;DARWIN: _g:
 
 @bar = common global [75 x i8] zeroinitializer, align 128
diff --git a/test/CodeGen/PowerPC/andc.ll b/test/CodeGen/PowerPC/andc.ll
new file mode 100644
index 000000000000..8b8eca6bad5b
--- /dev/null
+++ b/test/CodeGen/PowerPC/andc.ll
@@ -0,0 +1,36 @@
+; RUN: llc < %s -mtriple=powerpc64-apple-darwin | FileCheck %s
+
+; TODO: These could use 'andc'.
+
+define i1 @and_cmp1(i32 %x, i32 %y) {
+; CHECK-LABEL: and_cmp1:
+; CHECK:       ; BB#0:
+; CHECK-NEXT:    and r2, r3, r4
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    cmpw cr0, r2, r4
+; CHECK-NEXT:    bclr 12, 2, 0
+; CHECK-NEXT:  ; BB#1:
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+;
+  %and = and i32 %x, %y
+  %cmp = icmp eq i32 %and, %y
+  ret i1 %cmp
+}
+
+define i1 @and_cmp_const(i32 %x) {
+; CHECK-LABEL: and_cmp_const:
+; CHECK:       ; BB#0:
+; CHECK-NEXT:    andi. r2, r3, 43
+; CHECK-NEXT:    li r3, 1
+; CHECK-NEXT:    cmpwi r2, 43
+; CHECK-NEXT:    bclr 12, 2, 0
+; CHECK-NEXT:  ; BB#1:
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    blr
+;
+  %and = and i32 %x, 43
+  %cmp = icmp eq i32 %and, 43
+  ret i1 %cmp
+}
+
diff --git a/test/CodeGen/PowerPC/asm-constraints.ll b/test/CodeGen/PowerPC/asm-constraints.ll
index 2d9b0eb591d3..e7b6366bf995 100644
--- a/test/CodeGen/PowerPC/asm-constraints.ll
+++ b/test/CodeGen/PowerPC/asm-constraints.ll
@@ -1,5 +1,10 @@
 ; RUN: llc < %s -mcpu=pwr8 | FileCheck %s
 
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+; Function Attrs: nounwind
+; Check that we accept 'U' and 'X' constraints.
 ; Generated from following C code:
 ;
 ; void foo (int result, char *addr) {
@@ -12,34 +17,57 @@
 ;     : "m"(*addr) : "memory", "cr0");
 ; }
 
-target datalayout = "e-m:e-i64:64-n32:64"
-target triple = "powerpc64le-unknown-linux-gnu"
-
-; Function Attrs: nounwind
-; Check that we accept 'U' and 'X' constraints.
 define void @foo(i32 signext %result, i8* %addr) #0 {
+
+; CHECK-LABEL: @foo
+; CHECK: ld [[REG:[0-9]+]], 0(4)
+; CHECK: cmpw [[REG]], [[REG]]
+; CHECK: bne- 0, .Ltmp[[TMP:[0-9]+]]
+; CHECK: .Ltmp[[TMP]]:
+; CHECK: isync
+
 entry:
   %result.addr = alloca i32, align 4
   %addr.addr = alloca i8*, align 8
   store i32 %result, i32* %result.addr, align 4
   store i8* %addr, i8** %addr.addr, align 8
   %0 = load i8*, i8** %addr.addr, align 8
-  %1 = call i32 asm sideeffect "ld${1:U}${1:X} $0,$1\0Acmpw $0,$0\0Abne- 1f\0A1: isync\0A", "=r,*m,~{memory},~{cr0}"(i8* %0) #1, !srcloc !1
+  %1 = call i32 asm sideeffect "ld${1:U}${1:X} $0,$1\0Acmpw $0,$0\0Abne- 1f\0A1: isync\0A", "=r,*m,~{memory},~{cr0}"(i8* %0) #1, !srcloc !0
   store i32 %1, i32* %result.addr, align 4
   ret void
 }
 
-; CHECK-LABEL: @foo
-; CHECK: ld [[REG:[0-9]+]], 0(4)
-; CHECK: cmpw [[REG]], [[REG]]
-; CHECK: bne- 0, .Ltmp[[TMP:[0-9]+]]
-; CHECK: .Ltmp[[TMP]]:
-; CHECK: isync
+; Function Attrs: nounwind
+; Check that we accept the 'd' constraint.
+; Generated from the following C code:
+; int foo(double x) {
+;   int64_t result;
+;   __asm__ __volatile__("fctid %0, %1"
+;                        : "=d"(result)
+;                        : "d"(x)
+;                        : /* No clobbers */);
+;   return result;
+; }
+define signext i32 @bar(double %x) #0 {
+
+; CHECK-LABEL: @bar
+; CHECK: fctid 0, 1
+entry:
+  %x.addr = alloca double, align 8
+  %result = alloca i64, align 8
+  store double %x, double* %x.addr, align 8
+  %0 = load double, double* %x.addr, align 8
+  %1 = call i64 asm sideeffect "fctid $0, $1", "=d,d"(double %0) #1, !srcloc !1
+  store i64 %1, i64* %result, align 8
+  %2 = load i64, i64* %result, align 8
+  %conv = trunc i64 %2 to i32
+  ret i32 %conv
+}
 
-attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
-attributes #1 = { nounwind }
 
-!llvm.ident = !{!0}
+attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+attributes #1 = { nounwind }
 
-!0 = !{!"clang version 3.6.0 (trunk 217557)"}
-!1 = !{i32 67, i32 91, i32 110, i32 126}
+!0 = !{i32 67, i32 91, i32 110, i32 126}
+!1 = !{i32 84}
diff --git a/test/CodeGen/PowerPC/asm-printer-topological-order.ll b/test/CodeGen/PowerPC/asm-printer-topological-order.ll
new file mode 100644
index 000000000000..e1e62da4dbc2
--- /dev/null
+++ b/test/CodeGen/PowerPC/asm-printer-topological-order.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+@TestA = alias void (), void ()* @TestC
+@TestB = alias void (), void ()* @TestC
+@TestC = alias void (), void ()* @TestD
+
+define void @TestD() {
+entry:
+  ret void
+}
+
+; CHECK-LABEL: TestD:
+; CHECK: TestC = TestD
+; CHECK-DAG: TestB = TestC
+; CHECK-DAG: TestA = TestC
diff --git a/test/CodeGen/PowerPC/atomics-fences.ll b/test/CodeGen/PowerPC/atomics-fences.ll
index c015fa6eefb0..7682f8a7ef46 100644
--- a/test/CodeGen/PowerPC/atomics-fences.ll
+++ b/test/CodeGen/PowerPC/atomics-fences.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK
-; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc64 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK
+; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc64 -verify-machineinstrs | FileCheck %s
 ; RUN: llc < %s -mtriple=powerpc-apple-darwin -mcpu=440 | FileCheck %s --check-prefix=PPC440
 
 ; Fences
diff --git a/test/CodeGen/PowerPC/available-externally.ll b/test/CodeGen/PowerPC/available-externally.ll
index 53c435995485..6169e3fba995 100644
--- a/test/CodeGen/PowerPC/available-externally.ll
+++ b/test/CodeGen/PowerPC/available-externally.ll
@@ -1,12 +1,12 @@
 ; RUN: llc < %s -relocation-model=static | FileCheck %s -check-prefix=STATIC
-; RUN: llc < %s -relocation-model=pic -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PIC
+; RUN: llc < %s -relocation-model=pic -mtriple=powerpc-apple-darwin9 | FileCheck %s -check-prefix=PIC
 ; RUN: llc < %s -relocation-model=pic -mtriple=powerpc-unknown-linux | FileCheck %s -check-prefix=PICELF
-; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64-apple-darwin8 | FileCheck %s -check-prefix=PIC64
-; RUN: llc < %s -relocation-model=dynamic-no-pic -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=DYNAMIC
-; RUN: llc < %s -relocation-model=dynamic-no-pic -mtriple=powerpc64-apple-darwin8 | FileCheck %s -check-prefix=DYNAMIC64
+; RUN: llc < %s -relocation-model=pic -mtriple=powerpc64-apple-darwin9 | FileCheck %s -check-prefix=PIC64
+; RUN: llc < %s -relocation-model=dynamic-no-pic -mtriple=powerpc-apple-darwin9 | FileCheck %s -check-prefix=DYNAMIC
+; RUN: llc < %s -relocation-model=dynamic-no-pic -mtriple=powerpc64-apple-darwin9 | FileCheck %s -check-prefix=DYNAMIC64
 ; PR4482
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
-target triple = "powerpc-apple-darwin8"
+target triple = "powerpc-apple-darwin9"
 
 define i32 @foo(i64 %x) nounwind {
 entry:
@@ -16,7 +16,7 @@ entry:
 ; STATIC: .subsections_via_symbols
 
 ; PIC: _foo:
-; PIC: bl L_exact_log2$stub
+; PIC: bl _exact_log2
 ; PIC: blr
 
 ; PICELF: foo:
@@ -24,15 +24,15 @@ entry:
 ; PICELF: blr
 
 ; PIC64: _foo:
-; PIC64: bl L_exact_log2$stub
+; PIC64: bl _exact_log2
 ; PIC64: blr
 
 ; DYNAMIC: _foo:
-; DYNAMIC: bl L_exact_log2$stub
+; DYNAMIC: bl _exact_log2
 ; DYNAMIC: blr
 
 ; DYNAMIC64: _foo:
-; DYNAMIC64: bl L_exact_log2$stub
+; DYNAMIC64: bl _exact_log2
 ; DYNAMIC64: blr
 
         %A = call i32 @exact_log2(i64 %x) nounwind
@@ -45,70 +45,7 @@ entry:
 }
 
 
-; PIC: .section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
-; PIC: L_exact_log2$stub:
-; PIC: .indirect_symbol _exact_log2
-; PIC: mflr r0
-; PIC: bcl 20, 31, L_exact_log2$stub$tmp
-
-; PIC: L_exact_log2$stub$tmp:
-; PIC: mflr r11
-; PIC: addis r11, r11, ha16(L_exact_log2$lazy_ptr-L_exact_log2$stub$tmp)
-; PIC: mtlr r0
-; PIC: lwzu r12, lo16(L_exact_log2$lazy_ptr-L_exact_log2$stub$tmp)(r11)
-; PIC: mtctr r12
-; PIC: bctr
-
-; PIC: .section __DATA,__la_symbol_ptr,lazy_symbol_pointers
-; PIC: L_exact_log2$lazy_ptr:
-; PIC: .indirect_symbol _exact_log2
-; PIC: .long dyld_stub_binding_helper
-
 ; PIC: .subsections_via_symbols
 
-; PIC64: .section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
-; PIC64: L_exact_log2$stub:
-; PIC64: .indirect_symbol _exact_log2
-; PIC64: mflr r0
-; PIC64: bcl 20, 31, L_exact_log2$stub$tmp
-
-; PIC64: L_exact_log2$stub$tmp:
-; PIC64: mflr r11
-; PIC64: addis r11, r11, ha16(L_exact_log2$lazy_ptr-L_exact_log2$stub$tmp)
-; PIC64: mtlr r0
-; PIC64: ldu r12, lo16(L_exact_log2$lazy_ptr-L_exact_log2$stub$tmp)(r11)
-; PIC64: mtctr r12
-; PIC64: bctr
-
-; PIC64: .section __DATA,__la_symbol_ptr,lazy_symbol_pointers
-; PIC64: L_exact_log2$lazy_ptr:
-; PIC64: .indirect_symbol _exact_log2
-; PIC64: .quad dyld_stub_binding_helper
 
 ; PIC64: .subsections_via_symbols
-
-; DYNAMIC: .section __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16
-; DYNAMIC: L_exact_log2$stub:
-; DYNAMIC: .indirect_symbol _exact_log2
-; DYNAMIC: lis r11, ha16(L_exact_log2$lazy_ptr)
-; DYNAMIC: lwzu r12, lo16(L_exact_log2$lazy_ptr)(r11)
-; DYNAMIC: mtctr r12
-; DYNAMIC: bctr
-
-; DYNAMIC: .section __DATA,__la_symbol_ptr,lazy_symbol_pointers
-; DYNAMIC: L_exact_log2$lazy_ptr:
-; DYNAMIC: .indirect_symbol _exact_log2
-; DYNAMIC: .long dyld_stub_binding_helper
-
-; DYNAMIC64: .section __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16
-; DYNAMIC64: L_exact_log2$stub:
-; DYNAMIC64: .indirect_symbol _exact_log2
-; DYNAMIC64: lis r11, ha16(L_exact_log2$lazy_ptr)
-; DYNAMIC64: ldu r12, lo16(L_exact_log2$lazy_ptr)(r11)
-; DYNAMIC64: mtctr r12
-; DYNAMIC64: bctr
-
-; DYNAMIC64: .section __DATA,__la_symbol_ptr,lazy_symbol_pointers
-; DYNAMIC64: L_exact_log2$lazy_ptr:
-; DYNAMIC64: .indirect_symbol _exact_log2
-; DYNAMIC64: .quad dyld_stub_binding_helper
diff --git a/test/CodeGen/PowerPC/bdzlr.ll b/test/CodeGen/PowerPC/bdzlr.ll
index d6506044868f..a7c5fa4faa00 100644
--- a/test/CodeGen/PowerPC/bdzlr.ll
+++ b/test/CodeGen/PowerPC/bdzlr.ll
@@ -37,7 +37,8 @@ for.body:                                         ; preds = %for.body.for.body_c
   %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body.for.body_crit_edge ]
   %tt = getelementptr inbounds %struct.lua_TValue.17.692, %struct.lua_TValue.17.692* %0, i64 %indvars.iv, i32 1
   %1 = load i32, i32* %tt, align 4
-  store i32 %1, i32* undef, align 4
+  %2 = add i32 %1, %1
+  store i32 %2, i32* %tt, align 4
   %indvars.iv.next = add i64 %indvars.iv, 1
   %lftr.wideiv = trunc i64 %indvars.iv.next to i32
   %exitcond = icmp eq i32 %lftr.wideiv, %n
diff --git a/test/CodeGen/PowerPC/builtins-ppc-p8vector.ll b/test/CodeGen/PowerPC/builtins-ppc-p8vector.ll
index 37111ef0d89b..7afb1a659b6d 100644
--- a/test/CodeGen/PowerPC/builtins-ppc-p8vector.ll
+++ b/test/CodeGen/PowerPC/builtins-ppc-p8vector.ll
@@ -4,7 +4,9 @@
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-VSX
 
 @vsc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
+@vsc2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
 @vuc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
+@vuc2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16
 @res_vll = common global <2 x i64> zeroinitializer, align 16
 @res_vull = common global <2 x i64> zeroinitializer, align 16
 @res_vsc = common global <16 x i8> zeroinitializer, align 16
@@ -13,54 +15,39 @@
 ; Function Attrs: nounwind
 define void @test1() {
 entry:
-  %__a.addr.i = alloca <16 x i8>, align 16
-  %__b.addr.i = alloca <16 x i8>, align 16
   %0 = load <16 x i8>, <16 x i8>* @vsc, align 16
-  %1 = load <16 x i8>, <16 x i8>* @vsc, align 16
-  store <16 x i8> %0, <16 x i8>* %__a.addr.i, align 16
-  store <16 x i8> %1, <16 x i8>* %__b.addr.i, align 16
-  %2 = load <16 x i8>, <16 x i8>* %__a.addr.i, align 16
-  %3 = load <16 x i8>, <16 x i8>* %__b.addr.i, align 16
-  %4 = call <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8> %2, <16 x i8> %3)
-  store <2 x i64> %4, <2 x i64>* @res_vll, align 16
+  %1 = load <16 x i8>, <16 x i8>* @vsc2, align 16
+  %2 = call <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8> %0, <16 x i8> %1)
+  store <2 x i64> %2, <2 x i64>* @res_vll, align 16
   ret void
 ; CHECK-LABEL: @test1
-; CHECK: lvx [[REG1:[0-9]+]],
-; CHECK: lvx [[REG2:[0-9]+]],
-; CHECK: vbpermq {{[0-9]+}}, [[REG2]], [[REG1]]
+; CHECK: lvx [[REG1:[0-9]+]], 0, 3
+; CHECK: lvx [[REG2:[0-9]+]], 0, 4
+; CHECK: vbpermq {{[0-9]+}}, [[REG1]], [[REG2]]
 ; CHECK-VSX: vbpermq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 }
 
 ; Function Attrs: nounwind
 define void @test2() {
 entry:
-  %__a.addr.i = alloca <16 x i8>, align 16
-  %__b.addr.i = alloca <16 x i8>, align 16
   %0 = load <16 x i8>, <16 x i8>* @vuc, align 16
-  %1 = load <16 x i8>, <16 x i8>* @vuc, align 16
-  store <16 x i8> %0, <16 x i8>* %__a.addr.i, align 16
-  store <16 x i8> %1, <16 x i8>* %__b.addr.i, align 16
-  %2 = load <16 x i8>, <16 x i8>* %__a.addr.i, align 16
-  %3 = load <16 x i8>, <16 x i8>* %__b.addr.i, align 16
-  %4 = call <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8> %2, <16 x i8> %3)
-  store <2 x i64> %4, <2 x i64>* @res_vull, align 16
+  %1 = load <16 x i8>, <16 x i8>* @vuc2, align 16
+  %2 = call <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8> %0, <16 x i8> %1)
+  store <2 x i64> %2, <2 x i64>* @res_vull, align 16
   ret void
 ; CHECK-LABEL: @test2
-; CHECK: lvx [[REG1:[0-9]+]],
-; CHECK: lvx [[REG2:[0-9]+]],
-; CHECK: vbpermq {{[0-9]+}}, [[REG2]], [[REG1]]
+; CHECK: lvx [[REG1:[0-9]+]], 0, 3
+; CHECK: lvx [[REG2:[0-9]+]], 0, 4
+; CHECK: vbpermq {{[0-9]+}}, [[REG1]], [[REG2]]
 ; CHECK-VSX: vbpermq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 }
 
 ; Function Attrs: nounwind
 define void @test3() {
 entry:
-  %__a.addr.i = alloca <16 x i8>, align 16
   %0 = load <16 x i8>, <16 x i8>* @vsc, align 16
-  store <16 x i8> %0, <16 x i8>* %__a.addr.i, align 16
-  %1 = load <16 x i8>, <16 x i8>* %__a.addr.i, align 16
-  %2 = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %1)
-  store <16 x i8> %2, <16 x i8>* @res_vsc, align 16
+  %1 = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %0)
+  store <16 x i8> %1, <16 x i8>* @res_vsc, align 16
   ret void
 ; CHECK-LABEL: @test3
 ; CHECK: lvx [[REG1:[0-9]+]],
@@ -71,12 +58,9 @@ entry:
 ; Function Attrs: nounwind
 define void @test4() {
 entry:
-  %__a.addr.i = alloca <16 x i8>, align 16
   %0 = load <16 x i8>, <16 x i8>* @vuc, align 16
-  store <16 x i8> %0, <16 x i8>* %__a.addr.i, align 16
-  %1 = load <16 x i8>, <16 x i8>* %__a.addr.i, align 16
-  %2 = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %1)
-  store <16 x i8> %2, <16 x i8>* @res_vuc, align 16
+  %1 = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %0)
+  store <16 x i8> %1, <16 x i8>* @res_vuc, align 16
   ret void
 ; CHECK-LABEL: @test4
 ; CHECK: lvx [[REG1:[0-9]+]],
diff --git a/test/CodeGen/PowerPC/cannonicalize-vector-shifts.ll b/test/CodeGen/PowerPC/cannonicalize-vector-shifts.ll
new file mode 100644
index 000000000000..68d4530e81ec
--- /dev/null
+++ b/test/CodeGen/PowerPC/cannonicalize-vector-shifts.ll
@@ -0,0 +1,27 @@
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s
+define <4 x i32> @test1(<4 x i32> %a) {
+entry:
+; CHECK-LABEL: test1
+; CHECK: xxswapd 34, 34
+  %vecins6 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
+  ret <4 x i32> %vecins6
+}
+
+define <8 x i16> @test2(<8 x i16> %a) #0 {
+entry:
+; CHECK-LABEL: test2
+; CHECK: xxswapd 34, 34
+  %vecins14 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+  ret <8 x i16> %vecins14
+}
+
+define <16 x i8> @test3(<16 x i8> %a) #0 {
+entry:
+; CHECK-LABEL: test3
+; CHECK: xxswapd 34, 34
+  %vecins30 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  ret <16 x i8> %vecins30
+}
diff --git a/test/CodeGen/PowerPC/code-align.ll b/test/CodeGen/PowerPC/code-align.ll
index 19d1b236ce0d..a6fd37421064 100644
--- a/test/CodeGen/PowerPC/code-align.ll
+++ b/test/CodeGen/PowerPC/code-align.ll
@@ -22,9 +22,9 @@ entry:
 ; GENERIC-LABEL: .globl  foo
 ; BASIC-LABEL: .globl  foo
 ; PWR-LABEL: .globl  foo
-; GENERIC: .align  2
-; BASIC: .align  4
-; PWR: .align  4
+; GENERIC: .p2align  2
+; BASIC: .p2align  4
+; PWR: .p2align  4
 ; GENERIC: @foo
 ; BASIC: @foo
 ; PWR: @foo
@@ -41,9 +41,9 @@ entry:
 ; GENERIC: mtctr
 ; BASIC: mtctr
 ; PWR: mtctr
-; GENERIC-NOT: .align
-; BASIC: .align  4
-; PWR: .align  4
+; GENERIC-NOT: .p2align
+; BASIC: .p2align  4
+; PWR: .p2align  4
 ; GENERIC: lwzu
 ; BASIC: lwzu
 ; PWR: lwzu
@@ -83,9 +83,9 @@ entry:
 ; GENERIC: mtctr
 ; BASIC: mtctr
 ; PWR: mtctr
-; GENERIC-NOT: .align
-; BASIC: .align  4
-; PWR: .align  5
+; GENERIC-NOT: .p2align
+; BASIC: .p2align  4
+; PWR: .p2align  5
 ; GENERIC: bdnz
 ; BASIC: bdnz
 ; PWR: bdnz
@@ -105,6 +105,48 @@ for.end:                                          ; preds = %for.body
   ret void
 }
 
+; Function Attrs: nounwind
+define void @test_minsize(i32 signext %x, i32* nocapture %a) #2 {
+entry:
+  br label %vector.body
+
+; GENERIC-LABEL: @test_minsize
+; BASIC-LABEL: @test_minsize
+; PWR-LABEL: @test_minsize
+; GENERIC: mtctr
+; BASIC: mtctr
+; PWR: mtctr
+; GENERIC-NOT: .p2align
+; BASIC-NOT: .p2align
+; PWR-NOT: .p2align
+; GENERIC: lwzu
+; BASIC: lwzu
+; PWR: lwzu
+; GENERIC: bdnz
+; BASIC: bdnz
+; PWR: bdnz
+
+vector.body:                                      ; preds = %vector.body, %entry
+  %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
+  %induction45 = or i64 %index, 1
+  %0 = getelementptr inbounds i32, i32* %a, i64 %index
+  %1 = getelementptr inbounds i32, i32* %a, i64 %induction45
+  %2 = load i32, i32* %0, align 4
+  %3 = load i32, i32* %1, align 4
+  %4 = add nsw i32 %2, 4
+  %5 = add nsw i32 %3, 4
+  %6 = mul nsw i32 %4, 3
+  %7 = mul nsw i32 %5, 3
+  store i32 %6, i32* %0, align 4
+  store i32 %7, i32* %1, align 4
+  %index.next = add i64 %index, 2
+  %8 = icmp eq i64 %index.next, 2048
+  br i1 %8, label %for.end, label %vector.body
+
+for.end:                                          ; preds = %vector.body
+  ret void
+}
 attributes #0 = { nounwind readnone }
 attributes #1 = { nounwind }
+attributes #2 = { nounwind minsize}
 
diff --git a/test/CodeGen/PowerPC/combine-to-pre-index-store-crash.ll b/test/CodeGen/PowerPC/combine-to-pre-index-store-crash.ll
new file mode 100644
index 000000000000..9bd0dd874b4a
--- /dev/null
+++ b/test/CodeGen/PowerPC/combine-to-pre-index-store-crash.ll
@@ -0,0 +1,25 @@
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+; CHECK-LABEL: TestFoo:
+; CHECK: std
+; CHECK: bl TestBar
+; CHECK: stbu
+; CHECK: std
+; CHECK: blr
+
+%StructA = type <{ i64, { i64, i64 }, { i64, i64 } }>
+
+define void @TestFoo(%StructA* %this) {
+  %tmp = getelementptr inbounds %StructA, %StructA* %this, i64 0, i32 1
+  %tmp11 = getelementptr inbounds %StructA, %StructA* %this, i64 0, i32 1, i32 1
+  %tmp12 = bitcast { i64, i64 }* %tmp to i64**
+  store i64* %tmp11, i64** %tmp12
+  call void @TestBar()
+  %tmp13 = getelementptr inbounds %StructA, %StructA* %this, i64 0, i32 2, i32 1
+  store i64* %tmp13, i64** undef
+  %.cast.i.i.i = bitcast i64* %tmp13 to i8*
+  store i8 0, i8* %.cast.i.i.i
+  ret void
+}
+
+declare void @TestBar()
diff --git a/test/CodeGen/PowerPC/crsave.ll b/test/CodeGen/PowerPC/crsave.ll
index 8121e1b6e639..a079e7f1585e 100644
--- a/test/CodeGen/PowerPC/crsave.ll
+++ b/test/CodeGen/PowerPC/crsave.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC32
 ; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 < %s | FileCheck %s -check-prefix=PPC64
+; RUN: llc -O0 -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s -check-prefix=PPC64-ELFv2
 
 declare void @foo()
 
@@ -60,3 +61,22 @@ entry:
 ; PPC64: mtocrf 16, 12
 ; PPC64: mtocrf 8, 12
 
+; Generate mfocrf in prologue when we need to save 1 nonvolatile CR field
+define void @cloberOneNvCrField() {
+entry:
+  tail call void asm sideeffect "# clobbers", "~{cr2}"()
+  ret void
+
+; PPC64-ELFv2-LABEL: @cloberOneNvCrField
+; PPC64-ELFv2: mfocrf [[REG1:[0-9]+]], 32
+}
+
+; Generate mfcr in prologue when we need to save all nonvolatile CR field
+define void @cloberAllNvCrField() {
+entry:
+  tail call void asm sideeffect "# clobbers", "~{cr2},~{cr3},~{cr4}"()
+  ret void
+
+; PPC64-ELFv2-LABEL: @cloberAllNvCrField
+; PPC64-ELFv2: mfcr [[REG1:[0-9]+]]
+}
diff --git a/test/CodeGen/PowerPC/crypto_bifs.ll b/test/CodeGen/PowerPC/crypto_bifs.ll
index f58935b85b66..62247e8118f4 100644
--- a/test/CodeGen/PowerPC/crypto_bifs.ll
+++ b/test/CodeGen/PowerPC/crypto_bifs.ll
@@ -1,6 +1,7 @@
 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+crypto < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
 ; FIXME: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
 ; FIXME: The original intent was to add a check-next for the blr after every check.
 ; However, this currently fails since we don't eliminate stores of the unused
diff --git a/test/CodeGen/PowerPC/ctr-minmaxnum.ll b/test/CodeGen/PowerPC/ctr-minmaxnum.ll
new file mode 100644
index 000000000000..cecf620124c1
--- /dev/null
+++ b/test/CodeGen/PowerPC/ctr-minmaxnum.ll
@@ -0,0 +1,231 @@
+; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -mcpu=a2q < %s | FileCheck %s --check-prefix=QPX
+target triple = "powerpc64-unknown-linux-gnu"
+
+declare float @fabsf(float)
+
+declare float @fminf(float, float)
+declare double @fmin(double, double)
+declare float @llvm.minnum.f32(float, float)
+declare double @llvm.minnum.f64(double, double)
+
+declare float @fmaxf(float, float)
+declare double @fmax(double, double)
+declare float @llvm.maxnum.f32(float, float)
+declare double @llvm.maxnum.f64(double, double)
+
+declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>)
+declare <4 x double> @llvm.minnum.v4f64(<4 x double>, <4 x double>)
+declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>)
+declare <4 x double> @llvm.maxnum.v4f64(<4 x double>, <4 x double>)
+
+define void @test1(float %f, float* %fp) {
+entry:
+  br label %loop_body
+
+loop_body:
+  %invar_address.dim.0.01 = phi i64 [ 0, %entry ], [ %1, %loop_body ]
+  %0 = call float @llvm.minnum.f32(float %f, float 1.0)
+  store float %0, float* %fp, align 4
+  %1 = add i64 %invar_address.dim.0.01, 1
+  %2 = icmp eq i64 %1, 2
+  br i1 %2, label %loop_exit, label %loop_body
+
+loop_exit:
+  ret void
+}
+
+; CHECK-LABEL: test1:
+; CHECK-NOT: mtctr
+; CHECK: bl fminf
+
+define void @test1v(<4 x float> %f, <4 x float>* %fp) {
+entry:
+  br label %loop_body
+
+loop_body:
+  %invar_address.dim.0.01 = phi i64 [ 0, %entry ], [ %1, %loop_body ]
+  %0 = call <4 x float> @llvm.minnum.v4f32(<4 x float> %f, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)
+  store <4 x float> %0, <4 x float>* %fp, align 16
+  %1 = add i64 %invar_address.dim.0.01, 1
+  %2 = icmp eq i64 %1, 2
+  br i1 %2, label %loop_exit, label %loop_body
+
+loop_exit:
+  ret void
+}
+
+; CHECK-LABEL: test1v:
+; CHECK-NOT: mtctr
+; CHECK: bl fminf
+
+; QPX-LABEL: test1v:
+; QPX: mtctr
+; QPX-NOT: bl fminf
+; QPX: blr
+
+define void @test1a(float %f, float* %fp) {
+entry:
+  br label %loop_body
+
+loop_body:
+  %invar_address.dim.0.01 = phi i64 [ 0, %entry ], [ %1, %loop_body ]
+  %0 = call float @fminf(float %f, float 1.0) readnone
+  store float %0, float* %fp, align 4
+  %1 = add i64 %invar_address.dim.0.01, 1
+  %2 = icmp eq i64 %1, 2
+  br i1 %2, label %loop_exit, label %loop_body
+
+loop_exit:
+  ret void
+}
+
+; CHECK-LABEL: test1a:
+; CHECK-NOT: mtctr
+; CHECK: bl fminf
+
+define void @test2(float %f, float* %fp) {
+entry:
+  br label %loop_body
+
+loop_body:
+  %invar_address.dim.0.01 = phi i64 [ 0, %entry ], [ %1, %loop_body ]
+  %0 = call float @llvm.maxnum.f32(float %f, float 1.0)
+  store float %0, float* %fp, align 4
+  %1 = add i64 %invar_address.dim.0.01, 1
+  %2 = icmp eq i64 %1, 2
+  br i1 %2, label %loop_exit, label %loop_body
+
+loop_exit:
+  ret void
+}
+
+; CHECK-LABEL: test2:
+; CHECK-NOT: mtctr
+; CHECK: bl fmaxf
+
+define void @test2v(<4 x double> %f, <4 x double>* %fp) {
+entry:
+  br label %loop_body
+
+loop_body:
+  %invar_address.dim.0.01 = phi i64 [ 0, %entry ], [ %1, %loop_body ]
+  %0 = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %f, <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>)
+  store <4 x double> %0, <4 x double>* %fp, align 16
+  %1 = add i64 %invar_address.dim.0.01, 1
+  %2 = icmp eq i64 %1, 2
+  br i1 %2, label %loop_exit, label %loop_body
+
+loop_exit:
+  ret void
+}
+
+; CHECK-LABEL: test2v:
+; CHECK-NOT: mtctr
+; CHECK: bl fmax
+
+; QPX-LABEL: test2v:
+; QPX: mtctr
+; QPX-NOT: bl fmax
+; QPX: blr
+
+define void @test2a(float %f, float* %fp) {
+entry:
+  br label %loop_body
+
+loop_body:
+  %invar_address.dim.0.01 = phi i64 [ 0, %entry ], [ %1, %loop_body ]
+  %0 = call float @fmaxf(float %f, float 1.0) readnone
+  store float %0, float* %fp, align 4
+  %1 = add i64 %invar_address.dim.0.01, 1
+  %2 = icmp eq i64 %1, 2
+  br i1 %2, label %loop_exit, label %loop_body
+
+loop_exit:
+  ret void
+}
+
+; CHECK-LABEL: test2a:
+; CHECK-NOT: mtctr
+; CHECK: bl fmaxf
+
+define void @test3(double %f, double* %fp) {
+entry:
+  br label %loop_body
+
+loop_body:
+  %invar_address.dim.0.01 = phi i64 [ 0, %entry ], [ %1, %loop_body ]
+  %0 = call double @llvm.minnum.f64(double %f, double 1.0)
+  store double %0, double* %fp, align 8
+  %1 = add i64 %invar_address.dim.0.01, 1
+  %2 = icmp eq i64 %1, 2
+  br i1 %2, label %loop_exit, label %loop_body
+
+loop_exit:
+  ret void
+}
+
+; CHECK-LABEL: test3:
+; CHECK-NOT: mtctr
+; CHECK: bl fmin
+
+define void @test3a(double %f, double* %fp) {
+entry:
+  br label %loop_body
+
+loop_body:
+  %invar_address.dim.0.01 = phi i64 [ 0, %entry ], [ %1, %loop_body ]
+  %0 = call double @fmin(double %f, double 1.0) readnone
+  store double %0, double* %fp, align 8
+  %1 = add i64 %invar_address.dim.0.01, 1
+  %2 = icmp eq i64 %1, 2
+  br i1 %2, label %loop_exit, label %loop_body
+
+loop_exit:
+  ret void
+}
+
+; CHECK-LABEL: test3a:
+; CHECK-NOT: mtctr
+; CHECK: bl fmin
+
+define void @test4(double %f, double* %fp) {
+entry:
+  br label %loop_body
+
+loop_body:
+  %invar_address.dim.0.01 = phi i64 [ 0, %entry ], [ %1, %loop_body ]
+  %0 = call double @llvm.maxnum.f64(double %f, double 1.0)
+  store double %0, double* %fp, align 8
+  %1 = add i64 %invar_address.dim.0.01, 1
+  %2 = icmp eq i64 %1, 2
+  br i1 %2, label %loop_exit, label %loop_body
+
+loop_exit:
+  ret void
+}
+
+; CHECK-LABEL: test4:
+; CHECK-NOT: mtctr
+; CHECK: bl fmax
+
+define void @test4a(double %f, double* %fp) {
+entry:
+  br label %loop_body
+
+loop_body:
+  %invar_address.dim.0.01 = phi i64 [ 0, %entry ], [ %1, %loop_body ]
+  %0 = call double @fmax(double %f, double 1.0) readnone
+  store double %0, double* %fp, align 8
+  %1 = add i64 %invar_address.dim.0.01, 1
+  %2 = icmp eq i64 %1, 2
+  br i1 %2, label %loop_exit, label %loop_body
+
+loop_exit:
+  ret void
+}
+
+; CHECK-LABEL: test4a:
+; CHECK-NOT: mtctr
+; CHECK: bl fmax
+
diff --git a/test/CodeGen/PowerPC/ctrloop-udivti3.ll b/test/CodeGen/PowerPC/ctrloop-udivti3.ll
index d07a11fe60fb..e3f6838d0670 100644
--- a/test/CodeGen/PowerPC/ctrloop-udivti3.ll
+++ b/test/CodeGen/PowerPC/ctrloop-udivti3.ll
@@ -13,8 +13,9 @@ for.body.lr.ph:                                   ; preds = %entry
 for.body:                                         ; preds = %for.body, %for.body.lr.ph
   %i.018.in = phi i64 [ %n, %for.body.lr.ph ], [ %i.018, %for.body ]
   %i.018 = add i64 %i.018.in, -1
-  %add.i = or i128 undef, undef
-  %div.i = udiv i128 %add.i, 0
+  %jj = sext i64 %i.018 to i128
+  %add.i = or i128 %jj, undef
+  %div.i = udiv i128 %add.i, %jj
   %conv3.i11 = trunc i128 %div.i to i64
   store i64 %conv3.i11, i64* undef, align 8
   %cmp = icmp eq i64 %i.018, 0
diff --git a/test/CodeGen/PowerPC/ctrloops-softfloat.ll b/test/CodeGen/PowerPC/ctrloops-softfloat.ll
new file mode 100644
index 000000000000..037bfda7323b
--- /dev/null
+++ b/test/CodeGen/PowerPC/ctrloops-softfloat.ll
@@ -0,0 +1,129 @@
+; RUN: llc -mtriple=powerpc-unknown-linux-gnu -O1 < %s | FileCheck %s
+
+; double x, y;
+; 
+; void foo1()
+; {
+;   x = y = 1.1;
+;   for (int i = 0; i < 175; i++)
+;     y = x + y;    
+; }
+; void foo2()
+; {
+;   x = y = 1.1;
+;   for (int i = 0; i < 175; i++)
+;     y = x - y;    
+; }
+; void foo3()
+; {
+;   x = y = 1.1;
+;   for (int i = 0; i < 175; i++)
+;     y = x * y;    
+; }
+; void foo4()
+; {
+;   x = y = 1.1;
+;   for (int i = 0; i < 175; i++)
+;     y = x / y;    
+; }
+
+target datalayout = "E-m:e-p:32:32-i64:64-n32"
+target triple = "powerpc-buildroot-linux-gnu"
+
+@y = common global double 0.000000e+00, align 8
+@x = common global double 0.000000e+00, align 8
+
+define void @foo1() #0 {
+  store double 1.100000e+00, double* @y, align 8
+  store double 1.100000e+00, double* @x, align 8
+  br label %2
+
+; <label>:1                                       ; preds = %2
+  %.lcssa = phi double [ %4, %2 ]
+  store double %.lcssa, double* @y, align 8
+  ret void
+
+; <label>:2                                       ; preds = %2, %0
+  %3 = phi double [ 1.100000e+00, %0 ], [ %4, %2 ]
+  %i.01 = phi i32 [ 0, %0 ], [ %5, %2 ]
+  %4 = fadd double %3, 1.100000e+00
+  %5 = add nuw nsw i32 %i.01, 1
+  %exitcond = icmp eq i32 %5, 75
+  br i1 %exitcond, label %1, label %2
+  ; CHECK: bl __adddf3
+  ; CHECK: cmplwi
+  ; CHECK-NOT: li [[REG1:[0-9]+]], 175
+  ; CHECK-NOT: mtctr [[REG1]]
+}
+
+define void @foo2() #0 {
+  store double 1.100000e+00, double* @y, align 8
+  store double 1.100000e+00, double* @x, align 8
+  br label %2
+
+; <label>:1                                       ; preds = %2
+  %.lcssa = phi double [ %4, %2 ]
+  store double %.lcssa, double* @y, align 8
+  ret void
+
+; <label>:2                                       ; preds = %2, %0
+  %3 = phi double [ 1.100000e+00, %0 ], [ %4, %2 ]
+  %i.01 = phi i32 [ 0, %0 ], [ %5, %2 ]
+  %4 = fsub double 1.100000e+00, %3
+  %5 = add nuw nsw i32 %i.01, 1
+  %exitcond = icmp eq i32 %5, 75
+  br i1 %exitcond, label %1, label %2
+  ; CHECK: bl __subdf3
+  ; CHECK: cmplwi
+  ; CHECK-NOT: li [[REG1:[0-9]+]], 175
+  ; CHECK-NOT: mtctr [[REG1]]
+}
+
+define void @foo3() #0 {
+  store double 1.100000e+00, double* @y, align 8
+  store double 1.100000e+00, double* @x, align 8
+  br label %2
+
+; <label>:1                                       ; preds = %2
+  %.lcssa = phi double [ %4, %2 ]
+  store double %.lcssa, double* @y, align 8
+  ret void
+
+; <label>:2                                       ; preds = %2, %0
+  %3 = phi double [ 1.100000e+00, %0 ], [ %4, %2 ]
+  %i.01 = phi i32 [ 0, %0 ], [ %5, %2 ]
+  %4 = fmul double %3, 1.100000e+00
+  %5 = add nuw nsw i32 %i.01, 1
+  %exitcond = icmp eq i32 %5, 75
+  br i1 %exitcond, label %1, label %2
+  ; CHECK: bl __muldf3
+  ; CHECK: cmplwi
+  ; CHECK-NOT: li [[REG1:[0-9]+]], 175
+  ; CHECK-NOT: mtctr [[REG1]]
+}
+
+define void @foo4() #0 {
+  store double 1.100000e+00, double* @y, align 8
+  store double 1.100000e+00, double* @x, align 8
+  br label %2
+
+; <label>:1                                       ; preds = %2
+  %.lcssa = phi double [ %4, %2 ]
+  store double %.lcssa, double* @y, align 8
+  ret void
+
+; <label>:2                                       ; preds = %2, %0
+  %3 = phi double [ 1.100000e+00, %0 ], [ %4, %2 ]
+  %i.01 = phi i32 [ 0, %0 ], [ %5, %2 ]
+  %4 = fdiv double 1.100000e+00, %3
+  %5 = add nuw nsw i32 %i.01, 1
+  %exitcond = icmp eq i32 %5, 75
+  br i1 %exitcond, label %1, label %2
+  ; CHECK: bl __divdf3
+  ; CHECK: cmplwi
+  ; CHECK-NOT: li [[REG1:[0-9]+]], 175
+  ; CHECK-NOT: mtctr [[REG1]]
+}
+
+attributes #0 = { "use-soft-float"="true" }
+
diff --git a/test/CodeGen/PowerPC/ctrloops.ll b/test/CodeGen/PowerPC/ctrloops.ll
index fff9e20d2626..f1ad58fde2b6 100644
--- a/test/CodeGen/PowerPC/ctrloops.ll
+++ b/test/CodeGen/PowerPC/ctrloops.ll
@@ -76,23 +76,22 @@ for.end:                                          ; preds = %for.body, %entry
 
 @tls_var = external thread_local global i8
 
-define i32 @test4() {
+define i32 @test4(i32 %inp) {
 entry:
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
-  %phi = phi i32 [ %dec, %for.body ], [ undef, %entry ]
+  %phi = phi i32 [ %dec, %for.body ], [ %inp, %entry ]
   %load = ptrtoint i8* @tls_var to i32
+  %val = add i32 %load, %phi
   %dec = add i32 %phi, -1
   %cmp = icmp sgt i32 %phi, 1
   br i1 %cmp, label %for.body, label %return
 
 return:                                           ; preds = %for.body
-  ret i32 %load
+  ret i32 %val
 ; CHECK-LABEL: @test4
-; CHECK-NOT: mtctr
-; CHECK: addi {{[0-9]+}}
-; CHECK: cmpwi
-; CHECK-NOT: bdnz
-; CHECK: bgt
+; CHECK: mtctr
+; CHECK: bdnz
+; CHECK: __tls_get_addr
 }
diff --git a/test/CodeGen/PowerPC/cxx_tlscc64.ll b/test/CodeGen/PowerPC/cxx_tlscc64.ll
new file mode 100644
index 000000000000..2baff8498843
--- /dev/null
+++ b/test/CodeGen/PowerPC/cxx_tlscc64.ll
@@ -0,0 +1,43 @@
+; RUN: llc < %s --enable-shrink-wrap=false -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
+%struct.S = type { i8 }
+
+@sg = internal thread_local global %struct.S zeroinitializer, align 1
+@__dso_handle = external global i8
+@__tls_guard = internal thread_local unnamed_addr global i1 false
+@sum1 = internal thread_local global i32 0, align 4
+
+declare void @_ZN1SC1Ev(%struct.S*)
+declare void @_ZN1SD1Ev(%struct.S*)
+declare i32 @_tlv_atexit(void (i8*)*, i8*, i8*)
+
+; CHECK-LABEL: _ZTW2sg
+define cxx_fast_tlscc nonnull %struct.S* @_ZTW2sg() nounwind {
+  %.b.i = load i1, i1* @__tls_guard, align 1
+; CHECK: bc 12, 1, [[BB_end:.?LBB0_[0-9]+]]
+  br i1 %.b.i, label %__tls_init.exit, label %init.i
+
+init.i:
+; CHECK: Folded Spill
+  store i1 true, i1* @__tls_guard, align 1
+  tail call void @_ZN1SC1Ev(%struct.S* nonnull @sg) #2
+; CHECK: bl _ZN1SC1Ev
+  %1 = tail call i32 @_tlv_atexit(void (i8*)* nonnull bitcast (void (%struct.S*)* @_ZN1SD1Ev to void (i8*)*), i8* nonnull getelementptr inbounds (%struct.S, %struct.S* @sg, i64 0, i32 0), i8* nonnull @__dso_handle) #2
+; CHECK: Folded Reload
+; CHECK: _tlv_atexit
+  br label %__tls_init.exit
+
+; CHECK: [[BB_end]]:
+__tls_init.exit:
+  ret %struct.S* @sg
+}
+
+; CHECK-LABEL: _ZTW4sum1
+define cxx_fast_tlscc nonnull i32* @_ZTW4sum1() nounwind {
+  ret i32* @sum1
+}
+
+define cxx_fast_tlscc i32* @_ZTW4sum2() #0 {
+  ret i32* @sum1
+}
+
+attributes #0 = { nounwind "no-frame-pointer-elim"="true" }
\ No newline at end of file
diff --git a/test/CodeGen/PowerPC/dbg.ll b/test/CodeGen/PowerPC/dbg.ll
index b636cff0f205..94c8a88316a7 100644
--- a/test/CodeGen/PowerPC/dbg.ll
+++ b/test/CodeGen/PowerPC/dbg.ll
@@ -17,10 +17,9 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!22}
 
-!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.1", isOptimized: true, emissionKind: 0, file: !21, enums: !1, retainedTypes: !1, subprograms: !3, globals: !1, imports: !1)
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.1", isOptimized: true, emissionKind: FullDebug, file: !21, enums: !1, retainedTypes: !1, globals: !1, imports: !1)
 !1 = !{}
-!3 = !{!5}
-!5 = distinct !DISubprogram(name: "main", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !21, scope: null, type: !7, variables: !13)
+!5 = distinct !DISubprogram(name: "main", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, file: !21, scope: null, type: !7, variables: !13)
 !6 = !DIFile(filename: "dbg.c", directory: "/src")
 !7 = !DISubroutineType(types: !8)
 !8 = !{!9, !9, !10}
diff --git a/test/CodeGen/PowerPC/direct-move-profit.ll b/test/CodeGen/PowerPC/direct-move-profit.ll
new file mode 100644
index 000000000000..0fa8c776be33
--- /dev/null
+++ b/test/CodeGen/PowerPC/direct-move-profit.ll
@@ -0,0 +1,83 @@
+; RUN: llc -O2 -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
+
+; Function Attrs: norecurse nounwind
+define void @test1(float* noalias nocapture %a, i32* noalias nocapture readonly %b, i32* nocapture readnone %c, i32 signext %n) #0 {
+
+; CHECK-LABEL: test1
+
+entry:
+  %idxprom = sext i32 %n to i64
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 %idxprom
+  %0 = load i32, i32* %arrayidx, align 4, !tbaa !1
+  %conv = sitofp i32 %0 to float
+  %mul = fmul float %conv, 0x4002916880000000
+  %arrayidx2 = getelementptr inbounds float, float* %a, i64 %idxprom
+  store float %mul, float* %arrayidx2, align 4, !tbaa !5
+  ret void
+
+; CHECK-NOT: mtvsrwa
+; CHECK-NOT: mtfprwa
+; CHECK: lxsiwax [[REG:[0-9]+]], {{.*}}
+; CHECK-NOT: mtvsrwa
+; CHECK-NOT: mtfprwa
+; CHECK: xscvsxdsp {{.*}}, [[REG]]
+; CHECK-NOT: mtvsrwa
+; CHECK-NOT: mtfprwa
+; CHECK: blr
+
+}
+
+; Function Attrs: norecurse nounwind readonly
+define float @test2(i32* nocapture readonly %b) #0 {
+
+; CHECK-LABEL: test2
+
+entry:
+  %0 = load i32, i32* %b, align 4, !tbaa !1
+  %conv = sitofp i32 %0 to float
+  %mul = fmul float %conv, 0x40030A3D80000000
+  ret float %mul
+
+; CHECK-NOT: mtvsrwa
+; CHECK-NOT: mtfprwa
+; CHECK: lxsiwax [[REG:[0-9]+]], {{.*}}
+; CHECK-NOT: mtvsrwa
+; CHECK-NOT: mtfprwa
+; CHECK: xscvsxdsp {{.*}}, [[REG]]
+; CHECK-NOT: mtvsrwa
+; CHECK-NOT: mtfprwa
+; CHECK: blr
+
+}
+
+; Function Attrs: norecurse nounwind
+define void @test3(float* noalias nocapture %a, i32* noalias nocapture readonly %b, i32* noalias nocapture %c, i32 signext %n) #0 {
+
+; CHECK-LABEL: test3
+
+entry:
+  %idxprom = sext i32 %n to i64
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 %idxprom
+  %0 = load i32, i32* %arrayidx, align 4, !tbaa !1
+  %conv = sitofp i32 %0 to float
+  %mul = fmul float %conv, 0x4002916880000000
+  %arrayidx2 = getelementptr inbounds float, float* %a, i64 %idxprom
+  store float %mul, float* %arrayidx2, align 4, !tbaa !5
+  %arrayidx6 = getelementptr inbounds i32, i32* %c, i64 %idxprom
+  %1 = load i32, i32* %arrayidx6, align 4, !tbaa !1
+  %add = add nsw i32 %1, %0
+  store i32 %add, i32* %arrayidx6, align 4, !tbaa !1
+  ret void
+
+; CHECK: mtvsrwa
+; CHECK: blr
+
+}
+
+!0 = !{!"clang version 3.9.0 (http://llvm.org/git/clang.git b88a395e7ba26c0fb96cd99a2a004d76f4f41d0c) (http://llvm.org/git/llvm.git 1ac3fbac0f5b037c17c0b0f9d271c32c4d7ca1b5)"}
+!1 = !{!2, !2, i64 0}
+!2 = !{!"int", !3, i64 0}
+!3 = !{!"omnipotent char", !4, i64 0}
+!4 = !{!"Simple C++ TBAA"}
+!5 = !{!6, !6, i64 0}
+!6 = !{!"float", !3, i64 0}
diff --git a/test/CodeGen/PowerPC/ec-input.ll b/test/CodeGen/PowerPC/ec-input.ll
index a57f69be12da..6ef93d268b6b 100644
--- a/test/CodeGen/PowerPC/ec-input.ll
+++ b/test/CodeGen/PowerPC/ec-input.ll
@@ -17,7 +17,7 @@ target triple = "powerpc64-bgq-linux"
 declare void @fprintf(%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713* nocapture, i8* nocapture readonly, ...) #0
 
 ; Function Attrs: inlinehint nounwind
-define void @_ZN4PAMI6Device2MU15ResourceManager46calculatePerCoreMUResourcesBasedOnAvailabilityEv() #1 align 2 {
+define void @_ZN4PAMI6Device2MU15ResourceManager46calculatePerCoreMUResourcesBasedOnAvailabilityEv(i32 %inp32, i64 %inp64) #1 align 2 {
 ; CHECK-LABEL: @_ZN4PAMI6Device2MU15ResourceManager46calculatePerCoreMUResourcesBasedOnAvailabilityEv
 ; CHECK: sc
 
@@ -32,7 +32,7 @@ for.cond2.preheader:                              ; preds = %if.end23.3, %entry
   %minFreeBatIdsPerCore.097 = phi i64 [ 32, %entry ], [ %numFreeBatIdsInGroup.0.minFreeBatIdsPerCore.0, %if.end23.3 ]
   %minFreeRecFifosPerCore.096 = phi i64 [ 16, %entry ], [ %minFreeRecFifosPerCore.1, %if.end23.3 ]
   %minFreeInjFifosPerCore.095 = phi i64 [ 32, %entry ], [ %numFreeInjFifosInGroup.0.minFreeInjFifosPerCore.0, %if.end23.3 ]
-  %cmp5 = icmp eq i32 undef, 0
+  %cmp5 = icmp eq i32 %inp32, 0
   br i1 %cmp5, label %if.end, label %if.then
 
 if.then:                                          ; preds = %if.end23.2, %if.end23.1, %if.end23, %for.cond2.preheader
@@ -41,7 +41,7 @@ if.then:                                          ; preds = %if.end23.2, %if.end
 if.end:                                           ; preds = %for.cond2.preheader
   %1 = load i32, i32* %numFreeResourcesInSubgroup, align 4
   %conv = zext i32 %1 to i64
-  %2 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1034, i64 %indvars.iv, i64 %0, i64 undef) #2
+  %2 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1034, i64 %indvars.iv, i64 %0, i64 %inp64) #2
   %cmp10 = icmp eq i32 0, 0
   br i1 %cmp10, label %if.end14, label %if.then11
 
@@ -50,11 +50,11 @@ if.then11:                                        ; preds = %if.end.3, %if.end.2
 
 if.end14:                                         ; preds = %if.end
   %3 = load i32, i32* %numFreeResourcesInSubgroup, align 4
-  %cmp19 = icmp eq i32 undef, 0
+  %cmp19 = icmp eq i32 %inp32, 0
   br i1 %cmp19, label %if.end23, label %if.then20
 
 if.then20:                                        ; preds = %if.end14.3, %if.end14.2, %if.end14.1, %if.end14
-  %conv4.i65.lcssa = phi i32 [ undef, %if.end14 ], [ 0, %if.end14.1 ], [ %conv4.i65.2, %if.end14.2 ], [ %conv4.i65.3, %if.end14.3 ]
+  %conv4.i65.lcssa = phi i32 [ %inp32, %if.end14 ], [ 0, %if.end14.1 ], [ %conv4.i65.2, %if.end14.2 ], [ %conv4.i65.3, %if.end14.3 ]
   call void (%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713*, i8*, ...) @fprintf(%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713* undef, i8* getelementptr inbounds ([121 x i8], [121 x i8]* @.str236, i64 0, i64 0), i32 signext 2503) #3
   call void (%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713*, i8*, ...) @fprintf(%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713* undef, i8* getelementptr inbounds ([49 x i8], [49 x i8]* @.str294, i64 0, i64 0), i32 signext %conv4.i65.lcssa) #3
   unreachable
@@ -63,7 +63,7 @@ if.end23:                                         ; preds = %if.end14
   %conv15 = zext i32 %3 to i64
   %4 = load i32, i32* %numFreeResourcesInSubgroup, align 4
   %conv24 = zext i32 %4 to i64
-  %5 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1033, i64 0, i64 %0, i64 undef) #2
+  %5 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1033, i64 0, i64 %0, i64 %inp64) #2
   %cmp5.1 = icmp eq i32 0, 0
   br i1 %cmp5.1, label %if.end.1, label %if.then
 
@@ -74,8 +74,8 @@ if.end.1:                                         ; preds = %if.end23
   %6 = load i32, i32* %numFreeResourcesInSubgroup, align 4
   %conv.1 = zext i32 %6 to i64
   %add.1 = add nuw nsw i64 %conv.1, %conv
-  %7 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1034, i64 0, i64 %0, i64 undef) #2
-  %cmp10.1 = icmp eq i32 undef, 0
+  %7 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1034, i64 0, i64 %0, i64 %inp64) #2
+  %cmp10.1 = icmp eq i32 %inp32, 0
   br i1 %cmp10.1, label %if.end14.1, label %if.then11
 
 if.end14.1:                                       ; preds = %if.end.1
@@ -89,20 +89,20 @@ if.end23.1:                                       ; preds = %if.end14.1
   %9 = load i32, i32* %numFreeResourcesInSubgroup, align 4
   %conv24.1 = zext i32 %9 to i64
   %add25.1 = add nuw nsw i64 %conv24.1, %conv24
-  %cmp5.2 = icmp eq i32 undef, 0
+  %cmp5.2 = icmp eq i32 %inp32, 0
   br i1 %cmp5.2, label %if.end.2, label %if.then
 
 if.end.2:                                         ; preds = %if.end23.1
   %10 = load i32, i32* %numFreeResourcesInSubgroup, align 4
   %conv.2 = zext i32 %10 to i64
   %add.2 = add nuw nsw i64 %conv.2, %add.1
-  %11 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1034, i64 undef, i64 %0, i64 undef) #2
+  %11 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1034, i64 %inp64, i64 %0, i64 %inp64) #2
   %cmp10.2 = icmp eq i32 0, 0
   br i1 %cmp10.2, label %if.end14.2, label %if.then11
 
 if.end14.2:                                       ; preds = %if.end.2
   %12 = load i32, i32* %numFreeResourcesInSubgroup, align 4
-  %13 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1035, i64 undef, i64 %0, i64 0) #2
+  %13 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1035, i64 %inp64, i64 %0, i64 0) #2
   %asmresult1.i64.2 = extractvalue { i64, i64, i64, i64 } %13, 1
   %conv4.i65.2 = trunc i64 %asmresult1.i64.2 to i32
   %cmp19.2 = icmp eq i32 %conv4.i65.2, 0
@@ -121,7 +121,7 @@ if.end.3:                                         ; preds = %if.end23.2
   %15 = load i32, i32* %numFreeResourcesInSubgroup, align 4
   %conv.3 = zext i32 %15 to i64
   %add.3 = add nuw nsw i64 %conv.3, %add.2
-  %cmp10.3 = icmp eq i32 undef, 0
+  %cmp10.3 = icmp eq i32 %inp32, 0
   br i1 %cmp10.3, label %if.end14.3, label %if.then11
 
 if.end14.3:                                       ; preds = %if.end.3
diff --git a/test/CodeGen/PowerPC/ext-bool-trunc-repl.ll b/test/CodeGen/PowerPC/ext-bool-trunc-repl.ll
new file mode 100644
index 000000000000..df67ecd7a632
--- /dev/null
+++ b/test/CodeGen/PowerPC/ext-bool-trunc-repl.ll
@@ -0,0 +1,38 @@
+; RUN: llc -O0 < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+@c = external global i32, align 4
+@d = external global [2 x i32], align 4
+
+; Function Attrs: norecurse nounwind
+define void @fn2() #0 {
+; CHECK-LABEL: @fn2
+
+  br i1 undef, label %1, label %10
+
+; <label>:1:                                      ; preds = %0
+  br i1 undef, label %3, label %2
+
+; <label>:2:                                      ; preds = %2, %1
+  br i1 undef, label %3, label %2
+
+; <label>:3:                                      ; preds = %2, %1
+  br i1 undef, label %8, label %4
+
+; <label>:4:                                      ; preds = %4, %3
+  %5 = phi i64 [ %6, %4 ], [ undef, %3 ]
+  %6 = and i64 %5, and (i64 and (i64 and (i64 and (i64 and (i64 and (i64 and (i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i16), i16 0), i32 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i32), i32 lshr (i32 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i32), i32 6)) to i64), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i16), i16 0), i32 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i32), i32 lshr (i32 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i16), i16 0), i32 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i32), i32 lshr (i32 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i16), i16 0), i32 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i32), i32 lshr (i32 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i16), i16 0), i32 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i32), i32 lshr (i32 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i16), i16 0), i32 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i32), i32 lshr (i32 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i16), i16 0), i32 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i32), i32 lshr (i32 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i32), i32 6)) to i64)), i64 sext (i32 select (i1 icmp slt (i16 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i16), i16 0), i32 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i32), i32 lshr (i32 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @d, i64 0, i64 1), i32* @c) to i32), i32 6)) to i64))
+  %7 = icmp slt i32 undef, 6
+  br i1 %7, label %4, label %8
+
+; <label>:8:                                      ; preds = %4, %3
+  %9 = phi i64 [ undef, %3 ], [ %6, %4 ]
+  br label %10
+
+; <label>:10:                                     ; preds = %8, %0
+  ret void
+}
+
+attributes #0 = { norecurse nounwind "target-cpu"="ppc64le" }
+
diff --git a/test/CodeGen/PowerPC/fabs.ll b/test/CodeGen/PowerPC/fabs.ll
index 36aa23d03550..5a17c838f1b0 100644
--- a/test/CodeGen/PowerPC/fabs.ll
+++ b/test/CodeGen/PowerPC/fabs.ll
@@ -1,7 +1,30 @@
-; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin | grep "fabs f1, f1"
+; RUN: llc < %s -mattr=-vsx -march=ppc32 -mtriple=powerpc-apple-darwin | FileCheck %s
 
 define double @fabs(double %f) {
-entry:
-	%tmp2 = tail call double @fabs( double %f ) readnone	; <double> [#uses=1]
-	ret double %tmp2
+; CHECK-LABEL: fabs:
+; CHECK:       ; BB#0:
+; CHECK-NEXT:    fabs f1, f1
+; CHECK-NEXT:    blr
+;
+  %t = tail call double @fabs( double %f ) readnone
+  ret double %t
 }
+
+define float @bitcast_fabs(float %x) {
+; CHECK-LABEL: bitcast_fabs:
+; CHECK:       ; BB#0:
+; CHECK-NEXT:    stfs f1, -8(r1)
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    lwz r2, -8(r1)
+; CHECK-NEXT:    clrlwi r2, r2, 1
+; CHECK-NEXT:    stw r2, -4(r1)
+; CHECK-NEXT:    lfs f1, -4(r1)
+; CHECK-NEXT:    blr
+;
+  %bc1 = bitcast float %x to i32
+  %and = and i32 %bc1, 2147483647
+  %bc2 = bitcast i32 %and to float
+  ret float %bc2
+}
+
diff --git a/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll b/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
new file mode 100644
index 000000000000..4390b938aeab
--- /dev/null
+++ b/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
@@ -0,0 +1,187 @@
+; RUN: llc -mtriple powerpc64le-unknown-linux-gnu -fast-isel -O0 < %s | FileCheck %s
+
+define i1 @TestULT(double %t0) {
+; CHECK-LABEL: TestULT:
+; CHECK: mcrf
+; CHECK: blr
+entry:
+  %t1 = fcmp ult double %t0, 0.000000e+00
+  br i1 %t1, label %good, label %bad
+
+bad:
+  ret i1 false
+
+good:
+  ret i1 true
+}
+
+define i1 @TestULE(double %t0) {
+; CHECK-LABEL: TestULE:
+; CHECK: fcmpu
+; CHECK-NEXT: ble
+; CHECK: blr
+entry:
+  %t1 = fcmp ule double %t0, 0.000000e+00
+  br i1 %t1, label %good, label %bad
+
+bad:
+  ret i1 false
+
+good:
+  ret i1 true
+}
+
+define i1 @TestUNE(double %t0) {
+; CHECK-LABEL: TestUNE:
+; CHECK: fcmpu
+; CHECK-NEXT: bne
+; CHECK: blr
+entry:
+  %t1 = fcmp une double %t0, 0.000000e+00
+  br i1 %t1, label %good, label %bad
+
+bad:
+  ret i1 false
+
+good:
+  ret i1 true
+}
+
+define i1 @TestUEQ(double %t0) {
+; CHECK-LABEL: TestUEQ:
+; CHECK: mcrf
+; CHECK: blr
+entry:
+  %t1 = fcmp ueq double %t0, 0.000000e+00
+  br i1 %t1, label %good, label %bad
+
+bad:
+  ret i1 false
+
+good:
+  ret i1 true
+}
+
+define i1 @TestUGT(double %t0) {
+; CHECK-LABEL: TestUGT:
+; CHECK: mcrf
+; CHECK: blr
+entry:
+  %t1 = fcmp ugt double %t0, 0.000000e+00
+  br i1 %t1, label %good, label %bad
+
+bad:
+  ret i1 false
+
+good:
+  ret i1 true
+}
+
+define i1 @TestUGE(double %t0) {
+; CHECK-LABEL: TestUGE:
+; CHECK: fcmpu
+; CHECK-NEXT: bge
+; CHECK: blr
+entry:
+  %t1 = fcmp uge double %t0, 0.000000e+00
+  br i1 %t1, label %good, label %bad
+
+bad:
+  ret i1 false
+
+good:
+  ret i1 true
+}
+
+define i1 @TestOLT(double %t0) {
+; CHECK-LABEL: TestOLT:
+; CHECK: fcmpu
+; CHECK-NEXT: blt
+; CHECK: blr
+entry:
+  %t1 = fcmp olt double %t0, 0.000000e+00
+  br i1 %t1, label %good, label %bad
+
+bad:
+  ret i1 false
+
+good:
+  ret i1 true
+}
+
+define i1 @TestOLE(double %t0) {
+; CHECK-LABEL: TestOLE:
+; CHECK: mcrf
+; CHECK: blr
+entry:
+  %t1 = fcmp ole double %t0, 0.000000e+00
+  br i1 %t1, label %good, label %bad
+
+bad:
+  ret i1 false
+
+good:
+  ret i1 true
+}
+
+define i1 @TestONE(double %t0) {
+; CHECK-LABEL: TestONE:
+; CHECK: mcrf
+; CHECK: blr
+entry:
+  %t1 = fcmp one double %t0, 0.000000e+00
+  br i1 %t1, label %good, label %bad
+
+bad:
+  ret i1 false
+
+good:
+  ret i1 true
+}
+
+define i1 @TestOEQ(double %t0) {
+; CHECK-LABEL: TestOEQ:
+; CHECK: fcmpu
+; CHECK-NEXT: beq
+; CHECK: blr
+entry:
+  %t1 = fcmp oeq double %t0, 0.000000e+00
+  br i1 %t1, label %good, label %bad
+
+bad:
+  ret i1 false
+
+good:
+  ret i1 true
+}
+
+define i1 @TestOGT(double %t0) {
+; CHECK-LABEL: TestOGT:
+; CHECK: fcmpu
+; CHECK-NEXT: bgt
+; CHECK: blr
+entry:
+  %t1 = fcmp ogt double %t0, 0.000000e+00
+  br i1 %t1, label %good, label %bad
+
+bad:
+  ret i1 false
+
+good:
+  ret i1 true
+}
+
+define i1 @TestOGE(double %t0) {
+; CHECK-LABEL: TestOGE:
+; CHECK: mcrf
+; CHECK: blr
+entry:
+  %t1 = fcmp oge double %t0, 0.000000e+00
+  br i1 %t1, label %good, label %bad
+
+bad:
+  ret i1 false
+
+good:
+  ret i1 true
+}
diff --git a/test/CodeGen/PowerPC/fast-isel-fpconv.ll b/test/CodeGen/PowerPC/fast-isel-fpconv.ll
new file mode 100644
index 000000000000..eb14cf2aa769
--- /dev/null
+++ b/test/CodeGen/PowerPC/fast-isel-fpconv.ll
@@ -0,0 +1,33 @@
+; RUN: llc -mtriple powerpc64-unknown-linux-gnu -fast-isel -O0 < %s | FileCheck %s
+
+; The second fctiwz would use an incorrect input register due to wrong handling
+; of COPY_TO_REGCLASS in the FastISel pass.  Verify that this is fixed.
+
+declare void @func(i32, i32)
+
+define void @test() {
+; CHECK-LABEL: test:
+; CHECK: bl func
+; CHECK-NEXT: nop
+; CHECK: lfs [[REG:[0-9]+]], 
+; CHECK: fctiwz {{[0-9]+}}, [[REG]]
+; CHECK: bl func
+; CHECK-NEXT: nop
+
+  %memPos = alloca float, align 4
+  store float 1.500000e+01, float* %memPos
+  %valPos = load float, float* %memPos
+
+  %memNeg = alloca float, align 4
+  store float -1.500000e+01, float* %memNeg
+  %valNeg = load float, float* %memNeg
+
+  %FloatToIntPos = fptosi float %valPos to i32
+  call void @func(i32 15, i32 %FloatToIntPos)
+
+  %FloatToIntNeg = fptosi float %valNeg to i32
+  call void @func(i32 -15, i32 %FloatToIntNeg)
+
+  ret void
+}
+
diff --git a/test/CodeGen/PowerPC/fast-isel-i64offset.ll b/test/CodeGen/PowerPC/fast-isel-i64offset.ll
new file mode 100644
index 000000000000..00278d68f638
--- /dev/null
+++ b/test/CodeGen/PowerPC/fast-isel-i64offset.ll
@@ -0,0 +1,12 @@
+; RUN: llc -mtriple powerpc64-unknown-linux-gnu -fast-isel -O0 < %s | FileCheck %s
+
+; Verify that pointer offsets larger than 32 bits work correctly.
+
+define void @test(i32* %array) {
+; CHECK-LABEL: test:
+; CHECK-NOT: li {{[0-9]+}}, -8
+  %element = getelementptr i32, i32* %array, i64 2147483646
+  store i32 1234, i32* %element
+  ret void
+}
+
diff --git a/test/CodeGen/PowerPC/fdiv-combine.ll b/test/CodeGen/PowerPC/fdiv-combine.ll
index d3dc3fe913fd..3aac7032c69e 100644
--- a/test/CodeGen/PowerPC/fdiv-combine.ll
+++ b/test/CodeGen/PowerPC/fdiv-combine.ll
@@ -9,8 +9,8 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define void @three_fdiv_double(double %D, double %a, double %b, double %c) #0 {
 ; CHECK-LABEL: three_fdiv_double:
-; CHECK: fdiv
-; CHECK-NEXT-NOT: fdiv
+; CHECK: fdiv {{[0-9]}}
+; CHECK-NOT: fdiv
 ; CHECK: fmul
 ; CHECK: fmul
 ; CHECK: fmul
@@ -23,9 +23,9 @@ define void @three_fdiv_double(double %D, double %a, double %b, double %c) #0 {
 
 define void @two_fdiv_double(double %D, double %a, double %b) #0 {
 ; CHECK-LABEL: two_fdiv_double:
-; CHECK: fdiv
-; CHECK: fdiv
-; CHECK-NEXT-NOT: fmul
+; CHECK: fdiv {{[0-9]}}
+; CHECK: fdiv {{[0-9]}}
+; CHECK-NOT: fmul
   %div = fdiv double %a, %D
   %div1 = fdiv double %b, %D
   tail call void @foo_2d(double %div, double %div1)
diff --git a/test/CodeGen/PowerPC/fma-assoc.ll b/test/CodeGen/PowerPC/fma-assoc.ll
index 3044dd09128c..4a2ca6010f65 100644
--- a/test/CodeGen/PowerPC/fma-assoc.ll
+++ b/test/CodeGen/PowerPC/fma-assoc.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=ppc32 -fp-contract=fast -mattr=-vsx | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mattr=+vsx -mcpu=pwr7 | FileCheck -check-prefix=CHECK-VSX %s
+; RUN: llc < %s -march=ppc32 -fp-contract=fast -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mattr=+vsx -mcpu=pwr7 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-VSX %s
 
 define double @test_FMADD_ASSOC1(double %A, double %B, double %C,
                                  double %D, double %E) {
diff --git a/test/CodeGen/PowerPC/fma-ext.ll b/test/CodeGen/PowerPC/fma-ext.ll
index da7c34ccb9d8..fc3489def7cd 100644
--- a/test/CodeGen/PowerPC/fma-ext.ll
+++ b/test/CodeGen/PowerPC/fma-ext.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=ppc32 -fp-contract=fast -mattr=-vsx | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mattr=+vsx -mcpu=pwr7 | FileCheck -check-prefix=CHECK-VSX %s
+; RUN: llc < %s -march=ppc32 -fp-contract=fast -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mattr=+vsx -mcpu=pwr7 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-VSX %s
 
 define double @test_FMADD_EXT1(float %A, float %B, double %C) {
     %D = fmul float %A, %B          ; <float> [#uses=1]
diff --git a/test/CodeGen/PowerPC/fma-mutate-duplicate-vreg.ll b/test/CodeGen/PowerPC/fma-mutate-duplicate-vreg.ll
new file mode 100644
index 000000000000..08d1b1ba883f
--- /dev/null
+++ b/test/CodeGen/PowerPC/fma-mutate-duplicate-vreg.ll
@@ -0,0 +1,36 @@
+; RUN: llc -fp-contract=fast -O2 < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-grtev4-linux-gnu"
+
+; CHECK-LABEL: f
+; CHECK-NOT: xsmaddmsp [[REG:[0-9]+]], [[REG]], {{[0-9]+}}
+define float @f(float %xf) #0 {
+  %1 = fmul float %xf, %xf
+  %2 = fmul float %1, 0x3F43FB0140000000
+  %3 = fsub float 1.000000e+00, %2
+  %4 = fmul float %1, %3
+  %5 = fmul float %4, 0x3F461C5440000000
+  %6 = fsub float 1.000000e+00, %5
+  %7 = fmul float %1, %6
+  %8 = fmul float %7, 0x3F4899C100000000
+  %9 = fsub float 1.000000e+00, %8
+  %10 = fmul float %1, %9
+  %11 = fmul float %10, 0x3F4B894020000000
+  %12 = fsub float 1.000000e+00, %11
+  %13 = fmul float %1, %12
+  %14 = fmul float %13, 0x3F4F07C200000000
+  %15 = fsub float 1.000000e+00, %14
+  %16 = fmul float %1, %15
+  %17 = fmul float %16, 0x3F519E0120000000
+  %18 = fsub float 1.000000e+00, %17
+  %19 = fmul float %1, %18
+  %20 = fmul float %19, 0x3F542D6620000000
+  %21 = fsub float 1.000000e+00, %20
+  %22 = fmul float %1, %21
+  %23 = fmul float %22, 0x3F5756CAC0000000
+  %24 = fsub float 1.000000e+00, %23
+  %25 = fmul float %1, %24
+  ret float %25
+}
+
+attributes #0 = { norecurse nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr8" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/CodeGen/PowerPC/fma-mutate.ll b/test/CodeGen/PowerPC/fma-mutate.ll
index 1a391f4c2305..befd2d2e58b5 100644
--- a/test/CodeGen/PowerPC/fma-mutate.ll
+++ b/test/CodeGen/PowerPC/fma-mutate.ll
@@ -3,7 +3,7 @@
 ; same as the FMA target register.  The second one is legal.  The third
 ; one doesn't fit the feeding-copy pattern.
 
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-unsafe-fp-math -mattr=+vsx | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-unsafe-fp-math -mattr=+vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
diff --git a/test/CodeGen/PowerPC/fma.ll b/test/CodeGen/PowerPC/fma.ll
index 9cfef398edfd..79c5e11d05c5 100644
--- a/test/CodeGen/PowerPC/fma.ll
+++ b/test/CodeGen/PowerPC/fma.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=ppc32 -fp-contract=fast -mattr=-vsx | FileCheck %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mattr=+vsx -mcpu=pwr7 | FileCheck -check-prefix=CHECK-VSX %s
-; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mcpu=pwr8 | FileCheck -check-prefix=CHECK-P8 %s
-; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -fp-contract=fast -mcpu=pwr8 | FileCheck -check-prefix=CHECK-P8 %s
+; RUN: llc < %s -march=ppc32 -fp-contract=fast -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mattr=+vsx -mcpu=pwr7 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-VSX %s
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mcpu=pwr8 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-P8 %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -fp-contract=fast -mcpu=pwr8 -disable-ppc-vsx-fma-mutation=false | FileCheck -check-prefix=CHECK-P8 %s
 
 declare double @dummy1(double) #0
 declare double @dummy2(double, double) #0
diff --git a/test/CodeGen/PowerPC/fp2int2fp-ppcfp128.ll b/test/CodeGen/PowerPC/fp2int2fp-ppcfp128.ll
index 7742ffe33150..569e4e6cb923 100644
--- a/test/CodeGen/PowerPC/fp2int2fp-ppcfp128.ll
+++ b/test/CodeGen/PowerPC/fp2int2fp-ppcfp128.ll
@@ -2,9 +2,9 @@
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-bgq-linux"
 
-define linkonce_odr double @test1() {
+define linkonce_odr double @test1(ppc_fp128 %input) {
 entry:
-  %conv6.i.i = fptosi ppc_fp128 undef to i64
+  %conv6.i.i = fptosi ppc_fp128 %input to i64
   %conv.i = sitofp i64 %conv6.i.i to double
   ret double %conv.i
 
diff --git a/test/CodeGen/PowerPC/hello-reloc.s b/test/CodeGen/PowerPC/hello-reloc.s
index 12f4315f675a..bbf1e7cacbd4 100644
--- a/test/CodeGen/PowerPC/hello-reloc.s
+++ b/test/CodeGen/PowerPC/hello-reloc.s
@@ -2,7 +2,7 @@
 ; which is responsible for writing mach-o relocation entries for (PIC)
 ; PowerPC objects.
 
-; RUN: llvm-mc -filetype=obj -relocation-model=pic -mcpu=g4 -triple=powerpc-apple-darwin8 %s -o - | llvm-readobj -r --expand-relocs | FileCheck -check-prefix=DARWIN-G4-DUMP %s
+; RUN: llvm-mc -filetype=obj -mcpu=g4 -triple=powerpc-apple-darwin8 %s -o - | llvm-readobj -r --expand-relocs | FileCheck -check-prefix=DARWIN-G4-DUMP %s
 
 	.machine ppc7400
 	.section	__TEXT,__textcoal_nt,coalesced,pure_instructions
diff --git a/test/CodeGen/PowerPC/hidden-vis-2.ll b/test/CodeGen/PowerPC/hidden-vis-2.ll
index 3eb9dbd21ade..4ef0f708b4f6 100644
--- a/test/CodeGen/PowerPC/hidden-vis-2.ll
+++ b/test/CodeGen/PowerPC/hidden-vis-2.ll
@@ -1,12 +1,19 @@
-; RUN: llc < %s -mtriple=powerpc-apple-darwin9 | grep non_lazy_ptr | count 6
+; RUN: llc < %s -mtriple=powerpc-apple-darwin9 | FileCheck %s
 
-@x = external hidden global i32		; <i32*> [#uses=1]
-@y = extern_weak hidden global i32	; <i32*> [#uses=1]
+; CHECK: lis r2, ha16(L_x$non_lazy_ptr)
+; CHECK: lis r3, ha16(L_y$non_lazy_ptr)
+; CHECK: lwz r2, lo16(L_x$non_lazy_ptr)(r2)
+; CHECK: lwz r3, lo16(L_y$non_lazy_ptr)(r3)
+; CHECK: L_x$non_lazy_ptr:
+; CHECK: L_y$non_lazy_ptr:
+
+@x = external hidden global i32
+@y = extern_weak hidden global i32
 
 define i32 @t() nounwind readonly {
 entry:
-	%0 = load i32, i32* @x, align 4		; <i32> [#uses=1]
-	%1 = load i32, i32* @y, align 4		; <i32> [#uses=1]
-	%2 = add i32 %1, %0		; <i32> [#uses=1]
-	ret i32 %2
+        %0 = load i32, i32* @x, align 4
+        %1 = load i32, i32* @y, align 4
+        %2 = add i32 %1, %0
+        ret i32 %2
 }
diff --git a/test/CodeGen/PowerPC/indirect-hidden.ll b/test/CodeGen/PowerPC/indirect-hidden.ll
new file mode 100644
index 000000000000..5ef8b6df4b09
--- /dev/null
+++ b/test/CodeGen/PowerPC/indirect-hidden.ll
@@ -0,0 +1,21 @@
+; RUN: llc -mtriple=powerpc-apple-darwin < %s | FileCheck %s
+
+@a = external hidden global i32
+@b = external global i32
+
+define i32* @get_a() {
+  ret i32* @a
+}
+
+define i32* @get_b() {
+  ret i32* @b
+}
+
+; CHECK:      .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers
+; CHECK-NEXT: .p2align  2
+; CHECK-NEXT: L_a$non_lazy_ptr:
+; CHECK-NEXT:   .indirect_symbol        _a
+; CHECK-NEXT:   .long   0
+; CHECK-NEXT: L_b$non_lazy_ptr:
+; CHECK-NEXT:   .indirect_symbol        _b
+; CHECK-NEXT:   .long   0
diff --git a/test/CodeGen/PowerPC/inline-asm-scalar-to-vector-error.ll b/test/CodeGen/PowerPC/inline-asm-scalar-to-vector-error.ll
new file mode 100644
index 000000000000..3f1d9d32becd
--- /dev/null
+++ b/test/CodeGen/PowerPC/inline-asm-scalar-to-vector-error.ll
@@ -0,0 +1,14 @@
+; RUN: not llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8a -mattr=+altivec %s -o - 2>&1 | FileCheck %s
+
+define hidden void @f(i32 %x) {
+  ; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type
+  tail call void asm sideeffect "nop", "{v1}"(i32 %x) nounwind
+
+  ; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type
+  tail call void asm sideeffect "nop", "{vsl1}"(i32 %x) nounwind
+
+  ; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type
+  tail call void asm sideeffect "nop", "{vsh1}"(i32 %x) nounwind
+
+  ret void
+}
diff --git a/test/CodeGen/PowerPC/lbzux.ll b/test/CodeGen/PowerPC/lbzux.ll
index 4bd9cb6ab18a..a8ca639e6880 100644
--- a/test/CodeGen/PowerPC/lbzux.ll
+++ b/test/CodeGen/PowerPC/lbzux.ll
@@ -2,7 +2,7 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "powerpc64-unknown-linux-gnu"
 ; RUN: llc -disable-ppc-unaligned < %s | FileCheck %s
 
-define fastcc void @allocateSpace(i1 %cond1, i1 %cond2) nounwind {
+define fastcc void @allocateSpace(i1 %cond1, i1 %cond2, i32 %offset) nounwind {
 entry:
   %0 = load i8*, i8** undef, align 8
   br i1 undef, label %return, label %lor.lhs.false
@@ -19,14 +19,13 @@ if.then15:                                        ; preds = %if.end7
 while.cond:                                       ; preds = %while.body, %if.then15
   %idxprom17 = sext i32 0 to i64
   %arrayidx18 = getelementptr inbounds i8, i8* %0, i64 %idxprom17
-  %or = or i32 undef, undef
   br i1 %cond1, label %if.end71, label %while.body
 
 while.body:                                       ; preds = %while.cond
   br i1 %cond2, label %while.cond, label %if.then45
 
 if.then45:                                        ; preds = %while.body
-  %idxprom48139 = zext i32 %or to i64
+  %idxprom48139 = zext i32 %offset to i64
   %arrayidx49 = getelementptr inbounds i8, i8* %0, i64 %idxprom48139
   %1 = bitcast i8* %arrayidx49 to i16*
   %2 = bitcast i8* %arrayidx18 to i16*
diff --git a/test/CodeGen/PowerPC/load-two-flts.ll b/test/CodeGen/PowerPC/load-two-flts.ll
new file mode 100644
index 000000000000..270a852b1b04
--- /dev/null
+++ b/test/CodeGen/PowerPC/load-two-flts.ll
@@ -0,0 +1,60 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-bgq-linux"
+
+define void @_Z4testSt7complexIfE(float %v0, float %v1, i64* %ref.tmp, float* %_M_value.realp.i.i, float* %_M_value.imagp.i.i) {
+entry:
+  %v2 = load i64, i64* %ref.tmp, align 8
+  %v3 = lshr i64 %v2, 32
+  %v4 = trunc i64 %v3 to i32
+  %v5 = bitcast i32 %v4 to float
+  %v6 = trunc i64 %v2 to i32
+  %v7 = bitcast i32 %v6 to float
+  %mul_ad.i.i = fmul fast float %v5, %v1
+  %mul_bc.i.i = fmul fast float %v7, %v0
+  %mul_i.i.i = fadd fast float %mul_ad.i.i, %mul_bc.i.i
+  %mul_ac.i.i = fmul fast float %v5, %v0
+  %mul_bd.i.i = fmul fast float %v7, %v1
+  %mul_r.i.i = fsub fast float %mul_ac.i.i, %mul_bd.i.i
+  store float %mul_r.i.i, float* %_M_value.realp.i.i, align 4
+  store float %mul_i.i.i, float* %_M_value.imagp.i.i, align 4
+  ret void
+
+; CHECK-LABEL: @_Z4testSt7complexIfE
+; CHECK-NOT: ld {{[0-9]+}}, 0(5)
+; CHECK-NOT: stw
+; CHECK-NOT: rldicl
+; CHECK-DAG: lfs {{[0-9]+}}, 4(5)
+; CHECK-DAG: lfs {{[0-9]+}}, 0(5)
+; CHECK: blr
+}
+
+define i64* @_Z4testSt7complexIfE_idx(float %v0, float %v1, i64* %ref.tmp, float* %_M_value.realp.i.i, float* %_M_value.imagp.i.i) {
+entry:
+  %r = getelementptr i64, i64* %ref.tmp, i64 1
+  %v2 = load i64, i64* %r, align 8
+  %v3 = lshr i64 %v2, 32
+  %v4 = trunc i64 %v3 to i32
+  %v5 = bitcast i32 %v4 to float
+  %v6 = trunc i64 %v2 to i32
+  %v7 = bitcast i32 %v6 to float
+  %mul_ad.i.i = fmul fast float %v5, %v1
+  %mul_bc.i.i = fmul fast float %v7, %v0
+  %mul_i.i.i = fadd fast float %mul_ad.i.i, %mul_bc.i.i
+  %mul_ac.i.i = fmul fast float %v5, %v0
+  %mul_bd.i.i = fmul fast float %v7, %v1
+  %mul_r.i.i = fsub fast float %mul_ac.i.i, %mul_bd.i.i
+  store float %mul_r.i.i, float* %_M_value.realp.i.i, align 4
+  store float %mul_i.i.i, float* %_M_value.imagp.i.i, align 4
+  ret i64* %r
+
+; CHECK-LABEL: @_Z4testSt7complexIfE
+; CHECK-NOT: ld {{[0-9]+}}, 8(5)
+; CHECK-NOT: ldu {{[0-9]+}}, 8(5)
+; CHECK-NOT: stw
+; CHECK-NOT: rldicl
+; CHECK-DAG: lfsu {{[0-9]+}}, 8(5)
+; CHECK-DAG: lfs {{[0-9]+}}, 4(5)
+; CHECK: blr
+}
+
diff --git a/test/CodeGen/PowerPC/load-v4i8-improved.ll b/test/CodeGen/PowerPC/load-v4i8-improved.ll
new file mode 100644
index 000000000000..d03ff06bbd93
--- /dev/null
+++ b/test/CodeGen/PowerPC/load-v4i8-improved.ll
@@ -0,0 +1,23 @@
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck \
+; RUN:   -implicit-check-not vmrg -implicit-check-not=vperm %s
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck \
+; RUN:   -implicit-check-not vmrg -implicit-check-not=vperm %s \
+; RUN:   --check-prefix=CHECK-BE
+
+define <16 x i8> @test(i32* %s, i32* %t) {
+entry:
+  %0 = bitcast i32* %s to <4 x i8>*
+  %1 = load <4 x i8>, <4 x i8>* %0, align 4
+  %2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  ret <16 x i8> %2
+; CHECK-LABEL: test
+; CHECK: lwz [[GPR:[0-9]+]], 0(3)
+; CHECK: mtvsrd [[VSR:[0-9]+]], [[GPR]]
+; CHECK: xxswapd  [[SWP:[0-9]+]], [[VSR]]
+; CHECK: xxspltw 34, [[SWP]], 3
+; CHECK-BE-LABEL: test
+; CHECK-BE: lwz [[GPR:[0-9]+]], 0(3)
+; CHECK-BE: sldi [[SHL:[0-9]+]], [[GPR]], 32
+; CHECK-BE: mtvsrd [[VSR:[0-9]+]], [[SHL]]
+; CHECK-BE: xxspltw 34, [[VSR]], 0
+}
diff --git a/test/CodeGen/PowerPC/lsr-postinc-pos.ll b/test/CodeGen/PowerPC/lsr-postinc-pos.ll
index 7831df154606..17b05b219c72 100644
--- a/test/CodeGen/PowerPC/lsr-postinc-pos.ll
+++ b/test/CodeGen/PowerPC/lsr-postinc-pos.ll
@@ -3,27 +3,27 @@
 ; The icmp is a post-inc use, and the increment is in %bb11, but the
 ; scevgep needs to be inserted in %bb so that it is dominated by %t.
 
-; CHECK: %t = load i8*, i8** undef
+; CHECK: %t = load i8*, i8** %inp
 ; CHECK: %scevgep = getelementptr i8, i8* %t, i32 %lsr.iv.next
-; CHECK: %c1 = icmp ult i8* %scevgep, undef
+; CHECK: %c1 = icmp ult i8* %scevgep, %inp2
 
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
 target triple = "powerpc-apple-darwin9"
 
-define void @foo() nounwind {
+define void @foo(i8** %inp, i8* %inp2) nounwind {
 entry:
   br label %bb11
 
 bb11:
   %i = phi i32 [ 0, %entry ], [ %i.next, %bb ] ; <i32> [#uses=3]
   %ii = shl i32 %i, 2                       ; <i32> [#uses=1]
-  %c0 = icmp eq i32 %i, undef                ; <i1> [#uses=1]
+  %c0 = icmp eq i32 %i, 0                   ; <i1> [#uses=1]
   br i1 %c0, label %bb13, label %bb
 
 bb:
-  %t = load i8*, i8** undef, align 16                ; <i8*> [#uses=1]
+  %t = load i8*, i8** %inp, align 16                ; <i8*> [#uses=1]
   %p = getelementptr i8, i8* %t, i32 %ii ; <i8*> [#uses=1]
-  %c1 = icmp ult i8* %p, undef          ; <i1> [#uses=1]
+  %c1 = icmp ult i8* %p,  %inp2          ; <i1> [#uses=1]
   %i.next = add i32 %i, 1                        ; <i32> [#uses=1]
   br i1 %c1, label %bb11, label %bb13
 
diff --git a/test/CodeGen/PowerPC/machine-combiner.ll b/test/CodeGen/PowerPC/machine-combiner.ll
index 93fb2020d530..ae9e2e8cf6a6 100644
--- a/test/CodeGen/PowerPC/machine-combiner.ll
+++ b/test/CodeGen/PowerPC/machine-combiner.ll
@@ -98,6 +98,7 @@ define <4 x float> @vector_reassociate_adds1(<4 x float> %x0, <4 x float> %x1, <
 ; CHECK-PWR:       xvaddsp [[REG0:[0-9]+]], 34, 35
 ; CHECK-PWR:       xvaddsp [[REG1:[0-9]+]], 36, 37
 ; CHECK-PWR:       xvaddsp 34, [[REG0]], [[REG1]]
+; CHECK-PWR:       # kill
 ; CHECK-NEXT:  blr
 
   %t0 = fadd <4 x float> %x0, %x1
@@ -115,6 +116,7 @@ define <4 x float> @vector_reassociate_adds2(<4 x float> %x0, <4 x float> %x1, <
 ; CHECK-PWR:       xvaddsp [[REG0:[0-9]+]], 34, 35
 ; CHECK-PWR:       xvaddsp [[REG1:[0-9]+]], 36, 37
 ; CHECK-PWR:       xvaddsp 34, [[REG0]], [[REG1]]
+; CHECK-PWR:       # kill
 ; CHECK-NEXT:  blr
 
   %t0 = fadd <4 x float> %x0, %x1
@@ -132,6 +134,7 @@ define <4 x float> @vector_reassociate_adds3(<4 x float> %x0, <4 x float> %x1, <
 ; CHECK-PWR:       xvaddsp [[REG0:[0-9]+]], 34, 35
 ; CHECK-PWR:       xvaddsp [[REG1:[0-9]+]], 36, 37
 ; CHECK-PWR:       xvaddsp 34, [[REG0]], [[REG1]]
+; CHECK-PWR:       # kill
 ; CHECK-NEXT:  blr
 
   %t0 = fadd <4 x float> %x0, %x1
@@ -149,6 +152,7 @@ define <4 x float> @vector_reassociate_adds4(<4 x float> %x0, <4 x float> %x1, <
 ; CHECK-PWR:       xvaddsp [[REG0:[0-9]+]], 34, 35
 ; CHECK-PWR:       xvaddsp [[REG1:[0-9]+]], 36, 37
 ; CHECK-PWR:       xvaddsp 34, [[REG0]], [[REG1]]
+; CHECK-PWR:       # kill
 ; CHECK-NEXT:  blr
 
   %t0 = fadd <4 x float> %x0, %x1
diff --git a/test/CodeGen/PowerPC/multi-return.ll b/test/CodeGen/PowerPC/multi-return.ll
new file mode 100644
index 000000000000..454d1e342212
--- /dev/null
+++ b/test/CodeGen/PowerPC/multi-return.ll
@@ -0,0 +1,21 @@
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -O0 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -O2 < %s | FileCheck %s
+
+; Verify that returning multiple return values in registers works,
+; both with fast-isel and regular isel.
+
+define { i32, i32, i32, i32 } @foo() nounwind {
+  %A1 = insertvalue { i32, i32, i32, i32 } undef, i32 1, 0
+  %A2 = insertvalue { i32, i32, i32, i32 } %A1, i32 2, 1
+  %A3 = insertvalue { i32, i32, i32, i32 } %A2, i32 3, 2
+  %A4 = insertvalue { i32, i32, i32, i32 } %A3, i32 4, 3
+  ret { i32, i32, i32, i32 } %A4
+}
+
+; CHECK-LABEL: foo:
+; CHECK: li 3, 1
+; CHECK: li 4, 2
+; CHECK: li 5, 3
+; CHECK: li 6, 4
+; CHECK: blr
+
diff --git a/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir b/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
index 5c998d09a3db..76702ce50fd3 100644
--- a/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
+++ b/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
@@ -1,4 +1,4 @@
-# RUN: llc -start-after=dead-mi-elimination -stop-after=twoaddressinstruction -o /dev/null %s | FileCheck %s
+# RUN: llc -start-after=dead-mi-elimination -stop-after=twoaddressinstruction -o - %s | FileCheck %s
 
 --- |
   target datalayout = "E-m:e-i64:64-n32:64"
diff --git a/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll b/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
new file mode 100644
index 000000000000..1e3de6457337
--- /dev/null
+++ b/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
@@ -0,0 +1,23 @@
+; RUN: llc -print-before=peephole-opt -print-after=peephole-opt -mtriple=powerpc64-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s
+
+define signext i32 @fn1(i32 %baz) {
+  %1 = mul nsw i32 %baz, 208
+  %2 = zext i32 %1 to i64
+  %3 = shl i64 %2, 48
+  %4 = ashr exact i64 %3, 48
+; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,dead>;
+; CHECK: CMPLDI
+; CHECK: BCC
+
+; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def>;
+; CHECK: COPY %CR0
+; CHECK: BCC
+  %5 = icmp eq i64 %4, 0
+  br i1 %5, label %foo, label %bar
+
+foo:
+  ret i32 1
+
+bar:
+  ret i32 0
+}
diff --git a/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir b/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
new file mode 100644
index 000000000000..b835ce71c41d
--- /dev/null
+++ b/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
@@ -0,0 +1,143 @@
+# RUN: llc -start-after=machine-sink -stop-after=peephole-opt -mtriple=powerpc64-unknown-linux-gnu -o - %s | FileCheck %s
+
+--- |
+  ; ModuleID = '<stdin>'
+  source_filename = "<stdin>"
+  target datalayout = "E-m:e-i64:64-n32:64"
+  target triple = "powerpc64-unknown-linux-gnu"
+
+  ; Function Attrs: nounwind readnone
+  declare i128 @llvm.cttz.i128(i128, i1) #0
+
+  define void @fn1(i128, i128, i1) {
+  top:
+    br label %loop
+
+  loop:                                             ; preds = %loop, %top
+    %v = phi i128 [ %3, %loop ], [ %0, %top ]
+    %u = phi i128 [ %3, %loop ], [ %1, %top ]
+    %s = sub i128 %v, %u
+    %3 = call i128 @llvm.cttz.i128(i128 %s, i1 false)
+    br label %loop
+  }
+
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**) #1
+
+  attributes #0 = { nounwind readnone }
+  attributes #1 = { nounwind }
+
+...
+---
+name:            fn1
+alignment:       2
+exposesReturnsTwice: false
+hasInlineAsm:    false
+allVRegsAllocated: false
+isSSA:           true
+tracksRegLiveness: true
+tracksSubRegLiveness: false
+registers:
+  - { id: 0, class: g8rc }
+  - { id: 1, class: g8rc }
+  - { id: 2, class: g8rc }
+  - { id: 3, class: g8rc }
+  - { id: 4, class: g8rc }
+  - { id: 5, class: g8rc }
+  - { id: 6, class: g8rc }
+  - { id: 7, class: g8rc }
+  - { id: 8, class: g8rc }
+  - { id: 9, class: g8rc }
+  - { id: 10, class: g8rc }
+  - { id: 11, class: g8rc }
+  - { id: 12, class: g8rc }
+  - { id: 13, class: g8rc }
+  - { id: 14, class: g8rc }
+  - { id: 15, class: g8rc_and_g8rc_nox0 }
+  - { id: 16, class: g8rc_and_g8rc_nox0 }
+  - { id: 17, class: g8rc }
+  - { id: 18, class: g8rc }
+  - { id: 19, class: g8rc }
+  - { id: 20, class: g8rc }
+  - { id: 21, class: g8rc }
+  - { id: 22, class: g8rc }
+  - { id: 23, class: g8rc }
+  - { id: 24, class: g8rc }
+  - { id: 25, class: crrc }
+  - { id: 26, class: g8rc_and_g8rc_nox0 }
+  - { id: 27, class: g8rc_and_g8rc_nox0 }
+liveins:
+  - { reg: '%x3', virtual-reg: '%6' }
+  - { reg: '%x4', virtual-reg: '%7' }
+  - { reg: '%x5', virtual-reg: '%8' }
+  - { reg: '%x6', virtual-reg: '%9' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    0
+  adjustsStack:    false
+  hasCalls:        false
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+body:             |
+  bb.0.top:
+    successors: %bb.1.loop
+    liveins: %x3, %x4, %x5, %x6
+
+    %9 = COPY %x6
+    %8 = COPY %x5
+    %7 = COPY %x4
+    %6 = COPY %x3
+    %14 = COPY %9
+    %13 = COPY %8
+    %12 = COPY %7
+    %11 = COPY %6
+    %21 = LI8 128
+    %23 = LI8 64
+
+  bb.1.loop:
+    successors: %bb.2.loop, %bb.4
+
+    %0 = PHI %11, %bb.0.top, %4, %bb.3.loop
+    %1 = PHI %12, %bb.0.top, %5, %bb.3.loop
+    %2 = PHI %13, %bb.0.top, %4, %bb.3.loop
+    %3 = PHI %14, %bb.0.top, %5, %bb.3.loop
+    %15 = SUBFC8 %3, %1, implicit-def %carry
+    %16 = SUBFE8 %2, %0, implicit-def dead %carry, implicit %carry
+    %17 = ADDI8 %16, -1
+    %18 = ADDI8 %15, -1
+    %19 = ANDC8 killed %17, %16
+    %20 = ANDC8 killed %18, %15
+    %22 = CNTLZD killed %19
+    %24 = CNTLZD killed %20
+    %25 = CMPLDI %15, 0
+    BCC 76, %25, %bb.2.loop
+    ; CHECK: SUBFC8o %3, %1, implicit-def %carry, implicit-def %cr0
+    ; CHECK: COPY killed %cr0
+    ; CHECK: BCC
+
+  bb.4:
+    successors: %bb.3.loop
+
+    %27 = SUBF8 %24, %23
+    B %bb.3.loop
+
+  bb.2.loop:
+    successors: %bb.3.loop
+
+    %26 = SUBF8 %22, %21
+
+  bb.3.loop:
+    successors: %bb.1.loop
+
+    %5 = PHI %26, %bb.2.loop, %27, %bb.4
+    %4 = LI8 0
+    B %bb.1.loop
+
+...
diff --git a/test/CodeGen/PowerPC/optcmp.ll b/test/CodeGen/PowerPC/optcmp.ll
index d929eae20608..3f7522c0c801 100644
--- a/test/CodeGen/PowerPC/optcmp.ll
+++ b/test/CodeGen/PowerPC/optcmp.ll
@@ -72,13 +72,13 @@ define i64 @foold(i64 %a, i64 %b, i64* nocapture %c) #0 {
 entry:
   %sub = sub nsw i64 %b, %a
   store i64 %sub, i64* %c, align 8
-  %cmp = icmp eq i64 %a, %b
+  %cmp = icmp slt i64 %a, %b
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 
 ; CHECK: @foold
 ; CHECK: subf. [[REG:[0-9]+]], 3, 4
-; CHECK: isel 3, 3, 4, 2
+; CHECK: isel 3, 3, 4, 1
 ; CHECK: std [[REG]], 0(5)
 }
 
@@ -86,13 +86,13 @@ define i64 @foold2(i64 %a, i64 %b, i64* nocapture %c) #0 {
 entry:
   %sub = sub nsw i64 %a, %b
   store i64 %sub, i64* %c, align 8
-  %cmp = icmp eq i64 %a, %b
+  %cmp = icmp slt i64 %a, %b
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 
 ; CHECK: @foold2
 ; CHECK: subf. [[REG:[0-9]+]], 4, 3
-; CHECK: isel 3, 3, 4, 2
+; CHECK: isel 3, 3, 4, 0
 ; CHECK: std [[REG]], 0(5)
 }
 
diff --git a/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
index 8da8df58a85c..b34518431339 100644
--- a/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
+++ b/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
@@ -1102,7 +1102,7 @@ entry:
 ; CHECK: mfvsrwz 3, [[SHL]]
 ; CHECK: extsw 3, 3
 ; CHECK-LE-LABEL: @getsi0
-; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 2
+; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34
 ; CHECK-LE: mfvsrwz 3, [[SHL]]
 ; CHECK-LE: extsw 3, 3
 }
@@ -1150,7 +1150,7 @@ entry:
   %vecext = extractelement <4 x i32> %0, i32 3
   ret i32 %vecext
 ; CHECK-LABEL: @getsi3
-; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 2
+; CHECK: xxswapd [[SHL:[0-9]+]], 34
 ; CHECK: mfvsrwz 3, [[SHL]]
 ; CHECK: extsw 3, 3
 ; CHECK-LE-LABEL: @getsi3
@@ -1172,7 +1172,7 @@ entry:
 ; CHECK: mfvsrwz 3, [[SHL]]
 ; CHECK: clrldi   3, 3, 32
 ; CHECK-LE-LABEL: @getui0
-; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 2
+; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34
 ; CHECK-LE: mfvsrwz 3, [[SHL]]
 ; CHECK-LE: clrldi   3, 3, 32
 }
@@ -1220,7 +1220,7 @@ entry:
   %vecext = extractelement <4 x i32> %0, i32 3
   ret i32 %vecext
 ; CHECK-LABEL: @getui3
-; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 2
+; CHECK: xxswapd [[SHL:[0-9]+]], 34
 ; CHECK: mfvsrwz 3, [[SHL]]
 ; CHECK: clrldi   3, 3, 32
 ; CHECK-LE-LABEL: @getui3
@@ -1380,7 +1380,7 @@ entry:
 ; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
 ; CHECK: xscvspdpn 1, [[SHL]]
 ; CHECK-LE-LABEL: @getf1
-; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 2
+; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34
 ; CHECK-LE: xscvspdpn 1, [[SHL]]
 }
 
@@ -1393,7 +1393,7 @@ entry:
   %vecext = extractelement <4 x float> %0, i32 2
   ret float %vecext
 ; CHECK-LABEL: @getf2
-; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 2
+; CHECK: xxswapd [[SHL:[0-9]+]], 34
 ; CHECK: xscvspdpn 1, [[SHL]]
 ; CHECK-LE-LABEL: @getf2
 ; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1
diff --git a/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll b/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll
index 052f55644fe2..74dc1561d9f4 100644
--- a/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll
+++ b/test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll
@@ -9,7 +9,8 @@ entry:
   ret <2 x i32> %strided.vec
 
 ; CHECK-LABEL: @test1
-; CHECK: vsldoi 2, 2, 2, 12
+; CHECK: xxswapd 35, 34
+; CHECK: vmrghw 2, 2, 3
 ; CHECK: blr
 }
 
diff --git a/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll b/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
new file mode 100644
index 000000000000..ac187e084257
--- /dev/null
+++ b/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
@@ -0,0 +1,970 @@
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE
+
+define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 2
+; CHECK: xxinsertw 34, 0, 12
+; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 3
+; CHECK-BE: xxinsertw 34, 0, 0
+  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 1
+; CHECK: xxinsertw 34, 0, 12
+; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_
+; CHECK-BE-NOT: xxsldwi
+; CHECK-BE: xxinsertw 34, 35, 0
+  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_
+; CHECK-NOT: xxsldwi
+; CHECK: xxinsertw 34, 35, 12
+; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 1
+; CHECK-BE: xxinsertw 34, 0, 0
+  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 3
+; CHECK: xxinsertw 34, 0, 12
+; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 2
+; CHECK-BE: xxinsertw 34, 0, 0
+  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 2
+; CHECK: xxinsertw 34, 0, 8
+; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 3
+; CHECK-BE: xxinsertw 34, 0, 4
+  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 1
+; CHECK: xxinsertw 34, 0, 8
+; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_
+; CHECK-BE-NOT: xxsldwi
+; CHECK-BE: xxinsertw 34, 35, 4
+  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_
+; CHECK-NOT: xxsldwi
+; CHECK: xxinsertw 34, 35, 8
+; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 1
+; CHECK-BE: xxinsertw 34, 0, 4
+  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 3
+; CHECK: xxinsertw 34, 0, 8
+; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 2
+; CHECK-BE: xxinsertw 34, 0, 4
+  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 2
+; CHECK: xxinsertw 34, 0, 4
+; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 3
+; CHECK-BE: xxinsertw 34, 0, 8
+  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 1
+; CHECK: xxinsertw 34, 0, 4
+; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_
+; CHECK-BE-NOT: xxsldwi
+; CHECK-BE: xxinsertw 34, 35, 8
+  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_
+; CHECK-NOT: xxsldwi
+; CHECK: xxinsertw 34, 35, 4
+; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 1
+; CHECK-BE: xxinsertw 34, 0, 8
+  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 3
+; CHECK: xxinsertw 34, 0, 4
+; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 2
+; CHECK-BE: xxinsertw 34, 0, 8
+  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 2
+; CHECK: xxinsertw 34, 0, 0
+; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 3
+; CHECK-BE: xxinsertw 34, 0, 12
+  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 1
+; CHECK: xxinsertw 34, 0, 0
+; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_
+; CHECK-BE-NOT: xxsldwi
+; CHECK-BE: xxinsertw 34, 35, 12
+  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_
+; CHECK-NOT: xxsldwi
+; CHECK: xxinsertw 34, 35, 0
+; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 1
+; CHECK-BE: xxinsertw 34, 0, 12
+  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 3
+; CHECK: xxinsertw 34, 0, 0
+; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 2
+; CHECK-BE: xxinsertw 34, 0, 12
+  %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+  ret <4 x float> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 2
+; CHECK: xxinsertw 34, 0, 12
+; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 3
+; CHECK-BE: xxinsertw 34, 0, 0
+  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 1
+; CHECK: xxinsertw 34, 0, 12
+; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_
+; CHECK-BE-NOT: xxsldwi
+; CHECK-BE: xxinsertw 34, 35, 0
+  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_
+; CHECK-NOT: xxsldwi
+; CHECK: xxinsertw 34, 35, 12
+; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 1
+; CHECK-BE: xxinsertw 34, 0, 0
+  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 3
+; CHECK: xxinsertw 34, 0, 12
+; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 2
+; CHECK-BE: xxinsertw 34, 0, 0
+  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 2
+; CHECK: xxinsertw 34, 0, 8
+; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 3
+; CHECK-BE: xxinsertw 34, 0, 4
+  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 1
+; CHECK: xxinsertw 34, 0, 8
+; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_
+; CHECK-BE-NOT: xxsldwi
+; CHECK-BE: xxinsertw 34, 35, 4
+  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_
+; CHECK-NOT: xxsldwi
+; CHECK: xxinsertw 34, 35, 8
+; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 1
+; CHECK-BE: xxinsertw 34, 0, 4
+  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 3
+; CHECK: xxinsertw 34, 0, 8
+; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 2
+; CHECK-BE: xxinsertw 34, 0, 4
+  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 2
+; CHECK: xxinsertw 34, 0, 4
+; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 3
+; CHECK-BE: xxinsertw 34, 0, 8
+  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 1
+; CHECK: xxinsertw 34, 0, 4
+; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_
+; CHECK-BE-NOT: xxsldwi
+; CHECK-BE: xxinsertw 34, 35, 8
+  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_
+; CHECK-NOT: xxsldwi
+; CHECK: xxinsertw 34, 35, 4
+; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 1
+; CHECK-BE: xxinsertw 34, 0, 8
+  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 3
+; CHECK: xxinsertw 34, 0, 4
+; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 2
+; CHECK-BE: xxinsertw 34, 0, 8
+  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 2
+; CHECK: xxinsertw 34, 0, 0
+; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 3
+; CHECK-BE: xxinsertw 34, 0, 12
+  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 1
+; CHECK: xxinsertw 34, 0, 0
+; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_
+; CHECK-BE-NOT: xxsldwi
+; CHECK-BE: xxinsertw 34, 35, 12
+  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_
+; CHECK-NOT: xxsldwi
+; CHECK: xxinsertw 34, 35, 0
+; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 1
+; CHECK-BE: xxinsertw 34, 0, 12
+  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 3
+; CHECK: xxinsertw 34, 0, 0
+; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 2
+; CHECK-BE: xxinsertw 34, 0, 12
+  %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+  ret <4 x i32> %vecins
+}
+
+define float @_Z13testUiToFpExtILj0EEfDv4_j(<4 x i32> %a) {
+entry:
+; CHECK-LABEL: _Z13testUiToFpExtILj0EEfDv4_j
+; CHECK: xxextractuw 0, 34, 12
+; CHECK: xscvuxdsp 1, 0
+; CHECK-BE-LABEL: _Z13testUiToFpExtILj0EEfDv4_j
+; CHECK-BE: xxextractuw 0, 34, 0
+; CHECK-BE: xscvuxdsp 1, 0
+  %vecext = extractelement <4 x i32> %a, i32 0
+  %conv = uitofp i32 %vecext to float
+  ret float %conv
+}
+
+define float @_Z13testUiToFpExtILj1EEfDv4_j(<4 x i32> %a) {
+entry:
+; CHECK-LABEL: _Z13testUiToFpExtILj1EEfDv4_j
+; CHECK: xxextractuw 0, 34, 8
+; CHECK: xscvuxdsp 1, 0
+; CHECK-BE-LABEL: _Z13testUiToFpExtILj1EEfDv4_j
+; CHECK-BE: xxextractuw 0, 34, 4
+; CHECK-BE: xscvuxdsp 1, 0
+  %vecext = extractelement <4 x i32> %a, i32 1
+  %conv = uitofp i32 %vecext to float
+  ret float %conv
+}
+
+define float @_Z13testUiToFpExtILj2EEfDv4_j(<4 x i32> %a) {
+entry:
+; CHECK-LABEL: _Z13testUiToFpExtILj2EEfDv4_j
+; CHECK: xxextractuw 0, 34, 4
+; CHECK: xscvuxdsp 1, 0
+; CHECK-BE-LABEL: _Z13testUiToFpExtILj2EEfDv4_j
+; CHECK-BE: xxextractuw 0, 34, 8
+; CHECK-BE: xscvuxdsp 1, 0
+  %vecext = extractelement <4 x i32> %a, i32 2
+  %conv = uitofp i32 %vecext to float
+  ret float %conv
+}
+
+define float @_Z13testUiToFpExtILj3EEfDv4_j(<4 x i32> %a) {
+entry:
+; CHECK-LABEL: _Z13testUiToFpExtILj3EEfDv4_j
+; CHECK: xxextractuw 0, 34, 0
+; CHECK: xscvuxdsp 1, 0
+; CHECK-BE-LABEL: _Z13testUiToFpExtILj3EEfDv4_j
+; CHECK-BE: xxextractuw 0, 34, 12
+; CHECK-BE: xscvuxdsp 1, 0
+  %vecext = extractelement <4 x i32> %a, i32 3
+  %conv = uitofp i32 %vecext to float
+  ret float %conv
+}
+
+define <4 x float> @_Z10testInsEltILj0EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
+entry:
+; CHECK-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_
+; CHECK: xscvdpspn 0, 1
+; CHECK: xxsldwi 0, 0, 0, 3
+; CHECK: xxinsertw 34, 0, 12
+; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_
+; CHECK-BE: xscvdpspn 0, 1
+; CHECK-BE: xxsldwi 0, 0, 0, 3
+; CHECK-BE: xxinsertw 34, 0, 0
+  %vecins = insertelement <4 x float> %a, float %b, i32 0
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z10testInsEltILj1EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
+entry:
+; CHECK-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_
+; CHECK: xscvdpspn 0, 1
+; CHECK: xxsldwi 0, 0, 0, 3
+; CHECK: xxinsertw 34, 0, 8
+; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_
+; CHECK-BE: xscvdpspn 0, 1
+; CHECK-BE: xxsldwi 0, 0, 0, 3
+; CHECK-BE: xxinsertw 34, 0, 4
+  %vecins = insertelement <4 x float> %a, float %b, i32 1
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z10testInsEltILj2EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
+entry:
+; CHECK-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_
+; CHECK: xscvdpspn 0, 1
+; CHECK: xxsldwi 0, 0, 0, 3
+; CHECK: xxinsertw 34, 0, 4
+; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_
+; CHECK-BE: xscvdpspn 0, 1
+; CHECK-BE: xxsldwi 0, 0, 0, 3
+; CHECK-BE: xxinsertw 34, 0, 8
+  %vecins = insertelement <4 x float> %a, float %b, i32 2
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z10testInsEltILj3EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {
+entry:
+; CHECK-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_
+; CHECK: xscvdpspn 0, 1
+; CHECK: xxsldwi 0, 0, 0, 3
+; CHECK: xxinsertw 34, 0, 0
+; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_
+; CHECK-BE: xscvdpspn 0, 1
+; CHECK-BE: xxsldwi 0, 0, 0, 3
+; CHECK-BE: xxinsertw 34, 0, 12
+  %vecins = insertelement <4 x float> %a, float %b, i32 3
+  ret <4 x float> %vecins
+}
+
+define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
+entry:
+; CHECK-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_
+; CHECK: mtvsrwz 0, 5
+; CHECK: xxinsertw 34, 0, 12
+; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_
+; CHECK-BE: mtvsrwz 0, 5
+; CHECK-BE: xxinsertw 34, 0, 0
+  %vecins = insertelement <4 x i32> %a, i32 %b, i32 0
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z10testInsEltILj1EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
+entry:
+; CHECK-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_
+; CHECK: mtvsrwz 0, 5
+; CHECK: xxinsertw 34, 0, 8
+; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_
+; CHECK-BE: mtvsrwz 0, 5
+; CHECK-BE: xxinsertw 34, 0, 4
+  %vecins = insertelement <4 x i32> %a, i32 %b, i32 1
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z10testInsEltILj2EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
+entry:
+; CHECK-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_
+; CHECK: mtvsrwz 0, 5
+; CHECK: xxinsertw 34, 0, 4
+; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_
+; CHECK-BE: mtvsrwz 0, 5
+; CHECK-BE: xxinsertw 34, 0, 8
+  %vecins = insertelement <4 x i32> %a, i32 %b, i32 2
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z10testInsEltILj3EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
+entry:
+; CHECK-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_
+; CHECK: mtvsrwz 0, 5
+; CHECK: xxinsertw 34, 0, 0
+; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_
+; CHECK-BE: mtvsrwz 0, 5
+; CHECK-BE: xxinsertw 34, 0, 12
+  %vecins = insertelement <4 x i32> %a, i32 %b, i32 3
+  ret <4 x i32> %vecins
+}
+
+define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 2
+; CHECK: xxinsertw 34, 0, 12
+; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 3
+; CHECK-BE: xxinsertw 34, 0, 0
+  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 1
+; CHECK: xxinsertw 34, 0, 12
+; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_
+; CHECK-BE-NOT: xxsldwi
+; CHECK-BE: xxinsertw 34, 35, 0
+  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_
+; CHECK-NOT: xxsldwi
+; CHECK: xxinsertw 34, 35, 12
+; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 1
+; CHECK-BE: xxinsertw 34, 0, 0
+  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 3
+; CHECK: xxinsertw 34, 0, 12
+; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 2
+; CHECK-BE: xxinsertw 34, 0, 0
+  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 2
+; CHECK: xxinsertw 34, 0, 8
+; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 3
+; CHECK-BE: xxinsertw 34, 0, 4
+  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 1
+; CHECK: xxinsertw 34, 0, 8
+; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_
+; CHECK-BE-NOT: xxsldwi
+; CHECK-BE: xxinsertw 34, 35, 4
+  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_
+; CHECK-NOT: xxsldwi
+; CHECK: xxinsertw 34, 35, 8
+; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 1
+; CHECK-BE: xxinsertw 34, 0, 4
+  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 3
+; CHECK: xxinsertw 34, 0, 8
+; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 2
+; CHECK-BE: xxinsertw 34, 0, 4
+  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 2
+; CHECK: xxinsertw 34, 0, 4
+; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 3
+; CHECK-BE: xxinsertw 34, 0, 8
+  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 1
+; CHECK: xxinsertw 34, 0, 4
+; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_
+; CHECK-BE-NOT: xxsldwi
+; CHECK-BE: xxinsertw 34, 35, 8
+  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_
+; CHECK-NOT: xxsldwi
+; CHECK: xxinsertw 34, 35, 4
+; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 1
+; CHECK-BE: xxinsertw 34, 0, 8
+  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 3
+; CHECK: xxinsertw 34, 0, 4
+; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 2
+; CHECK-BE: xxinsertw 34, 0, 8
+  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 2
+; CHECK: xxinsertw 34, 0, 0
+; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 3
+; CHECK-BE: xxinsertw 34, 0, 12
+  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 1
+; CHECK: xxinsertw 34, 0, 0
+; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_
+; CHECK-BE-NOT: xxsldwi
+; CHECK-BE: xxinsertw 34, 35, 12
+  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_
+; CHECK-NOT: xxsldwi
+; CHECK: xxinsertw 34, 35, 0
+; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 1
+; CHECK-BE: xxinsertw 34, 0, 12
+  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2>
+  ret <4 x float> %vecins
+}
+
+define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 3
+; CHECK: xxinsertw 34, 0, 0
+; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 2
+; CHECK-BE: xxinsertw 34, 0, 12
+  %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3>
+  ret <4 x float> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 2
+; CHECK: xxinsertw 34, 0, 12
+; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 3
+; CHECK-BE: xxinsertw 34, 0, 0
+  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 1
+; CHECK: xxinsertw 34, 0, 12
+; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_
+; CHECK-BE-NOT: xxsldwi
+; CHECK-BE: xxinsertw 34, 35, 0
+  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_
+; CHECK-NOT: xxsldwi
+; CHECK: xxinsertw 34, 35, 12
+; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 1
+; CHECK-BE: xxinsertw 34, 0, 0
+  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 3
+; CHECK: xxinsertw 34, 0, 12
+; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 2
+; CHECK-BE: xxinsertw 34, 0, 0
+  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 2
+; CHECK: xxinsertw 34, 0, 8
+; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 3
+; CHECK-BE: xxinsertw 34, 0, 4
+  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 1
+; CHECK: xxinsertw 34, 0, 8
+; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_
+; CHECK-BE-NOT: xxsldwi
+; CHECK-BE: xxinsertw 34, 35, 4
+  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_
+; CHECK-NOT: xxsldwi
+; CHECK: xxinsertw 34, 35, 8
+; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 1
+; CHECK-BE: xxinsertw 34, 0, 4
+  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 3
+; CHECK: xxinsertw 34, 0, 8
+; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 2
+; CHECK-BE: xxinsertw 34, 0, 4
+  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 2
+; CHECK: xxinsertw 34, 0, 4
+; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 3
+; CHECK-BE: xxinsertw 34, 0, 8
+  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 1
+; CHECK: xxinsertw 34, 0, 4
+; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_
+; CHECK-BE-NOT: xxsldwi
+; CHECK-BE: xxinsertw 34, 35, 8
+  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_
+; CHECK-NOT: xxsldwi
+; CHECK: xxinsertw 34, 35, 4
+; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 1
+; CHECK-BE: xxinsertw 34, 0, 8
+  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 3
+; CHECK: xxinsertw 34, 0, 4
+; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 2
+; CHECK-BE: xxinsertw 34, 0, 8
+  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 2
+; CHECK: xxinsertw 34, 0, 0
+; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 3
+; CHECK-BE: xxinsertw 34, 0, 12
+  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 1
+; CHECK: xxinsertw 34, 0, 0
+; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_
+; CHECK-BE-NOT: xxsldwi
+; CHECK-BE: xxinsertw 34, 35, 12
+  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_
+; CHECK-NOT: xxsldwi
+; CHECK: xxinsertw 34, 35, 0
+; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 1
+; CHECK-BE: xxinsertw 34, 0, 12
+  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2>
+  ret <4 x i32> %vecins
+}
+
+define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {
+entry:
+; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_
+; CHECK: xxsldwi 0, 35, 35, 3
+; CHECK: xxinsertw 34, 0, 0
+; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_
+; CHECK-BE: xxsldwi 0, 35, 35, 2
+; CHECK-BE: xxinsertw 34, 0, 12
+  %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3>
+  ret <4 x i32> %vecins
+}
+define <4 x float> @testSameVecEl0BE(<4 x float> %a) {
+entry:
+; CHECK-BE-LABEL: testSameVecEl0BE
+; CHECK-BE: xxinsertw 34, 34, 0
+  %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 5, i32 1, i32 2, i32 3>
+  ret <4 x float> %vecins
+}
+define <4 x float> @testSameVecEl2BE(<4 x float> %a) {
+entry:
+; CHECK-BE-LABEL: testSameVecEl2BE
+; CHECK-BE: xxinsertw 34, 34, 8
+  %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
+  ret <4 x float> %vecins
+}
+define <4 x float> @testSameVecEl3BE(<4 x float> %a) {
+entry:
+; CHECK-BE-LABEL: testSameVecEl3BE
+; CHECK-BE: xxinsertw 34, 34, 12
+  %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
+  ret <4 x float> %vecins
+}
+define <4 x float> @testSameVecEl0LE(<4 x float> %a) {
+entry:
+; CHECK-LABEL: testSameVecEl0LE
+; CHECK: xxinsertw 34, 34, 12
+  %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 6, i32 1, i32 2, i32 3>
+  ret <4 x float> %vecins
+}
+define <4 x float> @testSameVecEl1LE(<4 x float> %a) {
+entry:
+; CHECK-LABEL: testSameVecEl1LE
+; CHECK: xxinsertw 34, 34, 8
+  %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
+  ret <4 x float> %vecins
+}
+define <4 x float> @testSameVecEl3LE(<4 x float> %a) {
+entry:
+; CHECK-LABEL: testSameVecEl3LE
+; CHECK: xxinsertw 34, 34, 0
+  %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
+  ret <4 x float> %vecins
+}
diff --git a/test/CodeGen/PowerPC/pie.ll b/test/CodeGen/PowerPC/pie.ll
new file mode 100644
index 000000000000..56e07caf2812
--- /dev/null
+++ b/test/CodeGen/PowerPC/pie.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=powerpc-pc-linux -relocation-model=pic | FileCheck %s
+
+
+define void @f() {
+  ret void
+}
+
+define void @g() {
+; CHECK: g:
+; CHECK: bl f{{$}}
+  call void @f()
+  ret void
+}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"PIE Level", i32 1}
diff --git a/test/CodeGen/PowerPC/popcnt.ll b/test/CodeGen/PowerPC/popcnt.ll
index b304d72aede2..5acaa29e2ee5 100644
--- a/test/CodeGen/PowerPC/popcnt.ll
+++ b/test/CodeGen/PowerPC/popcnt.ll
@@ -1,37 +1,53 @@
 ; RUN: llc -march=ppc64 -mattr=+popcntd < %s | FileCheck %s
+; RUN: llc -march=ppc64 -mattr=+slow-popcntd < %s | FileCheck %s --check-prefix=SLOWPC
+; RUN: llc -march=ppc64 -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -march=ppc64 -mcpu=a2q < %s | FileCheck %s --check-prefix=SLOWPC
+; RUN: llc -march=ppc64 -mcpu=a2q -mattr=+popcntd < %s | FileCheck %s
 
 define i8 @cnt8(i8 %x) nounwind readnone {
   %cnt = tail call i8 @llvm.ctpop.i8(i8 %x)
   ret i8 %cnt
-; CHECK: @cnt8
+; CHECK-LABEL: @cnt8
 ; CHECK: rlwinm
 ; CHECK: popcntw
 ; CHECK: blr
+
+; SLOWPC-LABEL: @cnt8
+; SLOWPC-NOT: popcnt
 }
 
 define i16 @cnt16(i16 %x) nounwind readnone {
   %cnt = tail call i16 @llvm.ctpop.i16(i16 %x)
   ret i16 %cnt
-; CHECK: @cnt16
+; CHECK-LABEL: @cnt16
 ; CHECK: rlwinm
 ; CHECK: popcntw
 ; CHECK: blr
+
+; SLOWPC-LABEL: @cnt16
+; SLOWPC-NOT: popcnt
 }
 
 define i32 @cnt32(i32 %x) nounwind readnone {
   %cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
   ret i32 %cnt
-; CHECK: @cnt32
+; CHECK-LABEL: @cnt32
 ; CHECK: popcntw
 ; CHECK: blr
+
+; SLOWPC-LABEL: @cnt32
+; SLOWPC-NOT: popcnt
 }
 
 define i64 @cnt64(i64 %x) nounwind readnone {
   %cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
   ret i64 %cnt
-; CHECK: @cnt64
+; CHECK-LABEL: @cnt64
 ; CHECK: popcntd
 ; CHECK: blr
+
+; SLOWPC-LABEL: @cnt64
+; SLOWPC-NOT: popcnt
 }
 
 declare i8 @llvm.ctpop.i8(i8) nounwind readnone
diff --git a/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll b/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
index 2f75190327ef..3dcb0b2aee1d 100644
--- a/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
+++ b/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
@@ -169,7 +169,7 @@ declare i32 @something(...)
 ; CHECK-NEXT: bne 0, .[[LOOP]]
 ;
 ; Next BB
-; CHECK: %for.exit
+; CHECK: %for.end
 ; CHECK: mtlr {{[0-9]+}}
 ; CHECK-NEXT: blr
 define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {
@@ -629,10 +629,11 @@ end:
 ; CHECK-LABEL: transpose
 ;
 ; Store of callee-save register saved by shrink wrapping
-; CHECK: std [[CSR:[0-9]+]], -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
+; FIXME: Test disabled: Improved scheduling needs no spills/reloads any longer!
+; CHECKXX: std [[CSR:[0-9]+]], -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
 ;
 ; Reload of callee-save register
-; CHECK: ld [[CSR]], -[[STACK_OFFSET]](1) # 8-byte Folded Reload
+; CHECKXX: ld [[CSR]], -[[STACK_OFFSET]](1) # 8-byte Folded Reload
 ;
 ; Ensure no subsequent uses of callee-save register before end of function
 ; CHECK-NOT: {{[a-z]+}} [[CSR]]
diff --git a/test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll b/test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll
new file mode 100644
index 000000000000..f8a6d071cfea
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll
@@ -0,0 +1,21 @@
+; RUN: llc -O2 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s
+
+@x = global ppc_fp128 0xM405EDA5E353F7CEE0000000000000000, align 16
+@.str = private unnamed_addr constant [5 x i8] c"%Lf\0A\00", align 1
+
+
+define void @foo() #0 {
+entry:
+  %0 = load ppc_fp128, ppc_fp128* @x, align 16
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), ppc_fp128 %0)
+  ret void
+}
+; Do not skip register r4 because of register alignment in soft float mode. Instead skipping 
+; put in r4 part of first argument for printf function (long double).
+; CHECK: lwzu 4, x@l({{[0-9]+}})
+
+declare i32 @printf(i8* nocapture readonly, ...) #0
+
+attributes #0 = { "use-soft-float"="true" }
+
+                        
\ No newline at end of file
diff --git a/test/CodeGen/PowerPC/ppc32-constant-BE-ppcf128.ll b/test/CodeGen/PowerPC/ppc32-constant-BE-ppcf128.ll
new file mode 100644
index 000000000000..3a23ae31a851
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc32-constant-BE-ppcf128.ll
@@ -0,0 +1,24 @@
+; RUN: llc -O2 -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s
+
+target datalayout = "E-m:e-p:32:32-i64:64-n32"
+target triple = "powerpc-buildroot-linux-gnu"
+
+@.str = private unnamed_addr constant [5 x i8] c"%Lf\0A\00", align 1
+
+define i32 @main() #0 {
+entry:
+  %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i32 0, i32 0), ppc_fp128 0xM3FF00000000000000000000000000000)
+  ret i32 0
+}
+
+; First available register for long double argument is r4, so put
+; Hi part in r4/r5, Lo part in r6/r7 (do not switch Hi/Lo parts)
+; CHECK: lis 4, 16368
+; CHECK-NOT: lis 6, 16368
+; CHECK: li 5, 0
+; CHECK: li 7, 0
+
+declare i32 @printf(i8* nocapture readonly, ...)
+
+attributes #0 = { "use-soft-float"="true" }
+
diff --git a/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll b/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll
index 028006320cb5..272d882c8bbf 100644
--- a/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll
+++ b/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -march=ppc32 -mcpu=ppc32 | FileCheck %s
-; RUN: llc < %s -march=ppc32 -mcpu=ppc32 -mtriple=powerpc-darwin | FileCheck %s -check-prefix=CHECK-D
+; RUN: llc < %s -march=ppc32 -mcpu=ppc32 -mtriple=powerpc-darwin9 | FileCheck %s -check-prefix=CHECK-D
 target triple = "powerpc-unknown-linux-gnu"
 
 declare void @printf(i8*, ...)
@@ -16,5 +16,5 @@ define void @main() {
 
 ; CHECK-D-LABEL: @main
 ; CHECK-D: li r4, 0
-; CHECK-D: bl L_printf$stub
+; CHECK-D: bl _printf
 
diff --git a/test/CodeGen/PowerPC/ppc64-align-long-double.ll b/test/CodeGen/PowerPC/ppc64-align-long-double.ll
index b9fd6707f041..b268ceeafd5d 100644
--- a/test/CodeGen/PowerPC/ppc64-align-long-double.ll
+++ b/test/CodeGen/PowerPC/ppc64-align-long-double.ll
@@ -18,17 +18,17 @@ entry:
   ret ppc_fp128 %0
 }
 
-; CHECK: std 6, 72(1)
-; CHECK: std 5, 64(1)
-; CHECK: std 4, 56(1)
-; CHECK: std 3, 48(1)
+; CHECK-DAG: std 6, 72(1)
+; CHECK-DAG: std 5, 64(1)
+; CHECK-DAG: std 4, 56(1)
+; CHECK-DAG: std 3, 48(1)
 ; CHECK: lfd 1, 64(1)
 ; CHECK: lfd 2, 72(1)
 
-; CHECK-VSX: std 6, 72(1)
-; CHECK-VSX: std 5, 64(1)
-; CHECK-VSX: std 4, 56(1)
-; CHECK-VSX: std 3, 48(1)
+; CHECK-VSX-DAG: std 6, 72(1)
+; CHECK-VSX-DAG: std 5, 64(1)
+; CHECK-VSX-DAG: std 4, 56(1)
+; CHECK-VSX-DAG: std 3, 48(1)
 ; CHECK-VSX: li 3, 16
 ; CHECK-VSX: addi 4, 1, 48
 ; CHECK-VSX: lxsdx 1, 4, 3
diff --git a/test/CodeGen/PowerPC/ppc64-byval-align.ll b/test/CodeGen/PowerPC/ppc64-byval-align.ll
index 7170f5906581..89e7cc6c50eb 100644
--- a/test/CodeGen/PowerPC/ppc64-byval-align.ll
+++ b/test/CodeGen/PowerPC/ppc64-byval-align.ll
@@ -35,8 +35,7 @@ entry:
   ret i64 %0
 }
 ; CHECK-LABEL: @callee2
-; CHECK: ld [[REG:[0-9]+]], 128(1)
-; CHECK: mr 3, [[REG]]
+; CHECK: ld 3, 128(1)
 ; CHECK: blr
 
 declare i64 @test2(%struct.pad* byval, i32 signext, %struct.test* byval align 16)
diff --git a/test/CodeGen/PowerPC/ppc64-calls.ll b/test/CodeGen/PowerPC/ppc64-calls.ll
index 23a14e6687d6..8b49cdb7f99c 100644
--- a/test/CodeGen/PowerPC/ppc64-calls.ll
+++ b/test/CodeGen/PowerPC/ppc64-calls.ll
@@ -2,7 +2,8 @@
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
-define void @foo() nounwind readnone noinline {
+
+define void @foo() nounwind noinline {
   ret void
 }
 
@@ -14,7 +15,8 @@ define weak void @foo_weak() nounwind {
 define void @test_direct() nounwind readnone {
 ; CHECK-LABEL: test_direct:
   tail call void @foo() nounwind
-; CHECK: bl foo
+; Because of tail call optimization, it can be 'b' instruction.
+; CHECK: [[BR:b[l]?]] foo
 ; CHECK-NOT: nop
   ret void
 }
diff --git a/test/CodeGen/PowerPC/ppc64-fastcc.ll b/test/CodeGen/PowerPC/ppc64-fastcc.ll
index 69e15d104da8..76677ecdf033 100644
--- a/test/CodeGen/PowerPC/ppc64-fastcc.ll
+++ b/test/CodeGen/PowerPC/ppc64-fastcc.ll
@@ -1,4 +1,6 @@
 ; RUN: llc -mcpu=pwr7 -mattr=-vsx < %s | FileCheck %s
+; XFAIL: *
+
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
@@ -522,7 +524,7 @@ define void @cv13(<4 x i32> %v) #0 {
 
 ; CHECK-LABEL: @cv13
 ; CHECK-DAG: li [[REG1:[0-9]+]], 96
-; CHECK-DAG: vor [[REG2:[0-9]+]], 2, 2
+; CHECK-DAG: vor [[REG2:[0-9]+]], 3, 3
 ; CHECK: stvx [[REG2]], 1, [[REG1]]
 ; CHECK: blr
 }
@@ -533,7 +535,7 @@ define void @cv14(<4 x i32> %v) #0 {
 
 ; CHECK-LABEL: @cv14
 ; CHECK-DAG: li [[REG1:[0-9]+]], 128
-; CHECK-DAG: vor [[REG2:[0-9]+]], 2, 2
+; CHECK-DAG: vor [[REG2:[0-9]+]], 3, 3
 ; CHECK: stvx [[REG2]], 1, [[REG1]]
 ; CHECK: blr
 }
diff --git a/test/CodeGen/PowerPC/ppc64-linux-func-size.ll b/test/CodeGen/PowerPC/ppc64-linux-func-size.ll
index fb017bc224ba..6f8351bb5bdd 100644
--- a/test/CodeGen/PowerPC/ppc64-linux-func-size.ll
+++ b/test/CodeGen/PowerPC/ppc64-linux-func-size.ll
@@ -2,7 +2,7 @@
 
 ; CHECK:      .section	.opd,"aw",@progbits
 ; CHECK-NEXT: test1:
-; CHECK-NEXT:	.align 3
+; CHECK-NEXT:	.p2align 3
 ; CHECK-NEXT:	.quad .L[[BEGIN:.*]]
 ; CHECK-NEXT:	.quad .TOC.@tocbase
 ; CHECK-NEXT:   .quad 0
diff --git a/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll b/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll
new file mode 100644
index 000000000000..b27aeec50b84
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll
@@ -0,0 +1,46 @@
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -disable-ppc-sco=false --enable-shrink-wrap=false | FileCheck %s -check-prefix=CHECK-SCO-ONLY
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -disable-ppc-sco=false --enable-shrink-wrap=true | FileCheck %s -check-prefix=CHECK-SCO-SHRK
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -disable-ppc-sco=false --enable-shrink-wrap=false | FileCheck %s -check-prefix=CHECK-SCO-ONLY
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -disable-ppc-sco=false --enable-shrink-wrap=true | FileCheck %s -check-prefix=CHECK-SCO-SHRK
+
+%"class.clang::NamedDecl" = type { i32 }
+declare void @__assert_fail();
+
+define i8 @_ZNK5clang9NamedDecl23getLinkageAndVisibilityEv(
+    %"class.clang::NamedDecl"* %this) {
+entry:
+  %tobool = icmp eq %"class.clang::NamedDecl"* %this, null
+  br i1 %tobool, label %cond.false, label %exit
+
+cond.false:
+  tail call void @__assert_fail()
+  unreachable
+
+exit:
+  %DeclKind = getelementptr inbounds
+                            %"class.clang::NamedDecl",
+                            %"class.clang::NamedDecl"* %this, i64 0, i32 0
+  %bf.load = load i32, i32* %DeclKind, align 4
+  %call.i = tail call i8 @LVComputationKind(
+    %"class.clang::NamedDecl"* %this,
+    i32 %bf.load)
+  ret i8 %call.i
+
+; CHECK-SCO-SHRK-LABEL: _ZNK5clang9NamedDecl23getLinkageAndVisibilityEv:
+; CHECK-SCO-SHRK: b LVComputationKind
+; CHECK-SCO-SHRK: #TC_RETURNd8
+; CHECK-SCO-SHRK: stdu 1, -{{[0-9]+}}(1)
+; CHECK-SCO-SHRK: bl __assert_fail
+;
+; CHECK-SCO-ONLY-LABEL: _ZNK5clang9NamedDecl23getLinkageAndVisibilityEv:
+; CHECK-SCO-ONLY: stdu 1, -{{[0-9]+}}(1)
+; CHECK-SCO-ONLY: b LVComputationKind
+; CHECK-SCO-ONLY: #TC_RETURNd8
+; CHECK-SCO-ONLY: bl __assert_fail
+}
+
+define fastcc i8 @LVComputationKind(
+    %"class.clang::NamedDecl"* %D,
+    i32 %computation) {
+  ret i8 0
+}
diff --git a/test/CodeGen/PowerPC/ppc64-sibcall.ll b/test/CodeGen/PowerPC/ppc64-sibcall.ll
new file mode 100644
index 000000000000..e4fe5468e942
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc64-sibcall.ll
@@ -0,0 +1,191 @@
+; RUN: llc < %s -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-SCO
+; RUN: llc < %s -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-SCO-HASQPX
+; RUN: llc < %s -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-SCO-HASQPX
+
+; No combination of "powerpc64le-unknown-linux-gnu" + "CHECK-SCO", because
+; only Power8 (and later) fully support LE.
+
+%S_56 = type { [13 x i32], i32 }
+%S_64 = type { [15 x i32], i32 }
+%S_32 = type { [7 x i32], i32 }
+
+; Function Attrs: noinline nounwind
+define void @callee_56_copy([7 x i64] %a, %S_56* %b) #0 { ret void }
+define void @callee_64_copy([8 x i64] %a, %S_64* %b) #0 { ret void }
+
+; Function Attrs: nounwind
+define void @caller_56_reorder_copy(%S_56* %b, [7 x i64] %a) #1 {
+  tail call void @callee_56_copy([7 x i64] %a, %S_56* %b)
+  ret void
+
+; CHECK-SCO-LABEL: caller_56_reorder_copy:
+; CHECK-SCO-NOT: stdu 1
+; CHECK-SCO: TC_RETURNd8 callee_56_copy
+}
+
+define void @caller_64_reorder_copy(%S_64* %b, [8 x i64] %a) #1 {
+  tail call void @callee_64_copy([8 x i64] %a, %S_64* %b)
+  ret void
+
+; CHECK-SCO-LABEL: caller_64_reorder_copy:
+; CHECK-SCO: bl callee_64_copy
+}
+
+define void @callee_64_64_copy([8 x i64] %a, [8 x i64] %b) #0 { ret void }
+define void @caller_64_64_copy([8 x i64] %a, [8 x i64] %b) #1 {
+  tail call void @callee_64_64_copy([8 x i64] %a, [8 x i64] %b)
+  ret void
+
+; CHECK-SCO-LABEL: caller_64_64_copy:
+; CHECK-SCO: b callee_64_64_copy
+}
+
+define void @caller_64_64_reorder_copy([8 x i64] %a, [8 x i64] %b) #1 {
+  tail call void @callee_64_64_copy([8 x i64] %b, [8 x i64] %a)
+  ret void
+
+; CHECK-SCO-LABEL: caller_64_64_reorder_copy:
+; CHECK-SCO: bl callee_64_64_copy
+}
+
+define void @caller_64_64_undef_copy([8 x i64] %a, [8 x i64] %b) #1 {
+  tail call void @callee_64_64_copy([8 x i64] %a, [8 x i64] undef)
+  ret void
+
+; CHECK-SCO-LABEL: caller_64_64_undef_copy:
+; CHECK-SCO: b callee_64_64_copy
+}
+
+define void @arg8_callee(
+  float %a, i32 signext %b, float %c, i32* %d,
+  i8 zeroext %e, float %f, i32* %g, i32 signext %h)
+{
+  ret void
+}
+
+define void @arg8_caller(float %a, i32 signext %b, i8 zeroext %c, i32* %d) {
+entry:
+  tail call void @arg8_callee(float undef, i32 signext undef, float undef,
+                              i32* %d, i8 zeroext undef, float undef,
+                              i32* undef, i32 signext undef)
+  ret void
+
+; CHECK-SCO-LABEL: arg8_caller:
+; CHECK-SCO: b arg8_callee
+}
+
+; Struct return test
+
+; Function Attrs: noinline nounwind
+define void @callee_sret_56(%S_56* noalias sret %agg.result) #0 { ret void }
+define void @callee_sret_32(%S_32* noalias sret %agg.result) #0 { ret void }
+
+; Function Attrs: nounwind
+define void @caller_do_something_sret_32(%S_32* noalias sret %agg.result) #1 {
+  %1 = alloca %S_56, align 4
+  %2 = bitcast %S_56* %1 to i8*
+  call void @callee_sret_56(%S_56* nonnull sret %1)
+  tail call void @callee_sret_32(%S_32* sret %agg.result)
+  ret void
+
+; CHECK-SCO-LABEL: caller_do_something_sret_32:
+; CHECK-SCO: stdu 1
+; CHECK-SCO: bl callee_sret_56
+; CHECK-SCO: addi 1
+; CHECK-SCO: TC_RETURNd8 callee_sret_32
+}
+
+define void @caller_local_sret_32(%S_32* %a) #1 {
+  %tmp = alloca %S_32, align 4
+  tail call void @callee_sret_32(%S_32* nonnull sret %tmp)
+  ret void
+
+; CHECK-SCO-LABEL: caller_local_sret_32:
+; CHECK-SCO: bl callee_sret_32
+}
+
+attributes #0 = { noinline nounwind  }
+attributes #1 = { nounwind }
+
+; vector <4 x i1> test
+
+define void @callee_v4i1(i8 %a, <4 x i1> %b, <4 x i1> %c) { ret void }
+define void @caller_v4i1_reorder(i8 %a, <4 x i1> %b, <4 x i1> %c) {
+  tail call void @callee_v4i1(i8 %a, <4 x i1> %c, <4 x i1> %b)
+  ret void
+
+; <4 x i1> is 32 bytes aligned, if subtarget doesn't support qpx, then we can't
+; place b, c to qpx register, so we can't do sco on caller_v4i1_reorder
+
+; CHECK-SCO-LABEL: caller_v4i1_reorder:
+; CHECK-SCO: bl callee_v4i1
+
+; CHECK-SCO-HASQPX-LABEL: caller_v4i1_reorder:
+; CHECK-SCO-HASQPX: b callee_v4i1
+}
+
+define void @f128_callee(i32* %ptr, ppc_fp128 %a, ppc_fp128 %b) { ret void }
+define void @f128_caller(i32* %ptr, ppc_fp128 %a, ppc_fp128 %b) {
+  tail call void @f128_callee(i32* %ptr, ppc_fp128 %a, ppc_fp128 %b)
+  ret void
+
+; CHECK-SCO-LABEL: f128_caller:
+; CHECK-SCO: b f128_callee
+}
+
+; weak linkage test
+%class.T = type { [2 x i8] }
+
+define weak_odr hidden void @wo_hcallee(%class.T* %this, i8* %c) { ret void }
+define void @wo_hcaller(%class.T* %this, i8* %c) {
+  tail call void @wo_hcallee(%class.T* %this, i8* %c)
+  ret void
+
+; CHECK-SCO-LABEL: wo_hcaller:
+; CHECK-SCO: b wo_hcallee
+}
+
+define weak_odr protected void @wo_pcallee(%class.T* %this, i8* %c) { ret void }
+define void @wo_pcaller(%class.T* %this, i8* %c) {
+  tail call void @wo_pcallee(%class.T* %this, i8* %c)
+  ret void
+
+; CHECK-SCO-LABEL: wo_pcaller:
+; CHECK-SCO: b wo_pcallee
+}
+
+define weak_odr void @wo_callee(%class.T* %this, i8* %c) { ret void }
+define void @wo_caller(%class.T* %this, i8* %c) {
+  tail call void @wo_callee(%class.T* %this, i8* %c)
+  ret void
+
+; CHECK-SCO-LABEL: wo_caller:
+; CHECK-SCO: bl wo_callee
+}
+
+define weak protected void @w_pcallee(i8* %ptr) { ret void }
+define void @w_pcaller(i8* %ptr) {
+  tail call void @w_pcallee(i8* %ptr)
+  ret void
+
+; CHECK-SCO-LABEL: w_pcaller:
+; CHECK-SCO: b w_pcallee
+}
+
+define weak hidden void @w_hcallee(i8* %ptr) { ret void }
+define void @w_hcaller(i8* %ptr) {
+  tail call void @w_hcallee(i8* %ptr)
+  ret void
+
+; CHECK-SCO-LABEL: w_hcaller:
+; CHECK-SCO: b w_hcallee
+}
+
+define weak void @w_callee(i8* %ptr) { ret void }
+define void @w_caller(i8* %ptr) {
+  tail call void @w_callee(i8* %ptr)
+  ret void
+
+; CHECK-SCO-LABEL: w_caller:
+; CHECK-SCO: bl w_callee
+}
diff --git a/test/CodeGen/PowerPC/ppc64-toc.ll b/test/CodeGen/PowerPC/ppc64-toc.ll
index 7500ed606636..8d35cba2d430 100644
--- a/test/CodeGen/PowerPC/ppc64-toc.ll
+++ b/test/CodeGen/PowerPC/ppc64-toc.ll
@@ -9,7 +9,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 define i64 @access_int64(i64 %a) nounwind readonly {
 entry:
 ; CHECK-LABEL: access_int64:
-; CHECK-NEXT: .align  3
+; CHECK-NEXT: .p2align  3
 ; CHECK-NEXT: .quad   .L[[BEGIN:.*]]
 ; CHECK-NEXT: .quad   .TOC.@tocbase
 ; CHECK-NEXT: .quad   0
diff --git a/test/CodeGen/PowerPC/ppcf128-endian.ll b/test/CodeGen/PowerPC/ppcf128-endian.ll
index ee314c1db58b..49dea37a2dac 100644
--- a/test/CodeGen/PowerPC/ppcf128-endian.ll
+++ b/test/CodeGen/PowerPC/ppcf128-endian.ll
@@ -104,9 +104,10 @@ entry:
   %0 = bitcast i128 %x to ppc_fp128
   ret ppc_fp128 %0
 }
-; CHECK: @convert_to
+; CHECK: convert_to:
 ; CHECK: std 3, [[OFF1:.*]](1)
 ; CHECK: std 4, [[OFF2:.*]](1)
+; CHECK: ori 2, 2, 0
 ; CHECK: lfd 1, [[OFF1]](1)
 ; CHECK: lfd 2, [[OFF2]](1)
 ; CHECK: blr
@@ -118,9 +119,10 @@ entry:
   ret ppc_fp128 %0
 }
 
-; CHECK: @convert_to
+; CHECK: convert_to2:
 ; CHECK: std 3, [[OFF1:.*]](1)
-; CHECK: std 4, [[OFF2:.*]](1)
+; CHECK: std 5, [[OFF2:.*]](1)
+; CHECK: ori 2, 2, 0
 ; CHECK: lfd 1, [[OFF1]](1)
 ; CHECK: lfd 2, [[OFF2]](1)
 ; CHECK: blr
diff --git a/test/CodeGen/PowerPC/ppcf128sf.ll b/test/CodeGen/PowerPC/ppcf128sf.ll
new file mode 100644
index 000000000000..2eea6d89be6a
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppcf128sf.ll
@@ -0,0 +1,179 @@
+; RUN: llc  -mtriple=powerpc-unknown-linux-gnu -O0 < %s | FileCheck %s
+
+@ld = common global ppc_fp128 0xM00000000000000000000000000000000, align 16
+@ld2 = common global ppc_fp128 0xM00000000000000000000000000000000, align 16
+@d = common global double 0.000000e+00, align 8
+@f = common global float 0.000000e+00, align 4
+@i = common global i32 0, align 4
+@ui = common global i32 0, align 4
+@var = common global i8 0, align 1
+
+define void @foo() #0 {
+entry:
+  %c = alloca ppc_fp128, align 16
+  %0 = load ppc_fp128, ppc_fp128* @ld, align 16
+  %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
+  %add = fadd ppc_fp128 %0, %1
+  store ppc_fp128 %add, ppc_fp128* %c, align 16
+  %2 = load ppc_fp128, ppc_fp128* @ld, align 16
+  %3 = load ppc_fp128, ppc_fp128* @ld2, align 16
+  %sub = fsub ppc_fp128 %2, %3
+  store ppc_fp128 %sub, ppc_fp128* %c, align 16
+  %4 = load ppc_fp128, ppc_fp128* @ld, align 16
+  %5 = load ppc_fp128, ppc_fp128* @ld2, align 16
+  %mul = fmul ppc_fp128 %4, %5
+  store ppc_fp128 %mul, ppc_fp128* %c, align 16
+  %6 = load ppc_fp128, ppc_fp128* @ld, align 16
+  %7 = load ppc_fp128, ppc_fp128* @ld2, align 16
+  %div = fdiv ppc_fp128 %6, %7
+  store ppc_fp128 %div, ppc_fp128* %c, align 16
+  ret void
+
+  ; CHECK-LABEL:    __gcc_qadd
+  ; CHECK-LABEL:    __gcc_qsub
+  ; CHECK-LABEL:    __gcc_qmul
+  ; CHECK-LABEL:    __gcc_qdiv
+}
+
+define void @foo1() #0 {
+entry:
+  %0 = load double, double* @d, align 8
+  %conv = fpext double %0 to ppc_fp128
+  store ppc_fp128 %conv, ppc_fp128* @ld, align 16
+  ret void
+
+  ; CHECK-LABEL:    __gcc_dtoq
+}
+
+define void @foo2() #0 {
+entry:
+  %0 = load ppc_fp128, ppc_fp128* @ld, align 16
+  %conv = fptrunc ppc_fp128 %0 to double
+  store double %conv, double* @d, align 8
+  ret void
+
+  ; CHECK-LABEL:    __gcc_qtod
+}
+
+define void @foo3() #0 {
+entry:
+  %0 = load ppc_fp128, ppc_fp128* @ld, align 16
+  %conv = fptrunc ppc_fp128 %0 to float
+  store float %conv, float* @f, align 4
+  ret void
+
+  ; CHECK-LABEL:    __gcc_qtos
+}
+
+define void @foo4() #0 {
+entry:
+  %0 = load i32, i32* @i, align 4
+  %conv = sitofp i32 %0 to ppc_fp128
+  store ppc_fp128 %conv, ppc_fp128* @ld, align 16
+  ret void
+
+  ; CHECK-LABEL:    __gcc_itoq
+}
+
+define void @foo5() #0 {
+entry:
+  %0 = load i32, i32* @ui, align 4
+  %conv = uitofp i32 %0 to ppc_fp128
+  store ppc_fp128 %conv, ppc_fp128* @ld, align 16
+  ret void
+
+  ; CHECK-LABEL:    __gcc_utoq
+}
+
+define void @foo6() #0 {
+entry:
+  %0 = load ppc_fp128, ppc_fp128* @ld, align 16
+  %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
+  %cmp = fcmp oeq ppc_fp128 %0, %1
+  %conv = zext i1 %cmp to i32
+  %conv1 = trunc i32 %conv to i8
+  store i8 %conv1, i8* @var, align 1
+  ret void
+
+  ; CHECK-LABEL:    __gcc_qeq
+}
+
+define void @foo7() #0 {
+entry:
+  %0 = load ppc_fp128, ppc_fp128* @ld, align 16
+  %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
+  %cmp = fcmp une ppc_fp128 %0, %1
+  %conv = zext i1 %cmp to i32
+  %conv1 = trunc i32 %conv to i8
+  store i8 %conv1, i8* @var, align 1
+  ret void
+
+  ; CHECK-LABEL:    __gcc_qne
+}
+
+define void @foo8() #0 {
+entry:
+  %0 = load ppc_fp128, ppc_fp128* @ld, align 16
+  %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
+  %cmp = fcmp ogt ppc_fp128 %0, %1
+  %conv = zext i1 %cmp to i32
+  %conv1 = trunc i32 %conv to i8
+  store i8 %conv1, i8* @var, align 1
+  ret void
+
+  ; CHECK-LABEL:    __gcc_qgt
+}
+
+define void @foo9() #0 {
+entry:
+  %0 = load ppc_fp128, ppc_fp128* @ld, align 16
+  %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
+  %cmp = fcmp olt ppc_fp128 %0, %1
+  %conv = zext i1 %cmp to i32
+  %conv1 = trunc i32 %conv to i8
+  store i8 %conv1, i8* @var, align 1
+  ret void
+
+  ; CHECK-LABEL:    __gcc_qlt
+}
+
+define void @foo10() #0 {
+entry:
+  %0 = load ppc_fp128, ppc_fp128* @ld, align 16
+  %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
+  %cmp = fcmp ole ppc_fp128 %0, %1
+  %conv = zext i1 %cmp to i32
+  %conv1 = trunc i32 %conv to i8
+  store i8 %conv1, i8* @var, align 1
+  ret void
+
+  ; CHECK-LABEL:    __gcc_qle
+}
+
+define void @foo11() #0 {
+entry:
+  %0 = load ppc_fp128, ppc_fp128* @ld, align 16
+  %1 = load ppc_fp128, ppc_fp128* @ld, align 16
+  %cmp = fcmp une ppc_fp128 %0, %1
+  %conv = zext i1 %cmp to i32
+  %conv1 = trunc i32 %conv to i8
+  store i8 %conv1, i8* @var, align 1
+  ret void
+
+  ; CHECK-LABEL:    __gcc_qunord
+}
+
+define void @foo12() #0 {
+entry:
+  %0 = load ppc_fp128, ppc_fp128* @ld, align 16
+  %1 = load ppc_fp128, ppc_fp128* @ld2, align 16
+  %cmp = fcmp oge ppc_fp128 %0, %1
+  %conv = zext i1 %cmp to i32
+  %conv1 = trunc i32 %conv to i8
+  store i8 %conv1, i8* @var, align 1
+  ret void
+
+  ; CHECK-LABEL:    __gcc_qge
+}
+
+attributes #0 = { "use-soft-float"="true" }
diff --git a/test/CodeGen/PowerPC/ppcsoftops.ll b/test/CodeGen/PowerPC/ppcsoftops.ll
index 56c057613bdc..70ee8a42baa9 100644
--- a/test/CodeGen/PowerPC/ppcsoftops.ll
+++ b/test/CodeGen/PowerPC/ppcsoftops.ll
@@ -1,4 +1,6 @@
 ; RUN: llc  -mtriple=powerpc-unknown-linux-gnu -O0 < %s | FileCheck %s
+
+; Testing operations in soft-float mode
 define double @foo() #0 {
 entry:
   %a = alloca double, align 8
diff --git a/test/CodeGen/PowerPC/pr17168.ll b/test/CodeGen/PowerPC/pr17168.ll
index b1bac59c9ce1..852ebfec576c 100644
--- a/test/CodeGen/PowerPC/pr17168.ll
+++ b/test/CodeGen/PowerPC/pr17168.ll
@@ -54,11 +54,10 @@ attributes #1 = { nounwind readnone }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!438, !464}
 
-!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 190311)", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !298, imports: !2)
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 190311)", isOptimized: true, emissionKind: FullDebug, file: !1, enums: !2, retainedTypes: !2, globals: !298, imports: !2)
 !1 = !DIFile(filename: "bt.c", directory: "/home/hfinkel/src/NPB2.3-omp-C/BT")
 !2 = !{}
-!3 = !{!4, !82, !102, !114, !132, !145, !154, !155, !162, !183, !200, !201, !207, !208, !215, !221, !230, !238, !246, !255, !260, !261, !268, !274, !279, !280, !287, !293}
-!4 = distinct !DISubprogram(name: "main", line: 74, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 74, file: !1, scope: !5, type: !6, variables: !12)
+!4 = distinct !DISubprogram(name: "main", line: 74, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 74, file: !1, scope: !5, type: !6, variables: !12)
 !5 = !DIFile(filename: "bt.c", directory: "/home/hfinkel/src/NPB2.3-omp-C/BT")
 !6 = !DISubroutineType(types: !7)
 !7 = !{!8, !8, !9}
@@ -136,7 +135,7 @@ attributes #1 = { nounwind readnone }
 !79 = !DICompositeType(tag: DW_TAG_array_type, size: 160, align: 8, baseType: !11, elements: !80)
 !80 = !{!81}
 !81 = !DISubrange(count: 20)
-!82 = distinct !DISubprogram(name: "verify", line: 2388, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2388, file: !1, scope: !5, type: !83, variables: !86)
+!82 = distinct !DISubprogram(name: "verify", line: 2388, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 2388, file: !1, scope: !5, type: !83, variables: !86)
 !83 = !DISubroutineType(types: !84)
 !84 = !{null, !8, !10, !85}
 !85 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !24)
@@ -156,7 +155,7 @@ attributes #1 = { nounwind readnone }
 !99 = !DILocalVariable(name: "xcr", line: 2398, scope: !82, file: !5, type: !91)
 !100 = !DILocalVariable(name: "dtref", line: 2398, scope: !82, file: !5, type: !20)
 !101 = !DILocalVariable(name: "m", line: 2399, scope: !82, file: !5, type: !8)
-!102 = distinct !DISubprogram(name: "rhs_norm", line: 266, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 266, file: !1, scope: !5, type: !103, variables: !106)
+!102 = distinct !DISubprogram(name: "rhs_norm", line: 266, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 266, file: !1, scope: !5, type: !103, variables: !106)
 !103 = !DISubroutineType(types: !104)
 !104 = !{null, !105}
 !105 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !20)
@@ -168,7 +167,7 @@ attributes #1 = { nounwind readnone }
 !111 = !DILocalVariable(name: "d", line: 271, scope: !102, file: !5, type: !8)
 !112 = !DILocalVariable(name: "m", line: 271, scope: !102, file: !5, type: !8)
 !113 = !DILocalVariable(name: "add", line: 272, scope: !102, file: !5, type: !20)
-!114 = distinct !DISubprogram(name: "compute_rhs", line: 1767, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1767, file: !1, scope: !5, type: !115, variables: !117)
+!114 = distinct !DISubprogram(name: "compute_rhs", line: 1767, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 1767, file: !1, scope: !5, type: !115, variables: !117)
 !115 = !DISubroutineType(types: !116)
 !116 = !{null}
 !117 = !{!118, !119, !120, !121, !122, !123, !124, !125, !126, !127, !128, !129, !130, !131}
@@ -186,7 +185,7 @@ attributes #1 = { nounwind readnone }
 !129 = !DILocalVariable(name: "wijk", line: 1770, scope: !114, file: !5, type: !20)
 !130 = !DILocalVariable(name: "wp1", line: 1770, scope: !114, file: !5, type: !20)
 !131 = !DILocalVariable(name: "wm1", line: 1770, scope: !114, file: !5, type: !20)
-!132 = distinct !DISubprogram(name: "error_norm", line: 225, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 225, file: !1, scope: !5, type: !103, variables: !133)
+!132 = distinct !DISubprogram(name: "error_norm", line: 225, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 225, file: !1, scope: !5, type: !103, variables: !133)
 !133 = !{!134, !135, !136, !137, !138, !139, !140, !141, !142, !143, !144}
 !134 = !DILocalVariable(name: "rms", line: 225, arg: 1, scope: !132, file: !5, type: !105)
 !135 = !DILocalVariable(name: "i", line: 232, scope: !132, file: !5, type: !8)
@@ -199,7 +198,7 @@ attributes #1 = { nounwind readnone }
 !142 = !DILocalVariable(name: "zeta", line: 233, scope: !132, file: !5, type: !20)
 !143 = !DILocalVariable(name: "u_exact", line: 233, scope: !132, file: !5, type: !91)
 !144 = !DILocalVariable(name: "add", line: 233, scope: !132, file: !5, type: !20)
-!145 = distinct !DISubprogram(name: "exact_solution", line: 643, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 644, file: !1, scope: !5, type: !146, variables: !148)
+!145 = distinct !DISubprogram(name: "exact_solution", line: 643, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 644, file: !1, scope: !5, type: !146, variables: !148)
 !146 = !DISubroutineType(types: !147)
 !147 = !{null, !20, !20, !20, !105}
 !148 = !{!149, !150, !151, !152, !153}
@@ -208,15 +207,15 @@ attributes #1 = { nounwind readnone }
 !151 = !DILocalVariable(name: "zeta", line: 643, arg: 3, scope: !145, file: !5, type: !20)
 !152 = !DILocalVariable(name: "dtemp", line: 644, arg: 4, scope: !145, file: !5, type: !105)
 !153 = !DILocalVariable(name: "m", line: 653, scope: !145, file: !5, type: !8)
-!154 = distinct !DISubprogram(name: "set_constants", line: 2191, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2191, file: !1, scope: !5, type: !115, variables: !2)
-!155 = distinct !DISubprogram(name: "lhsinit", line: 855, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 855, file: !1, scope: !5, type: !115, variables: !156)
+!154 = distinct !DISubprogram(name: "set_constants", line: 2191, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 2191, file: !1, scope: !5, type: !115, variables: !2)
+!155 = distinct !DISubprogram(name: "lhsinit", line: 855, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 855, file: !1, scope: !5, type: !115, variables: !156)
 !156 = !{!157, !158, !159, !160, !161}
 !157 = !DILocalVariable(name: "i", line: 857, scope: !155, file: !5, type: !8)
 !158 = !DILocalVariable(name: "j", line: 857, scope: !155, file: !5, type: !8)
 !159 = !DILocalVariable(name: "k", line: 857, scope: !155, file: !5, type: !8)
 !160 = !DILocalVariable(name: "m", line: 857, scope: !155, file: !5, type: !8)
 !161 = !DILocalVariable(name: "n", line: 857, scope: !155, file: !5, type: !8)
-!162 = distinct !DISubprogram(name: "initialize", line: 669, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 669, file: !1, scope: !5, type: !115, variables: !163)
+!162 = distinct !DISubprogram(name: "initialize", line: 669, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 669, file: !1, scope: !5, type: !115, variables: !163)
 !163 = !{!164, !165, !166, !167, !168, !169, !170, !171, !172, !173, !174, !179, !180, !181, !182}
 !164 = !DILocalVariable(name: "i", line: 679, scope: !162, file: !5, type: !8)
 !165 = !DILocalVariable(name: "j", line: 679, scope: !162, file: !5, type: !8)
@@ -237,7 +236,7 @@ attributes #1 = { nounwind readnone }
 !180 = !DILocalVariable(name: "Peta", line: 680, scope: !162, file: !5, type: !20)
 !181 = !DILocalVariable(name: "Pzeta", line: 680, scope: !162, file: !5, type: !20)
 !182 = !DILocalVariable(name: "temp", line: 680, scope: !162, file: !5, type: !91)
-!183 = distinct !DISubprogram(name: "exact_rhs", line: 301, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 301, file: !1, scope: !5, type: !115, variables: !184)
+!183 = distinct !DISubprogram(name: "exact_rhs", line: 301, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 301, file: !1, scope: !5, type: !115, variables: !184)
 !184 = !{!185, !186, !187, !188, !189, !190, !191, !192, !193, !194, !195, !196, !197, !198, !199}
 !185 = !DILocalVariable(name: "dtemp", line: 310, scope: !183, file: !5, type: !91)
 !186 = !DILocalVariable(name: "xi", line: 310, scope: !183, file: !5, type: !20)
@@ -254,28 +253,28 @@ attributes #1 = { nounwind readnone }
 !197 = !DILocalVariable(name: "jm1", line: 311, scope: !183, file: !5, type: !8)
 !198 = !DILocalVariable(name: "km1", line: 311, scope: !183, file: !5, type: !8)
 !199 = !DILocalVariable(name: "kp1", line: 311, scope: !183, file: !5, type: !8)
-!200 = distinct !DISubprogram(name: "adi", line: 210, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 210, file: !1, scope: !5, type: !115, variables: !2)
-!201 = distinct !DISubprogram(name: "add", line: 187, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 187, file: !1, scope: !5, type: !115, variables: !202)
+!200 = distinct !DISubprogram(name: "adi", line: 210, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 210, file: !1, scope: !5, type: !115, variables: !2)
+!201 = distinct !DISubprogram(name: "add", line: 187, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 187, file: !1, scope: !5, type: !115, variables: !202)
 !202 = !{!203, !204, !205, !206}
 !203 = !DILocalVariable(name: "i", line: 193, scope: !201, file: !5, type: !8)
 !204 = !DILocalVariable(name: "j", line: 193, scope: !201, file: !5, type: !8)
 !205 = !DILocalVariable(name: "k", line: 193, scope: !201, file: !5, type: !8)
 !206 = !DILocalVariable(name: "m", line: 193, scope: !201, file: !5, type: !8)
-!207 = distinct !DISubprogram(name: "z_solve", line: 3457, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3457, file: !1, scope: !5, type: !115, variables: !2)
-!208 = distinct !DISubprogram(name: "z_backsubstitute", line: 3480, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3480, file: !1, scope: !5, type: !115, variables: !209)
+!207 = distinct !DISubprogram(name: "z_solve", line: 3457, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 3457, file: !1, scope: !5, type: !115, variables: !2)
+!208 = distinct !DISubprogram(name: "z_backsubstitute", line: 3480, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 3480, file: !1, scope: !5, type: !115, variables: !209)
 !209 = !{!210, !211, !212, !213, !214}
 !210 = !DILocalVariable(name: "i", line: 3492, scope: !208, file: !5, type: !8)
 !211 = !DILocalVariable(name: "j", line: 3492, scope: !208, file: !5, type: !8)
 !212 = !DILocalVariable(name: "k", line: 3492, scope: !208, file: !5, type: !8)
 !213 = !DILocalVariable(name: "m", line: 3492, scope: !208, file: !5, type: !8)
 !214 = !DILocalVariable(name: "n", line: 3492, scope: !208, file: !5, type: !8)
-!215 = distinct !DISubprogram(name: "z_solve_cell", line: 3512, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3512, file: !1, scope: !5, type: !115, variables: !216)
+!215 = distinct !DISubprogram(name: "z_solve_cell", line: 3512, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 3512, file: !1, scope: !5, type: !115, variables: !216)
 !216 = !{!217, !218, !219, !220}
 !217 = !DILocalVariable(name: "i", line: 3527, scope: !215, file: !5, type: !8)
 !218 = !DILocalVariable(name: "j", line: 3527, scope: !215, file: !5, type: !8)
 !219 = !DILocalVariable(name: "k", line: 3527, scope: !215, file: !5, type: !8)
 !220 = !DILocalVariable(name: "ksize", line: 3527, scope: !215, file: !5, type: !8)
-!221 = distinct !DISubprogram(name: "binvrhs", line: 3154, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3154, file: !1, scope: !5, type: !222, variables: !225)
+!221 = distinct !DISubprogram(name: "binvrhs", line: 3154, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 3154, file: !1, scope: !5, type: !222, variables: !225)
 !222 = !DISubroutineType(types: !223)
 !223 = !{null, !224, !105}
 !224 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !91)
@@ -284,7 +283,7 @@ attributes #1 = { nounwind readnone }
 !227 = !DILocalVariable(name: "r", line: 3154, arg: 2, scope: !221, file: !5, type: !105)
 !228 = !DILocalVariable(name: "pivot", line: 3159, scope: !221, file: !5, type: !20)
 !229 = !DILocalVariable(name: "coeff", line: 3159, scope: !221, file: !5, type: !20)
-!230 = distinct !DISubprogram(name: "matmul_sub", line: 2841, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2842, file: !1, scope: !5, type: !231, variables: !233)
+!230 = distinct !DISubprogram(name: "matmul_sub", line: 2841, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 2842, file: !1, scope: !5, type: !231, variables: !233)
 !231 = !DISubroutineType(types: !232)
 !232 = !{null, !224, !224, !224}
 !233 = !{!234, !235, !236, !237}
@@ -292,7 +291,7 @@ attributes #1 = { nounwind readnone }
 !235 = !DILocalVariable(name: "bblock", line: 2841, arg: 2, scope: !230, file: !5, type: !224)
 !236 = !DILocalVariable(name: "cblock", line: 2842, arg: 3, scope: !230, file: !5, type: !224)
 !237 = !DILocalVariable(name: "j", line: 2851, scope: !230, file: !5, type: !8)
-!238 = distinct !DISubprogram(name: "matvec_sub", line: 2814, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2814, file: !1, scope: !5, type: !239, variables: !241)
+!238 = distinct !DISubprogram(name: "matvec_sub", line: 2814, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 2814, file: !1, scope: !5, type: !239, variables: !241)
 !239 = !DISubroutineType(types: !240)
 !240 = !{null, !224, !105, !105}
 !241 = !{!242, !243, !244, !245}
@@ -300,7 +299,7 @@ attributes #1 = { nounwind readnone }
 !243 = !DILocalVariable(name: "avec", line: 2814, arg: 2, scope: !238, file: !5, type: !105)
 !244 = !DILocalVariable(name: "bvec", line: 2814, arg: 3, scope: !238, file: !5, type: !105)
 !245 = !DILocalVariable(name: "i", line: 2823, scope: !238, file: !5, type: !8)
-!246 = distinct !DISubprogram(name: "binvcrhs", line: 2885, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2885, file: !1, scope: !5, type: !247, variables: !249)
+!246 = distinct !DISubprogram(name: "binvcrhs", line: 2885, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 2885, file: !1, scope: !5, type: !247, variables: !249)
 !247 = !DISubroutineType(types: !248)
 !248 = !{null, !224, !224, !105}
 !249 = !{!250, !251, !252, !253, !254}
@@ -309,45 +308,45 @@ attributes #1 = { nounwind readnone }
 !252 = !DILocalVariable(name: "r", line: 2885, arg: 3, scope: !246, file: !5, type: !105)
 !253 = !DILocalVariable(name: "pivot", line: 2890, scope: !246, file: !5, type: !20)
 !254 = !DILocalVariable(name: "coeff", line: 2890, scope: !246, file: !5, type: !20)
-!255 = distinct !DISubprogram(name: "lhsz", line: 1475, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1475, file: !1, scope: !5, type: !115, variables: !256)
+!255 = distinct !DISubprogram(name: "lhsz", line: 1475, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 1475, file: !1, scope: !5, type: !115, variables: !256)
 !256 = !{!257, !258, !259}
 !257 = !DILocalVariable(name: "i", line: 1484, scope: !255, file: !5, type: !8)
 !258 = !DILocalVariable(name: "j", line: 1484, scope: !255, file: !5, type: !8)
 !259 = !DILocalVariable(name: "k", line: 1484, scope: !255, file: !5, type: !8)
-!260 = distinct !DISubprogram(name: "y_solve", line: 3299, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3299, file: !1, scope: !5, type: !115, variables: !2)
-!261 = distinct !DISubprogram(name: "y_backsubstitute", line: 3323, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3323, file: !1, scope: !5, type: !115, variables: !262)
+!260 = distinct !DISubprogram(name: "y_solve", line: 3299, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 3299, file: !1, scope: !5, type: !115, variables: !2)
+!261 = distinct !DISubprogram(name: "y_backsubstitute", line: 3323, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 3323, file: !1, scope: !5, type: !115, variables: !262)
 !262 = !{!263, !264, !265, !266, !267}
 !263 = !DILocalVariable(name: "i", line: 3335, scope: !261, file: !5, type: !8)
 !264 = !DILocalVariable(name: "j", line: 3335, scope: !261, file: !5, type: !8)
 !265 = !DILocalVariable(name: "k", line: 3335, scope: !261, file: !5, type: !8)
 !266 = !DILocalVariable(name: "m", line: 3335, scope: !261, file: !5, type: !8)
 !267 = !DILocalVariable(name: "n", line: 3335, scope: !261, file: !5, type: !8)
-!268 = distinct !DISubprogram(name: "y_solve_cell", line: 3355, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3355, file: !1, scope: !5, type: !115, variables: !269)
+!268 = distinct !DISubprogram(name: "y_solve_cell", line: 3355, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 3355, file: !1, scope: !5, type: !115, variables: !269)
 !269 = !{!270, !271, !272, !273}
 !270 = !DILocalVariable(name: "i", line: 3370, scope: !268, file: !5, type: !8)
 !271 = !DILocalVariable(name: "j", line: 3370, scope: !268, file: !5, type: !8)
 !272 = !DILocalVariable(name: "k", line: 3370, scope: !268, file: !5, type: !8)
 !273 = !DILocalVariable(name: "jsize", line: 3370, scope: !268, file: !5, type: !8)
-!274 = distinct !DISubprogram(name: "lhsy", line: 1181, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1181, file: !1, scope: !5, type: !115, variables: !275)
+!274 = distinct !DISubprogram(name: "lhsy", line: 1181, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 1181, file: !1, scope: !5, type: !115, variables: !275)
 !275 = !{!276, !277, !278}
 !276 = !DILocalVariable(name: "i", line: 1190, scope: !274, file: !5, type: !8)
 !277 = !DILocalVariable(name: "j", line: 1190, scope: !274, file: !5, type: !8)
 !278 = !DILocalVariable(name: "k", line: 1190, scope: !274, file: !5, type: !8)
-!279 = distinct !DISubprogram(name: "x_solve", line: 2658, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2658, file: !1, scope: !5, type: !115, variables: !2)
-!280 = distinct !DISubprogram(name: "x_backsubstitute", line: 2684, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2684, file: !1, scope: !5, type: !115, variables: !281)
+!279 = distinct !DISubprogram(name: "x_solve", line: 2658, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 2658, file: !1, scope: !5, type: !115, variables: !2)
+!280 = distinct !DISubprogram(name: "x_backsubstitute", line: 2684, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 2684, file: !1, scope: !5, type: !115, variables: !281)
 !281 = !{!282, !283, !284, !285, !286}
 !282 = !DILocalVariable(name: "i", line: 2696, scope: !280, file: !5, type: !8)
 !283 = !DILocalVariable(name: "j", line: 2696, scope: !280, file: !5, type: !8)
 !284 = !DILocalVariable(name: "k", line: 2696, scope: !280, file: !5, type: !8)
 !285 = !DILocalVariable(name: "m", line: 2696, scope: !280, file: !5, type: !8)
 !286 = !DILocalVariable(name: "n", line: 2696, scope: !280, file: !5, type: !8)
-!287 = distinct !DISubprogram(name: "x_solve_cell", line: 2716, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 2716, file: !1, scope: !5, type: !115, variables: !288)
+!287 = distinct !DISubprogram(name: "x_solve_cell", line: 2716, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 2716, file: !1, scope: !5, type: !115, variables: !288)
 !288 = !{!289, !290, !291, !292}
 !289 = !DILocalVariable(name: "i", line: 2728, scope: !287, file: !5, type: !8)
 !290 = !DILocalVariable(name: "j", line: 2728, scope: !287, file: !5, type: !8)
 !291 = !DILocalVariable(name: "k", line: 2728, scope: !287, file: !5, type: !8)
 !292 = !DILocalVariable(name: "isize", line: 2728, scope: !287, file: !5, type: !8)
-!293 = distinct !DISubprogram(name: "lhsx", line: 898, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 898, file: !1, scope: !5, type: !115, variables: !294)
+!293 = distinct !DISubprogram(name: "lhsx", line: 898, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 898, file: !1, scope: !5, type: !115, variables: !294)
 !294 = !{!295, !296, !297}
 !295 = !DILocalVariable(name: "i", line: 907, scope: !293, file: !5, type: !8)
 !296 = !DILocalVariable(name: "j", line: 907, scope: !293, file: !5, type: !8)
diff --git a/test/CodeGen/PowerPC/pr24546.ll b/test/CodeGen/PowerPC/pr24546.ll
index 06f6bc93da99..2519bb623bc4 100644
--- a/test/CodeGen/PowerPC/pr24546.ll
+++ b/test/CodeGen/PowerPC/pr24546.ll
@@ -56,13 +56,12 @@ attributes #3 = { nounwind }
 !llvm.module.flags = !{!29, !30}
 !llvm.ident = !{!31}
 
-!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.8.0 (git://github.com/llvm-mirror/clang.git e0848b6353721eb1b278a5bbea257bbf6316251e) (git://github.com/llvm-mirror/llvm.git 8724a428dfd5e78d7865bb01783708e83f9ed128)", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !3, subprograms: !5, globals: !23)
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.8.0 (git://github.com/llvm-mirror/clang.git e0848b6353721eb1b278a5bbea257bbf6316251e) (git://github.com/llvm-mirror/llvm.git 8724a428dfd5e78d7865bb01783708e83f9ed128)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !3, globals: !23)
 !1 = !DIFile(filename: "testcase.i", directory: "/tmp/glibc.build")
 !2 = !{}
 !3 = !{!4}
 !4 = !DIBasicType(name: "double", size: 64, align: 64, encoding: DW_ATE_float)
-!5 = !{!6, !18}
-!6 = distinct !DISubprogram(name: "_php_math_round", scope: !1, file: !1, line: 15, type: !7, isLocal: false, isDefinition: true, scopeLine: 16, flags: DIFlagPrototyped, isOptimized: true, variables: !10)
+!6 = distinct !DISubprogram(name: "_php_math_round", scope: !1, file: !1, line: 15, type: !7, isLocal: false, isDefinition: true, scopeLine: 16, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !10)
 !7 = !DISubroutineType(types: !8)
 !8 = !{!4, !4, !9, !9}
 !9 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
@@ -74,7 +73,7 @@ attributes #3 = { nounwind }
 !15 = !DILocalVariable(name: "f2", scope: !6, file: !1, line: 17, type: !4)
 !16 = !DILocalVariable(name: "tmp_value", scope: !6, file: !1, line: 18, type: !4)
 !17 = !DILocalVariable(name: "precision_places", scope: !6, file: !1, line: 19, type: !9)
-!18 = distinct !DISubprogram(name: "php_intpow10", scope: !1, file: !1, line: 1, type: !19, isLocal: true, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, variables: !21)
+!18 = distinct !DISubprogram(name: "php_intpow10", scope: !1, file: !1, line: 1, type: !19, isLocal: true, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !21)
 !19 = !DISubroutineType(types: !20)
 !20 = !{!4, !9}
 !21 = !{!22}
diff --git a/test/CodeGen/PowerPC/pr25802.ll b/test/CodeGen/PowerPC/pr25802.ll
deleted file mode 100644
index 0631850be5fa..000000000000
--- a/test/CodeGen/PowerPC/pr25802.ll
+++ /dev/null
@@ -1,52 +0,0 @@
-; RUN: llc < %s | FileCheck %s
-; CHECK: .long   .Ltmp6-.Ltmp12          #   Call between .Ltmp12 and .Ltmp6
-
-; We used to crash in filetype=obj when computing a negative value.
-; RUN: llc -filetype=obj < %s
-
-target triple = "powerpc--netbsd"
-@_ZTI1I = external constant { i8*, i8* }
-define void @f(i8 %foo, i32 %bar) personality i8* bitcast (void ()* @g to i8*) {
-  invoke void @g()
-          to label %try.cont unwind label %lpad
-lpad:                                             ; preds = %0
-  %tmp = landingpad { i8*, i32 }
-          catch i8* bitcast ({ i8*, i8* }* @_ZTI1I to i8*)
-  br i1 undef, label %catch10, label %catch
-catch10:                                          ; preds = %lpad
-  %tmp8 = load i32, i32* undef, align 4
-  %conv.i.i = zext i8 %foo to i32
-  %cond.i.i = select i1 undef, i32 %conv.i.i, i32 %tmp8
-  invoke void @_Z24__put_character_sequenceIccEvR1AIT_T0_Ej(i32 %cond.i.i)
-          to label %invoke.cont20 unwind label %lpad15
-invoke.cont20:                                    ; preds = %catch10
-  ret void
-try.cont:                                         ; preds = %0
-  ret void
-catch:                                            ; preds = %lpad
-  %tmp14 = load i32, i32* undef, align 4
-  %conv.i.i34 = zext i8 %foo to i32
-  %cond.i.i35 = select i1 undef, i32 %conv.i.i34, i32 %tmp14
-  invoke void @_Z24__put_character_sequenceIccEvR1AIT_T0_Ej(i32 %cond.i.i35)
-          to label %invoke.cont8 unwind label %lpad3
-invoke.cont8:                                     ; preds = %call2.i.i.noexc36
-  ret void
-lpad3:                                            ; preds = %call2.i.i.noexc36, %catch
-  %tmp16 = landingpad { i8*, i32 }
-          cleanup
-  invoke void @g()
-          to label %eh.resume unwind label %terminate.lpad
-lpad15:                                           ; preds = %catch10
-  %tmp19 = landingpad { i8*, i32 }
-          cleanup
-  invoke void @g()
-          to label %eh.resume unwind label %terminate.lpad
-eh.resume:                                        ; preds = %lpad15, %lpad3
-  ret void
-terminate.lpad:                                   ; preds = %lpad15, %lpad3
-  %tmp22 = landingpad { i8*, i32 }
-          catch i8* null
-  ret void
-}
-declare void @g()
-declare void @_Z24__put_character_sequenceIccEvR1AIT_T0_Ej(i32)
diff --git a/test/CodeGen/PowerPC/pr26180.ll b/test/CodeGen/PowerPC/pr26180.ll
new file mode 100644
index 000000000000..e4cbcb8725d5
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr26180.ll
@@ -0,0 +1,14 @@
+; RUN: llc -mcpu=generic -mtriple=powerpc64le-unknown-unknown -O0 < %s | FileCheck %s --check-prefix=GENERIC
+; RUN: llc -mcpu=ppc -mtriple=powerpc64le-unknown-unknown -O0 < %s | FileCheck %s
+
+define i32 @bad(double %x) {
+  %1 = fptoui double %x to i32
+  ret i32 %1
+}
+
+; CHECK: fctidz 1, 1
+; CHECK: stfd 1, [[OFF:.*]](1)
+; CHECK: lwz {{[0-9]*}}, [[OFF]](1)
+; GENERIC: fctiwuz 1, 1
+; GENERIC: stfd 1, [[OFF:.*]](1)
+; GENERIC: lwz {{[0-9]*}}, [[OFF]](1)
diff --git a/test/CodeGen/PowerPC/pr26378.ll b/test/CodeGen/PowerPC/pr26378.ll
new file mode 100644
index 000000000000..e5e20553f52b
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr26378.ll
@@ -0,0 +1,6 @@
+; RUN: llc -compile-twice -filetype obj \
+; RUN:   -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 < %s
+@foo = common global i32 0, align 4
+define i8* @blah() #0 {
+  ret i8* bitcast (i32* @foo to i8*)
+}  
diff --git a/test/CodeGen/PowerPC/pr26617.ll b/test/CodeGen/PowerPC/pr26617.ll
new file mode 100644
index 000000000000..474d7b94aaf8
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr26617.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc-unknown-unknown < %s | FileCheck %s
+define i32 @test(<4 x i32> %v, i32 %elem) #0 {
+entry:
+  %vecext = extractelement <4 x i32> %v, i32 %elem
+  ret i32 %vecext
+}
+; CHECK: stxvw4x 34,
+; CHECK: lwzx 3,
+
+define float @test2(i32 signext %a) {
+entry:
+  %conv = bitcast i32 %a to float
+  ret float %conv
+}
+; CHECK-NOT: mtvsr
diff --git a/test/CodeGen/PowerPC/pr26690.ll b/test/CodeGen/PowerPC/pr26690.ll
index 3e7662409d51..e1c3c496ed40 100644
--- a/test/CodeGen/PowerPC/pr26690.ll
+++ b/test/CodeGen/PowerPC/pr26690.ll
@@ -35,9 +35,9 @@ while.body.lr.ph:                                 ; preds = %while.cond.preheade
 while.body:                                       ; preds = %while.body.backedge, %while.body.lr.ph
   switch i32 %.pre, label %while.body.backedge [
     i32 0, label %sw.bb1
-    i32 8, label %sw.bb1
-    i32 6, label %sw.bb1
-    i32 24, label %while.cond.backedge
+    i32 80, label %sw.bb1
+    i32 60, label %sw.bb1
+    i32 240, label %while.cond.backedge
   ]
 
 while.body.backedge:                              ; preds = %while.body, %while.cond.backedge
@@ -101,7 +101,7 @@ if.end16:                                         ; preds = %entry, %if.end13, %
   ret i32 2
 }
 
-; CHECK: mfcr {{[0-9]+}}
+; CHECK: mfocrf {{[0-9]+}}
 
 !llvm.ident = !{!0}
 
diff --git a/test/CodeGen/PowerPC/pr27078.ll b/test/CodeGen/PowerPC/pr27078.ll
new file mode 100644
index 000000000000..b1fdbbde6929
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr27078.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=+vsx < %s | FileCheck %s
+
+define <4 x float> @bar(float* %p, float* %q) {
+  %1 = bitcast float* %p to <12 x float>*
+  %2 = bitcast float* %q to <12 x float>*
+  %3 = load <12 x float>, <12 x float>* %1, align 16
+  %4 = load <12 x float>, <12 x float>* %2, align 16
+  %5 = fsub <12 x float> %4, %3
+  %6 = shufflevector <12 x float> %5, <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
+  ret <4 x float>  %6
+
+; CHECK: xxspltw
+; CHECK: vmrghw
+; CHECK: vsldoi
+}
diff --git a/test/CodeGen/PowerPC/pr27350.ll b/test/CodeGen/PowerPC/pr27350.ll
new file mode 100644
index 000000000000..a3f35b2e41a6
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr27350.ll
@@ -0,0 +1,26 @@
+; RUN: llc -mcpu=ppc64le -mtriple=powerpc64le-unknown-linux-gnu < %s
+
+; Function Attrs: argmemonly nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #0
+
+; Function Attrs: nounwind
+define internal fastcc void @foo() unnamed_addr #1 align 2 {
+entry:
+  call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* null, i64 16, i32 8, i1 false)
+  %0 = load <2 x i64>, <2 x i64>* null, align 8
+  %1 = extractelement <2 x i64> %0, i32 1
+  %.fca.1.insert159.i = insertvalue [2 x i64] undef, i64 %1, 1
+  tail call fastcc void @bar([2 x i64] undef, [2 x i64] %.fca.1.insert159.i) #2
+  unreachable
+}
+
+; Function Attrs: nounwind
+declare fastcc void @bar([2 x i64], [2 x i64]) unnamed_addr #1 align 2
+
+attributes #0 = { argmemonly nounwind }
+attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #2 = { nounwind }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.9.0 (trunk) (llvm/trunk 266222)"}
diff --git a/test/CodeGen/PowerPC/pr28130.ll b/test/CodeGen/PowerPC/pr28130.ll
new file mode 100644
index 000000000000..e549c46d9568
--- /dev/null
+++ b/test/CodeGen/PowerPC/pr28130.ll
@@ -0,0 +1,70 @@
+; RUN: llc -O0 < %s | FileCheck %s
+target triple = "powerpc64le-unknown-linux-gnu"
+
+%StructA = type { double, double, double, double, double, double, double, double }
+
+define void @Test(%StructA* %tmp) unnamed_addr #0 align 2 {
+; CHECK-LABEL: Test:
+; CHECK: lxvd2x
+; CHECK-NEXT: xxswapd
+; CHECK: lxvd2x
+; CHECK-NEXT: xxswapd
+; CHECK: lxvd2x
+; CHECK-NEXT: xxswapd
+; CHECK: lxvd2x
+; CHECK-NEXT: xxswapd
+; CHECK: xxswapd [[OUTPUT:[0-9]+]]
+; CHECK-NEXT: stxvd2x [[OUTPUT]]
+bb:
+  %tmp2 = getelementptr inbounds %StructA, %StructA* %tmp, i64 0, i32 0
+  %tmp4 = bitcast %StructA* %tmp to <2 x double>*
+  %tmp5 = getelementptr inbounds %StructA, %StructA* %tmp, i64 0, i32 2
+  %tmp9 = getelementptr inbounds %StructA, %StructA* %tmp, i64 0, i32 4
+  %tmp11 = getelementptr inbounds %StructA, %StructA* %tmp, i64 0, i32 5
+  %tmp13 = getelementptr inbounds %StructA, %StructA* %tmp, i64 0, i32 6
+  %tmp15 = getelementptr inbounds %StructA, %StructA* %tmp, i64 0, i32 7
+  %tmp18 = load double, double* %tmp2, align 16
+  %tmp19 = load double, double* %tmp11, align 8
+  %tmp20 = load double, double* %tmp9, align 16
+  %tmp21 = fsub double 1.210000e+04, %tmp20
+  %tmp22 = fmul double %tmp18, %tmp21
+  %tmp23 = fadd double %tmp20, %tmp22
+  %tmp24 = load double, double* %tmp13, align 16
+  %tmp25 = fsub double 1.000000e+02, %tmp24
+  %tmp26 = fmul double %tmp18, %tmp25
+  %tmp27 = fadd double %tmp24, %tmp26
+  %tmp28 = load double, double* %tmp15, align 8
+  %tmp29 = insertelement <2 x double> undef, double %tmp19, i32 0
+  %tmp30 = insertelement <2 x double> %tmp29, double %tmp28, i32 1
+  %tmp31 = fsub <2 x double> <double 1.100000e+04, double 1.100000e+02>, %tmp30
+  %tmp32 = insertelement <2 x double> undef, double %tmp18, i32 0
+  %tmp33 = insertelement <2 x double> %tmp32, double %tmp18, i32 1
+  %tmp34 = fmul <2 x double> %tmp33, %tmp31
+  %tmp35 = fadd <2 x double> %tmp30, %tmp34
+  %tmp36 = bitcast double* %tmp5 to <2 x double>*
+  %tmp37 = load <2 x double>, <2 x double>* %tmp36, align 16
+  %tmp38 = fsub <2 x double> <double 1.000000e+00, double 1.000000e+04>, %tmp37
+  %tmp39 = fmul <2 x double> %tmp33, %tmp38
+  %tmp40 = fadd <2 x double> %tmp37, %tmp39
+  %tmp41 = fsub <2 x double> <double 1.000000e+00, double 1.000000e+04>, %tmp40
+  %tmp42 = fmul <2 x double> %tmp33, %tmp41
+  %tmp43 = fadd <2 x double> %tmp40, %tmp42
+  %tmp44 = fsub <2 x double> <double 1.200000e+04, double 1.200000e+02>, %tmp35
+  %tmp45 = fmul <2 x double> %tmp33, %tmp44
+  %tmp46 = fadd <2 x double> %tmp35, %tmp45
+  %tmp48 = fsub double 1.440000e+04, %tmp23
+  %tmp49 = fmul double %tmp18, %tmp48
+  %tmp50 = fadd double %tmp23, %tmp49
+  store double %tmp50, double* %tmp9, align 16
+  %tmp51 = fsub double 1.000000e+02, %tmp27
+  %tmp52 = fmul double %tmp18, %tmp51
+  %tmp53 = fadd double %tmp27, %tmp52
+  store double %tmp53, double* %tmp13, align 16
+  %tmp54 = extractelement <2 x double> %tmp46, i32 1
+  store double %tmp54, double* %tmp15, align 8
+  %tmp55 = bitcast double* %tmp5 to <2 x double>*
+  store <2 x double> %tmp43, <2 x double>* %tmp55, align 16
+  ret void
+}
+
+attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr8" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/CodeGen/PowerPC/preincprep-invoke.ll b/test/CodeGen/PowerPC/preincprep-invoke.ll
index 8dbce9a3a08e..6e97468f07fa 100644
--- a/test/CodeGen/PowerPC/preincprep-invoke.ll
+++ b/test/CodeGen/PowerPC/preincprep-invoke.ll
@@ -11,12 +11,12 @@ declare void @_ZN13CStdOutStream5FlushEv()
 
 declare i32 @__gxx_personality_v0(...)
 
-define void @_Z11GetPasswordP13CStdOutStreamb() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+define void @_Z11GetPasswordP13CStdOutStreamb(i1 %cond, i8 %arg1, i8* %arg2) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
 entry:
   br label %for.cond.i.i
 
 for.cond.i.i:                                     ; preds = %for.cond.i.i, %entry
-  br i1 undef, label %_ZN11CStringBaseIcEC2EPKc.exit.critedge, label %for.cond.i.i
+  br i1 %cond, label %_ZN11CStringBaseIcEC2EPKc.exit.critedge, label %for.cond.i.i
 
 _ZN11CStringBaseIcEC2EPKc.exit.critedge:          ; preds = %for.cond.i.i
   invoke void @_ZN13CStdOutStreamlsEPKc()
@@ -37,11 +37,13 @@ for.cond.i.i30:                                   ; preds = %for.cond.i.i30, %in
   %indvars.iv.i.i26 = phi i64 [ %indvars.iv.next.i.i29, %for.cond.i.i30 ], [ 0, %invoke.cont4 ]
   %arrayidx.i.i27 = getelementptr inbounds i8, i8* %call7, i64 %indvars.iv.i.i26
   %0 = load i8, i8* %arrayidx.i.i27, align 1
+  %1 = add i8 %0, %arg1
+  store i8 %1, i8* %arg2, align 1
   %indvars.iv.next.i.i29 = add nuw nsw i64 %indvars.iv.i.i26, 1
   br label %for.cond.i.i30
 
 lpad:                                             ; preds = %invoke.cont4, %invoke.cont, %_ZN11CStringBaseIcEC2EPKc.exit.critedge
-  %1 = landingpad { i8*, i32 }
+  %2 = landingpad { i8*, i32 }
           cleanup
   resume { i8*, i32 } undef
 }
diff --git a/test/CodeGen/PowerPC/qpx-bv-sint.ll b/test/CodeGen/PowerPC/qpx-bv-sint.ll
index 0bc14ed4351a..9682e756c425 100644
--- a/test/CodeGen/PowerPC/qpx-bv-sint.ll
+++ b/test/CodeGen/PowerPC/qpx-bv-sint.ll
@@ -2,13 +2,13 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "powerpc64-bgq-linux"
 ; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s
 
-define void @s452() nounwind {
+define void @s452(i32 %inp1) nounwind {
 entry:
   br label %for.body4
 
 for.body4:                                        ; preds = %for.body4, %entry
-  %conv.4 = sitofp i32 undef to double
-  %conv.5 = sitofp i32 undef to double
+  %conv.4 = sitofp i32 %inp1 to double
+  %conv.5 = sitofp i32 %inp1 to double
   %mul.4.v.i0.1 = insertelement <2 x double> undef, double %conv.4, i32 0
   %mul.4.v.i0.2 = insertelement <2 x double> %mul.4.v.i0.1, double %conv.5, i32 1
   %mul.4 = fmul <2 x double> %mul.4.v.i0.2, undef
diff --git a/test/CodeGen/PowerPC/qpx-load-splat.ll b/test/CodeGen/PowerPC/qpx-load-splat.ll
new file mode 100644
index 000000000000..c76d5226b348
--- /dev/null
+++ b/test/CodeGen/PowerPC/qpx-load-splat.ll
@@ -0,0 +1,75 @@
+; RUN: llc < %s | FileCheck %s
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64-bgq-linux"
+
+; Function Attrs: norecurse nounwind readonly
+define <4 x double> @foo(double* nocapture readonly %a) #0 {
+entry:
+  %0 = load double, double* %a, align 8
+  %vecinit.i = insertelement <4 x double> undef, double %0, i32 0
+  %shuffle.i = shufflevector <4 x double> %vecinit.i, <4 x double> undef, <4 x i32> zeroinitializer
+  ret <4 x double> %shuffle.i
+
+; CHECK-LABEL: @foo
+; CHECK: lfd 1, 0(3)
+; CHECK: blr
+}
+
+define <4 x double> @foox(double* nocapture readonly %a, i64 %idx) #0 {
+entry:
+  %p = getelementptr double, double* %a, i64 %idx
+  %0 = load double, double* %p, align 8
+  %vecinit.i = insertelement <4 x double> undef, double %0, i32 0
+  %shuffle.i = shufflevector <4 x double> %vecinit.i, <4 x double> undef, <4 x i32> zeroinitializer
+  ret <4 x double> %shuffle.i
+
+; CHECK-LABEL: @foox
+; CHECK: sldi [[REG1:[0-9]+]], 4, 3
+; CHECK: lfdx 1, 3, [[REG1]]
+; CHECK: blr
+}
+
+define <4 x double> @fooxu(double* nocapture readonly %a, i64 %idx, double** %pptr) #0 {
+entry:
+  %p = getelementptr double, double* %a, i64 %idx
+  %0 = load double, double* %p, align 8
+  %vecinit.i = insertelement <4 x double> undef, double %0, i32 0
+  %shuffle.i = shufflevector <4 x double> %vecinit.i, <4 x double> undef, <4 x i32> zeroinitializer
+  store double* %p, double** %pptr, align 8
+  ret <4 x double> %shuffle.i
+
+; CHECK-LABEL: @foox
+; CHECK: sldi [[REG1:[0-9]+]], 4, 3
+; CHECK: lfdux 1, 3, [[REG1]]
+; CHECK: std 3, 0(5)
+; CHECK: blr
+}
+
+define <4 x float> @foof(float* nocapture readonly %a) #0 {
+entry:
+  %0 = load float, float* %a, align 4
+  %vecinit.i = insertelement <4 x float> undef, float %0, i32 0
+  %shuffle.i = shufflevector <4 x float> %vecinit.i, <4 x float> undef, <4 x i32> zeroinitializer
+  ret <4 x float> %shuffle.i
+
+; CHECK-LABEL: @foof
+; CHECK: lfs 1, 0(3)
+; CHECK: blr
+}
+
+define <4 x float> @foofx(float* nocapture readonly %a, i64 %idx) #0 {
+entry:
+  %p = getelementptr float, float* %a, i64 %idx
+  %0 = load float, float* %p, align 4
+  %vecinit.i = insertelement <4 x float> undef, float %0, i32 0
+  %shuffle.i = shufflevector <4 x float> %vecinit.i, <4 x float> undef, <4 x i32> zeroinitializer
+  ret <4 x float> %shuffle.i
+
+; CHECK-LABEL: @foofx
+; CHECK: sldi [[REG1:[0-9]+]], 4, 2
+; CHECK: lfsx 1, 3, [[REG1]]
+; CHECK: blr
+}
+
+attributes #0 = { norecurse nounwind readonly "target-cpu"="a2q" "target-features"="+qpx,-altivec,-bpermd,-crypto,-direct-move,-extdiv,-power8-vector,-vsx" }
+
diff --git a/test/CodeGen/PowerPC/qpx-s-sel.ll b/test/CodeGen/PowerPC/qpx-s-sel.ll
index 09a615c4597d..6481fc6681a0 100644
--- a/test/CodeGen/PowerPC/qpx-s-sel.ll
+++ b/test/CodeGen/PowerPC/qpx-s-sel.ll
@@ -1,7 +1,6 @@
 ; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s
 target triple = "powerpc64-bgq-linux"
 
-@Q = constant <4 x i1> <i1 0, i1 undef, i1 1, i1 1>, align 16
 @R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16
 
 define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x i1> %c) nounwind readnone {
@@ -44,9 +43,9 @@ entry:
 ; blr
 }
 
-define <4 x i1> @test4(<4 x i1> %a) nounwind {
+define <4 x i1> @test4(<4 x i1> %a, <4 x i1>* %t) nounwind {
 entry:
-  %q = load <4 x i1>, <4 x i1>* @Q, align 16
+  %q = load <4 x i1>, <4 x i1>* %t, align 16
   %v = and <4 x i1> %a, %q
   ret <4 x i1> %v
 
diff --git a/test/CodeGen/PowerPC/qpx-sel.ll b/test/CodeGen/PowerPC/qpx-sel.ll
index a375e6effbae..4b23df328a86 100644
--- a/test/CodeGen/PowerPC/qpx-sel.ll
+++ b/test/CodeGen/PowerPC/qpx-sel.ll
@@ -1,7 +1,6 @@
 ; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s
 target triple = "powerpc64-bgq-linux"
 
-@Q = constant <4 x i1> <i1 0, i1 undef, i1 1, i1 1>, align 16
 @R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16
 
 define <4 x double> @test1(<4 x double> %a, <4 x double> %b, <4 x i1> %c) nounwind readnone {
@@ -48,9 +47,9 @@ entry:
 ; blr
 }
 
-define <4 x i1> @test4(<4 x i1> %a) nounwind {
+define <4 x i1> @test4(<4 x i1> %a, <4 x i1>* %t) nounwind {
 entry:
-  %q = load <4 x i1>, <4 x i1>* @Q, align 16
+  %q = load <4 x i1>, <4 x i1>* %t, align 16
   %v = and <4 x i1> %a, %q
   ret <4 x i1> %v
 
diff --git a/test/CodeGen/PowerPC/qpx-split-vsetcc.ll b/test/CodeGen/PowerPC/qpx-split-vsetcc.ll
index c8cef0faeaa4..5bda3f625401 100644
--- a/test/CodeGen/PowerPC/qpx-split-vsetcc.ll
+++ b/test/CodeGen/PowerPC/qpx-split-vsetcc.ll
@@ -3,27 +3,18 @@ target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-bgq-linux"
 
 ; Function Attrs: nounwind
-define void @gsl_sf_legendre_Pl_deriv_array() #0 {
+define void @gsl_sf_legendre_Pl_deriv_array(<4 x i32> %inp1, <4 x double> %inp2) #0 {
 entry:
-  br i1 undef, label %do.body.i, label %if.else.i
-
-do.body.i:                                        ; preds = %entry
-  unreachable
-
-if.else.i:                                        ; preds = %entry
-  br i1 undef, label %return, label %for.body46.lr.ph
-
-for.body46.lr.ph:                                 ; preds = %if.else.i
   br label %vector.body198
 
 vector.body198:                                   ; preds = %vector.body198, %for.body46.lr.ph
-  %0 = icmp ne <4 x i32> undef, zeroinitializer
+  %0 = icmp ne <4 x i32> %inp1, zeroinitializer
   %1 = select <4 x i1> %0, <4 x double> <double 5.000000e-01, double 5.000000e-01, double 5.000000e-01, double 5.000000e-01>, <4 x double> <double -5.000000e-01, double -5.000000e-01, double -5.000000e-01, double -5.000000e-01>
-  %2 = fmul <4 x double> undef, %1
-  %3 = fmul <4 x double> undef, %2
-  %4 = fmul <4 x double> %3, undef
+  %2 = fmul <4 x double> %inp2, %1
+  %3 = fmul <4 x double> %inp2, %2
+  %4 = fmul <4 x double> %3, %inp2
   store <4 x double> %4, <4 x double>* undef, align 8
-  br label %vector.body198
+  br label %return
 
 ; CHECK-LABEL: @gsl_sf_legendre_Pl_deriv_array
 ; CHECK: qvlfiwzx
diff --git a/test/CodeGen/PowerPC/remove-redundant-moves.ll b/test/CodeGen/PowerPC/remove-redundant-moves.ll
new file mode 100644
index 000000000000..6b845cbf380a
--- /dev/null
+++ b/test/CodeGen/PowerPC/remove-redundant-moves.ll
@@ -0,0 +1,107 @@
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE
+define double @test1(<2 x i64> %a) {
+entry:
+; CHECK-LABEL: test1
+; CHECK: xxswapd [[SW:[0-9]+]], 34
+; CHECK: xscvsxddp 1, [[SW]]
+; CHECK-BE-LABEL: test1
+; CHECK-BE: xxlor [[CP:[0-9]+]], 34, 34
+; CHECK-BE: xscvsxddp 1, [[CP]]
+  %0 = extractelement <2 x i64> %a, i32 0
+  %1 = sitofp i64 %0 to double
+  ret double %1
+}
+
+define double @test2(<2 x i64> %a) {
+entry:
+; CHECK-LABEL: test2
+; CHECK: xxlor [[CP:[0-9]+]], 34, 34
+; CHECK: xscvsxddp 1, [[CP]]
+; CHECK-BE-LABEL: test2
+; CHECK-BE: xxswapd [[SW:[0-9]+]], 34
+; CHECK-BE: xscvsxddp 1, [[SW]]
+  %0 = extractelement <2 x i64> %a, i32 1
+  %1 = sitofp i64 %0 to double
+  ret double %1
+}
+
+define float @test1f(<2 x i64> %a) {
+entry:
+; CHECK-LABEL: test1f
+; CHECK: xxswapd [[SW:[0-9]+]], 34
+; CHECK: xscvsxdsp 1, [[SW]]
+; CHECK-BE-LABEL: test1f
+; CHECK-BE: xxlor [[CP:[0-9]+]], 34, 34
+; CHECK-BE: xscvsxdsp 1, [[CP]]
+  %0 = extractelement <2 x i64> %a, i32 0
+  %1 = sitofp i64 %0 to float
+  ret float %1
+}
+
+define float @test2f(<2 x i64> %a) {
+entry:
+; CHECK-LABEL: test2f
+; CHECK: xxlor [[CP:[0-9]+]], 34, 34
+; CHECK: xscvsxdsp 1, [[CP]]
+; CHECK-BE-LABEL: test2f
+; CHECK-BE: xxswapd [[SW:[0-9]+]], 34
+; CHECK-BE: xscvsxdsp 1, [[SW]]
+  %0 = extractelement <2 x i64> %a, i32 1
+  %1 = sitofp i64 %0 to float
+  ret float %1
+}
+
+define double @test1u(<2 x i64> %a) {
+entry:
+; CHECK-LABEL: test1u
+; CHECK: xxswapd [[SW:[0-9]+]], 34
+; CHECK: xscvuxddp 1, [[SW]]
+; CHECK-BE-LABEL: test1u
+; CHECK-BE: xxlor [[CP:[0-9]+]], 34, 34
+; CHECK-BE: xscvuxddp 1, [[CP]]
+  %0 = extractelement <2 x i64> %a, i32 0
+  %1 = uitofp i64 %0 to double
+  ret double %1
+}
+
+define double @test2u(<2 x i64> %a) {
+entry:
+; CHECK-LABEL: test2u
+; CHECK: xxlor [[CP:[0-9]+]], 34, 34
+; CHECK: xscvuxddp 1, [[CP]]
+; CHECK-BE-LABEL: test2u
+; CHECK-BE: xxswapd [[SW:[0-9]+]], 34
+; CHECK-BE: xscvuxddp 1, [[SW]]
+  %0 = extractelement <2 x i64> %a, i32 1
+  %1 = uitofp i64 %0 to double
+  ret double %1
+}
+
+define float @test1fu(<2 x i64> %a) {
+entry:
+; CHECK-LABEL: test1fu
+; CHECK: xxswapd [[SW:[0-9]+]], 34
+; CHECK: xscvuxdsp 1, [[SW]]
+; CHECK-BE-LABEL: test1fu
+; CHECK-BE: xxlor [[CP:[0-9]+]], 34, 34
+; CHECK-BE: xscvuxdsp 1, [[CP]]
+  %0 = extractelement <2 x i64> %a, i32 0
+  %1 = uitofp i64 %0 to float
+  ret float %1
+}
+
+define float @test2fu(<2 x i64> %a) {
+entry:
+; CHECK-LABEL: test2fu
+; CHECK: xxlor [[CP:[0-9]+]], 34, 34
+; CHECK: xscvuxdsp 1, [[CP]]
+; CHECK-BE-LABEL: test2fu
+; CHECK-BE: xxswapd [[SW:[0-9]+]], 34
+; CHECK-BE: xscvuxdsp 1, [[SW]]
+  %0 = extractelement <2 x i64> %a, i32 1
+  %1 = uitofp i64 %0 to float
+  ret float %1
+}
diff --git a/test/CodeGen/PowerPC/rlwinm-zero-ext.ll b/test/CodeGen/PowerPC/rlwinm-zero-ext.ll
new file mode 100644
index 000000000000..f174bb64ba32
--- /dev/null
+++ b/test/CodeGen/PowerPC/rlwinm-zero-ext.ll
@@ -0,0 +1,57 @@
+; RUN: llc -O2 < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+; CHECK-LABEL: test1
+define i8 @test1(i32 %a) {
+entry:
+; CHECK-NOT: rlwinm {{{[0-9]+}}}, {{[0-9]+}}, 0, 24, 27
+; CHECK: rlwinm. [[REG:[0-9]+]], {{[0-9]+}}, 0, 24, 27
+; CHECK-NOT: cmplwi [[REG]], 0
+; CHECK: beq 0
+  %0 = and i32 %a, 240
+  %1 = icmp eq i32 %0, 0
+  br i1 %1, label %eq0, label %neq0
+eq0:
+  ret i8 102
+neq0:
+  ret i8 116
+}
+
+; CHECK-LABEL: test2
+define i8 @test2(i32 %a) {
+entry:
+; CHECK: rlwinm [[REG:[0-9]+]], {{[0-9]+}}, 0, 28, 23
+; CHECK: cmplwi [[REG]], 0
+; CHECK: beq 0
+  %0 = and i32 %a, -241
+  %1 = icmp eq i32 %0, 0
+  br i1 %1, label %eq0, label %neq0
+eq0:
+  ret i8 102
+neq0:
+  ret i8 116
+}
+
+declare {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)
+
+; CHECK-LABEL: test3
+define i8 @test3(i32 %a, i32 %b) {
+entry:
+; CHECK-NOT: rlwnm {{{[0-9]+}}}, {{[0-9]+}}, {{{[0-9]+}}}, 28, 31
+; CHECK: rlwnm. [[REG:[0-9]+]], {{[0-9]+}}, 4, 28, 31
+; CHECK-NOT: cmplwi [[REG]], 0
+; CHECK: beq 0
+  %left = shl i32 %a, %b
+  %res = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 32, i32 %b)
+  %right_amount = extractvalue {i32, i1} %res, 0
+  %right = lshr i32 %a, %right_amount
+  %0 = or i32 %left, %right
+  %1 = and i32 %0, 15
+  %2 = icmp eq i32 %1, 0
+  br i1 %2, label %eq0, label %neq0
+eq0:
+  ret i8 102
+neq0:
+  ret i8 116
+}
diff --git a/test/CodeGen/PowerPC/stack-protector.ll b/test/CodeGen/PowerPC/stack-protector.ll
index 8d255bd9a43b..57d1c7e52b1b 100644
--- a/test/CodeGen/PowerPC/stack-protector.ll
+++ b/test/CodeGen/PowerPC/stack-protector.ll
@@ -1,6 +1,17 @@
-; RUN: llc -march=ppc32 -mtriple=ppc32-unknown-linux < %s | FileCheck %s
-; CHECK: __stack_chk_guard
-; CHECK: __stack_chk_fail
+; RUN: llc -mtriple=powerpc-apple-darwin8 < %s | FileCheck -check-prefix=DARWIN32 %s
+; RUN: llc -mtriple=powerpc64-apple-darwin < %s | FileCheck -check-prefix=DARWIN64 %s
+; RUN: llc -mtriple=ppc32-unknown-linux < %s | FileCheck -check-prefix=LINUX32 %s
+; RUN: llc -mtriple=powerpc64le-unknown-linux < %s | FileCheck -check-prefix=LINUX64 %s
+
+; DARWIN32: __stack_chk_guard
+; DARWIN64: __stack_chk_guard
+; LINUX32: lwz {{[0-9]+}}, -28680(2)
+; LINUX64: ld {{[0-9]+}}, -28688(13)
+
+; DARWIN32: __stack_chk_fail
+; DARWIN64: __stack_chk_fail
+; LINUX32: __stack_chk_fail
+; LINUX64: __stack_chk_fail
 
 @"\01LC" = internal constant [11 x i8] c"buf == %s\0A\00"		; <[11 x i8]*> [#uses=1]
 
diff --git a/test/CodeGen/PowerPC/stackmap-frame-setup.ll b/test/CodeGen/PowerPC/stackmap-frame-setup.ll
index 487da00faa1c..b5f1d4cfe4bc 100644
--- a/test/CodeGen/PowerPC/stackmap-frame-setup.ll
+++ b/test/CodeGen/PowerPC/stackmap-frame-setup.ll
@@ -1,5 +1,5 @@
-; RUN: llc -o /dev/null -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -stop-after machine-sink %s | FileCheck %s --check-prefix=ISEL
-; RUN: llc -o /dev/null -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -fast-isel -fast-isel-abort=1 -stop-after machine-sink %s | FileCheck %s --check-prefix=FAST-ISEL
+; RUN: llc -o - -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -stop-after machine-sink %s | FileCheck %s --check-prefix=ISEL
+; RUN: llc -o - -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -fast-isel -fast-isel-abort=1 -stop-after machine-sink %s | FileCheck %s --check-prefix=FAST-ISEL
 
 define void @caller_meta_leaf() {
 entry:
diff --git a/test/CodeGen/PowerPC/stubs.ll b/test/CodeGen/PowerPC/stubs.ll
index 694f208198a1..a167cb823325 100644
--- a/test/CodeGen/PowerPC/stubs.ll
+++ b/test/CodeGen/PowerPC/stubs.ll
@@ -1,4 +1,4 @@
-; RUN: llc %s -o - -mtriple=powerpc-apple-darwin8 | FileCheck %s
+; RUN: llc %s -o - -mtriple=powerpc-apple-darwin9 | FileCheck %s
 define ppc_fp128 @test1(i64 %X) nounwind readnone {
 entry:
   %0 = sitofp i64 %X to ppc_fp128
@@ -6,17 +6,4 @@ entry:
 }
 
 ; CHECK: _test1:
-; CHECK: bl L___floatditf$stub
-; CHECK: 	.section	__TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16
-; CHECK: L___floatditf$stub:
-; CHECK: 	.indirect_symbol ___floatditf
-; CHECK: 	lis r11, ha16(L___floatditf$lazy_ptr)
-; CHECK: 	lwzu r12, lo16(L___floatditf$lazy_ptr)(r11)
-; CHECK: 	mtctr r12
-; CHECK: 	bctr
-; CHECK: 	.section	__DATA,__la_symbol_ptr,lazy_symbol_pointers
-; CHECK: L___floatditf$lazy_ptr:
-; CHECK: 	.indirect_symbol ___floatditf
-; CHECK: 	.long dyld_stub_binding_helper
-
-
+; CHECK: bl ___floatditf
diff --git a/test/CodeGen/PowerPC/stwux.ll b/test/CodeGen/PowerPC/stwux.ll
index 2ed630d8002d..4f83c9f64ea5 100644
--- a/test/CodeGen/PowerPC/stwux.ll
+++ b/test/CodeGen/PowerPC/stwux.ll
@@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 @multvec_i = external unnamed_addr global [100 x i32], align 4
 
-define fastcc void @subs_STMultiExceptIntern() nounwind {
+define fastcc void @subs_STMultiExceptIntern(i32 %input) nounwind {
 entry:
   br i1 undef, label %while.body.lr.ph, label %return
 
@@ -16,10 +16,11 @@ while.body:                                       ; preds = %if.end12, %while.bo
   br i1 undef, label %if.end12, label %if.then
 
 if.then:                                          ; preds = %while.body
+  %0 = add i32 %input, 1
   br label %if.end12
 
 if.end12:                                         ; preds = %if.then, %while.body
-  %i.1 = phi i32 [ %i.0240, %while.body ], [ undef, %if.then ]
+  %i.1 = phi i32 [ %i.0240, %while.body ], [ %0, %if.then ]
   br i1 undef, label %while.body, label %while.end
 
 while.end:                                        ; preds = %if.end12
diff --git a/test/CodeGen/PowerPC/subreg-postra-2.ll b/test/CodeGen/PowerPC/subreg-postra-2.ll
index 051536443413..5471b11933bf 100644
--- a/test/CodeGen/PowerPC/subreg-postra-2.ll
+++ b/test/CodeGen/PowerPC/subreg-postra-2.ll
@@ -3,158 +3,30 @@ target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 ; Function Attrs: nounwind
-define void @jbd2_journal_commit_transaction() #0 {
+define void @jbd2_journal_commit_transaction(i32 %input1, i32* %input2, i32* %input3, i8** %input4) #0 {
 entry:
-  br i1 undef, label %do.body, label %if.then5
-
-if.then5:                                         ; preds = %entry
-  unreachable
-
-do.body:                                          ; preds = %entry
-  br i1 undef, label %do.body.i, label %trace_jbd2_start_commit.exit
-
-do.body.i:                                        ; preds = %do.body
-  unreachable
-
-trace_jbd2_start_commit.exit:                     ; preds = %do.body
-  br i1 undef, label %do.body.i1116, label %trace_jbd2_commit_locking.exit
-
-do.body.i1116:                                    ; preds = %trace_jbd2_start_commit.exit
-  unreachable
-
-trace_jbd2_commit_locking.exit:                   ; preds = %trace_jbd2_start_commit.exit
-  br i1 undef, label %while.end, label %while.body.lr.ph
-
-while.body.lr.ph:                                 ; preds = %trace_jbd2_commit_locking.exit
-  unreachable
-
-while.end:                                        ; preds = %trace_jbd2_commit_locking.exit
-  br i1 undef, label %spin_unlock.exit1146, label %if.then.i.i.i.i1144
-
-if.then.i.i.i.i1144:                              ; preds = %while.end
-  unreachable
-
-spin_unlock.exit1146:                             ; preds = %while.end
-  br i1 undef, label %spin_unlock.exit1154, label %if.then.i.i.i.i1152
-
-if.then.i.i.i.i1152:                              ; preds = %spin_unlock.exit1146
-  unreachable
-
-spin_unlock.exit1154:                             ; preds = %spin_unlock.exit1146
-  br i1 undef, label %do.body.i1159, label %trace_jbd2_commit_flushing.exit
-
-do.body.i1159:                                    ; preds = %spin_unlock.exit1154
-  br i1 undef, label %if.end.i1166, label %do.body5.i1165
-
-do.body5.i1165:                                   ; preds = %do.body.i1159
-  unreachable
-
-if.end.i1166:                                     ; preds = %do.body.i1159
-  unreachable
-
-trace_jbd2_commit_flushing.exit:                  ; preds = %spin_unlock.exit1154
-  br i1 undef, label %for.end.i, label %for.body.lr.ph.i
-
-for.body.lr.ph.i:                                 ; preds = %trace_jbd2_commit_flushing.exit
-  unreachable
-
-for.end.i:                                        ; preds = %trace_jbd2_commit_flushing.exit
-  br i1 undef, label %journal_submit_data_buffers.exit, label %if.then.i.i.i.i31.i
-
-if.then.i.i.i.i31.i:                              ; preds = %for.end.i
-  br label %journal_submit_data_buffers.exit
-
-journal_submit_data_buffers.exit:                 ; preds = %if.then.i.i.i.i31.i, %for.end.i
-  br i1 undef, label %if.end103, label %if.then102
-
-if.then102:                                       ; preds = %journal_submit_data_buffers.exit
-  unreachable
-
-if.end103:                                        ; preds = %journal_submit_data_buffers.exit
-  br i1 undef, label %do.body.i1182, label %trace_jbd2_commit_logging.exit
-
-do.body.i1182:                                    ; preds = %if.end103
-  br i1 undef, label %if.end.i1189, label %do.body5.i1188
-
-do.body5.i1188:                                   ; preds = %do.body5.i1188, %do.body.i1182
-  br i1 undef, label %if.end.i1189, label %do.body5.i1188
-
-if.end.i1189:                                     ; preds = %do.body5.i1188, %do.body.i1182
-  unreachable
-
-trace_jbd2_commit_logging.exit:                   ; preds = %if.end103
-  br label %while.cond129.outer1451
-
-while.cond129.outer1451:                          ; preds = %start_journal_io, %trace_jbd2_commit_logging.exit
-  br label %while.cond129
-
-while.cond129:                                    ; preds = %if.then135, %while.cond129.outer1451
-  br i1 undef, label %while.end246, label %if.then135
-
-if.then135:                                       ; preds = %while.cond129
-  br i1 undef, label %start_journal_io, label %while.cond129
-
-start_journal_io:                                 ; preds = %if.then135
-  br label %while.cond129.outer1451
-
-while.end246:                                     ; preds = %while.cond129
-  br i1 undef, label %for.end.i1287, label %for.body.i1277
-
-for.body.i1277:                                   ; preds = %while.end246
-  unreachable
-
-for.end.i1287:                                    ; preds = %while.end246
-  br i1 undef, label %journal_finish_inode_data_buffers.exit, label %if.then.i.i.i.i84.i
-
-if.then.i.i.i.i84.i:                              ; preds = %for.end.i1287
-  unreachable
-
-journal_finish_inode_data_buffers.exit:           ; preds = %for.end.i1287
-  br i1 undef, label %if.end256, label %if.then249
-
-if.then249:                                       ; preds = %journal_finish_inode_data_buffers.exit
-  unreachable
-
-if.end256:                                        ; preds = %journal_finish_inode_data_buffers.exit
-  br label %while.body318
-
-while.body318:                                    ; preds = %wait_on_buffer.exit, %if.end256
-  br i1 undef, label %wait_on_buffer.exit, label %if.then.i1296
-
-if.then.i1296:                                    ; preds = %while.body318
-  br label %wait_on_buffer.exit
-
-wait_on_buffer.exit:                              ; preds = %if.then.i1296, %while.body318
-  br i1 undef, label %do.body378, label %while.body318
-
-do.body378:                                       ; preds = %wait_on_buffer.exit
-  br i1 undef, label %while.end418, label %while.body392.lr.ph
-
-while.body392.lr.ph:                              ; preds = %do.body378
   br label %while.body392
 
 while.body392:                                    ; preds = %wait_on_buffer.exit1319, %while.body392.lr.ph
-  %0 = load i8*, i8** undef, align 8
+  %0 = load i8*, i8** %input4, align 8
   %add.ptr399 = getelementptr inbounds i8, i8* %0, i64 -72
   %b_state.i.i1314 = bitcast i8* %add.ptr399 to i64*
-  %tobool.i1316 = icmp eq i64 undef, 0
-  br i1 %tobool.i1316, label %wait_on_buffer.exit1319, label %if.then.i1317
-
-if.then.i1317:                                    ; preds = %while.body392
-  unreachable
+  %ivar = add i32 %input1, 1
+  %tobool.i1316 = icmp eq i32 %input1, 0
+  br i1 %tobool.i1316, label %wait_on_buffer.exit1319, label %while.end418
 
 wait_on_buffer.exit1319:                          ; preds = %while.body392
   %1 = load volatile i64, i64* %b_state.i.i1314, align 8
   %conv.i.i1322 = and i64 %1, 1
   %lnot404 = icmp eq i64 %conv.i.i1322, 0
-  %.err.4 = select i1 %lnot404, i32 -5, i32 undef
+  %.err.4 = select i1 %lnot404, i32 -5, i32 %input1
   %2 = call i64 asm sideeffect "1:.long 0x7c0000a8 $| ((($0) & 0x1f) << 21) $| (((0) & 0x1f) << 16) $| ((($3) & 0x1f) << 11) $| (((0) & 0x1) << 0) \0Aandc $0,$0,$2\0Astdcx. $0,0,$3\0Abne- 1b\0A", "=&r,=*m,r,r,*m,~{cc},~{memory}"(i64* %b_state.i.i1314, i64 262144, i64* %b_state.i.i1314, i64* %b_state.i.i1314) #0
-  store i8* %0, i8** undef, align 8
-  %cmp.i1312 = icmp eq i32* undef, undef
+  store i8* %0, i8** %input4, align 8
+  %cmp.i1312 = icmp eq i32* %input2, %input3
   br i1 %cmp.i1312, label %while.end418, label %while.body392
 
 while.end418:                                     ; preds = %wait_on_buffer.exit1319, %do.body378
-  %err.4.lcssa = phi i32 [ undef, %do.body378 ], [ %.err.4, %wait_on_buffer.exit1319 ]
+  %err.4.lcssa = phi i32 [ %ivar, %while.body392 ], [ %.err.4, %wait_on_buffer.exit1319 ]
   %tobool419 = icmp eq i32 %err.4.lcssa, 0
   br i1 %tobool419, label %if.end421, label %if.then420
 
@@ -169,6 +41,7 @@ if.then420:                                       ; preds = %while.end418
 
 if.end421:                                        ; preds = %while.end418
   unreachable
+
 }
 
 attributes #0 = { nounwind }
diff --git a/test/CodeGen/PowerPC/subreg-postra.ll b/test/CodeGen/PowerPC/subreg-postra.ll
index ba1b967cf204..b9f17465d003 100644
--- a/test/CodeGen/PowerPC/subreg-postra.ll
+++ b/test/CodeGen/PowerPC/subreg-postra.ll
@@ -3,7 +3,10 @@ target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 ; Function Attrs: nounwind
-define void @jbd2_journal_commit_transaction(i32* %journal) #0 {
+define void @jbd2_journal_commit_transaction(i32* %journal, i64 %inp1, i32 %inp2,
+                                             i32* %inp3, i32** %inp4,
+                                             i32** %inp5, i1 %inp6,
+                                             i1 %inp7, i1 %inp8) #0 {
 entry:
   br i1 undef, label %do.body, label %if.then5
 
@@ -104,17 +107,17 @@ do.body277:                                       ; preds = %if.then260, %if.end
   br label %while.body318
 
 while.body318:                                    ; preds = %wait_on_buffer.exit, %do.body277
-  %tobool.i1295 = icmp eq i64 undef, 0
+  %tobool.i1295 = icmp eq i64 %inp1, 0
   br i1 %tobool.i1295, label %wait_on_buffer.exit, label %if.then.i1296
 
 if.then.i1296:                                    ; preds = %while.body318
   unreachable
 
 wait_on_buffer.exit:                              ; preds = %while.body318
-  br i1 undef, label %do.body378, label %while.body318
+  br i1 %inp6, label %do.body378, label %while.body318
 
 do.body378:                                       ; preds = %wait_on_buffer.exit
-  br i1 undef, label %while.end418, label %while.body392.lr.ph
+  br i1 %inp7, label %while.end418, label %while.body392.lr.ph
 
 while.body392.lr.ph:                              ; preds = %do.body378
   br label %while.body392
@@ -123,7 +126,7 @@ while.body392:                                    ; preds = %wait_on_buffer.exit
   %0 = load i8*, i8** undef, align 8
   %add.ptr399 = getelementptr inbounds i8, i8* %0, i64 -72
   %b_state.i.i1314 = bitcast i8* %add.ptr399 to i64*
-  %tobool.i1316 = icmp eq i64 undef, 0
+  %tobool.i1316 = icmp eq i64 %inp1, 0
   br i1 %tobool.i1316, label %wait_on_buffer.exit1319, label %if.then.i1317
 
 if.then.i1317:                                    ; preds = %while.body392
@@ -133,23 +136,23 @@ wait_on_buffer.exit1319:                          ; preds = %while.body392
   %1 = load volatile i64, i64* %b_state.i.i1314, align 8
   %conv.i.i1322 = and i64 %1, 1
   %lnot404 = icmp eq i64 %conv.i.i1322, 0
-  %.err.4 = select i1 %lnot404, i32 -5, i32 undef
+  %.err.4 = select i1 %lnot404, i32 -5, i32 %inp2
   %2 = call i64 asm sideeffect "1:.long 0x7c0000a8 $| ((($0) & 0x1f) << 21) $| (((0) & 0x1f) << 16) $| ((($3) & 0x1f) << 11) $| (((0) & 0x1) << 0) \0Aandc $0,$0,$2\0Astdcx. $0,0,$3\0Abne- 1b\0A", "=&r,=*m,r,r,*m,~{cc},~{memory}"(i64* %b_state.i.i1314, i64 262144, i64* %b_state.i.i1314, i64* %b_state.i.i1314) #1
   %prev.i.i.i1325 = getelementptr inbounds i8, i8* %0, i64 8
-  %3 = load i32*, i32** null, align 8
-  store i32* %3, i32** undef, align 8
-  call void @__brelse(i32* undef) #1
-  br i1 undef, label %while.end418, label %while.body392
+  %3 = load i32*, i32** %inp4, align 8
+  store i32* %3, i32** %inp5, align 8
+  call void @__brelse(i32* %3) #1
+  br i1 %inp8, label %while.end418, label %while.body392
 
 ; CHECK-LABEL: @jbd2_journal_commit_transaction
 ; CHECK: andi.
-; CHECK: crmove [[REG:[0-9]+]], 1
+; CHECK: crmove
 ; CHECK: stdcx.
-; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]]
+; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}},
 
 while.end418:                                     ; preds = %wait_on_buffer.exit1319, %do.body378
-  %err.4.lcssa = phi i32 [ undef, %do.body378 ], [ %.err.4, %wait_on_buffer.exit1319 ]
-  br i1 undef, label %if.end421, label %if.then420
+  %err.4.lcssa = phi i32 [ %inp2, %do.body378 ], [ %.err.4, %wait_on_buffer.exit1319 ]
+  br i1 %inp7, label %if.end421, label %if.then420
 
 if.then420:                                       ; preds = %while.end418
   call void @jbd2_journal_abort(i32* %journal, i32 signext %err.4.lcssa) #1
diff --git a/test/CodeGen/PowerPC/subsumes-pred-regs.ll b/test/CodeGen/PowerPC/subsumes-pred-regs.ll
deleted file mode 100644
index 5389c1318445..000000000000
--- a/test/CodeGen/PowerPC/subsumes-pred-regs.ll
+++ /dev/null
@@ -1,65 +0,0 @@
-; RUN: llc < %s -mcpu=ppc64 -mattr=-crbits | FileCheck %s
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
-; Function Attrs: nounwind
-define zeroext i1 @test1() unnamed_addr #0 align 2 {
-
-; CHECK-LABEL: @test1
-
-entry:
-  br i1 undef, label %lor.end, label %lor.rhs
-
-lor.rhs:                                          ; preds = %entry
-  unreachable
-
-lor.end:                                          ; preds = %entry
-  br i1 undef, label %land.rhs, label %if.then
-
-if.then:                                          ; preds = %lor.end
-  br i1 undef, label %return, label %if.end.i24
-
-if.end.i24:                                       ; preds = %if.then
-  %0 = load i32, i32* undef, align 4
-  %lnot.i.i16.i23 = icmp eq i32 %0, 0
-  br i1 %lnot.i.i16.i23, label %if.end7.i37, label %test.exit27.i34
-
-test.exit27.i34: ; preds = %if.end.i24
-  br i1 undef, label %return, label %if.end7.i37
-
-if.end7.i37:                                      ; preds = %test.exit27.i34, %if.end.i24
-  %tobool.i.i36 = icmp eq i8 undef, 0
-  br i1 %tobool.i.i36, label %return, label %if.then9.i39
-
-if.then9.i39:                                     ; preds = %if.end7.i37
-  br i1 %lnot.i.i16.i23, label %return, label %lor.rhs.i.i49
-
-; CHECK: .LBB0_7:
-; CHECK:	bne 1, .LBB0_10
-; CHECK:	beq 0, .LBB0_10
-; CHECK: .LBB0_9:
-
-lor.rhs.i.i49:                                    ; preds = %if.then9.i39
-  %cmp.i.i.i.i48 = icmp ne i64 undef, 0
-  br label %return
-
-land.rhs:                                         ; preds = %lor.end
-  br i1 undef, label %return, label %if.end.i
-
-if.end.i:                                         ; preds = %land.rhs
-  br i1 undef, label %return, label %if.then9.i
-
-if.then9.i:                                       ; preds = %if.end.i
-  br i1 undef, label %return, label %lor.rhs.i.i
-
-lor.rhs.i.i:                                      ; preds = %if.then9.i
-  %cmp.i.i.i.i = icmp ne i64 undef, 0
-  br label %return
-
-return:                                           ; preds = %lor.rhs.i.i, %if.then9.i, %if.end.i, %land.rhs, %lor.rhs.i.i49, %if.then9.i39, %if.end7.i37, %test.exit27.i34, %if.then
-  %retval.0 = phi i1 [ false, %if.then ], [ false, %test.exit27.i34 ], [ true, %if.end7.i37 ], [ true, %if.then9.i39 ], [ %cmp.i.i.i.i48, %lor.rhs.i.i49 ], [ false, %land.rhs ], [ true, %if.end.i ], [ true, %if.then9.i ], [ %cmp.i.i.i.i, %lor.rhs.i.i ]
-  ret i1 %retval.0
-}
-
-attributes #0 = { nounwind }
-
diff --git a/test/CodeGen/PowerPC/svr4-redzone.ll b/test/CodeGen/PowerPC/svr4-redzone.ll
index bee3ac32b648..a72ac104fc68 100644
--- a/test/CodeGen/PowerPC/svr4-redzone.ll
+++ b/test/CodeGen/PowerPC/svr4-redzone.ll
@@ -2,10 +2,10 @@
 ; RUN: llc -mtriple="powerpc64-unknown-linux-gnu" < %s | FileCheck %s --check-prefix=PPC64
 ; PR15332
 
-define void @regalloc() nounwind {
+define i32 @regalloc() nounwind {
 entry:
-	%0 = add i32 1, 2
-	ret void
+ %0 = add i32 1, 2
+       ret i32 %0
 }
 ; PPC32-LABEL: regalloc:
 ; PPC32-NOT: stwu 1, -{{[0-9]+}}(1)
@@ -15,10 +15,10 @@ entry:
 ; PPC64-NOT: stdu 1, -{{[0-9]+}}(1)
 ; PPC64: blr
 
-define void @smallstack() nounwind {
+define i8* @smallstack() nounwind {
 entry:
-	%0 = alloca i8, i32 4
-	ret void
+ %0 = alloca i8, i32 4
+       ret i8* %0
 }
 ; PPC32-LABEL: smallstack:
 ; PPC32: stwu 1, -16(1)
@@ -27,10 +27,10 @@ entry:
 ; PPC64-NOT: stdu 1, -{{[0-9]+}}(1)
 ; PPC64: blr
 
-define void @bigstack() nounwind {
+define i8* @bigstack() nounwind {
 entry:
-	%0 = alloca i8, i32 230
-	ret void
+ %0 = alloca i8, i32 230
+       ret i8* %0
 }
 ; PPC32-LABEL: bigstack:
 ; PPC32: stwu 1, -240(1)
diff --git a/test/CodeGen/PowerPC/swaps-le-2.ll b/test/CodeGen/PowerPC/swaps-le-2.ll
index 08096ed20ddb..9d1eb412cba3 100644
--- a/test/CodeGen/PowerPC/swaps-le-2.ll
+++ b/test/CodeGen/PowerPC/swaps-le-2.ll
@@ -87,5 +87,5 @@ entry:
 
 ; CHECK-LABEL: @ifoo
 ; CHECK: lxvd2x
-; CHECK: vspltw {{[0-9]+}}, {{[0-9]+}}, 0
+; CHECK: xxspltw {{[0-9]+}}, {{[0-9]+}}, 0
 ; CHECK: stxvd2x
diff --git a/test/CodeGen/PowerPC/swaps-le-7.ll b/test/CodeGen/PowerPC/swaps-le-7.ll
new file mode 100644
index 000000000000..0c6970f5b17e
--- /dev/null
+++ b/test/CodeGen/PowerPC/swaps-le-7.ll
@@ -0,0 +1,55 @@
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -O3 < %s | FileCheck %s
+;
+; This is a regression test based on https://llvm.org/bugs/show_bug.cgi?id=27735
+;
+
+@G1 = global <2 x double> <double 2.0, double -10.0>
+@G2 = global <2 x double> <double 3.0, double 4.0>
+@G3 = global <2 x double> <double 5.0, double 6.0>
+@G4 = global <2 x double> <double 7.0, double 8.0>
+
+; CHECK-LABEL: @zg
+; CHECK: xxspltd
+; CHECK-NEXT: xxspltd
+; CHECK-NEXT: xxswapd
+; CHECK-NEXT: xvmuldp
+; CHECK-NEXT: xvmuldp
+; CHECK-NEXT: xvsubdp
+; CHECK-NEXT: xvadddp
+; CHECK-NEXT: xxpermdi
+; CHECK-NEXT: xvsubdp
+; CHECK-NEXT: xxswapd
+; CHECK-NEXT: stxvd2x
+; CHECK-NEXT: blr
+
+; Function Attrs: noinline
+define void @zg(i8* %.G0011_640.0, i8* %.G0012_642.0, <2 x double>* %JJ, <2 x double>* %.ka0000_391, double %.unpack, double %.unpack66) #0 {
+L.JA291:
+  %Z.L.JA291.2 = load <2 x double>, <2 x double>* %.ka0000_391, align 16
+  store <2 x double> %Z.L.JA291.2, <2 x double>* %JJ, align 8
+  %Z.L.JA291.3 = bitcast i8* %.G0012_642.0 to <2 x double>*
+  %Z.L.JA291.4 = load <2 x double>, <2 x double>* %Z.L.JA291.3, align 1
+  %.elt136 = bitcast i8* %.G0011_640.0 to double*
+  %.unpack137 = load double, double* %.elt136, align 1
+  %.elt138 = getelementptr inbounds i8, i8* %.G0011_640.0, i64 8
+  %Z.L.JA291.5 = bitcast i8* %.elt138 to double*
+  %.unpack139 = load double, double* %Z.L.JA291.5, align 1
+  %Z.L.JA291.6 = insertelement <2 x double> undef, double %.unpack137, i32 0
+  %Z.L.JA291.7 = insertelement <2 x double> %Z.L.JA291.6, double %.unpack137, i32 1
+  %Z.L.JA291.8 = fmul <2 x double> %Z.L.JA291.2, %Z.L.JA291.7
+  %Z.L.JA291.9 = shufflevector <2 x double> %Z.L.JA291.2, <2 x double> undef, <2 x i32> <i32 1, i32 0>
+  %Z.L.JA291.10 = insertelement <2 x double> undef, double %.unpack139, i32 0
+  %Z.L.JA291.11 = insertelement <2 x double> %Z.L.JA291.10, double %.unpack139, i32 1
+  %Z.L.JA291.12 = fmul <2 x double> %Z.L.JA291.9, %Z.L.JA291.11
+  %Z.L.JA291.13 = fsub <2 x double> %Z.L.JA291.8, %Z.L.JA291.12
+  %Z.L.JA291.14 = fadd <2 x double> %Z.L.JA291.8, %Z.L.JA291.12
+  %Z.L.JA291.15 = shufflevector <2 x double> %Z.L.JA291.13, <2 x double> %Z.L.JA291.14, <2 x i32> <i32 0, i32 3>
+  %Z.L.JA291.16 = fsub <2 x double> %Z.L.JA291.4, %Z.L.JA291.15
+  %Z.L.JA291.17 = bitcast i8* %.G0012_642.0 to <2 x double>*
+  store <2 x double> %Z.L.JA291.16, <2 x double>* %Z.L.JA291.17, align 8
+  %.. = bitcast <2 x double>* %JJ to i32*
+  %.pre = load i32, i32* %.., align 32
+  ret void
+}
+
+attributes #0 = { noinline }
\ No newline at end of file
diff --git a/test/CodeGen/PowerPC/tailcall-string-rvo.ll b/test/CodeGen/PowerPC/tailcall-string-rvo.ll
new file mode 100644
index 000000000000..3f850e6e94b7
--- /dev/null
+++ b/test/CodeGen/PowerPC/tailcall-string-rvo.ll
@@ -0,0 +1,47 @@
+; RUN: llc -O2 < %s | FileCheck %s
+
+; The call to function TestBar should be a tail call, when in C++ the string
+; `ret` is RVO returned.
+; string TestFoo() {
+;   string ret = undef;
+;   TestBar(&ret);  // tail call optimized
+;   return ret;
+; }
+
+target triple = "powerpc64le-linux-gnu"
+
+%class.basic_string.11.42.73 = type { %"class.__gnu_cxx::__versa_string.10.41.72" }
+%"class.__gnu_cxx::__versa_string.10.41.72" = type { %"class.__gnu_cxx::__sso_string_base.9.40.71" }
+%"class.__gnu_cxx::__sso_string_base.9.40.71" = type { %"struct.__gnu_cxx::__vstring_utility<char, std::char_traits<char>, std::allocator<char> >::_Alloc_hider.7.38.69", i64, %union.anon.8.39.70 }
+%"struct.__gnu_cxx::__vstring_utility<char, std::char_traits<char>, std::allocator<char> >::_Alloc_hider.7.38.69" = type { i8* }
+%union.anon.8.39.70 = type { i64, [8 x i8] }
+
+declare void @TestBaz(%class.basic_string.11.42.73* noalias sret %arg)
+
+define void @TestBar(%class.basic_string.11.42.73* noalias sret %arg) {
+bb:
+  call void @TestBaz(%class.basic_string.11.42.73* noalias sret %arg)
+  ret void
+}
+
+define void @TestFoo(%class.basic_string.11.42.73* noalias sret %arg) {
+; CHECK-LABEL: TestFoo:
+; CHECK: #TC_RETURNd8 TestBar 0
+bb:
+  %tmp = getelementptr inbounds %class.basic_string.11.42.73, %class.basic_string.11.42.73* %arg, i64 0, i32 0, i32 0, i32 2
+  %tmp1 = bitcast %class.basic_string.11.42.73* %arg to %union.anon.8.39.70**
+  store %union.anon.8.39.70* %tmp, %union.anon.8.39.70** %tmp1, align 8
+  %tmp2 = bitcast %union.anon.8.39.70* %tmp to i8*
+  tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp2, i8* nonnull undef, i64 13, i32 1, i1 false)
+  %tmp3 = getelementptr inbounds %class.basic_string.11.42.73, %class.basic_string.11.42.73* %arg, i64 0, i32 0, i32 0, i32 1
+  store i64 13, i64* %tmp3, align 8
+  %tmp4 = getelementptr inbounds %class.basic_string.11.42.73, %class.basic_string.11.42.73* %arg, i64 0, i32 0, i32 0, i32 2, i32 1, i64 5
+  store i8 0, i8* %tmp4, align 1
+  tail call void @TestBar(%class.basic_string.11.42.73* noalias sret %arg)
+  ret void
+}
+
+; Function Attrs: argmemonly nounwind
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #0
+
+attributes #0 = { argmemonly nounwind }
diff --git a/test/CodeGen/PowerPC/thread-pointer.ll b/test/CodeGen/PowerPC/thread-pointer.ll
new file mode 100644
index 000000000000..2e8282d8dfb0
--- /dev/null
+++ b/test/CodeGen/PowerPC/thread-pointer.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s --check-prefix=CHECK-64
+
+; Function Attrs: nounwind readnone
+declare i8* @llvm.thread.pointer() #1
+
+define i8* @thread_pointer() {
+; CHECK-32-LABEL: @thread_pointer
+; CHECK-32: mr 3, 2
+; CHECK-32: blr
+; CHECK-64-LABEL: @thread_pointer
+; CHECK-64: mr 3, 13
+; CHECK-64: blr
+  %1 = tail call i8* @llvm.thread.pointer()
+  ret i8* %1
+}
diff --git a/test/CodeGen/PowerPC/tls_get_addr_stackframe.ll b/test/CodeGen/PowerPC/tls_get_addr_stackframe.ll
index 4a235983e6f7..5ce7dfc54117 100644
--- a/test/CodeGen/PowerPC/tls_get_addr_stackframe.ll
+++ b/test/CodeGen/PowerPC/tls_get_addr_stackframe.ll
@@ -9,24 +9,19 @@
 
 @tls_var = external thread_local global %struct1.2.41*, align 8
 
-define void @foo_test() {
+define i32 @foo_test() {
   %1 = load %struct1.2.41*, %struct1.2.41** @tls_var, align 8
-  br i1 undef, label %foo.exit, label %2
 
-; <label>:2                                       ; preds = %0
-  br i1 undef, label %foo.exit, label %3
+  %2 = getelementptr inbounds %struct1.2.41, %struct1.2.41* %1, i64 0, i32 0, i32 3
+  %3 = load i32, i32* %2, align 8
+  %4 = add nsw i32 %3, -1
+  %5 = icmp eq i32 %4, 0
+  br i1 %5, label %bb7, label %foo.exit
 
-; <label>:3                                       ; preds = %2
-  %4 = getelementptr inbounds %struct1.2.41, %struct1.2.41* %1, i64 0, i32 0, i32 3
-  %5 = load i32, i32* %4, align 8
-  %6 = add nsw i32 %5, -1
-  %7 = icmp eq i32 %6, 0
-  br i1 %7, label %8, label %foo.exit
-
-; <label>:8                                       ; preds = %3
+bb7:                                       ; preds = %3
   tail call void undef(%struct1.2.41* undef, %struct1.2.41* nonnull undef)
   br label %foo.exit
 
 foo.exit:                                         ; preds = %8, %3, %2, %0
-  ret void
+  ret i32 %4
 }
diff --git a/test/CodeGen/PowerPC/unal-altivec.ll b/test/CodeGen/PowerPC/unal-altivec.ll
index 02f7ab40f049..823a6a70b859 100644
--- a/test/CodeGen/PowerPC/unal-altivec.ll
+++ b/test/CodeGen/PowerPC/unal-altivec.ll
@@ -30,17 +30,19 @@ vector.body:                                      ; preds = %vector.body, %vecto
 
 ; CHECK: @foo
 ; CHECK-DAG: li [[C0:[0-9]+]], 0
-; CHECK-DAG: li [[C16:[0-9]+]], 16
-; CHECK-DAG: li [[C31:[0-9]+]], 31
+; CHECK-DAG: li [[C15:[0-9]+]], 15
 ; CHECK-DAG: lvx [[CNST:[0-9]+]],
 ; CHECK: .LBB0_1:
-; CHECK-DAG: lvsl [[PC:[0-9]+]], [[B1:[0-9]+]], [[C0]]
-; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
+; CHECK-DAG: lvsl [[MASK1:[0-9]+]], [[B1:[0-9]+]], [[C0]]
+; CHECK-DAG: lvsl [[MASK2:[0-9]+]], [[B2:[0-9]+]], [[C0]]
 ; CHECK-DAG: add [[B3:[0-9]+]], [[B1]], [[C0]]
-; CHECK-DAG: lvx [[LD2:[0-9]+]], [[B3]], [[C16]]
-; CHECK-DAG: lvx [[LD3:[0-9]+]], [[B3]], [[C31]]
-; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[PC]]
-; CHECK-DAG: vperm [[R2:[0-9]+]], [[LD2]], [[LD3]], [[PC]]
+; CHECK-DAG: add [[B4:[0-9]+]], [[B2]], [[C0]]
+; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
+; CHECK-DAG: lvx [[LD2:[0-9]+]], [[B3]], [[C15]]
+; CHECK-DAG: lvx [[LD3:[0-9]+]], [[B2]], [[C0]]
+; CHECK-DAG: lvx [[LD4:[0-9]+]], [[B4]], [[C15]]
+; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
+; CHECK-DAG: vperm [[R2:[0-9]+]], [[LD3]], [[LD4]], [[MASK2]]
 ; CHECK-DAG: vaddfp {{[0-9]+}}, [[R1]], [[CNST]]
 ; CHECK-DAG: vaddfp {{[0-9]+}}, [[R2]], [[CNST]]
 ; CHECK: blr
diff --git a/test/CodeGen/PowerPC/unal4-std.ll b/test/CodeGen/PowerPC/unal4-std.ll
index e91109911161..de2a68c813b8 100644
--- a/test/CodeGen/PowerPC/unal4-std.ll
+++ b/test/CodeGen/PowerPC/unal4-std.ll
@@ -3,17 +3,10 @@
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
-define fastcc void @copy_to_conceal() #0 {
+define void @copy_to_conceal(<8 x i16>* %inp) #0 {
 entry:
-  br i1 undef, label %if.then, label %if.end210
-
-if.then:                                          ; preds = %entry
-  br label %vector.body.i
-
-vector.body.i:                                    ; preds = %vector.body.i, %if.then
-  %index.i = phi i64 [ 0, %vector.body.i ], [ 0, %if.then ]
-  store <8 x i16> zeroinitializer, <8 x i16>* undef, align 2
-  br label %vector.body.i
+  store <8 x i16> zeroinitializer, <8 x i16>* %inp, align 2
+  br label %if.end210
 
 if.end210:                                        ; preds = %entry
   ret void
diff --git a/test/CodeGen/PowerPC/unwind-dw2-g.ll b/test/CodeGen/PowerPC/unwind-dw2-g.ll
index e44da85f5b36..59b68342bd9a 100644
--- a/test/CodeGen/PowerPC/unwind-dw2-g.ll
+++ b/test/CodeGen/PowerPC/unwind-dw2-g.ll
@@ -21,11 +21,10 @@ attributes #0 = { nounwind }
 !llvm.dbg.cu = !{!0}
 !llvm.module.flags = !{!8, !11}
 
-!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2)
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4", isOptimized: false, emissionKind: FullDebug, file: !1, enums: !2, retainedTypes: !2, globals: !2, imports: !2)
 !1 = !DIFile(filename: "/tmp/unwind-dw2.c", directory: "/tmp")
 !2 = !{}
-!3 = !{!4}
-!4 = distinct !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, variables: !2)
+!4 = distinct !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, unit: !0, scopeLine: 1, file: !1, scope: !5, type: !6, variables: !2)
 !5 = !DIFile(filename: "/tmp/unwind-dw2.c", directory: "/tmp")
 !6 = !DISubroutineType(types: !7)
 !7 = !{null}
diff --git a/test/CodeGen/PowerPC/vec_abs.ll b/test/CodeGen/PowerPC/vec_abs.ll
new file mode 100644
index 000000000000..8fa26a614b96
--- /dev/null
+++ b/test/CodeGen/PowerPC/vec_abs.ll
@@ -0,0 +1,80 @@
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64le \
+; RUN:          -mattr=+altivec -mattr=+vsx |  FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64le \
+; RUN:          -mattr=+altivec -mattr=-vsx |  FileCheck %s \
+; RUN:          -check-prefix=CHECK-NOVSX
+
+define <4 x float> @test_float(<4 x float> %aa) #0 {
+
+; CHECK-LABEL: test_float
+; CHECK-NOVSX-LABEL: test_float
+; CHECK-NOVSX-LABEL: test_float
+
+  entry:
+    %0 = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %aa) #2
+    ret <4 x float> %0
+}
+; Function Attrs: nounwind readnone
+declare <4 x float> @llvm.fabs.v4f32(<4 x float>) #1
+
+; CHECK: xvabssp
+; CHECK: blr
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: blr
+
+define <4 x float> @test2_float(<4 x float> %aa) #0 {
+
+; CHECK-LABEL: test2_float
+; CHECK-NOVSX-LABEL: test2_float
+
+  entry:
+    %0 = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %aa) #2
+    %sub = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00,
+                             float -0.000000e+00, float -0.000000e+00>, %0
+    ret <4 x float> %sub
+}
+
+; CHECK: xvnabssp
+; CHECK: blr
+; CHECK-NOVSX: vspltisb
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: vsubfp
+; CHECK-NOVSX: blr
+
+define <2 x double> @test_double(<2 x double> %aa) #0 {
+
+; CHECK-LABEL: test_double
+; CHECK-NOVSX-LABEL: test_double
+
+  entry:
+    %0 = tail call <2 x double> @llvm.fabs.v2f64(<2 x double> %aa) #2
+    ret <2 x double> %0
+}
+
+; Function Attrs: nounwind readnone
+declare <2 x double> @llvm.fabs.v2f64(<2 x double>) #1
+
+; CHECK: xvabsdp
+; CHECK: blr
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: fabs
+; CHECK-NOVSX: blr
+
+define <2 x double> @foo(<2 x double> %aa) #0 {
+  entry:
+    %0 = tail call <2 x double> @llvm.fabs.v2f64(<2 x double> %aa) #2
+    %sub = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %0
+    ret <2 x double> %sub
+}
+
+; CHECK: xvnabsdp
+; CHECK: blr
+; CHECK-NOVSX: fnabs
+; CHECK-NOVSX: fnabs
+; CHECK-NOVSX: blr
diff --git a/test/CodeGen/PowerPC/vec_cmp.ll b/test/CodeGen/PowerPC/vec_cmp.ll
index 516b2dd58b99..7b228bffc386 100644
--- a/test/CodeGen/PowerPC/vec_cmp.ll
+++ b/test/CodeGen/PowerPC/vec_cmp.ll
@@ -24,7 +24,7 @@ define <4 x i8> @v4si8_cmp(<4 x i8> %x, <4 x i8> %y) nounwind readnone {
   ret <4 x i8> %sext
 }
 ; CHECK-LABEL: v4si8_cmp:
-; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
 define <8 x i8> @v8si8_cmp(<8 x i8> %x, <8 x i8> %y) nounwind readnone {
@@ -33,7 +33,7 @@ define <8 x i8> @v8si8_cmp(<8 x i8> %x, <8 x i8> %y) nounwind readnone {
   ret <8 x i8> %sext
 }
 ; CHECK-LABEL: v8si8_cmp:
-; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
 ; Additional tests for v16i8 since it is a altivec native type
@@ -158,7 +158,7 @@ define <4 x i16> @v4si16_cmp(<4 x i16> %x, <4 x i16> %y) nounwind readnone {
   ret <4 x i16> %sext
 }
 ; CHECK-LABEL: v4si16_cmp:
-; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
+; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
 ; Additional tests for v8i16 since it is an altivec native type
diff --git a/test/CodeGen/PowerPC/vec_fneg.ll b/test/CodeGen/PowerPC/vec_fneg.ll
index d6f6def64ea2..117336dc6a46 100644
--- a/test/CodeGen/PowerPC/vec_fneg.ll
+++ b/test/CodeGen/PowerPC/vec_fneg.ll
@@ -1,8 +1,37 @@
-; RUN: llc < %s -march=ppc32 -mcpu=g5 | grep vsubfp
+; RUN: llc < %s -march=ppc32 -mcpu=g5 | FileCheck %s -check-prefix=CHECK-NOVSX
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64le \
+; RUN:          -mattr=+altivec -mattr=+vsx |  FileCheck %s
+; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64le \
+; RUN:          -mattr=+altivec -mattr=-vsx |  FileCheck %s \
+; RUN:          -check-prefix=CHECK-NOVSX
 
-define void @t(<4 x float>* %A) {
+define void @test_float(<4 x float>* %A) {
+; CHECK-LABEL: test_float
+; CHECK-NOVSX-LABEL: test_float
 	%tmp2 = load <4 x float>, <4 x float>* %A
 	%tmp3 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp2
 	store <4 x float> %tmp3, <4 x float>* %A
 	ret void
+
+; CHECK: xvnegsp
+; CHECK: blr
+; CHECK-NOVSX: vsubfp
+; CHECK-NOVSX: blr
+
+}
+
+define void @test_double(<2 x double>* %A) {
+; CHECK-LABEL: test_double
+; CHECK-NOVSX-LABEL: test_double
+	%tmp2 = load <2 x double>, <2 x double>* %A
+	%tmp3 = fsub <2 x double> < double -0.000000e+00, double -0.000000e+00 >, %tmp2
+	store <2 x double> %tmp3, <2 x double>* %A
+	ret void
+
+; CHECK: xvnegdp
+; CHECK: blr
+; CHECK-NOVSX: fneg
+; CHECK-NOVSX: fneg
+; CHECK-NOVSX: blr
+
 }
diff --git a/test/CodeGen/PowerPC/vrsave-spill.ll b/test/CodeGen/PowerPC/vrsave-spill.ll
index c73206d8fc86..ceb787d05c9f 100644
--- a/test/CodeGen/PowerPC/vrsave-spill.ll
+++ b/test/CodeGen/PowerPC/vrsave-spill.ll
@@ -10,8 +10,8 @@ entry:
   br label %return
 
 ; CHECK: @foo
-; CHECK: mfspr r{{[0-9]+}}, 256
-; CHECK: mtspr 256, r{{[0-9]+}}
+; CHECK: mfvrsave r{{[0-9]+}}
+; CHECK: mtvrsave r{{[0-9]+}}
 
 return:                                           ; preds = %entry
   ret <4 x float> %d
diff --git a/test/CodeGen/PowerPC/vsx-fma-m.ll b/test/CodeGen/PowerPC/vsx-fma-m.ll
index 4f556b6b79c2..a94d955d35d4 100644
--- a/test/CodeGen/PowerPC/vsx-fma-m.ll
+++ b/test/CodeGen/PowerPC/vsx-fma-m.ll
@@ -1,5 +1,6 @@
 ; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s
 ; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 | FileCheck -check-prefix=CHECK-FISL %s
+; XFAIL: *
 
 ; Also run with -schedule-ppc-vsx-fma-mutation-early as a stress test for the
 ; live-interval-updating logic.
diff --git a/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll b/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll
index e3f4001aa1d3..06636f24f97c 100644
--- a/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll
+++ b/test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll
@@ -3,15 +3,15 @@ target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-unknown-linux-gnu"
 
 ; Function Attrs: nounwind
-define void @acosh_float8() #0 {
+define void @acosh_float8(<4 x i32> %v1, <4 x i32> %v2) #0 {
 entry:
   br i1 undef, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   %0 = tail call <4 x float> @llvm.fmuladd.v4f32(<4 x float> undef, <4 x float> <float 0x3FE62E4200000000, float 0x3FE62E4200000000, float 0x3FE62E4200000000, float 0x3FE62E4200000000>, <4 x float> undef) #0
   %astype.i.i.74.i = bitcast <4 x float> %0 to <4 x i32>
-  %and.i.i.76.i = and <4 x i32> %astype.i.i.74.i, undef
-  %or.i.i.79.i = or <4 x i32> %and.i.i.76.i, undef
+  %and.i.i.76.i = and <4 x i32> %astype.i.i.74.i, %v1
+  %or.i.i.79.i = or <4 x i32> %and.i.i.76.i, %v2
   %astype5.i.i.80.i = bitcast <4 x i32> %or.i.i.79.i to <4 x float>
   %1 = shufflevector <4 x float> %astype5.i.i.80.i, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
   %2 = shufflevector <8 x float> undef, <8 x float> %1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
diff --git a/test/CodeGen/PowerPC/vsx-fma-sp.ll b/test/CodeGen/PowerPC/vsx-fma-sp.ll
index b4dd2e1627c4..1a1f54ec30a5 100644
--- a/test/CodeGen/PowerPC/vsx-fma-sp.ll
+++ b/test/CodeGen/PowerPC/vsx-fma-sp.ll
@@ -1,5 +1,7 @@
 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s
 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx -fast-isel -O0 | FileCheck -check-prefix=CHECK-FISL %s
+; XFAIL: *
+
 define void @test1sp(float %a, float %b, float %c, float %e, float* nocapture %d) #0 {
 entry:
   %0 = tail call float @llvm.fma.f32(float %b, float %c, float %a)
diff --git a/test/CodeGen/PowerPC/vsx-infl-copy1.ll b/test/CodeGen/PowerPC/vsx-infl-copy1.ll
index 531e3ad2d87c..a518e1b890fb 100644
--- a/test/CodeGen/PowerPC/vsx-infl-copy1.ll
+++ b/test/CodeGen/PowerPC/vsx-infl-copy1.ll
@@ -6,7 +6,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 @uc = external global [1024 x i32], align 4
 
 ; Function Attrs: noinline nounwind
-define void @_Z8example9Pj() #0 {
+define <4 x i32> @_Z8example9Pj(<4 x i32>* %addr1, i64 %input1, i64 %input2) #0 {
 entry:
   br label %vector.body
 
@@ -31,7 +31,7 @@ vector.body:                                      ; preds = %vector.body, %entry
   %0 = getelementptr [1024 x i32], [1024 x i32]* @ub, i64 0, i64 %.sum82
   %1 = bitcast i32* %0 to <4 x i32>*
   %wide.load36 = load <4 x i32>, <4 x i32>* %1, align 4
-  %wide.load37 = load <4 x i32>, <4 x i32>* undef, align 4
+  %wide.load37 = load <4 x i32>, <4 x i32>* %addr1, align 4
   %.sum84 = add i64 %index, 32
   %2 = getelementptr [1024 x i32], [1024 x i32]* @ub, i64 0, i64 %.sum84
   %3 = bitcast i32* %2 to <4 x i32>*
@@ -40,7 +40,7 @@ vector.body:                                      ; preds = %vector.body, %entry
   %4 = getelementptr [1024 x i32], [1024 x i32]* @ub, i64 0, i64 %.sum85
   %5 = bitcast i32* %4 to <4 x i32>*
   %wide.load39 = load <4 x i32>, <4 x i32>* %5, align 4
-  %6 = getelementptr [1024 x i32], [1024 x i32]* @ub, i64 0, i64 undef
+  %6 = getelementptr [1024 x i32], [1024 x i32]* @ub, i64 0, i64 %input1
   %7 = bitcast i32* %6 to <4 x i32>*
   %wide.load40 = load <4 x i32>, <4 x i32>* %7, align 4
   %.sum87 = add i64 %index, 44
@@ -66,7 +66,7 @@ vector.body:                                      ; preds = %vector.body, %entry
   %18 = getelementptr [1024 x i32], [1024 x i32]* @uc, i64 0, i64 %.sum95
   %19 = bitcast i32* %18 to <4 x i32>*
   %wide.load47 = load <4 x i32>, <4 x i32>* %19, align 4
-  %20 = getelementptr [1024 x i32], [1024 x i32]* @uc, i64 0, i64 undef
+  %20 = getelementptr [1024 x i32], [1024 x i32]* @uc, i64 0, i64 %input2
   %21 = bitcast i32* %20 to <4 x i32>*
   %wide.load48 = load <4 x i32>, <4 x i32>* %21, align 4
   %.sum97 = add i64 %index, 28
@@ -126,7 +126,16 @@ middle.block:                                     ; preds = %vector.body
   %.lcssa103 = phi <4 x i32> [ %45, %vector.body ]
   %.lcssa102 = phi <4 x i32> [ %44, %vector.body ]
   %.lcssa = phi <4 x i32> [ %43, %vector.body ]
-  ret void
+  %54 = add <4 x i32> %.lcssa112, %.lcssa111
+  %55 = add <4 x i32> %.lcssa110, %54
+  %56 = add <4 x i32> %.lcssa109, %55
+  %57 = add <4 x i32> %.lcssa108, %56
+  %58 = add <4 x i32> %.lcssa107, %57
+  %59 = add <4 x i32> %.lcssa106, %58
+  %60 = add <4 x i32> %.lcssa105, %59
+  %61 = add <4 x i32> %.lcssa103, %60
+  %62 = add <4 x i32> %.lcssa102, %61
+  ret <4 x i32> %62
 }
 
 attributes #0 = { noinline nounwind }
diff --git a/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll b/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll
index d6940e46df37..ce8a9bb4e3fa 100644
--- a/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll
+++ b/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll
@@ -1,6 +1,4 @@
-; RUN: llc -mcpu=pwr8 -mattr=+vsx -O2 -mtriple=powerpc64le-unknown-linux-gnu < %s > %t
-; RUN: grep lxvd2x < %t | count 18
-; RUN: grep stxvd2x < %t | count 18
+; RUN: llc -mcpu=pwr8 -mattr=+vsx -O2 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
 
 @vf = global <4 x float> <float -1.500000e+00, float 2.500000e+00, float -3.500000e+00, float 4.500000e+00>, align 16
 @vd = global <2 x double> <double 3.500000e+00, double -7.500000e+00>, align 16
@@ -18,150 +16,60 @@
 define void @test1() {
 entry:
 ; CHECK-LABEL: test1
-  %__a.addr.i31 = alloca i32, align 4
-  %__b.addr.i32 = alloca <4 x i32>*, align 8
-  %__a.addr.i29 = alloca i32, align 4
-  %__b.addr.i30 = alloca <4 x float>*, align 8
-  %__a.addr.i27 = alloca i32, align 4
-  %__b.addr.i28 = alloca <2 x i64>*, align 8
-  %__a.addr.i25 = alloca i32, align 4
-  %__b.addr.i26 = alloca <2 x i64>*, align 8
-  %__a.addr.i23 = alloca i32, align 4
-  %__b.addr.i24 = alloca <2 x double>*, align 8
-  %__a.addr.i20 = alloca <4 x i32>, align 16
-  %__b.addr.i21 = alloca i32, align 4
-  %__c.addr.i22 = alloca <4 x i32>*, align 8
-  %__a.addr.i17 = alloca <4 x i32>, align 16
-  %__b.addr.i18 = alloca i32, align 4
-  %__c.addr.i19 = alloca <4 x i32>*, align 8
-  %__a.addr.i14 = alloca <4 x float>, align 16
-  %__b.addr.i15 = alloca i32, align 4
-  %__c.addr.i16 = alloca <4 x float>*, align 8
-  %__a.addr.i11 = alloca <2 x i64>, align 16
-  %__b.addr.i12 = alloca i32, align 4
-  %__c.addr.i13 = alloca <2 x i64>*, align 8
-  %__a.addr.i8 = alloca <2 x i64>, align 16
-  %__b.addr.i9 = alloca i32, align 4
-  %__c.addr.i10 = alloca <2 x i64>*, align 8
-  %__a.addr.i6 = alloca <2 x double>, align 16
-  %__b.addr.i7 = alloca i32, align 4
-  %__c.addr.i = alloca <2 x double>*, align 8
-  %__a.addr.i = alloca i32, align 4
-  %__b.addr.i = alloca <4 x i32>*, align 8
-  store i32 0, i32* %__a.addr.i, align 4
-  store <4 x i32>* @vsi, <4 x i32>** %__b.addr.i, align 8
-  %0 = load i32, i32* %__a.addr.i, align 4
-  %1 = load <4 x i32>*, <4 x i32>** %__b.addr.i, align 8
-  %2 = bitcast <4 x i32>* %1 to i8*
-  %3 = getelementptr i8, i8* %2, i32 %0
-  %4 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %3)
-  store <4 x i32> %4, <4 x i32>* @res_vsi, align 16
-  store i32 0, i32* %__a.addr.i31, align 4
-  store <4 x i32>* @vui, <4 x i32>** %__b.addr.i32, align 8
-  %5 = load i32, i32* %__a.addr.i31, align 4
-  %6 = load <4 x i32>*, <4 x i32>** %__b.addr.i32, align 8
-  %7 = bitcast <4 x i32>* %6 to i8*
-  %8 = getelementptr i8, i8* %7, i32 %5
-  %9 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %8)
-  store <4 x i32> %9, <4 x i32>* @res_vui, align 16
-  store i32 0, i32* %__a.addr.i29, align 4
-  store <4 x float>* @vf, <4 x float>** %__b.addr.i30, align 8
-  %10 = load i32, i32* %__a.addr.i29, align 4
-  %11 = load <4 x float>*, <4 x float>** %__b.addr.i30, align 8
-  %12 = bitcast <4 x float>* %11 to i8*
-  %13 = getelementptr i8, i8* %12, i32 %10
-  %14 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %13)
-  %15 = bitcast <4 x i32> %14 to <4 x float>
-  store <4 x float> %15, <4 x float>* @res_vf, align 16
-  store i32 0, i32* %__a.addr.i27, align 4
-  store <2 x i64>* @vsll, <2 x i64>** %__b.addr.i28, align 8
-  %16 = load i32, i32* %__a.addr.i27, align 4
-  %17 = load <2 x i64>*, <2 x i64>** %__b.addr.i28, align 8
-  %18 = bitcast <2 x i64>* %17 to i8*
-  %19 = getelementptr i8, i8* %18, i32 %16
-  %20 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %19)
-  %21 = bitcast <2 x double> %20 to <2 x i64>
-  store <2 x i64> %21, <2 x i64>* @res_vsll, align 16
-  store i32 0, i32* %__a.addr.i25, align 4
-  store <2 x i64>* @vull, <2 x i64>** %__b.addr.i26, align 8
-  %22 = load i32, i32* %__a.addr.i25, align 4
-  %23 = load <2 x i64>*, <2 x i64>** %__b.addr.i26, align 8
-  %24 = bitcast <2 x i64>* %23 to i8*
-  %25 = getelementptr i8, i8* %24, i32 %22
-  %26 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %25)
-  %27 = bitcast <2 x double> %26 to <2 x i64>
-  store <2 x i64> %27, <2 x i64>* @res_vull, align 16
-  store i32 0, i32* %__a.addr.i23, align 4
-  store <2 x double>* @vd, <2 x double>** %__b.addr.i24, align 8
-  %28 = load i32, i32* %__a.addr.i23, align 4
-  %29 = load <2 x double>*, <2 x double>** %__b.addr.i24, align 8
-  %30 = bitcast <2 x double>* %29 to i8*
-  %31 = getelementptr i8, i8* %30, i32 %28
-  %32 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %31)
-  store <2 x double> %32, <2 x double>* @res_vd, align 16
-  %33 = load <4 x i32>, <4 x i32>* @vsi, align 16
-  store <4 x i32> %33, <4 x i32>* %__a.addr.i20, align 16
-  store i32 0, i32* %__b.addr.i21, align 4
-  store <4 x i32>* @res_vsi, <4 x i32>** %__c.addr.i22, align 8
-  %34 = load <4 x i32>, <4 x i32>* %__a.addr.i20, align 16
-  %35 = load i32, i32* %__b.addr.i21, align 4
-  %36 = load <4 x i32>*, <4 x i32>** %__c.addr.i22, align 8
-  %37 = bitcast <4 x i32>* %36 to i8*
-  %38 = getelementptr i8, i8* %37, i32 %35
-  call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %34, i8* %38)
-  %39 = load <4 x i32>, <4 x i32>* @vui, align 16
-  store <4 x i32> %39, <4 x i32>* %__a.addr.i17, align 16
-  store i32 0, i32* %__b.addr.i18, align 4
-  store <4 x i32>* @res_vui, <4 x i32>** %__c.addr.i19, align 8
-  %40 = load <4 x i32>, <4 x i32>* %__a.addr.i17, align 16
-  %41 = load i32, i32* %__b.addr.i18, align 4
-  %42 = load <4 x i32>*, <4 x i32>** %__c.addr.i19, align 8
-  %43 = bitcast <4 x i32>* %42 to i8*
-  %44 = getelementptr i8, i8* %43, i32 %41
-  call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %40, i8* %44)
-  %45 = load <4 x float>, <4 x float>* @vf, align 16
-  store <4 x float> %45, <4 x float>* %__a.addr.i14, align 16
-  store i32 0, i32* %__b.addr.i15, align 4
-  store <4 x float>* @res_vf, <4 x float>** %__c.addr.i16, align 8
-  %46 = load <4 x float>, <4 x float>* %__a.addr.i14, align 16
-  %47 = bitcast <4 x float> %46 to <4 x i32>
-  %48 = load i32, i32* %__b.addr.i15, align 4
-  %49 = load <4 x float>*, <4 x float>** %__c.addr.i16, align 8
-  %50 = bitcast <4 x float>* %49 to i8*
-  %51 = getelementptr i8, i8* %50, i32 %48
-  call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %47, i8* %51) #1
-  %52 = load <2 x i64>, <2 x i64>* @vsll, align 16
-  store <2 x i64> %52, <2 x i64>* %__a.addr.i11, align 16
-  store i32 0, i32* %__b.addr.i12, align 4
-  store <2 x i64>* @res_vsll, <2 x i64>** %__c.addr.i13, align 8
-  %53 = load <2 x i64>, <2 x i64>* %__a.addr.i11, align 16
-  %54 = bitcast <2 x i64> %53 to <2 x double>
-  %55 = load i32, i32* %__b.addr.i12, align 4
-  %56 = load <2 x i64>*, <2 x i64>** %__c.addr.i13, align 8
-  %57 = bitcast <2 x i64>* %56 to i8*
-  %58 = getelementptr i8, i8* %57, i32 %55
-  call void @llvm.ppc.vsx.stxvd2x(<2 x double> %54, i8* %58)
-  %59 = load <2 x i64>, <2 x i64>* @vull, align 16
-  store <2 x i64> %59, <2 x i64>* %__a.addr.i8, align 16
-  store i32 0, i32* %__b.addr.i9, align 4
-  store <2 x i64>* @res_vull, <2 x i64>** %__c.addr.i10, align 8
-  %60 = load <2 x i64>, <2 x i64>* %__a.addr.i8, align 16
-  %61 = bitcast <2 x i64> %60 to <2 x double>
-  %62 = load i32, i32* %__b.addr.i9, align 4
-  %63 = load <2 x i64>*, <2 x i64>** %__c.addr.i10, align 8
-  %64 = bitcast <2 x i64>* %63 to i8*
-  %65 = getelementptr i8, i8* %64, i32 %62
-  call void @llvm.ppc.vsx.stxvd2x(<2 x double> %61, i8* %65)
-  %66 = load <2 x double>, <2 x double>* @vd, align 16
-  store <2 x double> %66, <2 x double>* %__a.addr.i6, align 16
-  store i32 0, i32* %__b.addr.i7, align 4
-  store <2 x double>* @res_vd, <2 x double>** %__c.addr.i, align 8
-  %67 = load <2 x double>, <2 x double>* %__a.addr.i6, align 16
-  %68 = load i32, i32* %__b.addr.i7, align 4
-  %69 = load <2 x double>*, <2 x double>** %__c.addr.i, align 8
-  %70 = bitcast <2 x double>* %69 to i8*
-  %71 = getelementptr i8, i8* %70, i32 %68
-  call void @llvm.ppc.vsx.stxvd2x(<2 x double> %67, i8* %71)
+; CHECK: lxvd2x
+  %0 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* bitcast (<4 x i32>* @vsi to i8*))
+; CHECK: stxvd2x
+  store <4 x i32> %0, <4 x i32>* @res_vsi, align 16
+; CHECK: lxvd2x
+  %1 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* bitcast (<4 x i32>* @vui to i8*))
+; CHECK: stxvd2x
+  store <4 x i32> %1, <4 x i32>* @res_vui, align 16
+; CHECK: lxvd2x
+  %2 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* bitcast (<4 x float>* @vf to i8*))
+  %3 = bitcast <4 x i32> %2 to <4 x float>
+; CHECK: stxvd2x
+  store <4 x float> %3, <4 x float>* @res_vf, align 16
+; CHECK: lxvd2x
+  %4 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* bitcast (<2 x i64>* @vsll to i8*))
+  %5 = bitcast <2 x double> %4 to <2 x i64>
+; CHECK: stxvd2x
+  store <2 x i64> %5, <2 x i64>* @res_vsll, align 16
+; CHECK: lxvd2x
+  %6 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* bitcast (<2 x i64>* @vull to i8*))
+  %7 = bitcast <2 x double> %6 to <2 x i64>
+; CHECK: stxvd2x
+  store <2 x i64> %7, <2 x i64>* @res_vull, align 16
+; CHECK: lxvd2x
+  %8 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* bitcast (<2 x double>* @vd to i8*))
+; CHECK: stxvd2x
+  store <2 x double> %8, <2 x double>* @res_vd, align 16
+; CHECK: lxvd2x
+  %9 = load <4 x i32>, <4 x i32>* @vsi, align 16
+; CHECK: stxvd2x
+  call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %9, i8* bitcast (<4 x i32>* @res_vsi to i8*))
+; CHECK: lxvd2x
+  %10 = load <4 x i32>, <4 x i32>* @vui, align 16
+; CHECK: stxvd2x
+  call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %10, i8* bitcast (<4 x i32>* @res_vui to i8*))
+; CHECK: lxvd2x
+  %11 = load <4 x float>, <4 x float>* @vf, align 16
+  %12 = bitcast <4 x float> %11 to <4 x i32>
+; CHECK: stxvd2x
+  call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %12, i8* bitcast (<4 x float>* @res_vf to i8*))
+; CHECK: lxvd2x
+  %13 = load <2 x i64>, <2 x i64>* @vsll, align 16
+  %14 = bitcast <2 x i64> %13 to <2 x double>
+; CHECK: stxvd2x
+  call void @llvm.ppc.vsx.stxvd2x(<2 x double> %14, i8* bitcast (<2 x i64>* @res_vsll to i8*))
+; CHECK: lxvd2x
+  %15 = load <2 x i64>, <2 x i64>* @vull, align 16
+  %16 = bitcast <2 x i64> %15 to <2 x double>
+; CHECK: stxvd2x
+  call void @llvm.ppc.vsx.stxvd2x(<2 x double> %16, i8* bitcast (<2 x i64>* @res_vull to i8*))
+; CHECK: lxvd2x
+  %17 = load <2 x double>, <2 x double>* @vd, align 16
+; CHECK: stxvd2x
+  call void @llvm.ppc.vsx.stxvd2x(<2 x double> %17, i8* bitcast (<2 x double>* @res_vd to i8*))
   ret void
 }
 
diff --git a/test/CodeGen/PowerPC/vsx-word-splats.ll b/test/CodeGen/PowerPC/vsx-word-splats.ll
new file mode 100644
index 000000000000..5632011da35d
--- /dev/null
+++ b/test/CodeGen/PowerPC/vsx-word-splats.ll
@@ -0,0 +1,147 @@
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK-BE
+
+define <4 x float> @test0f(<4 x float> %a) {
+entry:
+  %0 = bitcast <4 x float> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  %2 = bitcast <16 x i8> %1 to <4 x float>
+  ret <4 x float> %2
+; CHECK-LABEL: test0f
+; CHECK xxspltw: 34, 34, 3
+; CHECK-BE-LABEL: test0f
+; CHECK-BE: xxspltw 34, 34, 0
+}
+
+define <4 x float> @test1f(<4 x float> %a) {
+entry:
+  %0 = bitcast <4 x float> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
+  %2 = bitcast <16 x i8> %1 to <4 x float>
+  ret <4 x float> %2
+; CHECK-LABEL: test1f
+; CHECK xxspltw: 34, 34, 2
+; CHECK-BE-LABEL: test1f
+; CHECK-BE: xxspltw 34, 34, 1
+}
+
+define <4 x float> @test2f(<4 x float> %a) {
+entry:
+  %0 = bitcast <4 x float> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>
+  %2 = bitcast <16 x i8> %1 to <4 x float>
+  ret <4 x float> %2
+; CHECK-LABEL: test2f
+; CHECK xxspltw: 34, 34, 1
+; CHECK-LABEL: test2f
+; CHECK-BE: xxspltw 34, 34, 2
+}
+
+define <4 x float> @test3f(<4 x float> %a) {
+entry:
+  %0 = bitcast <4 x float> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
+  %2 = bitcast <16 x i8> %1 to <4 x float>
+  ret <4 x float> %2
+; CHECK-LABEL: test3f
+; CHECK xxspltw: 34, 34, 0
+; CHECK-BE-LABEL: test3f
+; CHECK-BE: xxspltw 34, 34, 3
+}
+
+define <4 x i32> @test0si(<4 x i32> %a) {
+entry:
+  %0 = bitcast <4 x i32> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  %2 = bitcast <16 x i8> %1 to <4 x i32>
+  ret <4 x i32> %2
+; CHECK-LABEL: test0si
+; CHECK xxspltw: 34, 34, 3
+; CHECK-BE-LABEL: test0si
+; CHECK-BE: xxspltw 34, 34, 0
+}
+
+define <4 x i32> @test1si(<4 x i32> %a) {
+entry:
+  %0 = bitcast <4 x i32> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
+  %2 = bitcast <16 x i8> %1 to <4 x i32>
+  ret <4 x i32> %2
+; CHECK-LABEL: test1si
+; CHECK xxspltw: 34, 34, 2
+; CHECK-BE-LABEL: test1si
+; CHECK-BE: xxspltw 34, 34, 1
+}
+
+define <4 x i32> @test2si(<4 x i32> %a) {
+entry:
+  %0 = bitcast <4 x i32> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>
+  %2 = bitcast <16 x i8> %1 to <4 x i32>
+  ret <4 x i32> %2
+; CHECK-LABEL: test2si
+; CHECK xxspltw: 34, 34, 1
+; CHECK-BE-LABEL: test2si
+; CHECK-BE: xxspltw 34, 34, 2
+}
+
+define <4 x i32> @test3si(<4 x i32> %a) {
+entry:
+  %0 = bitcast <4 x i32> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
+  %2 = bitcast <16 x i8> %1 to <4 x i32>
+  ret <4 x i32> %2
+; CHECK-LABEL: test3si
+; CHECK xxspltw: 34, 34, 0
+; CHECK-BE-LABEL: test3si
+; CHECK-BE: xxspltw 34, 34, 3
+}
+
+define <4 x i32> @test0ui(<4 x i32> %a) {
+entry:
+  %0 = bitcast <4 x i32> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  %2 = bitcast <16 x i8> %1 to <4 x i32>
+  ret <4 x i32> %2
+; CHECK-LABEL: test0ui
+; CHECK xxspltw: 34, 34, 3
+; CHECK-BE-LABEL: test0ui
+; CHECK-BE: xxspltw 34, 34, 0
+}
+
+define <4 x i32> @test1ui(<4 x i32> %a) {
+entry:
+  %0 = bitcast <4 x i32> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
+  %2 = bitcast <16 x i8> %1 to <4 x i32>
+  ret <4 x i32> %2
+; CHECK-LABEL: test1ui
+; CHECK xxspltw: 34, 34, 2
+; CHECK-BE-LABEL: test1ui
+; CHECK-BE: xxspltw 34, 34, 1
+}
+
+define <4 x i32> @test2ui(<4 x i32> %a) {
+entry:
+  %0 = bitcast <4 x i32> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>
+  %2 = bitcast <16 x i8> %1 to <4 x i32>
+  ret <4 x i32> %2
+; CHECK-LABEL: test2ui
+; CHECK xxspltw: 34, 34, 1
+; CHECK-BE-LABEL: test2ui
+; CHECK-BE: xxspltw 34, 34, 2
+}
+
+define <4 x i32> @test3ui(<4 x i32> %a) {
+entry:
+  %0 = bitcast <4 x i32> %a to <16 x i8>
+  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
+  %2 = bitcast <16 x i8> %1 to <4 x i32>
+  ret <4 x i32> %2
+; CHECK-LABEL: test3ui
+; CHECK xxspltw: 34, 34, 0
+; CHECK-BE-LABEL: test3ui
+; CHECK-BE: xxspltw 34, 34, 3
+}
diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll
index b2eefb666760..9b65649978d3 100644
--- a/test/CodeGen/PowerPC/vsx.ll
+++ b/test/CodeGen/PowerPC/vsx.ll
@@ -1144,62 +1144,67 @@ define <2 x double> @test68(<2 x i32> %a) {
   ret <2 x double> %w
 
 ; CHECK-LABEL: @test68
-; CHECK: xxsldwi [[V1:[0-9]+]], 34, 34, 1
+; CHECK: xxmrghw [[V1:[0-9]+]]
 ; CHECK: xvcvsxwdp 34, [[V1]]
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test68
-; CHECK-LE: xxsldwi [[V1:[0-9]+]], 34, 34, 1
+; CHECK-LE: xxmrglw [[V1:[0-9]+]], 34, 34
 ; CHECK-LE: xvcvsxwdp 34, [[V1]]
 ; CHECK-LE: blr
 }
 
+; This gets scalarized so the code isn't great
 define <2 x double> @test69(<2 x i16> %a) {
   %w = sitofp <2 x i16> %a to <2 x double>
   ret <2 x double> %w
 
 ; CHECK-LABEL: @test69
-; CHECK: vspltisw [[V1:[0-9]+]], 8
-; CHECK: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
-; CHECK: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
-; CHECK: vsraw {{[0-9]+}}, [[V3]], [[V2]]
-; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
-; CHECK: xvcvsxwdp 34, [[V4]]
+; CHECK-DAG: lfiwax
+; CHECK-DAG: lfiwax
+; CHECK-DAG: xscvsxddp
+; CHECK-DAG: xscvsxddp
+; CHECK: xxmrghd
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test69
-; CHECK-LE: vspltisw [[V1:[0-9]+]], 8
-; CHECK-LE: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
-; CHECK-LE: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
-; CHECK-LE: vsraw {{[0-9]+}}, [[V3]], [[V2]]
-; CHECK-LE: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
-; CHECK-LE: xvcvsxwdp 34, [[V4]]
+; CHECK-LE: mfvsrd
+; CHECK-LE: mtvsrwa
+; CHECK-LE: mtvsrwa
+; CHECK-LE: xscvsxddp
+; CHECK-LE: xscvsxddp
+; CHECK-LE: xxspltd
+; CHECK-LE: xxspltd
+; CHECK-LE: xxmrgld
 ; CHECK-LE: blr
 }
 
+; This gets scalarized so the code isn't great
 define <2 x double> @test70(<2 x i8> %a) {
   %w = sitofp <2 x i8> %a to <2 x double>
   ret <2 x double> %w
 
 ; CHECK-LABEL: @test70
-; CHECK: vspltisw [[V1:[0-9]+]], 12
-; CHECK: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
-; CHECK: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
-; CHECK: vsraw {{[0-9]+}}, [[V3]], [[V2]]
-; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
-; CHECK: xvcvsxwdp 34, [[V4]]
+; CHECK-DAG: lfiwax
+; CHECK-DAG: lfiwax
+; CHECK-DAG: xscvsxddp
+; CHECK-DAG: xscvsxddp
+; CHECK: xxmrghd
 ; CHECK: blr
 
 ; CHECK-LE-LABEL: @test70
-; CHECK-LE: vspltisw [[V1:[0-9]+]], 12
-; CHECK-LE: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
-; CHECK-LE: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
-; CHECK-LE: vsraw {{[0-9]+}}, [[V3]], [[V2]]
-; CHECK-LE: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
-; CHECK-LE: xvcvsxwdp 34, [[V4]]
+; CHECK-LE: mfvsrd
+; CHECK-LE: mtvsrwa
+; CHECK-LE: mtvsrwa
+; CHECK-LE: xscvsxddp
+; CHECK-LE: xscvsxddp
+; CHECK-LE: xxspltd
+; CHECK-LE: xxspltd
+; CHECK-LE: xxmrgld
 ; CHECK-LE: blr
 }
 
+; This gets scalarized so the code isn't great
 define <2 x i32> @test80(i32 %v) {
   %b1 = insertelement <2 x i32> undef, i32 %v, i32 0
   %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer
@@ -1207,31 +1212,38 @@ define <2 x i32> @test80(i32 %v) {
   ret <2 x i32> %i
 
 ; CHECK-REG-LABEL: @test80
-; CHECK-REG-DAG: addi [[R1:[0-9]+]], 3, 3
-; CHECK-REG-DAG: addi [[R2:[0-9]+]], 1, -16
-; CHECK-REG-DAG: addi [[R3:[0-9]+]], 3, 2
-; CHECK-REG: std [[R1]], -8(1)
-; CHECK-REG: std [[R3]], -16(1)
-; CHECK-REG: lxvd2x 34, 0, [[R2]]
-; CHECK-REG-NOT: stxvd2x
+; CHECK-REG: stw 3, -16(1)
+; CHECK-REG: addi [[R1:[0-9]+]], 1, -16
+; CHECK-REG: addis [[R2:[0-9]+]]
+; CHECK-REG: addi [[R2]], [[R2]]
+; CHECK-REG-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]]
+; CHECK-REG-DAG: lxvw4x 35, 0, [[R2]]
+; CHECK-REG: xxspltw 34, [[VS1]], 0
+; CHECK-REG: vadduwm 2, 2, 3
+; CHECK-REG-NOT: stxvw4x
 ; CHECK-REG: blr
 
 ; CHECK-FISL-LABEL: @test80
-; CHECK-FISL-DAG: addi [[R1:[0-9]+]], 3, 3
-; CHECK-FISL-DAG: addi [[R2:[0-9]+]], 1, -16
-; CHECK-FISL-DAG: addi [[R3:[0-9]+]], 3, 2
-; CHECK-FISL-DAG: std [[R1]], -8(1)
-; CHECK-FISL-DAG: std [[R3]], -16(1)
-; CHECK-FISL-DAG: lxvd2x 0, 0, [[R2]]
+; CHECK-FISL: mr 4, 3
+; CHECK-FISL: stw 4, -16(1)
+; CHECK-FISL: addi [[R1:[0-9]+]], 1, -16
+; CHECK-FISL-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]]
+; CHECK-FISL-DAG: xxspltw {{[0-9]+}}, [[VS1]], 0
+; CHECK-FISL: addis [[R2:[0-9]+]]
+; CHECK-FISL: addi [[R2]], [[R2]]
+; CHECK-FISL-DAG: lxvw4x {{[0-9]+}}, 0, [[R2]]
+; CHECK-FISL: vadduwm
+; CHECK-FISL-NOT: stxvw4x
 ; CHECK-FISL: blr
 
 ; CHECK-LE-LABEL: @test80
 ; CHECK-LE-DAG: mtvsrd [[R1:[0-9]+]], 3
+; CHECK-LE-DAG: xxswapd  [[V1:[0-9]+]], [[R1]]
 ; CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI
 ; CHECK-LE-DAG: lxvd2x [[V2:[0-9]+]], 0, [[R2]]
-; CHECK-LE-DAG: xxspltd 34, [[R1]]
+; CHECK-LE-DAG: xxspltw 34, [[V1]]
 ; CHECK-LE-DAG: xxswapd 35, [[V2]]
-; CHECK-LE: vaddudm 2, 2, 3
+; CHECK-LE: vadduwm 2, 2, 3
 ; CHECK-LE: blr
 }
 
diff --git a/test/CodeGen/PowerPC/weak_def_can_be_hidden.ll b/test/CodeGen/PowerPC/weak_def_can_be_hidden.ll
index 0b87613bb4d8..3760f1bb1657 100644
--- a/test/CodeGen/PowerPC/weak_def_can_be_hidden.ll
+++ b/test/CodeGen/PowerPC/weak_def_can_be_hidden.ll
@@ -3,7 +3,7 @@
 ; RUN: llc -mtriple=powerpc-apple-darwin9 -O0 < %s | FileCheck --check-prefix=CHECK-D89 %s
 ; RUN: llc -mtriple=powerpc-apple-darwin8 -O0 < %s | FileCheck --check-prefix=CHECK-D89 %s
 
-@v1 = linkonce_odr constant i32 32
+@v1 = linkonce_odr local_unnamed_addr constant i32 32
 ; CHECK: .globl  _v1
 ; CHECK: .weak_def_can_be_hidden _v1
 
@@ -26,7 +26,7 @@ define i32* @f2() {
   ret i32* @v2
 }
 
-@v3 = linkonce_odr unnamed_addr global i32 32
+@v3 = linkonce_odr unnamed_addr constant i32 32
 ; CHECK: .globl  _v3
 ; CHECK: .weak_def_can_be_hidden _v3
 
@@ -37,9 +37,9 @@ define i32* @f3() {
   ret i32* @v3
 }
 
-@v4 = linkonce_odr global i32 32
+@v4 = linkonce_odr unnamed_addr global i32 32
 ; CHECK: .globl  _v4
-; CHECK: .weak_definition _v4
+; CHECK: .weak_def_can_be_hidden _v4
 
 ; CHECK-D89: .globl  _v4
 ; CHECK-D89: .weak_definition _v4
diff --git a/test/CodeGen/PowerPC/xvcmpeqdp-v2f64.ll b/test/CodeGen/PowerPC/xvcmpeqdp-v2f64.ll
index ef63233e746b..fd8adff5a1d7 100644
--- a/test/CodeGen/PowerPC/xvcmpeqdp-v2f64.ll
+++ b/test/CodeGen/PowerPC/xvcmpeqdp-v2f64.ll
@@ -3,22 +3,24 @@ target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-unknown-linux-gnu"
 
 ; Function Attrs: nounwind
-define void @__fmax_double3_3D_exec() #0 {
+define void @__fmax_double3_3D_exec(<3 x double> %input1, <3 x i64> %input2, 
+                                    <3 x i1> %input3, <3 x i64> %input4,
+                                    <3 x i64> %input5,  <4 x double>* %input6) #0 {
 entry:
   br i1 undef, label %if.then.i, label %fmax_double3.exit
 
 if.then.i:                                        ; preds = %entry
-  %cmp24.i.i = fcmp ord <3 x double> undef, zeroinitializer
+  %cmp24.i.i = fcmp ord <3 x double> %input1, zeroinitializer
   %sext25.i.i = sext <3 x i1> %cmp24.i.i to <3 x i64>
   %neg.i.i = xor <3 x i64> %sext25.i.i, <i64 -1, i64 -1, i64 -1>
-  %or.i.i = or <3 x i64> undef, %neg.i.i
-  %neg.i.i.i = select <3 x i1> undef, <3 x i64> zeroinitializer, <3 x i64> %sext25.i.i
-  %and.i.i.i = and <3 x i64> undef, %neg.i.i.i
-  %and26.i.i.i = and <3 x i64> undef, %or.i.i
+  %or.i.i = or <3 x i64> %input2, %neg.i.i
+  %neg.i.i.i = select <3 x i1> %input3, <3 x i64> zeroinitializer, <3 x i64> %sext25.i.i
+  %and.i.i.i = and <3 x i64> %input4, %neg.i.i.i
+  %and26.i.i.i = and <3 x i64> %input5, %or.i.i
   %or.i.i.i = or <3 x i64> %and.i.i.i, %and26.i.i.i
   %astype32.i.i.i = bitcast <3 x i64> %or.i.i.i to <3 x double>
   %extractVec33.i.i.i = shufflevector <3 x double> %astype32.i.i.i, <3 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
-  store <4 x double> %extractVec33.i.i.i, <4 x double>* undef, align 32
+  store <4 x double> %extractVec33.i.i.i, <4 x double>* %input6, align 32
   br label %fmax_double3.exit
 
 ; CHECK-LABEL: @__fmax_double3_3D_exec