vendor/llvm/llvm-trunk-r300422

4 files changed, 47 insertions, 5 deletions

diff --git a/test/CodeGen/SPARC/mature-mc-support.ll b/test/CodeGen/SPARC/mature-mc-support.ll
index 4ed33098051d..3951ddd604c4 100644
--- a/test/CodeGen/SPARC/mature-mc-support.ll
+++ b/test/CodeGen/SPARC/mature-mc-support.ll
@@ -17,4 +17,4 @@
 
 module asm "	.this_directive_is_very_unlikely_to_exist"
 
-; CHECK: LLVM ERROR: Error parsing inline asm
+; CHECK: error: unknown directive
diff --git a/test/CodeGen/SPARC/register-clobber.ll b/test/CodeGen/SPARC/register-clobber.ll
new file mode 100644
index 000000000000..0ea36df6d015
--- /dev/null
+++ b/test/CodeGen/SPARC/register-clobber.ll
@@ -0,0 +1,35 @@
+; RUN: llc -march=sparc < %s | FileCheck %s
+
+;; Verify that g1 (the output of first asm) is properly understood to
+;; be clobbered by the call instruction, and moved out of the way
+;; before it. (NOTE: remember delay slot; mov executes before call)
+
+; CHECK-LABEL: test1:
+; CHECK: ta       9
+; CHECK: call dosomething
+; CHECK: mov      %g1, %i0
+
+define i32 @test1() nounwind {
+entry:
+  %0 = tail call i32 asm sideeffect "ta $1", "={r1},i"(i32 9) nounwind
+  tail call void @dosomething() nounwind
+  ret i32 %0
+}
+
+;; Also check using the value.
+; CHECK-LABEL: test2:
+; CHECK: ta       9
+; CHECK: call dosomething
+; CHECK: mov      %g1, %i0
+; CHECK: mov      %i0, %g1
+; CHECK: ta       10
+
+define void @test2() local_unnamed_addr nounwind {
+entry:
+  %0 = tail call i32 asm sideeffect "ta $1", "={r1},i"(i32 9) nounwind
+  tail call void @dosomething() nounwind
+  tail call void asm sideeffect "ta $0", "i,{r1}"(i32 10, i32 %0) nounwind
+  ret void
+}
+
+declare void @dosomething() local_unnamed_addr nounwind
diff --git a/test/CodeGen/SPARC/reserved-regs.ll b/test/CodeGen/SPARC/reserved-regs.ll
index fe208015827b..c5a124f538f9 100644
--- a/test/CodeGen/SPARC/reserved-regs.ll
+++ b/test/CodeGen/SPARC/reserved-regs.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=sparc  < %s | FileCheck %s
+; RUN: llc -march=sparc -verify-machineinstrs < %s | FileCheck %s
 
 @g = common global [32 x i32] zeroinitializer, align 16
 @h = common global [16 x i64] zeroinitializer, align 16
@@ -6,6 +6,7 @@
 ;; Ensures that we don't use registers which are supposed to be reserved.
 
 ; CHECK-LABEL: use_all_i32_regs:
+; CHECK: save %sp
 ; CHECK-NOT: %g0
 ; CHECK-NOT: %g1
 ; CHECK-NOT: %g5
@@ -86,6 +87,7 @@ entry:
 
 
 ; CHECK-LABEL: use_all_i64_regs:
+; CHECK: save %sp
 ; CHECK-NOT: %g0
 ; CHECK-NOT: %g1
 ; CHECK-NOT: %g4
diff --git a/test/CodeGen/SPARC/sjlj.ll b/test/CodeGen/SPARC/sjlj.ll
index 3bf583aa4754..459630f9255f 100755
--- a/test/CodeGen/SPARC/sjlj.ll
+++ b/test/CodeGen/SPARC/sjlj.ll
@@ -66,13 +66,18 @@ return:                                           ; preds = %if.end, %if.then
 ; CHECK:  ba   .LBB1_1
 ; CHECK:  nop
 ; CHECK:.LBB1_1:                                ! %entry
-; CHECK:  ba   .LBB1_3
 ; CHECK:  mov  %g0, %i0
+; CHECK:                                        ! %entry
+; CHECK:  cmp %i0, 0
+; CHECK:  be   .LBB1_5
+; CHECK:  nop
+; CHECK:.LBB1_4:
+; CHECK:  mov  1, %i0
+; CHECK:  ba .LBB1_6
 ; CHECK:.LBB1_2:                                ! Block address taken
 ; CHECK:  mov  1, %i0
-; CHECK:.LBB1_3:                                ! %entry
 ; CHECK:  cmp %i0, 0
-; CHECK:  be   .LBB1_5
+; CHECK:  bne  .LBB1_4
 ; CHECK:  nop
 }
 declare i8* @llvm.frameaddress(i32) #2