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-rw-r--r--Bindings/net/xlnx,axi-ethernet.yaml16
1 files changed, 16 insertions, 0 deletions
diff --git a/Bindings/net/xlnx,axi-ethernet.yaml b/Bindings/net/xlnx,axi-ethernet.yaml
index 1d33d80af11c..bbe89ea9590c 100644
--- a/Bindings/net/xlnx,axi-ethernet.yaml
+++ b/Bindings/net/xlnx,axi-ethernet.yaml
@@ -122,6 +122,20 @@ properties:
and "phy-handle" should point to an external PHY if exists.
maxItems: 1
+ dmas:
+ minItems: 2
+ maxItems: 32
+ description: TX and RX DMA channel phandle
+
+ dma-names:
+ items:
+ pattern: "^[tr]x_chan([0-9]|1[0-5])$"
+ description:
+ Should be "tx_chan0", "tx_chan1" ... "tx_chan15" for DMA Tx channel
+ Should be "rx_chan0", "rx_chan1" ... "rx_chan15" for DMA Rx channel
+ minItems: 2
+ maxItems: 32
+
required:
- compatible
- interrupts
@@ -143,6 +157,8 @@ examples:
clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
phy-mode = "mii";
reg = <0x40c00000 0x40000>,<0x50c00000 0x40000>;
+ dmas = <&xilinx_dma 0>, <&xilinx_dma 1>;
+ dma-names = "tx_chan0", "rx_chan0";
xlnx,rxcsum = <0x2>;
xlnx,rxmem = <0x800>;
xlnx,txcsum = <0x2>;