diff options
Diffstat (limited to 'clang/lib/Basic/Targets')
26 files changed, 1172 insertions, 372 deletions
diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index 34bdb58dffc1..60ef52ac3f0d 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -435,6 +435,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts, if (HasRandGen) Builder.defineMacro("__ARM_FEATURE_RNG", "1"); + if (HasMOPS) + Builder.defineMacro("__ARM_FEATURE_MOPS", "1"); + switch (ArchKind) { default: break; @@ -482,6 +485,10 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); + // Allow detection of fast FMA support. + Builder.defineMacro("__FP_FAST_FMA", "1"); + Builder.defineMacro("__FP_FAST_FMAF", "1"); + if (Opts.VScaleMin && Opts.VScaleMin == Opts.VScaleMax) { Builder.defineMacro("__ARM_FEATURE_SVE_BITS", Twine(Opts.VScaleMin * 128)); Builder.defineMacro("__ARM_FEATURE_SVE_VECTOR_OPERATORS"); @@ -506,21 +513,18 @@ AArch64TargetInfo::getVScaleRange(const LangOptions &LangOpts) const { } bool AArch64TargetInfo::hasFeature(StringRef Feature) const { - return Feature == "aarch64" || Feature == "arm64" || Feature == "arm" || - (Feature == "neon" && (FPU & NeonMode)) || - ((Feature == "sve" || Feature == "sve2" || Feature == "sve2-bitperm" || - Feature == "sve2-aes" || Feature == "sve2-sha3" || - Feature == "sve2-sm4" || Feature == "f64mm" || Feature == "f32mm" || - Feature == "i8mm" || Feature == "bf16") && - (FPU & SveMode)) || - (Feature == "ls64" && HasLS64); + return llvm::StringSwitch<bool>(Feature) + .Cases("aarch64", "arm64", "arm", true) + .Case("neon", FPU & NeonMode) + .Cases("sve", "sve2", "sve2-bitperm", "sve2-aes", "sve2-sha3", "sve2-sm4", "f64mm", "f32mm", "i8mm", "bf16", FPU & SveMode) + .Case("ls64", HasLS64) + .Default(false); } bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, DiagnosticsEngine &Diags) { FPU = FPUMode; HasCRC = false; - HasCrypto = false; HasAES = false; HasSHA2 = false; HasSHA3 = false; @@ -543,7 +547,6 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasMatmulFP64 = false; HasMatmulFP32 = false; HasLSE = false; - HasHBC = false; HasMOPS = false; ArchKind = llvm::AArch64::ArchKind::INVALID; @@ -594,8 +597,6 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, } if (Feature == "+crc") HasCRC = true; - if (Feature == "+crypto") - HasCrypto = true; if (Feature == "+aes") HasAES = true; if (Feature == "+sha2") @@ -660,8 +661,8 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasRandGen = true; if (Feature == "+flagm") HasFlagM = true; - if (Feature == "+hbc") - HasHBC = true; + if (Feature == "+mops") + HasMOPS = true; } setDataLayout(); @@ -679,6 +680,7 @@ AArch64TargetInfo::checkCallingConvention(CallingConv CC) const { case CC_PreserveAll: case CC_OpenCLKernel: case CC_AArch64VectorCall: + case CC_AArch64SVEPCS: case CC_Win64: return CCCR_OK; default: diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h index 9e22aeaff251..bd6812d1257c 100644 --- a/clang/lib/Basic/Targets/AArch64.h +++ b/clang/lib/Basic/Targets/AArch64.h @@ -30,7 +30,6 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo { unsigned FPU; bool HasCRC; - bool HasCrypto; bool HasAES; bool HasSHA2; bool HasSHA3; @@ -54,7 +53,6 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo { bool HasMatmulFP32; bool HasLSE; bool HasFlagM; - bool HasHBC; bool HasMOPS; llvm::AArch64::ArchKind ArchKind; diff --git a/clang/lib/Basic/Targets/AMDGPU.cpp b/clang/lib/Basic/Targets/AMDGPU.cpp index ba7ffa34c73e..50256d8e210c 100644 --- a/clang/lib/Basic/Targets/AMDGPU.cpp +++ b/clang/lib/Basic/Targets/AMDGPU.cpp @@ -183,6 +183,27 @@ bool AMDGPUTargetInfo::initFeatureMap( // XXX - What does the member GPU mean if device name string passed here? if (isAMDGCN(getTriple())) { switch (llvm::AMDGPU::parseArchAMDGCN(CPU)) { + case GK_GFX1103: + case GK_GFX1102: + case GK_GFX1101: + case GK_GFX1100: + Features["ci-insts"] = true; + Features["dot1-insts"] = true; + Features["dot5-insts"] = true; + Features["dot6-insts"] = true; + Features["dot7-insts"] = true; + Features["dot8-insts"] = true; + Features["dl-insts"] = true; + Features["flat-address-space"] = true; + Features["16-bit-insts"] = true; + Features["dpp"] = true; + Features["gfx8-insts"] = true; + Features["gfx9-insts"] = true; + Features["gfx10-insts"] = true; + Features["gfx10-3-insts"] = true; + Features["gfx11-insts"] = true; + break; + case GK_GFX1036: case GK_GFX1035: case GK_GFX1034: case GK_GFX1033: @@ -227,6 +248,9 @@ bool AMDGPUTargetInfo::initFeatureMap( Features["s-memrealtime"] = true; Features["s-memtime-inst"] = true; break; + case GK_GFX940: + Features["gfx940-insts"] = true; + LLVM_FALLTHROUGH; case GK_GFX90A: Features["gfx90a-insts"] = true; LLVM_FALLTHROUGH; @@ -384,12 +408,17 @@ void AMDGPUTargetInfo::getTargetDefines(const LangOptions &Opts, StringRef CanonName = isAMDGCN(getTriple()) ? getArchNameAMDGCN(GPUKind) : getArchNameR600(GPUKind); Builder.defineMacro(Twine("__") + Twine(CanonName) + Twine("__")); + // Emit macros for gfx family e.g. gfx906 -> __GFX9__, gfx1030 -> __GFX10___ + if (isAMDGCN(getTriple())) { + assert(CanonName.startswith("gfx") && "Invalid amdgcn canonical name"); + Builder.defineMacro(Twine("__") + Twine(CanonName.drop_back(2).upper()) + + Twine("__")); + } if (isAMDGCN(getTriple())) { Builder.defineMacro("__amdgcn_processor__", Twine("\"") + Twine(CanonName) + Twine("\"")); Builder.defineMacro("__amdgcn_target_id__", - Twine("\"") + Twine(getTargetID().getValue()) + - Twine("\"")); + Twine("\"") + Twine(*getTargetID()) + Twine("\"")); for (auto F : getAllPossibleTargetIDFeatures(getTriple(), CanonName)) { auto Loc = OffloadArchFeatures.find(F); if (Loc != OffloadArchFeatures.end()) { @@ -403,6 +432,9 @@ void AMDGPUTargetInfo::getTargetDefines(const LangOptions &Opts, } } + if (AllowAMDGPUUnsafeFPAtomics) + Builder.defineMacro("__AMDGCN_UNSAFE_FP_ATOMICS__"); + // TODO: __HAS_FMAF__, __HAS_LDEXPF__, __HAS_FP64__ are deprecated and will be // removed in the near future. if (hasFMAF()) @@ -429,9 +461,13 @@ void AMDGPUTargetInfo::setAuxTarget(const TargetInfo *Aux) { // supported by AMDGPU. Therefore keep its own format for these two types. auto SaveLongDoubleFormat = LongDoubleFormat; auto SaveFloat128Format = Float128Format; + auto SaveLongDoubleWidth = LongDoubleWidth; + auto SaveLongDoubleAlign = LongDoubleAlign; copyAuxTarget(Aux); LongDoubleFormat = SaveLongDoubleFormat; Float128Format = SaveFloat128Format; + LongDoubleWidth = SaveLongDoubleWidth; + LongDoubleAlign = SaveLongDoubleAlign; // For certain builtin types support on the host target, claim they are // support to pass the compilation of the host code during the device-side // compilation. diff --git a/clang/lib/Basic/Targets/AMDGPU.h b/clang/lib/Basic/Targets/AMDGPU.h index 974922191488..5e73a3cb8019 100644 --- a/clang/lib/Basic/Targets/AMDGPU.h +++ b/clang/lib/Basic/Targets/AMDGPU.h @@ -411,6 +411,7 @@ public: return CCCR_Warning; case CC_C: case CC_OpenCLKernel: + case CC_AMDGPUKernelCall: return CCCR_OK; } } @@ -434,17 +435,17 @@ public: DiagnosticsEngine &Diags) override { auto TargetIDFeatures = getAllPossibleTargetIDFeatures(getTriple(), getArchNameAMDGCN(GPUKind)); - llvm::for_each(Features, [&](const auto &F) { + for (const auto &F : Features) { assert(F.front() == '+' || F.front() == '-'); if (F == "+wavefrontsize64") WavefrontSize = 64; bool IsOn = F.front() == '+'; StringRef Name = StringRef(F).drop_front(); if (!llvm::is_contained(TargetIDFeatures, Name)) - return; + continue; assert(OffloadArchFeatures.find(Name) == OffloadArchFeatures.end()); OffloadArchFeatures[Name] = IsOn; - }); + } return true; } diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp index 9c9d198e8f32..b2f61cff81c9 100644 --- a/clang/lib/Basic/Targets/ARM.cpp +++ b/clang/lib/Basic/Targets/ARM.cpp @@ -955,6 +955,7 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts, case llvm::ARM::ArchKind::ARMV8_4A: case llvm::ARM::ArchKind::ARMV8_5A: case llvm::ARM::ArchKind::ARMV8_6A: + case llvm::ARM::ArchKind::ARMV8_7A: case llvm::ARM::ArchKind::ARMV8_8A: case llvm::ARM::ArchKind::ARMV9A: case llvm::ARM::ArchKind::ARMV9_1A: diff --git a/clang/lib/Basic/Targets/AVR.cpp b/clang/lib/Basic/Targets/AVR.cpp index 6266ed72cd5c..67e27ebd58de 100644 --- a/clang/lib/Basic/Targets/AVR.cpp +++ b/clang/lib/Basic/Targets/AVR.cpp @@ -24,282 +24,309 @@ namespace targets { struct LLVM_LIBRARY_VISIBILITY MCUInfo { const char *Name; const char *DefineName; - const int NumFlashBanks; // -1 means the device does not support LPM/ELPM. + const int NumFlashBanks; // Set to 0 for the devices do not support LPM/ELPM. + bool IsTiny; // Set to true for the devices belong to the avrtiny family. }; -// This list should be kept up-to-date with AVRDevices.td in LLVM. +// NOTE: This list has been synchronized with gcc-avr 5.4.0 and avr-libc 2.0.0. static MCUInfo AVRMcus[] = { - {"at90s1200", "__AVR_AT90S1200__", 0}, - {"attiny11", "__AVR_ATtiny11__", 0}, - {"attiny12", "__AVR_ATtiny12__", 0}, - {"attiny15", "__AVR_ATtiny15__", 0}, - {"attiny28", "__AVR_ATtiny28__", 0}, - {"at90s2313", "__AVR_AT90S2313__", 1}, - {"at90s2323", "__AVR_AT90S2323__", 1}, - {"at90s2333", "__AVR_AT90S2333__", 1}, - {"at90s2343", "__AVR_AT90S2343__", 1}, - {"attiny22", "__AVR_ATtiny22__", 1}, - {"attiny26", "__AVR_ATtiny26__", 1}, - {"at86rf401", "__AVR_AT86RF401__", 1}, - {"at90s4414", "__AVR_AT90S4414__", 1}, - {"at90s4433", "__AVR_AT90S4433__", 1}, - {"at90s4434", "__AVR_AT90S4434__", 1}, - {"at90s8515", "__AVR_AT90S8515__", 1}, - {"at90c8534", "__AVR_AT90c8534__", 1}, - {"at90s8535", "__AVR_AT90S8535__", 1}, - {"ata5272", "__AVR_ATA5272__", 1}, - {"attiny13", "__AVR_ATtiny13__", 1}, - {"attiny13a", "__AVR_ATtiny13A__", 1}, - {"attiny2313", "__AVR_ATtiny2313__", 1}, - {"attiny2313a", "__AVR_ATtiny2313A__", 1}, - {"attiny24", "__AVR_ATtiny24__", 1}, - {"attiny24a", "__AVR_ATtiny24A__", 1}, - {"attiny4313", "__AVR_ATtiny4313__", 1}, - {"attiny44", "__AVR_ATtiny44__", 1}, - {"attiny44a", "__AVR_ATtiny44A__", 1}, - {"attiny84", "__AVR_ATtiny84__", 1}, - {"attiny84a", "__AVR_ATtiny84A__", 1}, - {"attiny25", "__AVR_ATtiny25__", 1}, - {"attiny45", "__AVR_ATtiny45__", 1}, - {"attiny85", "__AVR_ATtiny85__", 1}, - {"attiny261", "__AVR_ATtiny261__", 1}, - {"attiny261a", "__AVR_ATtiny261A__", 1}, - {"attiny441", "__AVR_ATtiny441__", 1}, - {"attiny461", "__AVR_ATtiny461__", 1}, - {"attiny461a", "__AVR_ATtiny461A__", 1}, - {"attiny841", "__AVR_ATtiny841__", 1}, - {"attiny861", "__AVR_ATtiny861__", 1}, - {"attiny861a", "__AVR_ATtiny861A__", 1}, - {"attiny87", "__AVR_ATtiny87__", 1}, - {"attiny43u", "__AVR_ATtiny43U__", 1}, - {"attiny48", "__AVR_ATtiny48__", 1}, - {"attiny88", "__AVR_ATtiny88__", 1}, - {"attiny828", "__AVR_ATtiny828__", 1}, - {"at43usb355", "__AVR_AT43USB355__", 1}, - {"at76c711", "__AVR_AT76C711__", 1}, - {"atmega103", "__AVR_ATmega103__", 1}, - {"at43usb320", "__AVR_AT43USB320__", 1}, - {"attiny167", "__AVR_ATtiny167__", 1}, - {"at90usb82", "__AVR_AT90USB82__", 1}, - {"at90usb162", "__AVR_AT90USB162__", 1}, - {"ata5505", "__AVR_ATA5505__", 1}, - {"atmega8u2", "__AVR_ATmega8U2__", 1}, - {"atmega16u2", "__AVR_ATmega16U2__", 1}, - {"atmega32u2", "__AVR_ATmega32U2__", 1}, - {"attiny1634", "__AVR_ATtiny1634__", 1}, - {"atmega8", "__AVR_ATmega8__", 1}, - {"ata6289", "__AVR_ATA6289__", 1}, - {"atmega8a", "__AVR_ATmega8A__", 1}, - {"ata6285", "__AVR_ATA6285__", 1}, - {"ata6286", "__AVR_ATA6286__", 1}, - {"atmega48", "__AVR_ATmega48__", 1}, - {"atmega48a", "__AVR_ATmega48A__", 1}, - {"atmega48pa", "__AVR_ATmega48PA__", 1}, - {"atmega48pb", "__AVR_ATmega48PB__", 1}, - {"atmega48p", "__AVR_ATmega48P__", 1}, - {"atmega88", "__AVR_ATmega88__", 1}, - {"atmega88a", "__AVR_ATmega88A__", 1}, - {"atmega88p", "__AVR_ATmega88P__", 1}, - {"atmega88pa", "__AVR_ATmega88PA__", 1}, - {"atmega88pb", "__AVR_ATmega88PB__", 1}, - {"atmega8515", "__AVR_ATmega8515__", 1}, - {"atmega8535", "__AVR_ATmega8535__", 1}, - {"atmega8hva", "__AVR_ATmega8HVA__", 1}, - {"at90pwm1", "__AVR_AT90PWM1__", 1}, - {"at90pwm2", "__AVR_AT90PWM2__", 1}, - {"at90pwm2b", "__AVR_AT90PWM2B__", 1}, - {"at90pwm3", "__AVR_AT90PWM3__", 1}, - {"at90pwm3b", "__AVR_AT90PWM3B__", 1}, - {"at90pwm81", "__AVR_AT90PWM81__", 1}, - {"ata5790", "__AVR_ATA5790__", 1}, - {"ata5795", "__AVR_ATA5795__", 1}, - {"atmega16", "__AVR_ATmega16__", 1}, - {"atmega16a", "__AVR_ATmega16A__", 1}, - {"atmega161", "__AVR_ATmega161__", 1}, - {"atmega162", "__AVR_ATmega162__", 1}, - {"atmega163", "__AVR_ATmega163__", 1}, - {"atmega164a", "__AVR_ATmega164A__", 1}, - {"atmega164p", "__AVR_ATmega164P__", 1}, - {"atmega164pa", "__AVR_ATmega164PA__", 1}, - {"atmega165", "__AVR_ATmega165__", 1}, - {"atmega165a", "__AVR_ATmega165A__", 1}, - {"atmega165p", "__AVR_ATmega165P__", 1}, - {"atmega165pa", "__AVR_ATmega165PA__", 1}, - {"atmega168", "__AVR_ATmega168__", 1}, - {"atmega168a", "__AVR_ATmega168A__", 1}, - {"atmega168p", "__AVR_ATmega168P__", 1}, - {"atmega168pa", "__AVR_ATmega168PA__", 1}, - {"atmega168pb", "__AVR_ATmega168PB__", 1}, - {"atmega169", "__AVR_ATmega169__", 1}, - {"atmega169a", "__AVR_ATmega169A__", 1}, - {"atmega169p", "__AVR_ATmega169P__", 1}, - {"atmega169pa", "__AVR_ATmega169PA__", 1}, - {"atmega32", "__AVR_ATmega32__", 1}, - {"atmega32a", "__AVR_ATmega32A__", 1}, - {"atmega323", "__AVR_ATmega323__", 1}, - {"atmega324a", "__AVR_ATmega324A__", 1}, - {"atmega324p", "__AVR_ATmega324P__", 1}, - {"atmega324pa", "__AVR_ATmega324PA__", 1}, - {"atmega324pb", "__AVR_ATmega324PB__", 1}, - {"atmega325", "__AVR_ATmega325__", 1}, - {"atmega325a", "__AVR_ATmega325A__", 1}, - {"atmega325p", "__AVR_ATmega325P__", 1}, - {"atmega325pa", "__AVR_ATmega325PA__", 1}, - {"atmega3250", "__AVR_ATmega3250__", 1}, - {"atmega3250a", "__AVR_ATmega3250A__", 1}, - {"atmega3250p", "__AVR_ATmega3250P__", 1}, - {"atmega3250pa", "__AVR_ATmega3250PA__", 1}, - {"atmega328", "__AVR_ATmega328__", 1}, - {"atmega328p", "__AVR_ATmega328P__", 1}, - {"atmega328pb", "__AVR_ATmega328PB__", 1}, - {"atmega329", "__AVR_ATmega329__", 1}, - {"atmega329a", "__AVR_ATmega329A__", 1}, - {"atmega329p", "__AVR_ATmega329P__", 1}, - {"atmega329pa", "__AVR_ATmega329PA__", 1}, - {"atmega3290", "__AVR_ATmega3290__", 1}, - {"atmega3290a", "__AVR_ATmega3290A__", 1}, - {"atmega3290p", "__AVR_ATmega3290P__", 1}, - {"atmega3290pa", "__AVR_ATmega3290PA__", 1}, - {"atmega406", "__AVR_ATmega406__", 1}, - {"atmega64", "__AVR_ATmega64__", 1}, - {"atmega64a", "__AVR_ATmega64A__", 1}, - {"atmega640", "__AVR_ATmega640__", 1}, - {"atmega644", "__AVR_ATmega644__", 1}, - {"atmega644a", "__AVR_ATmega644A__", 1}, - {"atmega644p", "__AVR_ATmega644P__", 1}, - {"atmega644pa", "__AVR_ATmega644PA__", 1}, - {"atmega645", "__AVR_ATmega645__", 1}, - {"atmega645a", "__AVR_ATmega645A__", 1}, - {"atmega645p", "__AVR_ATmega645P__", 1}, - {"atmega649", "__AVR_ATmega649__", 1}, - {"atmega649a", "__AVR_ATmega649A__", 1}, - {"atmega649p", "__AVR_ATmega649P__", 1}, - {"atmega6450", "__AVR_ATmega6450__", 1}, - {"atmega6450a", "__AVR_ATmega6450A__", 1}, - {"atmega6450p", "__AVR_ATmega6450P__", 1}, - {"atmega6490", "__AVR_ATmega6490__", 1}, - {"atmega6490a", "__AVR_ATmega6490A__", 1}, - {"atmega6490p", "__AVR_ATmega6490P__", 1}, - {"atmega64rfr2", "__AVR_ATmega64RFR2__", 1}, - {"atmega644rfr2", "__AVR_ATmega644RFR2__", 1}, - {"atmega16hva", "__AVR_ATmega16HVA__", 1}, - {"atmega16hva2", "__AVR_ATmega16HVA2__", 1}, - {"atmega16hvb", "__AVR_ATmega16HVB__", 1}, - {"atmega16hvbrevb", "__AVR_ATmega16HVBREVB__", 1}, - {"atmega32hvb", "__AVR_ATmega32HVB__", 1}, - {"atmega32hvbrevb", "__AVR_ATmega32HVBREVB__", 1}, - {"atmega64hve", "__AVR_ATmega64HVE__", 1}, - {"at90can32", "__AVR_AT90CAN32__", 1}, - {"at90can64", "__AVR_AT90CAN64__", 1}, - {"at90pwm161", "__AVR_AT90PWM161__", 1}, - {"at90pwm216", "__AVR_AT90PWM216__", 1}, - {"at90pwm316", "__AVR_AT90PWM316__", 1}, - {"atmega32c1", "__AVR_ATmega32C1__", 1}, - {"atmega64c1", "__AVR_ATmega64C1__", 1}, - {"atmega16m1", "__AVR_ATmega16M1__", 1}, - {"atmega32m1", "__AVR_ATmega32M1__", 1}, - {"atmega64m1", "__AVR_ATmega64M1__", 1}, - {"atmega16u4", "__AVR_ATmega16U4__", 1}, - {"atmega32u4", "__AVR_ATmega32U4__", 1}, - {"atmega32u6", "__AVR_ATmega32U6__", 1}, - {"at90usb646", "__AVR_AT90USB646__", 1}, - {"at90usb647", "__AVR_AT90USB647__", 1}, - {"at90scr100", "__AVR_AT90SCR100__", 1}, - {"at94k", "__AVR_AT94K__", 1}, - {"m3000", "__AVR_AT000__", 1}, - {"atmega128", "__AVR_ATmega128__", 2}, - {"atmega128a", "__AVR_ATmega128A__", 2}, - {"atmega1280", "__AVR_ATmega1280__", 2}, - {"atmega1281", "__AVR_ATmega1281__", 2}, - {"atmega1284", "__AVR_ATmega1284__", 2}, - {"atmega1284p", "__AVR_ATmega1284P__", 2}, - {"atmega128rfa1", "__AVR_ATmega128RFA1__", 2}, - {"atmega128rfr2", "__AVR_ATmega128RFR2__", 2}, - {"atmega1284rfr2", "__AVR_ATmega1284RFR2__", 2}, - {"at90can128", "__AVR_AT90CAN128__", 2}, - {"at90usb1286", "__AVR_AT90USB1286__", 2}, - {"at90usb1287", "__AVR_AT90USB1287__", 2}, - {"atmega2560", "__AVR_ATmega2560__", 4}, - {"atmega2561", "__AVR_ATmega2561__", 4}, - {"atmega256rfr2", "__AVR_ATmega256RFR2__", 4}, - {"atmega2564rfr2", "__AVR_ATmega2564RFR2__", 4}, - {"atxmega16a4", "__AVR_ATxmega16A4__", 1}, - {"atxmega16a4u", "__AVR_ATxmega16A4U__", 1}, - {"atxmega16c4", "__AVR_ATxmega16C4__", 1}, - {"atxmega16d4", "__AVR_ATxmega16D4__", 1}, - {"atxmega32a4", "__AVR_ATxmega32A4__", 1}, - {"atxmega32a4u", "__AVR_ATxmega32A4U__", 1}, - {"atxmega32c4", "__AVR_ATxmega32C4__", 1}, - {"atxmega32d4", "__AVR_ATxmega32D4__", 1}, - {"atxmega32e5", "__AVR_ATxmega32E5__", 1}, - {"atxmega16e5", "__AVR_ATxmega16E5__", 1}, - {"atxmega8e5", "__AVR_ATxmega8E5__", 1}, - {"atxmega32x1", "__AVR_ATxmega32X1__", 1}, - {"atxmega64a3", "__AVR_ATxmega64A3__", 1}, - {"atxmega64a3u", "__AVR_ATxmega64A3U__", 1}, - {"atxmega64a4u", "__AVR_ATxmega64A4U__", 1}, - {"atxmega64b1", "__AVR_ATxmega64B1__", 1}, - {"atxmega64b3", "__AVR_ATxmega64B3__", 1}, - {"atxmega64c3", "__AVR_ATxmega64C3__", 1}, - {"atxmega64d3", "__AVR_ATxmega64D3__", 1}, - {"atxmega64d4", "__AVR_ATxmega64D4__", 1}, - {"atxmega64a1", "__AVR_ATxmega64A1__", 1}, - {"atxmega64a1u", "__AVR_ATxmega64A1U__", 1}, - {"atxmega128a3", "__AVR_ATxmega128A3__", 2}, - {"atxmega128a3u", "__AVR_ATxmega128A3U__", 2}, - {"atxmega128b1", "__AVR_ATxmega128B1__", 2}, - {"atxmega128b3", "__AVR_ATxmega128B3__", 2}, - {"atxmega128c3", "__AVR_ATxmega128C3__", 2}, - {"atxmega128d3", "__AVR_ATxmega128D3__", 2}, - {"atxmega128d4", "__AVR_ATxmega128D4__", 2}, - {"atxmega192a3", "__AVR_ATxmega192A3__", 3}, - {"atxmega192a3u", "__AVR_ATxmega192A3U__", 3}, - {"atxmega192c3", "__AVR_ATxmega192C3__", 3}, - {"atxmega192d3", "__AVR_ATxmega192D3__", 3}, - {"atxmega256a3", "__AVR_ATxmega256A3__", 4}, - {"atxmega256a3u", "__AVR_ATxmega256A3U__", 4}, - {"atxmega256a3b", "__AVR_ATxmega256A3B__", 4}, - {"atxmega256a3bu", "__AVR_ATxmega256A3BU__", 4}, - {"atxmega256c3", "__AVR_ATxmega256C3__", 4}, - {"atxmega256d3", "__AVR_ATxmega256D3__", 4}, - {"atxmega384c3", "__AVR_ATxmega384C3__", 6}, - {"atxmega384d3", "__AVR_ATxmega384D3__", 6}, - {"atxmega128a1", "__AVR_ATxmega128A1__", 2}, - {"atxmega128a1u", "__AVR_ATxmega128A1U__", 2}, - {"atxmega128a4u", "__AVR_ATxmega128A4U__", 2}, - {"attiny4", "__AVR_ATtiny4__", 0}, - {"attiny5", "__AVR_ATtiny5__", 0}, - {"attiny9", "__AVR_ATtiny9__", 0}, - {"attiny10", "__AVR_ATtiny10__", 0}, - {"attiny20", "__AVR_ATtiny20__", 0}, - {"attiny40", "__AVR_ATtiny40__", 0}, - {"attiny102", "__AVR_ATtiny102__", 0}, - {"attiny104", "__AVR_ATtiny104__", 0}, - {"attiny202", "__AVR_ATtiny202__", 1}, - {"attiny402", "__AVR_ATtiny402__", 1}, - {"attiny204", "__AVR_ATtiny204__", 1}, - {"attiny404", "__AVR_ATtiny404__", 1}, - {"attiny804", "__AVR_ATtiny804__", 1}, - {"attiny1604", "__AVR_ATtiny1604__", 1}, - {"attiny406", "__AVR_ATtiny406__", 1}, - {"attiny806", "__AVR_ATtiny806__", 1}, - {"attiny1606", "__AVR_ATtiny1606__", 1}, - {"attiny807", "__AVR_ATtiny807__", 1}, - {"attiny1607", "__AVR_ATtiny1607__", 1}, - {"attiny212", "__AVR_ATtiny212__", 1}, - {"attiny412", "__AVR_ATtiny412__", 1}, - {"attiny214", "__AVR_ATtiny214__", 1}, - {"attiny414", "__AVR_ATtiny414__", 1}, - {"attiny814", "__AVR_ATtiny814__", 1}, - {"attiny1614", "__AVR_ATtiny1614__", 1}, - {"attiny416", "__AVR_ATtiny416__", 1}, - {"attiny816", "__AVR_ATtiny816__", 1}, - {"attiny1616", "__AVR_ATtiny1616__", 1}, - {"attiny3216", "__AVR_ATtiny3216__", 1}, - {"attiny417", "__AVR_ATtiny417__", 1}, - {"attiny817", "__AVR_ATtiny817__", 1}, - {"attiny1617", "__AVR_ATtiny1617__", 1}, - {"attiny3217", "__AVR_ATtiny3217__", 1}, + {"at90s1200", "__AVR_AT90S1200__", 0, false}, + {"attiny11", "__AVR_ATtiny11__", 0, false}, + {"attiny12", "__AVR_ATtiny12__", 0, false}, + {"attiny15", "__AVR_ATtiny15__", 0, false}, + {"attiny28", "__AVR_ATtiny28__", 0, false}, + {"at90s2313", "__AVR_AT90S2313__", 1, false}, + {"at90s2323", "__AVR_AT90S2323__", 1, false}, + {"at90s2333", "__AVR_AT90S2333__", 1, false}, + {"at90s2343", "__AVR_AT90S2343__", 1, false}, + {"attiny22", "__AVR_ATtiny22__", 1, false}, + {"attiny26", "__AVR_ATtiny26__", 1, false}, + {"at86rf401", "__AVR_AT86RF401__", 1, false}, + {"at90s4414", "__AVR_AT90S4414__", 1, false}, + {"at90s4433", "__AVR_AT90S4433__", 1, false}, + {"at90s4434", "__AVR_AT90S4434__", 1, false}, + {"at90s8515", "__AVR_AT90S8515__", 1, false}, + {"at90c8534", "__AVR_AT90c8534__", 1, false}, + {"at90s8535", "__AVR_AT90S8535__", 1, false}, + {"ata5272", "__AVR_ATA5272__", 1, false}, + {"ata6616c", "__AVR_ATA6616c__", 1, false}, + {"attiny13", "__AVR_ATtiny13__", 1, false}, + {"attiny13a", "__AVR_ATtiny13A__", 1, false}, + {"attiny2313", "__AVR_ATtiny2313__", 1, false}, + {"attiny2313a", "__AVR_ATtiny2313A__", 1, false}, + {"attiny24", "__AVR_ATtiny24__", 1, false}, + {"attiny24a", "__AVR_ATtiny24A__", 1, false}, + {"attiny4313", "__AVR_ATtiny4313__", 1, false}, + {"attiny44", "__AVR_ATtiny44__", 1, false}, + {"attiny44a", "__AVR_ATtiny44A__", 1, false}, + {"attiny84", "__AVR_ATtiny84__", 1, false}, + {"attiny84a", "__AVR_ATtiny84A__", 1, false}, + {"attiny25", "__AVR_ATtiny25__", 1, false}, + {"attiny45", "__AVR_ATtiny45__", 1, false}, + {"attiny85", "__AVR_ATtiny85__", 1, false}, + {"attiny261", "__AVR_ATtiny261__", 1, false}, + {"attiny261a", "__AVR_ATtiny261A__", 1, false}, + {"attiny441", "__AVR_ATtiny441__", 1, false}, + {"attiny461", "__AVR_ATtiny461__", 1, false}, + {"attiny461a", "__AVR_ATtiny461A__", 1, false}, + {"attiny841", "__AVR_ATtiny841__", 1, false}, + {"attiny861", "__AVR_ATtiny861__", 1, false}, + {"attiny861a", "__AVR_ATtiny861A__", 1, false}, + {"attiny87", "__AVR_ATtiny87__", 1, false}, + {"attiny43u", "__AVR_ATtiny43U__", 1, false}, + {"attiny48", "__AVR_ATtiny48__", 1, false}, + {"attiny88", "__AVR_ATtiny88__", 1, false}, + {"attiny828", "__AVR_ATtiny828__", 1, false}, + {"at43usb355", "__AVR_AT43USB355__", 1, false}, + {"at76c711", "__AVR_AT76C711__", 1, false}, + {"atmega103", "__AVR_ATmega103__", 1, false}, + {"at43usb320", "__AVR_AT43USB320__", 1, false}, + {"attiny167", "__AVR_ATtiny167__", 1, false}, + {"at90usb82", "__AVR_AT90USB82__", 1, false}, + {"at90usb162", "__AVR_AT90USB162__", 1, false}, + {"ata5505", "__AVR_ATA5505__", 1, false}, + {"ata6617c", "__AVR_ATA6617C__", 1, false}, + {"ata664251", "__AVR_ATA664251__", 1, false}, + {"atmega8u2", "__AVR_ATmega8U2__", 1, false}, + {"atmega16u2", "__AVR_ATmega16U2__", 1, false}, + {"atmega32u2", "__AVR_ATmega32U2__", 1, false}, + {"attiny1634", "__AVR_ATtiny1634__", 1, false}, + {"atmega8", "__AVR_ATmega8__", 1, false}, + {"ata6289", "__AVR_ATA6289__", 1, false}, + {"atmega8a", "__AVR_ATmega8A__", 1, false}, + {"ata6285", "__AVR_ATA6285__", 1, false}, + {"ata6286", "__AVR_ATA6286__", 1, false}, + {"ata6612c", "__AVR_ATA6612C__", 1, false}, + {"atmega48", "__AVR_ATmega48__", 1, false}, + {"atmega48a", "__AVR_ATmega48A__", 1, false}, + {"atmega48pa", "__AVR_ATmega48PA__", 1, false}, + {"atmega48pb", "__AVR_ATmega48PB__", 1, false}, + {"atmega48p", "__AVR_ATmega48P__", 1, false}, + {"atmega88", "__AVR_ATmega88__", 1, false}, + {"atmega88a", "__AVR_ATmega88A__", 1, false}, + {"atmega88p", "__AVR_ATmega88P__", 1, false}, + {"atmega88pa", "__AVR_ATmega88PA__", 1, false}, + {"atmega88pb", "__AVR_ATmega88PB__", 1, false}, + {"atmega8515", "__AVR_ATmega8515__", 1, false}, + {"atmega8535", "__AVR_ATmega8535__", 1, false}, + {"atmega8hva", "__AVR_ATmega8HVA__", 1, false}, + {"at90pwm1", "__AVR_AT90PWM1__", 1, false}, + {"at90pwm2", "__AVR_AT90PWM2__", 1, false}, + {"at90pwm2b", "__AVR_AT90PWM2B__", 1, false}, + {"at90pwm3", "__AVR_AT90PWM3__", 1, false}, + {"at90pwm3b", "__AVR_AT90PWM3B__", 1, false}, + {"at90pwm81", "__AVR_AT90PWM81__", 1, false}, + {"ata5702m322", "__AVR_ATA5702M322__", 1, false}, + {"ata5782", "__AVR_ATA5782__", 1, false}, + {"ata5790", "__AVR_ATA5790__", 1, false}, + {"ata5790n", "__AVR_ATA5790N__", 1, false}, + {"ata5791", "__AVR_ATA5791__", 1, false}, + {"ata5795", "__AVR_ATA5795__", 1, false}, + {"ata5831", "__AVR_ATA5831__", 1, false}, + {"ata6613c", "__AVR_ATA6613C__", 1, false}, + {"ata6614q", "__AVR_ATA6614Q__", 1, false}, + {"ata8210", "__AVR_ATA8210__", 1, false}, + {"ata8510", "__AVR_ATA8510__", 1, false}, + {"atmega16", "__AVR_ATmega16__", 1, false}, + {"atmega16a", "__AVR_ATmega16A__", 1, false}, + {"atmega161", "__AVR_ATmega161__", 1, false}, + {"atmega162", "__AVR_ATmega162__", 1, false}, + {"atmega163", "__AVR_ATmega163__", 1, false}, + {"atmega164a", "__AVR_ATmega164A__", 1, false}, + {"atmega164p", "__AVR_ATmega164P__", 1, false}, + {"atmega164pa", "__AVR_ATmega164PA__", 1, false}, + {"atmega165", "__AVR_ATmega165__", 1, false}, + {"atmega165a", "__AVR_ATmega165A__", 1, false}, + {"atmega165p", "__AVR_ATmega165P__", 1, false}, + {"atmega165pa", "__AVR_ATmega165PA__", 1, false}, + {"atmega168", "__AVR_ATmega168__", 1, false}, + {"atmega168a", "__AVR_ATmega168A__", 1, false}, + {"atmega168p", "__AVR_ATmega168P__", 1, false}, + {"atmega168pa", "__AVR_ATmega168PA__", 1, false}, + {"atmega168pb", "__AVR_ATmega168PB__", 1, false}, + {"atmega169", "__AVR_ATmega169__", 1, false}, + {"atmega169a", "__AVR_ATmega169A__", 1, false}, + {"atmega169p", "__AVR_ATmega169P__", 1, false}, + {"atmega169pa", "__AVR_ATmega169PA__", 1, false}, + {"atmega32", "__AVR_ATmega32__", 1, false}, + {"atmega32a", "__AVR_ATmega32A__", 1, false}, + {"atmega323", "__AVR_ATmega323__", 1, false}, + {"atmega324a", "__AVR_ATmega324A__", 1, false}, + {"atmega324p", "__AVR_ATmega324P__", 1, false}, + {"atmega324pa", "__AVR_ATmega324PA__", 1, false}, + {"atmega324pb", "__AVR_ATmega324PB__", 1, false}, + {"atmega325", "__AVR_ATmega325__", 1, false}, + {"atmega325a", "__AVR_ATmega325A__", 1, false}, + {"atmega325p", "__AVR_ATmega325P__", 1, false}, + {"atmega325pa", "__AVR_ATmega325PA__", 1, false}, + {"atmega3250", "__AVR_ATmega3250__", 1, false}, + {"atmega3250a", "__AVR_ATmega3250A__", 1, false}, + {"atmega3250p", "__AVR_ATmega3250P__", 1, false}, + {"atmega3250pa", "__AVR_ATmega3250PA__", 1, false}, + {"atmega328", "__AVR_ATmega328__", 1, false}, + {"atmega328p", "__AVR_ATmega328P__", 1, false}, + {"atmega328pb", "__AVR_ATmega328PB__", 1, false}, + {"atmega329", "__AVR_ATmega329__", 1, false}, + {"atmega329a", "__AVR_ATmega329A__", 1, false}, + {"atmega329p", "__AVR_ATmega329P__", 1, false}, + {"atmega329pa", "__AVR_ATmega329PA__", 1, false}, + {"atmega3290", "__AVR_ATmega3290__", 1, false}, + {"atmega3290a", "__AVR_ATmega3290A__", 1, false}, + {"atmega3290p", "__AVR_ATmega3290P__", 1, false}, + {"atmega3290pa", "__AVR_ATmega3290PA__", 1, false}, + {"atmega406", "__AVR_ATmega406__", 1, false}, + {"atmega64", "__AVR_ATmega64__", 1, false}, + {"atmega64a", "__AVR_ATmega64A__", 1, false}, + {"atmega640", "__AVR_ATmega640__", 1, false}, + {"atmega644", "__AVR_ATmega644__", 1, false}, + {"atmega644a", "__AVR_ATmega644A__", 1, false}, + {"atmega644p", "__AVR_ATmega644P__", 1, false}, + {"atmega644pa", "__AVR_ATmega644PA__", 1, false}, + {"atmega645", "__AVR_ATmega645__", 1, false}, + {"atmega645a", "__AVR_ATmega645A__", 1, false}, + {"atmega645p", "__AVR_ATmega645P__", 1, false}, + {"atmega649", "__AVR_ATmega649__", 1, false}, + {"atmega649a", "__AVR_ATmega649A__", 1, false}, + {"atmega649p", "__AVR_ATmega649P__", 1, false}, + {"atmega6450", "__AVR_ATmega6450__", 1, false}, + {"atmega6450a", "__AVR_ATmega6450A__", 1, false}, + {"atmega6450p", "__AVR_ATmega6450P__", 1, false}, + {"atmega6490", "__AVR_ATmega6490__", 1, false}, + {"atmega6490a", "__AVR_ATmega6490A__", 1, false}, + {"atmega6490p", "__AVR_ATmega6490P__", 1, false}, + {"atmega64rfr2", "__AVR_ATmega64RFR2__", 1, false}, + {"atmega644rfr2", "__AVR_ATmega644RFR2__", 1, false}, + {"atmega16hva", "__AVR_ATmega16HVA__", 1, false}, + {"atmega16hva2", "__AVR_ATmega16HVA2__", 1, false}, + {"atmega16hvb", "__AVR_ATmega16HVB__", 1, false}, + {"atmega16hvbrevb", "__AVR_ATmega16HVBREVB__", 1, false}, + {"atmega32hvb", "__AVR_ATmega32HVB__", 1, false}, + {"atmega32hvbrevb", "__AVR_ATmega32HVBREVB__", 1, false}, + {"atmega64hve", "__AVR_ATmega64HVE__", 1, false}, + {"atmega64hve2", "__AVR_ATmega64HVE2__", 1, false}, + {"at90can32", "__AVR_AT90CAN32__", 1, false}, + {"at90can64", "__AVR_AT90CAN64__", 1, false}, + {"at90pwm161", "__AVR_AT90PWM161__", 1, false}, + {"at90pwm216", "__AVR_AT90PWM216__", 1, false}, + {"at90pwm316", "__AVR_AT90PWM316__", 1, false}, + {"atmega32c1", "__AVR_ATmega32C1__", 1, false}, + {"atmega64c1", "__AVR_ATmega64C1__", 1, false}, + {"atmega16m1", "__AVR_ATmega16M1__", 1, false}, + {"atmega32m1", "__AVR_ATmega32M1__", 1, false}, + {"atmega64m1", "__AVR_ATmega64M1__", 1, false}, + {"atmega16u4", "__AVR_ATmega16U4__", 1, false}, + {"atmega32u4", "__AVR_ATmega32U4__", 1, false}, + {"atmega32u6", "__AVR_ATmega32U6__", 1, false}, + {"at90usb646", "__AVR_AT90USB646__", 1, false}, + {"at90usb647", "__AVR_AT90USB647__", 1, false}, + {"at90scr100", "__AVR_AT90SCR100__", 1, false}, + {"at94k", "__AVR_AT94K__", 1, false}, + {"m3000", "__AVR_AT000__", 1, false}, + {"atmega128", "__AVR_ATmega128__", 2, false}, + {"atmega128a", "__AVR_ATmega128A__", 2, false}, + {"atmega1280", "__AVR_ATmega1280__", 2, false}, + {"atmega1281", "__AVR_ATmega1281__", 2, false}, + {"atmega1284", "__AVR_ATmega1284__", 2, false}, + {"atmega1284p", "__AVR_ATmega1284P__", 2, false}, + {"atmega128rfa1", "__AVR_ATmega128RFA1__", 2, false}, + {"atmega128rfr2", "__AVR_ATmega128RFR2__", 2, false}, + {"atmega1284rfr2", "__AVR_ATmega1284RFR2__", 2, false}, + {"at90can128", "__AVR_AT90CAN128__", 2, false}, + {"at90usb1286", "__AVR_AT90USB1286__", 2, false}, + {"at90usb1287", "__AVR_AT90USB1287__", 2, false}, + {"atmega2560", "__AVR_ATmega2560__", 4, false}, + {"atmega2561", "__AVR_ATmega2561__", 4, false}, + {"atmega256rfr2", "__AVR_ATmega256RFR2__", 4, false}, + {"atmega2564rfr2", "__AVR_ATmega2564RFR2__", 4, false}, + {"atxmega16a4", "__AVR_ATxmega16A4__", 1, false}, + {"atxmega16a4u", "__AVR_ATxmega16A4U__", 1, false}, + {"atxmega16c4", "__AVR_ATxmega16C4__", 1, false}, + {"atxmega16d4", "__AVR_ATxmega16D4__", 1, false}, + {"atxmega32a4", "__AVR_ATxmega32A4__", 1, false}, + {"atxmega32a4u", "__AVR_ATxmega32A4U__", 1, false}, + {"atxmega32c3", "__AVR_ATxmega32C3__", 1, false}, + {"atxmega32c4", "__AVR_ATxmega32C4__", 1, false}, + {"atxmega32d3", "__AVR_ATxmega32D3__", 1, false}, + {"atxmega32d4", "__AVR_ATxmega32D4__", 1, false}, + {"atxmega32e5", "__AVR_ATxmega32E5__", 1, false}, + {"atxmega16e5", "__AVR_ATxmega16E5__", 1, false}, + {"atxmega8e5", "__AVR_ATxmega8E5__", 1, false}, + {"atxmega64a3", "__AVR_ATxmega64A3__", 1, false}, + {"atxmega64a3u", "__AVR_ATxmega64A3U__", 1, false}, + {"atxmega64a4u", "__AVR_ATxmega64A4U__", 1, false}, + {"atxmega64b1", "__AVR_ATxmega64B1__", 1, false}, + {"atxmega64b3", "__AVR_ATxmega64B3__", 1, false}, + {"atxmega64c3", "__AVR_ATxmega64C3__", 1, false}, + {"atxmega64d3", "__AVR_ATxmega64D3__", 1, false}, + {"atxmega64d4", "__AVR_ATxmega64D4__", 1, false}, + {"atxmega64a1", "__AVR_ATxmega64A1__", 1, false}, + {"atxmega64a1u", "__AVR_ATxmega64A1U__", 1, false}, + {"atxmega128a3", "__AVR_ATxmega128A3__", 2, false}, + {"atxmega128a3u", "__AVR_ATxmega128A3U__", 2, false}, + {"atxmega128b1", "__AVR_ATxmega128B1__", 2, false}, + {"atxmega128b3", "__AVR_ATxmega128B3__", 2, false}, + {"atxmega128c3", "__AVR_ATxmega128C3__", 2, false}, + {"atxmega128d3", "__AVR_ATxmega128D3__", 2, false}, + {"atxmega128d4", "__AVR_ATxmega128D4__", 2, false}, + {"atxmega192a3", "__AVR_ATxmega192A3__", 3, false}, + {"atxmega192a3u", "__AVR_ATxmega192A3U__", 3, false}, + {"atxmega192c3", "__AVR_ATxmega192C3__", 3, false}, + {"atxmega192d3", "__AVR_ATxmega192D3__", 3, false}, + {"atxmega256a3", "__AVR_ATxmega256A3__", 4, false}, + {"atxmega256a3u", "__AVR_ATxmega256A3U__", 4, false}, + {"atxmega256a3b", "__AVR_ATxmega256A3B__", 4, false}, + {"atxmega256a3bu", "__AVR_ATxmega256A3BU__", 4, false}, + {"atxmega256c3", "__AVR_ATxmega256C3__", 4, false}, + {"atxmega256d3", "__AVR_ATxmega256D3__", 4, false}, + {"atxmega384c3", "__AVR_ATxmega384C3__", 6, false}, + {"atxmega384d3", "__AVR_ATxmega384D3__", 6, false}, + {"atxmega128a1", "__AVR_ATxmega128A1__", 2, false}, + {"atxmega128a1u", "__AVR_ATxmega128A1U__", 2, false}, + {"atxmega128a4u", "__AVR_ATxmega128A4U__", 2, false}, + {"attiny4", "__AVR_ATtiny4__", 0, true}, + {"attiny5", "__AVR_ATtiny5__", 0, true}, + {"attiny9", "__AVR_ATtiny9__", 0, true}, + {"attiny10", "__AVR_ATtiny10__", 0, true}, + {"attiny20", "__AVR_ATtiny20__", 0, true}, + {"attiny40", "__AVR_ATtiny40__", 0, true}, + {"attiny102", "__AVR_ATtiny102__", 0, true}, + {"attiny104", "__AVR_ATtiny104__", 0, true}, + {"attiny202", "__AVR_ATtiny202__", 1, false}, + {"attiny402", "__AVR_ATtiny402__", 1, false}, + {"attiny204", "__AVR_ATtiny204__", 1, false}, + {"attiny404", "__AVR_ATtiny404__", 1, false}, + {"attiny804", "__AVR_ATtiny804__", 1, false}, + {"attiny1604", "__AVR_ATtiny1604__", 1, false}, + {"attiny406", "__AVR_ATtiny406__", 1, false}, + {"attiny806", "__AVR_ATtiny806__", 1, false}, + {"attiny1606", "__AVR_ATtiny1606__", 1, false}, + {"attiny807", "__AVR_ATtiny807__", 1, false}, + {"attiny1607", "__AVR_ATtiny1607__", 1, false}, + {"attiny212", "__AVR_ATtiny212__", 1, false}, + {"attiny412", "__AVR_ATtiny412__", 1, false}, + {"attiny214", "__AVR_ATtiny214__", 1, false}, + {"attiny414", "__AVR_ATtiny414__", 1, false}, + {"attiny814", "__AVR_ATtiny814__", 1, false}, + {"attiny1614", "__AVR_ATtiny1614__", 1, false}, + {"attiny416", "__AVR_ATtiny416__", 1, false}, + {"attiny816", "__AVR_ATtiny816__", 1, false}, + {"attiny1616", "__AVR_ATtiny1616__", 1, false}, + {"attiny3216", "__AVR_ATtiny3216__", 1, false}, + {"attiny417", "__AVR_ATtiny417__", 1, false}, + {"attiny817", "__AVR_ATtiny817__", 1, false}, + {"attiny1617", "__AVR_ATtiny1617__", 1, false}, + {"attiny3217", "__AVR_ATtiny3217__", 1, false}, + {"attiny1624", "__AVR_ATtiny1624__", 1, false}, + {"attiny1626", "__AVR_ATtiny1626__", 1, false}, + {"attiny1627", "__AVR_ATtiny1627__", 1, false}, + {"atmega808", "__AVR_ATmega808__", 1, false}, + {"atmega809", "__AVR_ATmega809__", 1, false}, + {"atmega1608", "__AVR_ATmega1608__", 1, false}, + {"atmega1609", "__AVR_ATmega1609__", 1, false}, + {"atmega3208", "__AVR_ATmega3208__", 1, false}, + {"atmega3209", "__AVR_ATmega3209__", 1, false}, + {"atmega4808", "__AVR_ATmega4808__", 1, false}, + {"atmega4809", "__AVR_ATmega4809__", 1, false}, }; } // namespace targets @@ -325,6 +352,27 @@ void AVRTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const { Values.push_back(Info.Name); } +bool AVRTargetInfo::setCPU(const std::string &Name) { + // Set the ABI and CPU fields if parameter Name is a family name. + if (llvm::is_contained(ValidFamilyNames, Name)) { + CPU = Name; + ABI = Name == "avrtiny" ? "avrtiny" : "avr"; + return true; + } + + // Set the ABI field if parameter Name is a device name. + auto It = llvm::find_if( + AVRMcus, [&](const MCUInfo &Info) { return Info.Name == Name; }); + if (It != std::end(AVRMcus)) { + CPU = Name; + ABI = It->IsTiny ? "avrtiny" : "avr"; + return true; + } + + // Parameter Name is neither valid family name nor valid device name. + return false; +} + void AVRTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("AVR"); @@ -332,6 +380,9 @@ void AVRTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__AVR__"); Builder.defineMacro("__ELF__"); + if (ABI == "avrtiny") + Builder.defineMacro("__AVR_TINY__", "1"); + if (!this->CPU.empty()) { auto It = llvm::find_if( AVRMcus, [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); diff --git a/clang/lib/Basic/Targets/AVR.h b/clang/lib/Basic/Targets/AVR.h index a281e2c2cd74..74b012a0923b 100644 --- a/clang/lib/Basic/Targets/AVR.h +++ b/clang/lib/Basic/Targets/AVR.h @@ -74,8 +74,7 @@ public: static const char *const GCCRegNames[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", - "r20", "r21", "r22", "r23", "r24", "r25", "X", "Y", "Z", "SP" - }; + "r20", "r21", "r22", "r23", "r24", "r25", "X", "Y", "Z", "SP"}; return llvm::makeArrayRef(GCCRegNames); } @@ -169,15 +168,12 @@ public: bool isValidCPUName(StringRef Name) const override; void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override; - bool setCPU(const std::string &Name) override { - bool isValid = isValidCPUName(Name); - if (isValid) - CPU = Name; - return isValid; - } + bool setCPU(const std::string &Name) override; + StringRef getABI() const override { return ABI; } protected: std::string CPU; + StringRef ABI; }; } // namespace targets diff --git a/clang/lib/Basic/Targets/CSKY.cpp b/clang/lib/Basic/Targets/CSKY.cpp new file mode 100644 index 000000000000..adcffd90ae78 --- /dev/null +++ b/clang/lib/Basic/Targets/CSKY.cpp @@ -0,0 +1,314 @@ +//===--- CSKY.cpp - Implement CSKY target feature support -----------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements CSKY TargetInfo objects. +// +//===----------------------------------------------------------------------===// + +#include "CSKY.h" + +using namespace clang; +using namespace clang::targets; + +bool CSKYTargetInfo::isValidCPUName(StringRef Name) const { + return llvm::CSKY::parseCPUArch(Name) != llvm::CSKY::ArchKind::INVALID; +} + +bool CSKYTargetInfo::setCPU(const std::string &Name) { + llvm::CSKY::ArchKind archKind = llvm::CSKY::parseCPUArch(Name); + bool isValid = (archKind != llvm::CSKY::ArchKind::INVALID); + + if (isValid) { + CPU = Name; + Arch = archKind; + } + + return isValid; +} + +void CSKYTargetInfo::getTargetDefines(const LangOptions &Opts, + MacroBuilder &Builder) const { + Builder.defineMacro("__ELF__"); + Builder.defineMacro("__csky__", "2"); + Builder.defineMacro("__CSKY__", "2"); + Builder.defineMacro("__ckcore__", "2"); + Builder.defineMacro("__CKCORE__", "2"); + + Builder.defineMacro("__CSKYABI__", ABI == "abiv2" ? "2" : "1"); + Builder.defineMacro("__cskyabi__", ABI == "abiv2" ? "2" : "1"); + + StringRef ArchName = "ck810"; + StringRef CPUName = "ck810"; + + if (Arch != llvm::CSKY::ArchKind::INVALID) { + ArchName = llvm::CSKY::getArchName(Arch); + CPUName = CPU; + } + + Builder.defineMacro("__" + ArchName.upper() + "__"); + Builder.defineMacro("__" + ArchName.lower() + "__"); + Builder.defineMacro("__" + CPUName.upper() + "__"); + Builder.defineMacro("__" + CPUName.lower() + "__"); + + // TODO: Add support for BE if BE was supported later + StringRef endian = "__cskyLE__"; + + Builder.defineMacro(endian); + Builder.defineMacro(endian.upper()); + Builder.defineMacro(endian.lower()); + + if (DSPV2) { + StringRef dspv2 = "__CSKY_DSPV2__"; + Builder.defineMacro(dspv2); + Builder.defineMacro(dspv2.lower()); + } + + if (VDSPV2) { + StringRef vdspv2 = "__CSKY_VDSPV2__"; + Builder.defineMacro(vdspv2); + Builder.defineMacro(vdspv2.lower()); + + if (HardFloat) { + StringRef vdspv2_f = "__CSKY_VDSPV2_F__"; + Builder.defineMacro(vdspv2_f); + Builder.defineMacro(vdspv2_f.lower()); + } + } + if (VDSPV1) { + StringRef vdspv1_64 = "__CSKY_VDSP64__"; + StringRef vdspv1_128 = "__CSKY_VDSP128__"; + + Builder.defineMacro(vdspv1_64); + Builder.defineMacro(vdspv1_64.lower()); + Builder.defineMacro(vdspv1_128); + Builder.defineMacro(vdspv1_128.lower()); + } + if (is3E3R1) { + StringRef is3e3r1 = "__CSKY_3E3R1__"; + Builder.defineMacro(is3e3r1); + Builder.defineMacro(is3e3r1.lower()); + } +} + +bool CSKYTargetInfo::hasFeature(StringRef Feature) const { + return llvm::StringSwitch<bool>(Feature) + .Case("hard-float", HardFloat) + .Case("hard-float-abi", HardFloatABI) + .Case("fpuv2_sf", FPUV2_SF) + .Case("fpuv2_df", FPUV2_DF) + .Case("fpuv3_sf", FPUV3_SF) + .Case("fpuv3_df", FPUV3_DF) + .Case("vdspv2", VDSPV2) + .Case("dspv2", DSPV2) + .Case("vdspv1", VDSPV1) + .Case("3e3r1", is3E3R1) + .Default(false); +} + +bool CSKYTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, + DiagnosticsEngine &Diags) { + for (const auto &Feature : Features) { + if (Feature == "+hard-float") + HardFloat = true; + if (Feature == "+hard-float-abi") + HardFloatABI = true; + if (Feature == "+fpuv2_sf") + FPUV2_SF = true; + if (Feature == "+fpuv2_df") + FPUV2_DF = true; + if (Feature == "+fpuv3_sf") + FPUV3_SF = true; + if (Feature == "+fpuv3_df") + FPUV3_DF = true; + if (Feature == "+vdspv2") + VDSPV2 = true; + if (Feature == "+dspv2") + DSPV2 = true; + if (Feature == "+vdspv1") + VDSPV1 = true; + if (Feature == "+3e3r1") + is3E3R1 = true; + } + + return true; +} + +ArrayRef<Builtin::Info> CSKYTargetInfo::getTargetBuiltins() const { + return ArrayRef<Builtin::Info>(); +} + +ArrayRef<const char *> CSKYTargetInfo::getGCCRegNames() const { + static const char *const GCCRegNames[] = { + // Integer registers + "r0", + "r1", + "r2", + "r3", + "r4", + "r5", + "r6", + "r7", + "r8", + "r9", + "r10", + "r11", + "r12", + "r13", + "r14", + "r15", + "r16", + "r17", + "r18", + "r19", + "r20", + "r21", + "r22", + "r23", + "r24", + "r25", + "r26", + "r27", + "r28", + "r29", + "r30", + "r31", + + // Floating point registers + "fr0", + "fr1", + "fr2", + "fr3", + "fr4", + "fr5", + "fr6", + "fr7", + "fr8", + "fr9", + "fr10", + "fr11", + "fr12", + "fr13", + "fr14", + "fr15", + "fr16", + "fr17", + "fr18", + "fr19", + "fr20", + "fr21", + "fr22", + "fr23", + "fr24", + "fr25", + "fr26", + "fr27", + "fr28", + "fr29", + "fr30", + "fr31", + + }; + return llvm::makeArrayRef(GCCRegNames); +} + +ArrayRef<TargetInfo::GCCRegAlias> CSKYTargetInfo::getGCCRegAliases() const { + static const TargetInfo::GCCRegAlias GCCRegAliases[] = { + {{"a0"}, "r0"}, + {{"a1"}, "r1"}, + {{"a2"}, "r2"}, + {{"a3"}, "r3"}, + {{"l0"}, "r4"}, + {{"l1"}, "r5"}, + {{"l2"}, "r6"}, + {{"l3"}, "r7"}, + {{"l4"}, "r8"}, + {{"l5"}, "r9"}, + {{"l6"}, "r10"}, + {{"l7"}, "r11"}, + {{"t0"}, "r12"}, + {{"t1"}, "r13"}, + {{"sp"}, "r14"}, + {{"lr"}, "r15"}, + {{"l8"}, "r16"}, + {{"l9"}, "r17"}, + {{"t2"}, "r18"}, + {{"t3"}, "r19"}, + {{"t4"}, "r20"}, + {{"t5"}, "r21"}, + {{"t6"}, "r22"}, + {{"t7", "fp"}, "r23"}, + {{"t8", "top"}, "r24"}, + {{"t9", "bsp"}, "r25"}, + {{"r26"}, "r26"}, + {{"r27"}, "r27"}, + {{"gb", "rgb", "rdb"}, "r28"}, + {{"tb", "rtb"}, "r29"}, + {{"svbr"}, "r30"}, + {{"tls"}, "r31"}, + + {{"vr0"}, "fr0"}, + {{"vr1"}, "fr1"}, + {{"vr2"}, "fr2"}, + {{"vr3"}, "fr3"}, + {{"vr4"}, "fr4"}, + {{"vr5"}, "fr5"}, + {{"vr6"}, "fr6"}, + {{"vr7"}, "fr7"}, + {{"vr8"}, "fr8"}, + {{"vr9"}, "fr9"}, + {{"vr10"}, "fr10"}, + {{"vr11"}, "fr11"}, + {{"vr12"}, "fr12"}, + {{"vr13"}, "fr13"}, + {{"vr14"}, "fr14"}, + {{"vr15"}, "fr15"}, + {{"vr16"}, "fr16"}, + {{"vr17"}, "fr17"}, + {{"vr18"}, "fr18"}, + {{"vr19"}, "fr19"}, + {{"vr20"}, "fr20"}, + {{"vr21"}, "fr21"}, + {{"vr22"}, "fr22"}, + {{"vr23"}, "fr23"}, + {{"vr24"}, "fr24"}, + {{"vr25"}, "fr25"}, + {{"vr26"}, "fr26"}, + {{"vr27"}, "fr27"}, + {{"vr28"}, "fr28"}, + {{"vr29"}, "fr29"}, + {{"vr30"}, "fr30"}, + {{"vr31"}, "fr31"}, + + }; + return llvm::makeArrayRef(GCCRegAliases); +} + +bool CSKYTargetInfo::validateAsmConstraint( + const char *&Name, TargetInfo::ConstraintInfo &Info) const { + switch (*Name) { + default: + return false; + case 'a': + case 'b': + case 'c': + case 'y': + case 'l': + case 'h': + case 'w': + case 'v': // A floating-point and vector register. + case 'z': + Info.setAllowsRegister(); + return true; + } +} + +unsigned CSKYTargetInfo::getMinGlobalAlign(uint64_t Size) const { + if (Size >= 32) + return 32; + return 0; +} diff --git a/clang/lib/Basic/Targets/CSKY.h b/clang/lib/Basic/Targets/CSKY.h new file mode 100644 index 000000000000..7e932e7c86b1 --- /dev/null +++ b/clang/lib/Basic/Targets/CSKY.h @@ -0,0 +1,107 @@ +//===--- CSKY.h - Declare CSKY target feature support -----------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file declares CSKY TargetInfo objects. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_CSKY_H +#define LLVM_CLANG_LIB_BASIC_TARGETS_CSKY_H + +#include "clang/Basic/MacroBuilder.h" +#include "clang/Basic/TargetInfo.h" +#include "llvm/Support/CSKYTargetParser.h" + +namespace clang { +namespace targets { + +class LLVM_LIBRARY_VISIBILITY CSKYTargetInfo : public TargetInfo { +protected: + std::string ABI; + llvm::CSKY::ArchKind Arch = llvm::CSKY::ArchKind::INVALID; + std::string CPU; + + bool HardFloat = false; + bool HardFloatABI = false; + bool FPUV2_SF = false; + bool FPUV2_DF = false; + bool FPUV3_SF = false; + bool FPUV3_DF = false; + bool VDSPV2 = false; + bool VDSPV1 = false; + bool DSPV2 = false; + bool is3E3R1 = false; + +public: + CSKYTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) + : TargetInfo(Triple) { + NoAsmVariants = true; + LongLongAlign = 32; + SuitableAlign = 32; + DoubleAlign = LongDoubleAlign = 32; + SizeType = UnsignedInt; + PtrDiffType = SignedInt; + IntPtrType = SignedInt; + WCharType = SignedInt; + WIntType = UnsignedInt; + + UseZeroLengthBitfieldAlignment = true; + MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; + resetDataLayout("e-m:e-S32-p:32:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-" + "v64:32:32-v128:32:32-a:0:32-Fi32-n32"); + + setABI("abiv2"); + } + + StringRef getABI() const override { return ABI; } + bool setABI(const std::string &Name) override { + if (Name == "abiv2" || Name == "abiv1") { + ABI = Name; + return true; + } + return false; + } + + bool setCPU(const std::string &Name) override; + + bool isValidCPUName(StringRef Name) const override; + + virtual unsigned getMinGlobalAlign(uint64_t) const override; + + ArrayRef<Builtin::Info> getTargetBuiltins() const override; + + BuiltinVaListKind getBuiltinVaListKind() const override { + return VoidPtrBuiltinVaList; + } + + bool validateAsmConstraint(const char *&Name, + TargetInfo::ConstraintInfo &info) const override; + + const char *getClobbers() const override { return ""; } + + void getTargetDefines(const LangOptions &Opts, + MacroBuilder &Builder) const override; + bool hasFeature(StringRef Feature) const override; + bool handleTargetFeatures(std::vector<std::string> &Features, + DiagnosticsEngine &Diags) override; + + /// Whether target allows to overalign ABI-specified preferred alignment + bool allowsLargerPreferedTypeAlignment() const override { return false; } + + bool hasBitIntType() const override { return true; } + +protected: + ArrayRef<const char *> getGCCRegNames() const override; + + ArrayRef<GCCRegAlias> getGCCRegAliases() const override; +}; + +} // namespace targets +} // namespace clang + +#endif // LLVM_CLANG_LIB_BASIC_TARGETS_CSKY_H diff --git a/clang/lib/Basic/Targets/DirectX.cpp b/clang/lib/Basic/Targets/DirectX.cpp new file mode 100644 index 000000000000..0dd27e6e93b3 --- /dev/null +++ b/clang/lib/Basic/Targets/DirectX.cpp @@ -0,0 +1,22 @@ +//===--- DirectX.cpp - Implement DirectX target feature support -----------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements DirectX TargetInfo objects. +// +//===----------------------------------------------------------------------===// + +#include "DirectX.h" +#include "Targets.h" + +using namespace clang; +using namespace clang::targets; + +void DirectXTargetInfo::getTargetDefines(const LangOptions &Opts, + MacroBuilder &Builder) const { + DefineStd(Builder, "DIRECTX", Opts); +} diff --git a/clang/lib/Basic/Targets/DirectX.h b/clang/lib/Basic/Targets/DirectX.h new file mode 100644 index 000000000000..a773090b413f --- /dev/null +++ b/clang/lib/Basic/Targets/DirectX.h @@ -0,0 +1,93 @@ +//===--- DirectX.h - Declare DirectX target feature support -----*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file declares DXIL TargetInfo objects. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_DIRECTX_H +#define LLVM_CLANG_LIB_BASIC_TARGETS_DIRECTX_H +#include "clang/Basic/TargetInfo.h" +#include "clang/Basic/TargetOptions.h" +#include "llvm/ADT/Triple.h" +#include "llvm/Support/Compiler.h" + +namespace clang { +namespace targets { + +static const unsigned DirectXAddrSpaceMap[] = { + 0, // Default + 1, // opencl_global + 3, // opencl_local + 2, // opencl_constant + 0, // opencl_private + 4, // opencl_generic + 5, // opencl_global_device + 6, // opencl_global_host + 0, // cuda_device + 0, // cuda_constant + 0, // cuda_shared + // SYCL address space values for this map are dummy + 0, // sycl_global + 0, // sycl_global_device + 0, // sycl_global_host + 0, // sycl_local + 0, // sycl_private + 0, // ptr32_sptr + 0, // ptr32_uptr + 0 // ptr64 +}; + +class LLVM_LIBRARY_VISIBILITY DirectXTargetInfo : public TargetInfo { +public: + DirectXTargetInfo(const llvm::Triple &Triple, const TargetOptions &) + : TargetInfo(Triple) { + TLSSupported = false; + VLASupported = false; + LongWidth = LongAlign = 64; + AddrSpaceMap = &DirectXAddrSpaceMap; + UseAddrSpaceMapMangling = true; + HasLegalHalfType = true; + HasFloat16 = true; + NoAsmVariants = true; + resetDataLayout("e-m:e-p:32:32-i1:32-i8:8-i16:16-i32:32-i64:64-f16:16-f32:" + "32-f64:64-n8:16:32:64"); + TheCXXABI.set(TargetCXXABI::Microsoft); + } + bool useFP16ConversionIntrinsics() const override { return false; } + void getTargetDefines(const LangOptions &Opts, + MacroBuilder &Builder) const override; + + bool hasFeature(StringRef Feature) const override { + return Feature == "directx"; + } + + ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } + + const char *getClobbers() const override { return ""; } + + ArrayRef<const char *> getGCCRegNames() const override { return None; } + + bool validateAsmConstraint(const char *&Name, + TargetInfo::ConstraintInfo &info) const override { + return true; + } + + ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { + return None; + } + + BuiltinVaListKind getBuiltinVaListKind() const override { + return TargetInfo::VoidPtrBuiltinVaList; + } +}; + +} // namespace targets +} // namespace clang + +#endif // LLVM_CLANG_LIB_BASIC_TARGETS_DIRECTX_H diff --git a/clang/lib/Basic/Targets/NVPTX.cpp b/clang/lib/Basic/Targets/NVPTX.cpp index 75e82d819900..9dd60adb00fb 100644 --- a/clang/lib/Basic/Targets/NVPTX.cpp +++ b/clang/lib/Basic/Targets/NVPTX.cpp @@ -179,7 +179,7 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("__PTX__"); Builder.defineMacro("__NVPTX__"); - if (Opts.CUDAIsDevice) { + if (Opts.CUDAIsDevice || Opts.OpenMPIsDevice) { // Set __CUDA_ARCH__ for the GPU specified. std::string CUDAArchCode = [this] { switch (GPU) { @@ -205,6 +205,7 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts, case CudaArch::GFX909: case CudaArch::GFX90a: case CudaArch::GFX90c: + case CudaArch::GFX940: case CudaArch::GFX1010: case CudaArch::GFX1011: case CudaArch::GFX1012: @@ -215,6 +216,11 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions &Opts, case CudaArch::GFX1033: case CudaArch::GFX1034: case CudaArch::GFX1035: + case CudaArch::GFX1036: + case CudaArch::GFX1100: + case CudaArch::GFX1101: + case CudaArch::GFX1102: + case CudaArch::GFX1103: case CudaArch::Generic: case CudaArch::LAST: break; diff --git a/clang/lib/Basic/Targets/OSTargets.cpp b/clang/lib/Basic/Targets/OSTargets.cpp index f8f12daaa072..f2ed076039a0 100644 --- a/clang/lib/Basic/Targets/OSTargets.cpp +++ b/clang/lib/Basic/Targets/OSTargets.cpp @@ -73,19 +73,19 @@ void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, char Str[7]; if (OsVersion.getMajor() < 10) { Str[0] = '0' + OsVersion.getMajor(); - Str[1] = '0' + (OsVersion.getMinor().getValueOr(0) / 10); - Str[2] = '0' + (OsVersion.getMinor().getValueOr(0) % 10); - Str[3] = '0' + (OsVersion.getSubminor().getValueOr(0) / 10); - Str[4] = '0' + (OsVersion.getSubminor().getValueOr(0) % 10); + Str[1] = '0' + (OsVersion.getMinor().value_or(0) / 10); + Str[2] = '0' + (OsVersion.getMinor().value_or(0) % 10); + Str[3] = '0' + (OsVersion.getSubminor().value_or(0) / 10); + Str[4] = '0' + (OsVersion.getSubminor().value_or(0) % 10); Str[5] = '\0'; } else { // Handle versions >= 10. Str[0] = '0' + (OsVersion.getMajor() / 10); Str[1] = '0' + (OsVersion.getMajor() % 10); - Str[2] = '0' + (OsVersion.getMinor().getValueOr(0) / 10); - Str[3] = '0' + (OsVersion.getMinor().getValueOr(0) % 10); - Str[4] = '0' + (OsVersion.getSubminor().getValueOr(0) / 10); - Str[5] = '0' + (OsVersion.getSubminor().getValueOr(0) % 10); + Str[2] = '0' + (OsVersion.getMinor().value_or(0) / 10); + Str[3] = '0' + (OsVersion.getMinor().value_or(0) % 10); + Str[4] = '0' + (OsVersion.getSubminor().value_or(0) / 10); + Str[5] = '0' + (OsVersion.getSubminor().value_or(0) % 10); Str[6] = '\0'; } if (Triple.isTvOS()) @@ -98,12 +98,25 @@ void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, assert(OsVersion < VersionTuple(10) && "Invalid version!"); char Str[6]; Str[0] = '0' + OsVersion.getMajor(); - Str[1] = '0' + (OsVersion.getMinor().getValueOr(0) / 10); - Str[2] = '0' + (OsVersion.getMinor().getValueOr(0) % 10); - Str[3] = '0' + (OsVersion.getSubminor().getValueOr(0) / 10); - Str[4] = '0' + (OsVersion.getSubminor().getValueOr(0) % 10); + Str[1] = '0' + (OsVersion.getMinor().value_or(0) / 10); + Str[2] = '0' + (OsVersion.getMinor().value_or(0) % 10); + Str[3] = '0' + (OsVersion.getSubminor().value_or(0) / 10); + Str[4] = '0' + (OsVersion.getSubminor().value_or(0) % 10); Str[5] = '\0'; Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); + } else if (Triple.isDriverKit()) { + assert(OsVersion.getMajor() < 100 && + OsVersion.getMinor().value_or(0) < 100 && + OsVersion.getSubminor().value_or(0) < 100 && "Invalid version!"); + char Str[7]; + Str[0] = '0' + (OsVersion.getMajor() / 10); + Str[1] = '0' + (OsVersion.getMajor() % 10); + Str[2] = '0' + (OsVersion.getMinor().value_or(0) / 10); + Str[3] = '0' + (OsVersion.getMinor().value_or(0) % 10); + Str[4] = '0' + (OsVersion.getSubminor().value_or(0) / 10); + Str[5] = '0' + (OsVersion.getSubminor().value_or(0) % 10); + Str[6] = '\0'; + Builder.defineMacro("__ENVIRONMENT_DRIVERKIT_VERSION_MIN_REQUIRED__", Str); } else if (Triple.isMacOSX()) { // Note that the Driver allows versions which aren't representable in the // define (because we only get a single digit for the minor and micro @@ -114,17 +127,17 @@ void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, if (OsVersion < VersionTuple(10, 10)) { Str[0] = '0' + (OsVersion.getMajor() / 10); Str[1] = '0' + (OsVersion.getMajor() % 10); - Str[2] = '0' + std::min(OsVersion.getMinor().getValueOr(0), 9U); - Str[3] = '0' + std::min(OsVersion.getSubminor().getValueOr(0), 9U); + Str[2] = '0' + std::min(OsVersion.getMinor().value_or(0), 9U); + Str[3] = '0' + std::min(OsVersion.getSubminor().value_or(0), 9U); Str[4] = '\0'; } else { // Handle versions > 10.9. Str[0] = '0' + (OsVersion.getMajor() / 10); Str[1] = '0' + (OsVersion.getMajor() % 10); - Str[2] = '0' + (OsVersion.getMinor().getValueOr(0) / 10); - Str[3] = '0' + (OsVersion.getMinor().getValueOr(0) % 10); - Str[4] = '0' + (OsVersion.getSubminor().getValueOr(0) / 10); - Str[5] = '0' + (OsVersion.getSubminor().getValueOr(0) % 10); + Str[2] = '0' + (OsVersion.getMinor().value_or(0) / 10); + Str[3] = '0' + (OsVersion.getMinor().value_or(0) % 10); + Str[4] = '0' + (OsVersion.getSubminor().value_or(0) / 10); + Str[5] = '0' + (OsVersion.getSubminor().value_or(0) % 10); Str[6] = '\0'; } Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); @@ -202,6 +215,9 @@ static void addVisualCDefines(const LangOptions &Opts, MacroBuilder &Builder) { } } + if (Opts.Kernel) + Builder.defineMacro("_KERNEL_MODE"); + Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); Builder.defineMacro("__STDC_NO_THREADS__"); diff --git a/clang/lib/Basic/Targets/OSTargets.h b/clang/lib/Basic/Targets/OSTargets.h index 3c1830d5f8e8..a814f681b146 100644 --- a/clang/lib/Basic/Targets/OSTargets.h +++ b/clang/lib/Basic/Targets/OSTargets.h @@ -108,6 +108,8 @@ public: this->TLSSupported = !Triple.isOSVersionLT(2); else this->TLSSupported = !Triple.isOSVersionLT(3); + } else if (Triple.isDriverKit()) { + // No TLS on DriverKit. } this->MCountName = "\01mcount"; @@ -539,8 +541,9 @@ public: } }; +// Common base class for PS4/PS5 targets. template <typename Target> -class LLVM_LIBRARY_VISIBILITY PS4OSTargetInfo : public OSTargetInfo<Target> { +class LLVM_LIBRARY_VISIBILITY PSOSTargetInfo : public OSTargetInfo<Target> { protected: void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, MacroBuilder &Builder) const override { @@ -550,35 +553,66 @@ protected: DefineStd(Builder, "unix", Opts); Builder.defineMacro("__ELF__"); Builder.defineMacro("__SCE__"); - Builder.defineMacro("__ORBIS__"); } public: - PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) + PSOSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : OSTargetInfo<Target>(Triple, Opts) { this->WCharType = TargetInfo::UnsignedShort; - // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). + // On PS4/PS5, TLS variable cannot be aligned to more than 32 bytes (256 + // bits). this->MaxTLSAlign = 256; - // On PS4, do not honor explicit bit field alignment, + // On PS4/PS5, do not honor explicit bit field alignment, // as in "__attribute__((aligned(2))) int b : 1;". this->UseExplicitBitFieldAlignment = false; - switch (Triple.getArch()) { - default: - case llvm::Triple::x86_64: - this->MCountName = ".mcount"; - this->NewAlign = 256; - break; - } + this->MCountName = ".mcount"; + this->NewAlign = 256; + this->SuitableAlign = 256; } + TargetInfo::CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { return (CC == CC_C) ? TargetInfo::CCCR_OK : TargetInfo::CCCR_Error; } }; +// PS4 Target +template <typename Target> +class LLVM_LIBRARY_VISIBILITY PS4OSTargetInfo : public PSOSTargetInfo<Target> { +protected: + void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, + MacroBuilder &Builder) const override { + // Start with base class defines. + PSOSTargetInfo<Target>::getOSDefines(Opts, Triple, Builder); + + Builder.defineMacro("__ORBIS__"); + } + +public: + PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) + : PSOSTargetInfo<Target>(Triple, Opts) {} +}; + +// PS5 Target +template <typename Target> +class LLVM_LIBRARY_VISIBILITY PS5OSTargetInfo : public PSOSTargetInfo<Target> { +protected: + void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, + MacroBuilder &Builder) const override { + // Start with base class defines. + PSOSTargetInfo<Target>::getOSDefines(Opts, Triple, Builder); + + Builder.defineMacro("__PROSPERO__"); + } + +public: + PS5OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) + : PSOSTargetInfo<Target>(Triple, Opts) {} +}; + // RTEMS Target template <typename Target> class LLVM_LIBRARY_VISIBILITY RTEMSTargetInfo : public OSTargetInfo<Target> { @@ -749,7 +783,9 @@ public: } // AIX sets FLT_EVAL_METHOD to be 1. - unsigned getFloatEvalMethod() const override { return 1; } + LangOptions::FPEvalMethodKind getFPEvalMethod() const override { + return LangOptions::FPEvalMethodKind::FEM_Double; + } bool defaultsToAIXPowerAlignment() const override { return true; } }; diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp index 1eb0317af60b..9120808e298d 100644 --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -36,6 +36,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasAltivec = true; } else if (Feature == "+vsx") { HasVSX = true; + } else if (Feature == "+crbits") { + UseCRBits = true; } else if (Feature == "+bpermd") { HasBPERMD = true; } else if (Feature == "+extdiv") { @@ -81,6 +83,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, IsISA3_0 = true; } else if (Feature == "+isa-v31-instructions") { IsISA3_1 = true; + } else if (Feature == "+quadword-atomics") { + HasQuadwordAtomics = true; } // TODO: Finish this list and add an assert that we've handled them // all. @@ -206,6 +210,7 @@ static void defineXLCompatMacros(MacroBuilder &Builder) { Builder.defineMacro("__dcbf", "__builtin_dcbf"); Builder.defineMacro("__fmadd", "__builtin_fma"); Builder.defineMacro("__fmadds", "__builtin_fmaf"); + Builder.defineMacro("__abs", "__builtin_abs"); Builder.defineMacro("__labs", "__builtin_labs"); Builder.defineMacro("__llabs", "__builtin_llabs"); Builder.defineMacro("__popcnt4", "__builtin_popcount"); @@ -247,6 +252,14 @@ static void defineXLCompatMacros(MacroBuilder &Builder) { Builder.defineMacro("__test_data_class", "__builtin_ppc_test_data_class"); Builder.defineMacro("__swdiv", "__builtin_ppc_swdiv"); Builder.defineMacro("__swdivs", "__builtin_ppc_swdivs"); + Builder.defineMacro("__fnabs", "__builtin_ppc_fnabs"); + Builder.defineMacro("__fnabss", "__builtin_ppc_fnabss"); + Builder.defineMacro("__builtin_maxfe", "__builtin_ppc_maxfe"); + Builder.defineMacro("__builtin_maxfl", "__builtin_ppc_maxfl"); + Builder.defineMacro("__builtin_maxfs", "__builtin_ppc_maxfs"); + Builder.defineMacro("__builtin_minfe", "__builtin_ppc_minfe"); + Builder.defineMacro("__builtin_minfl", "__builtin_ppc_minfl"); + Builder.defineMacro("__builtin_minfs", "__builtin_ppc_minfs"); } /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific @@ -506,6 +519,11 @@ bool PPCTargetInfo::initFeatureMap( .Case("pwr9", true) .Case("pwr8", true) .Default(false); + Features["crbits"] = llvm::StringSwitch<bool>(CPU) + .Case("ppc64le", true) + .Case("pwr9", true) + .Case("pwr8", true) + .Default(false); Features["vsx"] = llvm::StringSwitch<bool>(CPU) .Case("ppc64le", true) .Case("pwr9", true) @@ -533,6 +551,7 @@ bool PPCTargetInfo::initFeatureMap( .Case("pwr9", true) .Case("pwr8", true) .Case("pwr7", true) + .Case("a2", true) .Default(false); Features["isa-v207-instructions"] = llvm::StringSwitch<bool>(CPU) @@ -544,6 +563,12 @@ bool PPCTargetInfo::initFeatureMap( Features["isa-v30-instructions"] = llvm::StringSwitch<bool>(CPU).Case("pwr9", true).Default(false); + Features["quadword-atomics"] = + getTriple().isArch64Bit() && llvm::StringSwitch<bool>(CPU) + .Case("pwr9", true) + .Case("pwr8", true) + .Default(false); + // Power10 includes all the same features as Power9 plus any features specific // to the Power10 core. if (CPU == "pwr10" || CPU == "power10") { @@ -569,12 +594,12 @@ bool PPCTargetInfo::initFeatureMap( } if (!(ArchDefs & ArchDefinePwr10)) { - if (llvm::find(FeaturesVec, "+mma") != FeaturesVec.end()) { + if (llvm::is_contained(FeaturesVec, "+mma")) { // MMA operations are not available pre-Power10. Diags.Report(diag::err_opt_not_valid_with_opt) << "-mmma" << CPU; return false; } - if (llvm::find(FeaturesVec, "+pcrel") != FeaturesVec.end()) { + if (llvm::is_contained(FeaturesVec, "+pcrel")) { // PC-Relative instructions are not available pre-Power10, // and these instructions also require prefixed instructions support. Diags.Report(diag::err_opt_not_valid_without_opt) @@ -582,13 +607,13 @@ bool PPCTargetInfo::initFeatureMap( << "-mcpu=pwr10 -mprefixed"; return false; } - if (llvm::find(FeaturesVec, "+prefixed") != FeaturesVec.end()) { + if (llvm::is_contained(FeaturesVec, "+prefixed")) { // Prefixed instructions are not available pre-Power10. Diags.Report(diag::err_opt_not_valid_without_opt) << "-mprefixed" << "-mcpu=pwr10"; return false; } - if (llvm::find(FeaturesVec, "+paired-vector-memops") != FeaturesVec.end()) { + if (llvm::is_contained(FeaturesVec, "+paired-vector-memops")) { // Paired vector memops are not available pre-Power10. Diags.Report(diag::err_opt_not_valid_without_opt) << "-mpaired-vector-memops" @@ -634,6 +659,7 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const { .Case("powerpc", true) .Case("altivec", HasAltivec) .Case("vsx", HasVSX) + .Case("crbits", UseCRBits) .Case("power8-vector", HasP8Vector) .Case("crypto", HasP8Crypto) .Case("direct-move", HasDirectMove) @@ -654,6 +680,7 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const { .Case("isa-v207-instructions", IsISA2_07) .Case("isa-v30-instructions", IsISA3_0) .Case("isa-v31-instructions", IsISA3_1) + .Case("quadword-atomics", HasQuadwordAtomics) .Default(false); } diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h index ac52eb219f54..8148762f446b 100644 --- a/clang/lib/Basic/Targets/PPC.h +++ b/clang/lib/Basic/Targets/PPC.h @@ -62,6 +62,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { bool HasROPProtect = false; bool HasPrivileged = false; bool HasVSX = false; + bool UseCRBits = false; bool HasP8Vector = false; bool HasP8Crypto = false; bool HasDirectMove = false; @@ -78,6 +79,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo { bool IsISA2_07 = false; bool IsISA3_0 = false; bool IsISA3_1 = false; + bool HasQuadwordAtomics = false; protected: std::string ABI; @@ -439,8 +441,18 @@ public: DataLayout += "-S128-v256:256:256-v512:512:512"; resetDataLayout(DataLayout); - // PPC64 supports atomics up to 8 bytes. - MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; + // Newer PPC64 instruction sets support atomics up to 16 bytes. + MaxAtomicPromoteWidth = 128; + // Baseline PPC64 supports inlining atomics up to 8 bytes. + MaxAtomicInlineWidth = 64; + } + + void setMaxAtomicWidth() override { + // For power8 and up, backend is able to inline 16-byte atomic lock free + // code. + // TODO: We should allow AIX to inline quadword atomics in the future. + if (!getTriple().isOSAIX() && hasFeature("quadword-atomics")) + MaxAtomicInlineWidth = 128; } BuiltinVaListKind getBuiltinVaListKind() const override { diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index 0680cad5b07c..32dd2bad2c5c 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -188,7 +188,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts, if (ISAInfo->hasExtension("c")) Builder.defineMacro("__riscv_compressed"); - if (ISAInfo->hasExtension("zve32x") || ISAInfo->hasExtension("v")) + if (ISAInfo->hasExtension("zve32x")) Builder.defineMacro("__riscv_vector"); } @@ -232,8 +232,14 @@ bool RISCVTargetInfo::initFeatureMap( return false; } - return TargetInfo::initFeatureMap(Features, Diags, CPU, - (*ParseResult)->toFeatureVector()); + // RISCVISAInfo makes implications for ISA features + std::vector<std::string> ImpliedFeatures = (*ParseResult)->toFeatureVector(); + // Add non-ISA features like `relax` and `save-restore` back + for (const std::string &Feature : FeaturesVec) + if (!llvm::is_contained(ImpliedFeatures, Feature)) + ImpliedFeatures.push_back(Feature); + + return TargetInfo::initFeatureMap(Features, Diags, CPU, ImpliedFeatures); } /// Return true if has this feature, need to sync with handleTargetFeatures. @@ -245,7 +251,7 @@ bool RISCVTargetInfo::hasFeature(StringRef Feature) const { .Case("riscv64", Is64Bit) .Case("64bit", Is64Bit) .Default(None); - if (Result.hasValue()) + if (Result) return Result.getValue(); if (ISAInfo->isSupportedExtensionFeature(Feature)) @@ -272,7 +278,7 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, } if (ABI.empty()) - ABI = llvm::RISCV::computeDefaultABIFromArch(*ISAInfo).str(); + ABI = ISAInfo->computeDefaultABI().str(); return true; } diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h index 5331ed4a50ae..7817e6e81e26 100644 --- a/clang/lib/Basic/Targets/RISCV.h +++ b/clang/lib/Basic/Targets/RISCV.h @@ -96,6 +96,10 @@ public: DiagnosticsEngine &Diags) override; bool hasBitIntType() const override { return true; } + + bool useFP16ConversionIntrinsics() const override { + return false; + } }; class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo { public: diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h index a40d4b3ca27e..08c49f018ac7 100644 --- a/clang/lib/Basic/Targets/SPIR.h +++ b/clang/lib/Basic/Targets/SPIR.h @@ -144,16 +144,16 @@ public: // FIXME: SYCL specification considers unannotated pointers and references // to be pointing to the generic address space. See section 5.9.3 of // SYCL 2020 specification. - // Currently, there is no way of representing SYCL's and HIP's default + // Currently, there is no way of representing SYCL's and HIP/CUDA's default // address space language semantic along with the semantics of embedded C's // default address space in the same address space map. Hence the map needs // to be reset to allow mapping to the desired value of 'Default' entry for - // SYCL and HIP. + // SYCL and HIP/CUDA. setAddressSpaceMap( /*DefaultIsGeneric=*/Opts.SYCLIsDevice || - // The address mapping from HIP language for device code is only defined - // for SPIR-V. - (getTriple().isSPIRV() && Opts.HIP && Opts.CUDAIsDevice)); + // The address mapping from HIP/CUDA language for device code is only + // defined for SPIR-V. + (getTriple().isSPIRV() && Opts.CUDAIsDevice)); } void setSupportedOpenCLOpts() override { diff --git a/clang/lib/Basic/Targets/SystemZ.cpp b/clang/lib/Basic/Targets/SystemZ.cpp index e3e0da21f8d5..84874b58ba68 100644 --- a/clang/lib/Basic/Targets/SystemZ.cpp +++ b/clang/lib/Basic/Targets/SystemZ.cpp @@ -59,6 +59,17 @@ bool SystemZTargetInfo::validateAsmConstraint( default: return false; + case 'Z': + switch (Name[1]) { + default: + return false; + case 'Q': // Address with base and unsigned 12-bit displacement + case 'R': // Likewise, plus an index + case 'S': // Address with base and signed 20-bit displacement + case 'T': // Likewise, plus an index + break; + } + LLVM_FALLTHROUGH; case 'a': // Address register case 'd': // Data register (equivalent to 'r') case 'f': // Floating-point register @@ -93,7 +104,7 @@ static constexpr ISANameRevision ISARevisions[] = { {{"arch11"}, 11}, {{"z13"}, 11}, {{"arch12"}, 12}, {{"z14"}, 12}, {{"arch13"}, 13}, {{"z15"}, 13}, - {{"arch14"}, 14} + {{"arch14"}, 14}, {{"z16"}, 14}, }; int SystemZTargetInfo::getISARevision(StringRef Name) const { diff --git a/clang/lib/Basic/Targets/SystemZ.h b/clang/lib/Basic/Targets/SystemZ.h index 92cefeea5d26..d12045c756c1 100644 --- a/clang/lib/Basic/Targets/SystemZ.h +++ b/clang/lib/Basic/Targets/SystemZ.h @@ -82,6 +82,30 @@ public: bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &info) const override; + std::string convertConstraint(const char *&Constraint) const override { + switch (Constraint[0]) { + case 'p': // Keep 'p' constraint. + return std::string("p"); + case 'Z': + switch (Constraint[1]) { + case 'Q': // Address with base and unsigned 12-bit displacement + case 'R': // Likewise, plus an index + case 'S': // Address with base and signed 20-bit displacement + case 'T': // Likewise, plus an index + // "^" hints llvm that this is a 2 letter constraint. + // "Constraint++" is used to promote the string iterator + // to the next constraint. + return std::string("^") + std::string(Constraint++, 2); + default: + break; + } + break; + default: + break; + } + return TargetInfo::convertConstraint(Constraint); + } + const char *getClobbers() const override { // FIXME: Is this really right? return ""; diff --git a/clang/lib/Basic/Targets/VE.cpp b/clang/lib/Basic/Targets/VE.cpp index 22223654e8ad..4d66c98edc92 100644 --- a/clang/lib/Basic/Targets/VE.cpp +++ b/clang/lib/Basic/Targets/VE.cpp @@ -18,6 +18,12 @@ using namespace clang; using namespace clang::targets; +const Builtin::Info VETargetInfo::BuiltinInfo[] = { +#define BUILTIN(ID, TYPE, ATTRS) \ + {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, +#include "clang/Basic/BuiltinsVE.def" +}; + void VETargetInfo::getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const { Builder.defineMacro("_LP64", "1"); @@ -35,5 +41,6 @@ void VETargetInfo::getTargetDefines(const LangOptions &Opts, } ArrayRef<Builtin::Info> VETargetInfo::getTargetBuiltins() const { - return ArrayRef<Builtin::Info>(); + return llvm::makeArrayRef(BuiltinInfo, + clang::VE::LastTSBuiltin - Builtin::FirstTSBuiltin); } diff --git a/clang/lib/Basic/Targets/WebAssembly.cpp b/clang/lib/Basic/Targets/WebAssembly.cpp index 2309997eb77b..b3b6c2be5c13 100644 --- a/clang/lib/Basic/Targets/WebAssembly.cpp +++ b/clang/lib/Basic/Targets/WebAssembly.cpp @@ -56,6 +56,7 @@ bool WebAssemblyTargetInfo::hasFeature(StringRef Feature) const { .Case("multivalue", HasMultivalue) .Case("tail-call", HasTailCall) .Case("reference-types", HasReferenceTypes) + .Case("extended-const", HasExtendedConst) .Default(false); } @@ -93,6 +94,8 @@ void WebAssemblyTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__wasm_tail_call__"); if (HasReferenceTypes) Builder.defineMacro("__wasm_reference_types__"); + if (HasExtendedConst) + Builder.defineMacro("__wasm_extended_const__"); } void WebAssemblyTargetInfo::setSIMDLevel(llvm::StringMap<bool> &Features, @@ -240,6 +243,14 @@ bool WebAssemblyTargetInfo::handleTargetFeatures( HasReferenceTypes = false; continue; } + if (Feature == "+extended-const") { + HasExtendedConst = true; + continue; + } + if (Feature == "-extended-const") { + HasExtendedConst = false; + continue; + } Diags.Report(diag::err_opt_not_valid_with_opt) << Feature << "-target-feature"; @@ -255,9 +266,11 @@ ArrayRef<Builtin::Info> WebAssemblyTargetInfo::getTargetBuiltins() const { void WebAssemblyTargetInfo::adjust(DiagnosticsEngine &Diags, LangOptions &Opts) { - // If the Atomics feature isn't available, turn off POSIXThreads and - // ThreadModel, so that we don't predefine _REENTRANT or __STDCPP_THREADS__. - if (!HasAtomics) { + TargetInfo::adjust(Diags, Opts); + // Turn off POSIXThreads and ThreadModel so that we don't predefine _REENTRANT + // or __STDCPP_THREADS__ if we will eventually end up stripping atomics + // because they are unsupported. + if (!HasAtomics || !HasBulkMemory) { Opts.POSIXThreads = false; Opts.setThreadModel(LangOptions::ThreadModelKind::Single); Opts.ThreadsafeStatics = false; diff --git a/clang/lib/Basic/Targets/WebAssembly.h b/clang/lib/Basic/Targets/WebAssembly.h index 075486990558..63418869d10a 100644 --- a/clang/lib/Basic/Targets/WebAssembly.h +++ b/clang/lib/Basic/Targets/WebAssembly.h @@ -39,6 +39,7 @@ class LLVM_LIBRARY_VISIBILITY WebAssemblyTargetInfo : public TargetInfo { bool HasMultivalue = false; bool HasTailCall = false; bool HasReferenceTypes = false; + bool HasExtendedConst = false; std::string ABI; diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp index 5c4bd364b06a..06988830eaed 100644 --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -239,7 +239,6 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasAVX512ER = true; } else if (Feature == "+avx512fp16") { HasAVX512FP16 = true; - HasFloat16 = true; } else if (Feature == "+avx512pf") { HasAVX512PF = true; } else if (Feature == "+avx512dq") { @@ -355,6 +354,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, .Default(NoSSE); SSELevel = std::max(SSELevel, Level); + HasFloat16 = SSELevel >= SSE2; + MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature) .Case("+3dnowa", AMD3DNowAthlon) .Case("+3dnow", AMD3DNow) @@ -1095,22 +1096,22 @@ unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const { bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const { return llvm::StringSwitch<bool>(Name) -#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true) -#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true) +#define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, true) +#define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, true) #include "llvm/Support/X86TargetParser.def" .Default(false); } static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) { return llvm::StringSwitch<StringRef>(Name) -#define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME) +#define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, NAME) #include "llvm/Support/X86TargetParser.def" .Default(Name); } char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const { return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name)) -#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) +#define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, MANGLING) #include "llvm/Support/X86TargetParser.def" .Default(0); } @@ -1119,12 +1120,20 @@ void X86TargetInfo::getCPUSpecificCPUDispatchFeatures( StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const { StringRef WholeList = llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name)) -#define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) +#define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, FEATURES) #include "llvm/Support/X86TargetParser.def" .Default(""); WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); } +StringRef X86TargetInfo::getCPUSpecificTuneName(StringRef Name) const { + return llvm::StringSwitch<StringRef>(Name) +#define CPU_SPECIFIC(NAME, TUNE_NAME, MANGLING, FEATURES) .Case(NAME, TUNE_NAME) +#define CPU_SPECIFIC_ALIAS(NEW_NAME, TUNE_NAME, NAME) .Case(NEW_NAME, TUNE_NAME) +#include "llvm/Support/X86TargetParser.def" + .Default(""); +} + // We can't use a generic validation scheme for the cpus accepted here // versus subtarget cpus accepted in the target attribute because the // variables intitialized by the runtime only support the below currently @@ -1482,8 +1491,8 @@ std::string X86TargetInfo::convertConstraint(const char *&Constraint) const { return std::string("{si}"); case 'D': return std::string("{di}"); - case 'p': // address - return std::string("im"); + case 'p': // Keep 'p' constraint (address). + return std::string("p"); case 't': // top of floating point stack. return std::string("{st}"); case 'u': // second from top of floating point stack. diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h index d1b66432e38b..78e444f4e4eb 100644 --- a/clang/lib/Basic/Targets/X86.h +++ b/clang/lib/Basic/Targets/X86.h @@ -14,6 +14,7 @@ #define LLVM_CLANG_LIB_BASIC_TARGETS_X86_H #include "OSTargets.h" +#include "clang/Basic/BitmaskEnum.h" #include "clang/Basic/TargetInfo.h" #include "clang/Basic/TargetOptions.h" #include "llvm/ADT/Triple.h" @@ -168,11 +169,15 @@ public: return LongDoubleFormat == &llvm::APFloat::IEEEquad() ? "g" : "e"; } - unsigned getFloatEvalMethod() const override { + LangOptions::FPEvalMethodKind getFPEvalMethod() const override { // X87 evaluates with 80 bits "long double" precision. - return SSELevel == NoSSE ? 2 : 0; + return SSELevel == NoSSE ? LangOptions::FPEvalMethodKind::FEM_Extended + : LangOptions::FPEvalMethodKind::FEM_Source; } + // EvalMethod `source` is not supported for targets with `NoSSE` feature. + bool supportSourceEvalMethod() const override { return SSELevel > NoSSE; } + ArrayRef<const char *> getGCCRegNames() const override; ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { @@ -197,6 +202,8 @@ public: StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const override; + StringRef getCPUSpecificTuneName(StringRef Name) const override; + Optional<unsigned> getCPUCacheLineSize() const override; bool validateAsmConstraint(const char *&Name, @@ -412,9 +419,9 @@ public: RegParmMax = 3; // Use fpret for all types. - RealTypeUsesObjCFPRet = - ((1 << (int)FloatModeKind::Float) | (1 << (int)FloatModeKind::Double) | - (1 << (int)FloatModeKind::LongDouble)); + RealTypeUsesObjCFPRetMask = + (int)(FloatModeKind::Float | FloatModeKind::Double | + FloatModeKind::LongDouble); // x86-32 has atomics up to 8 bytes MaxAtomicPromoteWidth = 64; @@ -471,13 +478,13 @@ public: NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} - unsigned getFloatEvalMethod() const override { + LangOptions::FPEvalMethodKind getFPEvalMethod() const override { VersionTuple OsVersion = getTriple().getOSVersion(); // New NetBSD uses the default rounding mode. if (OsVersion >= VersionTuple(6, 99, 26) || OsVersion.getMajor() == 0) - return X86_32TargetInfo::getFloatEvalMethod(); + return X86_32TargetInfo::getFPEvalMethod(); // NetBSD before 6.99.26 defaults to "double" rounding. - return 1; + return LangOptions::FPEvalMethodKind::FEM_Double; } }; @@ -693,7 +700,7 @@ public: "64-i64:64-f80:128-n8:16:32:64-S128"); // Use fpret only for long double. - RealTypeUsesObjCFPRet = (1 << (int)FloatModeKind::LongDouble); + RealTypeUsesObjCFPRetMask = (int)FloatModeKind::LongDouble; // Use fp2ret for _Complex long double. ComplexLongDoubleUsesFP2Ret = true; |