diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 28cb2fc57ac7..e16bead81b65 100644 --- a/contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -3880,6 +3880,22 @@ bool AMDGPUInstructionSelector::isDSOffset2Legal(Register Base, int64_t Offset0, return KnownBits->signBitIsZero(Base); } +bool AMDGPUInstructionSelector::isUnneededShiftMask(const MachineInstr &MI, + unsigned ShAmtBits) const { + assert(MI.getOpcode() == TargetOpcode::G_AND); + + Optional<APInt> RHS = getIConstantVRegVal(MI.getOperand(2).getReg(), *MRI); + if (!RHS) + return false; + + if (RHS->countTrailingOnes() >= ShAmtBits) + return true; + + const APInt &LHSKnownZeros = + KnownBits->getKnownZeroes(MI.getOperand(1).getReg()); + return (LHSKnownZeros | *RHS).countTrailingOnes() >= ShAmtBits; +} + InstructionSelector::ComplexRendererFns AMDGPUInstructionSelector::selectMUBUFScratchOffset( MachineOperand &Root) const { |
