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-rw-r--r--contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp12
1 files changed, 2 insertions, 10 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index a3a0e9c9b9ac..200e00ee5521 100644
--- a/contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -1586,17 +1586,9 @@ bool SIFoldOperands::tryFoldRegSequence(MachineInstr &MI) {
unsigned OpIdx = Op - &UseMI->getOperand(0);
const MCInstrDesc &InstDesc = UseMI->getDesc();
- const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
- switch (OpInfo.RegClass) {
- case AMDGPU::AV_32RegClassID: LLVM_FALLTHROUGH;
- case AMDGPU::AV_64RegClassID: LLVM_FALLTHROUGH;
- case AMDGPU::AV_96RegClassID: LLVM_FALLTHROUGH;
- case AMDGPU::AV_128RegClassID: LLVM_FALLTHROUGH;
- case AMDGPU::AV_160RegClassID:
- break;
- default:
+ if (!TRI->isVectorSuperClass(
+ TRI->getRegClass(InstDesc.OpInfo[OpIdx].RegClass)))
return false;
- }
const auto *NewDstRC = TRI->getEquivalentAGPRClass(MRI->getRegClass(Reg));
auto Dst = MRI->createVirtualRegister(NewDstRC);