diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.h')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.h | 40 |
1 files changed, 28 insertions, 12 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.h index fc5e5be03541..dd9ea2b53ca2 100644 --- a/contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -78,8 +78,11 @@ private: moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst, MachineDominatorTree *MDT = nullptr) const; - void lowerSelect(SetVectorType &Worklist, MachineInstr &Inst, - MachineDominatorTree *MDT = nullptr) const; + void lowerSelect32(SetVectorType &Worklist, MachineInstr &Inst, + MachineDominatorTree *MDT = nullptr) const; + + void splitSelect64(SetVectorType &Worklist, MachineInstr &Inst, + MachineDominatorTree *MDT = nullptr) const; void lowerScalarAbs(SetVectorType &Worklist, MachineInstr &Inst) const; @@ -122,7 +125,8 @@ private: void addSCCDefUsersToVALUWorklist(MachineOperand &Op, MachineInstr &SCCDefInst, - SetVectorType &Worklist) const; + SetVectorType &Worklist, + Register NewCond = Register()) const; void addSCCDefsToVALUWorklist(MachineOperand &Op, SetVectorType &Worklist) const; @@ -271,11 +275,10 @@ public: MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; - unsigned insertIndirectBranch(MachineBasicBlock &MBB, - MachineBasicBlock &NewDestBB, - const DebugLoc &DL, - int64_t BrOffset, - RegScavenger *RS = nullptr) const override; + void insertIndirectBranch(MachineBasicBlock &MBB, + MachineBasicBlock &NewDestBB, + MachineBasicBlock &RestoreBB, const DebugLoc &DL, + int64_t BrOffset, RegScavenger *RS) const override; bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, @@ -315,6 +318,14 @@ public: Register DstReg, ArrayRef<MachineOperand> Cond, Register TrueReg, Register FalseReg) const; + bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, + Register &SrcReg2, int64_t &CmpMask, + int64_t &CmpValue) const override; + + bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, + Register SrcReg2, int64_t CmpMask, int64_t CmpValue, + const MachineRegisterInfo *MRI) const override; + unsigned getAddressSpaceForPseudoSourceKind( unsigned Kind) const override; @@ -322,16 +333,15 @@ public: areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override; - bool isFoldableCopy(const MachineInstr &MI) const; + static bool isFoldableCopy(const MachineInstr &MI); bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const final; unsigned getMachineCSELookAheadLimit() const override { return 500; } - MachineInstr *convertToThreeAddress(MachineFunction::iterator &MBB, - MachineInstr &MI, - LiveVariables *LV) const override; + MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, + LiveIntervals *LIS) const override; bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, @@ -1036,6 +1046,10 @@ public: ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override; + ScheduleHazardRecognizer * + CreateTargetMIHazardRecognizer(const InstrItineraryData *II, + const ScheduleDAGMI *DAG) const override; + bool isBasicBlockPrologue(const MachineInstr &MI) const override; MachineInstr *createPHIDestinationCopy(MachineBasicBlock &MBB, @@ -1119,6 +1133,8 @@ public: } static unsigned getDSShaderTypeValue(const MachineFunction &MF); + + const TargetSchedModel &getSchedModel() const { return SchedModel; } }; /// \brief Returns true if a reg:subreg pair P has a TRC class |