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Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp')
-rw-r--r--contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp78
1 files changed, 41 insertions, 37 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp b/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp
index bb5336931932..618101755904 100644
--- a/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp
+++ b/contrib/llvm-project/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp
@@ -16,8 +16,8 @@
#include "MCTargetDesc/ARCMCTargetDesc.h"
#include "TargetInfo/ARCTargetInfo.h"
#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCDecoderOps.h"
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
-#include "llvm/MC/MCFixedLenDisassembler.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
@@ -83,41 +83,43 @@ static bool readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
}
template <unsigned B>
-static DecodeStatus DecodeSignedOperand(MCInst &Inst, unsigned InsnS,
- uint64_t Address = 0,
- const void *Decoder = nullptr);
+static DecodeStatus
+DecodeSignedOperand(MCInst &Inst, unsigned InsnS, uint64_t Address = 0,
+ const MCDisassembler *Decoder = nullptr);
template <unsigned B>
-static DecodeStatus DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS,
- uint64_t Address = 0,
- const void *Decoder = nullptr);
+static DecodeStatus
+DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS, uint64_t Address = 0,
+ const MCDisassembler *Decoder = nullptr);
template <unsigned B>
static DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS,
- uint64_t Address, const void *Decoder);
+ uint64_t Address,
+ const MCDisassembler *Decoder);
-static DecodeStatus DecodeMEMrs9(MCInst &, unsigned, uint64_t, const void *);
+static DecodeStatus DecodeMEMrs9(MCInst &, unsigned, uint64_t,
+ const MCDisassembler *);
static DecodeStatus DecodeLdLImmInstruction(MCInst &, uint64_t, uint64_t,
- const void *);
+ const MCDisassembler *);
static DecodeStatus DecodeStLImmInstruction(MCInst &, uint64_t, uint64_t,
- const void *);
+ const MCDisassembler *);
static DecodeStatus DecodeLdRLImmInstruction(MCInst &, uint64_t, uint64_t,
- const void *);
+ const MCDisassembler *);
static DecodeStatus DecodeSOPwithRS12(MCInst &, uint64_t, uint64_t,
- const void *);
+ const MCDisassembler *);
static DecodeStatus DecodeSOPwithRU6(MCInst &, uint64_t, uint64_t,
- const void *);
+ const MCDisassembler *);
static DecodeStatus DecodeCCRU6Instruction(MCInst &, uint64_t, uint64_t,
- const void *);
+ const MCDisassembler *);
static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t, uint64_t,
- const void *);
+ const MCDisassembler *);
static const uint16_t GPR32DecoderTable[] = {
ARC::R0, ARC::R1, ARC::R2, ARC::R3, ARC::R4, ARC::R5, ARC::R6,
@@ -128,7 +130,7 @@ static const uint16_t GPR32DecoderTable[] = {
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
if (RegNo >= 32) {
LLVM_DEBUG(dbgs() << "Not a GPR32 register.");
return MCDisassembler::Fail;
@@ -140,8 +142,8 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
}
static DecodeStatus DecodeGBR32ShortRegister(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const void *Decoder) {
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
// Enumerates registers from ranges [r0-r3],[r12-r15].
if (RegNo > 3)
RegNo += 8; // 4 for r12, etc...
@@ -165,7 +167,7 @@ static unsigned decodeAField(unsigned Insn) {
}
static DecodeStatus DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address,
- const void *Dec) {
+ const MCDisassembler *Dec) {
// We have the 9-bit immediate in the low bits, 6-bit register in high bits.
unsigned S9 = Insn & 0x1ff;
unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9;
@@ -175,17 +177,16 @@ static DecodeStatus DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address,
}
static bool DecodeSymbolicOperand(MCInst &Inst, uint64_t Address,
- uint64_t Value, const void *Decoder) {
+ uint64_t Value,
+ const MCDisassembler *Decoder) {
static const uint64_t AtLeast = 2;
- // TODO: Try to force emitter to use MCDisassembler* instead of void*.
- auto Disassembler = static_cast<const MCDisassembler *>(Decoder);
- return (nullptr != Disassembler &&
- Disassembler->tryAddingSymbolicOperand(Inst, Value, Address, true, 0,
- AtLeast));
+ return (nullptr != Decoder && Decoder->tryAddingSymbolicOperand(
+ Inst, Value, Address, true, 0, AtLeast, 0));
}
static void DecodeSymbolicOperandOff(MCInst &Inst, uint64_t Address,
- uint64_t Offset, const void *Decoder) {
+ uint64_t Offset,
+ const MCDisassembler *Decoder) {
uint64_t NextAddress = Address + Offset;
if (!DecodeSymbolicOperand(Inst, Address, NextAddress, Decoder))
@@ -194,7 +195,8 @@ static void DecodeSymbolicOperandOff(MCInst &Inst, uint64_t Address,
template <unsigned B>
static DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS,
- uint64_t Address, const void *Decoder) {
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
static_assert(B > 0, "field is empty");
DecodeSymbolicOperandOff(Inst, Address, SignExtend32<B>(InsnS), Decoder);
@@ -204,7 +206,7 @@ static DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS,
template <unsigned B>
static DecodeStatus DecodeSignedOperand(MCInst &Inst, unsigned InsnS,
uint64_t /*Address*/,
- const void * /*Decoder*/) {
+ const MCDisassembler * /*Decoder*/) {
static_assert(B > 0, "field is empty");
Inst.addOperand(MCOperand::createImm(
@@ -215,7 +217,7 @@ static DecodeStatus DecodeSignedOperand(MCInst &Inst, unsigned InsnS,
template <unsigned B>
static DecodeStatus DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS,
uint64_t /*Address*/,
- const void * /*Decoder*/) {
+ const MCDisassembler * /*Decoder*/) {
static_assert(B > 0, "field is empty");
const unsigned max = (1u << B) - 1;
@@ -226,7 +228,7 @@ static DecodeStatus DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS,
static DecodeStatus DecodeStLImmInstruction(MCInst &Inst, uint64_t Insn,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
unsigned SrcC, DstB, LImm;
DstB = decodeBField(Insn);
if (DstB != 62) {
@@ -243,7 +245,7 @@ static DecodeStatus DecodeStLImmInstruction(MCInst &Inst, uint64_t Insn,
static DecodeStatus DecodeLdLImmInstruction(MCInst &Inst, uint64_t Insn,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
unsigned DstA, SrcB, LImm;
LLVM_DEBUG(dbgs() << "Decoding LdLImm:\n");
SrcB = decodeBField(Insn);
@@ -261,7 +263,7 @@ static DecodeStatus DecodeLdLImmInstruction(MCInst &Inst, uint64_t Insn,
static DecodeStatus DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
unsigned DstA, SrcB;
LLVM_DEBUG(dbgs() << "Decoding LdRLimm\n");
DstA = decodeAField(Insn);
@@ -278,7 +280,7 @@ static DecodeStatus DecodeLdRLImmInstruction(MCInst &Inst, uint64_t Insn,
static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t Insn,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
LLVM_DEBUG(dbgs() << "Decoding MOV_S h-register\n");
using Field = decltype(Insn);
Field H = fieldFromInstruction(Insn, 5, 3) |
@@ -304,7 +306,7 @@ static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t Insn,
static DecodeStatus DecodeCCRU6Instruction(MCInst &Inst, uint64_t Insn,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
unsigned DstB;
LLVM_DEBUG(dbgs() << "Decoding CCRU6 instruction:\n");
DstB = decodeBField(Insn);
@@ -318,7 +320,8 @@ static DecodeStatus DecodeCCRU6Instruction(MCInst &Inst, uint64_t Insn,
}
static DecodeStatus DecodeSOPwithRU6(MCInst &Inst, uint64_t Insn,
- uint64_t Address, const void *Decoder) {
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
unsigned DstB = decodeBField(Insn);
DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
using Field = decltype(Insn);
@@ -328,7 +331,8 @@ static DecodeStatus DecodeSOPwithRU6(MCInst &Inst, uint64_t Insn,
}
static DecodeStatus DecodeSOPwithRS12(MCInst &Inst, uint64_t Insn,
- uint64_t Address, const void *Decoder) {
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
unsigned DstB = decodeBField(Insn);
DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
using Field = decltype(Insn);
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-12 01:16:20 +0000