diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.h')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.h b/contrib/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.h index 6c2b92de7a1d..f398b01f4186 100644 --- a/contrib/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/contrib/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.h @@ -375,6 +375,14 @@ class VectorType; // Bit position of rounding mode bits in FPSCR. const unsigned RoundingBitsPos = 22; + + // Bits of floating-point status. These are NZCV flags, QC bit and cumulative + // FP exception bits. + const unsigned FPStatusBits = 0xf800009f; + + // Some bits in the FPSCR are not yet defined. They must be preserved when + // modifying the contents. + const unsigned FPReservedBits = 0x00006060; } // namespace ARM /// Define some predicates that are used for node matching. @@ -835,6 +843,8 @@ class VectorType; SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSET_FPMODE(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerRESET_FPMODE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) const; SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, |