diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/contrib/llvm-project/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index fd06bfdf352c..6e259b1baf97 100644 --- a/contrib/llvm-project/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/contrib/llvm-project/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -564,7 +564,7 @@ void ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB, } // End of block was reached. - if (MBB.succ_size() > 0) { + if (!MBB.succ_empty()) { // FIXME: Because of a bug, live registers are sometimes missing from // the successor blocks' live-in sets. This means we can't trust that // information and *always* have to reset at the end of a block. @@ -587,7 +587,7 @@ unsigned ARMLoadStoreOpt::findFreeReg(const TargetRegisterClass &RegClass) { } for (unsigned Reg : RegClassInfo.getOrder(&RegClass)) - if (!LiveRegs.contains(Reg)) + if (LiveRegs.available(MF->getRegInfo(), Reg)) return Reg; return 0; } @@ -2476,8 +2476,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB, } } else { for (unsigned i = 0; i != NumMove; ++i) { - MachineInstr *Op = Ops.back(); - Ops.pop_back(); + MachineInstr *Op = Ops.pop_back_val(); MBB->splice(InsertPos, MBB, Op); } } @@ -2811,6 +2810,7 @@ static MachineInstr *createPostIncLoadStore(MachineInstr *MI, int Offset, .addImm(Offset) .add(MI->getOperand(3)) .add(MI->getOperand(4)) + .add(MI->getOperand(5)) .cloneMemRefs(*MI); case ARMII::AddrModeT2_i8: if (MI->mayLoad()) { |