diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp | 200 |
1 files changed, 167 insertions, 33 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp b/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp index 9dcd370b9f1e..ee0ae08e192f 100644 --- a/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp +++ b/contrib/llvm-project/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp @@ -18,8 +18,8 @@ #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDecoderOps.h" #include "llvm/MC/MCDisassembler/MCDisassembler.h" -#include "llvm/MC/MCFixedLenDisassembler.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/TargetRegistry.h" @@ -36,7 +36,7 @@ class AVRDisassembler : public MCDisassembler { public: AVRDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : MCDisassembler(STI, Ctx) {} - virtual ~AVRDisassembler() {} + virtual ~AVRDisassembler() = default; DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, @@ -66,7 +66,7 @@ static const uint16_t GPRDecoderTable[] = { static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 31) return MCDisassembler::Fail; @@ -77,7 +77,7 @@ static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo > 15) return MCDisassembler::Fail; @@ -86,48 +86,51 @@ static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo, return MCDisassembler::Success; } -static DecodeStatus DecodePTRREGSRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder) { - // Note: this function must be defined but does not seem to be called. - assert(false && "unimplemented: PTRREGS register class"); - return MCDisassembler::Success; -} - static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); + +static DecodeStatus decodeMemri(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder); + +static DecodeStatus decodeLoadStore(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder); #include "AVRGenDisassemblerTables.inc" static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned addr = 0; addr |= fieldFromInstruction(Insn, 0, 4); addr |= fieldFromInstruction(Insn, 9, 2) << 4; @@ -140,7 +143,7 @@ static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address, } static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned addr = 0; addr |= fieldFromInstruction(Insn, 0, 4); addr |= fieldFromInstruction(Insn, 9, 2) << 4; @@ -153,7 +156,7 @@ static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address, } static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned addr = fieldFromInstruction(Insn, 3, 5); unsigned b = fieldFromInstruction(Insn, 0, 3); Inst.addOperand(MCOperand::createImm(addr)); @@ -162,7 +165,8 @@ static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address, } static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Field, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { // Call targets need to be shifted left by one so this needs a custom // decoder. Inst.addOperand(MCOperand::createImm(Field << 1)); @@ -170,7 +174,7 @@ static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Field, } static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned d = fieldFromInstruction(Insn, 4, 5); if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail) @@ -179,7 +183,7 @@ static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address, } static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { if (decodeFRd(Inst, Insn, Address, Decoder) == MCDisassembler::Fail) return MCDisassembler::Fail; Inst.addOperand(MCOperand::createReg(AVR::R31R30)); @@ -187,7 +191,8 @@ static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address, } static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned d = fieldFromInstruction(Insn, 4, 3) + 16; unsigned r = fieldFromInstruction(Insn, 0, 3) + 16; if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == @@ -200,7 +205,8 @@ static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn, } static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned r = fieldFromInstruction(Insn, 4, 4) * 2; unsigned d = fieldFromInstruction(Insn, 0, 4) * 2; if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) == @@ -213,7 +219,7 @@ static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn, } static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned d = fieldFromInstruction(Insn, 4, 2) * 2 + 24; // starts at r24:r25 unsigned k = 0; k |= fieldFromInstruction(Insn, 0, 4); @@ -229,7 +235,8 @@ static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address, } static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn, - uint64_t Address, const void *Decoder) { + uint64_t Address, + const MCDisassembler *Decoder) { unsigned rd = fieldFromInstruction(Insn, 4, 4) + 16; unsigned rr = fieldFromInstruction(Insn, 0, 4) + 16; if (DecodeGPR8RegisterClass(Inst, rd, Address, Decoder) == @@ -241,6 +248,128 @@ static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn, return MCDisassembler::Success; } +static DecodeStatus decodeMemri(MCInst &Inst, unsigned Insn, uint64_t Address, + const MCDisassembler *Decoder) { + // As in the EncoderMethod `AVRMCCodeEmitter::encodeMemri`, the memory + // address is encoded into 7-bit, in which bits 0-5 are the immediate offset, + // and the bit-6 is the pointer register bit (Z=0, Y=1). + if (Insn > 127) + return MCDisassembler::Fail; + + // Append the base register operand. + Inst.addOperand( + MCOperand::createReg((Insn & 0x40) ? AVR::R29R28 : AVR::R31R30)); + // Append the immediate offset operand. + Inst.addOperand(MCOperand::createImm(Insn & 0x3f)); + + return MCDisassembler::Success; +} + +static DecodeStatus decodeLoadStore(MCInst &Inst, unsigned Insn, + uint64_t Address, + const MCDisassembler *Decoder) { + // Get the register will be loaded or stored. + unsigned RegVal = GPRDecoderTable[(Insn >> 4) & 0x1f]; + + // Decode LDD/STD with offset less than 8. + if ((Insn & 0xf000) == 0x8000) { + unsigned RegBase = (Insn & 0x8) ? AVR::R29R28 : AVR::R31R30; + unsigned Offset = Insn & 7; // We need not consider offset > 7. + if ((Insn & 0x200) == 0) { // Decode LDD. + Inst.setOpcode(AVR::LDDRdPtrQ); + Inst.addOperand(MCOperand::createReg(RegVal)); + Inst.addOperand(MCOperand::createReg(RegBase)); + Inst.addOperand(MCOperand::createImm(Offset)); + } else { // Decode STD. + Inst.setOpcode(AVR::STDPtrQRr); + Inst.addOperand(MCOperand::createReg(RegBase)); + Inst.addOperand(MCOperand::createImm(Offset)); + Inst.addOperand(MCOperand::createReg(RegVal)); + } + return MCDisassembler::Success; + } + + // Decode the following 14 instructions. Bit 9 indicates load(0) or store(1), + // bits 8~4 indicate the value register, bits 3-2 indicate the base address + // register (11-X, 10-Y, 00-Z), bits 1~0 indicate the mode (00-basic, + // 01-postinc, 10-predec). + // ST X, Rr : 1001 001r rrrr 1100 + // ST X+, Rr : 1001 001r rrrr 1101 + // ST -X, Rr : 1001 001r rrrr 1110 + // ST Y+, Rr : 1001 001r rrrr 1001 + // ST -Y, Rr : 1001 001r rrrr 1010 + // ST Z+, Rr : 1001 001r rrrr 0001 + // ST -Z, Rr : 1001 001r rrrr 0010 + // LD Rd, X : 1001 000d dddd 1100 + // LD Rd, X+ : 1001 000d dddd 1101 + // LD Rd, -X : 1001 000d dddd 1110 + // LD Rd, Y+ : 1001 000d dddd 1001 + // LD Rd, -Y : 1001 000d dddd 1010 + // LD Rd, Z+ : 1001 000d dddd 0001 + // LD Rd, -Z : 1001 000d dddd 0010 + if ((Insn & 0xfc00) != 0x9000 || (Insn & 0xf) == 0) + return MCDisassembler::Fail; + + // Get the base address register. + unsigned RegBase; + switch (Insn & 0xc) { + case 0xc: + RegBase = AVR::R27R26; + break; + case 0x8: + RegBase = AVR::R29R28; + break; + case 0x0: + RegBase = AVR::R31R30; + break; + default: + return MCDisassembler::Fail; + } + + // Set the opcode. + switch (Insn & 0x203) { + case 0x200: + Inst.setOpcode(AVR::STPtrRr); + Inst.addOperand(MCOperand::createReg(RegBase)); + Inst.addOperand(MCOperand::createReg(RegVal)); + return MCDisassembler::Success; + case 0x201: + Inst.setOpcode(AVR::STPtrPiRr); + break; + case 0x202: + Inst.setOpcode(AVR::STPtrPdRr); + break; + case 0: + Inst.setOpcode(AVR::LDRdPtr); + Inst.addOperand(MCOperand::createReg(RegVal)); + Inst.addOperand(MCOperand::createReg(RegBase)); + return MCDisassembler::Success; + case 1: + Inst.setOpcode(AVR::LDRdPtrPi); + break; + case 2: + Inst.setOpcode(AVR::LDRdPtrPd); + break; + default: + return MCDisassembler::Fail; + } + + // Build postinc/predec machine instructions. + if ((Insn & 0x200) == 0) { // This is a load instruction. + Inst.addOperand(MCOperand::createReg(RegVal)); + Inst.addOperand(MCOperand::createReg(RegBase)); + Inst.addOperand(MCOperand::createReg(RegBase)); + } else { // This is a store instruction. + Inst.addOperand(MCOperand::createReg(RegBase)); + Inst.addOperand(MCOperand::createReg(RegBase)); + Inst.addOperand(MCOperand::createReg(RegVal)); + // STPtrPiRr and STPtrPdRr have an extra immediate operand. + Inst.addOperand(MCOperand::createImm(1)); + } + + return MCDisassembler::Success; +} + static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn) { if (Bytes.size() < 2) { @@ -299,7 +428,12 @@ DecodeStatus AVRDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, // Try to auto-decode a 16-bit instruction. Result = decodeInstruction(getDecoderTable(Size), Instr, Insn, Address, this, STI); + if (Result != MCDisassembler::Fail) + return Result; + // Try to decode to a load/store instruction. ST/LD need a specified + // DecoderMethod, as they already have a specified PostEncoderMethod. + Result = decodeLoadStore(Instr, Insn, Address, this); if (Result != MCDisassembler::Fail) return Result; } @@ -323,4 +457,4 @@ DecodeStatus AVRDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, } typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); |