diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/Mips')
8 files changed, 76 insertions, 23 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/Mips64InstrInfo.td b/contrib/llvm-project/llvm/lib/Target/Mips/Mips64InstrInfo.td index ac679c4c01bc..c0e7eef8dd9d 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/contrib/llvm-project/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -164,20 +164,20 @@ def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>, GPR_64; /// Shift Instructions let AdditionalPredicates = [NotInMicroMips] in { - def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, + def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, mshl_64, immZExt6>, SRA_FM<0x38, 0>, ISA_MIPS3; - def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, + def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, msrl_64, immZExt6>, SRA_FM<0x3a, 0>, ISA_MIPS3; - def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, + def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, msra_64, immZExt6>, SRA_FM<0x3b, 0>, ISA_MIPS3; - def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>, + def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, mshl_64>, SRLV_FM<0x14, 0>, ISA_MIPS3; - def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>, + def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, msra_64>, SRLV_FM<0x17, 0>, ISA_MIPS3; - def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>, + def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, msrl_64>, SRLV_FM<0x16, 0>, ISA_MIPS3; def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>, SRA_FM<0x3c, 0>, ISA_MIPS3; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp index 77ce8ba890a8..01b41f3b2159 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -22,6 +22,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/CodeGen/StackProtector.h" #include "llvm/IR/CFG.h" @@ -31,6 +32,7 @@ #include "llvm/IR/Type.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/KnownBits.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetMachine.h" using namespace llvm; @@ -324,6 +326,24 @@ bool MipsDAGToDAGISel::SelectInlineAsmMemoryOperand( return true; } +bool MipsDAGToDAGISel::isUnneededShiftMask(SDNode *N, + unsigned ShAmtBits) const { + assert(N->getOpcode() == ISD::AND && "Unexpected opcode"); + + const APInt &RHS = N->getConstantOperandAPInt(1); + if (RHS.countr_one() >= ShAmtBits) { + LLVM_DEBUG( + dbgs() + << DEBUG_TYPE + << " Need optimize 'and & shl/srl/sra' and operand value bits is " + << RHS.countr_one() << "\n"); + return true; + } + + KnownBits Known = CurDAG->computeKnownBits(N->getOperand(0)); + return (Known.Zero | RHS).countr_one() >= ShAmtBits; +} + char MipsDAGToDAGISel::ID = 0; INITIALIZE_PASS(MipsDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelDAGToDAG.h b/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelDAGToDAG.h index e41cb08712ca..52207d0f6284 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelDAGToDAG.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelDAGToDAG.h @@ -143,6 +143,7 @@ private: bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector<SDValue> &OutOps) override; + bool isUnneededShiftMask(SDNode *N, unsigned ShAmtBits) const; }; } diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.cpp index a0cab8024386..483eba4e4f47 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -2508,7 +2508,7 @@ SDValue MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const { SDValue MipsTargetLowering:: lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { // check the depth - if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) { + if (Op.getConstantOperandVal(0) != 0) { DAG.getContext()->emitError( "return address can be determined only for current frame"); return SDValue(); @@ -2529,7 +2529,7 @@ SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, return SDValue(); // check the depth - if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) { + if (Op.getConstantOperandVal(0) != 0) { DAG.getContext()->emitError( "return address can be determined only for current frame"); return SDValue(); diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrCompiler.td b/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrCompiler.td new file mode 100644 index 000000000000..8ae3d71978b1 --- /dev/null +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrCompiler.td @@ -0,0 +1,33 @@ +//===- MipsInstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the various pseudo instructions used by the compiler, +// as well as Pat patterns used during instruction selection. +// +//===----------------------------------------------------------------------===// + + +def shiftMask_32 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ + return isUnneededShiftMask(N, 5); +}]>; + +def shiftMask_64 : PatFrag<(ops node:$src0), (and node:$src0, imm), [{ + return isUnneededShiftMask(N, 6); +}]>; + +foreach width = [32, 64] in { +defvar shiftMask = !cast<SDPatternOperator>("shiftMask_"#width); +def mshl_#width : PatFrags<(ops node:$src0, node:$src1), + [(shl node:$src0, node:$src1), (shl node:$src0, (shiftMask node:$src1))]>; + +def msrl_#width : PatFrags<(ops node:$src0, node:$src1), + [(srl node:$src0, node:$src1), (srl node:$src0, (shiftMask node:$src1))]>; + +def msra_#width : PatFrags<(ops node:$src0, node:$src1), + [(sra node:$src0, node:$src1), (sra node:$src0, (shiftMask node:$src1))]>; +} diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.td b/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.td index 75270857ea13..4b6f4b22e71b 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -14,6 +14,7 @@ //===----------------------------------------------------------------------===// // Mips profiles and nodes //===----------------------------------------------------------------------===// +include "MipsInstrCompiler.td" def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, @@ -2079,17 +2080,17 @@ let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in { /// Shift Instructions - def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl, + def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, mshl_32, immZExt5>, SRA_FM<0, 0>, ISA_MIPS1; - def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl, + def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, msrl_32, immZExt5>, SRA_FM<2, 0>, ISA_MIPS1; - def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra, + def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, msra_32, immZExt5>, SRA_FM<3, 0>, ISA_MIPS1; - def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>, + def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, mshl_32>, SRLV_FM<4, 0>, ISA_MIPS1; - def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>, + def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, msrl_32>, SRLV_FM<6, 0>, ISA_MIPS1; - def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>, + def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, msra_32>, SRLV_FM<7, 0>, ISA_MIPS1; // Rotate Instructions diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 8c865afd4207..0ed87ee0809a 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -831,8 +831,7 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { } case ISD::INTRINSIC_W_CHAIN: { - const unsigned IntrinsicOpcode = - cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); + const unsigned IntrinsicOpcode = Node->getConstantOperandVal(1); switch (IntrinsicOpcode) { default: break; @@ -885,7 +884,7 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { } case ISD::INTRINSIC_WO_CHAIN: { - switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) { + switch (Node->getConstantOperandVal(0)) { default: break; @@ -901,8 +900,7 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { } case ISD::INTRINSIC_VOID: { - const unsigned IntrinsicOpcode = - cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); + const unsigned IntrinsicOpcode = Node->getConstantOperandVal(1); switch (IntrinsicOpcode) { default: break; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEISelLowering.cpp index 5c34067c8888..e9788fa7ed73 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEISelLowering.cpp @@ -1519,7 +1519,7 @@ static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) { SDLoc DL(Op); EVT ResTy = Op->getValueType(0); APInt BitImm = APInt(ResTy.getScalarSizeInBits(), 1) - << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue(); + << Op->getConstantOperandAPInt(2); SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy); return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask); @@ -1528,7 +1528,7 @@ static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) { SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); - unsigned Intrinsic = cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue(); + unsigned Intrinsic = Op->getConstantOperandVal(0); switch (Intrinsic) { default: return SDValue(); @@ -2300,7 +2300,7 @@ static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const { - unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); + unsigned Intr = Op->getConstantOperandVal(1); switch (Intr) { default: return SDValue(); @@ -2375,7 +2375,7 @@ static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const { - unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); + unsigned Intr = Op->getConstantOperandVal(1); switch (Intr) { default: return SDValue(); |