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Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp')
-rw-r--r--contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp98
1 files changed, 54 insertions, 44 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
index 5a12c3f22dee..d3d720054f16 100644
--- a/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ b/contrib/llvm-project/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -8,8 +8,8 @@
#include "MCTargetDesc/PPCMCTargetDesc.h"
#include "TargetInfo/PowerPCTargetInfo.h"
+#include "llvm/MC/MCDecoderOps.h"
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
-#include "llvm/MC/MCFixedLenDisassembler.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
@@ -64,14 +64,14 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler() {
static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm,
uint64_t /*Address*/,
- const void * /*Decoder*/) {
+ const MCDisassembler * /*Decoder*/) {
Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));
return MCDisassembler::Success;
}
static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm,
uint64_t /*Address*/,
- const void * /*Decoder*/) {
+ const MCDisassembler * /*Decoder*/) {
int32_t Offset = SignExtend32<24>(Imm);
Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
@@ -90,85 +90,85 @@ static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, CRRegs);
}
static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
- uint64_t Address,
- const void *Decoder) {
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, CRBITRegs);
}
static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, FRegs);
}
static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, FRegs);
}
static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, VFRegs);
}
static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, VRegs);
}
static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, VSRegs);
}
static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
- uint64_t Address,
- const void *Decoder) {
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, VSFRegs);
}
static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
- uint64_t Address,
- const void *Decoder) {
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, VSSRegs);
}
static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, RRegs);
}
-static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
- uint64_t Address,
- const void *Decoder) {
+static DecodeStatus
+DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address,
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
}
static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, XRegs);
}
static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, XRegs);
}
-static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo,
- uint64_t Address,
- const void *Decoder) {
+static DecodeStatus
+DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address,
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
}
@@ -176,44 +176,47 @@ static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo,
#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
- uint64_t Address,
- const void *Decoder) {
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, SPERegs);
}
static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, ACCRegs);
}
static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, VSRpRegs);
}
#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
-template<unsigned N>
+template <unsigned N>
static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
- int64_t Address, const void *Decoder) {
+ int64_t Address,
+ const MCDisassembler *Decoder) {
assert(isUInt<N>(Imm) && "Invalid immediate");
Inst.addOperand(MCOperand::createImm(Imm));
return MCDisassembler::Success;
}
-template<unsigned N>
+template <unsigned N>
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
- int64_t Address, const void *Decoder) {
+ int64_t Address,
+ const MCDisassembler *Decoder) {
assert(isUInt<N>(Imm) && "Invalid immediate");
Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
return MCDisassembler::Success;
}
static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm,
- int64_t Address, const void *Decoder) {
+ int64_t Address,
+ const MCDisassembler *Decoder) {
if (Imm != 0)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(Imm));
@@ -222,7 +225,7 @@ static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm,
static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
if (RegNo & 1)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1]));
@@ -230,7 +233,8 @@ static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo,
}
static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
- int64_t Address, const void *Decoder) {
+ int64_t Address,
+ const MCDisassembler *Decoder) {
// Decode the memri field (imm, reg), which has the low 16-bits as the
// displacement and the next 5 bits as the register #.
@@ -265,7 +269,8 @@ static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
}
static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
- int64_t Address, const void *Decoder) {
+ int64_t Address,
+ const MCDisassembler *Decoder) {
// Decode the memrix field (imm, reg), which has the low 14-bits as the
// displacement and the next 5 bits as the register #.
@@ -287,7 +292,7 @@ static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
static DecodeStatus decodeMemRIHashOperands(MCInst &Inst, uint64_t Imm,
int64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
// Decode the memrix field for a hash store or hash check operation.
// The field is composed of a register and an immediate value that is 6 bits
// and covers the range -8 to -512. The immediate is always negative and 2s
@@ -303,7 +308,8 @@ static DecodeStatus decodeMemRIHashOperands(MCInst &Inst, uint64_t Imm,
}
static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm,
- int64_t Address, const void *Decoder) {
+ int64_t Address,
+ const MCDisassembler *Decoder) {
// Decode the memrix16 field (imm, reg), which has the low 12-bits as the
// displacement with 16-byte aligned, and the next 5 bits as the register #.
@@ -319,7 +325,7 @@ static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm,
static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm,
int64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
// Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the
// displacement, and the next 5 bits as an immediate 0.
uint64_t Base = Imm >> 34;
@@ -333,7 +339,7 @@ static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm,
static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm,
int64_t Address,
- const void *Decoder) {
+ const MCDisassembler *Decoder) {
// Decode the memri34 field (imm, reg), which has the low 34-bits as the
// displacement, and the next 5 bits as the register #.
uint64_t Base = Imm >> 34;
@@ -347,7 +353,8 @@ static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm,
}
static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm,
- int64_t Address, const void *Decoder) {
+ int64_t Address,
+ const MCDisassembler *Decoder) {
// Decode the spe8disp field (imm, reg), which has the low 5-bits as the
// displacement with 8-byte aligned, and the next 5 bits as the register #.
@@ -362,7 +369,8 @@ static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm,
}
static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm,
- int64_t Address, const void *Decoder) {
+ int64_t Address,
+ const MCDisassembler *Decoder) {
// Decode the spe4disp field (imm, reg), which has the low 5-bits as the
// displacement with 4-byte aligned, and the next 5 bits as the register #.
@@ -377,7 +385,8 @@ static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm,
}
static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm,
- int64_t Address, const void *Decoder) {
+ int64_t Address,
+ const MCDisassembler *Decoder) {
// Decode the spe2disp field (imm, reg), which has the low 5-bits as the
// displacement with 2-byte aligned, and the next 5 bits as the register #.
@@ -392,7 +401,8 @@ static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm,
}
static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
- int64_t Address, const void *Decoder) {
+ int64_t Address,
+ const MCDisassembler *Decoder) {
// The cr bit encoding is 0x80 >> cr_reg_num.
unsigned Zeros = countTrailingZeros(Imm);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 20:40:21 +0000