diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 22c662a79d87..385b3b74c34d 100644 --- a/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/contrib/llvm-project/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -10986,7 +10986,6 @@ SDValue PPCTargetLowering::LowerINTRINSIC_VOID(SDValue Op, switch (cast<ConstantSDNode>(Op.getOperand(ArgStart))->getZExtValue()) { case Intrinsic::ppc_cfence: { assert(ArgStart == 1 && "llvm.ppc.cfence must carry a chain argument."); - assert(Subtarget.isPPC64() && "Only 64-bit is supported for now."); SDValue Val = Op.getOperand(ArgStart + 1); EVT Ty = Val.getValueType(); if (Ty == MVT::i128) { @@ -10994,9 +10993,11 @@ SDValue PPCTargetLowering::LowerINTRINSIC_VOID(SDValue Op, // ordering? Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, Val); } + unsigned Opcode = Subtarget.isPPC64() ? PPC::CFENCE8 : PPC::CFENCE; + EVT FTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; return SDValue( - DAG.getMachineNode(PPC::CFENCE8, DL, MVT::Other, - DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Val), + DAG.getMachineNode(Opcode, DL, MVT::Other, + DAG.getNode(ISD::ANY_EXTEND, DL, FTy, Val), Op.getOperand(0)), 0); } @@ -11827,7 +11828,7 @@ Instruction *PPCTargetLowering::emitTrailingFence(IRBuilderBase &Builder, // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification. - if (isa<LoadInst>(Inst) && Subtarget.isPPC64()) + if (isa<LoadInst>(Inst)) return Builder.CreateCall( Intrinsic::getDeclaration( Builder.GetInsertBlock()->getParent()->getParent(), |