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-rw-r--r--contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 00b4751905f6..30ed36525e29 100644
--- a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -113,6 +113,15 @@ enum {
UsesVXRMShift = HasRoundModeOpShift + 1,
UsesVXRMMask = 1 << UsesVXRMShift,
+
+ // Indicates whether these instructions can partially overlap between source
+ // registers and destination registers according to the vector spec.
+ // 0 -> not a vector pseudo
+ // 1 -> default value for vector pseudos. not widening or narrowing.
+ // 2 -> narrowing case
+ // 3 -> widening case
+ TargetOverlapConstraintTypeShift = UsesVXRMShift + 1,
+ TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,
};
enum VLMUL : uint8_t {