diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc')
12 files changed, 757 insertions, 32 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h index 090132af3585..56991ccf010a 100644 --- a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h @@ -9,9 +9,9 @@ #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVASMBACKEND_H +#include "MCTargetDesc/RISCVBaseInfo.h" #include "MCTargetDesc/RISCVFixupKinds.h" #include "MCTargetDesc/RISCVMCTargetDesc.h" -#include "Utils/RISCVBaseInfo.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCSubtargetInfo.h" diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp new file mode 100644 index 000000000000..fa36234d0f5f --- /dev/null +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp @@ -0,0 +1,142 @@ +//===-- RISCVBaseInfo.cpp - Top level definitions for RISCV MC ------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains small standalone enum definitions for the RISCV target +// useful for the compiler back-end and the MC libraries. +// +//===----------------------------------------------------------------------===// + +#include "RISCVBaseInfo.h" +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/Triple.h" +#include "llvm/Support/raw_ostream.h" + +namespace llvm { +namespace RISCVSysReg { +#define GET_SysRegsList_IMPL +#include "RISCVGenSearchableTables.inc" +} // namespace RISCVSysReg + +namespace RISCVABI { +ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, + StringRef ABIName) { + auto TargetABI = getTargetABI(ABIName); + bool IsRV64 = TT.isArch64Bit(); + bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; + + if (!ABIName.empty() && TargetABI == ABI_Unknown) { + errs() + << "'" << ABIName + << "' is not a recognized ABI for this target (ignoring target-abi)\n"; + } else if (ABIName.startswith("ilp32") && IsRV64) { + errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring " + "target-abi)\n"; + TargetABI = ABI_Unknown; + } else if (ABIName.startswith("lp64") && !IsRV64) { + errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring " + "target-abi)\n"; + TargetABI = ABI_Unknown; + } else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) { + // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser + errs() + << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n"; + TargetABI = ABI_Unknown; + } + + if (TargetABI != ABI_Unknown) + return TargetABI; + + // For now, default to the ilp32/ilp32e/lp64 ABI if no explicit ABI is given + // or an invalid/unrecognised string is given. In the future, it might be + // worth changing this to default to ilp32f/lp64f and ilp32d/lp64d when + // hardware support for floating point is present. + if (IsRV32E) + return ABI_ILP32E; + if (IsRV64) + return ABI_LP64; + return ABI_ILP32; +} + +ABI getTargetABI(StringRef ABIName) { + auto TargetABI = StringSwitch<ABI>(ABIName) + .Case("ilp32", ABI_ILP32) + .Case("ilp32f", ABI_ILP32F) + .Case("ilp32d", ABI_ILP32D) + .Case("ilp32e", ABI_ILP32E) + .Case("lp64", ABI_LP64) + .Case("lp64f", ABI_LP64F) + .Case("lp64d", ABI_LP64D) + .Default(ABI_Unknown); + return TargetABI; +} + +// To avoid the BP value clobbered by a function call, we need to choose a +// callee saved register to save the value. RV32E only has X8 and X9 as callee +// saved registers and X8 will be used as fp. So we choose X9 as bp. +MCRegister getBPReg() { return RISCV::X9; } + +// Returns the register holding shadow call stack pointer. +MCRegister getSCSPReg() { return RISCV::X18; } + +} // namespace RISCVABI + +namespace RISCVFeatures { + +void validate(const Triple &TT, const FeatureBitset &FeatureBits) { + if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E]) + report_fatal_error("RV32E can't be enabled for an RV64 target"); +} + +} // namespace RISCVFeatures + +namespace RISCVVPseudosTable { + +#define GET_RISCVVPseudosTable_IMPL +#include "RISCVGenSearchableTables.inc" + +} // namespace RISCVVPseudosTable + +void RISCVVType::printVType(unsigned VType, raw_ostream &OS) { + RISCVVSEW VSEW = getVSEW(VType); + RISCVVLMUL VLMUL = getVLMUL(VType); + + unsigned Sew = 1 << (static_cast<unsigned>(VSEW) + 3); + OS << "e" << Sew; + + switch (VLMUL) { + case RISCVVLMUL::LMUL_RESERVED: + llvm_unreachable("Unexpected LMUL value!"); + case RISCVVLMUL::LMUL_1: + case RISCVVLMUL::LMUL_2: + case RISCVVLMUL::LMUL_4: + case RISCVVLMUL::LMUL_8: { + unsigned LMul = 1 << static_cast<unsigned>(VLMUL); + OS << ",m" << LMul; + break; + } + case RISCVVLMUL::LMUL_F2: + case RISCVVLMUL::LMUL_F4: + case RISCVVLMUL::LMUL_F8: { + unsigned LMul = 1 << (8 - static_cast<unsigned>(VLMUL)); + OS << ",mf" << LMul; + break; + } + } + + if (isTailAgnostic(VType)) + OS << ",ta"; + else + OS << ",tu"; + + if (isMaskAgnostic(VType)) + OS << ",ma"; + else + OS << ",mu"; +} + +} // namespace llvm diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h new file mode 100644 index 000000000000..6c9f860c204c --- /dev/null +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -0,0 +1,406 @@ +//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains small standalone enum definitions for the RISCV target +// useful for the compiler back-end and the MC libraries. +// +//===----------------------------------------------------------------------===// +#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H +#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H + +#include "MCTargetDesc/RISCVMCTargetDesc.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/ADT/StringSwitch.h" +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/MC/SubtargetFeature.h" +#include "llvm/Support/MachineValueType.h" + +namespace llvm { + +// RISCVII - This namespace holds all of the target specific flags that +// instruction info tracks. All definitions must match RISCVInstrFormats.td. +namespace RISCVII { +enum { + InstFormatPseudo = 0, + InstFormatR = 1, + InstFormatR4 = 2, + InstFormatI = 3, + InstFormatS = 4, + InstFormatB = 5, + InstFormatU = 6, + InstFormatJ = 7, + InstFormatCR = 8, + InstFormatCI = 9, + InstFormatCSS = 10, + InstFormatCIW = 11, + InstFormatCL = 12, + InstFormatCS = 13, + InstFormatCA = 14, + InstFormatCB = 15, + InstFormatCJ = 16, + InstFormatOther = 17, + + InstFormatMask = 31, + + ConstraintShift = 5, + ConstraintMask = 0b111 << ConstraintShift, + + VLMulShift = ConstraintShift + 3, + VLMulMask = 0b111 << VLMulShift, + + // Do we need to add a dummy mask op when converting RVV Pseudo to MCInst. + HasDummyMaskOpShift = VLMulShift + 3, + HasDummyMaskOpMask = 1 << HasDummyMaskOpShift, + + // Does this instruction only update element 0 the destination register. + WritesElement0Shift = HasDummyMaskOpShift + 1, + WritesElement0Mask = 1 << WritesElement0Shift, + + // Does this instruction have a merge operand that must be removed when + // converting to MCInst. It will be the first explicit use operand. Used by + // RVV Pseudos. + HasMergeOpShift = WritesElement0Shift + 1, + HasMergeOpMask = 1 << HasMergeOpShift, + + // Does this instruction have a SEW operand. It will be the last explicit + // operand. Used by RVV Pseudos. + HasSEWOpShift = HasMergeOpShift + 1, + HasSEWOpMask = 1 << HasSEWOpShift, + + // Does this instruction have a VL operand. It will be the second to last + // explicit operand. Used by RVV Pseudos. + HasVLOpShift = HasSEWOpShift + 1, + HasVLOpMask = 1 << HasVLOpShift, +}; + +// Match with the definitions in RISCVInstrFormatsV.td +enum RVVConstraintType { + NoConstraint = 0, + VS2Constraint = 0b001, + VS1Constraint = 0b010, + VMConstraint = 0b100, +}; + +// RISC-V Specific Machine Operand Flags +enum { + MO_None = 0, + MO_CALL = 1, + MO_PLT = 2, + MO_LO = 3, + MO_HI = 4, + MO_PCREL_LO = 5, + MO_PCREL_HI = 6, + MO_GOT_HI = 7, + MO_TPREL_LO = 8, + MO_TPREL_HI = 9, + MO_TPREL_ADD = 10, + MO_TLS_GOT_HI = 11, + MO_TLS_GD_HI = 12, + + // Used to differentiate between target-specific "direct" flags and "bitmask" + // flags. A machine operand can only have one "direct" flag, but can have + // multiple "bitmask" flags. + MO_DIRECT_FLAG_MASK = 15 +}; +} // namespace RISCVII + +namespace RISCVOp { +enum OperandType : unsigned { + OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET, + OPERAND_UIMM4 = OPERAND_FIRST_RISCV_IMM, + OPERAND_UIMM5, + OPERAND_UIMM12, + OPERAND_SIMM12, + OPERAND_UIMM20, + OPERAND_UIMMLOG2XLEN, + OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN +}; +} // namespace RISCVOp + +// Describes the predecessor/successor bits used in the FENCE instruction. +namespace RISCVFenceField { +enum FenceField { + I = 8, + O = 4, + R = 2, + W = 1 +}; +} + +// Describes the supported floating point rounding mode encodings. +namespace RISCVFPRndMode { +enum RoundingMode { + RNE = 0, + RTZ = 1, + RDN = 2, + RUP = 3, + RMM = 4, + DYN = 7, + Invalid +}; + +inline static StringRef roundingModeToString(RoundingMode RndMode) { + switch (RndMode) { + default: + llvm_unreachable("Unknown floating point rounding mode"); + case RISCVFPRndMode::RNE: + return "rne"; + case RISCVFPRndMode::RTZ: + return "rtz"; + case RISCVFPRndMode::RDN: + return "rdn"; + case RISCVFPRndMode::RUP: + return "rup"; + case RISCVFPRndMode::RMM: + return "rmm"; + case RISCVFPRndMode::DYN: + return "dyn"; + } +} + +inline static RoundingMode stringToRoundingMode(StringRef Str) { + return StringSwitch<RoundingMode>(Str) + .Case("rne", RISCVFPRndMode::RNE) + .Case("rtz", RISCVFPRndMode::RTZ) + .Case("rdn", RISCVFPRndMode::RDN) + .Case("rup", RISCVFPRndMode::RUP) + .Case("rmm", RISCVFPRndMode::RMM) + .Case("dyn", RISCVFPRndMode::DYN) + .Default(RISCVFPRndMode::Invalid); +} + +inline static bool isValidRoundingMode(unsigned Mode) { + switch (Mode) { + default: + return false; + case RISCVFPRndMode::RNE: + case RISCVFPRndMode::RTZ: + case RISCVFPRndMode::RDN: + case RISCVFPRndMode::RUP: + case RISCVFPRndMode::RMM: + case RISCVFPRndMode::DYN: + return true; + } +} +} // namespace RISCVFPRndMode + +namespace RISCVSysReg { +struct SysReg { + const char *Name; + unsigned Encoding; + const char *AltName; + // FIXME: add these additional fields when needed. + // Privilege Access: Read, Write, Read-Only. + // unsigned ReadWrite; + // Privilege Mode: User, System or Machine. + // unsigned Mode; + // Check field name. + // unsigned Extra; + // Register number without the privilege bits. + // unsigned Number; + FeatureBitset FeaturesRequired; + bool isRV32Only; + + bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const { + // Not in 32-bit mode. + if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit]) + return false; + // No required feature associated with the system register. + if (FeaturesRequired.none()) + return true; + return (FeaturesRequired & ActiveFeatures) == FeaturesRequired; + } +}; + +#define GET_SysRegsList_DECL +#include "RISCVGenSearchableTables.inc" +} // end namespace RISCVSysReg + +namespace RISCVABI { + +enum ABI { + ABI_ILP32, + ABI_ILP32F, + ABI_ILP32D, + ABI_ILP32E, + ABI_LP64, + ABI_LP64F, + ABI_LP64D, + ABI_Unknown +}; + +// Returns the target ABI, or else a StringError if the requested ABIName is +// not supported for the given TT and FeatureBits combination. +ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, + StringRef ABIName); + +ABI getTargetABI(StringRef ABIName); + +// Returns the register used to hold the stack pointer after realignment. +MCRegister getBPReg(); + +// Returns the register holding shadow call stack pointer. +MCRegister getSCSPReg(); + +} // namespace RISCVABI + +namespace RISCVFeatures { + +// Validates if the given combination of features are valid for the target +// triple. Exits with report_fatal_error if not. +void validate(const Triple &TT, const FeatureBitset &FeatureBits); + +} // namespace RISCVFeatures + +namespace RISCVVMVTs { + +constexpr MVT vint8mf8_t = MVT::nxv1i8; +constexpr MVT vint8mf4_t = MVT::nxv2i8; +constexpr MVT vint8mf2_t = MVT::nxv4i8; +constexpr MVT vint8m1_t = MVT::nxv8i8; +constexpr MVT vint8m2_t = MVT::nxv16i8; +constexpr MVT vint8m4_t = MVT::nxv32i8; +constexpr MVT vint8m8_t = MVT::nxv64i8; + +constexpr MVT vint16mf4_t = MVT::nxv1i16; +constexpr MVT vint16mf2_t = MVT::nxv2i16; +constexpr MVT vint16m1_t = MVT::nxv4i16; +constexpr MVT vint16m2_t = MVT::nxv8i16; +constexpr MVT vint16m4_t = MVT::nxv16i16; +constexpr MVT vint16m8_t = MVT::nxv32i16; + +constexpr MVT vint32mf2_t = MVT::nxv1i32; +constexpr MVT vint32m1_t = MVT::nxv2i32; +constexpr MVT vint32m2_t = MVT::nxv4i32; +constexpr MVT vint32m4_t = MVT::nxv8i32; +constexpr MVT vint32m8_t = MVT::nxv16i32; + +constexpr MVT vint64m1_t = MVT::nxv1i64; +constexpr MVT vint64m2_t = MVT::nxv2i64; +constexpr MVT vint64m4_t = MVT::nxv4i64; +constexpr MVT vint64m8_t = MVT::nxv8i64; + +constexpr MVT vfloat16mf4_t = MVT::nxv1f16; +constexpr MVT vfloat16mf2_t = MVT::nxv2f16; +constexpr MVT vfloat16m1_t = MVT::nxv4f16; +constexpr MVT vfloat16m2_t = MVT::nxv8f16; +constexpr MVT vfloat16m4_t = MVT::nxv16f16; +constexpr MVT vfloat16m8_t = MVT::nxv32f16; + +constexpr MVT vfloat32mf2_t = MVT::nxv1f32; +constexpr MVT vfloat32m1_t = MVT::nxv2f32; +constexpr MVT vfloat32m2_t = MVT::nxv4f32; +constexpr MVT vfloat32m4_t = MVT::nxv8f32; +constexpr MVT vfloat32m8_t = MVT::nxv16f32; + +constexpr MVT vfloat64m1_t = MVT::nxv1f64; +constexpr MVT vfloat64m2_t = MVT::nxv2f64; +constexpr MVT vfloat64m4_t = MVT::nxv4f64; +constexpr MVT vfloat64m8_t = MVT::nxv8f64; + +constexpr MVT vbool1_t = MVT::nxv64i1; +constexpr MVT vbool2_t = MVT::nxv32i1; +constexpr MVT vbool4_t = MVT::nxv16i1; +constexpr MVT vbool8_t = MVT::nxv8i1; +constexpr MVT vbool16_t = MVT::nxv4i1; +constexpr MVT vbool32_t = MVT::nxv2i1; +constexpr MVT vbool64_t = MVT::nxv1i1; + +} // namespace RISCVVMVTs + +enum class RISCVVSEW { + SEW_8 = 0, + SEW_16, + SEW_32, + SEW_64, + SEW_128, + SEW_256, + SEW_512, + SEW_1024, +}; + +enum class RISCVVLMUL { + LMUL_1 = 0, + LMUL_2, + LMUL_4, + LMUL_8, + LMUL_RESERVED, + LMUL_F8, + LMUL_F4, + LMUL_F2 +}; + +namespace RISCVVType { +// Is this a SEW value that can be encoded into the VTYPE format. +inline static bool isValidSEW(unsigned SEW) { + return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024; +} + +// Is this a LMUL value that can be encoded into the VTYPE format. +inline static bool isValidLMUL(unsigned LMUL, bool Fractional) { + return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1); +} + +// Encode VTYPE into the binary format used by the the VSETVLI instruction which +// is used by our MC layer representation. +// +// Bits | Name | Description +// -----+------------+------------------------------------------------ +// 7 | vma | Vector mask agnostic +// 6 | vta | Vector tail agnostic +// 5:3 | vsew[2:0] | Standard element width (SEW) setting +// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting +inline static unsigned encodeVTYPE(RISCVVLMUL VLMUL, RISCVVSEW VSEW, + bool TailAgnostic, bool MaskAgnostic) { + unsigned VLMULBits = static_cast<unsigned>(VLMUL); + unsigned VSEWBits = static_cast<unsigned>(VSEW); + unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7); + if (TailAgnostic) + VTypeI |= 0x40; + if (MaskAgnostic) + VTypeI |= 0x80; + + return VTypeI; +} + +inline static RISCVVLMUL getVLMUL(unsigned VType) { + unsigned VLMUL = VType & 0x7; + return static_cast<RISCVVLMUL>(VLMUL); +} + +inline static RISCVVSEW getVSEW(unsigned VType) { + unsigned VSEW = (VType >> 3) & 0x7; + return static_cast<RISCVVSEW>(VSEW); +} + +inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; } + +inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; } + +void printVType(unsigned VType, raw_ostream &OS); + +} // namespace RISCVVType + +namespace RISCVVPseudosTable { + +struct PseudoInfo { +#include "MCTargetDesc/RISCVBaseInfo.h" + uint16_t Pseudo; + uint16_t BaseInstr; +}; + +using namespace RISCV; + +#define GET_RISCVVPseudosTable_DECL +#include "RISCVGenSearchableTables.inc" + +} // end namespace RISCVVPseudosTable + +} // namespace llvm + +#endif diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp index 079dc919928a..7df454be8729 100644 --- a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp @@ -11,9 +11,9 @@ //===----------------------------------------------------------------------===// #include "RISCVELFStreamer.h" -#include "MCTargetDesc/RISCVAsmBackend.h" +#include "RISCVAsmBackend.h" +#include "RISCVBaseInfo.h" #include "RISCVMCTargetDesc.h" -#include "Utils/RISCVBaseInfo.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCSectionELF.h" diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp index eae3e13dbe40..5f8d6e137518 100644 --- a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -11,8 +11,8 @@ //===----------------------------------------------------------------------===// #include "RISCVInstPrinter.h" -#include "MCTargetDesc/RISCVMCExpr.h" -#include "Utils/RISCVBaseInfo.h" +#include "RISCVBaseInfo.h" +#include "RISCVMCExpr.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" @@ -102,6 +102,24 @@ void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, MO.getExpr()->print(O, &MAI); } +void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address, + unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { + const MCOperand &MO = MI->getOperand(OpNo); + if (!MO.isImm()) + return printOperand(MI, OpNo, STI, O); + + if (PrintBranchImmAsAddress) { + uint64_t Target = Address + MO.getImm(); + if (!STI.hasFeature(RISCV::Feature64Bit)) + Target &= 0xffffffff; + O << formatHex(Target); + } else { + O << MO.getImm(); + } +} + void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { @@ -147,18 +165,12 @@ void RISCVInstPrinter::printAtomicMemOp(const MCInst *MI, unsigned OpNo, O << "("; printRegName(O, MO.getReg()); O << ")"; - return; } void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { unsigned Imm = MI->getOperand(OpNo).getImm(); - unsigned Sew = (Imm >> 2) & 0x7; - unsigned Lmul = Imm & 0x3; - - Lmul = 0x1 << Lmul; - Sew = 0x1 << (Sew + 3); - O << "e" << Sew << ",m" << Lmul; + RISCVVType::printVType(Imm, O); } void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo, @@ -174,15 +186,6 @@ void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo, O << ".t"; } -void RISCVInstPrinter::printSImm5Plus1(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { - const MCOperand &MO = MI->getOperand(OpNo); - - assert(MO.isImm() && "printSImm5Plus1 can only print constant operands"); - O << MO.getImm() + 1; -} - const char *RISCVInstPrinter::getRegisterName(unsigned RegNo) { return getRegisterName(RegNo, ArchRegNames ? RISCV::NoRegAltName : RISCV::ABIRegAltName); diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h index fdaa00c5f8eb..d078ead2c8ad 100644 --- a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h @@ -32,6 +32,8 @@ public: void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier = nullptr); + void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); void printCSRSystemRegister(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printFenceArg(const MCInst *MI, unsigned OpNo, @@ -44,10 +46,9 @@ public: raw_ostream &O); void printVMaskReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printSImm5Plus1(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); // Autogenerated by tblgen. + std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O); bool printAliasInstr(const MCInst *MI, uint64_t Address, diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp index 816206c477df..b299541939ec 100644 --- a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp @@ -10,12 +10,11 @@ // //===----------------------------------------------------------------------===// +#include "MCTargetDesc/RISCVBaseInfo.h" #include "MCTargetDesc/RISCVFixupKinds.h" #include "MCTargetDesc/RISCVMCExpr.h" #include "MCTargetDesc/RISCVMCTargetDesc.h" -#include "Utils/RISCVBaseInfo.h" #include "llvm/ADT/Statistic.h" -#include "llvm/CodeGen/Register.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" @@ -84,6 +83,12 @@ public: unsigned getVMaskReg(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; + +private: + FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const; + void + verifyInstructionPredicates(const MCInst &MI, + const FeatureBitset &AvailableFeatures) const; }; } // end anonymous namespace @@ -106,7 +111,7 @@ void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS, const MCSubtargetInfo &STI) const { MCInst TmpInst; MCOperand Func; - Register Ra; + MCRegister Ra; if (MI.getOpcode() == RISCV::PseudoTAIL) { Func = MI.getOperand(0); Ra = RISCV::X6; @@ -185,6 +190,9 @@ void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS, void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { + verifyInstructionPredicates(MI, + computeAvailableFeatures(STI.getFeatureBits())); + const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); // Get byte count of instruction. unsigned Size = Desc.getSize(); @@ -397,4 +405,5 @@ unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo, } } +#define ENABLE_INSTR_PREDICATE_VERIFIER #include "RISCVGenMCCodeEmitter.inc" diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp index 2a6f372e50be..8ce2184c7a41 100644 --- a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp @@ -13,7 +13,6 @@ #include "RISCVMCExpr.h" #include "MCTargetDesc/RISCVAsmBackend.h" -#include "RISCV.h" #include "RISCVFixupKinds.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/MC/MCAsmLayout.h" diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp index a474224e1a4e..093118518db6 100644 --- a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp @@ -11,14 +11,13 @@ //===----------------------------------------------------------------------===// #include "RISCVMCTargetDesc.h" +#include "RISCVBaseInfo.h" #include "RISCVELFStreamer.h" #include "RISCVInstPrinter.h" #include "RISCVMCAsmInfo.h" #include "RISCVTargetStreamer.h" #include "TargetInfo/RISCVTargetInfo.h" -#include "Utils/RISCVBaseInfo.h" #include "llvm/ADT/STLExtras.h" -#include "llvm/CodeGen/Register.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrInfo.h" @@ -56,7 +55,7 @@ static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI, const MCTargetOptions &Options) { MCAsmInfo *MAI = new RISCVMCAsmInfo(TT); - Register SP = MRI.getDwarfRegNum(RISCV::X2, true); + MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true); MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0); MAI->addInitialFrameState(Inst); @@ -68,7 +67,7 @@ static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT, std::string CPUName = std::string(CPU); if (CPUName.empty()) CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"; - return createRISCVMCSubtargetInfoImpl(TT, CPUName, FS); + return createRISCVMCSubtargetInfoImpl(TT, CPUName, /*TuneCPU*/ CPUName, FS); } static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T, diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp new file mode 100644 index 000000000000..1f3dead61011 --- /dev/null +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp @@ -0,0 +1,91 @@ +//===- RISCVMatInt.cpp - Immediate materialisation -------------*- C++ -*--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "RISCVMatInt.h" +#include "MCTargetDesc/RISCVMCTargetDesc.h" +#include "llvm/ADT/APInt.h" +#include "llvm/Support/MathExtras.h" + +namespace llvm { + +namespace RISCVMatInt { +void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res) { + if (isInt<32>(Val)) { + // Depending on the active bits in the immediate Value v, the following + // instruction sequences are emitted: + // + // v == 0 : ADDI + // v[0,12) != 0 && v[12,32) == 0 : ADDI + // v[0,12) == 0 && v[12,32) != 0 : LUI + // v[0,32) != 0 : LUI+ADDI(W) + int64_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF; + int64_t Lo12 = SignExtend64<12>(Val); + + if (Hi20) + Res.push_back(Inst(RISCV::LUI, Hi20)); + + if (Lo12 || Hi20 == 0) { + unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI; + Res.push_back(Inst(AddiOpc, Lo12)); + } + return; + } + + assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target"); + + // In the worst case, for a full 64-bit constant, a sequence of 8 instructions + // (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emmitted. Note + // that the first two instructions (LUI+ADDIW) can contribute up to 32 bits + // while the following ADDI instructions contribute up to 12 bits each. + // + // On the first glance, implementing this seems to be possible by simply + // emitting the most significant 32 bits (LUI+ADDIW) followed by as many left + // shift (SLLI) and immediate additions (ADDI) as needed. However, due to the + // fact that ADDI performs a sign extended addition, doing it like that would + // only be possible when at most 11 bits of the ADDI instructions are used. + // Using all 12 bits of the ADDI instructions, like done by GAS, actually + // requires that the constant is processed starting with the least significant + // bit. + // + // In the following, constants are processed from LSB to MSB but instruction + // emission is performed from MSB to LSB by recursively calling + // generateInstSeq. In each recursion, first the lowest 12 bits are removed + // from the constant and the optimal shift amount, which can be greater than + // 12 bits if the constant is sparse, is determined. Then, the shifted + // remaining constant is processed recursively and gets emitted as soon as it + // fits into 32 bits. The emission of the shifts and additions is subsequently + // performed when the recursion returns. + + int64_t Lo12 = SignExtend64<12>(Val); + int64_t Hi52 = ((uint64_t)Val + 0x800ull) >> 12; + int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52); + Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount); + + generateInstSeq(Hi52, IsRV64, Res); + + Res.push_back(Inst(RISCV::SLLI, ShiftAmount)); + if (Lo12) + Res.push_back(Inst(RISCV::ADDI, Lo12)); +} + +int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64) { + int PlatRegSize = IsRV64 ? 64 : 32; + + // Split the constant into platform register sized chunks, and calculate cost + // of each chunk. + int Cost = 0; + for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) { + APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize); + InstSeq MatSeq; + generateInstSeq(Chunk.getSExtValue(), IsRV64, MatSeq); + Cost += MatSeq.size(); + } + return std::max(1, Cost); +} +} // namespace RISCVMatInt +} // namespace llvm diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h new file mode 100644 index 000000000000..17ca57458b49 --- /dev/null +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h @@ -0,0 +1,43 @@ +//===- RISCVMatInt.h - Immediate materialisation ---------------*- C++ -*--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_RISCV_MATINT_H +#define LLVM_LIB_TARGET_RISCV_MATINT_H + +#include "llvm/ADT/SmallVector.h" +#include <cstdint> + +namespace llvm { +class APInt; + +namespace RISCVMatInt { +struct Inst { + unsigned Opc; + int64_t Imm; + + Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {} +}; +using InstSeq = SmallVector<Inst, 8>; + +// Helper to generate an instruction sequence that will materialise the given +// immediate value into a register. A sequence of instructions represented by +// a simple struct produced rather than directly emitting the instructions in +// order to allow this helper to be used from both the MC layer and during +// instruction selection. +void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res); + +// Helper to estimate the number of instructions required to materialise the +// given immediate value into a register. This estimate does not account for +// `Val` possibly fitting into an immediate, and so may over-estimate. +// +// This will attempt to produce instructions to materialise `Val` as an +// `Size`-bit immediate. `IsRV64` should match the target architecture. +int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64); +} // namespace RISCVMatInt +} // namespace llvm +#endif diff --git a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp index 54a2fb288579..72434a15bedb 100644 --- a/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp +++ b/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp @@ -11,7 +11,7 @@ //===----------------------------------------------------------------------===// #include "RISCVTargetStreamer.h" -#include "RISCVSubtarget.h" +#include "RISCVMCTargetDesc.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Support/RISCVAttributes.h" @@ -60,6 +60,38 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) { Arch += "_d2p0"; if (STI.hasFeature(RISCV::FeatureStdExtC)) Arch += "_c2p0"; + if (STI.hasFeature(RISCV::FeatureStdExtB)) + Arch += "_b0p93"; + if (STI.hasFeature(RISCV::FeatureStdExtV)) + Arch += "_v1p0"; + if (STI.hasFeature(RISCV::FeatureExtZfh)) + Arch += "_zfh0p1"; + if (STI.hasFeature(RISCV::FeatureExtZba)) + Arch += "_zba0p93"; + if (STI.hasFeature(RISCV::FeatureExtZbb)) + Arch += "_zbb0p93"; + if (STI.hasFeature(RISCV::FeatureExtZbc)) + Arch += "_zbc0p93"; + if (STI.hasFeature(RISCV::FeatureExtZbe)) + Arch += "_zbe0p93"; + if (STI.hasFeature(RISCV::FeatureExtZbf)) + Arch += "_zbf0p93"; + if (STI.hasFeature(RISCV::FeatureExtZbm)) + Arch += "_zbm0p93"; + if (STI.hasFeature(RISCV::FeatureExtZbp)) + Arch += "_zbp0p93"; + if (STI.hasFeature(RISCV::FeatureExtZbproposedc)) + Arch += "_zbproposedc0p93"; + if (STI.hasFeature(RISCV::FeatureExtZbr)) + Arch += "_zbr0p93"; + if (STI.hasFeature(RISCV::FeatureExtZbs)) + Arch += "_zbs0p93"; + if (STI.hasFeature(RISCV::FeatureExtZbt)) + Arch += "_zbt0p93"; + if (STI.hasFeature(RISCV::FeatureExtZvamo)) + Arch += "_zvamo1p0"; + if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg)) + Arch += "_zvlsseg1p0"; emitTextAttribute(RISCVAttrs::ARCH, Arch); } |