diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/Sparc')
11 files changed, 44 insertions, 25 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index 9a2df8ca7fe9..48e6903bd1b1 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -25,10 +25,10 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" +#include "llvm/MC/TargetRegistry.h" #include "llvm/Support/Casting.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/SMLoc.h" -#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #include <algorithm> #include <cassert> diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp index 5c4419c108c0..142124a8e0d9 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -17,7 +17,7 @@ #include "llvm/MC/MCDisassembler/MCDisassembler.h" #include "llvm/MC/MCFixedLenDisassembler.h" #include "llvm/MC/MCInst.h" -#include "llvm/Support/TargetRegistry.h" +#include "llvm/MC/TargetRegistry.h" using namespace llvm; diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp index 51eccfa52359..e950f9582f09 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp @@ -15,8 +15,8 @@ #include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCValue.h" +#include "llvm/MC/TargetRegistry.h" #include "llvm/Support/EndianStream.h" -#include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -274,7 +274,8 @@ namespace { llvm_unreachable("relaxInstruction() unimplemented"); } - bool writeNopData(raw_ostream &OS, uint64_t Count) const override { + bool writeNopData(raw_ostream &OS, uint64_t Count, + const MCSubtargetInfo *STI) const override { // Cannot emit NOP with size not multiple of 32 bits. if (Count % 4 != 0) return false; diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp index 9531e3105fe2..49b75b7e0bd1 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -18,8 +18,8 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/TargetRegistry.h" using namespace llvm; diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp index 2006c9bede34..f6f9c0a1de81 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -29,7 +29,7 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" -#include "llvm/Support/TargetRegistry.h" +#include "llvm/MC/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcISelLowering.cpp index 2007303d9903..ed1faf6b1fe8 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -1614,11 +1614,14 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, if (!Subtarget->is64Bit()) { // These libcalls are not available in 32-bit. + setLibcallName(RTLIB::MULO_I64, nullptr); setLibcallName(RTLIB::SHL_I128, nullptr); setLibcallName(RTLIB::SRL_I128, nullptr); setLibcallName(RTLIB::SRA_I128, nullptr); } + setLibcallName(RTLIB::MULO_I128, nullptr); + if (!Subtarget->isV9()) { // SparcV8 does not have FNEGD and FABSD. setOperationAction(ISD::FNEG, MVT::f64, Custom); @@ -2957,8 +2960,15 @@ static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, SDValue ShiftAmt = DAG.getConstant(63, dl, VT); SDValue RHS = Op.getOperand(1); - SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); - SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt); + SDValue HiLHS, HiRHS; + if (isSigned) { + HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); + HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt); + } else { + HiLHS = DAG.getConstant(0, dl, VT); + HiRHS = DAG.getConstant(0, dl, MVT::i64); + } + SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; TargetLowering::MakeLibCallOptions CallOptions; diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index dc3a41c63098..a8a0b2cc9e67 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -20,8 +20,8 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/MC/TargetRegistry.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/TargetRegistry.h" using namespace llvm; diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrInfo.td b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrInfo.td index b161e2a9d087..5e305fc9df71 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -369,8 +369,7 @@ multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, // TODO: Instructions of the LoadASI class are currently asm only; hooking up // CodeGen's address spaces to use these is a future task. -class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, - RegisterClass RC, ValueType Ty, InstrItinClass itin = NoItinerary> : +class LoadASI<string OpcStr, bits<6> Op3Val, RegisterClass RC> : F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi), !strconcat(OpcStr, "a [$addr] $asi, $dst"), []>; @@ -380,7 +379,7 @@ multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val, SDPatternOperator OpNode, RegisterClass RC, ValueType Ty, InstrItinClass itin = NoItinerary> : Load<OpcStr, Op3Val, OpNode, RC, Ty, itin> { - def Arr : LoadASI<OpcStr, LoadAOp3Val, OpNode, RC, Ty>; + def Arr : LoadASI<OpcStr, LoadAOp3Val, RC>; } // The LDSTUB instruction is supported for asm only. @@ -411,8 +410,7 @@ multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, // TODO: Instructions of the StoreASI class are currently asm only; hooking up // CodeGen's address spaces to use these is a future task. -class StoreASI<string OpcStr, bits<6> Op3Val, - SDPatternOperator OpNode, RegisterClass RC, ValueType Ty, +class StoreASI<string OpcStr, bits<6> Op3Val, RegisterClass RC, InstrItinClass itin = IIC_st> : F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi), !strconcat(OpcStr, "a $rd, [$addr] $asi"), @@ -420,10 +418,9 @@ class StoreASI<string OpcStr, bits<6> Op3Val, itin>; multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val, - SDPatternOperator OpNode, RegisterClass RC, ValueType Ty, - InstrItinClass itin = IIC_st> : + SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : Store<OpcStr, Op3Val, OpNode, RC, Ty> { - def Arr : StoreASI<OpcStr, StoreAOp3Val, OpNode, RC, Ty, itin>; + def Arr : StoreASI<OpcStr, StoreAOp3Val, RC>; } //===----------------------------------------------------------------------===// @@ -523,12 +520,12 @@ let DecoderMethod = "DecodeLoadIntPair" in // Section B.2 - Load Floating-point Instructions, p. 92 let DecoderMethod = "DecodeLoadFP" in { defm LDF : Load<"ld", 0b100000, load, FPRegs, f32, IIC_iu_or_fpu_instr>; - def LDFArr : LoadASI<"ld", 0b110000, load, FPRegs, f32, IIC_iu_or_fpu_instr>, + def LDFArr : LoadASI<"ld", 0b110000, FPRegs>, Requires<[HasV9]>; } let DecoderMethod = "DecodeLoadDFP" in { defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64, IIC_ldd>; - def LDDFArr : LoadASI<"ldd", 0b110011, load, DFPRegs, f64>, + def LDDFArr : LoadASI<"ldd", 0b110011, DFPRegs>, Requires<[HasV9]>; } let DecoderMethod = "DecodeLoadQFP" in @@ -573,17 +570,17 @@ let DecoderMethod = "DecodeStoreInt" in { } let DecoderMethod = "DecodeStoreIntPair" in - defm STD : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32, IIC_std>; + defm STD : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32>; // Section B.5 - Store Floating-point Instructions, p. 97 let DecoderMethod = "DecodeStoreFP" in { defm STF : Store<"st", 0b100100, store, FPRegs, f32>; - def STFArr : StoreASI<"st", 0b110100, store, FPRegs, f32>, + def STFArr : StoreASI<"st", 0b110100, FPRegs>, Requires<[HasV9]>; } let DecoderMethod = "DecodeStoreDFP" in { defm STDF : Store<"std", 0b100111, store, DFPRegs, f64, IIC_std>; - def STDFArr : StoreASI<"std", 0b110111, store, DFPRegs, f64>, + def STDFArr : StoreASI<"std", 0b110111, DFPRegs>, Requires<[HasV9]>; } let DecoderMethod = "DecodeStoreQFP" in @@ -1623,6 +1620,17 @@ let hasSideEffects = 1 in { } } +// Section A.42 - Prefetch Data +let Predicates = [HasV9] in { + def PREFETCHr : F3_1<3, 0b101101, + (outs), (ins MEMrr:$addr, shift_imm5:$rd), + "prefetch [$addr], $rd", []>; + def PREFETCHi : F3_2<3, 0b101101, + (outs), (ins MEMri:$addr, shift_imm5:$rd), + "prefetch [$addr], $rd", []>; +} + + // Section A.43 - Read Privileged Register Instructions let Predicates = [HasV9] in { diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcSubtarget.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcSubtarget.cpp index abc47ef51563..618a8633f0a9 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcSubtarget.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcSubtarget.cpp @@ -12,8 +12,8 @@ #include "SparcSubtarget.h" #include "Sparc.h" +#include "llvm/MC/TargetRegistry.h" #include "llvm/Support/MathExtras.h" -#include "llvm/Support/TargetRegistry.h" using namespace llvm; diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index 083339bc157c..27c49a408a02 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -17,7 +17,7 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/IR/LegacyPassManager.h" -#include "llvm/Support/TargetRegistry.h" +#include "llvm/MC/TargetRegistry.h" using namespace llvm; extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget() { diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp index 3bf5907012da..1138788ac7fa 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// #include "TargetInfo/SparcTargetInfo.h" -#include "llvm/Support/TargetRegistry.h" +#include "llvm/MC/TargetRegistry.h" using namespace llvm; Target &llvm::getTheSparcTarget() { |