diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/Sparc')
21 files changed, 318 insertions, 161 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index 16e159621672..5f1bf316e871 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -82,6 +82,11 @@ class SparcAsmParser : public MCTargetAsmParser { OperandMatchResultTy parseMembarTag(OperandVector &Operands); + template <unsigned N> + OperandMatchResultTy parseShiftAmtImm(OperandVector &Operands); + + OperandMatchResultTy parseCallTarget(OperandVector &Operands); + OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name); OperandMatchResultTy @@ -262,6 +267,36 @@ public: bool isMEMri() const { return Kind == k_MemoryImm; } bool isMembarTag() const { return Kind == k_Immediate; } + bool isCallTarget() const { + if (!isImm()) + return false; + + if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) + return CE->getValue() % 4 == 0; + + return true; + } + + bool isShiftAmtImm5() const { + if (!isImm()) + return false; + + if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) + return isUInt<5>(CE->getValue()); + + return false; + } + + bool isShiftAmtImm6() const { + if (!isImm()) + return false; + + if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) + return isUInt<6>(CE->getValue()); + + return false; + } + bool isIntReg() const { return (Kind == k_Register && Reg.Kind == rk_IntReg); } @@ -343,6 +378,15 @@ public: addExpr(Inst, Expr); } + void addShiftAmtImm5Operands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + addExpr(Inst, getImm()); + } + void addShiftAmtImm6Operands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + addExpr(Inst, getImm()); + } + void addExpr(MCInst &Inst, const MCExpr *Expr) const{ // Add as immediate when possible. Null MCExpr = 0. if (!Expr) @@ -377,6 +421,11 @@ public: addExpr(Inst, Expr); } + void addCallTargetOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + addExpr(Inst, getImm()); + } + static std::unique_ptr<SparcOperand> CreateToken(StringRef Str, SMLoc S) { auto Op = std::make_unique<SparcOperand>(k_Token); Op->Tok.Data = Str.data(); @@ -645,7 +694,7 @@ OperandMatchResultTy SparcAsmParser::tryParseRegister(unsigned &RegNo, EndLoc = Tok.getEndLoc(); RegNo = 0; if (getLexer().getKind() != AsmToken::Percent) - return MatchOperand_Success; + return MatchOperand_NoMatch; Parser.Lex(); unsigned regKind = SparcOperand::rk_None; if (matchRegisterName(Tok, RegNo, regKind)) { @@ -729,37 +778,74 @@ ParseDirective(AsmToken DirectiveID) OperandMatchResultTy SparcAsmParser::parseMEMOperand(OperandVector &Operands) { SMLoc S, E; - unsigned BaseReg = 0; - if (ParseRegister(BaseReg, S, E)) { + std::unique_ptr<SparcOperand> LHS; + if (parseSparcAsmOperand(LHS) != MatchOperand_Success) return MatchOperand_NoMatch; + + // Single immediate operand + if (LHS->isImm()) { + Operands.push_back(SparcOperand::MorphToMEMri(Sparc::G0, std::move(LHS))); + return MatchOperand_Success; } - switch (getLexer().getKind()) { - default: return MatchOperand_NoMatch; + if (!LHS->isIntReg()) { + Error(LHS->getStartLoc(), "invalid register kind for this operand"); + return MatchOperand_ParseFail; + } - case AsmToken::Comma: - case AsmToken::RBrac: - case AsmToken::EndOfStatement: - Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E)); - return MatchOperand_Success; + AsmToken Tok = getLexer().getTok(); + // The plus token may be followed by a register or an immediate value, the + // minus one is always interpreted as sign for the immediate value + if (Tok.is(AsmToken::Plus) || Tok.is(AsmToken::Minus)) { + (void)Parser.parseOptionalToken(AsmToken::Plus); - case AsmToken:: Plus: - Parser.Lex(); // Eat the '+' - break; - case AsmToken::Minus: - break; + std::unique_ptr<SparcOperand> RHS; + if (parseSparcAsmOperand(RHS) != MatchOperand_Success) + return MatchOperand_NoMatch; + + if (RHS->isReg() && !RHS->isIntReg()) { + Error(RHS->getStartLoc(), "invalid register kind for this operand"); + return MatchOperand_ParseFail; + } + + Operands.push_back( + RHS->isImm() + ? SparcOperand::MorphToMEMri(LHS->getReg(), std::move(RHS)) + : SparcOperand::MorphToMEMrr(LHS->getReg(), std::move(RHS))); + + return MatchOperand_Success; } - std::unique_ptr<SparcOperand> Offset; - OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset); - if (ResTy != MatchOperand_Success || !Offset) + Operands.push_back(SparcOperand::CreateMEMr(LHS->getReg(), S, E)); + return MatchOperand_Success; +} + +template <unsigned N> +OperandMatchResultTy SparcAsmParser::parseShiftAmtImm(OperandVector &Operands) { + SMLoc S = Parser.getTok().getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + + // This is a register, not an immediate + if (getLexer().getKind() == AsmToken::Percent) return MatchOperand_NoMatch; - Operands.push_back( - Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset)) - : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset))); + const MCExpr *Expr; + if (getParser().parseExpression(Expr)) + return MatchOperand_ParseFail; + + const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); + if (!CE) { + Error(S, "constant expression expected"); + return MatchOperand_ParseFail; + } + + if (!isUInt<N>(CE->getValue())) { + Error(S, "immediate shift value out of range"); + return MatchOperand_ParseFail; + } + Operands.push_back(SparcOperand::CreateImm(Expr, S, E)); return MatchOperand_Success; } @@ -809,6 +895,33 @@ OperandMatchResultTy SparcAsmParser::parseMembarTag(OperandVector &Operands) { return MatchOperand_Success; } +OperandMatchResultTy SparcAsmParser::parseCallTarget(OperandVector &Operands) { + SMLoc S = Parser.getTok().getLoc(); + SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1); + + switch (getLexer().getKind()) { + default: + return MatchOperand_NoMatch; + case AsmToken::LParen: + case AsmToken::Integer: + case AsmToken::Identifier: + case AsmToken::Dot: + break; + } + + const MCExpr *DestValue; + if (getParser().parseExpression(DestValue)) + return MatchOperand_NoMatch; + + bool IsPic = getContext().getObjectFileInfo()->isPositionIndependent(); + SparcMCExpr::VariantKind Kind = + IsPic ? SparcMCExpr::VK_Sparc_WPLT30 : SparcMCExpr::VK_Sparc_WDISP30; + + const MCExpr *DestExpr = SparcMCExpr::create(Kind, DestValue, getContext()); + Operands.push_back(SparcOperand::CreateImm(DestExpr, S, E)); + return MatchOperand_Success; +} + OperandMatchResultTy SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { @@ -936,6 +1049,7 @@ SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op, } break; + case AsmToken::Plus: case AsmToken::Minus: case AsmToken::Integer: case AsmToken::LParen: @@ -1272,7 +1386,7 @@ const SparcMCExpr * SparcAsmParser::adjustPICRelocation(SparcMCExpr::VariantKind VK, const MCExpr *subExpr) { // When in PIC mode, "%lo(...)" and "%hi(...)" behave differently. - // If the expression refers contains _GLOBAL_OFFSETE_TABLE, it is + // If the expression refers contains _GLOBAL_OFFSET_TABLE, it is // actually a %pc10 or %pc22 relocation. Otherwise, they are interpreted // as %got10 or %got22 relocation. diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/LeonPasses.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/LeonPasses.cpp index e9d3aaeb9cfe..6ad6940c6b51 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/LeonPasses.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/LeonPasses.cpp @@ -10,14 +10,13 @@ //===----------------------------------------------------------------------===// #include "LeonPasses.h" -#include "llvm/CodeGen/ISDOpcodes.h" +#include "SparcSubtarget.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/IR/DiagnosticInfo.h" -#include "llvm/IR/LLVMContext.h" #include "llvm/Support/raw_ostream.h" + using namespace llvm; LEONMachineFunctionPass::LEONMachineFunctionPass(char &ID) diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/LeonPasses.h b/contrib/llvm-project/llvm/lib/Target/Sparc/LeonPasses.h index b165bc93780f..9bc4569a1298 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/LeonPasses.h +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/LeonPasses.h @@ -12,14 +12,11 @@ #ifndef LLVM_LIB_TARGET_SPARC_LEON_PASSES_H #define LLVM_LIB_TARGET_SPARC_LEON_PASSES_H -#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/Passes.h" - -#include "Sparc.h" -#include "SparcSubtarget.h" namespace llvm { +class SparcSubtarget; + class LLVM_LIBRARY_VISIBILITY LEONMachineFunctionPass : public MachineFunctionPass { protected: @@ -33,13 +30,11 @@ protected: protected: LEONMachineFunctionPass(char &ID); - int GetRegIndexForOperand(MachineInstr &MI, int OperandIndex); void clearUsedRegisterList() { UsedRegisters.clear(); } void markRegisterUsed(int registerIndex) { UsedRegisters.push_back(registerIndex); } - int getUnusedFPRegister(MachineRegisterInfo &MRI); }; class LLVM_LIBRARY_VISIBILITY InsertNOPLoad : public LEONMachineFunctionPass { diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp index 83c44e0682ce..5a9ecfe74ecc 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp @@ -255,12 +255,6 @@ namespace { } } - bool mayNeedRelaxation(const MCInst &Inst, - const MCSubtargetInfo &STI) const override { - // FIXME. - return false; - } - /// fixupNeedsRelaxation - Target specific predicate for whether a given /// fixup requires the associated instruction to be relaxed. bool fixupNeedsRelaxation(const MCFixup &Fixup, diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp index f6728a070736..8e4621946008 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp @@ -141,24 +141,34 @@ void SparcInstPrinter::printOperand(const MCInst *MI, int opNum, void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier) { - printOperand(MI, opNum, STI, O); - // If this is an ADD operand, emit it like normal operands. if (Modifier && !strcmp(Modifier, "arith")) { + printOperand(MI, opNum, STI, O); O << ", "; - printOperand(MI, opNum+1, STI, O); + printOperand(MI, opNum + 1, STI, O); return; } - const MCOperand &MO = MI->getOperand(opNum+1); - if (MO.isReg() && MO.getReg() == SP::G0) - return; // don't print "+%g0" - if (MO.isImm() && MO.getImm() == 0) - return; // don't print "+0" + const MCOperand &Op1 = MI->getOperand(opNum); + const MCOperand &Op2 = MI->getOperand(opNum + 1); + + bool PrintedFirstOperand = false; + if (Op1.isReg() && Op1.getReg() != SP::G0) { + printOperand(MI, opNum, STI, O); + PrintedFirstOperand = true; + } - O << "+"; + // Skip the second operand iff it adds nothing (literal 0 or %g0) and we've + // already printed the first one + const bool SkipSecondOperand = + PrintedFirstOperand && ((Op2.isReg() && Op2.getReg() == SP::G0) || + (Op2.isImm() && Op2.getImm() == 0)); - printOperand(MI, opNum+1, STI, O); + if (!SkipSecondOperand) { + if (PrintedFirstOperand) + O << '+'; + printOperand(MI, opNum + 1, STI, O); + } } void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum, diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h index 11587f165ef2..91b78bd03fc3 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h @@ -31,6 +31,7 @@ public: bool isV9(const MCSubtargetInfo &STI) const; // Autogenerated by tblgen. + std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override; void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O); bool printAliasInstr(const MCInst *MI, uint64_t Address, diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp index 7e908011bd50..9f8522541332 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp @@ -22,6 +22,7 @@ #include "llvm/MC/MCFixup.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCObjectFileInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" @@ -68,13 +69,15 @@ public: unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; - unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; + unsigned getSImm13OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; @@ -146,20 +149,50 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO, return 0; } +unsigned +SparcMCCodeEmitter::getSImm13OpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + + if (MO.isImm()) + return MO.getImm(); + + assert(MO.isExpr() && + "getSImm13OpValue expects only expressions or an immediate"); + + const MCExpr *Expr = MO.getExpr(); + + // Constant value, no fixup is needed + if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) + return CE->getValue(); + + MCFixupKind Kind; + if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) { + Kind = MCFixupKind(SExpr->getFixupKind()); + } else { + bool IsPic = Ctx.getObjectFileInfo()->isPositionIndependent(); + Kind = IsPic ? MCFixupKind(Sparc::fixup_sparc_got13) + : MCFixupKind(Sparc::fixup_sparc_13); + } + + Fixups.push_back(MCFixup::create(0, Expr, Kind)); + return 0; +} + unsigned SparcMCCodeEmitter:: getCallTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); - if (MO.isReg() || MO.isImm()) - return getMachineOpValue(MI, MO, Fixups, STI); + const MCExpr *Expr = MO.getExpr(); + const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr); if (MI.getOpcode() == SP::TLS_CALL) { // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in // encodeInstruction. #ifndef NDEBUG // Verify that the callee is actually __tls_get_addr. - const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr()); assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef && "Unexpected expression in TLS_CALL"); const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr()); @@ -169,15 +202,8 @@ getCallTargetOpValue(const MCInst &MI, unsigned OpNo, return 0; } - MCFixupKind fixupKind = (MCFixupKind)Sparc::fixup_sparc_call30; - - if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr())) { - if (SExpr->getKind() == SparcMCExpr::VK_Sparc_WPLT30) - fixupKind = (MCFixupKind)Sparc::fixup_sparc_wplt30; - } - - Fixups.push_back(MCFixup::create(0, MO.getExpr(), fixupKind)); - + MCFixupKind Kind = MCFixupKind(SExpr->getFixupKind()); + Fixups.push_back(MCFixup::create(0, Expr, Kind)); return 0; } diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp index 00f319fc37e1..b84ecf074455 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp @@ -41,46 +41,46 @@ void SparcMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const { bool SparcMCExpr::printVariantKind(raw_ostream &OS, VariantKind Kind) { - bool closeParen = true; switch (Kind) { - case VK_Sparc_None: closeParen = false; break; - case VK_Sparc_LO: OS << "%lo("; break; - case VK_Sparc_HI: OS << "%hi("; break; - case VK_Sparc_H44: OS << "%h44("; break; - case VK_Sparc_M44: OS << "%m44("; break; - case VK_Sparc_L44: OS << "%l44("; break; - case VK_Sparc_HH: OS << "%hh("; break; - case VK_Sparc_HM: OS << "%hm("; break; + case VK_Sparc_None: return false; + case VK_Sparc_LO: OS << "%lo("; return true; + case VK_Sparc_HI: OS << "%hi("; return true; + case VK_Sparc_H44: OS << "%h44("; return true; + case VK_Sparc_M44: OS << "%m44("; return true; + case VK_Sparc_L44: OS << "%l44("; return true; + case VK_Sparc_HH: OS << "%hh("; return true; + case VK_Sparc_HM: OS << "%hm("; return true; // FIXME: use %pc22/%pc10, if system assembler supports them. - case VK_Sparc_PC22: OS << "%hi("; break; - case VK_Sparc_PC10: OS << "%lo("; break; + case VK_Sparc_PC22: OS << "%hi("; return true; + case VK_Sparc_PC10: OS << "%lo("; return true; // FIXME: use %got22/%got10, if system assembler supports them. - case VK_Sparc_GOT22: OS << "%hi("; break; - case VK_Sparc_GOT10: OS << "%lo("; break; - case VK_Sparc_GOT13: closeParen = false; break; - case VK_Sparc_13: closeParen = false; break; - case VK_Sparc_WPLT30: closeParen = false; break; - case VK_Sparc_R_DISP32: OS << "%r_disp32("; break; - case VK_Sparc_TLS_GD_HI22: OS << "%tgd_hi22("; break; - case VK_Sparc_TLS_GD_LO10: OS << "%tgd_lo10("; break; - case VK_Sparc_TLS_GD_ADD: OS << "%tgd_add("; break; - case VK_Sparc_TLS_GD_CALL: OS << "%tgd_call("; break; - case VK_Sparc_TLS_LDM_HI22: OS << "%tldm_hi22("; break; - case VK_Sparc_TLS_LDM_LO10: OS << "%tldm_lo10("; break; - case VK_Sparc_TLS_LDM_ADD: OS << "%tldm_add("; break; - case VK_Sparc_TLS_LDM_CALL: OS << "%tldm_call("; break; - case VK_Sparc_TLS_LDO_HIX22: OS << "%tldo_hix22("; break; - case VK_Sparc_TLS_LDO_LOX10: OS << "%tldo_lox10("; break; - case VK_Sparc_TLS_LDO_ADD: OS << "%tldo_add("; break; - case VK_Sparc_TLS_IE_HI22: OS << "%tie_hi22("; break; - case VK_Sparc_TLS_IE_LO10: OS << "%tie_lo10("; break; - case VK_Sparc_TLS_IE_LD: OS << "%tie_ld("; break; - case VK_Sparc_TLS_IE_LDX: OS << "%tie_ldx("; break; - case VK_Sparc_TLS_IE_ADD: OS << "%tie_add("; break; - case VK_Sparc_TLS_LE_HIX22: OS << "%tle_hix22("; break; - case VK_Sparc_TLS_LE_LOX10: OS << "%tle_lox10("; break; + case VK_Sparc_GOT22: OS << "%hi("; return true; + case VK_Sparc_GOT10: OS << "%lo("; return true; + case VK_Sparc_GOT13: return false; + case VK_Sparc_13: return false; + case VK_Sparc_WDISP30: return false; + case VK_Sparc_WPLT30: return false; + case VK_Sparc_R_DISP32: OS << "%r_disp32("; return true; + case VK_Sparc_TLS_GD_HI22: OS << "%tgd_hi22("; return true; + case VK_Sparc_TLS_GD_LO10: OS << "%tgd_lo10("; return true; + case VK_Sparc_TLS_GD_ADD: OS << "%tgd_add("; return true; + case VK_Sparc_TLS_GD_CALL: OS << "%tgd_call("; return true; + case VK_Sparc_TLS_LDM_HI22: OS << "%tldm_hi22("; return true; + case VK_Sparc_TLS_LDM_LO10: OS << "%tldm_lo10("; return true; + case VK_Sparc_TLS_LDM_ADD: OS << "%tldm_add("; return true; + case VK_Sparc_TLS_LDM_CALL: OS << "%tldm_call("; return true; + case VK_Sparc_TLS_LDO_HIX22: OS << "%tldo_hix22("; return true; + case VK_Sparc_TLS_LDO_LOX10: OS << "%tldo_lox10("; return true; + case VK_Sparc_TLS_LDO_ADD: OS << "%tldo_add("; return true; + case VK_Sparc_TLS_IE_HI22: OS << "%tie_hi22("; return true; + case VK_Sparc_TLS_IE_LO10: OS << "%tie_lo10("; return true; + case VK_Sparc_TLS_IE_LD: OS << "%tie_ld("; return true; + case VK_Sparc_TLS_IE_LDX: OS << "%tie_ldx("; return true; + case VK_Sparc_TLS_IE_ADD: OS << "%tie_add("; return true; + case VK_Sparc_TLS_LE_HIX22: OS << "%tle_hix22("; return true; + case VK_Sparc_TLS_LE_LOX10: OS << "%tle_lox10("; return true; } - return closeParen; + llvm_unreachable("Unhandled SparcMCExpr::VariantKind"); } SparcMCExpr::VariantKind SparcMCExpr::parseVariantKind(StringRef name) @@ -137,6 +137,7 @@ Sparc::Fixups SparcMCExpr::getFixupKind(SparcMCExpr::VariantKind Kind) { case VK_Sparc_GOT13: return Sparc::fixup_sparc_got13; case VK_Sparc_13: return Sparc::fixup_sparc_13; case VK_Sparc_WPLT30: return Sparc::fixup_sparc_wplt30; + case VK_Sparc_WDISP30: return Sparc::fixup_sparc_call30; case VK_Sparc_TLS_GD_HI22: return Sparc::fixup_sparc_tls_gd_hi22; case VK_Sparc_TLS_GD_LO10: return Sparc::fixup_sparc_tls_gd_lo10; case VK_Sparc_TLS_GD_ADD: return Sparc::fixup_sparc_tls_gd_add; @@ -205,10 +206,8 @@ void SparcMCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const { MCSymbol *Symbol = Asm.getContext().getOrCreateSymbol("__tls_get_addr"); Asm.registerSymbol(*Symbol); auto ELFSymbol = cast<MCSymbolELF>(Symbol); - if (!ELFSymbol->isBindingSet()) { + if (!ELFSymbol->isBindingSet()) ELFSymbol->setBinding(ELF::STB_GLOBAL); - ELFSymbol->setExternal(true); - } LLVM_FALLTHROUGH; } case VK_Sparc_TLS_GD_HI22: diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h index c2467faca257..76603530e521 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h @@ -38,6 +38,7 @@ public: VK_Sparc_GOT13, VK_Sparc_13, VK_Sparc_WPLT30, + VK_Sparc_WDISP30, VK_Sparc_R_DISP32, VK_Sparc_TLS_GD_HI22, VK_Sparc_TLS_GD_LO10, diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp index fb2bcdc6c91b..9531e3105fe2 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -68,7 +68,7 @@ static MCSubtargetInfo * createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { if (CPU.empty()) CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8"; - return createSparcMCSubtargetInfoImpl(TT, CPU, FS); + return createSparcMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); } static MCTargetStreamer * diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp index 7845a18b14c1..ee0b85292cfd 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -80,7 +80,7 @@ static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind, } static MCOperand createPCXCallOP(MCSymbol *Label, MCContext &OutContext) { - return createSparcMCOperand(SparcMCExpr::VK_Sparc_None, Label, OutContext); + return createSparcMCOperand(SparcMCExpr::VK_Sparc_WDISP30, Label, OutContext); } static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcFrameLowering.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcFrameLowering.cpp index 8d8424641cd9..63187fdce999 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcFrameLowering.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcFrameLowering.cpp @@ -257,9 +257,9 @@ bool SparcFrameLowering::hasFP(const MachineFunction &MF) const { MFI.isFrameAddressTaken(); } -int SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, - int FI, - Register &FrameReg) const { +StackOffset +SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const { const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); const MachineFrameInfo &MFI = MF.getFrameInfo(); const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); @@ -295,10 +295,10 @@ int SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, if (UseFP) { FrameReg = RegInfo->getFrameRegister(MF); - return FrameOffset; + return StackOffset::getFixed(FrameOffset); } else { FrameReg = SP::O6; // %sp - return FrameOffset + MF.getFrameInfo().getStackSize(); + return StackOffset::getFixed(FrameOffset + MF.getFrameInfo().getStackSize()); } } diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcFrameLowering.h b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcFrameLowering.h index 3ec9dc8b85dd..ab0ceb6591c6 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcFrameLowering.h +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcFrameLowering.h @@ -15,6 +15,7 @@ #include "Sparc.h" #include "llvm/CodeGen/TargetFrameLowering.h" +#include "llvm/Support/TypeSize.h" namespace llvm { @@ -38,8 +39,8 @@ public: void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS = nullptr) const override; - int getFrameIndexReference(const MachineFunction &MF, int FI, - Register &FrameReg) const override; + StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, + Register &FrameReg) const override; /// targetHandlesStackFrameRounding - Returns true if the target is /// responsible for rounding up the stack frame (probably at emitPrologue diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcISelLowering.cpp index 116352e08382..e5c7794b7d2f 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -939,7 +939,8 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, // If the callee is a GlobalAddress node (quite common, every direct call is) // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. // Likewise ExternalSymbol -> TargetExternalSymbol. - unsigned TF = isPositionIndependent() ? SparcMCExpr::VK_Sparc_WPLT30 : 0; + unsigned TF = isPositionIndependent() ? SparcMCExpr::VK_Sparc_WPLT30 + : SparcMCExpr::VK_Sparc_WDISP30; if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF); else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) @@ -1242,7 +1243,8 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, // Likewise ExternalSymbol -> TargetExternalSymbol. SDValue Callee = CLI.Callee; bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CB); - unsigned TF = isPositionIndependent() ? SparcMCExpr::VK_Sparc_WPLT30 : 0; + unsigned TF = isPositionIndependent() ? SparcMCExpr::VK_Sparc_WPLT30 + : SparcMCExpr::VK_Sparc_WDISP30; if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT, 0, TF); else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) @@ -1877,8 +1879,7 @@ void SparcTargetLowering::computeKnownBitsForTargetNode Known2 = DAG.computeKnownBits(Op.getOperand(0), Depth + 1); // Only known if known in both the LHS and RHS. - Known.One &= Known2.One; - Known.Zero &= Known2.Zero; + Known = KnownBits::commonBits(Known, Known2); break; } } @@ -2139,7 +2140,7 @@ SDValue SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, int FI = MFI.CreateStackObject(16, Align(8), false); SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); Chain = DAG.getStore(Chain, DL, Entry.Node, FIPtr, MachinePointerInfo(), - /* Alignment = */ 8); + Align(8)); Entry.Node = FIPtr; Entry.Ty = PointerType::getUnqual(ArgTy); @@ -2198,7 +2199,7 @@ SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG, // Load RetPtr to get the return value. return DAG.getLoad(Op.getValueType(), SDLoc(Op), Chain, RetPtr, - MachinePointerInfo(), /* Alignment = */ 8); + MachinePointerInfo(), Align(8)); } SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS, @@ -2541,8 +2542,9 @@ static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { MachinePointerInfo(SV)); // Load the actual argument out of the pointer VAList. // We can't count on greater alignment than the word size. - return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(), - std::min(PtrVT.getSizeInBits(), VT.getSizeInBits()) / 8); + return DAG.getLoad( + VT, DL, InChain, VAList, MachinePointerInfo(), + std::min(PtrVT.getFixedSizeInBits(), VT.getFixedSizeInBits()) / 8); } static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, @@ -2731,23 +2733,21 @@ static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG, static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG) { SDLoc dl(Op); - LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode()); - assert(LdNode && LdNode->getOffset().isUndef() - && "Unexpected node type"); + LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode()); + assert(LdNode->getOffset().isUndef() && "Unexpected node type"); - unsigned alignment = LdNode->getAlignment(); - if (alignment > 8) - alignment = 8; + Align Alignment = commonAlignment(LdNode->getOriginalAlign(), 8); SDValue Hi64 = DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LdNode->getBasePtr(), - LdNode->getPointerInfo(), alignment); + LdNode->getPointerInfo(), Alignment); EVT addrVT = LdNode->getBasePtr().getValueType(); SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, LdNode->getBasePtr(), DAG.getConstant(8, dl, addrVT)); SDValue Lo64 = DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LoPtr, - LdNode->getPointerInfo(), alignment); + LdNode->getPointerInfo().getWithOffset(8), + Alignment); SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32); SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32); @@ -2785,9 +2785,9 @@ static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) // Lower a f128 store into two f64 stores. static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) { SDLoc dl(Op); - StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode()); - assert(StNode && StNode->getOffset().isUndef() - && "Unexpected node type"); + StoreSDNode *StNode = cast<StoreSDNode>(Op.getNode()); + assert(StNode->getOffset().isUndef() && "Unexpected node type"); + SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32); SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32); @@ -2802,20 +2802,20 @@ static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) { StNode->getValue(), SubRegOdd); - unsigned alignment = StNode->getAlignment(); - if (alignment > 8) - alignment = 8; + Align Alignment = commonAlignment(StNode->getOriginalAlign(), 8); SDValue OutChains[2]; OutChains[0] = DAG.getStore(StNode->getChain(), dl, SDValue(Hi64, 0), - StNode->getBasePtr(), MachinePointerInfo(), alignment); + StNode->getBasePtr(), StNode->getPointerInfo(), + Alignment); EVT addrVT = StNode->getBasePtr().getValueType(); SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, StNode->getBasePtr(), DAG.getConstant(8, dl, addrVT)); OutChains[1] = DAG.getStore(StNode->getChain(), dl, SDValue(Lo64, 0), LoPtr, - MachinePointerInfo(), alignment); + StNode->getPointerInfo().getWithOffset(8), + Alignment); return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); } @@ -2834,7 +2834,8 @@ static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, St->getValue()); SDValue Chain = DAG.getStore( St->getChain(), dl, Val, St->getBasePtr(), St->getPointerInfo(), - St->getAlignment(), St->getMemOperand()->getFlags(), St->getAAInfo()); + St->getOriginalAlign(), St->getMemOperand()->getFlags(), + St->getAAInfo()); return Chain; } @@ -3400,8 +3401,9 @@ void SparcTargetLowering::ReplaceNodeResults(SDNode *N, SDLoc dl(N); SDValue LoadRes = DAG.getExtLoad( Ld->getExtensionType(), dl, MVT::v2i32, Ld->getChain(), - Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32, Ld->getAlignment(), - Ld->getMemOperand()->getFlags(), Ld->getAAInfo()); + Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32, + Ld->getOriginalAlign(), Ld->getMemOperand()->getFlags(), + Ld->getAAInfo()); SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes); Results.push_back(Res); diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstr64Bit.td index 9a200a36cd3e..df65c5457c1d 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstr64Bit.td +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstr64Bit.td @@ -42,9 +42,9 @@ def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>; def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>; def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>; -defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, I64Regs>; -defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, I64Regs>; -defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>; +defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, shift_imm6, I64Regs>; +defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, shift_imm6, I64Regs>; +defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, shift_imm6, I64Regs>; } // Predicates = [Is64Bit] diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrFormats.td b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrFormats.td index 2d8f063f7ed1..da53307bcb1c 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrFormats.td +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrFormats.td @@ -224,13 +224,13 @@ class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, // Define rr and ri shift instructions with patterns. multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode, - ValueType VT, RegisterClass RC, + ValueType VT, ValueType SIT, RegisterClass RC, InstrItinClass itin = IIC_iu_instr> { def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2), !strconcat(OpcStr, " $rs1, $rs2, $rd"), [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))], itin>; - def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt), + def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, SIT:$shcnt), !strconcat(OpcStr, " $rs1, $shcnt, $rd"), [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))], itin>; diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrInfo.td b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrInfo.td index 8b01313c7911..d1190ae03d2c 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -113,6 +113,18 @@ def SETHIimm_not : PatLeaf<(i32 imm), [{ def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>; def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>; +// Constrained operands for the shift operations. +class ShiftAmtImmAsmOperand<int Bits> : AsmOperandClass { + let Name = "ShiftAmtImm" # Bits; + let ParserMethod = "parseShiftAmtImm<" # Bits # ">"; +} +def shift_imm5 : Operand<i32> { + let ParserMatchClass = ShiftAmtImmAsmOperand<5>; +} +def shift_imm6 : Operand<i32> { + let ParserMatchClass = ShiftAmtImmAsmOperand<6>; +} + // Address operands def SparcMEMrrAsmOperand : AsmOperandClass { let Name = "MEMrr"; @@ -160,13 +172,20 @@ def bprtarget16 : Operand<OtherVT> { let EncoderMethod = "getBranchOnRegTargetOpValue"; } +def SparcCallTargetAsmOperand : AsmOperandClass { + let Name = "CallTarget"; + let ParserMethod = "parseCallTarget"; +} + def calltarget : Operand<i32> { let EncoderMethod = "getCallTargetOpValue"; let DecoderMethod = "DecodeCall"; + let ParserMatchClass = SparcCallTargetAsmOperand; } def simm13Op : Operand<i32> { let DecoderMethod = "DecodeSIMM13"; + let EncoderMethod = "getSImm13OpValue"; } // Operand for printing out a condition code. @@ -691,9 +710,9 @@ let Defs = [ICC] in { } // Section B.12 - Shift Instructions, p. 107 -defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>; -defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>; -defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>; +defm SLL : F3_S<"sll", 0b100101, 0, shl, i32, shift_imm5, IntRegs>; +defm SRL : F3_S<"srl", 0b100110, 0, srl, i32, shift_imm5, IntRegs>; +defm SRA : F3_S<"sra", 0b100111, 0, sra, i32, shift_imm5, IntRegs>; // Section B.13 - Add Instructions, p. 108 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>; diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp index 990dbe23e7ac..21dced23210c 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -175,7 +175,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, Register FrameReg; int Offset; - Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg); + Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed(); Offset += MI.getOperand(FIOperandNum + 1).getImm(); diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcSubtarget.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcSubtarget.cpp index dbc6cf8e5b86..abc47ef51563 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcSubtarget.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcSubtarget.cpp @@ -55,7 +55,7 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU, CPUName = (Is64Bit) ? "v9" : "v8"; // Parse features string. - ParseSubtargetFeatures(CPUName, FS); + ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS); // Popc is a v9-only instruction. if (!IsV9) @@ -67,9 +67,9 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU, SparcSubtarget::SparcSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool is64Bit) - : SparcGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), Is64Bit(is64Bit), - InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), - FrameLowering(*this) {} + : SparcGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT), + Is64Bit(is64Bit), InstrInfo(initializeSubtargetDependencies(CPU, FS)), + TLInfo(TM, *this), FrameLowering(*this) {} int SparcSubtarget::getAdjustedFrameSize(int frameSize) const { diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcSubtarget.h b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcSubtarget.h index db19f99e3c9c..82a4aa510355 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcSubtarget.h +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcSubtarget.h @@ -16,8 +16,8 @@ #include "SparcFrameLowering.h" #include "SparcISelLowering.h" #include "SparcInstrInfo.h" +#include "llvm/ADT/Triple.h" #include "llvm/CodeGen/SelectionDAGTargetInfo.h" -#include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/DataLayout.h" #include <string> @@ -101,7 +101,7 @@ public: /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - void ParseSubtargetFeatures(StringRef CPU, StringRef FS); + void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); SparcSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); bool is64Bit() const { return Is64Bit; } diff --git a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index d48d94e2faf1..ae5228db5827 100644 --- a/contrib/llvm-project/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -55,9 +55,7 @@ static std::string computeDataLayout(const Triple &T, bool is64Bit) { } static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { - if (!RM.hasValue()) - return Reloc::Static; - return *RM; + return RM.getValueOr(Reloc::Static); } // Code models. Some only make sense for 64-bit code. @@ -111,12 +109,10 @@ SparcTargetMachine::getSubtargetImpl(const Function &F) const { Attribute CPUAttr = F.getFnAttribute("target-cpu"); Attribute FSAttr = F.getFnAttribute("target-features"); - std::string CPU = !CPUAttr.hasAttribute(Attribute::None) - ? CPUAttr.getValueAsString().str() - : TargetCPU; - std::string FS = !FSAttr.hasAttribute(Attribute::None) - ? FSAttr.getValueAsString().str() - : TargetFS; + std::string CPU = + CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; + std::string FS = + FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; // FIXME: This is related to the code below to reset the target options, // we need to know whether or not the soft float flag is set on the |