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Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZSchedule.td')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZSchedule.td | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZSchedule.td b/contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZSchedule.td new file mode 100644 index 000000000000..98eca2802242 --- /dev/null +++ b/contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZSchedule.td @@ -0,0 +1,66 @@ +//==-- SystemZSchedule.td - SystemZ Scheduling Definitions ----*- tblgen -*-==// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Scheduler resources + +// These resources are used to express decoder grouping rules. The number of +// decoder slots needed by an instructions is normally one, but there are +// exceptions. +def NormalGr : SchedWrite; +def Cracked : SchedWrite; +def GroupAlone : SchedWrite; +def GroupAlone2 : SchedWrite; +def GroupAlone3 : SchedWrite; +def BeginGroup : SchedWrite; +def EndGroup : SchedWrite; + +// A SchedWrite added to other SchedWrites to make LSU latency parameterizable. +def LSULatency : SchedWrite; + +// Operand WriteLatencies. +foreach L = 1 - 30 in def "WLat"#L : SchedWrite; + +foreach L = 1 - 16 in + def "WLat"#L#"LSU" : WriteSequence<[!cast<SchedWrite>("WLat"#L), + LSULatency]>; + +// ReadAdvances, used for the register operand next to a memory operand, +// modelling that the register operand is needed later than the address +// operands. +def RegReadAdv : SchedRead; + +foreach Num = ["", "2", "3", "4", "5", "6"] in { + // Fixed-point units + def "FXa"#Num : SchedWrite; + def "FXb"#Num : SchedWrite; + def "FXU"#Num : SchedWrite; + // Load/store unit + def "LSU"#Num : SchedWrite; + // Vector sub units (z13 and later) + def "VecBF"#Num : SchedWrite; + def "VecDF"#Num : SchedWrite; + def "VecDFX"#Num : SchedWrite; + def "VecMul"#Num : SchedWrite; + def "VecStr"#Num : SchedWrite; + def "VecXsPm"#Num : SchedWrite; + // Floating point unit (zEC12 and earlier) + def "FPU"#Num : SchedWrite; + def "DFU"#Num : SchedWrite; +} + +def VecFPd : SchedWrite; // Blocking BFP div/sqrt unit. + +def VBU : SchedWrite; // Virtual branching unit + +def MCD : SchedWrite; // Millicode + +include "SystemZScheduleArch13.td" +include "SystemZScheduleZ14.td" +include "SystemZScheduleZ13.td" +include "SystemZScheduleZEC12.td" +include "SystemZScheduleZ196.td" |
