diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp')
-rw-r--r-- | contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index 4bcf89690505..7c47790d1e35 100644 --- a/contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -1869,8 +1869,7 @@ SDValue WebAssemblyTargetLowering::LowerIntrinsic(SDValue Op, Ops[OpIdx++] = Op.getOperand(2); while (OpIdx < 18) { const SDValue &MaskIdx = Op.getOperand(OpIdx + 1); - if (MaskIdx.isUndef() || - cast<ConstantSDNode>(MaskIdx.getNode())->getZExtValue() >= 32) { + if (MaskIdx.isUndef() || MaskIdx.getNode()->getAsZExtVal() >= 32) { bool isTarget = MaskIdx.getNode()->getOpcode() == ISD::TargetConstant; Ops[OpIdx++] = DAG.getConstant(0, DL, MVT::i32, isTarget); } else { @@ -1912,7 +1911,7 @@ WebAssemblyTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, const SDNode *Index = Extract.getOperand(1).getNode(); if (!isa<ConstantSDNode>(Index)) return SDValue(); - unsigned IndexVal = cast<ConstantSDNode>(Index)->getZExtValue(); + unsigned IndexVal = Index->getAsZExtVal(); unsigned Scale = ExtractedVecT.getVectorNumElements() / VecT.getVectorNumElements(); assert(Scale > 1); @@ -2335,7 +2334,7 @@ WebAssemblyTargetLowering::LowerAccessVectorElement(SDValue Op, SDNode *IdxNode = Op.getOperand(Op.getNumOperands() - 1).getNode(); if (isa<ConstantSDNode>(IdxNode)) { // Ensure the index type is i32 to match the tablegen patterns - uint64_t Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue(); + uint64_t Idx = IdxNode->getAsZExtVal(); SmallVector<SDValue, 3> Ops(Op.getNode()->ops()); Ops[Op.getNumOperands() - 1] = DAG.getConstant(Idx, SDLoc(IdxNode), MVT::i32); |