diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | 38 |
1 files changed, 29 insertions, 9 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index 82581eb3c30a..908eb6d1fab1 100644 --- a/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -83,9 +83,9 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/TargetRegistry.h" #include "llvm/Support/Debug.h" #include "llvm/Support/Format.h" -#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -150,6 +150,12 @@ static InstrUID decode(OpcodeType type, InstructionContext insnContext, dec = &THREEDNOW_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; break; + case MAP5: + dec = &MAP5_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; + break; + case MAP6: + dec = &MAP6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; + break; } switch (dec->modrm_type) { @@ -332,7 +338,7 @@ static int readPrefixes(struct InternalInstruction *insn) { } if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) && - ((~byte1 & 0xc) == 0xc) && ((byte2 & 0x4) == 0x4)) { + ((~byte1 & 0x8) == 0x8) && ((byte2 & 0x4) == 0x4)) { insn->vectorExtensionType = TYPE_EVEX; } else { --insn->readerCursor; // unconsume byte1 @@ -800,10 +806,6 @@ static int readModRM(struct InternalInstruction *insn) { return prefix##_DR0 + index; \ case TYPE_CONTROLREG: \ return prefix##_CR0 + index; \ - case TYPE_BNDR: \ - if (index > 3) \ - *valid = 0; \ - return prefix##_BND0 + index; \ case TYPE_MVSIBX: \ return prefix##_XMM0 + index; \ case TYPE_MVSIBY: \ @@ -876,11 +878,11 @@ static bool readOpcode(struct InternalInstruction *insn) { insn->opcodeType = ONEBYTE; if (insn->vectorExtensionType == TYPE_EVEX) { - switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) { + switch (mmmFromEVEX2of4(insn->vectorExtensionPrefix[1])) { default: LLVM_DEBUG( - dbgs() << format("Unhandled mm field for instruction (0x%hhx)", - mmFromEVEX2of4(insn->vectorExtensionPrefix[1]))); + dbgs() << format("Unhandled mmm field for instruction (0x%hhx)", + mmmFromEVEX2of4(insn->vectorExtensionPrefix[1]))); return true; case VEX_LOB_0F: insn->opcodeType = TWOBYTE; @@ -891,6 +893,12 @@ static bool readOpcode(struct InternalInstruction *insn) { case VEX_LOB_0F3A: insn->opcodeType = THREEBYTE_3A; return consume(insn, insn->opcode); + case VEX_LOB_MAP5: + insn->opcodeType = MAP5; + return consume(insn, insn->opcode); + case VEX_LOB_MAP6: + insn->opcodeType = MAP6; + return consume(insn, insn->opcode); } } else if (insn->vectorExtensionType == TYPE_VEX_3B) { switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) { @@ -908,6 +916,12 @@ static bool readOpcode(struct InternalInstruction *insn) { case VEX_LOB_0F3A: insn->opcodeType = THREEBYTE_3A; return consume(insn, insn->opcode); + case VEX_LOB_MAP5: + insn->opcodeType = MAP5; + return consume(insn, insn->opcode); + case VEX_LOB_MAP6: + insn->opcodeType = MAP6; + return consume(insn, insn->opcode); } } else if (insn->vectorExtensionType == TYPE_VEX_2B) { insn->opcodeType = TWOBYTE; @@ -1043,6 +1057,12 @@ static int getInstructionIDWithAttrMask(uint16_t *instructionID, case THREEDNOW_MAP: decision = &THREEDNOW_MAP_SYM; break; + case MAP5: + decision = &MAP5_SYM; + break; + case MAP6: + decision = &MAP6_SYM; + break; } if (decision->opcodeDecisions[insnCtx] |