diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/X86/X86InstrAMX.td')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/X86/X86InstrAMX.td | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/X86/X86InstrAMX.td b/contrib/llvm-project/llvm/lib/Target/X86/X86InstrAMX.td index 2dbb3e5ee316..7f3e193d9a1b 100644 --- a/contrib/llvm-project/llvm/lib/Target/X86/X86InstrAMX.td +++ b/contrib/llvm-project/llvm/lib/Target/X86/X86InstrAMX.td @@ -20,32 +20,32 @@ let Predicates = [HasAMXTILE, In64BitMode] in { Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in def LDTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src), "ldtilecfg\t$src", - [(int_x86_ldtilecfg addr:$src)]>, VEX, T8PS; + [(int_x86_ldtilecfg addr:$src)]>, VEX, T8; let hasSideEffects = 1 in def STTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src), "sttilecfg\t$src", - [(int_x86_sttilecfg addr:$src)]>, VEX, T8PD; + [(int_x86_sttilecfg addr:$src)]>, VEX, T8, PD; let mayLoad = 1 in def TILELOADD : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst), (ins sibmem:$src), "tileloadd\t{$src, $dst|$dst, $src}", []>, - VEX, T8XD; + VEX, T8, XD; let mayLoad = 1 in def TILELOADDT1 : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst), (ins sibmem:$src), "tileloaddt1\t{$src, $dst|$dst, $src}", []>, - VEX, T8PD; + VEX, T8, PD; let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in def TILERELEASE : I<0x49, MRM_C0, (outs), (ins), - "tilerelease", [(int_x86_tilerelease)]>, VEX, T8PS; + "tilerelease", [(int_x86_tilerelease)]>, VEX, T8; let mayStore = 1 in def TILESTORED : I<0x4b, MRMDestMemFSIB, (outs), (ins sibmem:$dst, TILE:$src), "tilestored\t{$src, $dst|$dst, $src}", []>, - VEX, T8XS; + VEX, T8, XS; def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins), "tilezero\t$dst", []>, - VEX, T8XD; + VEX, T8, XD; // Pseduo instruction for RA. let isPseudo = true, mayLoad = 1, hasSideEffects = 1, @@ -91,19 +91,19 @@ let Predicates = [HasAMXINT8, In64BitMode] in { def TDPBSSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst), (ins TILE:$src1, TILE:$src2, TILE:$src3), "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>, - VEX_4V, T8XD; + VEX, VVVV, T8, XD; def TDPBSUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst), (ins TILE:$src1, TILE:$src2, TILE:$src3), "tdpbsud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>, - VEX_4V, T8XS; + VEX, VVVV, T8, XS; def TDPBUSD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst), (ins TILE:$src1, TILE:$src2, TILE:$src3), "tdpbusd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>, - VEX_4V, T8PD; + VEX, VVVV, T8, PD; def TDPBUUD : I<0x5e, MRMSrcReg4VOp3, (outs TILE:$dst), (ins TILE:$src1, TILE:$src2, TILE:$src3), "tdpbuud\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>, - VEX_4V, T8PS; + VEX, VVVV, T8; } // Pseduo instruction for RA. @@ -163,7 +163,7 @@ let Predicates = [HasAMXBF16, In64BitMode] in { def TDPBF16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst), (ins TILE:$src1, TILE:$src2, TILE:$src3), "tdpbf16ps\t{$src3, $src2, $dst|$dst, $src2, $src3}", - []>, VEX_4V, T8XS; + []>, VEX, VVVV, T8, XS; // Pseduo instruction for RA. let isPseudo = true, Constraints = "$src4 = $dst" in @@ -193,7 +193,7 @@ let Predicates = [HasAMXFP16, In64BitMode] in { def TDPFP16PS : I<0x5c, MRMSrcReg4VOp3, (outs TILE:$dst), (ins TILE:$src1, TILE:$src2, TILE:$src3), "tdpfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}", - []>, VEX_4V, T8XD; + []>, VEX, VVVV, T8, XD; } // Pseduo instruction for RA. @@ -222,11 +222,11 @@ let Predicates = [HasAMXCOMPLEX, In64BitMode] in { def TCMMIMFP16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst), (ins TILE:$src1, TILE:$src2, TILE:$src3), "tcmmimfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}", - []>, T8PD, VEX_4V; + []>, T8, PD, VEX, VVVV; def TCMMRLFP16PS : I<0x6c, MRMSrcReg4VOp3, (outs TILE:$dst), (ins TILE:$src1, TILE:$src2, TILE:$src3), "tcmmrlfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}", - []>, VEX_4V, WIG, T8PS; + []>, VEX, VVVV, WIG, T8; } // Constraints = "$src1 = $dst" |