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Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/X86/X86InstrTDX.td')
-rw-r--r-- | contrib/llvm-project/llvm/lib/Target/X86/X86InstrTDX.td | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/X86/X86InstrTDX.td b/contrib/llvm-project/llvm/lib/Target/X86/X86InstrTDX.td new file mode 100644 index 000000000000..8d7cd6082095 --- /dev/null +++ b/contrib/llvm-project/llvm/lib/Target/X86/X86InstrTDX.td @@ -0,0 +1,39 @@ +//===- X86InstrTDX.td - TDX Instruction Set Extension -*- tablegen -*===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the instructions that make up the Intel TDX instruction +// set. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// TDX instructions + +// 64-bit only instructions +let SchedRW = [WriteSystem], Predicates = [In64BitMode] in { +// SEAMCALL - Call to SEAM VMX-root Operation Module +def SEAMCALL : I<0x01, MRM_CF, (outs), (ins), + "seamcall", []>, PD; + +// SEAMRET - Return to Legacy VMX-root Operation +def SEAMRET : I<0x01, MRM_CD, (outs), (ins), + "seamret", []>, PD; + +// SEAMOPS - SEAM Operations +def SEAMOPS : I<0x01, MRM_CE, (outs), (ins), + "seamops", []>, PD; + +} // SchedRW + +// common instructions +let SchedRW = [WriteSystem] in { +// TDCALL - Call SEAM Module Functions +def TDCALL : I<0x01, MRM_CC, (outs), (ins), + "tdcall", []>, PD; + +} // SchedRW |