aboutsummaryrefslogtreecommitdiff
path: root/contrib/llvm-project/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'contrib/llvm-project/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp')
-rw-r--r--contrib/llvm-project/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp234
1 files changed, 106 insertions, 128 deletions
diff --git a/contrib/llvm-project/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp b/contrib/llvm-project/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
index f298e639bf7f..183c8f9494db 100644
--- a/contrib/llvm-project/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
+++ b/contrib/llvm-project/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -37,11 +37,11 @@
// compressing/uncompressing MCInst instructions, plus
// some helper functions:
//
-// bool compressInst(MCInst& OutInst, const MCInst &MI,
+// bool compressInst(MCInst &OutInst, const MCInst &MI,
// const MCSubtargetInfo &STI,
// MCContext &Context);
//
-// bool uncompressInst(MCInst& OutInst, const MCInst &MI,
+// bool uncompressInst(MCInst &OutInst, const MCInst &MI,
// const MCRegisterInfo &MRI,
// const MCSubtargetInfo &STI);
//
@@ -101,11 +101,12 @@ class RISCVCompressInstEmitter {
IndexedMap<OpData>
DestOperandMap; // Maps operands in the Dest Instruction
// to the corresponding Source instruction operand.
+ bool IsCompressOnly;
CompressPat(CodeGenInstruction &S, CodeGenInstruction &D,
std::vector<Record *> RF, IndexedMap<OpData> &SourceMap,
- IndexedMap<OpData> &DestMap)
+ IndexedMap<OpData> &DestMap, bool IsCompressOnly)
: Source(S), Dest(D), PatReqFeatures(RF), SourceOperandMap(SourceMap),
- DestOperandMap(DestMap) {}
+ DestOperandMap(DestMap), IsCompressOnly(IsCompressOnly) {}
};
enum EmitterType { Compress, Uncompress, CheckCompress };
RecordKeeper &Records;
@@ -138,13 +139,12 @@ public:
} // End anonymous namespace.
bool RISCVCompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) {
- assert(Reg->isSubClassOf("Register") && "Reg record should be a Register\n");
- assert(RegClass->isSubClassOf("RegisterClass") && "RegClass record should be"
- " a RegisterClass\n");
+ assert(Reg->isSubClassOf("Register") && "Reg record should be a Register");
+ assert(RegClass->isSubClassOf("RegisterClass") &&
+ "RegClass record should be a RegisterClass");
const CodeGenRegisterClass &RC = Target.getRegisterClass(RegClass);
const CodeGenRegister *R = Target.getRegisterByName(Reg->getName().lower());
- assert((R != nullptr) &&
- ("Register" + Reg->getName().str() + " not defined!!\n").c_str());
+ assert((R != nullptr) && "Register not defined!!");
return RC.contains(R);
}
@@ -237,9 +237,9 @@ void RISCVCompressInstEmitter::addDagOperandMapping(
if (Inst.Operands[i].Rec->isSubClassOf("RegisterClass"))
PrintFatalError(
Rec->getLoc(),
- ("Error in Dag '" + Dag->getAsString() + "' Found immediate: '" +
- II->getAsString() +
- "' but corresponding instruction operand expected a register!"));
+ "Error in Dag '" + Dag->getAsString() + "' Found immediate: '" +
+ II->getAsString() +
+ "' but corresponding instruction operand expected a register!");
// No pattern validation check possible for values of fixed immediate.
OperandMap[i].Kind = OpData::Imm;
OperandMap[i].Data.Imm = II->getValue();
@@ -285,11 +285,7 @@ static bool verifyDagOpCount(CodeGenInstruction &Inst, DagInit *Dag,
}
static bool validateArgsTypes(Init *Arg1, Init *Arg2) {
- DefInit *Type1 = dyn_cast<DefInit>(Arg1);
- DefInit *Type2 = dyn_cast<DefInit>(Arg2);
- assert(Type1 && ("Arg1 type not found\n"));
- assert(Type2 && ("Arg2 type not found\n"));
- return Type1->getDef() == Type2->getDef();
+ return cast<DefInit>(Arg1)->getDef() == cast<DefInit>(Arg2)->getDef();
}
// Creates a mapping between the operand name in the Dag (e.g. $rs1) and
@@ -471,7 +467,8 @@ void RISCVCompressInstEmitter::evaluateCompressPat(Record *Rec) {
});
CompressPatterns.push_back(CompressPat(SourceInst, DestInst, PatReqFeatures,
- SourceOperandMap, DestOperandMap));
+ SourceOperandMap, DestOperandMap,
+ Rec->getValueAsBit("isCompressOnly")));
}
static void
@@ -514,50 +511,41 @@ getReqFeatures(std::set<std::pair<bool, StringRef>> &FeaturesSet,
static unsigned getPredicates(DenseMap<const Record *, unsigned> &PredicateMap,
std::vector<const Record *> &Predicates,
Record *Rec, StringRef Name) {
- unsigned Entry = PredicateMap[Rec];
+ unsigned &Entry = PredicateMap[Rec];
if (Entry)
return Entry;
if (!Rec->isValueUnset(Name)) {
Predicates.push_back(Rec);
Entry = Predicates.size();
- PredicateMap[Rec] = Entry;
return Entry;
}
PrintFatalError(Rec->getLoc(), "No " + Name +
- " predicate on this operand at all: '" + Rec->getName().str() + "'");
+ " predicate on this operand at all: '" +
+ Rec->getName() + "'");
return 0;
}
-static void printPredicates(std::vector<const Record *> &Predicates,
+static void printPredicates(const std::vector<const Record *> &Predicates,
StringRef Name, raw_ostream &o) {
for (unsigned i = 0; i < Predicates.size(); ++i) {
- Init *Pred = Predicates[i]->getValueInit(Name);
- if (CodeInit *SI = dyn_cast<CodeInit>(Pred))
- o << " case " << i + 1 << ": {\n"
- << " // " << Predicates[i]->getName().str() << "\n"
- << " " << SI->getValue() << "\n"
- << " }\n";
- else
- llvm_unreachable("Unexpected predicate field!");
+ StringRef Pred = Predicates[i]->getValueAsString(Name);
+ o << " case " << i + 1 << ": {\n"
+ << " // " << Predicates[i]->getName() << "\n"
+ << " " << Pred << "\n"
+ << " }\n";
}
}
-static std::string mergeCondAndCode(raw_string_ostream &CondStream,
- raw_string_ostream &CodeStream) {
- std::string S;
- raw_string_ostream CombinedStream(S);
- CombinedStream.indent(4)
- << "if ("
- << CondStream.str().substr(
- 6, CondStream.str().length() -
- 10) // remove first indentation and last '&&'.
- << ") {\n";
- CombinedStream << CodeStream.str();
+static void mergeCondAndCode(raw_ostream &CombinedStream, StringRef CondStr,
+ StringRef CodeStr) {
+ // Remove first indentation and last '&&'.
+ CondStr = CondStr.drop_front(6).drop_back(4);
+ CombinedStream.indent(4) << "if (" << CondStr << ") {\n";
+ CombinedStream << CodeStr;
CombinedStream.indent(4) << " return true;\n";
CombinedStream.indent(4) << "} // if\n";
- return CombinedStream.str();
}
void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
@@ -568,23 +556,20 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
"'PassSubtarget' is false. SubTargetInfo object is needed "
"for target features.\n");
- std::string Namespace = std::string(Target.getName());
+ StringRef Namespace = Target.getName();
// Sort entries in CompressPatterns to handle instructions that can have more
// than one candidate for compression\uncompression, e.g ADD can be
// transformed to a C_ADD or a C_MV. When emitting 'uncompress()' function the
// source and destination are flipped and the sort key needs to change
// accordingly.
- llvm::stable_sort(CompressPatterns,
- [EType](const CompressPat &LHS, const CompressPat &RHS) {
- if (EType == EmitterType::Compress ||
- EType == EmitterType::CheckCompress)
- return (LHS.Source.TheDef->getName().str() <
- RHS.Source.TheDef->getName().str());
- else
- return (LHS.Dest.TheDef->getName().str() <
- RHS.Dest.TheDef->getName().str());
- });
+ llvm::stable_sort(CompressPatterns, [EType](const CompressPat &LHS,
+ const CompressPat &RHS) {
+ if (EType == EmitterType::Compress || EType == EmitterType::CheckCompress)
+ return (LHS.Source.TheDef->getName() < RHS.Source.TheDef->getName());
+ else
+ return (LHS.Dest.TheDef->getName() < RHS.Dest.TheDef->getName());
+ });
// A list of MCOperandPredicates for all operands in use, and the reverse map.
std::vector<const Record *> MCOpPredicates;
@@ -610,17 +595,17 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
<< "#undef GEN_CHECK_COMPRESS_INSTR\n\n";
if (EType == EmitterType::Compress) {
- FuncH << "static bool compressInst(MCInst& OutInst,\n";
+ FuncH << "static bool compressInst(MCInst &OutInst,\n";
FuncH.indent(25) << "const MCInst &MI,\n";
FuncH.indent(25) << "const MCSubtargetInfo &STI,\n";
FuncH.indent(25) << "MCContext &Context) {\n";
} else if (EType == EmitterType::Uncompress){
- FuncH << "static bool uncompressInst(MCInst& OutInst,\n";
+ FuncH << "static bool uncompressInst(MCInst &OutInst,\n";
FuncH.indent(27) << "const MCInst &MI,\n";
FuncH.indent(27) << "const MCRegisterInfo &MRI,\n";
FuncH.indent(27) << "const MCSubtargetInfo &STI) {\n";
} else if (EType == EmitterType::CheckCompress) {
- FuncH << "static bool isCompressibleInst(const MachineInstr& MI,\n";
+ FuncH << "static bool isCompressibleInst(const MachineInstr &MI,\n";
FuncH.indent(27) << "const RISCVSubtarget *Subtarget,\n";
FuncH.indent(27) << "const MCRegisterInfo &MRI,\n";
FuncH.indent(27) << "const MCSubtargetInfo &STI) {\n";
@@ -638,10 +623,10 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
return;
}
- std::string CaseString("");
+ std::string CaseString;
raw_string_ostream CaseStream(CaseString);
- std::string PrevOp("");
- std::string CurOp("");
+ StringRef PrevOp;
+ StringRef CurOp;
CaseStream << " switch (MI.getOpcode()) {\n";
CaseStream << " default: return false;\n";
@@ -651,6 +636,9 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
EType == EmitterType::Compress || EType == EmitterType::Uncompress;
for (auto &CompressPat : CompressPatterns) {
+ if (EType == EmitterType::Uncompress && CompressPat.IsCompressOnly)
+ continue;
+
std::string CondString;
std::string CodeString;
raw_string_ostream CondStream(CondString);
@@ -664,10 +652,10 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
IndexedMap<OpData> &DestOperandMap = CompressOrCheck ?
CompressPat.DestOperandMap : CompressPat.SourceOperandMap;
- CurOp = Source.TheDef->getName().str();
+ CurOp = Source.TheDef->getName();
// Check current and previous opcode to decide to continue or end a case.
if (CurOp != PrevOp) {
- if (PrevOp != "")
+ if (!PrevOp.empty())
CaseStream.indent(6) << "break;\n } // case " + PrevOp + "\n";
CaseStream.indent(4) << "case " + Namespace + "::" + CurOp + ": {\n";
}
@@ -688,9 +676,9 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
// Emit checks for all required features.
for (auto &Op : FeaturesSet) {
StringRef Not = Op.first ? "!" : "";
- CondStream.indent(6)
- << Not << ("STI.getFeatureBits()[" + Namespace + "::" + Op.second + "]").str() +
- " &&\n";
+ CondStream.indent(6) << Not << "STI.getFeatureBits()[" << Namespace
+ << "::" << Op.second << "]"
+ << " &&\n";
}
// Emit checks for all required feature groups.
@@ -699,8 +687,8 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
for (auto &Op : Set) {
bool isLast = &Op == &*Set.rbegin();
StringRef Not = Op.first ? "!" : "";
- CondStream << Not << ("STI.getFeatureBits()[" + Namespace + "::" + Op.second +
- "]").str();
+ CondStream << Not << "STI.getFeatureBits()[" << Namespace
+ << "::" << Op.second << "]";
if (!isLast)
CondStream << " || ";
}
@@ -713,10 +701,8 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
if (SourceOperandMap[OpNo].TiedOpIdx != -1) {
if (Source.Operands[OpNo].Rec->isSubClassOf("RegisterClass"))
CondStream.indent(6)
- << "(MI.getOperand("
- << std::to_string(OpNo) + ").getReg() == MI.getOperand("
- << std::to_string(SourceOperandMap[OpNo].TiedOpIdx)
- << ").getReg()) &&\n";
+ << "(MI.getOperand(" << OpNo << ").getReg() == MI.getOperand("
+ << SourceOperandMap[OpNo].TiedOpIdx << ").getReg()) &&\n";
else
PrintFatalError("Unexpected tied operand types!\n");
}
@@ -727,27 +713,26 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
break;
case OpData::Imm:
CondStream.indent(6)
- << "(MI.getOperand(" + std::to_string(OpNo) + ").isImm()) &&\n" +
- " (MI.getOperand(" + std::to_string(OpNo) +
- ").getImm() == " +
- std::to_string(SourceOperandMap[OpNo].Data.Imm) + ") &&\n";
+ << "(MI.getOperand(" << OpNo << ").isImm()) &&\n"
+ << " (MI.getOperand(" << OpNo
+ << ").getImm() == " << SourceOperandMap[OpNo].Data.Imm << ") &&\n";
break;
case OpData::Reg: {
Record *Reg = SourceOperandMap[OpNo].Data.Reg;
- CondStream.indent(6) << "(MI.getOperand(" + std::to_string(OpNo) +
- ").getReg() == " + Namespace +
- "::" + Reg->getName().str() + ") &&\n";
+ CondStream.indent(6)
+ << "(MI.getOperand(" << OpNo << ").getReg() == " << Namespace
+ << "::" << Reg->getName() << ") &&\n";
break;
}
}
}
- CodeStream.indent(6) << "// " + Dest.AsmString + "\n";
+ CodeStream.indent(6) << "// " << Dest.AsmString << "\n";
if (CompressOrUncompress)
- CodeStream.indent(6) << "OutInst.setOpcode(" + Namespace +
- "::" + Dest.TheDef->getName().str() + ");\n";
+ CodeStream.indent(6) << "OutInst.setOpcode(" << Namespace
+ << "::" << Dest.TheDef->getName() << ");\n";
OpNo = 0;
for (const auto &DestOperand : Dest.Operands) {
- CodeStream.indent(6) << "// Operand: " + DestOperand.Name + "\n";
+ CodeStream.indent(6) << "// Operand: " << DestOperand.Name << "\n";
switch (DestOperandMap[OpNo].Kind) {
case OpData::Operand: {
unsigned OpIdx = DestOperandMap[OpNo].Data.Operand;
@@ -759,68 +744,67 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
// Don't check register class if this is a tied operand, it was done
// for the operand its tied to.
if (DestOperand.getTiedRegister() == -1)
- CondStream.indent(6)
- << "(MRI.getRegClass(" + Namespace +
- "::" + DestOperand.Rec->getName().str() +
- "RegClassID).contains(" + "MI.getOperand(" +
- std::to_string(OpIdx) + ").getReg())) &&\n";
+ CondStream.indent(6) << "(MRI.getRegClass(" << Namespace
+ << "::" << DestOperand.Rec->getName()
+ << "RegClassID).contains(MI.getOperand("
+ << OpIdx << ").getReg())) &&\n";
if (CompressOrUncompress)
- CodeStream.indent(6) << "OutInst.addOperand(MI.getOperand(" +
- std::to_string(OpIdx) + "));\n";
+ CodeStream.indent(6)
+ << "OutInst.addOperand(MI.getOperand(" << OpIdx << "));\n";
} else {
// Handling immediate operands.
if (CompressOrUncompress) {
- unsigned Entry = getPredicates(MCOpPredicateMap, MCOpPredicates,
- DestOperand.Rec, StringRef("MCOperandPredicate"));
- CondStream.indent(6) << Namespace + "ValidateMCOperand(" +
- "MI.getOperand(" + std::to_string(OpIdx) +
- "), STI, " + std::to_string(Entry) +
- ") &&\n";
+ unsigned Entry =
+ getPredicates(MCOpPredicateMap, MCOpPredicates, DestOperand.Rec,
+ "MCOperandPredicate");
+ CondStream.indent(6)
+ << Namespace << "ValidateMCOperand("
+ << "MI.getOperand(" << OpIdx << "), STI, " << Entry << ") &&\n";
} else {
- unsigned Entry = getPredicates(ImmLeafPredicateMap, ImmLeafPredicates,
- DestOperand.Rec, StringRef("ImmediateCode"));
- CondStream.indent(6) << "MI.getOperand(" + std::to_string(OpIdx) +
- ").isImm() && \n";
- CondStream.indent(6) << Namespace + "ValidateMachineOperand(" +
- "MI.getOperand(" + std::to_string(OpIdx) +
- "), Subtarget, " + std::to_string(Entry) +
- ") &&\n";
+ unsigned Entry =
+ getPredicates(ImmLeafPredicateMap, ImmLeafPredicates,
+ DestOperand.Rec, "ImmediateCode");
+ CondStream.indent(6)
+ << "MI.getOperand(" << OpIdx << ").isImm() &&\n";
+ CondStream.indent(6) << Namespace << "ValidateMachineOperand("
+ << "MI.getOperand(" << OpIdx
+ << "), Subtarget, " << Entry << ") &&\n";
}
if (CompressOrUncompress)
- CodeStream.indent(6) << "OutInst.addOperand(MI.getOperand(" +
- std::to_string(OpIdx) + "));\n";
+ CodeStream.indent(6)
+ << "OutInst.addOperand(MI.getOperand(" << OpIdx << "));\n";
}
break;
}
case OpData::Imm: {
if (CompressOrUncompress) {
unsigned Entry = getPredicates(MCOpPredicateMap, MCOpPredicates,
- DestOperand.Rec, StringRef("MCOperandPredicate"));
+ DestOperand.Rec, "MCOperandPredicate");
CondStream.indent(6)
- << Namespace + "ValidateMCOperand(" + "MCOperand::createImm(" +
- std::to_string(DestOperandMap[OpNo].Data.Imm) + "), STI, " +
- std::to_string(Entry) + ") &&\n";
+ << Namespace << "ValidateMCOperand("
+ << "MCOperand::createImm(" << DestOperandMap[OpNo].Data.Imm
+ << "), STI, " << Entry << ") &&\n";
} else {
unsigned Entry = getPredicates(ImmLeafPredicateMap, ImmLeafPredicates,
- DestOperand.Rec, StringRef("ImmediateCode"));
+ DestOperand.Rec, "ImmediateCode");
CondStream.indent(6)
- << Namespace + "ValidateMachineOperand(" + "MachineOperand::CreateImm(" +
- std::to_string(DestOperandMap[OpNo].Data.Imm) + "), SubTarget, " +
- std::to_string(Entry) + ") &&\n";
+ << Namespace
+ << "ValidateMachineOperand(MachineOperand::CreateImm("
+ << DestOperandMap[OpNo].Data.Imm << "), SubTarget, " << Entry
+ << ") &&\n";
}
if (CompressOrUncompress)
- CodeStream.indent(6)
- << "OutInst.addOperand(MCOperand::createImm(" +
- std::to_string(DestOperandMap[OpNo].Data.Imm) + "));\n";
+ CodeStream.indent(6) << "OutInst.addOperand(MCOperand::createImm("
+ << DestOperandMap[OpNo].Data.Imm << "));\n";
} break;
case OpData::Reg: {
if (CompressOrUncompress) {
// Fixed register has been validated at pattern validation time.
Record *Reg = DestOperandMap[OpNo].Data.Reg;
- CodeStream.indent(6) << "OutInst.addOperand(MCOperand::createReg(" +
- Namespace + "::" + Reg->getName().str() +
- "));\n";
+ CodeStream.indent(6)
+ << "OutInst.addOperand(MCOperand::createReg(" << Namespace
+ << "::" << Reg->getName() << "));\n";
}
} break;
}
@@ -828,12 +812,12 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
}
if (CompressOrUncompress)
CodeStream.indent(6) << "OutInst.setLoc(MI.getLoc());\n";
- CaseStream << mergeCondAndCode(CondStream, CodeStream);
+ mergeCondAndCode(CaseStream, CondStream.str(), CodeStream.str());
PrevOp = CurOp;
}
Func << CaseStream.str() << "\n";
// Close brace for the last case.
- Func.indent(4) << "} // case " + CurOp + "\n";
+ Func.indent(4) << "} // case " << CurOp << "\n";
Func.indent(2) << "} // switch\n";
Func.indent(2) << "return false;\n}\n";
@@ -858,7 +842,7 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
<< "ValidateMachineOperand(const MachineOperand &MO,\n"
<< " const RISCVSubtarget *Subtarget,\n"
<< " unsigned PredicateIndex) {\n"
- << " int64_t Imm = MO.getImm(); \n"
+ << " int64_t Imm = MO.getImm();\n"
<< " switch (PredicateIndex) {\n"
<< " default:\n"
<< " llvm_unreachable(\"Unknown ImmLeaf Predicate kind\");\n"
@@ -884,13 +868,7 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
}
void RISCVCompressInstEmitter::run(raw_ostream &o) {
- Record *CompressClass = Records.getClass("CompressPat");
- assert(CompressClass && "Compress class definition missing!");
- std::vector<Record *> Insts;
- for (const auto &D : Records.getDefs()) {
- if (D.second->isSubClassOf(CompressClass))
- Insts.push_back(D.second.get());
- }
+ std::vector<Record *> Insts = Records.getAllDerivedDefinitions("CompressPat");
// Process the CompressPat definitions, validating them as we do so.
for (unsigned i = 0, e = Insts.size(); i != e; ++i)
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-01 06:55:03 +0000