diff options
Diffstat (limited to 'contrib/llvm/utils/TableGen/X86FoldTablesEmitter.cpp')
| -rw-r--r-- | contrib/llvm/utils/TableGen/X86FoldTablesEmitter.cpp | 45 |
1 files changed, 20 insertions, 25 deletions
diff --git a/contrib/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/contrib/llvm/utils/TableGen/X86FoldTablesEmitter.cpp index ff1afa89efc8..1ea668643575 100644 --- a/contrib/llvm/utils/TableGen/X86FoldTablesEmitter.cpp +++ b/contrib/llvm/utils/TableGen/X86FoldTablesEmitter.cpp @@ -47,7 +47,9 @@ const char *ExplicitAlign[] = {"MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS", "MOVNTPD", "MOVNTDQ", "MOVNTDQA"}; // List of instructions NOT requiring explicit memory alignment. -const char *ExplicitUnalign[] = {"MOVDQU", "MOVUPS", "MOVUPD"}; +const char *ExplicitUnalign[] = {"MOVDQU", "MOVUPS", "MOVUPD", + "PCMPESTRM", "PCMPESTRI", + "PCMPISTRM", "PCMPISTRI" }; // For manually mapping instructions that do not match by their encoding. const ManualMapEntry ManualMapSet[] = { @@ -63,9 +65,9 @@ const ManualMapEntry ManualMapSet[] = { { "ADD16rr_DB", "ADD16rm", NO_UNFOLD }, { "ADD32rr_DB", "ADD32rm", NO_UNFOLD }, { "ADD64rr_DB", "ADD64rm", NO_UNFOLD }, - { "PUSH16r", "PUSH16rmm", NO_UNFOLD }, - { "PUSH32r", "PUSH32rmm", NO_UNFOLD }, - { "PUSH64r", "PUSH64rmm", NO_UNFOLD }, + { "PUSH16r", "PUSH16rmm", UNFOLD }, + { "PUSH32r", "PUSH32rmm", UNFOLD }, + { "PUSH64r", "PUSH64rmm", UNFOLD }, { "TAILJMPr", "TAILJMPm", UNFOLD }, { "TAILJMPr64", "TAILJMPm64", UNFOLD }, { "TAILJMPr64_REX", "TAILJMPm64_REX", UNFOLD }, @@ -106,8 +108,8 @@ class X86FoldTablesEmitter { friend raw_ostream &operator<<(raw_ostream &OS, const X86FoldTableEntry &E) { - OS << "{ X86::" << E.RegInst->TheDef->getName().str() - << ", X86::" << E.MemInst->TheDef->getName().str() << ", "; + OS << "{ X86::" << E.RegInst->TheDef->getName() + << ", X86::" << E.MemInst->TheDef->getName() << ", "; if (E.IsLoad) OS << "TB_FOLDED_LOAD | "; @@ -157,7 +159,7 @@ private: // Print the given table as a static const C++ array of type // X86MemoryFoldTableEntry. - void printTable(const FoldTable &Table, std::string TableName, + void printTable(const FoldTable &Table, StringRef TableName, raw_ostream &OS) { OS << "static const X86MemoryFoldTableEntry MemoryFold" << TableName << "[] = {\n"; @@ -251,16 +253,6 @@ getMemOperandSize(const Record *MemRec, const bool IntrinsicSensitive = false) { llvm_unreachable("Memory operand's size not known!"); } -// Returns true if the record's list of defs includes the given def. -static inline bool hasDefInList(const Record *Rec, const StringRef List, - const StringRef Def) { - if (!Rec->isValueUnset(List)) { - return any_of(*(Rec->getValueAsListInit(List)), - [Def](const Init *I) { return I->getAsString() == Def; }); - } - return false; -} - // Return true if the instruction defined as a register flavor. static inline bool hasRegisterFormat(const Record *Inst) { const BitsInit *FormBits = Inst->getValueAsBitsInit("FormBits"); @@ -335,20 +327,24 @@ public: MemRec->getValueAsDef("OpPrefix") || RegRec->getValueAsDef("OpMap") != MemRec->getValueAsDef("OpMap") || RegRec->getValueAsDef("OpSize") != MemRec->getValueAsDef("OpSize") || + RegRec->getValueAsDef("AdSize") != MemRec->getValueAsDef("AdSize") || RegRec->getValueAsBit("hasVEX_4V") != MemRec->getValueAsBit("hasVEX_4V") || RegRec->getValueAsBit("hasEVEX_K") != MemRec->getValueAsBit("hasEVEX_K") || RegRec->getValueAsBit("hasEVEX_Z") != MemRec->getValueAsBit("hasEVEX_Z") || - RegRec->getValueAsBit("hasEVEX_B") != - MemRec->getValueAsBit("hasEVEX_B") || + // EVEX_B means different things for memory and register forms. + RegRec->getValueAsBit("hasEVEX_B") != 0 || + MemRec->getValueAsBit("hasEVEX_B") != 0 || RegRec->getValueAsBit("hasEVEX_RC") != MemRec->getValueAsBit("hasEVEX_RC") || RegRec->getValueAsBit("hasREX_WPrefix") != MemRec->getValueAsBit("hasREX_WPrefix") || RegRec->getValueAsBit("hasLockPrefix") != MemRec->getValueAsBit("hasLockPrefix") || + RegRec->getValueAsBit("hasNoTrackPrefix") != + MemRec->getValueAsBit("hasNoTrackPrefix") || !equalBitsInits(RegRec->getValueAsBitsInit("EVEX_LL"), MemRec->getValueAsBitsInit("EVEX_LL")) || !equalBitsInits(RegRec->getValueAsBitsInit("VEX_WPrefix"), @@ -511,10 +507,8 @@ void X86FoldTablesEmitter::updateTables(const CodeGenInstruction *RegInstr, unsigned MemInSize = MemRec->getValueAsDag("InOperandList")->getNumArgs(); unsigned RegInSize = RegRec->getValueAsDag("InOperandList")->getNumArgs(); - // Instructions which have the WriteRMW value (Read-Modify-Write) should be - // added to Table2Addr. - if (hasDefInList(MemRec, "SchedRW", "WriteRMW") && MemOutSize != RegOutSize && - MemInSize == RegInSize) { + // Instructions which Read-Modify-Write should be added to Table2Addr. + if (MemOutSize != RegOutSize && MemInSize == RegInSize) { addEntryWithFlags(Table2Addr, RegInstr, MemInstr, S, 0); return; } @@ -548,7 +542,7 @@ void X86FoldTablesEmitter::updateTables(const CodeGenInstruction *RegInstr, } } else if (MemInSize == RegInSize + 1 && MemOutSize + 1 == RegOutSize) { // Store-Folding cases. - // If the memory form instruction performs performs a store, the *output* + // If the memory form instruction performs a store, the *output* // register of the register form instructions disappear and instead a // memory *input* operand appears in the memory form instruction. // For example: @@ -556,7 +550,8 @@ void X86FoldTablesEmitter::updateTables(const CodeGenInstruction *RegInstr, // MOVAPSmr => (outs), (ins f128mem:$dst, VR128:$src) Record *RegOpRec = RegInstr->Operands[RegOutSize - 1].Rec; Record *MemOpRec = MemInstr->Operands[RegOutSize - 1].Rec; - if (isRegisterOperand(RegOpRec) && isMemoryOperand(MemOpRec)) + if (isRegisterOperand(RegOpRec) && isMemoryOperand(MemOpRec) && + getRegOperandSize(RegOpRec) == getMemOperandSize(MemOpRec)) addEntryWithFlags(Table0, RegInstr, MemInstr, S, 0); } |