diff options
Diffstat (limited to 'lib/Target/AArch64/Utils/AArch64BaseInfo.h')
| -rw-r--r-- | lib/Target/AArch64/Utils/AArch64BaseInfo.h | 50 |
1 files changed, 46 insertions, 4 deletions
diff --git a/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/lib/Target/AArch64/Utils/AArch64BaseInfo.h index 44c6a6b44895..e5e2fc2cb0df 100644 --- a/lib/Target/AArch64/Utils/AArch64BaseInfo.h +++ b/lib/Target/AArch64/Utils/AArch64BaseInfo.h @@ -1,9 +1,8 @@ //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -186,6 +185,49 @@ static inline unsigned getDRegFromBReg(unsigned Reg) { return Reg; } +static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) { + switch (Opcode) { + case AArch64::LDADDAB: case AArch64::LDADDAH: + case AArch64::LDADDAW: case AArch64::LDADDAX: + case AArch64::LDADDALB: case AArch64::LDADDALH: + case AArch64::LDADDALW: case AArch64::LDADDALX: + case AArch64::LDCLRAB: case AArch64::LDCLRAH: + case AArch64::LDCLRAW: case AArch64::LDCLRAX: + case AArch64::LDCLRALB: case AArch64::LDCLRALH: + case AArch64::LDCLRALW: case AArch64::LDCLRALX: + case AArch64::LDEORAB: case AArch64::LDEORAH: + case AArch64::LDEORAW: case AArch64::LDEORAX: + case AArch64::LDEORALB: case AArch64::LDEORALH: + case AArch64::LDEORALW: case AArch64::LDEORALX: + case AArch64::LDSETAB: case AArch64::LDSETAH: + case AArch64::LDSETAW: case AArch64::LDSETAX: + case AArch64::LDSETALB: case AArch64::LDSETALH: + case AArch64::LDSETALW: case AArch64::LDSETALX: + case AArch64::LDSMAXAB: case AArch64::LDSMAXAH: + case AArch64::LDSMAXAW: case AArch64::LDSMAXAX: + case AArch64::LDSMAXALB: case AArch64::LDSMAXALH: + case AArch64::LDSMAXALW: case AArch64::LDSMAXALX: + case AArch64::LDSMINAB: case AArch64::LDSMINAH: + case AArch64::LDSMINAW: case AArch64::LDSMINAX: + case AArch64::LDSMINALB: case AArch64::LDSMINALH: + case AArch64::LDSMINALW: case AArch64::LDSMINALX: + case AArch64::LDUMAXAB: case AArch64::LDUMAXAH: + case AArch64::LDUMAXAW: case AArch64::LDUMAXAX: + case AArch64::LDUMAXALB: case AArch64::LDUMAXALH: + case AArch64::LDUMAXALW: case AArch64::LDUMAXALX: + case AArch64::LDUMINAB: case AArch64::LDUMINAH: + case AArch64::LDUMINAW: case AArch64::LDUMINAX: + case AArch64::LDUMINALB: case AArch64::LDUMINALH: + case AArch64::LDUMINALW: case AArch64::LDUMINALX: + case AArch64::SWPAB: case AArch64::SWPAH: + case AArch64::SWPAW: case AArch64::SWPAX: + case AArch64::SWPALB: case AArch64::SWPALH: + case AArch64::SWPALW: case AArch64::SWPALX: + return true; + } + return false; +} + namespace AArch64CC { // The CondCodes constants map directly to the 4-bit encoding of the condition |