diff options
Diffstat (limited to 'lib/Target/ARM/MCTargetDesc')
17 files changed, 344 insertions, 451 deletions
diff --git a/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h b/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h index 3959eab966a8..f472b2154314 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h +++ b/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h @@ -38,11 +38,9 @@ namespace ARM_AM { add }; - static inline const char *getAddrOpcStr(AddrOpc Op) { - return Op == sub ? "-" : ""; - } + inline const char *getAddrOpcStr(AddrOpc Op) { return Op == sub ? "-" : ""; } - static inline const char *getShiftOpcStr(ShiftOpc Op) { + inline const char *getShiftOpcStr(ShiftOpc Op) { switch (Op) { default: llvm_unreachable("Unknown shift opc!"); case ARM_AM::asr: return "asr"; @@ -53,7 +51,7 @@ namespace ARM_AM { } } - static inline unsigned getShiftOpcEncoding(ShiftOpc Op) { + inline unsigned getShiftOpcEncoding(ShiftOpc Op) { switch (Op) { default: llvm_unreachable("Unknown shift opc!"); case ARM_AM::asr: return 2; @@ -71,7 +69,7 @@ namespace ARM_AM { db }; - static inline const char *getAMSubModeStr(AMSubMode Mode) { + inline const char *getAMSubModeStr(AMSubMode Mode) { switch (Mode) { default: llvm_unreachable("Unknown addressing sub-mode!"); case ARM_AM::ia: return "ia"; @@ -83,14 +81,14 @@ namespace ARM_AM { /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits. /// - static inline unsigned rotr32(unsigned Val, unsigned Amt) { + inline unsigned rotr32(unsigned Val, unsigned Amt) { assert(Amt < 32 && "Invalid rotate amount"); return (Val >> Amt) | (Val << ((32-Amt)&31)); } /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits. /// - static inline unsigned rotl32(unsigned Val, unsigned Amt) { + inline unsigned rotl32(unsigned Val, unsigned Amt) { assert(Amt < 32 && "Invalid rotate amount"); return (Val << Amt) | (Val >> ((32-Amt)&31)); } @@ -109,32 +107,24 @@ namespace ARM_AM { // reg, the second is the shift amount (or reg0 if not present or imm). The // third operand encodes the shift opcode and the imm if a reg isn't present. // - static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { + inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { return ShOp | (Imm << 3); } - static inline unsigned getSORegOffset(unsigned Op) { - return Op >> 3; - } - static inline ShiftOpc getSORegShOp(unsigned Op) { - return (ShiftOpc)(Op & 7); - } + inline unsigned getSORegOffset(unsigned Op) { return Op >> 3; } + inline ShiftOpc getSORegShOp(unsigned Op) { return (ShiftOpc)(Op & 7); } /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return /// the 8-bit imm value. - static inline unsigned getSOImmValImm(unsigned Imm) { - return Imm & 0xFF; - } + inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF; } /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return /// the rotate amount. - static inline unsigned getSOImmValRot(unsigned Imm) { - return (Imm >> 8) * 2; - } + inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; } /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, /// computing the rotate amount to use. If this immediate value cannot be /// handled with a single shifter-op, determine a good rotate amount that will /// take a maximal chunk of bits out of the immediate. - static inline unsigned getSOImmValRotate(unsigned Imm) { + inline unsigned getSOImmValRotate(unsigned Imm) { // 8-bit (or less) immediates are trivially shifter_operands with a rotate // of zero. if ((Imm & ~255U) == 0) return 0; @@ -168,7 +158,7 @@ namespace ARM_AM { /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit /// into an shifter_operand immediate operand, return the 12-bit encoding for /// it. If not, return -1. - static inline int getSOImmVal(unsigned Arg) { + inline int getSOImmVal(unsigned Arg) { // 8-bit (or less) immediates are trivially shifter_operands with a rotate // of zero. if ((Arg & ~255U) == 0) return Arg; @@ -185,7 +175,7 @@ namespace ARM_AM { /// isSOImmTwoPartVal - Return true if the specified value can be obtained by /// or'ing together two SOImmVal's. - static inline bool isSOImmTwoPartVal(unsigned V) { + inline bool isSOImmTwoPartVal(unsigned V) { // If this can be handled with a single shifter_op, bail out. V = rotr32(~255U, getSOImmValRotate(V)) & V; if (V == 0) @@ -198,13 +188,13 @@ namespace ARM_AM { /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, /// return the first chunk of it. - static inline unsigned getSOImmTwoPartFirst(unsigned V) { + inline unsigned getSOImmTwoPartFirst(unsigned V) { return rotr32(255U, getSOImmValRotate(V)) & V; } /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, /// return the second chunk of it. - static inline unsigned getSOImmTwoPartSecond(unsigned V) { + inline unsigned getSOImmTwoPartSecond(unsigned V) { // Mask out the first hunk. V = rotr32(~255U, getSOImmValRotate(V)) & V; @@ -215,7 +205,7 @@ namespace ARM_AM { /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed /// by a left shift. Returns the shift amount to use. - static inline unsigned getThumbImmValShift(unsigned Imm) { + inline unsigned getThumbImmValShift(unsigned Imm) { // 8-bit (or less) immediates are trivially immediate operand with a shift // of zero. if ((Imm & ~255U) == 0) return 0; @@ -226,7 +216,7 @@ namespace ARM_AM { /// isThumbImmShiftedVal - Return true if the specified value can be obtained /// by left shifting a 8-bit immediate. - static inline bool isThumbImmShiftedVal(unsigned V) { + inline bool isThumbImmShiftedVal(unsigned V) { // If this can be handled with V = (~255U << getThumbImmValShift(V)) & V; return V == 0; @@ -234,7 +224,7 @@ namespace ARM_AM { /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed /// by a left shift. Returns the shift amount to use. - static inline unsigned getThumbImm16ValShift(unsigned Imm) { + inline unsigned getThumbImm16ValShift(unsigned Imm) { // 16-bit (or less) immediates are trivially immediate operand with a shift // of zero. if ((Imm & ~65535U) == 0) return 0; @@ -245,7 +235,7 @@ namespace ARM_AM { /// isThumbImm16ShiftedVal - Return true if the specified value can be /// obtained by left shifting a 16-bit immediate. - static inline bool isThumbImm16ShiftedVal(unsigned V) { + inline bool isThumbImm16ShiftedVal(unsigned V) { // If this can be handled with V = (~65535U << getThumbImm16ValShift(V)) & V; return V == 0; @@ -253,7 +243,7 @@ namespace ARM_AM { /// getThumbImmNonShiftedVal - If V is a value that satisfies /// isThumbImmShiftedVal, return the non-shiftd value. - static inline unsigned getThumbImmNonShiftedVal(unsigned V) { + inline unsigned getThumbImmNonShiftedVal(unsigned V) { return V >> getThumbImmValShift(V); } @@ -267,7 +257,7 @@ namespace ARM_AM { /// abcdefgh abcdefgh abcdefgh abcdefgh control = 3 /// Return -1 if none of the above apply. /// See ARM Reference Manual A6.3.2. - static inline int getT2SOImmValSplatVal(unsigned V) { + inline int getT2SOImmValSplatVal(unsigned V) { unsigned u, Vs, Imm; // control = 0 if ((V & 0xffffff00) == 0) @@ -295,7 +285,7 @@ namespace ARM_AM { /// specified value is a rotated 8-bit value. Return -1 if no rotation /// encoding is possible. /// See ARM Reference Manual A6.3.2. - static inline int getT2SOImmValRotateVal(unsigned V) { + inline int getT2SOImmValRotateVal(unsigned V) { unsigned RotAmt = countLeadingZeros(V); if (RotAmt >= 24) return -1; @@ -311,7 +301,7 @@ namespace ARM_AM { /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit /// encoding for it. If not, return -1. /// See ARM Reference Manual A6.3.2. - static inline int getT2SOImmVal(unsigned Arg) { + inline int getT2SOImmVal(unsigned Arg) { // If 'Arg' is an 8-bit splat, then get the encoded value. int Splat = getT2SOImmValSplatVal(Arg); if (Splat != -1) @@ -325,14 +315,14 @@ namespace ARM_AM { return -1; } - static inline unsigned getT2SOImmValRotate(unsigned V) { + inline unsigned getT2SOImmValRotate(unsigned V) { if ((V & ~255U) == 0) return 0; // Use CTZ to compute the rotate amount. unsigned RotAmt = countTrailingZeros(V); return (32 - RotAmt) & 31; } - static inline bool isT2SOImmTwoPartVal (unsigned Imm) { + inline bool isT2SOImmTwoPartVal(unsigned Imm) { unsigned V = Imm; // Passing values can be any combination of splat values and shifter // values. If this can be handled with a single shifter or splat, bail @@ -359,7 +349,7 @@ namespace ARM_AM { return false; } - static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) { + inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) { assert (isT2SOImmTwoPartVal(Imm) && "Immedate cannot be encoded as two part immediate!"); // Try a shifter operand as one part @@ -376,7 +366,7 @@ namespace ARM_AM { return Imm & 0x00ff00ffU; } - static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) { + inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) { // Mask out the first hunk Imm ^= getT2SOImmTwoPartFirst(Imm); // Return what's left @@ -404,25 +394,22 @@ namespace ARM_AM { // and code rewriting), this operand will have the form: FI#, reg0, <offs> // with no shift amount for the frame offset. // - static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, - unsigned IdxMode = 0) { + inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, + unsigned IdxMode = 0) { assert(Imm12 < (1 << 12) && "Imm too large!"); bool isSub = Opc == sub; return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ; } - static inline unsigned getAM2Offset(unsigned AM2Opc) { + inline unsigned getAM2Offset(unsigned AM2Opc) { return AM2Opc & ((1 << 12)-1); } - static inline AddrOpc getAM2Op(unsigned AM2Opc) { + inline AddrOpc getAM2Op(unsigned AM2Opc) { return ((AM2Opc >> 12) & 1) ? sub : add; } - static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { + inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { return (ShiftOpc)((AM2Opc >> 13) & 7); } - static inline unsigned getAM2IdxMode(unsigned AM2Opc) { - return (AM2Opc >> 16); - } - + inline unsigned getAM2IdxMode(unsigned AM2Opc) { return (AM2Opc >> 16); } //===--------------------------------------------------------------------===// // Addressing Mode #3 @@ -439,20 +426,16 @@ namespace ARM_AM { // index mode. /// getAM3Opc - This function encodes the addrmode3 opc field. - static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset, - unsigned IdxMode = 0) { + inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset, + unsigned IdxMode = 0) { bool isSub = Opc == sub; return ((int)isSub << 8) | Offset | (IdxMode << 9); } - static inline unsigned char getAM3Offset(unsigned AM3Opc) { - return AM3Opc & 0xFF; - } - static inline AddrOpc getAM3Op(unsigned AM3Opc) { + inline unsigned char getAM3Offset(unsigned AM3Opc) { return AM3Opc & 0xFF; } + inline AddrOpc getAM3Op(unsigned AM3Opc) { return ((AM3Opc >> 8) & 1) ? sub : add; } - static inline unsigned getAM3IdxMode(unsigned AM3Opc) { - return (AM3Opc >> 9); - } + inline unsigned getAM3IdxMode(unsigned AM3Opc) { return (AM3Opc >> 9); } //===--------------------------------------------------------------------===// // Addressing Mode #4 @@ -469,13 +452,11 @@ namespace ARM_AM { // DB - Decrement before // For VFP instructions, only the IA and DB modes are valid. - static inline AMSubMode getAM4SubMode(unsigned Mode) { + inline AMSubMode getAM4SubMode(unsigned Mode) { return (AMSubMode)(Mode & 0x7); } - static inline unsigned getAM4ModeImm(AMSubMode SubMode) { - return (int)SubMode; - } + inline unsigned getAM4ModeImm(AMSubMode SubMode) { return (int)SubMode; } //===--------------------------------------------------------------------===// // Addressing Mode #5 @@ -489,14 +470,12 @@ namespace ARM_AM { // operation (add or subtract) in bit 8 and the immediate in bits 0-7. /// getAM5Opc - This function encodes the addrmode5 opc field. - static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) { + inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) { bool isSub = Opc == sub; return ((int)isSub << 8) | Offset; } - static inline unsigned char getAM5Offset(unsigned AM5Opc) { - return AM5Opc & 0xFF; - } - static inline AddrOpc getAM5Op(unsigned AM5Opc) { + inline unsigned char getAM5Offset(unsigned AM5Opc) { return AM5Opc & 0xFF; } + inline AddrOpc getAM5Op(unsigned AM5Opc) { return ((AM5Opc >> 8) & 1) ? sub : add; } @@ -512,14 +491,14 @@ namespace ARM_AM { // operation (add or subtract) in bit 8 and the immediate in bits 0-7. /// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field. - static inline unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset) { + inline unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset) { bool isSub = Opc == sub; return ((int)isSub << 8) | Offset; } - static inline unsigned char getAM5FP16Offset(unsigned AM5Opc) { + inline unsigned char getAM5FP16Offset(unsigned AM5Opc) { return AM5Opc & 0xFF; } - static inline AddrOpc getAM5FP16Op(unsigned AM5Opc) { + inline AddrOpc getAM5FP16Op(unsigned AM5Opc) { return ((AM5Opc >> 8) & 1) ? sub : add; } @@ -548,20 +527,18 @@ namespace ARM_AM { // the "Cmode" field of the instruction. The interfaces below treat the // Op and Cmode values as a single 5-bit value. - static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) { + inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) { return (OpCmode << 8) | Val; } - static inline unsigned getNEONModImmOpCmode(unsigned ModImm) { + inline unsigned getNEONModImmOpCmode(unsigned ModImm) { return (ModImm >> 8) & 0x1f; } - static inline unsigned getNEONModImmVal(unsigned ModImm) { - return ModImm & 0xff; - } + inline unsigned getNEONModImmVal(unsigned ModImm) { return ModImm & 0xff; } /// decodeNEONModImm - Decode a NEON modified immediate value into the /// element value and the element size in bits. (If the element size is /// smaller than the vector, it is splatted into all the elements.) - static inline uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits) { + inline uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits) { unsigned OpCmode = getNEONModImmOpCmode(ModImm); unsigned Imm8 = getNEONModImmVal(ModImm); uint64_t Val = 0; @@ -599,7 +576,7 @@ namespace ARM_AM { } // Generic validation for single-byte immediate (0X00, 00X0, etc). - static inline bool isNEONBytesplat(unsigned Value, unsigned Size) { + inline bool isNEONBytesplat(unsigned Value, unsigned Size) { assert(Size >= 1 && Size <= 4 && "Invalid size"); unsigned count = 0; for (unsigned i = 0; i < Size; ++i) { @@ -610,7 +587,7 @@ namespace ARM_AM { } /// Checks if Value is a correct immediate for instructions like VBIC/VORR. - static inline bool isNEONi16splat(unsigned Value) { + inline bool isNEONi16splat(unsigned Value) { if (Value > 0xffff) return false; // i16 value with set bits only in one byte X0 or 0X. @@ -618,7 +595,7 @@ namespace ARM_AM { } // Encode NEON 16 bits Splat immediate for instructions like VBIC/VORR - static inline unsigned encodeNEONi16splat(unsigned Value) { + inline unsigned encodeNEONi16splat(unsigned Value) { assert(isNEONi16splat(Value) && "Invalid NEON splat value"); if (Value >= 0x100) Value = (Value >> 8) | 0xa00; @@ -628,13 +605,13 @@ namespace ARM_AM { } /// Checks if Value is a correct immediate for instructions like VBIC/VORR. - static inline bool isNEONi32splat(unsigned Value) { + inline bool isNEONi32splat(unsigned Value) { // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. return Value == 0 || isNEONBytesplat(Value, 4); } /// Encode NEON 32 bits Splat immediate for instructions like VBIC/VORR. - static inline unsigned encodeNEONi32splat(unsigned Value) { + inline unsigned encodeNEONi32splat(unsigned Value) { assert(isNEONi32splat(Value) && "Invalid NEON splat value"); if (Value >= 0x100 && Value <= 0xff00) Value = (Value >> 8) | 0x200; @@ -648,7 +625,7 @@ namespace ARM_AM { //===--------------------------------------------------------------------===// // Floating-point Immediates // - static inline float getFPImmFloat(unsigned Imm) { + inline float getFPImmFloat(unsigned Imm) { // We expect an 8-bit binary encoding of a floating-point number here. union { uint32_t I; @@ -676,7 +653,7 @@ namespace ARM_AM { /// getFP16Imm - Return an 8-bit floating-point version of the 16-bit /// floating-point value. If the value cannot be represented as an 8-bit /// floating-point value, then return -1. - static inline int getFP16Imm(const APInt &Imm) { + inline int getFP16Imm(const APInt &Imm) { uint32_t Sign = Imm.lshr(15).getZExtValue() & 1; int32_t Exp = (Imm.lshr(10).getSExtValue() & 0x1f) - 15; // -14 to 15 int64_t Mantissa = Imm.getZExtValue() & 0x3ff; // 10 bits @@ -695,14 +672,14 @@ namespace ARM_AM { return ((int)Sign << 7) | (Exp << 4) | Mantissa; } - static inline int getFP16Imm(const APFloat &FPImm) { + inline int getFP16Imm(const APFloat &FPImm) { return getFP16Imm(FPImm.bitcastToAPInt()); } /// getFP32Imm - Return an 8-bit floating-point version of the 32-bit /// floating-point value. If the value cannot be represented as an 8-bit /// floating-point value, then return -1. - static inline int getFP32Imm(const APInt &Imm) { + inline int getFP32Imm(const APInt &Imm) { uint32_t Sign = Imm.lshr(31).getZExtValue() & 1; int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits @@ -723,14 +700,14 @@ namespace ARM_AM { return ((int)Sign << 7) | (Exp << 4) | Mantissa; } - static inline int getFP32Imm(const APFloat &FPImm) { + inline int getFP32Imm(const APFloat &FPImm) { return getFP32Imm(FPImm.bitcastToAPInt()); } /// getFP64Imm - Return an 8-bit floating-point version of the 64-bit /// floating-point value. If the value cannot be represented as an 8-bit /// floating-point value, then return -1. - static inline int getFP64Imm(const APInt &Imm) { + inline int getFP64Imm(const APInt &Imm) { uint64_t Sign = Imm.lshr(63).getZExtValue() & 1; int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL; @@ -751,7 +728,7 @@ namespace ARM_AM { return ((int)Sign << 7) | (Exp << 4) | Mantissa; } - static inline int getFP64Imm(const APFloat &FPImm) { + inline int getFP64Imm(const APFloat &FPImm) { return getFP64Imm(FPImm.bitcastToAPInt()); } diff --git a/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp index a77df7a2598f..1cb9dd44f789 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -12,7 +12,6 @@ #include "MCTargetDesc/ARMAsmBackendDarwin.h" #include "MCTargetDesc/ARMAsmBackendELF.h" #include "MCTargetDesc/ARMAsmBackendWinCOFF.h" -#include "MCTargetDesc/ARMBaseInfo.h" #include "MCTargetDesc/ARMFixupKinds.h" #include "MCTargetDesc/ARMMCTargetDesc.h" #include "llvm/ADT/StringSwitch.h" @@ -25,7 +24,6 @@ #include "llvm/MC/MCELFObjectWriter.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCFixupKindInfo.h" -#include "llvm/MC/MCMachObjectWriter.h" #include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSectionELF.h" @@ -1127,30 +1125,30 @@ uint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding( } static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) { - unsigned AK = ARM::parseArch(Arch); + ARM::ArchKind AK = ARM::parseArch(Arch); switch (AK) { default: return MachO::CPU_SUBTYPE_ARM_V7; - case ARM::AK_ARMV4T: + case ARM::ArchKind::ARMV4T: return MachO::CPU_SUBTYPE_ARM_V4T; - case ARM::AK_ARMV5T: - case ARM::AK_ARMV5TE: - case ARM::AK_ARMV5TEJ: + case ARM::ArchKind::ARMV5T: + case ARM::ArchKind::ARMV5TE: + case ARM::ArchKind::ARMV5TEJ: return MachO::CPU_SUBTYPE_ARM_V5; - case ARM::AK_ARMV6: - case ARM::AK_ARMV6K: + case ARM::ArchKind::ARMV6: + case ARM::ArchKind::ARMV6K: return MachO::CPU_SUBTYPE_ARM_V6; - case ARM::AK_ARMV7A: + case ARM::ArchKind::ARMV7A: return MachO::CPU_SUBTYPE_ARM_V7; - case ARM::AK_ARMV7S: + case ARM::ArchKind::ARMV7S: return MachO::CPU_SUBTYPE_ARM_V7S; - case ARM::AK_ARMV7K: + case ARM::ArchKind::ARMV7K: return MachO::CPU_SUBTYPE_ARM_V7K; - case ARM::AK_ARMV6M: + case ARM::ArchKind::ARMV6M: return MachO::CPU_SUBTYPE_ARM_V6M; - case ARM::AK_ARMV7M: + case ARM::ArchKind::ARMV7M: return MachO::CPU_SUBTYPE_ARM_V7M; - case ARM::AK_ARMV7EM: + case ARM::ArchKind::ARMV7EM: return MachO::CPU_SUBTYPE_ARM_V7EM; } } diff --git a/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h b/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h index bd729fabedf5..f05e3a6f1160 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h +++ b/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h @@ -12,6 +12,7 @@ #include "ARMAsmBackend.h" #include "llvm/BinaryFormat/MachO.h" +#include "llvm/MC/MCObjectWriter.h" namespace llvm { class ARMAsmBackendDarwin : public ARMAsmBackend { @@ -23,7 +24,8 @@ public: : ARMAsmBackend(T, TT, /* IsLittleEndian */ true), MRI(MRI), Subtype(st) { } - MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { + std::unique_ptr<MCObjectWriter> + createObjectWriter(raw_pwrite_stream &OS) const override { return createARMMachObjectWriter(OS, /*Is64Bit=*/false, MachO::CPU_TYPE_ARM, Subtype); } diff --git a/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h b/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h index 748f915be17b..d0f5419a1b0f 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h +++ b/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h @@ -12,6 +12,8 @@ #include "ARMAsmBackend.h" #include "MCTargetDesc/ARMMCTargetDesc.h" +#include "llvm/MC/MCObjectWriter.h" + using namespace llvm; namespace { @@ -22,7 +24,8 @@ public: bool IsLittle) : ARMAsmBackend(T, TT, IsLittle), OSABI(OSABI) {} - MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { + std::unique_ptr<MCObjectWriter> + createObjectWriter(raw_pwrite_stream &OS) const override { return createARMELFObjectWriter(OS, OSABI, isLittle()); } }; diff --git a/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h b/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h index 2a375be49a83..53b9c29446a3 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h +++ b/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h @@ -11,6 +11,7 @@ #define LLVM_LIB_TARGET_ARM_ARMASMBACKENDWINCOFF_H #include "ARMAsmBackend.h" +#include "llvm/MC/MCObjectWriter.h" using namespace llvm; namespace { @@ -18,7 +19,8 @@ class ARMAsmBackendWinCOFF : public ARMAsmBackend { public: ARMAsmBackendWinCOFF(const Target &T, const Triple &TheTriple) : ARMAsmBackend(T, TheTriple, true) {} - MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { + std::unique_ptr<MCObjectWriter> + createObjectWriter(raw_pwrite_stream &OS) const override { return createARMWinCOFFObjectWriter(OS, /*Is64Bit=*/false); } }; diff --git a/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h b/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h index 92e553f21f14..c4480e3da505 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h +++ b/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h @@ -19,73 +19,10 @@ #include "ARMMCTargetDesc.h" #include "llvm/Support/ErrorHandling.h" +#include "Utils/ARMBaseInfo.h" namespace llvm { -// Enums corresponding to ARM condition codes -namespace ARMCC { - // The CondCodes constants map directly to the 4-bit encoding of the - // condition field for predicated instructions. - enum CondCodes { // Meaning (integer) Meaning (floating-point) - EQ, // Equal Equal - NE, // Not equal Not equal, or unordered - HS, // Carry set >, ==, or unordered - LO, // Carry clear Less than - MI, // Minus, negative Less than - PL, // Plus, positive or zero >, ==, or unordered - VS, // Overflow Unordered - VC, // No overflow Not unordered - HI, // Unsigned higher Greater than, or unordered - LS, // Unsigned lower or same Less than or equal - GE, // Greater than or equal Greater than or equal - LT, // Less than Less than, or unordered - GT, // Greater than Greater than - LE, // Less than or equal <, ==, or unordered - AL // Always (unconditional) Always (unconditional) - }; - - inline static CondCodes getOppositeCondition(CondCodes CC) { - switch (CC) { - default: llvm_unreachable("Unknown condition code"); - case EQ: return NE; - case NE: return EQ; - case HS: return LO; - case LO: return HS; - case MI: return PL; - case PL: return MI; - case VS: return VC; - case VC: return VS; - case HI: return LS; - case LS: return HI; - case GE: return LT; - case LT: return GE; - case GT: return LE; - case LE: return GT; - } - } -} // namespace ARMCC - -inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) { - switch (CC) { - case ARMCC::EQ: return "eq"; - case ARMCC::NE: return "ne"; - case ARMCC::HS: return "hs"; - case ARMCC::LO: return "lo"; - case ARMCC::MI: return "mi"; - case ARMCC::PL: return "pl"; - case ARMCC::VS: return "vs"; - case ARMCC::VC: return "vc"; - case ARMCC::HI: return "hi"; - case ARMCC::LS: return "ls"; - case ARMCC::GE: return "ge"; - case ARMCC::LT: return "lt"; - case ARMCC::GT: return "gt"; - case ARMCC::LE: return "le"; - case ARMCC::AL: return "al"; - } - llvm_unreachable("Unknown condition code"); -} - namespace ARM_PROC { enum IMod { IE = 2, @@ -291,7 +228,10 @@ namespace ARMII { /// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects /// just that part of the flag set. - MO_OPTION_MASK = 0x0f, + MO_OPTION_MASK = 0x3, + + /// MO_GOT - On a symbol operand, this represents a GOT relative relocation. + MO_GOT = 0x8, /// MO_SBREL - On a symbol operand, this represents a static base relative /// relocation. Used in movw and movt instructions. @@ -406,6 +346,7 @@ namespace ARMII { NVExtFrm = 39 << FormShift, NVMulSLFrm = 40 << FormShift, NVTBLFrm = 41 << FormShift, + N3RegCplxFrm = 43 << FormShift, //===------------------------------------------------------------------===// // Misc flags. diff --git a/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp b/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp index 59f31be69d58..3cd52fe1e7eb 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp @@ -14,6 +14,7 @@ #include "llvm/MC/MCELFObjectWriter.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCFixup.h" +#include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCValue.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -78,7 +79,6 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, MCContext &Ctx) const { MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant(); - unsigned Type = 0; if (IsPCRel) { switch ((unsigned)Fixup.getKind()) { default: @@ -86,220 +86,159 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, return ELF::R_ARM_NONE; case FK_Data_4: switch (Modifier) { - default: llvm_unreachable("Unsupported Modifier"); + default: + llvm_unreachable("Unsupported Modifier"); case MCSymbolRefExpr::VK_None: - Type = ELF::R_ARM_REL32; - break; - case MCSymbolRefExpr::VK_TLSGD: - llvm_unreachable("unimplemented"); + return ELF::R_ARM_REL32; case MCSymbolRefExpr::VK_GOTTPOFF: - Type = ELF::R_ARM_TLS_IE32; - break; + return ELF::R_ARM_TLS_IE32; case MCSymbolRefExpr::VK_ARM_GOT_PREL: - Type = ELF::R_ARM_GOT_PREL; - break; + return ELF::R_ARM_GOT_PREL; case MCSymbolRefExpr::VK_ARM_PREL31: - Type = ELF::R_ARM_PREL31; - break; + return ELF::R_ARM_PREL31; } - break; case ARM::fixup_arm_blx: case ARM::fixup_arm_uncondbl: switch (Modifier) { case MCSymbolRefExpr::VK_PLT: - Type = ELF::R_ARM_CALL; - break; + return ELF::R_ARM_CALL; case MCSymbolRefExpr::VK_TLSCALL: - Type = ELF::R_ARM_TLS_CALL; - break; + return ELF::R_ARM_TLS_CALL; default: - Type = ELF::R_ARM_CALL; - break; + return ELF::R_ARM_CALL; } - break; case ARM::fixup_arm_condbl: case ARM::fixup_arm_condbranch: case ARM::fixup_arm_uncondbranch: - Type = ELF::R_ARM_JUMP24; - break; + return ELF::R_ARM_JUMP24; case ARM::fixup_t2_condbranch: - Type = ELF::R_ARM_THM_JUMP19; - break; + return ELF::R_ARM_THM_JUMP19; case ARM::fixup_t2_uncondbranch: - Type = ELF::R_ARM_THM_JUMP24; - break; + return ELF::R_ARM_THM_JUMP24; case ARM::fixup_arm_movt_hi16: - Type = ELF::R_ARM_MOVT_PREL; - break; + return ELF::R_ARM_MOVT_PREL; case ARM::fixup_arm_movw_lo16: - Type = ELF::R_ARM_MOVW_PREL_NC; - break; + return ELF::R_ARM_MOVW_PREL_NC; case ARM::fixup_t2_movt_hi16: - Type = ELF::R_ARM_THM_MOVT_PREL; - break; + return ELF::R_ARM_THM_MOVT_PREL; case ARM::fixup_t2_movw_lo16: - Type = ELF::R_ARM_THM_MOVW_PREL_NC; - break; + return ELF::R_ARM_THM_MOVW_PREL_NC; case ARM::fixup_arm_thumb_br: - Type = ELF::R_ARM_THM_JUMP11; - break; + return ELF::R_ARM_THM_JUMP11; case ARM::fixup_arm_thumb_bcc: - Type = ELF::R_ARM_THM_JUMP8; - break; + return ELF::R_ARM_THM_JUMP8; case ARM::fixup_arm_thumb_bl: case ARM::fixup_arm_thumb_blx: switch (Modifier) { case MCSymbolRefExpr::VK_TLSCALL: - Type = ELF::R_ARM_THM_TLS_CALL; - break; + return ELF::R_ARM_THM_TLS_CALL; default: - Type = ELF::R_ARM_THM_CALL; - break; + return ELF::R_ARM_THM_CALL; } - break; } - } else { - switch ((unsigned)Fixup.getKind()) { + } + switch ((unsigned)Fixup.getKind()) { + default: + Ctx.reportFatalError(Fixup.getLoc(), "unsupported relocation on symbol"); + return ELF::R_ARM_NONE; + case FK_Data_1: + switch (Modifier) { default: - Ctx.reportFatalError(Fixup.getLoc(), "unsupported relocation on symbol"); + llvm_unreachable("unsupported Modifier"); + case MCSymbolRefExpr::VK_None: + return ELF::R_ARM_ABS8; + } + case FK_Data_2: + switch (Modifier) { + default: + llvm_unreachable("unsupported modifier"); + case MCSymbolRefExpr::VK_None: + return ELF::R_ARM_ABS16; + } + case FK_Data_4: + switch (Modifier) { + default: + llvm_unreachable("Unsupported Modifier"); + case MCSymbolRefExpr::VK_ARM_NONE: return ELF::R_ARM_NONE; - case FK_Data_1: - switch (Modifier) { - default: llvm_unreachable("unsupported Modifier"); - case MCSymbolRefExpr::VK_None: - Type = ELF::R_ARM_ABS8; - break; - } - break; - case FK_Data_2: - switch (Modifier) { - default: llvm_unreachable("unsupported modifier"); - case MCSymbolRefExpr::VK_None: - Type = ELF::R_ARM_ABS16; - break; - } - break; - case FK_Data_4: - switch (Modifier) { - default: llvm_unreachable("Unsupported Modifier"); - case MCSymbolRefExpr::VK_ARM_NONE: - Type = ELF::R_ARM_NONE; - break; - case MCSymbolRefExpr::VK_GOT: - Type = ELF::R_ARM_GOT_BREL; - break; - case MCSymbolRefExpr::VK_TLSGD: - Type = ELF::R_ARM_TLS_GD32; - break; - case MCSymbolRefExpr::VK_TPOFF: - Type = ELF::R_ARM_TLS_LE32; - break; - case MCSymbolRefExpr::VK_GOTTPOFF: - Type = ELF::R_ARM_TLS_IE32; - break; - case MCSymbolRefExpr::VK_None: - Type = ELF::R_ARM_ABS32; - break; - case MCSymbolRefExpr::VK_GOTOFF: - Type = ELF::R_ARM_GOTOFF32; - break; - case MCSymbolRefExpr::VK_ARM_GOT_PREL: - Type = ELF::R_ARM_GOT_PREL; - break; - case MCSymbolRefExpr::VK_ARM_TARGET1: - Type = ELF::R_ARM_TARGET1; - break; - case MCSymbolRefExpr::VK_ARM_TARGET2: - Type = ELF::R_ARM_TARGET2; - break; - case MCSymbolRefExpr::VK_ARM_PREL31: - Type = ELF::R_ARM_PREL31; - break; - case MCSymbolRefExpr::VK_ARM_SBREL: - Type = ELF::R_ARM_SBREL32; - break; - case MCSymbolRefExpr::VK_ARM_TLSLDO: - Type = ELF::R_ARM_TLS_LDO32; - break; - case MCSymbolRefExpr::VK_TLSCALL: - Type = ELF::R_ARM_TLS_CALL; - break; - case MCSymbolRefExpr::VK_TLSDESC: - Type = ELF::R_ARM_TLS_GOTDESC; - break; - case MCSymbolRefExpr::VK_TLSLDM: - Type = ELF::R_ARM_TLS_LDM32; - break; - case MCSymbolRefExpr::VK_ARM_TLSDESCSEQ: - Type = ELF::R_ARM_TLS_DESCSEQ; - break; - } - break; - case ARM::fixup_arm_ldst_pcrel_12: - case ARM::fixup_arm_pcrel_10: - case ARM::fixup_arm_adr_pcrel_12: - case ARM::fixup_arm_thumb_bl: - case ARM::fixup_arm_thumb_cb: - case ARM::fixup_arm_thumb_cp: - case ARM::fixup_arm_thumb_br: - llvm_unreachable("Unimplemented"); - case ARM::fixup_arm_condbranch: - case ARM::fixup_arm_uncondbranch: - Type = ELF::R_ARM_JUMP24; - break; - case ARM::fixup_arm_movt_hi16: - switch (Modifier) { - default: llvm_unreachable("Unsupported Modifier"); - case MCSymbolRefExpr::VK_None: - Type = ELF::R_ARM_MOVT_ABS; - break; - case MCSymbolRefExpr::VK_ARM_SBREL: - Type = ELF:: R_ARM_MOVT_BREL; - break; - } - break; - case ARM::fixup_arm_movw_lo16: - switch (Modifier) { - default: llvm_unreachable("Unsupported Modifier"); - case MCSymbolRefExpr::VK_None: - Type = ELF::R_ARM_MOVW_ABS_NC; - break; - case MCSymbolRefExpr::VK_ARM_SBREL: - Type = ELF:: R_ARM_MOVW_BREL_NC; - break; - } - break; - case ARM::fixup_t2_movt_hi16: - switch (Modifier) { - default: llvm_unreachable("Unsupported Modifier"); - case MCSymbolRefExpr::VK_None: - Type = ELF::R_ARM_THM_MOVT_ABS; - break; - case MCSymbolRefExpr::VK_ARM_SBREL: - Type = ELF:: R_ARM_THM_MOVT_BREL; - break; - } - break; - case ARM::fixup_t2_movw_lo16: - switch (Modifier) { - default: llvm_unreachable("Unsupported Modifier"); - case MCSymbolRefExpr::VK_None: - Type = ELF::R_ARM_THM_MOVW_ABS_NC; - break; - case MCSymbolRefExpr::VK_ARM_SBREL: - Type = ELF:: R_ARM_THM_MOVW_BREL_NC; - break; - } - break; + case MCSymbolRefExpr::VK_GOT: + return ELF::R_ARM_GOT_BREL; + case MCSymbolRefExpr::VK_TLSGD: + return ELF::R_ARM_TLS_GD32; + case MCSymbolRefExpr::VK_TPOFF: + return ELF::R_ARM_TLS_LE32; + case MCSymbolRefExpr::VK_GOTTPOFF: + return ELF::R_ARM_TLS_IE32; + case MCSymbolRefExpr::VK_None: + return ELF::R_ARM_ABS32; + case MCSymbolRefExpr::VK_GOTOFF: + return ELF::R_ARM_GOTOFF32; + case MCSymbolRefExpr::VK_ARM_GOT_PREL: + return ELF::R_ARM_GOT_PREL; + case MCSymbolRefExpr::VK_ARM_TARGET1: + return ELF::R_ARM_TARGET1; + case MCSymbolRefExpr::VK_ARM_TARGET2: + return ELF::R_ARM_TARGET2; + case MCSymbolRefExpr::VK_ARM_PREL31: + return ELF::R_ARM_PREL31; + case MCSymbolRefExpr::VK_ARM_SBREL: + return ELF::R_ARM_SBREL32; + case MCSymbolRefExpr::VK_ARM_TLSLDO: + return ELF::R_ARM_TLS_LDO32; + case MCSymbolRefExpr::VK_TLSCALL: + return ELF::R_ARM_TLS_CALL; + case MCSymbolRefExpr::VK_TLSDESC: + return ELF::R_ARM_TLS_GOTDESC; + case MCSymbolRefExpr::VK_TLSLDM: + return ELF::R_ARM_TLS_LDM32; + case MCSymbolRefExpr::VK_ARM_TLSDESCSEQ: + return ELF::R_ARM_TLS_DESCSEQ; + } + case ARM::fixup_arm_condbranch: + case ARM::fixup_arm_uncondbranch: + return ELF::R_ARM_JUMP24; + case ARM::fixup_arm_movt_hi16: + switch (Modifier) { + default: + llvm_unreachable("Unsupported Modifier"); + case MCSymbolRefExpr::VK_None: + return ELF::R_ARM_MOVT_ABS; + case MCSymbolRefExpr::VK_ARM_SBREL: + return ELF::R_ARM_MOVT_BREL; + } + case ARM::fixup_arm_movw_lo16: + switch (Modifier) { + default: + llvm_unreachable("Unsupported Modifier"); + case MCSymbolRefExpr::VK_None: + return ELF::R_ARM_MOVW_ABS_NC; + case MCSymbolRefExpr::VK_ARM_SBREL: + return ELF::R_ARM_MOVW_BREL_NC; + } + case ARM::fixup_t2_movt_hi16: + switch (Modifier) { + default: + llvm_unreachable("Unsupported Modifier"); + case MCSymbolRefExpr::VK_None: + return ELF::R_ARM_THM_MOVT_ABS; + case MCSymbolRefExpr::VK_ARM_SBREL: + return ELF::R_ARM_THM_MOVT_BREL; + } + case ARM::fixup_t2_movw_lo16: + switch (Modifier) { + default: + llvm_unreachable("Unsupported Modifier"); + case MCSymbolRefExpr::VK_None: + return ELF::R_ARM_THM_MOVW_ABS_NC; + case MCSymbolRefExpr::VK_ARM_SBREL: + return ELF::R_ARM_THM_MOVW_BREL_NC; } } - - return Type; } -MCObjectWriter *llvm::createARMELFObjectWriter(raw_pwrite_stream &OS, - uint8_t OSABI, - bool IsLittleEndian) { - MCELFObjectTargetWriter *MOTW = new ARMELFObjectWriter(OSABI); - return createELFObjectWriter(MOTW, OS, IsLittleEndian); +std::unique_ptr<MCObjectWriter> +llvm::createARMELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, + bool IsLittleEndian) { + return createELFObjectWriter(llvm::make_unique<ARMELFObjectWriter>(OSABI), OS, + IsLittleEndian); } diff --git a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp index 93f4006cee87..d465da1a7bb1 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -92,9 +92,9 @@ class ARMTargetAsmStreamer : public ARMTargetStreamer { void emitTextAttribute(unsigned Attribute, StringRef String) override; void emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue) override; - void emitArch(unsigned Arch) override; + void emitArch(ARM::ArchKind Arch) override; void emitArchExtension(unsigned ArchExt) override; - void emitObjectArch(unsigned Arch) override; + void emitObjectArch(ARM::ArchKind Arch) override; void emitFPU(unsigned FPU) override; void emitInst(uint32_t Inst, char Suffix = '\0') override; void finishAttributeSection() override; @@ -218,7 +218,7 @@ void ARMTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute, OS << "\n"; } -void ARMTargetAsmStreamer::emitArch(unsigned Arch) { +void ARMTargetAsmStreamer::emitArch(ARM::ArchKind Arch) { OS << "\t.arch\t" << ARM::getArchName(Arch) << "\n"; } @@ -226,7 +226,7 @@ void ARMTargetAsmStreamer::emitArchExtension(unsigned ArchExt) { OS << "\t.arch_extension\t" << ARM::getArchExtName(ArchExt) << "\n"; } -void ARMTargetAsmStreamer::emitObjectArch(unsigned Arch) { +void ARMTargetAsmStreamer::emitObjectArch(ARM::ArchKind Arch) { OS << "\t.object_arch\t" << ARM::getArchName(Arch) << '\n'; } @@ -303,8 +303,8 @@ private: StringRef CurrentVendor; unsigned FPU = ARM::FK_INVALID; - unsigned Arch = ARM::AK_INVALID; - unsigned EmittedArch = ARM::AK_INVALID; + ARM::ArchKind Arch = ARM::ArchKind::INVALID; + ARM::ArchKind EmittedArch = ARM::ArchKind::INVALID; SmallVector<AttributeItem, 64> Contents; MCSection *AttributeSection = nullptr; @@ -404,8 +404,8 @@ private: void emitTextAttribute(unsigned Attribute, StringRef String) override; void emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue) override; - void emitArch(unsigned Arch) override; - void emitObjectArch(unsigned Arch) override; + void emitArch(ARM::ArchKind Arch) override; + void emitObjectArch(ARM::ArchKind Arch) override; void emitFPU(unsigned FPU) override; void emitInst(uint32_t Inst, char Suffix = '\0') override; void finishAttributeSection() override; @@ -440,9 +440,11 @@ class ARMELFStreamer : public MCELFStreamer { public: friend class ARMTargetELFStreamer; - ARMELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_pwrite_stream &OS, - MCCodeEmitter *Emitter, bool IsThumb) - : MCELFStreamer(Context, TAB, OS, Emitter), IsThumb(IsThumb) { + ARMELFStreamer(MCContext &Context, std::unique_ptr<MCAsmBackend> TAB, + raw_pwrite_stream &OS, std::unique_ptr<MCCodeEmitter> Emitter, + bool IsThumb) + : MCELFStreamer(Context, std::move(TAB), OS, std::move(Emitter)), + IsThumb(IsThumb) { EHReset(); } @@ -776,11 +778,11 @@ void ARMTargetELFStreamer::emitIntTextAttribute(unsigned Attribute, /* OverwriteExisting= */ true); } -void ARMTargetELFStreamer::emitArch(unsigned Value) { +void ARMTargetELFStreamer::emitArch(ARM::ArchKind Value) { Arch = Value; } -void ARMTargetELFStreamer::emitObjectArch(unsigned Value) { +void ARMTargetELFStreamer::emitObjectArch(ARM::ArchKind Value) { EmittedArch = Value; } @@ -791,7 +793,7 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() { ARM::getCPUAttr(Arch), false); - if (EmittedArch == ARM::AK_INVALID) + if (EmittedArch == ARM::ArchKind::INVALID) setAttributeItem(CPU_arch, ARM::getArchAttr(Arch), false); @@ -801,58 +803,59 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() { false); switch (Arch) { - case ARM::AK_ARMV2: - case ARM::AK_ARMV2A: - case ARM::AK_ARMV3: - case ARM::AK_ARMV3M: - case ARM::AK_ARMV4: + case ARM::ArchKind::ARMV2: + case ARM::ArchKind::ARMV2A: + case ARM::ArchKind::ARMV3: + case ARM::ArchKind::ARMV3M: + case ARM::ArchKind::ARMV4: setAttributeItem(ARM_ISA_use, Allowed, false); break; - case ARM::AK_ARMV4T: - case ARM::AK_ARMV5T: - case ARM::AK_ARMV5TE: - case ARM::AK_ARMV6: + case ARM::ArchKind::ARMV4T: + case ARM::ArchKind::ARMV5T: + case ARM::ArchKind::ARMV5TE: + case ARM::ArchKind::ARMV6: setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, Allowed, false); break; - case ARM::AK_ARMV6T2: + case ARM::ArchKind::ARMV6T2: setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, AllowThumb32, false); break; - case ARM::AK_ARMV6K: - case ARM::AK_ARMV6KZ: + case ARM::ArchKind::ARMV6K: + case ARM::ArchKind::ARMV6KZ: setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, Allowed, false); setAttributeItem(Virtualization_use, AllowTZ, false); break; - case ARM::AK_ARMV6M: + case ARM::ArchKind::ARMV6M: setAttributeItem(THUMB_ISA_use, Allowed, false); break; - case ARM::AK_ARMV7A: + case ARM::ArchKind::ARMV7A: setAttributeItem(CPU_arch_profile, ApplicationProfile, false); setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, AllowThumb32, false); break; - case ARM::AK_ARMV7R: + case ARM::ArchKind::ARMV7R: setAttributeItem(CPU_arch_profile, RealTimeProfile, false); setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, AllowThumb32, false); break; - case ARM::AK_ARMV7M: + case ARM::ArchKind::ARMV7EM: + case ARM::ArchKind::ARMV7M: setAttributeItem(CPU_arch_profile, MicroControllerProfile, false); setAttributeItem(THUMB_ISA_use, AllowThumb32, false); break; - case ARM::AK_ARMV8A: - case ARM::AK_ARMV8_1A: - case ARM::AK_ARMV8_2A: + case ARM::ArchKind::ARMV8A: + case ARM::ArchKind::ARMV8_1A: + case ARM::ArchKind::ARMV8_2A: setAttributeItem(CPU_arch_profile, ApplicationProfile, false); setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, AllowThumb32, false); @@ -860,26 +863,26 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() { setAttributeItem(Virtualization_use, AllowTZVirtualization, false); break; - case ARM::AK_ARMV8MBaseline: - case ARM::AK_ARMV8MMainline: + case ARM::ArchKind::ARMV8MBaseline: + case ARM::ArchKind::ARMV8MMainline: setAttributeItem(THUMB_ISA_use, AllowThumbDerived, false); setAttributeItem(CPU_arch_profile, MicroControllerProfile, false); break; - case ARM::AK_IWMMXT: + case ARM::ArchKind::IWMMXT: setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, Allowed, false); setAttributeItem(WMMX_arch, AllowWMMXv1, false); break; - case ARM::AK_IWMMXT2: + case ARM::ArchKind::IWMMXT2: setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, Allowed, false); setAttributeItem(WMMX_arch, AllowWMMXv2, false); break; default: - report_fatal_error("Unknown Arch: " + Twine(Arch)); + report_fatal_error("Unknown Arch: " + Twine(ARM::getArchName(Arch))); break; } } @@ -1057,7 +1060,7 @@ void ARMTargetELFStreamer::finishAttributeSection() { if (FPU != ARM::FK_INVALID) emitFPUDefaultAttributes(); - if (Arch != ARM::AK_INVALID) + if (Arch != ARM::ArchKind::INVALID) emitArchDefaultAttributes(); if (Contents.empty()) @@ -1169,6 +1172,8 @@ void ARMELFStreamer::reset() { ATS.reset(); MappingSymbolCounter = 0; MCELFStreamer::reset(); + LastMappingSymbols.clear(); + LastEMSInfo.reset(); // MCELFStreamer clear's the assembler's e_flags. However, for // arm we manually set the ABI version on streamer creation, so // do the same here @@ -1485,19 +1490,21 @@ MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S, return new ARMTargetStreamer(S); } -MCELFStreamer *createARMELFStreamer(MCContext &Context, MCAsmBackend &TAB, +MCELFStreamer *createARMELFStreamer(MCContext &Context, + std::unique_ptr<MCAsmBackend> TAB, raw_pwrite_stream &OS, - MCCodeEmitter *Emitter, bool RelaxAll, - bool IsThumb) { - ARMELFStreamer *S = new ARMELFStreamer(Context, TAB, OS, Emitter, IsThumb); - // FIXME: This should eventually end up somewhere else where more - // intelligent flag decisions can be made. For now we are just maintaining - // the status quo for ARM and setting EF_ARM_EABI_VER5 as the default. - S->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5); + std::unique_ptr<MCCodeEmitter> Emitter, + bool RelaxAll, bool IsThumb) { + ARMELFStreamer *S = new ARMELFStreamer(Context, std::move(TAB), OS, + std::move(Emitter), IsThumb); + // FIXME: This should eventually end up somewhere else where more + // intelligent flag decisions can be made. For now we are just maintaining + // the status quo for ARM and setting EF_ARM_EABI_VER5 as the default. + S->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5); - if (RelaxAll) - S->getAssembler().setRelaxAll(true); - return S; + if (RelaxAll) + S->getAssembler().setRelaxAll(true); + return S; } } // end namespace llvm diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp index 1e062ad45af5..0cef683778e5 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp @@ -58,7 +58,6 @@ ARMELFMCAsmInfo::ARMELFMCAsmInfo(const Triple &TheTriple) { // Exceptions handling switch (TheTriple.getOS()) { - case Triple::Bitrig: case Triple::NetBSD: ExceptionsType = ExceptionHandling::DwarfCFI; break; @@ -87,7 +86,7 @@ void ARMCOFFMCAsmInfoMicrosoft::anchor() { } ARMCOFFMCAsmInfoMicrosoft::ARMCOFFMCAsmInfoMicrosoft() { AlignmentIsInBytes = false; - + ExceptionsType = ExceptionHandling::WinEH; PrivateGlobalPrefix = "$M"; PrivateLabelPrefix = "$M"; CommentString = ";"; @@ -106,10 +105,10 @@ ARMCOFFMCAsmInfoGNU::ARMCOFFMCAsmInfoGNU() { PrivateLabelPrefix = ".L"; SupportsDebugInformation = true; - ExceptionsType = ExceptionHandling::None; + ExceptionsType = ExceptionHandling::DwarfCFI; UseParensForSymbolVariant = true; - UseIntegratedAssembler = false; - DwarfRegNumForCFI = true; + UseIntegratedAssembler = true; + DwarfRegNumForCFI = false; } diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCExpr.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCExpr.cpp index 2063ca6bdf3b..306f068312f5 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCExpr.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCExpr.cpp @@ -8,7 +8,6 @@ //===----------------------------------------------------------------------===// #include "ARMMCExpr.h" -#include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCStreamer.h" using namespace llvm; diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp index 2ab7bfe4410b..ae5bc723ee5f 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -16,6 +16,8 @@ #include "ARMMCAsmInfo.h" #include "InstPrinter/ARMInstPrinter.h" #include "llvm/ADT/Triple.h" +#include "llvm/MC/MCAsmBackend.h" +#include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrInfo.h" @@ -131,16 +133,13 @@ static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI, #include "ARMGenSubtargetInfo.inc" std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) { - bool isThumb = - TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb; - std::string ARMArchFeature; - unsigned ArchID = ARM::parseArch(TT.getArchName()); - if (ArchID != ARM::AK_INVALID && (CPU.empty() || CPU == "generic")) + ARM::ArchKind ArchID = ARM::parseArch(TT.getArchName()); + if (ArchID != ARM::ArchKind::INVALID && (CPU.empty() || CPU == "generic")) ARMArchFeature = (ARMArchFeature + "+" + ARM::getArchName(ArchID)).str(); - if (isThumb) { + if (TT.isThumb()) { if (ARMArchFeature.empty()) ARMArchFeature = "+thumb-mode,+v4t"; else @@ -201,18 +200,22 @@ static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, } static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx, - MCAsmBackend &MAB, raw_pwrite_stream &OS, - MCCodeEmitter *Emitter, bool RelaxAll) { - return createARMELFStreamer(Ctx, MAB, OS, Emitter, false, - (T.getArch() == Triple::thumb || - T.getArch() == Triple::thumbeb)); + std::unique_ptr<MCAsmBackend> &&MAB, + raw_pwrite_stream &OS, + std::unique_ptr<MCCodeEmitter> &&Emitter, + bool RelaxAll) { + return createARMELFStreamer( + Ctx, std::move(MAB), OS, std::move(Emitter), false, + (T.getArch() == Triple::thumb || T.getArch() == Triple::thumbeb)); } -static MCStreamer *createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB, - raw_pwrite_stream &OS, - MCCodeEmitter *Emitter, bool RelaxAll, - bool DWARFMustBeAtTheEnd) { - return createMachOStreamer(Ctx, MAB, OS, Emitter, false, DWARFMustBeAtTheEnd); +static MCStreamer * +createARMMachOStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&MAB, + raw_pwrite_stream &OS, + std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll, + bool DWARFMustBeAtTheEnd) { + return createMachOStreamer(Ctx, std::move(MAB), OS, std::move(Emitter), false, + DWARFMustBeAtTheEnd); } static MCInstPrinter *createARMMCInstPrinter(const Triple &T, diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h index ba834201e585..0fb97e5fee97 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h +++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h @@ -15,6 +15,7 @@ #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H #include "llvm/Support/DataTypes.h" +#include <memory> #include <string> namespace llvm { @@ -92,23 +93,27 @@ MCAsmBackend *createThumbBEAsmBackend(const Target &T, // Construct a PE/COFF machine code streamer which will generate a PE/COFF // object file. -MCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB, +MCStreamer *createARMWinCOFFStreamer(MCContext &Context, + std::unique_ptr<MCAsmBackend> &&MAB, raw_pwrite_stream &OS, - MCCodeEmitter *Emitter, bool RelaxAll, + std::unique_ptr<MCCodeEmitter> &&Emitter, + bool RelaxAll, bool IncrementalLinkerCompatible); /// Construct an ELF Mach-O object writer. -MCObjectWriter *createARMELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, - bool IsLittleEndian); +std::unique_ptr<MCObjectWriter> createARMELFObjectWriter(raw_pwrite_stream &OS, + uint8_t OSABI, + bool IsLittleEndian); /// Construct an ARM Mach-O object writer. -MCObjectWriter *createARMMachObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, - uint32_t CPUType, - uint32_t CPUSubtype); +std::unique_ptr<MCObjectWriter> createARMMachObjectWriter(raw_pwrite_stream &OS, + bool Is64Bit, + uint32_t CPUType, + uint32_t CPUSubtype); /// Construct an ARM PE/COFF object writer. -MCObjectWriter *createARMWinCOFFObjectWriter(raw_pwrite_stream &OS, - bool Is64Bit); +std::unique_ptr<MCObjectWriter> +createARMWinCOFFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit); /// Construct ARM Mach-O relocation info. MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx); diff --git a/lib/Target/ARM/MCTargetDesc/ARMMachORelocationInfo.cpp b/lib/Target/ARM/MCTargetDesc/ARMMachORelocationInfo.cpp index 5516a1bdb03d..6259c98321f4 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMachORelocationInfo.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMachORelocationInfo.cpp @@ -10,7 +10,6 @@ #include "ARMMCExpr.h" #include "MCTargetDesc/ARMMCTargetDesc.h" #include "llvm-c/Disassembler.h" -#include "llvm/MC/MCContext.h" #include "llvm/MC/MCDisassembler/MCRelocationInfo.h" #include "llvm/MC/MCExpr.h" diff --git a/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp index 4a8139dea668..521ae5337e7a 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMachObjectWriter.cpp @@ -322,6 +322,14 @@ bool ARMMachObjectWriter::requiresExternRelocation(MachObjectWriter *Writer, default: return false; case MachO::ARM_RELOC_BR24: + // An ARM call might be to a Thumb function, in which case the offset may + // not be encodable in the instruction and we must use an external + // relocation that explicitly mentions the function. Not a problem if it's + // to a temporary "Lwhatever" symbol though, and in fact trying to use an + // external relocation there causes more issues. + if (!S.isTemporary()) + return true; + // PC pre-adjustment of 8 for these instructions. Value -= 8; // ARM BL/BLX has a 25-bit offset. @@ -476,11 +484,10 @@ void ARMMachObjectWriter::recordRelocation(MachObjectWriter *Writer, Writer->addRelocation(RelSymbol, Fragment->getParent(), MRE); } -MCObjectWriter *llvm::createARMMachObjectWriter(raw_pwrite_stream &OS, - bool Is64Bit, uint32_t CPUType, - uint32_t CPUSubtype) { - return createMachObjectWriter(new ARMMachObjectWriter(Is64Bit, - CPUType, - CPUSubtype), - OS, /*IsLittleEndian=*/true); +std::unique_ptr<MCObjectWriter> +llvm::createARMMachObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, + uint32_t CPUType, uint32_t CPUSubtype) { + return createMachObjectWriter( + llvm::make_unique<ARMMachObjectWriter>(Is64Bit, CPUType, CPUSubtype), OS, + /*IsLittleEndian=*/true); } diff --git a/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp b/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp index 4a943187ab6d..42371736fef4 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMTargetStreamer.cpp @@ -71,9 +71,9 @@ void ARMTargetStreamer::emitTextAttribute(unsigned Attribute, void ARMTargetStreamer::emitIntTextAttribute(unsigned Attribute, unsigned IntValue, StringRef StringValue) {} -void ARMTargetStreamer::emitArch(unsigned Arch) {} +void ARMTargetStreamer::emitArch(ARM::ArchKind Arch) {} void ARMTargetStreamer::emitArchExtension(unsigned ArchExt) {} -void ARMTargetStreamer::emitObjectArch(unsigned Arch) {} +void ARMTargetStreamer::emitObjectArch(ARM::ArchKind Arch) {} void ARMTargetStreamer::emitFPU(unsigned FPU) {} void ARMTargetStreamer::finishAttributeSection() {} void ARMTargetStreamer::emitInst(uint32_t Inst, char Suffix) {} diff --git a/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp b/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp index f74fb2e20b5a..5e09b126f43f 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp @@ -14,6 +14,7 @@ #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCFixup.h" #include "llvm/MC/MCFixupKindInfo.h" +#include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCValue.h" #include "llvm/MC/MCWinCOFFObjectWriter.h" #include "llvm/Support/ErrorHandling.h" @@ -90,10 +91,10 @@ bool ARMWinCOFFObjectWriter::recordRelocation(const MCFixup &Fixup) const { namespace llvm { -MCObjectWriter *createARMWinCOFFObjectWriter(raw_pwrite_stream &OS, - bool Is64Bit) { - MCWinCOFFObjectTargetWriter *MOTW = new ARMWinCOFFObjectWriter(Is64Bit); - return createWinCOFFObjectWriter(MOTW, OS); +std::unique_ptr<MCObjectWriter> +createARMWinCOFFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit) { + auto MOTW = llvm::make_unique<ARMWinCOFFObjectWriter>(Is64Bit); + return createWinCOFFObjectWriter(std::move(MOTW), OS); } } // end namespace llvm diff --git a/lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp b/lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp index 83fa084e60c7..a2424e1abab3 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp @@ -8,6 +8,8 @@ //===----------------------------------------------------------------------===// #include "ARMMCTargetDesc.h" +#include "llvm/MC/MCAsmBackend.h" +#include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCWinCOFFStreamer.h" using namespace llvm; @@ -15,12 +17,13 @@ using namespace llvm; namespace { class ARMWinCOFFStreamer : public MCWinCOFFStreamer { public: - ARMWinCOFFStreamer(MCContext &C, MCAsmBackend &AB, MCCodeEmitter &CE, - raw_pwrite_stream &OS) - : MCWinCOFFStreamer(C, AB, CE, OS) {} + ARMWinCOFFStreamer(MCContext &C, std::unique_ptr<MCAsmBackend> AB, + std::unique_ptr<MCCodeEmitter> CE, raw_pwrite_stream &OS) + : MCWinCOFFStreamer(C, std::move(AB), std::move(CE), OS) {} void EmitAssemblerFlag(MCAssemblerFlag Flag) override; void EmitThumbFunc(MCSymbol *Symbol) override; + void FinishImpl() override; }; void ARMWinCOFFStreamer::EmitAssemblerFlag(MCAssemblerFlag Flag) { @@ -35,12 +38,20 @@ void ARMWinCOFFStreamer::EmitAssemblerFlag(MCAssemblerFlag Flag) { void ARMWinCOFFStreamer::EmitThumbFunc(MCSymbol *Symbol) { getAssembler().setIsThumbFunc(Symbol); } + +void ARMWinCOFFStreamer::FinishImpl() { + EmitFrames(nullptr); + + MCWinCOFFStreamer::FinishImpl(); +} } MCStreamer *llvm::createARMWinCOFFStreamer( - MCContext &Context, MCAsmBackend &MAB, raw_pwrite_stream &OS, - MCCodeEmitter *Emitter, bool RelaxAll, bool IncrementalLinkerCompatible) { - auto *S = new ARMWinCOFFStreamer(Context, MAB, *Emitter, OS); + MCContext &Context, std::unique_ptr<MCAsmBackend> &&MAB, + raw_pwrite_stream &OS, std::unique_ptr<MCCodeEmitter> &&Emitter, + bool RelaxAll, bool IncrementalLinkerCompatible) { + auto *S = + new ARMWinCOFFStreamer(Context, std::move(MAB), std::move(Emitter), OS); S->getAssembler().setIncrementalLinkerCompatible(IncrementalLinkerCompatible); return S; } |