diff options
Diffstat (limited to 'lib/Target/WebAssembly/WebAssemblyInstrAtomics.td')
| -rw-r--r-- | lib/Target/WebAssembly/WebAssemblyInstrAtomics.td | 546 |
1 files changed, 213 insertions, 333 deletions
diff --git a/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td b/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td index 5fb8ef90bc43..e85aa57efc42 100644 --- a/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td +++ b/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td @@ -1,9 +1,8 @@ // WebAssemblyInstrAtomics.td-WebAssembly Atomic codegen support-*- tablegen -*- // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// /// @@ -12,20 +11,132 @@ /// //===----------------------------------------------------------------------===// +let UseNamedOperandTable = 1 in +multiclass ATOMIC_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s, + list<dag> pattern_r, string asmstr_r = "", + string asmstr_s = "", bits<32> atomic_op = -1> { + defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s, + !or(0xfe00, !and(0xff, atomic_op))>, + Requires<[HasAtomics]>; +} + +multiclass ATOMIC_NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "", + bits<32> atomic_op = -1> { + defm "" : NRI<oops, iops, pattern, asmstr, + !or(0xfe00, !and(0xff, atomic_op))>, + Requires<[HasAtomics]>; +} + +//===----------------------------------------------------------------------===// +// Atomic wait / notify +//===----------------------------------------------------------------------===// + +let hasSideEffects = 1 in { +defm ATOMIC_NOTIFY : + ATOMIC_I<(outs I32:$dst), + (ins P2Align:$p2align, offset32_op:$off, I32:$addr, I32:$count), + (outs), (ins P2Align:$p2align, offset32_op:$off), [], + "atomic.notify \t$dst, ${off}(${addr})${p2align}, $count", + "atomic.notify \t${off}${p2align}", 0x00>; +let mayLoad = 1 in { +defm ATOMIC_WAIT_I32 : + ATOMIC_I<(outs I32:$dst), + (ins P2Align:$p2align, offset32_op:$off, I32:$addr, I32:$exp, + I64:$timeout), + (outs), (ins P2Align:$p2align, offset32_op:$off), [], + "i32.atomic.wait \t$dst, ${off}(${addr})${p2align}, $exp, $timeout", + "i32.atomic.wait \t${off}${p2align}", 0x01>; +defm ATOMIC_WAIT_I64 : + ATOMIC_I<(outs I32:$dst), + (ins P2Align:$p2align, offset32_op:$off, I32:$addr, I64:$exp, + I64:$timeout), + (outs), (ins P2Align:$p2align, offset32_op:$off), [], + "i64.atomic.wait \t$dst, ${off}(${addr})${p2align}, $exp, $timeout", + "i64.atomic.wait \t${off}${p2align}", 0x02>; +} // mayLoad = 1 +} // hasSideEffects = 1 + +let Predicates = [HasAtomics] in { +// Select notifys with no constant offset. +def NotifyPatNoOffset : + Pat<(i32 (int_wasm_atomic_notify I32:$addr, I32:$count)), + (ATOMIC_NOTIFY 0, 0, I32:$addr, I32:$count)>; + +// Select notifys with a constant offset. + +// Pattern with address + immediate offset +class NotifyPatImmOff<PatFrag operand> : + Pat<(i32 (int_wasm_atomic_notify (operand I32:$addr, imm:$off), I32:$count)), + (ATOMIC_NOTIFY 0, imm:$off, I32:$addr, I32:$count)>; +def : NotifyPatImmOff<regPlusImm>; +def : NotifyPatImmOff<or_is_add>; + +def NotifyPatGlobalAddr : + Pat<(i32 (int_wasm_atomic_notify (regPlusGA I32:$addr, + (WebAssemblywrapper tglobaladdr:$off)), + I32:$count)), + (ATOMIC_NOTIFY 0, tglobaladdr:$off, I32:$addr, I32:$count)>; + +// Select notifys with just a constant offset. +def NotifyPatOffsetOnly : + Pat<(i32 (int_wasm_atomic_notify imm:$off, I32:$count)), + (ATOMIC_NOTIFY 0, imm:$off, (CONST_I32 0), I32:$count)>; + +def NotifyPatGlobalAddrOffOnly : + Pat<(i32 (int_wasm_atomic_notify (WebAssemblywrapper tglobaladdr:$off), + I32:$count)), + (ATOMIC_NOTIFY 0, tglobaladdr:$off, (CONST_I32 0), I32:$count)>; + +// Select waits with no constant offset. +class WaitPatNoOffset<ValueType ty, Intrinsic kind, NI inst> : + Pat<(i32 (kind I32:$addr, ty:$exp, I64:$timeout)), + (inst 0, 0, I32:$addr, ty:$exp, I64:$timeout)>; +def : WaitPatNoOffset<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>; +def : WaitPatNoOffset<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>; + +// Select waits with a constant offset. + +// Pattern with address + immediate offset +class WaitPatImmOff<ValueType ty, Intrinsic kind, PatFrag operand, NI inst> : + Pat<(i32 (kind (operand I32:$addr, imm:$off), ty:$exp, I64:$timeout)), + (inst 0, imm:$off, I32:$addr, ty:$exp, I64:$timeout)>; +def : WaitPatImmOff<i32, int_wasm_atomic_wait_i32, regPlusImm, ATOMIC_WAIT_I32>; +def : WaitPatImmOff<i32, int_wasm_atomic_wait_i32, or_is_add, ATOMIC_WAIT_I32>; +def : WaitPatImmOff<i64, int_wasm_atomic_wait_i64, regPlusImm, ATOMIC_WAIT_I64>; +def : WaitPatImmOff<i64, int_wasm_atomic_wait_i64, or_is_add, ATOMIC_WAIT_I64>; + +class WaitPatGlobalAddr<ValueType ty, Intrinsic kind, NI inst> : + Pat<(i32 (kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)), + ty:$exp, I64:$timeout)), + (inst 0, tglobaladdr:$off, I32:$addr, ty:$exp, I64:$timeout)>; +def : WaitPatGlobalAddr<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>; +def : WaitPatGlobalAddr<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>; + +// Select wait_i32, ATOMIC_WAIT_I32s with just a constant offset. +class WaitPatOffsetOnly<ValueType ty, Intrinsic kind, NI inst> : + Pat<(i32 (kind imm:$off, ty:$exp, I64:$timeout)), + (inst 0, imm:$off, (CONST_I32 0), ty:$exp, I64:$timeout)>; +def : WaitPatOffsetOnly<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>; +def : WaitPatOffsetOnly<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>; + +class WaitPatGlobalAddrOffOnly<ValueType ty, Intrinsic kind, NI inst> : + Pat<(i32 (kind (WebAssemblywrapper tglobaladdr:$off), ty:$exp, I64:$timeout)), + (inst 0, tglobaladdr:$off, (CONST_I32 0), ty:$exp, I64:$timeout)>; +def : WaitPatGlobalAddrOffOnly<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>; +def : WaitPatGlobalAddrOffOnly<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>; +} // Predicates = [HasAtomics] + //===----------------------------------------------------------------------===// // Atomic loads //===----------------------------------------------------------------------===// -multiclass ATOMIC_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s, - list<dag> pattern_r, string asmstr_r = "", - string asmstr_s = "", bits<32> inst = -1> { - defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s, - inst>, +multiclass AtomicLoad<WebAssemblyRegClass rc, string name, int atomic_op> { + defm "" : WebAssemblyLoad<rc, name, !or(0xfe00, !and(0xff, atomic_op))>, Requires<[HasAtomics]>; } -defm ATOMIC_LOAD_I32 : WebAssemblyLoad<I32, "i32.atomic.load", 0xfe10>; -defm ATOMIC_LOAD_I64 : WebAssemblyLoad<I64, "i64.atomic.load", 0xfe11>; +defm ATOMIC_LOAD_I32 : AtomicLoad<I32, "i32.atomic.load", 0x10>; +defm ATOMIC_LOAD_I64 : AtomicLoad<I64, "i64.atomic.load", 0x11>; // Select loads with no constant offset. let Predicates = [HasAtomics] in { @@ -43,9 +154,6 @@ def : LoadPatImmOff<i64, atomic_load_64, or_is_add, ATOMIC_LOAD_I64>; def : LoadPatGlobalAddr<i32, atomic_load_32, ATOMIC_LOAD_I32>; def : LoadPatGlobalAddr<i64, atomic_load_64, ATOMIC_LOAD_I64>; -def : LoadPatExternalSym<i32, atomic_load_32, ATOMIC_LOAD_I32>; -def : LoadPatExternalSym<i64, atomic_load_64, ATOMIC_LOAD_I64>; - // Select loads with just a constant offset. def : LoadPatOffsetOnly<i32, atomic_load_32, ATOMIC_LOAD_I32>; def : LoadPatOffsetOnly<i64, atomic_load_64, ATOMIC_LOAD_I64>; @@ -53,18 +161,15 @@ def : LoadPatOffsetOnly<i64, atomic_load_64, ATOMIC_LOAD_I64>; def : LoadPatGlobalAddrOffOnly<i32, atomic_load_32, ATOMIC_LOAD_I32>; def : LoadPatGlobalAddrOffOnly<i64, atomic_load_64, ATOMIC_LOAD_I64>; -def : LoadPatExternSymOffOnly<i32, atomic_load_32, ATOMIC_LOAD_I32>; -def : LoadPatExternSymOffOnly<i64, atomic_load_64, ATOMIC_LOAD_I64>; - } // Predicates = [HasAtomics] // Extending loads. Note that there are only zero-extending atomic loads, no // sign-extending loads. -defm ATOMIC_LOAD8_U_I32 : WebAssemblyLoad<I32, "i32.atomic.load8_u", 0xfe12>; -defm ATOMIC_LOAD16_U_I32 : WebAssemblyLoad<I32, "i32.atomic.load16_u", 0xfe13>; -defm ATOMIC_LOAD8_U_I64 : WebAssemblyLoad<I64, "i64.atomic.load8_u", 0xfe14>; -defm ATOMIC_LOAD16_U_I64 : WebAssemblyLoad<I64, "i64.atomic.load16_u", 0xfe15>; -defm ATOMIC_LOAD32_U_I64 : WebAssemblyLoad<I64, "i64.atomic.load32_u", 0xfe16>; +defm ATOMIC_LOAD8_U_I32 : AtomicLoad<I32, "i32.atomic.load8_u", 0x12>; +defm ATOMIC_LOAD16_U_I32 : AtomicLoad<I32, "i32.atomic.load16_u", 0x13>; +defm ATOMIC_LOAD8_U_I64 : AtomicLoad<I64, "i64.atomic.load8_u", 0x14>; +defm ATOMIC_LOAD16_U_I64 : AtomicLoad<I64, "i64.atomic.load16_u", 0x15>; +defm ATOMIC_LOAD32_U_I64 : AtomicLoad<I64, "i64.atomic.load32_u", 0x16>; // Fragments for extending loads. These are different from regular loads because // the SDNodes are derived from AtomicSDNode rather than LoadSDNode and @@ -149,16 +254,6 @@ def : LoadPatGlobalAddr<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>; def : LoadPatGlobalAddr<i64, sext_aload_8_64, ATOMIC_LOAD8_U_I64>; def : LoadPatGlobalAddr<i64, sext_aload_16_64, ATOMIC_LOAD16_U_I64>; -def : LoadPatExternalSym<i32, zext_aload_8_32, ATOMIC_LOAD8_U_I32>; -def : LoadPatExternalSym<i32, zext_aload_16_32, ATOMIC_LOAD16_U_I32>; -def : LoadPatExternalSym<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>; -def : LoadPatExternalSym<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>; -def : LoadPatExternalSym<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>; -def : LoadPatExternalSym<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>; -def : LoadPatExternalSym<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>; -def : LoadPatExternalSym<i64, sext_aload_8_64, ATOMIC_LOAD8_U_I64>; -def : LoadPatExternalSym<i64, sext_aload_16_64, ATOMIC_LOAD16_U_I64>; - // Extending loads with just a constant offset def : LoadPatOffsetOnly<i32, zext_aload_8_32, ATOMIC_LOAD8_U_I32>; def : LoadPatOffsetOnly<i32, zext_aload_16_32, ATOMIC_LOAD16_U_I32>; @@ -180,24 +275,19 @@ def : LoadPatGlobalAddrOffOnly<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>; def : LoadPatGlobalAddrOffOnly<i64, sext_aload_8_64, ATOMIC_LOAD8_U_I64>; def : LoadPatGlobalAddrOffOnly<i64, sext_aload_16_64, ATOMIC_LOAD16_U_I64>; -def : LoadPatExternSymOffOnly<i32, zext_aload_8_32, ATOMIC_LOAD8_U_I32>; -def : LoadPatExternSymOffOnly<i32, zext_aload_16_32, ATOMIC_LOAD16_U_I32>; -def : LoadPatExternSymOffOnly<i64, zext_aload_8_64, ATOMIC_LOAD8_U_I64>; -def : LoadPatExternSymOffOnly<i64, zext_aload_16_64, ATOMIC_LOAD16_U_I64>; -def : LoadPatExternSymOffOnly<i64, zext_aload_32_64, ATOMIC_LOAD32_U_I64>; -def : LoadPatExternSymOffOnly<i32, atomic_load_8, ATOMIC_LOAD8_U_I32>; -def : LoadPatExternSymOffOnly<i32, atomic_load_16, ATOMIC_LOAD16_U_I32>; -def : LoadPatExternSymOffOnly<i64, sext_aload_8_64, ATOMIC_LOAD8_U_I64>; -def : LoadPatExternSymOffOnly<i64, sext_aload_16_64, ATOMIC_LOAD16_U_I64>; - } // Predicates = [HasAtomics] //===----------------------------------------------------------------------===// // Atomic stores //===----------------------------------------------------------------------===// -defm ATOMIC_STORE_I32 : WebAssemblyStore<I32, "i32.atomic.store", 0xfe17>; -defm ATOMIC_STORE_I64 : WebAssemblyStore<I64, "i64.atomic.store", 0xfe18>; +multiclass AtomicStore<WebAssemblyRegClass rc, string name, int atomic_op> { + defm "" : WebAssemblyStore<rc, name, !or(0xfe00, !and(0xff, atomic_op))>, + Requires<[HasAtomics]>; +} + +defm ATOMIC_STORE_I32 : AtomicStore<I32, "i32.atomic.store", 0x17>; +defm ATOMIC_STORE_I64 : AtomicStore<I64, "i64.atomic.store", 0x18>; // We need an 'atomic' version of store patterns because store and atomic_store // nodes have different operand orders: @@ -230,12 +320,6 @@ class AStorePatGlobalAddr<ValueType ty, PatFrag kind, NI inst> : def : AStorePatGlobalAddr<i32, atomic_store_32, ATOMIC_STORE_I32>; def : AStorePatGlobalAddr<i64, atomic_store_64, ATOMIC_STORE_I64>; -class AStorePatExternalSym<ValueType ty, PatFrag kind, NI inst> : - Pat<(kind (add I32:$addr, (WebAssemblywrapper texternalsym:$off)), ty:$val), - (inst 0, texternalsym:$off, I32:$addr, ty:$val)>; -def : AStorePatExternalSym<i32, atomic_store_32, ATOMIC_STORE_I32>; -def : AStorePatExternalSym<i64, atomic_store_64, ATOMIC_STORE_I64>; - // Select stores with just a constant offset. class AStorePatOffsetOnly<ValueType ty, PatFrag kind, NI inst> : Pat<(kind imm:$off, ty:$val), (inst 0, imm:$off, (CONST_I32 0), ty:$val)>; @@ -248,20 +332,14 @@ class AStorePatGlobalAddrOffOnly<ValueType ty, PatFrag kind, NI inst> : def : AStorePatGlobalAddrOffOnly<i32, atomic_store_32, ATOMIC_STORE_I32>; def : AStorePatGlobalAddrOffOnly<i64, atomic_store_64, ATOMIC_STORE_I64>; -class AStorePatExternSymOffOnly<ValueType ty, PatFrag kind, NI inst> : - Pat<(kind (WebAssemblywrapper texternalsym:$off), ty:$val), - (inst 0, texternalsym:$off, (CONST_I32 0), ty:$val)>; -def : AStorePatExternSymOffOnly<i32, atomic_store_32, ATOMIC_STORE_I32>; -def : AStorePatExternSymOffOnly<i64, atomic_store_64, ATOMIC_STORE_I64>; - } // Predicates = [HasAtomics] // Truncating stores. -defm ATOMIC_STORE8_I32 : WebAssemblyStore<I32, "i32.atomic.store8", 0xfe19>; -defm ATOMIC_STORE16_I32 : WebAssemblyStore<I32, "i32.atomic.store16", 0xfe1a>; -defm ATOMIC_STORE8_I64 : WebAssemblyStore<I64, "i64.atomic.store8", 0xfe1b>; -defm ATOMIC_STORE16_I64 : WebAssemblyStore<I64, "i64.atomic.store16", 0xfe1c>; -defm ATOMIC_STORE32_I64 : WebAssemblyStore<I64, "i64.atomic.store32", 0xfe1d>; +defm ATOMIC_STORE8_I32 : AtomicStore<I32, "i32.atomic.store8", 0x19>; +defm ATOMIC_STORE16_I32 : AtomicStore<I32, "i32.atomic.store16", 0x1a>; +defm ATOMIC_STORE8_I64 : AtomicStore<I64, "i64.atomic.store8", 0x1b>; +defm ATOMIC_STORE16_I64 : AtomicStore<I64, "i64.atomic.store16", 0x1c>; +defm ATOMIC_STORE32_I64 : AtomicStore<I64, "i64.atomic.store32", 0x1d>; // Fragments for truncating stores. @@ -302,12 +380,6 @@ def : AStorePatGlobalAddr<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>; def : AStorePatGlobalAddr<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>; def : AStorePatGlobalAddr<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>; -def : AStorePatExternalSym<i32, atomic_store_8, ATOMIC_STORE8_I32>; -def : AStorePatExternalSym<i32, atomic_store_16, ATOMIC_STORE16_I32>; -def : AStorePatExternalSym<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>; -def : AStorePatExternalSym<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>; -def : AStorePatExternalSym<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>; - // Truncating stores with just a constant offset def : AStorePatOffsetOnly<i32, atomic_store_8, ATOMIC_STORE8_I32>; def : AStorePatOffsetOnly<i32, atomic_store_16, ATOMIC_STORE16_I32>; @@ -321,105 +393,101 @@ def : AStorePatGlobalAddrOffOnly<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>; def : AStorePatGlobalAddrOffOnly<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>; def : AStorePatGlobalAddrOffOnly<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>; -def : AStorePatExternSymOffOnly<i32, atomic_store_8, ATOMIC_STORE8_I32>; -def : AStorePatExternSymOffOnly<i32, atomic_store_16, ATOMIC_STORE16_I32>; -def : AStorePatExternSymOffOnly<i64, trunc_astore_8_64, ATOMIC_STORE8_I64>; -def : AStorePatExternSymOffOnly<i64, trunc_astore_16_64, ATOMIC_STORE16_I64>; -def : AStorePatExternSymOffOnly<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>; - } // Predicates = [HasAtomics] //===----------------------------------------------------------------------===// // Atomic binary read-modify-writes //===----------------------------------------------------------------------===// -multiclass WebAssemblyBinRMW<WebAssemblyRegClass rc, string Name, int Opcode> { - defm "" : I<(outs rc:$dst), - (ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$val), - (outs), (ins P2Align:$p2align, offset32_op:$off), [], - !strconcat(Name, "\t$dst, ${off}(${addr})${p2align}, $val"), - !strconcat(Name, "\t${off}, ${p2align}"), Opcode>; +multiclass WebAssemblyBinRMW<WebAssemblyRegClass rc, string name, + int atomic_op> { + defm "" : + ATOMIC_I<(outs rc:$dst), + (ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$val), + (outs), (ins P2Align:$p2align, offset32_op:$off), [], + !strconcat(name, "\t$dst, ${off}(${addr})${p2align}, $val"), + !strconcat(name, "\t${off}${p2align}"), atomic_op>; } -defm ATOMIC_RMW_ADD_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.add", 0xfe1e>; -defm ATOMIC_RMW_ADD_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.add", 0xfe1f>; +defm ATOMIC_RMW_ADD_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.add", 0x1e>; +defm ATOMIC_RMW_ADD_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.add", 0x1f>; defm ATOMIC_RMW8_U_ADD_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw8.add_u", 0xfe20>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw8.add_u", 0x20>; defm ATOMIC_RMW16_U_ADD_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw16.add_u", 0xfe21>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw16.add_u", 0x21>; defm ATOMIC_RMW8_U_ADD_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw8.add_u", 0xfe22>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw8.add_u", 0x22>; defm ATOMIC_RMW16_U_ADD_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw16.add_u", 0xfe23>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw16.add_u", 0x23>; defm ATOMIC_RMW32_U_ADD_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw32.add_u", 0xfe24>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw32.add_u", 0x24>; -defm ATOMIC_RMW_SUB_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.sub", 0xfe25>; -defm ATOMIC_RMW_SUB_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.sub", 0xfe26>; +defm ATOMIC_RMW_SUB_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.sub", 0x25>; +defm ATOMIC_RMW_SUB_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.sub", 0x26>; defm ATOMIC_RMW8_U_SUB_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw8.sub_u", 0xfe27>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw8.sub_u", 0x27>; defm ATOMIC_RMW16_U_SUB_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw16.sub_u", 0xfe28>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw16.sub_u", 0x28>; defm ATOMIC_RMW8_U_SUB_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw8.sub_u", 0xfe29>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw8.sub_u", 0x29>; defm ATOMIC_RMW16_U_SUB_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw16.sub_u", 0xfe2a>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw16.sub_u", 0x2a>; defm ATOMIC_RMW32_U_SUB_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw32.sub_u", 0xfe2b>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw32.sub_u", 0x2b>; -defm ATOMIC_RMW_AND_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.and", 0xfe2c>; -defm ATOMIC_RMW_AND_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.and", 0xfe2d>; +defm ATOMIC_RMW_AND_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.and", 0x2c>; +defm ATOMIC_RMW_AND_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.and", 0x2d>; defm ATOMIC_RMW8_U_AND_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw8.and_u", 0xfe2e>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw8.and_u", 0x2e>; defm ATOMIC_RMW16_U_AND_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw16.and_u", 0xfe2f>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw16.and_u", 0x2f>; defm ATOMIC_RMW8_U_AND_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw8.and_u", 0xfe30>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw8.and_u", 0x30>; defm ATOMIC_RMW16_U_AND_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw16.and_u", 0xfe31>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw16.and_u", 0x31>; defm ATOMIC_RMW32_U_AND_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw32.and_u", 0xfe32>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw32.and_u", 0x32>; -defm ATOMIC_RMW_OR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.or", 0xfe33>; -defm ATOMIC_RMW_OR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.or", 0xfe34>; +defm ATOMIC_RMW_OR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.or", 0x33>; +defm ATOMIC_RMW_OR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.or", 0x34>; defm ATOMIC_RMW8_U_OR_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw8.or_u", 0xfe35>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw8.or_u", 0x35>; defm ATOMIC_RMW16_U_OR_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw16.or_u", 0xfe36>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw16.or_u", 0x36>; defm ATOMIC_RMW8_U_OR_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw8.or_u", 0xfe37>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw8.or_u", 0x37>; defm ATOMIC_RMW16_U_OR_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw16.or_u", 0xfe38>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw16.or_u", 0x38>; defm ATOMIC_RMW32_U_OR_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw32.or_u", 0xfe39>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw32.or_u", 0x39>; -defm ATOMIC_RMW_XOR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.xor", 0xfe3a>; -defm ATOMIC_RMW_XOR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.xor", 0xfe3b>; +defm ATOMIC_RMW_XOR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.xor", 0x3a>; +defm ATOMIC_RMW_XOR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.xor", 0x3b>; defm ATOMIC_RMW8_U_XOR_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xor_u", 0xfe3c>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xor_u", 0x3c>; defm ATOMIC_RMW16_U_XOR_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xor_u", 0xfe3d>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xor_u", 0x3d>; defm ATOMIC_RMW8_U_XOR_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xor_u", 0xfe3e>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xor_u", 0x3e>; defm ATOMIC_RMW16_U_XOR_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xor_u", 0xfe3f>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xor_u", 0x3f>; defm ATOMIC_RMW32_U_XOR_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xor_u", 0xfe40>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xor_u", 0x40>; defm ATOMIC_RMW_XCHG_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw.xchg", 0xfe41>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw.xchg", 0x41>; defm ATOMIC_RMW_XCHG_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw.xchg", 0xfe42>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw.xchg", 0x42>; defm ATOMIC_RMW8_U_XCHG_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xchg_u", 0xfe43>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xchg_u", 0x43>; defm ATOMIC_RMW16_U_XCHG_I32 : - WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xchg_u", 0xfe44>; + WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xchg_u", 0x44>; defm ATOMIC_RMW8_U_XCHG_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xchg_u", 0xfe45>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xchg_u", 0x45>; defm ATOMIC_RMW16_U_XCHG_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xchg_u", 0xfe46>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xchg_u", 0x46>; defm ATOMIC_RMW32_U_XCHG_I64 : - WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xchg_u", 0xfe47>; + WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xchg_u", 0x47>; // Select binary RMWs with no constant offset. class BinRMWPatNoOffset<ValueType ty, PatFrag kind, NI inst> : @@ -437,11 +505,6 @@ class BinRMWPatGlobalAddr<ValueType ty, PatFrag kind, NI inst> : ty:$val)), (inst 0, tglobaladdr:$off, I32:$addr, ty:$val)>; -class BinRMWPatExternalSym<ValueType ty, PatFrag kind, NI inst> : - Pat<(ty (kind (add I32:$addr, (WebAssemblywrapper texternalsym:$off)), - ty:$val)), - (inst 0, texternalsym:$off, I32:$addr, ty:$val)>; - // Select binary RMWs with just a constant offset. class BinRMWPatOffsetOnly<ValueType ty, PatFrag kind, NI inst> : Pat<(ty (kind imm:$off, ty:$val)), @@ -451,10 +514,6 @@ class BinRMWPatGlobalAddrOffOnly<ValueType ty, PatFrag kind, NI inst> : Pat<(ty (kind (WebAssemblywrapper tglobaladdr:$off), ty:$val)), (inst 0, tglobaladdr:$off, (CONST_I32 0), ty:$val)>; -class BinRMWPatExternSymOffOnly<ValueType ty, PatFrag kind, NI inst> : - Pat<(ty (kind (WebAssemblywrapper texternalsym:$off), ty:$val)), - (inst 0, texternalsym:$off, (CONST_I32 0), ty:$val)>; - // Patterns for various addressing modes. multiclass BinRMWPattern<PatFrag rmw_32, PatFrag rmw_64, NI inst_32, NI inst_64> { @@ -469,17 +528,11 @@ multiclass BinRMWPattern<PatFrag rmw_32, PatFrag rmw_64, NI inst_32, def : BinRMWPatGlobalAddr<i32, rmw_32, inst_32>; def : BinRMWPatGlobalAddr<i64, rmw_64, inst_64>; - def : BinRMWPatExternalSym<i32, rmw_32, inst_32>; - def : BinRMWPatExternalSym<i64, rmw_64, inst_64>; - def : BinRMWPatOffsetOnly<i32, rmw_32, inst_32>; def : BinRMWPatOffsetOnly<i64, rmw_64, inst_64>; def : BinRMWPatGlobalAddrOffOnly<i32, rmw_32, inst_32>; def : BinRMWPatGlobalAddrOffOnly<i64, rmw_64, inst_64>; - - def : BinRMWPatExternSymOffOnly<i32, rmw_32, inst_32>; - def : BinRMWPatExternSymOffOnly<i64, rmw_64, inst_64>; } let Predicates = [HasAtomics] in { @@ -580,17 +633,6 @@ multiclass BinRMWTruncExtPattern< def : BinRMWPatGlobalAddr<i64, sext_bin_rmw_8_64<rmw_8>, inst8_64>; def : BinRMWPatGlobalAddr<i64, sext_bin_rmw_16_64<rmw_16>, inst16_64>; - def : BinRMWPatExternalSym<i32, zext_bin_rmw_8_32<rmw_8>, inst8_32>; - def : BinRMWPatExternalSym<i32, zext_bin_rmw_16_32<rmw_16>, inst16_32>; - def : BinRMWPatExternalSym<i64, zext_bin_rmw_8_64<rmw_8>, inst8_64>; - def : BinRMWPatExternalSym<i64, zext_bin_rmw_16_64<rmw_16>, inst16_64>; - def : BinRMWPatExternalSym<i64, zext_bin_rmw_32_64<rmw_32>, inst32_64>; - - def : BinRMWPatExternalSym<i32, sext_bin_rmw_8_32<rmw_8>, inst8_32>; - def : BinRMWPatExternalSym<i32, sext_bin_rmw_16_32<rmw_16>, inst16_32>; - def : BinRMWPatExternalSym<i64, sext_bin_rmw_8_64<rmw_8>, inst8_64>; - def : BinRMWPatExternalSym<i64, sext_bin_rmw_16_64<rmw_16>, inst16_64>; - // Truncating-extending binary RMWs with just a constant offset def : BinRMWPatOffsetOnly<i32, zext_bin_rmw_8_32<rmw_8>, inst8_32>; def : BinRMWPatOffsetOnly<i32, zext_bin_rmw_16_32<rmw_16>, inst16_32>; @@ -613,17 +655,6 @@ multiclass BinRMWTruncExtPattern< def : BinRMWPatGlobalAddrOffOnly<i32, sext_bin_rmw_16_32<rmw_16>, inst16_32>; def : BinRMWPatGlobalAddrOffOnly<i64, sext_bin_rmw_8_64<rmw_8>, inst8_64>; def : BinRMWPatGlobalAddrOffOnly<i64, sext_bin_rmw_16_64<rmw_16>, inst16_64>; - - def : BinRMWPatExternSymOffOnly<i32, zext_bin_rmw_8_32<rmw_8>, inst8_32>; - def : BinRMWPatExternSymOffOnly<i32, zext_bin_rmw_16_32<rmw_16>, inst16_32>; - def : BinRMWPatExternSymOffOnly<i64, zext_bin_rmw_8_64<rmw_8>, inst8_64>; - def : BinRMWPatExternSymOffOnly<i64, zext_bin_rmw_16_64<rmw_16>, inst16_64>; - def : BinRMWPatExternSymOffOnly<i64, zext_bin_rmw_32_64<rmw_32>, inst32_64>; - - def : BinRMWPatExternSymOffOnly<i32, sext_bin_rmw_8_32<rmw_8>, inst8_32>; - def : BinRMWPatExternSymOffOnly<i32, sext_bin_rmw_16_32<rmw_16>, inst16_32>; - def : BinRMWPatExternSymOffOnly<i64, sext_bin_rmw_8_64<rmw_8>, inst8_64>; - def : BinRMWPatExternSymOffOnly<i64, sext_bin_rmw_16_64<rmw_16>, inst16_64>; } let Predicates = [HasAtomics] in { @@ -663,29 +694,31 @@ defm : BinRMWTruncExtPattern< // Consider adding a pass after instruction selection that optimizes this case // if it is frequent. -multiclass WebAssemblyTerRMW<WebAssemblyRegClass rc, string Name, int Opcode> { - defm "" : I<(outs rc:$dst), - (ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$exp, - rc:$new), - (outs), (ins P2Align:$p2align, offset32_op:$off), [], - !strconcat(Name, "\t$dst, ${off}(${addr})${p2align}, $exp, $new"), - !strconcat(Name, "\t${off}, ${p2align}"), Opcode>; +multiclass WebAssemblyTerRMW<WebAssemblyRegClass rc, string name, + int atomic_op> { + defm "" : + ATOMIC_I<(outs rc:$dst), + (ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$exp, + rc:$new_), + (outs), (ins P2Align:$p2align, offset32_op:$off), [], + !strconcat(name, "\t$dst, ${off}(${addr})${p2align}, $exp, $new_"), + !strconcat(name, "\t${off}${p2align}"), atomic_op>; } defm ATOMIC_RMW_CMPXCHG_I32 : - WebAssemblyTerRMW<I32, "i32.atomic.rmw.cmpxchg", 0xfe48>; + WebAssemblyTerRMW<I32, "i32.atomic.rmw.cmpxchg", 0x48>; defm ATOMIC_RMW_CMPXCHG_I64 : - WebAssemblyTerRMW<I64, "i64.atomic.rmw.cmpxchg", 0xfe49>; + WebAssemblyTerRMW<I64, "i64.atomic.rmw.cmpxchg", 0x49>; defm ATOMIC_RMW8_U_CMPXCHG_I32 : - WebAssemblyTerRMW<I32, "i32.atomic.rmw8.cmpxchg_u", 0xfe4a>; + WebAssemblyTerRMW<I32, "i32.atomic.rmw8.cmpxchg_u", 0x4a>; defm ATOMIC_RMW16_U_CMPXCHG_I32 : - WebAssemblyTerRMW<I32, "i32.atomic.rmw16.cmpxchg_u", 0xfe4b>; + WebAssemblyTerRMW<I32, "i32.atomic.rmw16.cmpxchg_u", 0x4b>; defm ATOMIC_RMW8_U_CMPXCHG_I64 : - WebAssemblyTerRMW<I64, "i64.atomic.rmw8.cmpxchg_u", 0xfe4c>; + WebAssemblyTerRMW<I64, "i64.atomic.rmw8.cmpxchg_u", 0x4c>; defm ATOMIC_RMW16_U_CMPXCHG_I64 : - WebAssemblyTerRMW<I64, "i64.atomic.rmw16.cmpxchg_u", 0xfe4d>; + WebAssemblyTerRMW<I64, "i64.atomic.rmw16.cmpxchg_u", 0x4d>; defm ATOMIC_RMW32_U_CMPXCHG_I64 : - WebAssemblyTerRMW<I64, "i64.atomic.rmw32.cmpxchg_u", 0xfe4e>; + WebAssemblyTerRMW<I64, "i64.atomic.rmw32.cmpxchg_u", 0x4e>; // Select ternary RMWs with no constant offset. class TerRMWPatNoOffset<ValueType ty, PatFrag kind, NI inst> : @@ -704,11 +737,6 @@ class TerRMWPatGlobalAddr<ValueType ty, PatFrag kind, NI inst> : ty:$exp, ty:$new)), (inst 0, tglobaladdr:$off, I32:$addr, ty:$exp, ty:$new)>; -class TerRMWPatExternalSym<ValueType ty, PatFrag kind, NI inst> : - Pat<(ty (kind (add I32:$addr, (WebAssemblywrapper texternalsym:$off)), - ty:$exp, ty:$new)), - (inst 0, texternalsym:$off, I32:$addr, ty:$exp, ty:$new)>; - // Select ternary RMWs with just a constant offset. class TerRMWPatOffsetOnly<ValueType ty, PatFrag kind, NI inst> : Pat<(ty (kind imm:$off, ty:$exp, ty:$new)), @@ -718,10 +746,6 @@ class TerRMWPatGlobalAddrOffOnly<ValueType ty, PatFrag kind, NI inst> : Pat<(ty (kind (WebAssemblywrapper tglobaladdr:$off), ty:$exp, ty:$new)), (inst 0, tglobaladdr:$off, (CONST_I32 0), ty:$exp, ty:$new)>; -class TerRMWPatExternSymOffOnly<ValueType ty, PatFrag kind, NI inst> : - Pat<(ty (kind (WebAssemblywrapper texternalsym:$off), ty:$exp, ty:$new)), - (inst 0, texternalsym:$off, (CONST_I32 0), ty:$exp, ty:$new)>; - // Patterns for various addressing modes. multiclass TerRMWPattern<PatFrag rmw_32, PatFrag rmw_64, NI inst_32, NI inst_64> { @@ -736,23 +760,16 @@ multiclass TerRMWPattern<PatFrag rmw_32, PatFrag rmw_64, NI inst_32, def : TerRMWPatGlobalAddr<i32, rmw_32, inst_32>; def : TerRMWPatGlobalAddr<i64, rmw_64, inst_64>; - def : TerRMWPatExternalSym<i32, rmw_32, inst_32>; - def : TerRMWPatExternalSym<i64, rmw_64, inst_64>; - def : TerRMWPatOffsetOnly<i32, rmw_32, inst_32>; def : TerRMWPatOffsetOnly<i64, rmw_64, inst_64>; def : TerRMWPatGlobalAddrOffOnly<i32, rmw_32, inst_32>; def : TerRMWPatGlobalAddrOffOnly<i64, rmw_64, inst_64>; - - def : TerRMWPatExternSymOffOnly<i32, rmw_32, inst_32>; - def : TerRMWPatExternSymOffOnly<i64, rmw_64, inst_64>; } -let Predicates = [HasAtomics] in { +let Predicates = [HasAtomics] in defm : TerRMWPattern<atomic_cmp_swap_32, atomic_cmp_swap_64, ATOMIC_RMW_CMPXCHG_I32, ATOMIC_RMW_CMPXCHG_I64>; -} // Predicates = [HasAtomics] // Truncating & zero-extending ternary RMW patterns. // DAG legalization & optimization before instruction selection may introduce @@ -840,17 +857,6 @@ multiclass TerRMWTruncExtPattern< def : TerRMWPatGlobalAddr<i64, sext_ter_rmw_8_64<rmw_8>, inst8_64>; def : TerRMWPatGlobalAddr<i64, sext_ter_rmw_16_64<rmw_16>, inst16_64>; - def : TerRMWPatExternalSym<i32, zext_ter_rmw_8_32<rmw_8>, inst8_32>; - def : TerRMWPatExternalSym<i32, zext_ter_rmw_16_32<rmw_16>, inst16_32>; - def : TerRMWPatExternalSym<i64, zext_ter_rmw_8_64<rmw_8>, inst8_64>; - def : TerRMWPatExternalSym<i64, zext_ter_rmw_16_64<rmw_16>, inst16_64>; - def : TerRMWPatExternalSym<i64, zext_ter_rmw_32_64<rmw_32>, inst32_64>; - - def : TerRMWPatExternalSym<i32, sext_ter_rmw_8_32<rmw_8>, inst8_32>; - def : TerRMWPatExternalSym<i32, sext_ter_rmw_16_32<rmw_16>, inst16_32>; - def : TerRMWPatExternalSym<i64, sext_ter_rmw_8_64<rmw_8>, inst8_64>; - def : TerRMWPatExternalSym<i64, sext_ter_rmw_16_64<rmw_16>, inst16_64>; - // Truncating-extending ternary RMWs with just a constant offset def : TerRMWPatOffsetOnly<i32, zext_ter_rmw_8_32<rmw_8>, inst8_32>; def : TerRMWPatOffsetOnly<i32, zext_ter_rmw_16_32<rmw_16>, inst16_32>; @@ -873,147 +879,21 @@ multiclass TerRMWTruncExtPattern< def : TerRMWPatGlobalAddrOffOnly<i32, sext_ter_rmw_16_32<rmw_16>, inst16_32>; def : TerRMWPatGlobalAddrOffOnly<i64, sext_ter_rmw_8_64<rmw_8>, inst8_64>; def : TerRMWPatGlobalAddrOffOnly<i64, sext_ter_rmw_16_64<rmw_16>, inst16_64>; - - def : TerRMWPatExternSymOffOnly<i32, zext_ter_rmw_8_32<rmw_8>, inst8_32>; - def : TerRMWPatExternSymOffOnly<i32, zext_ter_rmw_16_32<rmw_16>, inst16_32>; - def : TerRMWPatExternSymOffOnly<i64, zext_ter_rmw_8_64<rmw_8>, inst8_64>; - def : TerRMWPatExternSymOffOnly<i64, zext_ter_rmw_16_64<rmw_16>, inst16_64>; - def : TerRMWPatExternSymOffOnly<i64, zext_ter_rmw_32_64<rmw_32>, inst32_64>; - - def : TerRMWPatExternSymOffOnly<i32, sext_ter_rmw_8_32<rmw_8>, inst8_32>; - def : TerRMWPatExternSymOffOnly<i32, sext_ter_rmw_16_32<rmw_16>, inst16_32>; - def : TerRMWPatExternSymOffOnly<i64, sext_ter_rmw_8_64<rmw_8>, inst8_64>; - def : TerRMWPatExternSymOffOnly<i64, sext_ter_rmw_16_64<rmw_16>, inst16_64>; } -let Predicates = [HasAtomics] in { +let Predicates = [HasAtomics] in defm : TerRMWTruncExtPattern< atomic_cmp_swap_8, atomic_cmp_swap_16, atomic_cmp_swap_32, atomic_cmp_swap_64, ATOMIC_RMW8_U_CMPXCHG_I32, ATOMIC_RMW16_U_CMPXCHG_I32, ATOMIC_RMW8_U_CMPXCHG_I64, ATOMIC_RMW16_U_CMPXCHG_I64, ATOMIC_RMW32_U_CMPXCHG_I64>; -} //===----------------------------------------------------------------------===// -// Atomic wait / notify +// Atomic fences //===----------------------------------------------------------------------===// -let hasSideEffects = 1 in { -defm ATOMIC_NOTIFY : - I<(outs I32:$dst), - (ins P2Align:$p2align, offset32_op:$off, I32:$addr, I32:$count), - (outs), (ins P2Align:$p2align, offset32_op:$off), [], - "atomic.notify \t$dst, ${off}(${addr})${p2align}, $count", - "atomic.notify \t${off}, ${p2align}", 0xfe00>; -let mayLoad = 1 in { -defm ATOMIC_WAIT_I32 : - I<(outs I32:$dst), - (ins P2Align:$p2align, offset32_op:$off, I32:$addr, I32:$exp, I64:$timeout), - (outs), (ins P2Align:$p2align, offset32_op:$off), [], - "i32.atomic.wait \t$dst, ${off}(${addr})${p2align}, $exp, $timeout", - "i32.atomic.wait \t${off}, ${p2align}", 0xfe01>; -defm ATOMIC_WAIT_I64 : - I<(outs I32:$dst), - (ins P2Align:$p2align, offset32_op:$off, I32:$addr, I64:$exp, I64:$timeout), - (outs), (ins P2Align:$p2align, offset32_op:$off), [], - "i64.atomic.wait \t$dst, ${off}(${addr})${p2align}, $exp, $timeout", - "i64.atomic.wait \t${off}, ${p2align}", 0xfe02>; -} // mayLoad = 1 -} // hasSideEffects = 1 - -let Predicates = [HasAtomics] in { -// Select notifys with no constant offset. -class NotifyPatNoOffset<Intrinsic kind> : - Pat<(i32 (kind I32:$addr, I32:$count)), - (ATOMIC_NOTIFY 0, 0, I32:$addr, I32:$count)>; -def : NotifyPatNoOffset<int_wasm_atomic_notify>; - -// Select notifys with a constant offset. - -// Pattern with address + immediate offset -class NotifyPatImmOff<Intrinsic kind, PatFrag operand> : - Pat<(i32 (kind (operand I32:$addr, imm:$off), I32:$count)), - (ATOMIC_NOTIFY 0, imm:$off, I32:$addr, I32:$count)>; -def : NotifyPatImmOff<int_wasm_atomic_notify, regPlusImm>; -def : NotifyPatImmOff<int_wasm_atomic_notify, or_is_add>; - -class NotifyPatGlobalAddr<Intrinsic kind> : - Pat<(i32 (kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)), - I32:$count)), - (ATOMIC_NOTIFY 0, tglobaladdr:$off, I32:$addr, I32:$count)>; -def : NotifyPatGlobalAddr<int_wasm_atomic_notify>; - -class NotifyPatExternalSym<Intrinsic kind> : - Pat<(i32 (kind (add I32:$addr, (WebAssemblywrapper texternalsym:$off)), - I32:$count)), - (ATOMIC_NOTIFY 0, texternalsym:$off, I32:$addr, I32:$count)>; -def : NotifyPatExternalSym<int_wasm_atomic_notify>; - -// Select notifys with just a constant offset. -class NotifyPatOffsetOnly<Intrinsic kind> : - Pat<(i32 (kind imm:$off, I32:$count)), - (ATOMIC_NOTIFY 0, imm:$off, (CONST_I32 0), I32:$count)>; -def : NotifyPatOffsetOnly<int_wasm_atomic_notify>; - -class NotifyPatGlobalAddrOffOnly<Intrinsic kind> : - Pat<(i32 (kind (WebAssemblywrapper tglobaladdr:$off), I32:$count)), - (ATOMIC_NOTIFY 0, tglobaladdr:$off, (CONST_I32 0), I32:$count)>; -def : NotifyPatGlobalAddrOffOnly<int_wasm_atomic_notify>; - -class NotifyPatExternSymOffOnly<Intrinsic kind> : - Pat<(i32 (kind (WebAssemblywrapper texternalsym:$off), I32:$count)), - (ATOMIC_NOTIFY 0, texternalsym:$off, (CONST_I32 0), I32:$count)>; -def : NotifyPatExternSymOffOnly<int_wasm_atomic_notify>; - -// Select waits with no constant offset. -class WaitPatNoOffset<ValueType ty, Intrinsic kind, NI inst> : - Pat<(i32 (kind I32:$addr, ty:$exp, I64:$timeout)), - (inst 0, 0, I32:$addr, ty:$exp, I64:$timeout)>; -def : WaitPatNoOffset<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>; -def : WaitPatNoOffset<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>; - -// Select waits with a constant offset. - -// Pattern with address + immediate offset -class WaitPatImmOff<ValueType ty, Intrinsic kind, PatFrag operand, NI inst> : - Pat<(i32 (kind (operand I32:$addr, imm:$off), ty:$exp, I64:$timeout)), - (inst 0, imm:$off, I32:$addr, ty:$exp, I64:$timeout)>; -def : WaitPatImmOff<i32, int_wasm_atomic_wait_i32, regPlusImm, ATOMIC_WAIT_I32>; -def : WaitPatImmOff<i32, int_wasm_atomic_wait_i32, or_is_add, ATOMIC_WAIT_I32>; -def : WaitPatImmOff<i64, int_wasm_atomic_wait_i64, regPlusImm, ATOMIC_WAIT_I64>; -def : WaitPatImmOff<i64, int_wasm_atomic_wait_i64, or_is_add, ATOMIC_WAIT_I64>; - -class WaitPatGlobalAddr<ValueType ty, Intrinsic kind, NI inst> : - Pat<(i32 (kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)), - ty:$exp, I64:$timeout)), - (inst 0, tglobaladdr:$off, I32:$addr, ty:$exp, I64:$timeout)>; -def : WaitPatGlobalAddr<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>; -def : WaitPatGlobalAddr<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>; - -class WaitPatExternalSym<ValueType ty, Intrinsic kind, NI inst> : - Pat<(i32 (kind (add I32:$addr, (WebAssemblywrapper texternalsym:$off)), - ty:$exp, I64:$timeout)), - (inst 0, texternalsym:$off, I32:$addr, ty:$exp, I64:$timeout)>; -def : WaitPatExternalSym<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>; -def : WaitPatExternalSym<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>; - -// Select wait_i32, ATOMIC_WAIT_I32s with just a constant offset. -class WaitPatOffsetOnly<ValueType ty, Intrinsic kind, NI inst> : - Pat<(i32 (kind imm:$off, ty:$exp, I64:$timeout)), - (inst 0, imm:$off, (CONST_I32 0), ty:$exp, I64:$timeout)>; -def : WaitPatOffsetOnly<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>; -def : WaitPatOffsetOnly<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>; - -class WaitPatGlobalAddrOffOnly<ValueType ty, Intrinsic kind, NI inst> : - Pat<(i32 (kind (WebAssemblywrapper tglobaladdr:$off), ty:$exp, I64:$timeout)), - (inst 0, tglobaladdr:$off, (CONST_I32 0), ty:$exp, I64:$timeout)>; -def : WaitPatGlobalAddrOffOnly<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>; -def : WaitPatGlobalAddrOffOnly<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>; - -class WaitPatExternSymOffOnly<ValueType ty, Intrinsic kind, NI inst> : - Pat<(i32 (kind (WebAssemblywrapper texternalsym:$off), ty:$exp, - I64:$timeout)), - (inst 0, texternalsym:$off, (CONST_I32 0), ty:$exp, I64:$timeout)>; -def : WaitPatExternSymOffOnly<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>; -def : WaitPatExternSymOffOnly<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>; -} // Predicates = [HasAtomics] +// A compiler fence instruction that prevents reordering of instructions. +let Defs = [ARGUMENTS] in { +let isPseudo = 1, hasSideEffects = 1 in +defm COMPILER_FENCE : ATOMIC_NRI<(outs), (ins), [], "compiler_fence">; +} // Defs = [ARGUMENTS] |