diff options
Diffstat (limited to 'lib/Target/WebAssembly/WebAssemblyInstrInfo.td')
| -rw-r--r-- | lib/Target/WebAssembly/WebAssemblyInstrInfo.td | 129 |
1 files changed, 84 insertions, 45 deletions
diff --git a/lib/Target/WebAssembly/WebAssemblyInstrInfo.td b/lib/Target/WebAssembly/WebAssemblyInstrInfo.td index e3d795f2aab1..73ddbe85d551 100644 --- a/lib/Target/WebAssembly/WebAssemblyInstrInfo.td +++ b/lib/Target/WebAssembly/WebAssemblyInstrInfo.td @@ -1,9 +1,8 @@ // WebAssemblyInstrInfo.td-Describe the WebAssembly Instructions-*- tablegen -*- // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// /// @@ -16,41 +15,52 @@ // WebAssembly Instruction Predicate Definitions. //===----------------------------------------------------------------------===// +def IsPIC : Predicate<"TM.isPositionIndependent()">; +def IsNotPIC : Predicate<"!TM.isPositionIndependent()">; + def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">; + def HasAddr64 : Predicate<"Subtarget->hasAddr64()">; -def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">, - AssemblerPredicate<"FeatureSIMD128", "simd128">; + +def HasSIMD128 : + Predicate<"Subtarget->hasSIMD128()">, + AssemblerPredicate<"FeatureSIMD128", "simd128">; + def HasUnimplementedSIMD128 : Predicate<"Subtarget->hasUnimplementedSIMD128()">, AssemblerPredicate<"FeatureUnimplementedSIMD128", "unimplemented-simd128">; -def HasAtomics : Predicate<"Subtarget->hasAtomics()">, - AssemblerPredicate<"FeatureAtomics", "atomics">; + +def HasAtomics : + Predicate<"Subtarget->hasAtomics()">, + AssemblerPredicate<"FeatureAtomics", "atomics">; + +def HasMultivalue : + Predicate<"Subtarget->hasMultivalue()">, + AssemblerPredicate<"FeatureMultivalue", "multivalue">; + def HasNontrappingFPToInt : Predicate<"Subtarget->hasNontrappingFPToInt()">, - AssemblerPredicate<"FeatureNontrappingFPToInt", - "nontrapping-fptoint">; + AssemblerPredicate<"FeatureNontrappingFPToInt", "nontrapping-fptoint">; + def NotHasNontrappingFPToInt : Predicate<"!Subtarget->hasNontrappingFPToInt()">, - AssemblerPredicate<"!FeatureNontrappingFPToInt", - "nontrapping-fptoint">; + AssemblerPredicate<"!FeatureNontrappingFPToInt", "nontrapping-fptoint">; + def HasSignExt : Predicate<"Subtarget->hasSignExt()">, - AssemblerPredicate<"FeatureSignExt", - "sign-ext">; -def NotHasSignExt : - Predicate<"!Subtarget->hasSignExt()">, - AssemblerPredicate<"!FeatureSignExt", - "sign-ext">; + AssemblerPredicate<"FeatureSignExt", "sign-ext">; + +def HasTailCall : + Predicate<"Subtarget->hasTailCall()">, + AssemblerPredicate<"FeatureTailCall", "tail-call">; def HasExceptionHandling : Predicate<"Subtarget->hasExceptionHandling()">, - AssemblerPredicate<"FeatureExceptionHandling", - "exception-handling">; + AssemblerPredicate<"FeatureExceptionHandling", "exception-handling">; -def NotHasExceptionHandling : - Predicate<"!Subtarget->hasExceptionHandling()">, - AssemblerPredicate<"!FeatureExceptionHandling", - "exception-handling">; +def HasBulkMemory : + Predicate<"Subtarget->hasBulkMemory()">, + AssemblerPredicate<"FeatureBulkMemory", "bulk-memory">; //===----------------------------------------------------------------------===// // WebAssembly-specific DAG Node Types. @@ -60,14 +70,16 @@ def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; def SDT_WebAssemblyCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; -def SDT_WebAssemblyCall0 : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; -def SDT_WebAssemblyCall1 : SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>; -def SDT_WebAssemblyBrTable : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; -def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>; -def SDT_WebAssemblyReturn : SDTypeProfile<0, -1, []>; -def SDT_WebAssemblyWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, - SDTCisPtrTy<0>]>; -def SDT_WebAssemblyThrow : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>; +def SDT_WebAssemblyCall0 : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; +def SDT_WebAssemblyCall1 : SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>; +def SDT_WebAssemblyBrTable : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; +def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>; +def SDT_WebAssemblyReturn : SDTypeProfile<0, -1, []>; +def SDT_WebAssemblyWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, + SDTCisPtrTy<0>]>; +def SDT_WebAssemblyWrapperPIC : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, + SDTCisPtrTy<0>]>; +def SDT_WebAssemblyThrow : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; //===----------------------------------------------------------------------===// // WebAssembly-specific DAG Nodes. @@ -85,6 +97,9 @@ def WebAssemblycall0 : SDNode<"WebAssemblyISD::CALL0", def WebAssemblycall1 : SDNode<"WebAssemblyISD::CALL1", SDT_WebAssemblyCall1, [SDNPHasChain, SDNPVariadic]>; +def WebAssemblyretcall : SDNode<"WebAssemblyISD::RET_CALL", + SDT_WebAssemblyCall0, + [SDNPHasChain, SDNPVariadic]>; def WebAssemblybr_table : SDNode<"WebAssemblyISD::BR_TABLE", SDT_WebAssemblyBrTable, [SDNPHasChain, SDNPVariadic]>; @@ -94,13 +109,26 @@ def WebAssemblyreturn : SDNode<"WebAssemblyISD::RETURN", SDT_WebAssemblyReturn, [SDNPHasChain]>; def WebAssemblywrapper : SDNode<"WebAssemblyISD::Wrapper", SDT_WebAssemblyWrapper>; +def WebAssemblywrapperPIC : SDNode<"WebAssemblyISD::WrapperPIC", + SDT_WebAssemblyWrapperPIC>; def WebAssemblythrow : SDNode<"WebAssemblyISD::THROW", SDT_WebAssemblyThrow, - [SDNPHasChain]>; + [SDNPHasChain, SDNPVariadic]>; //===----------------------------------------------------------------------===// // WebAssembly-specific Operands. //===----------------------------------------------------------------------===// +// Default Operand has AsmOperandClass "Imm" which is for integers (and +// symbols), so specialize one for floats: +def FPImmAsmOperand : AsmOperandClass { + let Name = "FPImm"; + let PredicateMethod = "isFPImm"; +} + +class FPOperand<ValueType ty> : Operand<ty> { + AsmOperandClass ParserMatchClass = FPImmAsmOperand; +} + let OperandNamespace = "WebAssembly" in { let OperandType = "OPERAND_BASIC_BLOCK" in @@ -119,10 +147,10 @@ let OperandType = "OPERAND_I64IMM" in def i64imm_op : Operand<i64>; let OperandType = "OPERAND_F32IMM" in -def f32imm_op : Operand<f32>; +def f32imm_op : FPOperand<f32>; let OperandType = "OPERAND_F64IMM" in -def f64imm_op : Operand<f64>; +def f64imm_op : FPOperand<f64>; let OperandType = "OPERAND_VEC_I8IMM" in def vec_i8imm_op : Operand<i32>; @@ -152,11 +180,10 @@ def event_op : Operand<i32>; } // OperandType = "OPERAND_P2ALIGN" -let OperandType = "OPERAND_SIGNATURE" in { +let OperandType = "OPERAND_SIGNATURE" in def Signature : Operand<i32> { let PrintMethod = "printWebAssemblySignatureOperand"; } -} // OperandType = "OPERAND_SIGNATURE" let OperandType = "OPERAND_TYPEINDEX" in def TypeIndex : Operand<i32>; @@ -187,8 +214,8 @@ include "WebAssemblyInstrFormats.td" //===----------------------------------------------------------------------===// multiclass ARGUMENT<WebAssemblyRegClass reg, ValueType vt> { - let hasSideEffects = 1, isCodeGenOnly = 1, - Defs = []<Register>, Uses = [ARGUMENTS] in + let hasSideEffects = 1, isCodeGenOnly = 1, Defs = []<Register>, + Uses = [ARGUMENTS] in defm ARGUMENT_#vt : I<(outs reg:$res), (ins i32imm:$argno), (outs), (ins i32imm:$argno), [(set (vt reg:$res), (WebAssemblyargument timm:$argno))]>; @@ -197,12 +224,12 @@ defm "": ARGUMENT<I32, i32>; defm "": ARGUMENT<I64, i64>; defm "": ARGUMENT<F32, f32>; defm "": ARGUMENT<F64, f64>; -defm "": ARGUMENT<EXCEPT_REF, ExceptRef>; +defm "": ARGUMENT<EXNREF, exnref>; // local.get and local.set are not generated by instruction selection; they // are implied by virtual register uses and defs. multiclass LOCAL<WebAssemblyRegClass vt> { -let hasSideEffects = 0 in { + let hasSideEffects = 0 in { // COPY is not an actual instruction in wasm, but since we allow local.get and // local.set to be implicit during most of codegen, we can have a COPY which // is actually a no-op because all the work is done in the implied local.get @@ -267,7 +294,7 @@ defm "" : LOCAL<I64>; defm "" : LOCAL<F32>; defm "" : LOCAL<F64>; defm "" : LOCAL<V128>, Requires<[HasSIMD128]>; -defm "" : LOCAL<EXCEPT_REF>, Requires<[HasExceptionHandling]>; +defm "" : LOCAL<EXNREF>, Requires<[HasExceptionHandling]>; let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in { defm CONST_I32 : I<(outs I32:$res), (ins i32imm_op:$imm), @@ -289,9 +316,20 @@ defm CONST_F64 : I<(outs F64:$res), (ins f64imm_op:$imm), } // isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$addr)), - (CONST_I32 tglobaladdr:$addr)>; + (CONST_I32 tglobaladdr:$addr)>, Requires<[IsNotPIC]>; + +def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$addr)), + (GLOBAL_GET_I32 tglobaladdr:$addr)>, Requires<[IsPIC]>; + +def : Pat<(i32 (WebAssemblywrapperPIC tglobaladdr:$addr)), + (CONST_I32 tglobaladdr:$addr)>, Requires<[IsPIC]>; + def : Pat<(i32 (WebAssemblywrapper texternalsym:$addr)), - (CONST_I32 texternalsym:$addr)>; + (GLOBAL_GET_I32 texternalsym:$addr)>, Requires<[IsPIC]>; + +def : Pat<(i32 (WebAssemblywrapper texternalsym:$addr)), + (CONST_I32 texternalsym:$addr)>, Requires<[IsNotPIC]>; + def : Pat<(i32 (WebAssemblywrapper mcsym:$sym)), (CONST_I32 mcsym:$sym)>; def : Pat<(i64 (WebAssemblywrapper mcsym:$sym)), (CONST_I64 mcsym:$sym)>; @@ -307,4 +345,5 @@ include "WebAssemblyInstrConv.td" include "WebAssemblyInstrFloat.td" include "WebAssemblyInstrAtomics.td" include "WebAssemblyInstrSIMD.td" -include "WebAssemblyInstrExceptRef.td" +include "WebAssemblyInstrRef.td" +include "WebAssemblyInstrBulkMemory.td" |